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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.57 98.12 95.94 97.44 94.92 98.34 98.17 93.03


Total test records in report: 3740
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T3569 /workspace/coverage/default/29.usbdev_rx_full.4149466620 Aug 11 07:13:46 PM PDT 24 Aug 11 07:13:47 PM PDT 24 359582367 ps
T3570 /workspace/coverage/default/41.usbdev_setup_stage.2063597047 Aug 11 07:15:22 PM PDT 24 Aug 11 07:15:23 PM PDT 24 151119058 ps
T3571 /workspace/coverage/default/45.usbdev_link_suspend.2073576261 Aug 11 07:16:01 PM PDT 24 Aug 11 07:16:15 PM PDT 24 10872779569 ps
T3572 /workspace/coverage/default/44.usbdev_setup_stage.2700513921 Aug 11 07:15:48 PM PDT 24 Aug 11 07:15:49 PM PDT 24 158271422 ps
T3573 /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3946456000 Aug 11 07:09:58 PM PDT 24 Aug 11 07:11:41 PM PDT 24 7438038786 ps
T3574 /workspace/coverage/default/33.usbdev_data_toggle_clear.2957912488 Aug 11 07:14:09 PM PDT 24 Aug 11 07:14:10 PM PDT 24 319361761 ps
T3575 /workspace/coverage/default/492.usbdev_tx_rx_disruption.3437511020 Aug 11 07:18:13 PM PDT 24 Aug 11 07:18:15 PM PDT 24 571691251 ps
T3576 /workspace/coverage/default/29.usbdev_av_buffer.1511705923 Aug 11 07:13:36 PM PDT 24 Aug 11 07:13:37 PM PDT 24 209960916 ps
T3577 /workspace/coverage/default/18.usbdev_data_toggle_clear.3865477800 Aug 11 07:11:55 PM PDT 24 Aug 11 07:11:57 PM PDT 24 565935681 ps
T3578 /workspace/coverage/default/24.usbdev_setup_trans_ignored.4249894736 Aug 11 07:13:04 PM PDT 24 Aug 11 07:13:05 PM PDT 24 207874321 ps
T3579 /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.211049665 Aug 11 07:13:01 PM PDT 24 Aug 11 07:13:07 PM PDT 24 827173160 ps
T3580 /workspace/coverage/default/454.usbdev_tx_rx_disruption.2007380803 Aug 11 07:18:22 PM PDT 24 Aug 11 07:18:24 PM PDT 24 596735639 ps
T3581 /workspace/coverage/default/476.usbdev_tx_rx_disruption.3334197761 Aug 11 07:18:12 PM PDT 24 Aug 11 07:18:14 PM PDT 24 633706335 ps
T3582 /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.165025212 Aug 11 07:12:16 PM PDT 24 Aug 11 07:12:17 PM PDT 24 148185562 ps
T3583 /workspace/coverage/default/12.usbdev_stream_len_max.2551143245 Aug 11 07:11:07 PM PDT 24 Aug 11 07:11:09 PM PDT 24 1084828299 ps
T3584 /workspace/coverage/default/67.usbdev_tx_rx_disruption.2979732262 Aug 11 07:16:42 PM PDT 24 Aug 11 07:16:44 PM PDT 24 474953983 ps
T3585 /workspace/coverage/default/18.usbdev_in_trans.3007803924 Aug 11 07:12:02 PM PDT 24 Aug 11 07:12:03 PM PDT 24 262677357 ps
T3586 /workspace/coverage/default/455.usbdev_tx_rx_disruption.973126269 Aug 11 07:18:24 PM PDT 24 Aug 11 07:18:26 PM PDT 24 458677769 ps
T3587 /workspace/coverage/default/30.usbdev_out_iso.1505089925 Aug 11 07:13:51 PM PDT 24 Aug 11 07:13:52 PM PDT 24 181836307 ps
T3588 /workspace/coverage/default/51.usbdev_tx_rx_disruption.824198243 Aug 11 07:16:37 PM PDT 24 Aug 11 07:16:38 PM PDT 24 474908951 ps
T3589 /workspace/coverage/default/1.usbdev_alert_test.1953994051 Aug 11 07:08:48 PM PDT 24 Aug 11 07:08:49 PM PDT 24 32015503 ps
T3590 /workspace/coverage/default/336.usbdev_tx_rx_disruption.2809086280 Aug 11 07:17:46 PM PDT 24 Aug 11 07:17:48 PM PDT 24 539511046 ps
T3591 /workspace/coverage/default/121.usbdev_tx_rx_disruption.3179612799 Aug 11 07:17:04 PM PDT 24 Aug 11 07:17:06 PM PDT 24 547112011 ps
T3592 /workspace/coverage/default/7.usbdev_endpoint_access.1273415413 Aug 11 07:09:55 PM PDT 24 Aug 11 07:09:57 PM PDT 24 921696883 ps
T3593 /workspace/coverage/default/32.usbdev_device_timeout.873417298 Aug 11 07:13:59 PM PDT 24 Aug 11 07:14:32 PM PDT 24 4970242478 ps
T3594 /workspace/coverage/default/25.usbdev_min_length_in_transaction.123372769 Aug 11 07:13:10 PM PDT 24 Aug 11 07:13:11 PM PDT 24 205816420 ps
T3595 /workspace/coverage/default/33.usbdev_in_iso.962629869 Aug 11 07:14:28 PM PDT 24 Aug 11 07:14:29 PM PDT 24 293564101 ps
T3596 /workspace/coverage/default/2.usbdev_resume_link_active.2346381496 Aug 11 07:08:59 PM PDT 24 Aug 11 07:09:23 PM PDT 24 20156821881 ps
T3597 /workspace/coverage/default/248.usbdev_tx_rx_disruption.1871662071 Aug 11 07:17:31 PM PDT 24 Aug 11 07:17:33 PM PDT 24 469483662 ps
T3598 /workspace/coverage/default/24.usbdev_phy_pins_sense.2100865133 Aug 11 07:13:03 PM PDT 24 Aug 11 07:13:04 PM PDT 24 48892326 ps
T3599 /workspace/coverage/default/4.usbdev_in_stall.2082989471 Aug 11 07:09:18 PM PDT 24 Aug 11 07:09:19 PM PDT 24 157963677 ps
T3600 /workspace/coverage/default/41.usbdev_in_trans.3539976631 Aug 11 07:15:26 PM PDT 24 Aug 11 07:15:27 PM PDT 24 206293869 ps
T3601 /workspace/coverage/default/41.usbdev_max_length_in_transaction.4182405474 Aug 11 07:15:30 PM PDT 24 Aug 11 07:15:31 PM PDT 24 269318454 ps
T3602 /workspace/coverage/default/41.usbdev_bitstuff_err.4198420556 Aug 11 07:15:21 PM PDT 24 Aug 11 07:15:22 PM PDT 24 144058875 ps
T3603 /workspace/coverage/default/1.usbdev_rx_full.3542190375 Aug 11 07:08:47 PM PDT 24 Aug 11 07:08:49 PM PDT 24 334490968 ps
T3604 /workspace/coverage/default/401.usbdev_tx_rx_disruption.846322703 Aug 11 07:17:48 PM PDT 24 Aug 11 07:17:55 PM PDT 24 527268689 ps
T3605 /workspace/coverage/default/16.usbdev_setup_stage.1536808417 Aug 11 07:11:41 PM PDT 24 Aug 11 07:11:41 PM PDT 24 184047856 ps
T3606 /workspace/coverage/default/29.usbdev_alert_test.1723957037 Aug 11 07:13:56 PM PDT 24 Aug 11 07:13:56 PM PDT 24 63015943 ps
T3607 /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3150112780 Aug 11 07:14:07 PM PDT 24 Aug 11 07:14:16 PM PDT 24 5955890011 ps
T3608 /workspace/coverage/default/254.usbdev_tx_rx_disruption.2503874513 Aug 11 07:17:39 PM PDT 24 Aug 11 07:17:41 PM PDT 24 518111155 ps
T3609 /workspace/coverage/default/7.usbdev_in_trans.2721367945 Aug 11 07:09:54 PM PDT 24 Aug 11 07:09:55 PM PDT 24 258614510 ps
T3610 /workspace/coverage/default/24.usbdev_data_toggle_restore.319473185 Aug 11 07:13:01 PM PDT 24 Aug 11 07:13:03 PM PDT 24 398666166 ps
T3611 /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2777080117 Aug 11 07:13:54 PM PDT 24 Aug 11 07:15:22 PM PDT 24 3043410709 ps
T3612 /workspace/coverage/default/4.usbdev_rand_bus_resets.3348811098 Aug 11 07:09:28 PM PDT 24 Aug 11 07:11:07 PM PDT 24 3700907463 ps
T3613 /workspace/coverage/default/12.usbdev_random_length_in_transaction.2908021135 Aug 11 07:11:08 PM PDT 24 Aug 11 07:11:09 PM PDT 24 201408931 ps
T3614 /workspace/coverage/default/38.usbdev_min_length_out_transaction.1622836538 Aug 11 07:14:56 PM PDT 24 Aug 11 07:14:57 PM PDT 24 152516041 ps
T3615 /workspace/coverage/default/27.usbdev_data_toggle_clear.798439843 Aug 11 07:13:19 PM PDT 24 Aug 11 07:13:21 PM PDT 24 349638203 ps
T3616 /workspace/coverage/default/26.usbdev_tx_rx_disruption.49241081 Aug 11 07:13:18 PM PDT 24 Aug 11 07:13:20 PM PDT 24 534700000 ps
T3617 /workspace/coverage/default/14.usbdev_av_buffer.2071542282 Aug 11 07:11:16 PM PDT 24 Aug 11 07:11:17 PM PDT 24 153459387 ps
T3618 /workspace/coverage/default/23.usbdev_aon_wake_reset.2807176718 Aug 11 07:12:48 PM PDT 24 Aug 11 07:13:03 PM PDT 24 14157214624 ps
T3619 /workspace/coverage/default/47.usbdev_setup_trans_ignored.1126537244 Aug 11 07:16:24 PM PDT 24 Aug 11 07:16:25 PM PDT 24 161707072 ps
T3620 /workspace/coverage/default/40.usbdev_data_toggle_clear.1631711741 Aug 11 07:15:18 PM PDT 24 Aug 11 07:15:20 PM PDT 24 403644474 ps
T3621 /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3560725439 Aug 11 07:10:59 PM PDT 24 Aug 11 07:11:14 PM PDT 24 1888502539 ps
T3622 /workspace/coverage/default/30.usbdev_rx_crc_err.3110662182 Aug 11 07:13:48 PM PDT 24 Aug 11 07:13:49 PM PDT 24 205490844 ps
T3623 /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3167109592 Aug 11 07:16:35 PM PDT 24 Aug 11 07:17:28 PM PDT 24 1868347055 ps
T3624 /workspace/coverage/default/18.usbdev_pkt_sent.448267713 Aug 11 07:12:04 PM PDT 24 Aug 11 07:12:05 PM PDT 24 191456468 ps
T3625 /workspace/coverage/default/173.usbdev_endpoint_types.2796635925 Aug 11 07:17:19 PM PDT 24 Aug 11 07:17:21 PM PDT 24 887037959 ps
T3626 /workspace/coverage/default/10.usbdev_av_buffer.1482071055 Aug 11 07:10:31 PM PDT 24 Aug 11 07:10:32 PM PDT 24 150347824 ps
T3627 /workspace/coverage/default/154.usbdev_tx_rx_disruption.3391774726 Aug 11 07:17:06 PM PDT 24 Aug 11 07:17:08 PM PDT 24 554253554 ps
T3628 /workspace/coverage/default/169.usbdev_tx_rx_disruption.1841500462 Aug 11 07:17:16 PM PDT 24 Aug 11 07:17:18 PM PDT 24 684099600 ps
T3629 /workspace/coverage/default/434.usbdev_tx_rx_disruption.2662378172 Aug 11 07:18:06 PM PDT 24 Aug 11 07:18:08 PM PDT 24 557321473 ps
T3630 /workspace/coverage/default/22.usbdev_data_toggle_restore.1175725997 Aug 11 07:12:35 PM PDT 24 Aug 11 07:12:37 PM PDT 24 777755894 ps
T3631 /workspace/coverage/default/38.usbdev_rx_crc_err.1889880332 Aug 11 07:14:56 PM PDT 24 Aug 11 07:14:57 PM PDT 24 143899929 ps
T3632 /workspace/coverage/default/40.usbdev_setup_trans_ignored.137525722 Aug 11 07:15:22 PM PDT 24 Aug 11 07:15:23 PM PDT 24 147001701 ps
T3633 /workspace/coverage/default/42.usbdev_in_iso.3569782329 Aug 11 07:15:22 PM PDT 24 Aug 11 07:15:24 PM PDT 24 247030822 ps
T263 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2956164166 Aug 11 06:21:29 PM PDT 24 Aug 11 06:21:30 PM PDT 24 32509748 ps
T264 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3890289423 Aug 11 06:21:22 PM PDT 24 Aug 11 06:21:24 PM PDT 24 50599859 ps
T265 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3324973587 Aug 11 06:21:22 PM PDT 24 Aug 11 06:21:24 PM PDT 24 103377814 ps
T312 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2378437944 Aug 11 06:21:08 PM PDT 24 Aug 11 06:21:09 PM PDT 24 114934923 ps
T313 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2563653834 Aug 11 06:21:28 PM PDT 24 Aug 11 06:21:30 PM PDT 24 134986017 ps
T231 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.368293732 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 34697915 ps
T234 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2323029921 Aug 11 06:21:38 PM PDT 24 Aug 11 06:21:39 PM PDT 24 52722024 ps
T223 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2130009683 Aug 11 06:21:22 PM PDT 24 Aug 11 06:21:24 PM PDT 24 178661114 ps
T224 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1682223559 Aug 11 06:21:30 PM PDT 24 Aug 11 06:21:32 PM PDT 24 95485196 ps
T225 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.813826555 Aug 11 06:21:16 PM PDT 24 Aug 11 06:21:17 PM PDT 24 104971439 ps
T314 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3547426171 Aug 11 06:21:30 PM PDT 24 Aug 11 06:21:32 PM PDT 24 236702624 ps
T315 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.463294939 Aug 11 06:21:14 PM PDT 24 Aug 11 06:21:15 PM PDT 24 96746827 ps
T235 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.105496464 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 43038626 ps
T236 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1959325872 Aug 11 06:21:38 PM PDT 24 Aug 11 06:21:39 PM PDT 24 42360337 ps
T316 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.549284342 Aug 11 06:21:21 PM PDT 24 Aug 11 06:21:22 PM PDT 24 111808229 ps
T232 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3149076933 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:37 PM PDT 24 59925729 ps
T302 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.864927854 Aug 11 06:21:09 PM PDT 24 Aug 11 06:21:13 PM PDT 24 124525484 ps
T317 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1748657857 Aug 11 06:21:20 PM PDT 24 Aug 11 06:21:21 PM PDT 24 99178496 ps
T261 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.806858151 Aug 11 06:21:07 PM PDT 24 Aug 11 06:21:09 PM PDT 24 69029292 ps
T233 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2899620960 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 42804708 ps
T283 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1124321002 Aug 11 06:21:08 PM PDT 24 Aug 11 06:21:10 PM PDT 24 149295986 ps
T262 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1040458650 Aug 11 06:21:10 PM PDT 24 Aug 11 06:21:16 PM PDT 24 1316207694 ps
T269 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.556754205 Aug 11 06:21:26 PM PDT 24 Aug 11 06:21:28 PM PDT 24 211431874 ps
T318 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3830947315 Aug 11 06:21:10 PM PDT 24 Aug 11 06:21:11 PM PDT 24 183746766 ps
T3634 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1358317062 Aug 11 06:21:20 PM PDT 24 Aug 11 06:21:28 PM PDT 24 752573228 ps
T366 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.403206723 Aug 11 06:21:36 PM PDT 24 Aug 11 06:21:37 PM PDT 24 38711236 ps
T3635 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3664966098 Aug 11 06:21:09 PM PDT 24 Aug 11 06:21:13 PM PDT 24 682639428 ps
T272 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.100457559 Aug 11 06:21:07 PM PDT 24 Aug 11 06:21:12 PM PDT 24 1272567936 ps
T3636 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1788904815 Aug 11 06:21:30 PM PDT 24 Aug 11 06:21:32 PM PDT 24 81014638 ps
T278 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3809159483 Aug 11 06:21:10 PM PDT 24 Aug 11 06:21:13 PM PDT 24 120389311 ps
T279 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1164123116 Aug 11 06:21:05 PM PDT 24 Aug 11 06:21:08 PM PDT 24 160387764 ps
T369 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1497630000 Aug 11 06:21:20 PM PDT 24 Aug 11 06:21:20 PM PDT 24 60114474 ps
T3637 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3863916371 Aug 11 06:21:21 PM PDT 24 Aug 11 06:21:22 PM PDT 24 115841963 ps
T284 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1940009113 Aug 11 06:21:11 PM PDT 24 Aug 11 06:21:12 PM PDT 24 144098662 ps
T3638 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1536572807 Aug 11 06:21:13 PM PDT 24 Aug 11 06:21:15 PM PDT 24 97099072 ps
T280 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.78014993 Aug 11 06:21:18 PM PDT 24 Aug 11 06:21:20 PM PDT 24 70550223 ps
T367 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.4241742792 Aug 11 06:21:06 PM PDT 24 Aug 11 06:21:07 PM PDT 24 61967107 ps
T273 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3706998505 Aug 11 06:21:27 PM PDT 24 Aug 11 06:21:30 PM PDT 24 496494186 ps
T333 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2619379643 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 73557748 ps
T327 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2238753432 Aug 11 06:21:28 PM PDT 24 Aug 11 06:21:33 PM PDT 24 944268303 ps
T368 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3926477543 Aug 11 06:21:39 PM PDT 24 Aug 11 06:21:40 PM PDT 24 49826560 ps
T3639 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3642633151 Aug 11 06:21:07 PM PDT 24 Aug 11 06:21:11 PM PDT 24 501956567 ps
T334 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.301093861 Aug 11 06:21:41 PM PDT 24 Aug 11 06:21:42 PM PDT 24 42496036 ps
T303 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1926392261 Aug 11 06:21:11 PM PDT 24 Aug 11 06:21:12 PM PDT 24 96954108 ps
T335 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1388354802 Aug 11 06:21:22 PM PDT 24 Aug 11 06:21:23 PM PDT 24 47090965 ps
T3640 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2563559622 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:17 PM PDT 24 86010250 ps
T304 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1831028189 Aug 11 06:21:11 PM PDT 24 Aug 11 06:21:12 PM PDT 24 47762540 ps
T377 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2378608194 Aug 11 06:21:23 PM PDT 24 Aug 11 06:21:27 PM PDT 24 601700991 ps
T336 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2367144793 Aug 11 06:21:36 PM PDT 24 Aug 11 06:21:37 PM PDT 24 102976758 ps
T3641 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.950921896 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 65945153 ps
T3642 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3565841453 Aug 11 06:21:06 PM PDT 24 Aug 11 06:21:07 PM PDT 24 140481375 ps
T3643 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1349336592 Aug 11 06:21:26 PM PDT 24 Aug 11 06:21:29 PM PDT 24 158639831 ps
T370 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2413485651 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 52216559 ps
T3644 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2477476558 Aug 11 06:21:12 PM PDT 24 Aug 11 06:21:13 PM PDT 24 40047109 ps
T3645 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2623336865 Aug 11 06:21:26 PM PDT 24 Aug 11 06:21:28 PM PDT 24 149262830 ps
T3646 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2738753456 Aug 11 06:21:07 PM PDT 24 Aug 11 06:21:10 PM PDT 24 141279078 ps
T3647 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.447838195 Aug 11 06:21:29 PM PDT 24 Aug 11 06:21:30 PM PDT 24 43362763 ps
T3648 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3677883037 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:16 PM PDT 24 42273433 ps
T376 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.501896124 Aug 11 06:21:18 PM PDT 24 Aug 11 06:21:20 PM PDT 24 298061352 ps
T3649 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.383557893 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 33571422 ps
T305 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3058503322 Aug 11 06:21:24 PM PDT 24 Aug 11 06:21:25 PM PDT 24 74001030 ps
T3650 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1077933505 Aug 11 06:21:39 PM PDT 24 Aug 11 06:21:40 PM PDT 24 38524873 ps
T328 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.774223201 Aug 11 06:21:27 PM PDT 24 Aug 11 06:21:30 PM PDT 24 462254681 ps
T373 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3766903575 Aug 11 06:21:30 PM PDT 24 Aug 11 06:21:36 PM PDT 24 1170043820 ps
T3651 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3872585911 Aug 11 06:21:24 PM PDT 24 Aug 11 06:21:26 PM PDT 24 160467437 ps
T3652 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.54562208 Aug 11 06:21:32 PM PDT 24 Aug 11 06:21:33 PM PDT 24 178882398 ps
T281 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4063219543 Aug 11 06:21:14 PM PDT 24 Aug 11 06:21:17 PM PDT 24 108407669 ps
T329 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.393839202 Aug 11 06:21:33 PM PDT 24 Aug 11 06:21:35 PM PDT 24 162594034 ps
T3653 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1609628176 Aug 11 06:21:23 PM PDT 24 Aug 11 06:21:24 PM PDT 24 96843796 ps
T306 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1298835046 Aug 11 06:21:20 PM PDT 24 Aug 11 06:21:21 PM PDT 24 66130931 ps
T3654 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1912217486 Aug 11 06:21:05 PM PDT 24 Aug 11 06:21:06 PM PDT 24 48816523 ps
T3655 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.436215827 Aug 11 06:21:30 PM PDT 24 Aug 11 06:21:31 PM PDT 24 37232680 ps
T307 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.161477153 Aug 11 06:21:06 PM PDT 24 Aug 11 06:21:07 PM PDT 24 49076801 ps
T3656 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3228522518 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:16 PM PDT 24 79396180 ps
T3657 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1057153188 Aug 11 06:21:16 PM PDT 24 Aug 11 06:21:18 PM PDT 24 71157190 ps
T3658 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2695900957 Aug 11 06:21:14 PM PDT 24 Aug 11 06:21:16 PM PDT 24 126415077 ps
T308 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.868551019 Aug 11 06:21:20 PM PDT 24 Aug 11 06:21:21 PM PDT 24 56539758 ps
T330 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1951331037 Aug 11 06:21:16 PM PDT 24 Aug 11 06:21:18 PM PDT 24 242458592 ps
T3659 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1959816017 Aug 11 06:21:05 PM PDT 24 Aug 11 06:21:07 PM PDT 24 140417120 ps
T309 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1840910539 Aug 11 06:21:10 PM PDT 24 Aug 11 06:21:12 PM PDT 24 83923852 ps
T331 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1106491788 Aug 11 06:21:04 PM PDT 24 Aug 11 06:21:05 PM PDT 24 156899146 ps
T3660 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2484176595 Aug 11 06:21:16 PM PDT 24 Aug 11 06:21:18 PM PDT 24 124202554 ps
T310 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.710556883 Aug 11 06:21:02 PM PDT 24 Aug 11 06:21:05 PM PDT 24 170652078 ps
T3661 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2002551369 Aug 11 06:21:29 PM PDT 24 Aug 11 06:21:30 PM PDT 24 58351940 ps
T332 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.546332682 Aug 11 06:21:32 PM PDT 24 Aug 11 06:21:34 PM PDT 24 167802787 ps
T3662 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3337448602 Aug 11 06:21:36 PM PDT 24 Aug 11 06:21:37 PM PDT 24 83070642 ps
T380 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.5620345 Aug 11 06:21:11 PM PDT 24 Aug 11 06:21:17 PM PDT 24 1394889667 ps
T3663 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3037384166 Aug 11 06:21:20 PM PDT 24 Aug 11 06:21:22 PM PDT 24 146921763 ps
T3664 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3696989050 Aug 11 06:21:33 PM PDT 24 Aug 11 06:21:33 PM PDT 24 53077819 ps
T3665 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1278239090 Aug 11 06:21:09 PM PDT 24 Aug 11 06:21:10 PM PDT 24 56336178 ps
T3666 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2694885648 Aug 11 06:21:29 PM PDT 24 Aug 11 06:21:32 PM PDT 24 183067633 ps
T3667 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3818122190 Aug 11 06:21:26 PM PDT 24 Aug 11 06:21:26 PM PDT 24 68239164 ps
T3668 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3640074511 Aug 11 06:21:04 PM PDT 24 Aug 11 06:21:07 PM PDT 24 580864153 ps
T3669 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4239699802 Aug 11 06:21:24 PM PDT 24 Aug 11 06:21:25 PM PDT 24 63532806 ps
T3670 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3303106442 Aug 11 06:21:05 PM PDT 24 Aug 11 06:21:08 PM PDT 24 260099874 ps
T3671 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.573602636 Aug 11 06:21:14 PM PDT 24 Aug 11 06:21:15 PM PDT 24 55384634 ps
T3672 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3442494909 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:16 PM PDT 24 46345398 ps
T3673 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1625039856 Aug 11 06:21:22 PM PDT 24 Aug 11 06:21:23 PM PDT 24 53192581 ps
T3674 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.222154915 Aug 11 06:21:21 PM PDT 24 Aug 11 06:21:23 PM PDT 24 79179346 ps
T3675 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.994274601 Aug 11 06:21:38 PM PDT 24 Aug 11 06:21:39 PM PDT 24 98122359 ps
T3676 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.377604438 Aug 11 06:21:21 PM PDT 24 Aug 11 06:21:22 PM PDT 24 75168828 ps
T3677 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.580495228 Aug 11 06:21:11 PM PDT 24 Aug 11 06:21:11 PM PDT 24 66813933 ps
T3678 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.943442286 Aug 11 06:21:22 PM PDT 24 Aug 11 06:21:24 PM PDT 24 57540913 ps
T3679 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1309070309 Aug 11 06:21:32 PM PDT 24 Aug 11 06:21:33 PM PDT 24 34091093 ps
T3680 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3802660407 Aug 11 06:21:31 PM PDT 24 Aug 11 06:21:33 PM PDT 24 184115803 ps
T3681 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3747187737 Aug 11 06:21:22 PM PDT 24 Aug 11 06:21:23 PM PDT 24 246673823 ps
T3682 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1870062593 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:16 PM PDT 24 188462267 ps
T3683 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3966465849 Aug 11 06:21:07 PM PDT 24 Aug 11 06:21:08 PM PDT 24 182277728 ps
T3684 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3574360861 Aug 11 06:21:38 PM PDT 24 Aug 11 06:21:39 PM PDT 24 46674521 ps
T3685 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.996732635 Aug 11 06:21:34 PM PDT 24 Aug 11 06:21:35 PM PDT 24 42834368 ps
T3686 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3622224517 Aug 11 06:21:27 PM PDT 24 Aug 11 06:21:28 PM PDT 24 77178232 ps
T311 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2916371555 Aug 11 06:21:30 PM PDT 24 Aug 11 06:21:31 PM PDT 24 96296361 ps
T282 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1434680449 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:17 PM PDT 24 150858666 ps
T3687 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2920681076 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:16 PM PDT 24 79305101 ps
T3688 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.18397345 Aug 11 06:21:12 PM PDT 24 Aug 11 06:21:15 PM PDT 24 343483229 ps
T3689 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.926431554 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:17 PM PDT 24 83451479 ps
T3690 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4029625614 Aug 11 06:21:06 PM PDT 24 Aug 11 06:21:12 PM PDT 24 1291141040 ps
T3691 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1961206442 Aug 11 06:21:27 PM PDT 24 Aug 11 06:21:28 PM PDT 24 110077268 ps
T3692 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.563972366 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:18 PM PDT 24 183985450 ps
T3693 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.56545835 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 104230265 ps
T3694 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.824801042 Aug 11 06:21:05 PM PDT 24 Aug 11 06:21:07 PM PDT 24 97448234 ps
T3695 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1949617252 Aug 11 06:21:16 PM PDT 24 Aug 11 06:21:17 PM PDT 24 75601418 ps
T384 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1669771873 Aug 11 06:21:16 PM PDT 24 Aug 11 06:21:19 PM PDT 24 531900580 ps
T3696 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.248239356 Aug 11 06:21:27 PM PDT 24 Aug 11 06:21:28 PM PDT 24 101814798 ps
T374 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1559633184 Aug 11 06:21:16 PM PDT 24 Aug 11 06:21:22 PM PDT 24 1359877672 ps
T3697 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2677920483 Aug 11 06:21:20 PM PDT 24 Aug 11 06:21:22 PM PDT 24 68883779 ps
T3698 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3334839862 Aug 11 06:21:27 PM PDT 24 Aug 11 06:21:28 PM PDT 24 40406501 ps
T3699 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2806209330 Aug 11 06:21:16 PM PDT 24 Aug 11 06:21:16 PM PDT 24 41315200 ps
T3700 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.130896977 Aug 11 06:21:29 PM PDT 24 Aug 11 06:21:31 PM PDT 24 188739949 ps
T3701 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2698728984 Aug 11 06:21:32 PM PDT 24 Aug 11 06:21:33 PM PDT 24 85281295 ps
T378 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3884198206 Aug 11 06:21:24 PM PDT 24 Aug 11 06:21:26 PM PDT 24 464984557 ps
T3702 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.594892298 Aug 11 06:21:17 PM PDT 24 Aug 11 06:21:18 PM PDT 24 102114226 ps
T3703 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3180205475 Aug 11 06:21:28 PM PDT 24 Aug 11 06:21:30 PM PDT 24 80181054 ps
T3704 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.251985343 Aug 11 06:21:24 PM PDT 24 Aug 11 06:21:25 PM PDT 24 57306726 ps
T3705 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2783929095 Aug 11 06:21:14 PM PDT 24 Aug 11 06:21:15 PM PDT 24 66076836 ps
T3706 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1258833507 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 57841867 ps
T383 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3423661925 Aug 11 06:21:28 PM PDT 24 Aug 11 06:21:33 PM PDT 24 533199601 ps
T381 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.274463779 Aug 11 06:21:26 PM PDT 24 Aug 11 06:21:30 PM PDT 24 521430663 ps
T3707 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.271299934 Aug 11 06:21:11 PM PDT 24 Aug 11 06:21:12 PM PDT 24 241860921 ps
T3708 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3177177965 Aug 11 06:21:27 PM PDT 24 Aug 11 06:21:28 PM PDT 24 41206299 ps
T3709 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2174939914 Aug 11 06:21:29 PM PDT 24 Aug 11 06:21:31 PM PDT 24 75591706 ps
T3710 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3199484528 Aug 11 06:21:29 PM PDT 24 Aug 11 06:21:32 PM PDT 24 111154779 ps
T3711 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3392253820 Aug 11 06:21:36 PM PDT 24 Aug 11 06:21:36 PM PDT 24 57934766 ps
T3712 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3464355740 Aug 11 06:21:06 PM PDT 24 Aug 11 06:21:07 PM PDT 24 128655812 ps
T3713 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2683695735 Aug 11 06:21:21 PM PDT 24 Aug 11 06:21:23 PM PDT 24 71945051 ps
T3714 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3348374968 Aug 11 06:21:20 PM PDT 24 Aug 11 06:21:21 PM PDT 24 111547411 ps
T3715 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3876190082 Aug 11 06:21:32 PM PDT 24 Aug 11 06:21:34 PM PDT 24 86245852 ps
T382 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1538316456 Aug 11 06:21:23 PM PDT 24 Aug 11 06:21:28 PM PDT 24 1275208259 ps
T3716 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.495053423 Aug 11 06:21:39 PM PDT 24 Aug 11 06:21:39 PM PDT 24 36179731 ps
T3717 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2172378212 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 37078080 ps
T3718 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4034146324 Aug 11 06:21:31 PM PDT 24 Aug 11 06:21:32 PM PDT 24 144211233 ps
T3719 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2233194464 Aug 11 06:21:23 PM PDT 24 Aug 11 06:21:25 PM PDT 24 145883051 ps
T3720 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3117632169 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 38403340 ps
T3721 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4087220942 Aug 11 06:21:10 PM PDT 24 Aug 11 06:21:15 PM PDT 24 898603208 ps
T3722 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.892748638 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 60723519 ps
T3723 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2161930742 Aug 11 06:21:17 PM PDT 24 Aug 11 06:21:18 PM PDT 24 54944022 ps
T3724 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4049030466 Aug 11 06:21:16 PM PDT 24 Aug 11 06:21:18 PM PDT 24 72106070 ps
T3725 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.363833021 Aug 11 06:21:18 PM PDT 24 Aug 11 06:21:19 PM PDT 24 63269926 ps
T3726 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.471851548 Aug 11 06:21:21 PM PDT 24 Aug 11 06:21:24 PM PDT 24 194408835 ps
T3727 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.199472553 Aug 11 06:21:32 PM PDT 24 Aug 11 06:21:32 PM PDT 24 33653888 ps
T3728 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2737007080 Aug 11 06:21:34 PM PDT 24 Aug 11 06:21:35 PM PDT 24 35810353 ps
T379 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3879452009 Aug 11 06:21:17 PM PDT 24 Aug 11 06:21:21 PM PDT 24 698708874 ps
T3729 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1695992530 Aug 11 06:21:14 PM PDT 24 Aug 11 06:21:16 PM PDT 24 99665064 ps
T3730 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3988461595 Aug 11 06:21:23 PM PDT 24 Aug 11 06:21:25 PM PDT 24 109716340 ps
T3731 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2455100156 Aug 11 06:21:06 PM PDT 24 Aug 11 06:21:15 PM PDT 24 910576927 ps
T3732 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2635467053 Aug 11 06:21:37 PM PDT 24 Aug 11 06:21:38 PM PDT 24 45611031 ps
T3733 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.616897322 Aug 11 06:21:05 PM PDT 24 Aug 11 06:21:06 PM PDT 24 95234593 ps
T375 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2895535455 Aug 11 06:21:30 PM PDT 24 Aug 11 06:21:35 PM PDT 24 953205171 ps
T3734 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.67479912 Aug 11 06:21:36 PM PDT 24 Aug 11 06:21:37 PM PDT 24 61966855 ps
T3735 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2968494040 Aug 11 06:21:14 PM PDT 24 Aug 11 06:21:15 PM PDT 24 51650161 ps
T3736 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3098618960 Aug 11 06:21:11 PM PDT 24 Aug 11 06:21:12 PM PDT 24 198796162 ps
T3737 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3206480924 Aug 11 06:21:15 PM PDT 24 Aug 11 06:21:18 PM PDT 24 357595047 ps
T3738 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1196077034 Aug 11 06:21:07 PM PDT 24 Aug 11 06:21:10 PM PDT 24 115316966 ps
T3739 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3440314140 Aug 11 06:21:24 PM PDT 24 Aug 11 06:21:27 PM PDT 24 601510634 ps
T3740 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3067818471 Aug 11 06:21:31 PM PDT 24 Aug 11 06:21:34 PM PDT 24 149386339 ps


Test location /workspace/coverage/default/147.usbdev_tx_rx_disruption.2862633671
Short name T31
Test name
Test status
Simulation time 639964903 ps
CPU time 1.71 seconds
Started Aug 11 07:17:22 PM PDT 24
Finished Aug 11 07:17:24 PM PDT 24
Peak memory 207524 kb
Host smart-6c73f12d-fac5-4fee-bae5-6b5a2b343d9e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862633671 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.usbdev_tx_rx_disruption.2862633671
Directory /workspace/147.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/48.usbdev_device_address.3566348945
Short name T66
Test name
Test status
Simulation time 25421941047 ps
CPU time 38.87 seconds
Started Aug 11 07:16:23 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 207852 kb
Host smart-72225a08-f3d9-4d04-90ab-78512d24ee11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35663
48945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3566348945
Directory /workspace/48.usbdev_device_address/latest


Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1576926260
Short name T9
Test name
Test status
Simulation time 12265721154 ps
CPU time 17.67 seconds
Started Aug 11 07:13:31 PM PDT 24
Finished Aug 11 07:13:49 PM PDT 24
Peak memory 207804 kb
Host smart-14bc8313-0e77-469a-81a2-76d4a55c8cf8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576926260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.1576926260
Directory /workspace/29.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2899620960
Short name T233
Test name
Test status
Simulation time 42804708 ps
CPU time 0.73 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206512 kb
Host smart-a297ea24-1ec9-4d60-882b-1d5434ec798e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2899620960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2899620960
Directory /workspace/40.usbdev_intr_test/latest


Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.242061297
Short name T105
Test name
Test status
Simulation time 5305454698 ps
CPU time 163.29 seconds
Started Aug 11 07:14:44 PM PDT 24
Finished Aug 11 07:17:27 PM PDT 24
Peak memory 218540 kb
Host smart-668c0361-3e18-458d-8fdb-dfe9b0c1d00f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=242061297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.242061297
Directory /workspace/36.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1124321002
Short name T283
Test name
Test status
Simulation time 149295986 ps
CPU time 1.77 seconds
Started Aug 11 06:21:08 PM PDT 24
Finished Aug 11 06:21:10 PM PDT 24
Peak memory 215172 kb
Host smart-1ea317ba-af16-4c0a-ad28-b5e8a8624f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124321002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1124321002
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2194968281
Short name T7
Test name
Test status
Simulation time 15041785926 ps
CPU time 20.25 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:33 PM PDT 24
Peak memory 215964 kb
Host smart-f1fb3387-9f1b-420a-adb6-886b8e5984a1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194968281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2194968281
Directory /workspace/46.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/42.usbdev_link_resume.2441635405
Short name T70
Test name
Test status
Simulation time 6864952059 ps
CPU time 8.3 seconds
Started Aug 11 07:15:35 PM PDT 24
Finished Aug 11 07:15:44 PM PDT 24
Peak memory 216008 kb
Host smart-a51a3697-0f97-47d6-b1c3-f43f4a9cf020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24416
35405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2441635405
Directory /workspace/42.usbdev_link_resume/latest


Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2671079623
Short name T60
Test name
Test status
Simulation time 1030359695 ps
CPU time 2.86 seconds
Started Aug 11 07:09:52 PM PDT 24
Finished Aug 11 07:09:55 PM PDT 24
Peak memory 207768 kb
Host smart-13aaeb28-6a37-4165-bbb5-ad8af977ffda
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2671079623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2671079623
Directory /workspace/7.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/0.usbdev_sec_cm.301613784
Short name T238
Test name
Test status
Simulation time 300859758 ps
CPU time 1.14 seconds
Started Aug 11 07:08:29 PM PDT 24
Finished Aug 11 07:08:30 PM PDT 24
Peak memory 223636 kb
Host smart-a568a7fa-84fc-42a6-b5fd-a85a2dc3d8e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=301613784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.301613784
Directory /workspace/0.usbdev_sec_cm/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2970899157
Short name T251
Test name
Test status
Simulation time 318701340 ps
CPU time 1.14 seconds
Started Aug 11 07:08:29 PM PDT 24
Finished Aug 11 07:08:30 PM PDT 24
Peak memory 207528 kb
Host smart-45894cb0-cfe7-424f-9789-8efa4ea71977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29708
99157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.2970899157
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest


Test location /workspace/coverage/default/174.usbdev_tx_rx_disruption.523396481
Short name T109
Test name
Test status
Simulation time 520058954 ps
CPU time 1.49 seconds
Started Aug 11 07:17:12 PM PDT 24
Finished Aug 11 07:17:14 PM PDT 24
Peak memory 207564 kb
Host smart-fdd94043-b1cd-4a98-b287-932918ff4e9c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523396481 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 174.usbdev_tx_rx_disruption.523396481
Directory /workspace/174.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/3.usbdev_device_address.2504822942
Short name T37
Test name
Test status
Simulation time 16418266127 ps
CPU time 24.85 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:36 PM PDT 24
Peak memory 207744 kb
Host smart-a920cbb8-0567-4f21-86fe-72ce4802c3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25048
22942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2504822942
Directory /workspace/3.usbdev_device_address/latest


Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2644297430
Short name T25
Test name
Test status
Simulation time 33012432 ps
CPU time 0.69 seconds
Started Aug 11 07:13:30 PM PDT 24
Finished Aug 11 07:13:31 PM PDT 24
Peak memory 207528 kb
Host smart-54c08dd7-6946-4300-9fc5-4f72f6271cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26442
97430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2644297430
Directory /workspace/28.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3149076933
Short name T232
Test name
Test status
Simulation time 59925729 ps
CPU time 0.74 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:37 PM PDT 24
Peak memory 206512 kb
Host smart-b7886378-1c0e-443b-ad1c-ec357069ba7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3149076933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3149076933
Directory /workspace/43.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3324973587
Short name T265
Test name
Test status
Simulation time 103377814 ps
CPU time 1.01 seconds
Started Aug 11 06:21:22 PM PDT 24
Finished Aug 11 06:21:24 PM PDT 24
Peak memory 206760 kb
Host smart-b5e8f2fc-b872-4001-a5dd-e16b5bfa65eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3324973587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3324973587
Directory /workspace/13.usbdev_csr_rw/latest


Test location /workspace/coverage/default/420.usbdev_tx_rx_disruption.948154117
Short name T253
Test name
Test status
Simulation time 459432332 ps
CPU time 1.47 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:07 PM PDT 24
Peak memory 207536 kb
Host smart-f538a45d-d478-4621-871c-ff0b2af5bf4b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948154117 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 420.usbdev_tx_rx_disruption.948154117
Directory /workspace/420.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3470582384
Short name T115
Test name
Test status
Simulation time 10550412901 ps
CPU time 13.96 seconds
Started Aug 11 07:11:19 PM PDT 24
Finished Aug 11 07:11:33 PM PDT 24
Peak memory 207872 kb
Host smart-66350baf-310c-4907-bb1e-6d82f52440df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470582384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.3470582384
Directory /workspace/14.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3766903575
Short name T373
Test name
Test status
Simulation time 1170043820 ps
CPU time 5.46 seconds
Started Aug 11 06:21:30 PM PDT 24
Finished Aug 11 06:21:36 PM PDT 24
Peak memory 206940 kb
Host smart-36e0e4b8-1503-4225-afdd-c72dbff06111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3766903575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3766903575
Directory /workspace/18.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2272000949
Short name T117
Test name
Test status
Simulation time 30341190434 ps
CPU time 34.33 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:12:12 PM PDT 24
Peak memory 207820 kb
Host smart-97622411-8840-4e38-8d7e-2289018dfa9b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272000949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.2272000949
Directory /workspace/16.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3071133110
Short name T3498
Test name
Test status
Simulation time 7302029123 ps
CPU time 9.29 seconds
Started Aug 11 07:15:24 PM PDT 24
Finished Aug 11 07:15:34 PM PDT 24
Peak memory 216016 kb
Host smart-3c291e8e-2733-47d0-8a0c-825148daaae7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071133110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.3071133110
Directory /workspace/42.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/482.usbdev_tx_rx_disruption.2382077624
Short name T256
Test name
Test status
Simulation time 519892102 ps
CPU time 1.7 seconds
Started Aug 11 07:18:14 PM PDT 24
Finished Aug 11 07:18:16 PM PDT 24
Peak memory 207596 kb
Host smart-089490fb-b551-4270-be11-88f9e07749a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382077624 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 482.usbdev_tx_rx_disruption.2382077624
Directory /workspace/482.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2051904658
Short name T21
Test name
Test status
Simulation time 156789401 ps
CPU time 0.87 seconds
Started Aug 11 07:12:54 PM PDT 24
Finished Aug 11 07:12:55 PM PDT 24
Peak memory 207720 kb
Host smart-df67ac51-a03d-4023-a4b1-14e320adf14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20519
04658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2051904658
Directory /workspace/23.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1461323530
Short name T277
Test name
Test status
Simulation time 17892621561 ps
CPU time 43.57 seconds
Started Aug 11 07:15:52 PM PDT 24
Finished Aug 11 07:16:36 PM PDT 24
Peak memory 224180 kb
Host smart-bd02e11e-5e17-4323-9618-7f70bd74e17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14613
23530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1461323530
Directory /workspace/43.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/42.usbdev_rx_full.4887228
Short name T51
Test name
Test status
Simulation time 253068680 ps
CPU time 1.07 seconds
Started Aug 11 07:15:41 PM PDT 24
Finished Aug 11 07:15:42 PM PDT 24
Peak memory 207516 kb
Host smart-7e65fdfb-25fc-4497-a805-e135904f698d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48872
28 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.4887228
Directory /workspace/42.usbdev_rx_full/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3809159483
Short name T278
Test name
Test status
Simulation time 120389311 ps
CPU time 3.3 seconds
Started Aug 11 06:21:10 PM PDT 24
Finished Aug 11 06:21:13 PM PDT 24
Peak memory 223288 kb
Host smart-fc54df02-fc28-4dae-92f6-f9128b4bc852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3809159483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3809159483
Directory /workspace/4.usbdev_tl_errors/latest


Test location /workspace/coverage/default/13.usbdev_rx_crc_err.207486922
Short name T72
Test name
Test status
Simulation time 189157579 ps
CPU time 0.91 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:17 PM PDT 24
Peak memory 207440 kb
Host smart-5afac8f1-d320-4b55-a63c-5b688c619350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20748
6922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.207486922
Directory /workspace/13.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/19.usbdev_device_address.801771226
Short name T177
Test name
Test status
Simulation time 27545400846 ps
CPU time 49.01 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:54 PM PDT 24
Peak memory 207812 kb
Host smart-b816d055-7efc-4732-b79e-498ad9f4ac09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80177
1226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.801771226
Directory /workspace/19.usbdev_device_address/latest


Test location /workspace/coverage/default/157.usbdev_endpoint_types.1514850613
Short name T473
Test name
Test status
Simulation time 529588935 ps
CPU time 1.5 seconds
Started Aug 11 07:17:10 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 207496 kb
Host smart-dbeb6a84-6c28-46f4-83e1-0e7ee38e4fba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1514850613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.1514850613
Directory /workspace/157.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/148.usbdev_endpoint_types.2040310261
Short name T424
Test name
Test status
Simulation time 682082706 ps
CPU time 1.58 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207576 kb
Host smart-36b4edb9-ed1f-4f46-abe6-d7d745ad10a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2040310261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.2040310261
Directory /workspace/148.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/235.usbdev_tx_rx_disruption.2005731268
Short name T165
Test name
Test status
Simulation time 522947720 ps
CPU time 1.75 seconds
Started Aug 11 07:17:37 PM PDT 24
Finished Aug 11 07:17:39 PM PDT 24
Peak memory 207564 kb
Host smart-01ce1cc1-05cf-428e-bd8c-911e568089f0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005731268 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.usbdev_tx_rx_disruption.2005731268
Directory /workspace/235.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2367144793
Short name T336
Test name
Test status
Simulation time 102976758 ps
CPU time 0.82 seconds
Started Aug 11 06:21:36 PM PDT 24
Finished Aug 11 06:21:37 PM PDT 24
Peak memory 206572 kb
Host smart-5b0a2d1a-9d21-4934-88d5-9c09af70f126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2367144793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2367144793
Directory /workspace/24.usbdev_intr_test/latest


Test location /workspace/coverage/default/103.usbdev_endpoint_types.2179082233
Short name T405
Test name
Test status
Simulation time 454913664 ps
CPU time 1.38 seconds
Started Aug 11 07:16:59 PM PDT 24
Finished Aug 11 07:17:01 PM PDT 24
Peak memory 207540 kb
Host smart-e92a15d0-e4c9-46fb-a6ef-774eaaca31ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2179082233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.2179082233
Directory /workspace/103.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/136.usbdev_endpoint_types.191965027
Short name T409
Test name
Test status
Simulation time 765740674 ps
CPU time 1.81 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207516 kb
Host smart-caeade80-ea43-4e19-9786-d336f917ccf3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=191965027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.191965027
Directory /workspace/136.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/162.usbdev_endpoint_types.2564639174
Short name T483
Test name
Test status
Simulation time 625545641 ps
CPU time 1.54 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207508 kb
Host smart-45ed7957-f5ca-4421-9a27-9cafb384f77d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2564639174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.2564639174
Directory /workspace/162.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/33.usbdev_endpoint_types.2245872869
Short name T458
Test name
Test status
Simulation time 566453962 ps
CPU time 1.42 seconds
Started Aug 11 07:14:09 PM PDT 24
Finished Aug 11 07:14:11 PM PDT 24
Peak memory 207492 kb
Host smart-68ca5f22-b7db-45cd-8ec8-f428887524ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2245872869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.2245872869
Directory /workspace/33.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/0.usbdev_disconnected.3643313424
Short name T884
Test name
Test status
Simulation time 178472563 ps
CPU time 0.86 seconds
Started Aug 11 07:08:26 PM PDT 24
Finished Aug 11 07:08:27 PM PDT 24
Peak memory 207520 kb
Host smart-d38c13e7-1c69-4e46-a679-8f9de5de5c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36433
13424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3643313424
Directory /workspace/0.usbdev_disconnected/latest


Test location /workspace/coverage/default/10.usbdev_device_address.3317205425
Short name T104
Test name
Test status
Simulation time 24136175883 ps
CPU time 37.17 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207804 kb
Host smart-b1f05aa7-16f9-4532-8842-dea0d9c35926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33172
05425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3317205425
Directory /workspace/10.usbdev_device_address/latest


Test location /workspace/coverage/default/15.usbdev_endpoint_types.2105767281
Short name T438
Test name
Test status
Simulation time 1095467071 ps
CPU time 2.25 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:32 PM PDT 24
Peak memory 207492 kb
Host smart-5025904c-12e0-47c1-a336-b93ede3b0850
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2105767281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.2105767281
Directory /workspace/15.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/194.usbdev_endpoint_types.1728659913
Short name T414
Test name
Test status
Simulation time 521910714 ps
CPU time 1.42 seconds
Started Aug 11 07:17:18 PM PDT 24
Finished Aug 11 07:17:20 PM PDT 24
Peak memory 207488 kb
Host smart-58bc2374-27d1-45ca-b097-d95f24e491f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1728659913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.1728659913
Directory /workspace/194.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/67.usbdev_endpoint_types.2382417792
Short name T476
Test name
Test status
Simulation time 867650390 ps
CPU time 1.98 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:56 PM PDT 24
Peak memory 207500 kb
Host smart-7bbfd83c-5142-4a29-a000-c438c8f9fa34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2382417792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.2382417792
Directory /workspace/67.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.1246191519
Short name T18
Test name
Test status
Simulation time 217298426 ps
CPU time 1.02 seconds
Started Aug 11 07:16:30 PM PDT 24
Finished Aug 11 07:16:31 PM PDT 24
Peak memory 207488 kb
Host smart-88ef0314-3bf2-4319-9fc9-84ccbf2465f5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1246191519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1246191519
Directory /workspace/47.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1305788758
Short name T6
Test name
Test status
Simulation time 4024939427 ps
CPU time 41.5 seconds
Started Aug 11 07:16:11 PM PDT 24
Finished Aug 11 07:16:52 PM PDT 24
Peak memory 218812 kb
Host smart-a808e67f-101f-4085-9c3c-d1cbcb6f137e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1305788758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1305788758
Directory /workspace/45.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3762947462
Short name T350
Test name
Test status
Simulation time 1449524909 ps
CPU time 3.44 seconds
Started Aug 11 07:08:56 PM PDT 24
Finished Aug 11 07:08:59 PM PDT 24
Peak memory 207776 kb
Host smart-6944c3de-30f0-4d10-8415-e713a724f0bf
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3762947462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3762947462
Directory /workspace/2.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/86.usbdev_endpoint_types.3899336911
Short name T478
Test name
Test status
Simulation time 581360671 ps
CPU time 1.47 seconds
Started Aug 11 07:16:52 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207504 kb
Host smart-66a067c1-8169-4586-8ce7-6859a7688b0c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3899336911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.3899336911
Directory /workspace/86.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/96.usbdev_endpoint_types.3199639189
Short name T249
Test name
Test status
Simulation time 570543601 ps
CPU time 1.53 seconds
Started Aug 11 07:16:56 PM PDT 24
Finished Aug 11 07:16:57 PM PDT 24
Peak memory 207532 kb
Host smart-d19fff5a-2ff1-461f-9cf2-5ecb1697076c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3199639189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.3199639189
Directory /workspace/96.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/30.usbdev_pkt_buffer.12228644
Short name T293
Test name
Test status
Simulation time 18321119155 ps
CPU time 44.92 seconds
Started Aug 11 07:13:50 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 216044 kb
Host smart-8c290018-9bb8-4cb3-8e43-834b7f11163c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12228
644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.12228644
Directory /workspace/30.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/0.usbdev_setup_priority.1914375278
Short name T54
Test name
Test status
Simulation time 414094521 ps
CPU time 1.46 seconds
Started Aug 11 07:08:32 PM PDT 24
Finished Aug 11 07:08:33 PM PDT 24
Peak memory 207528 kb
Host smart-afd498be-d84c-43a9-99f3-61a9ee1d0ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19143
75278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1914375278
Directory /workspace/0.usbdev_setup_priority/latest


Test location /workspace/coverage/default/144.usbdev_endpoint_types.1433403259
Short name T452
Test name
Test status
Simulation time 674658405 ps
CPU time 1.67 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207516 kb
Host smart-48f1da27-25de-4466-a62d-6ab0d00cb620
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1433403259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.1433403259
Directory /workspace/144.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/150.usbdev_endpoint_types.2021702231
Short name T468
Test name
Test status
Simulation time 587801335 ps
CPU time 1.45 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207552 kb
Host smart-431056cb-d9e3-415f-99f1-3f01f173855d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2021702231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.2021702231
Directory /workspace/150.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/47.usbdev_nak_trans.1117103710
Short name T131
Test name
Test status
Simulation time 202186373 ps
CPU time 0.91 seconds
Started Aug 11 07:16:16 PM PDT 24
Finished Aug 11 07:16:17 PM PDT 24
Peak memory 207556 kb
Host smart-a4fdfeb1-e838-474b-b5ae-29330c9b2a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11171
03710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1117103710
Directory /workspace/47.usbdev_nak_trans/latest


Test location /workspace/coverage/default/0.usbdev_alert_test.4231703770
Short name T217
Test name
Test status
Simulation time 39762041 ps
CPU time 0.68 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:32 PM PDT 24
Peak memory 207488 kb
Host smart-59ef9681-9c0e-4a14-bcad-b1061f1eae2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4231703770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.4231703770
Directory /workspace/0.usbdev_alert_test/latest


Test location /workspace/coverage/default/0.usbdev_av_overflow.354303500
Short name T90
Test name
Test status
Simulation time 150698080 ps
CPU time 0.89 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 207456 kb
Host smart-c72af282-6eb5-457c-b902-85615bf3b82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35430
3500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.354303500
Directory /workspace/0.usbdev_av_overflow/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1912217486
Short name T3654
Test name
Test status
Simulation time 48816523 ps
CPU time 0.73 seconds
Started Aug 11 06:21:05 PM PDT 24
Finished Aug 11 06:21:06 PM PDT 24
Peak memory 206532 kb
Host smart-47d56f66-59f5-463f-96df-3e811fa43233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1912217486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1912217486
Directory /workspace/1.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2238753432
Short name T327
Test name
Test status
Simulation time 944268303 ps
CPU time 5.03 seconds
Started Aug 11 06:21:28 PM PDT 24
Finished Aug 11 06:21:33 PM PDT 24
Peak memory 206948 kb
Host smart-852e2d40-427b-4530-9128-aa1463e3b29e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2238753432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2238753432
Directory /workspace/17.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/1.usbdev_pkt_received.2207336973
Short name T706
Test name
Test status
Simulation time 235335271 ps
CPU time 1.04 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:08:46 PM PDT 24
Peak memory 207564 kb
Host smart-22e854bf-ca6f-469f-96bd-7412310c75d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22073
36973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2207336973
Directory /workspace/1.usbdev_pkt_received/latest


Test location /workspace/coverage/default/111.usbdev_endpoint_types.1143918039
Short name T425
Test name
Test status
Simulation time 598187934 ps
CPU time 1.56 seconds
Started Aug 11 07:17:04 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207444 kb
Host smart-232f93e8-f2ac-4afc-8636-551718f3604d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1143918039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.1143918039
Directory /workspace/111.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/112.usbdev_endpoint_types.483135109
Short name T533
Test name
Test status
Simulation time 736951141 ps
CPU time 1.82 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 207504 kb
Host smart-a5cf735e-258d-4f17-857a-7d3c75928312
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=483135109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.483135109
Directory /workspace/112.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/119.usbdev_endpoint_types.2694162840
Short name T487
Test name
Test status
Simulation time 350769494 ps
CPU time 1.18 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207540 kb
Host smart-597202ae-4c2f-4d64-9a7e-4c5bd645189c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2694162840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.2694162840
Directory /workspace/119.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/129.usbdev_endpoint_types.3768889850
Short name T459
Test name
Test status
Simulation time 433038362 ps
CPU time 1.28 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 207716 kb
Host smart-34146b94-fe1d-40a5-8429-a9d9d2761c36
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3768889850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.3768889850
Directory /workspace/129.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/141.usbdev_endpoint_types.3776430421
Short name T447
Test name
Test status
Simulation time 548554520 ps
CPU time 1.68 seconds
Started Aug 11 07:17:09 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207492 kb
Host smart-38a68ebb-f7ec-4bd9-aac0-11687de5e870
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3776430421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.3776430421
Directory /workspace/141.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.3024657574
Short name T2409
Test name
Test status
Simulation time 1111433487 ps
CPU time 2.93 seconds
Started Aug 11 07:11:49 PM PDT 24
Finished Aug 11 07:11:52 PM PDT 24
Peak memory 207744 kb
Host smart-4c4270d4-9fb9-4c88-b87c-8a1e7a0e0b4b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3024657574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.3024657574
Directory /workspace/17.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/2.usbdev_freq_loclk.3781176761
Short name T359
Test name
Test status
Simulation time 111099165573 ps
CPU time 182.06 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207868 kb
Host smart-7d01cce2-1328-479b-b8e1-5c6ada7aef48
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3781176761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.3781176761
Directory /workspace/2.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/30.usbdev_endpoint_types.4198720696
Short name T418
Test name
Test status
Simulation time 630320507 ps
CPU time 1.51 seconds
Started Aug 11 07:13:42 PM PDT 24
Finished Aug 11 07:13:44 PM PDT 24
Peak memory 207484 kb
Host smart-a634e578-e01f-452a-a5d3-c18d7bafa686
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4198720696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.4198720696
Directory /workspace/30.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/35.usbdev_endpoint_types.4213599492
Short name T509
Test name
Test status
Simulation time 521580461 ps
CPU time 1.45 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207536 kb
Host smart-8441fb33-0fc4-4f53-8cbc-48f54454385e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4213599492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.4213599492
Directory /workspace/35.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/4.usbdev_device_address.3296901838
Short name T386
Test name
Test status
Simulation time 47673967966 ps
CPU time 87.22 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:10:44 PM PDT 24
Peak memory 207772 kb
Host smart-f99e748f-5a5c-4349-8e6e-b850fa2eb39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32969
01838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3296901838
Directory /workspace/4.usbdev_device_address/latest


Test location /workspace/coverage/default/81.usbdev_endpoint_types.4144578261
Short name T535
Test name
Test status
Simulation time 616330910 ps
CPU time 1.51 seconds
Started Aug 11 07:16:52 PM PDT 24
Finished Aug 11 07:16:53 PM PDT 24
Peak memory 207484 kb
Host smart-872599f7-39b3-4094-badc-c4fb2406b7e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4144578261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.4144578261
Directory /workspace/81.usbdev_endpoint_types/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.161477153
Short name T307
Test name
Test status
Simulation time 49076801 ps
CPU time 0.81 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 206636 kb
Host smart-5b383706-12fa-4a9b-8132-d9f3a7f69ae0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=161477153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.161477153
Directory /workspace/0.usbdev_csr_rw/latest


Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3316808174
Short name T132
Test name
Test status
Simulation time 2855657557 ps
CPU time 77.47 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 218952 kb
Host smart-220214e5-50d5-4dfa-adce-e5113e935c82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3316808174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3316808174
Directory /workspace/43.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2378608194
Short name T377
Test name
Test status
Simulation time 601700991 ps
CPU time 4.37 seconds
Started Aug 11 06:21:23 PM PDT 24
Finished Aug 11 06:21:27 PM PDT 24
Peak memory 206888 kb
Host smart-e1a03530-0b82-4c26-ba46-8bdea2df5328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2378608194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2378608194
Directory /workspace/10.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/0.usbdev_endpoint_types.3688552008
Short name T467
Test name
Test status
Simulation time 345364347 ps
CPU time 1.11 seconds
Started Aug 11 07:08:23 PM PDT 24
Finished Aug 11 07:08:25 PM PDT 24
Peak memory 207508 kb
Host smart-aa75eba7-e210-48b6-9cc8-ab11f744a861
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3688552008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.3688552008
Directory /workspace/0.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/10.usbdev_endpoint_types.2009115274
Short name T3039
Test name
Test status
Simulation time 621816270 ps
CPU time 1.54 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:10:37 PM PDT 24
Peak memory 207568 kb
Host smart-5815aeb1-194b-4c95-afe4-1f022ea79082
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2009115274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.2009115274
Directory /workspace/10.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/102.usbdev_endpoint_types.2946257599
Short name T435
Test name
Test status
Simulation time 585181913 ps
CPU time 1.63 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207544 kb
Host smart-38c1533c-47e6-4445-a30b-919dc8afb69b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2946257599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.2946257599
Directory /workspace/102.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/124.usbdev_endpoint_types.4011274721
Short name T454
Test name
Test status
Simulation time 585173947 ps
CPU time 1.64 seconds
Started Aug 11 07:17:10 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 207736 kb
Host smart-ef619d38-560e-4287-9d3e-eb4d84fc640a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4011274721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.4011274721
Directory /workspace/124.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/190.usbdev_endpoint_types.3591040064
Short name T488
Test name
Test status
Simulation time 309505164 ps
CPU time 1.09 seconds
Started Aug 11 07:17:14 PM PDT 24
Finished Aug 11 07:17:15 PM PDT 24
Peak memory 207532 kb
Host smart-3a3759ed-1f29-40d0-b8ba-86012518dbea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3591040064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.3591040064
Directory /workspace/190.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/66.usbdev_endpoint_types.1563328340
Short name T422
Test name
Test status
Simulation time 381655202 ps
CPU time 1.26 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207568 kb
Host smart-c6103191-c2dc-4150-b281-36f64691c17b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1563328340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.1563328340
Directory /workspace/66.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/74.usbdev_endpoint_types.3907058269
Short name T532
Test name
Test status
Simulation time 363335457 ps
CPU time 1.26 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207504 kb
Host smart-b95227d7-1451-4b6b-99f6-6bed36af9840
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3907058269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.3907058269
Directory /workspace/74.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/76.usbdev_endpoint_types.3707231647
Short name T451
Test name
Test status
Simulation time 573044103 ps
CPU time 1.5 seconds
Started Aug 11 07:16:51 PM PDT 24
Finished Aug 11 07:16:53 PM PDT 24
Peak memory 207484 kb
Host smart-190c4094-e35e-423c-809d-6c93820d287b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3707231647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.3707231647
Directory /workspace/76.usbdev_endpoint_types/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4063219543
Short name T281
Test name
Test status
Simulation time 108407669 ps
CPU time 2.71 seconds
Started Aug 11 06:21:14 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 220768 kb
Host smart-79747925-796a-4c4f-b0df-fa0de6d5341a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4063219543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4063219543
Directory /workspace/2.usbdev_tl_errors/latest


Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.45314387
Short name T101
Test name
Test status
Simulation time 4507753608 ps
CPU time 112.71 seconds
Started Aug 11 07:08:48 PM PDT 24
Finished Aug 11 07:10:41 PM PDT 24
Peak memory 216020 kb
Host smart-9192c97c-40cb-44c7-8013-8f9775de11af
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45314387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.45314387
Directory /workspace/1.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/23.usbdev_endpoint_types.3044373565
Short name T134
Test name
Test status
Simulation time 233955897 ps
CPU time 1.02 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:12:46 PM PDT 24
Peak memory 207536 kb
Host smart-978a41ad-152d-47e5-a886-3b7d3ee1b2dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3044373565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.3044373565
Directory /workspace/23.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2474947106
Short name T1966
Test name
Test status
Simulation time 6504711658 ps
CPU time 193.23 seconds
Started Aug 11 07:09:42 PM PDT 24
Finished Aug 11 07:12:56 PM PDT 24
Peak memory 218440 kb
Host smart-8c0c53a2-2ef5-41e5-a04c-c733f38987ab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474947106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2474947106
Directory /workspace/5.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/40.usbdev_in_iso.3540496977
Short name T23
Test name
Test status
Simulation time 228738591 ps
CPU time 1.19 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 215920 kb
Host smart-a82c6739-b804-4fea-9c49-59ace16d106e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3540496977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3540496977
Directory /workspace/40.usbdev_in_iso/latest


Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.397721019
Short name T183
Test name
Test status
Simulation time 4389750709 ps
CPU time 43.61 seconds
Started Aug 11 07:08:55 PM PDT 24
Finished Aug 11 07:09:39 PM PDT 24
Peak memory 216092 kb
Host smart-6717c1c2-91b6-4591-b892-ca01db3fe126
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=397721019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.397721019
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.607164813
Short name T41
Test name
Test status
Simulation time 30919923 ps
CPU time 0.75 seconds
Started Aug 11 07:15:15 PM PDT 24
Finished Aug 11 07:15:16 PM PDT 24
Peak memory 207532 kb
Host smart-8c7f7c66-980e-43f9-bc55-18da0e39e766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60716
4813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.607164813
Directory /workspace/40.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3440314140
Short name T3739
Test name
Test status
Simulation time 601510634 ps
CPU time 2.98 seconds
Started Aug 11 06:21:24 PM PDT 24
Finished Aug 11 06:21:27 PM PDT 24
Peak memory 207032 kb
Host smart-f445fc18-6544-455e-bf3f-094062638779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3440314140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3440314140
Directory /workspace/11.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3781279335
Short name T364
Test name
Test status
Simulation time 5133930636 ps
CPU time 149.66 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:10:55 PM PDT 24
Peak memory 215996 kb
Host smart-ef4f7933-29a7-4bcb-a24d-733a623c9c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37812
79335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3781279335
Directory /workspace/0.usbdev_dpi_config_host/latest


Test location /workspace/coverage/default/1.usbdev_rx_full.3542190375
Short name T3603
Test name
Test status
Simulation time 334490968 ps
CPU time 1.25 seconds
Started Aug 11 07:08:47 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 207524 kb
Host smart-d8e821af-002f-484a-a270-ee867bf9610e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35421
90375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.3542190375
Directory /workspace/1.usbdev_rx_full/latest


Test location /workspace/coverage/default/107.usbdev_endpoint_types.4191823913
Short name T549
Test name
Test status
Simulation time 327375741 ps
CPU time 1.18 seconds
Started Aug 11 07:16:50 PM PDT 24
Finished Aug 11 07:16:52 PM PDT 24
Peak memory 207736 kb
Host smart-e6543340-342a-4300-b284-a2b183174f0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4191823913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.4191823913
Directory /workspace/107.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/108.usbdev_endpoint_types.4149812440
Short name T421
Test name
Test status
Simulation time 583418913 ps
CPU time 1.58 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207568 kb
Host smart-100e2f38-6a54-4070-8052-2ab52472c8c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4149812440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.4149812440
Directory /workspace/108.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/115.usbdev_endpoint_types.15243276
Short name T513
Test name
Test status
Simulation time 354312162 ps
CPU time 1.18 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207444 kb
Host smart-82d892a2-3ac6-4407-841a-eec16a8f5d29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=15243276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.15243276
Directory /workspace/115.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/118.usbdev_tx_rx_disruption.1658693279
Short name T393
Test name
Test status
Simulation time 536819956 ps
CPU time 1.49 seconds
Started Aug 11 07:17:04 PM PDT 24
Finished Aug 11 07:17:06 PM PDT 24
Peak memory 207572 kb
Host smart-020fd1b0-23ca-4bfe-949b-0510a88359b3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658693279 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.usbdev_tx_rx_disruption.1658693279
Directory /workspace/118.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/16.usbdev_invalid_sync.1566966289
Short name T400
Test name
Test status
Simulation time 5061257617 ps
CPU time 52.12 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 224220 kb
Host smart-8c4ed66a-637c-4c92-9a51-57dbbb4ed6e1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1566966289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1566966289
Directory /workspace/16.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/177.usbdev_endpoint_types.3040338599
Short name T423
Test name
Test status
Simulation time 393859201 ps
CPU time 1.24 seconds
Started Aug 11 07:17:17 PM PDT 24
Finished Aug 11 07:17:18 PM PDT 24
Peak memory 207516 kb
Host smart-f39b9775-c3b4-4c02-9343-95f51f38cf38
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3040338599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.3040338599
Directory /workspace/177.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/18.usbdev_rx_full.3117805416
Short name T343
Test name
Test status
Simulation time 259454896 ps
CPU time 1.16 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:06 PM PDT 24
Peak memory 207548 kb
Host smart-bea94c88-8946-4409-ac9a-0d2988ad4889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31178
05416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.3117805416
Directory /workspace/18.usbdev_rx_full/latest


Test location /workspace/coverage/default/189.usbdev_endpoint_types.3774243534
Short name T528
Test name
Test status
Simulation time 742054415 ps
CPU time 1.94 seconds
Started Aug 11 07:17:28 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207540 kb
Host smart-bcc563ea-3300-42af-a0d1-054788757344
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3774243534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.3774243534
Directory /workspace/189.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/195.usbdev_endpoint_types.27935662
Short name T551
Test name
Test status
Simulation time 235940386 ps
CPU time 1.04 seconds
Started Aug 11 07:17:30 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 207448 kb
Host smart-b97db97e-88fd-429c-ab4b-bf4f6764e5fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=27935662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.27935662
Directory /workspace/195.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/21.usbdev_endpoint_types.3761435008
Short name T485
Test name
Test status
Simulation time 501088400 ps
CPU time 1.38 seconds
Started Aug 11 07:12:24 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 207472 kb
Host smart-4705c06d-7c8c-485c-9edc-782467f2e98c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3761435008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.3761435008
Directory /workspace/21.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/24.usbdev_rx_full.1430610249
Short name T339
Test name
Test status
Simulation time 291753393 ps
CPU time 1.12 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207572 kb
Host smart-fc377f39-7ec6-4178-8049-33500bb75cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14306
10249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.1430610249
Directory /workspace/24.usbdev_rx_full/latest


Test location /workspace/coverage/default/26.usbdev_endpoint_types.3245231222
Short name T492
Test name
Test status
Simulation time 513413997 ps
CPU time 1.34 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207500 kb
Host smart-554745e6-b220-45bc-9e06-f0fe04522967
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3245231222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.3245231222
Directory /workspace/26.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/39.usbdev_endpoint_types.1549312820
Short name T432
Test name
Test status
Simulation time 691627943 ps
CPU time 1.75 seconds
Started Aug 11 07:14:57 PM PDT 24
Finished Aug 11 07:14:59 PM PDT 24
Peak memory 207544 kb
Host smart-3ebb4976-3cf2-4839-8de8-03668395c1e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1549312820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.1549312820
Directory /workspace/39.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/55.usbdev_endpoint_types.2536598946
Short name T470
Test name
Test status
Simulation time 453004296 ps
CPU time 1.28 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:16:36 PM PDT 24
Peak memory 207480 kb
Host smart-d1639f19-b632-4344-99de-b43c3c5316e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2536598946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.2536598946
Directory /workspace/55.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/85.usbdev_endpoint_types.574946525
Short name T436
Test name
Test status
Simulation time 825541431 ps
CPU time 1.81 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207548 kb
Host smart-06ae8023-bcb3-46fa-945c-b4c6ef384c07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=574946525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.574946525
Directory /workspace/85.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2422967277
Short name T113
Test name
Test status
Simulation time 152846634 ps
CPU time 0.89 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:12:46 PM PDT 24
Peak memory 207548 kb
Host smart-070a7344-9380-44ca-887a-23c2793cda66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24229
67277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2422967277
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/119.usbdev_tx_rx_disruption.26392527
Short name T260
Test name
Test status
Simulation time 579091585 ps
CPU time 1.53 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207568 kb
Host smart-ccd258fd-2a32-4e33-9311-f3e2fa60f7e4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26392527 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 119.usbdev_tx_rx_disruption.26392527
Directory /workspace/119.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/13.usbdev_link_resume.3860858494
Short name T3539
Test name
Test status
Simulation time 12142481194 ps
CPU time 16.49 seconds
Started Aug 11 07:11:09 PM PDT 24
Finished Aug 11 07:11:25 PM PDT 24
Peak memory 207772 kb
Host smart-99b3eb16-28d0-4855-9537-bca6763cac2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38608
58494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3860858494
Directory /workspace/13.usbdev_link_resume/latest


Test location /workspace/coverage/default/129.usbdev_tx_rx_disruption.3541664650
Short name T98
Test name
Test status
Simulation time 455504679 ps
CPU time 1.57 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207572 kb
Host smart-12c52d03-4efa-4aa6-8feb-eb23c9b82ee2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541664650 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.usbdev_tx_rx_disruption.3541664650
Directory /workspace/129.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/2.usbdev_av_overflow.2738198926
Short name T64
Test name
Test status
Simulation time 134307042 ps
CPU time 0.87 seconds
Started Aug 11 07:08:57 PM PDT 24
Finished Aug 11 07:08:58 PM PDT 24
Peak memory 207732 kb
Host smart-97543bb6-d1ac-43de-bae6-3a665dfaa2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27381
98926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2738198926
Directory /workspace/2.usbdev_av_overflow/latest


Test location /workspace/coverage/default/20.usbdev_device_address.1500144734
Short name T389
Test name
Test status
Simulation time 38907827887 ps
CPU time 67.58 seconds
Started Aug 11 07:12:21 PM PDT 24
Finished Aug 11 07:13:28 PM PDT 24
Peak memory 207780 kb
Host smart-25b04801-4c48-4517-bb26-19f46f06b14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15001
44734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.1500144734
Directory /workspace/20.usbdev_device_address/latest


Test location /workspace/coverage/default/0.usbdev_av_empty.133785157
Short name T58
Test name
Test status
Simulation time 236639485 ps
CPU time 1.07 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:32 PM PDT 24
Peak memory 207476 kb
Host smart-514cfda4-d050-451b-a453-2b208892fd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13378
5157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.133785157
Directory /workspace/0.usbdev_av_empty/latest


Test location /workspace/coverage/default/0.usbdev_host_lost.1252994188
Short name T67
Test name
Test status
Simulation time 4160491520 ps
CPU time 9.89 seconds
Started Aug 11 07:08:26 PM PDT 24
Finished Aug 11 07:08:36 PM PDT 24
Peak memory 207828 kb
Host smart-d4a7cae6-e543-4d56-ae73-3117654309a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12529
94188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1252994188
Directory /workspace/0.usbdev_host_lost/latest


Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.983388659
Short name T73
Test name
Test status
Simulation time 393687837 ps
CPU time 1.4 seconds
Started Aug 11 07:08:28 PM PDT 24
Finished Aug 11 07:08:30 PM PDT 24
Peak memory 207100 kb
Host smart-bf062eba-fa5b-4b5a-8ee7-18e1804ee9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98338
8659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.983388659
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest


Test location /workspace/coverage/default/0.usbdev_link_reset.1554450171
Short name T68
Test name
Test status
Simulation time 207331340 ps
CPU time 0.92 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:32 PM PDT 24
Peak memory 207520 kb
Host smart-a3623e65-3d90-4496-82fc-0ec5a1fc464f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15544
50171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1554450171
Directory /workspace/0.usbdev_link_reset/latest


Test location /workspace/coverage/default/0.usbdev_rx_pid_err.4247484278
Short name T2942
Test name
Test status
Simulation time 209364223 ps
CPU time 0.96 seconds
Started Aug 11 07:08:34 PM PDT 24
Finished Aug 11 07:08:35 PM PDT 24
Peak memory 207516 kb
Host smart-e9749f82-b21c-4b82-8342-7121ad934af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42474
84278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.4247484278
Directory /workspace/0.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/1.usbdev_av_empty.894986780
Short name T50
Test name
Test status
Simulation time 162763527 ps
CPU time 0.91 seconds
Started Aug 11 07:08:36 PM PDT 24
Finished Aug 11 07:08:37 PM PDT 24
Peak memory 207528 kb
Host smart-b5577c9c-b943-4a3b-93bc-67a6835e759f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89498
6780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.894986780
Directory /workspace/1.usbdev_av_empty/latest


Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3292049577
Short name T3227
Test name
Test status
Simulation time 3225175101 ps
CPU time 24.63 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:09:40 PM PDT 24
Peak memory 224284 kb
Host smart-60b63dd1-75ad-4f01-8209-4234fefaeea6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292049577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3292049577
Directory /workspace/3.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1164123116
Short name T279
Test name
Test status
Simulation time 160387764 ps
CPU time 2.24 seconds
Started Aug 11 06:21:05 PM PDT 24
Finished Aug 11 06:21:08 PM PDT 24
Peak memory 206988 kb
Host smart-cd3d48c7-f99d-4b99-92b5-50759775c448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1164123116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1164123116
Directory /workspace/0.usbdev_tl_errors/latest


Test location /workspace/coverage/default/0.usbdev_nak_trans.1360659526
Short name T138
Test name
Test status
Simulation time 215950685 ps
CPU time 1 seconds
Started Aug 11 07:08:26 PM PDT 24
Finished Aug 11 07:08:27 PM PDT 24
Peak memory 207548 kb
Host smart-e533702b-dce4-42e6-843d-b0bfe258aeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13606
59526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1360659526
Directory /workspace/0.usbdev_nak_trans/latest


Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.1090754860
Short name T86
Test name
Test status
Simulation time 3298408155 ps
CPU time 18.83 seconds
Started Aug 11 07:08:30 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 218352 kb
Host smart-5a362578-fb5b-49a1-8515-423f4cc4225d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090754860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.1090754860
Directory /workspace/0.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/1.usbdev_iso_retraction.413163119
Short name T720
Test name
Test status
Simulation time 9733855626 ps
CPU time 61.72 seconds
Started Aug 11 07:08:37 PM PDT 24
Finished Aug 11 07:09:39 PM PDT 24
Peak memory 207884 kb
Host smart-c2bad9c6-ae89-4a3c-b44e-1c2829c7e451
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=413163119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.413163119
Directory /workspace/1.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2043007863
Short name T388
Test name
Test status
Simulation time 4119453711 ps
CPU time 121.56 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:10:46 PM PDT 24
Peak memory 216088 kb
Host smart-2e5a59cd-c11b-4425-9a53-023a3905fd9d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2043007863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2043007863
Directory /workspace/1.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/107.usbdev_tx_rx_disruption.140386341
Short name T201
Test name
Test status
Simulation time 627728750 ps
CPU time 1.72 seconds
Started Aug 11 07:16:58 PM PDT 24
Finished Aug 11 07:17:00 PM PDT 24
Peak memory 207564 kb
Host smart-76055380-5f2e-4e82-9ed6-8aa779839d65
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140386341 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 107.usbdev_tx_rx_disruption.140386341
Directory /workspace/107.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/11.usbdev_fifo_rst.691305838
Short name T214
Test name
Test status
Simulation time 379546203 ps
CPU time 2.83 seconds
Started Aug 11 07:10:43 PM PDT 24
Finished Aug 11 07:10:46 PM PDT 24
Peak memory 207624 kb
Host smart-1eed9aea-d84d-4775-8346-21cbac20ff24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69130
5838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.691305838
Directory /workspace/11.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/11.usbdev_nak_trans.623062910
Short name T3269
Test name
Test status
Simulation time 172476266 ps
CPU time 0.87 seconds
Started Aug 11 07:10:48 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207504 kb
Host smart-c643e98e-d9c6-4d0f-911c-8e16989926b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62306
2910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.623062910
Directory /workspace/11.usbdev_nak_trans/latest


Test location /workspace/coverage/default/113.usbdev_tx_rx_disruption.82593430
Short name T2002
Test name
Test status
Simulation time 522626768 ps
CPU time 1.5 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:03 PM PDT 24
Peak memory 207524 kb
Host smart-a4a05563-32e2-45fd-82b2-6885d5155e67
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82593430 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 113.usbdev_tx_rx_disruption.82593430
Directory /workspace/113.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/13.usbdev_nak_trans.1516071345
Short name T143
Test name
Test status
Simulation time 237321868 ps
CPU time 0.97 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207552 kb
Host smart-5761df94-246b-4739-adf4-22122891af75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15160
71345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1516071345
Directory /workspace/13.usbdev_nak_trans/latest


Test location /workspace/coverage/default/138.usbdev_tx_rx_disruption.2167019081
Short name T1581
Test name
Test status
Simulation time 426097359 ps
CPU time 1.36 seconds
Started Aug 11 07:17:09 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207556 kb
Host smart-b17f0df4-7b9c-473d-9686-1fae9092e632
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167019081 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.usbdev_tx_rx_disruption.2167019081
Directory /workspace/138.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/15.usbdev_nak_trans.1502818386
Short name T1792
Test name
Test status
Simulation time 241962053 ps
CPU time 1.02 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:31 PM PDT 24
Peak memory 207488 kb
Host smart-cfd1ec4b-2e65-4323-9b99-e4c96f5beb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15028
18386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1502818386
Directory /workspace/15.usbdev_nak_trans/latest


Test location /workspace/coverage/default/16.usbdev_nak_trans.2284092366
Short name T144
Test name
Test status
Simulation time 228393684 ps
CPU time 1.03 seconds
Started Aug 11 07:11:43 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 207532 kb
Host smart-ca6fde2c-77d0-45be-baed-7c99ee653a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22840
92366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2284092366
Directory /workspace/16.usbdev_nak_trans/latest


Test location /workspace/coverage/default/2.usbdev_nak_trans.2133422567
Short name T148
Test name
Test status
Simulation time 239483888 ps
CPU time 1.01 seconds
Started Aug 11 07:09:03 PM PDT 24
Finished Aug 11 07:09:04 PM PDT 24
Peak memory 207496 kb
Host smart-a35e6fb2-6535-4162-a232-1a8f26a023a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21334
22567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2133422567
Directory /workspace/2.usbdev_nak_trans/latest


Test location /workspace/coverage/default/25.usbdev_nak_trans.618832177
Short name T2802
Test name
Test status
Simulation time 219165118 ps
CPU time 0.97 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:04 PM PDT 24
Peak memory 207516 kb
Host smart-aa0906db-c976-4f3d-8c7b-8dbefeb07b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61883
2177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.618832177
Directory /workspace/25.usbdev_nak_trans/latest


Test location /workspace/coverage/default/38.usbdev_nak_trans.3928165574
Short name T147
Test name
Test status
Simulation time 176665417 ps
CPU time 0.88 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207516 kb
Host smart-f4792b77-9f0d-4175-81a0-4ba09a02f94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39281
65574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3928165574
Directory /workspace/38.usbdev_nak_trans/latest


Test location /workspace/coverage/default/42.usbdev_nak_trans.3873869401
Short name T139
Test name
Test status
Simulation time 235154022 ps
CPU time 0.98 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:40 PM PDT 24
Peak memory 207516 kb
Host smart-6fa417d1-bc84-464a-bd0f-ea6ce40b098e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38738
69401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3873869401
Directory /workspace/42.usbdev_nak_trans/latest


Test location /workspace/coverage/default/48.usbdev_nak_trans.3909384283
Short name T154
Test name
Test status
Simulation time 203740743 ps
CPU time 0.93 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207564 kb
Host smart-6d78ca2e-bf98-4f56-9c26-216ec3dbf50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39093
84283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3909384283
Directory /workspace/48.usbdev_nak_trans/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.824801042
Short name T3694
Test name
Test status
Simulation time 97448234 ps
CPU time 1.88 seconds
Started Aug 11 06:21:05 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 206808 kb
Host smart-d70069cd-6b34-4acd-9477-49542990fb51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=824801042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.824801042
Directory /workspace/0.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2455100156
Short name T3731
Test name
Test status
Simulation time 910576927 ps
CPU time 9.08 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 206912 kb
Host smart-8c72e8fb-0da3-4a7b-b188-7de0eb9b2d91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2455100156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2455100156
Directory /workspace/0.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3565841453
Short name T3642
Test name
Test status
Simulation time 140481375 ps
CPU time 0.95 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 206592 kb
Host smart-446a020c-66c8-44b6-8bfa-b1a708e59f11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3565841453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3565841453
Directory /workspace/0.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.4241742792
Short name T367
Test name
Test status
Simulation time 61967107 ps
CPU time 0.73 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 206588 kb
Host smart-154c3e73-857f-4d60-8fb1-8f772f0a2c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4241742792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.4241742792
Directory /workspace/0.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.710556883
Short name T310
Test name
Test status
Simulation time 170652078 ps
CPU time 2.41 seconds
Started Aug 11 06:21:02 PM PDT 24
Finished Aug 11 06:21:05 PM PDT 24
Peak memory 215116 kb
Host smart-1301159c-e246-4b41-ae84-6d033beac281
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=710556883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.710556883
Directory /workspace/0.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3303106442
Short name T3670
Test name
Test status
Simulation time 260099874 ps
CPU time 2.61 seconds
Started Aug 11 06:21:05 PM PDT 24
Finished Aug 11 06:21:08 PM PDT 24
Peak memory 206784 kb
Host smart-7d5e26f3-73f5-4cc9-872b-4fddbbdedc02
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3303106442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3303106442
Directory /workspace/0.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1106491788
Short name T331
Test name
Test status
Simulation time 156899146 ps
CPU time 1.18 seconds
Started Aug 11 06:21:04 PM PDT 24
Finished Aug 11 06:21:05 PM PDT 24
Peak memory 206780 kb
Host smart-79c67da1-122d-4bb8-88c3-92b14fb5f935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1106491788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1106491788
Directory /workspace/0.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3640074511
Short name T3668
Test name
Test status
Simulation time 580864153 ps
CPU time 2.74 seconds
Started Aug 11 06:21:04 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 206928 kb
Host smart-cb4d492b-272c-43c8-8537-b0ddb36abfcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3640074511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3640074511
Directory /workspace/0.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2738753456
Short name T3646
Test name
Test status
Simulation time 141279078 ps
CPU time 3.22 seconds
Started Aug 11 06:21:07 PM PDT 24
Finished Aug 11 06:21:10 PM PDT 24
Peak memory 206980 kb
Host smart-dde5c59f-14c1-40b3-a8f7-16d59599c4f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2738753456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2738753456
Directory /workspace/1.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4029625614
Short name T3690
Test name
Test status
Simulation time 1291141040 ps
CPU time 6.01 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 206872 kb
Host smart-0663053d-2d98-47da-a8a9-da6fa1549daa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4029625614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.4029625614
Directory /workspace/1.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3966465849
Short name T3683
Test name
Test status
Simulation time 182277728 ps
CPU time 1.04 seconds
Started Aug 11 06:21:07 PM PDT 24
Finished Aug 11 06:21:08 PM PDT 24
Peak memory 206756 kb
Host smart-b78bca6b-d58a-47cd-aeaa-db9eb722d01c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3966465849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3966465849
Directory /workspace/1.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1695992530
Short name T3729
Test name
Test status
Simulation time 99665064 ps
CPU time 1.34 seconds
Started Aug 11 06:21:14 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 215004 kb
Host smart-a7329b75-6594-408a-9e56-3e81b68aa4eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695992530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1695992530
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.616897322
Short name T3733
Test name
Test status
Simulation time 95234593 ps
CPU time 0.88 seconds
Started Aug 11 06:21:05 PM PDT 24
Finished Aug 11 06:21:06 PM PDT 24
Peak memory 206592 kb
Host smart-125b2fea-db1e-4bc0-b8f1-089cd06938a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=616897322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.616897322
Directory /workspace/1.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3464355740
Short name T3712
Test name
Test status
Simulation time 128655812 ps
CPU time 1.42 seconds
Started Aug 11 06:21:06 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 215112 kb
Host smart-58c1d44e-8311-4831-a56b-1d6025fdd328
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3464355740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3464355740
Directory /workspace/1.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1959816017
Short name T3659
Test name
Test status
Simulation time 140417120 ps
CPU time 2.38 seconds
Started Aug 11 06:21:05 PM PDT 24
Finished Aug 11 06:21:07 PM PDT 24
Peak memory 206852 kb
Host smart-465b3463-75de-4db4-8191-fefc69c1c614
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1959816017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1959816017
Directory /workspace/1.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2378437944
Short name T312
Test name
Test status
Simulation time 114934923 ps
CPU time 1.11 seconds
Started Aug 11 06:21:08 PM PDT 24
Finished Aug 11 06:21:09 PM PDT 24
Peak memory 206892 kb
Host smart-8b75d4b1-813a-4c47-9bea-0509491ae55e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2378437944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2378437944
Directory /workspace/1.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1196077034
Short name T3738
Test name
Test status
Simulation time 115316966 ps
CPU time 3.18 seconds
Started Aug 11 06:21:07 PM PDT 24
Finished Aug 11 06:21:10 PM PDT 24
Peak memory 223156 kb
Host smart-ec059449-c0ef-4c57-80e5-207702f1df24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1196077034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1196077034
Directory /workspace/1.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.100457559
Short name T272
Test name
Test status
Simulation time 1272567936 ps
CPU time 4.6 seconds
Started Aug 11 06:21:07 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 206936 kb
Host smart-4f3cb639-dc89-449f-9c06-f5bace7f60b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=100457559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.100457559
Directory /workspace/1.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.943442286
Short name T3678
Test name
Test status
Simulation time 57540913 ps
CPU time 1.29 seconds
Started Aug 11 06:21:22 PM PDT 24
Finished Aug 11 06:21:24 PM PDT 24
Peak memory 215176 kb
Host smart-e2c93da2-b9b2-4e9f-a140-31205fe5c8bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943442286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.943442286
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3622224517
Short name T3686
Test name
Test status
Simulation time 77178232 ps
CPU time 0.86 seconds
Started Aug 11 06:21:27 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 206740 kb
Host smart-5981f6e4-dd38-465e-b3b0-e180f4c4647a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3622224517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3622224517
Directory /workspace/10.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3334839862
Short name T3698
Test name
Test status
Simulation time 40406501 ps
CPU time 0.69 seconds
Started Aug 11 06:21:27 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 206588 kb
Host smart-eb807a47-5971-4038-b21f-369e4f50e4cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3334839862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3334839862
Directory /workspace/10.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3348374968
Short name T3714
Test name
Test status
Simulation time 111547411 ps
CPU time 1.13 seconds
Started Aug 11 06:21:20 PM PDT 24
Finished Aug 11 06:21:21 PM PDT 24
Peak memory 206792 kb
Host smart-85a0a742-e325-4142-b582-e1beaf7f98ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3348374968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3348374968
Directory /workspace/10.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2233194464
Short name T3719
Test name
Test status
Simulation time 145883051 ps
CPU time 1.68 seconds
Started Aug 11 06:21:23 PM PDT 24
Finished Aug 11 06:21:25 PM PDT 24
Peak memory 206972 kb
Host smart-f762bca4-b30d-46d0-b5c2-5ef944965248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2233194464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2233194464
Directory /workspace/10.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1609628176
Short name T3653
Test name
Test status
Simulation time 96843796 ps
CPU time 1.25 seconds
Started Aug 11 06:21:23 PM PDT 24
Finished Aug 11 06:21:24 PM PDT 24
Peak memory 223304 kb
Host smart-b5d9713d-455d-4137-a658-e5983370981d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609628176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1609628176
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3863916371
Short name T3637
Test name
Test status
Simulation time 115841963 ps
CPU time 0.9 seconds
Started Aug 11 06:21:21 PM PDT 24
Finished Aug 11 06:21:22 PM PDT 24
Peak memory 206656 kb
Host smart-9f4a3882-2c95-4954-9d2f-ace45c51021d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3863916371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3863916371
Directory /workspace/11.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3818122190
Short name T3667
Test name
Test status
Simulation time 68239164 ps
CPU time 0.77 seconds
Started Aug 11 06:21:26 PM PDT 24
Finished Aug 11 06:21:26 PM PDT 24
Peak memory 206604 kb
Host smart-07bc1880-0f26-4a48-959b-61f5f43d474e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3818122190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3818122190
Directory /workspace/11.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.549284342
Short name T316
Test name
Test status
Simulation time 111808229 ps
CPU time 1.09 seconds
Started Aug 11 06:21:21 PM PDT 24
Finished Aug 11 06:21:22 PM PDT 24
Peak memory 206988 kb
Host smart-9179a634-7f9e-4d91-aa47-724890e92d55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=549284342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.549284342
Directory /workspace/11.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1349336592
Short name T3643
Test name
Test status
Simulation time 158639831 ps
CPU time 2.22 seconds
Started Aug 11 06:21:26 PM PDT 24
Finished Aug 11 06:21:29 PM PDT 24
Peak memory 206896 kb
Host smart-652f4b52-3de2-43ac-bf8f-2a342dbef7ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1349336592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1349336592
Directory /workspace/11.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1961206442
Short name T3691
Test name
Test status
Simulation time 110077268 ps
CPU time 1.41 seconds
Started Aug 11 06:21:27 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 215176 kb
Host smart-28f4fcb7-e2ea-4b4d-b51f-857ef5d85bcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961206442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1961206442
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.251985343
Short name T3704
Test name
Test status
Simulation time 57306726 ps
CPU time 1.01 seconds
Started Aug 11 06:21:24 PM PDT 24
Finished Aug 11 06:21:25 PM PDT 24
Peak memory 206760 kb
Host smart-c4894727-51f2-42fa-a8ea-cd69c0325c3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=251985343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.251985343
Directory /workspace/12.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1388354802
Short name T335
Test name
Test status
Simulation time 47090965 ps
CPU time 0.72 seconds
Started Aug 11 06:21:22 PM PDT 24
Finished Aug 11 06:21:23 PM PDT 24
Peak memory 206564 kb
Host smart-2dcb61dd-fc7e-4fe7-906d-4b6ee85fd63b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1388354802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1388354802
Directory /workspace/12.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3747187737
Short name T3681
Test name
Test status
Simulation time 246673823 ps
CPU time 1.66 seconds
Started Aug 11 06:21:22 PM PDT 24
Finished Aug 11 06:21:23 PM PDT 24
Peak memory 206884 kb
Host smart-0cea837b-47f8-487f-813f-c76b68b87827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3747187737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3747187737
Directory /workspace/12.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3872585911
Short name T3651
Test name
Test status
Simulation time 160467437 ps
CPU time 1.65 seconds
Started Aug 11 06:21:24 PM PDT 24
Finished Aug 11 06:21:26 PM PDT 24
Peak memory 206936 kb
Host smart-ce41d0fe-ff26-4cd3-bdbd-97237e4e104b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3872585911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3872585911
Directory /workspace/12.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3706998505
Short name T273
Test name
Test status
Simulation time 496494186 ps
CPU time 2.71 seconds
Started Aug 11 06:21:27 PM PDT 24
Finished Aug 11 06:21:30 PM PDT 24
Peak memory 207008 kb
Host smart-8c01b6bf-738e-4c6a-a33d-0d1bfe9da340
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3706998505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3706998505
Directory /workspace/12.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2683695735
Short name T3713
Test name
Test status
Simulation time 71945051 ps
CPU time 1.66 seconds
Started Aug 11 06:21:21 PM PDT 24
Finished Aug 11 06:21:23 PM PDT 24
Peak memory 215156 kb
Host smart-6766ab6c-319f-4202-ae21-985330654e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683695735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2683695735
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.248239356
Short name T3696
Test name
Test status
Simulation time 101814798 ps
CPU time 0.78 seconds
Started Aug 11 06:21:27 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 206548 kb
Host smart-b4a1f773-47e6-4a2d-9d4a-2fb49d3f513b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=248239356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.248239356
Directory /workspace/13.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2623336865
Short name T3645
Test name
Test status
Simulation time 149262830 ps
CPU time 1.85 seconds
Started Aug 11 06:21:26 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 206976 kb
Host smart-d1b3d274-2d16-4ea0-a171-0b26cc6e5ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2623336865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2623336865
Directory /workspace/13.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.556754205
Short name T269
Test name
Test status
Simulation time 211431874 ps
CPU time 2.49 seconds
Started Aug 11 06:21:26 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 206944 kb
Host smart-4226d708-4710-4dc9-8707-30b5c4bd836c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=556754205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.556754205
Directory /workspace/13.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1538316456
Short name T382
Test name
Test status
Simulation time 1275208259 ps
CPU time 5.6 seconds
Started Aug 11 06:21:23 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 206952 kb
Host smart-b43d7843-dc6e-46aa-9d2f-efbbf58e8cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1538316456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1538316456
Directory /workspace/13.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3988461595
Short name T3730
Test name
Test status
Simulation time 109716340 ps
CPU time 1.88 seconds
Started Aug 11 06:21:23 PM PDT 24
Finished Aug 11 06:21:25 PM PDT 24
Peak memory 215244 kb
Host smart-165b064b-7ec9-4d00-83e1-fcb2f531db8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988461595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3988461595
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3058503322
Short name T305
Test name
Test status
Simulation time 74001030 ps
CPU time 0.99 seconds
Started Aug 11 06:21:24 PM PDT 24
Finished Aug 11 06:21:25 PM PDT 24
Peak memory 206700 kb
Host smart-1caaef9e-999a-4949-81c6-9aa47de27c83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3058503322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3058503322
Directory /workspace/14.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1625039856
Short name T3673
Test name
Test status
Simulation time 53192581 ps
CPU time 0.76 seconds
Started Aug 11 06:21:22 PM PDT 24
Finished Aug 11 06:21:23 PM PDT 24
Peak memory 206604 kb
Host smart-286c1deb-3768-40df-b54a-0635e3ea8e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1625039856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1625039856
Directory /workspace/14.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.222154915
Short name T3674
Test name
Test status
Simulation time 79179346 ps
CPU time 1.15 seconds
Started Aug 11 06:21:21 PM PDT 24
Finished Aug 11 06:21:23 PM PDT 24
Peak memory 207000 kb
Host smart-6fd7abef-b76d-4a17-a715-91d22338e35d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=222154915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.222154915
Directory /workspace/14.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2130009683
Short name T223
Test name
Test status
Simulation time 178661114 ps
CPU time 1.98 seconds
Started Aug 11 06:21:22 PM PDT 24
Finished Aug 11 06:21:24 PM PDT 24
Peak memory 206804 kb
Host smart-d13688e0-3e2f-41e5-abf1-8b17faf8a53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2130009683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2130009683
Directory /workspace/14.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.774223201
Short name T328
Test name
Test status
Simulation time 462254681 ps
CPU time 3.12 seconds
Started Aug 11 06:21:27 PM PDT 24
Finished Aug 11 06:21:30 PM PDT 24
Peak memory 206880 kb
Host smart-b999cd10-9e91-41e5-a8de-38bbe7c36db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=774223201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.774223201
Directory /workspace/14.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.546332682
Short name T332
Test name
Test status
Simulation time 167802787 ps
CPU time 2.05 seconds
Started Aug 11 06:21:32 PM PDT 24
Finished Aug 11 06:21:34 PM PDT 24
Peak memory 215144 kb
Host smart-e5d7c6b7-816f-4cbd-8c49-d09b6034a5ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546332682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.546332682
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2956164166
Short name T263
Test name
Test status
Simulation time 32509748 ps
CPU time 0.86 seconds
Started Aug 11 06:21:29 PM PDT 24
Finished Aug 11 06:21:30 PM PDT 24
Peak memory 206868 kb
Host smart-994e948c-d90d-4686-b648-4345b90c302b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2956164166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2956164166
Directory /workspace/15.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1309070309
Short name T3679
Test name
Test status
Simulation time 34091093 ps
CPU time 0.71 seconds
Started Aug 11 06:21:32 PM PDT 24
Finished Aug 11 06:21:33 PM PDT 24
Peak memory 206604 kb
Host smart-b76d6233-77e6-4ca0-b83e-54c24a01dfca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1309070309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1309070309
Directory /workspace/15.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.54562208
Short name T3652
Test name
Test status
Simulation time 178882398 ps
CPU time 1.56 seconds
Started Aug 11 06:21:32 PM PDT 24
Finished Aug 11 06:21:33 PM PDT 24
Peak memory 206796 kb
Host smart-cca3a467-ef7f-4a68-a06d-c123819199a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=54562208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.54562208
Directory /workspace/15.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3067818471
Short name T3740
Test name
Test status
Simulation time 149386339 ps
CPU time 2.85 seconds
Started Aug 11 06:21:31 PM PDT 24
Finished Aug 11 06:21:34 PM PDT 24
Peak memory 223156 kb
Host smart-01e09f50-a6c1-4a89-b563-0b19daf09c28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3067818471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3067818471
Directory /workspace/15.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2895535455
Short name T375
Test name
Test status
Simulation time 953205171 ps
CPU time 4.88 seconds
Started Aug 11 06:21:30 PM PDT 24
Finished Aug 11 06:21:35 PM PDT 24
Peak memory 206964 kb
Host smart-5ef79637-fd6b-485f-8dae-3af1251cbedf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2895535455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2895535455
Directory /workspace/15.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.130896977
Short name T3700
Test name
Test status
Simulation time 188739949 ps
CPU time 1.65 seconds
Started Aug 11 06:21:29 PM PDT 24
Finished Aug 11 06:21:31 PM PDT 24
Peak memory 215304 kb
Host smart-55112af1-90eb-4ce0-8e67-88d79822e12f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130896977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.130896977
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2916371555
Short name T311
Test name
Test status
Simulation time 96296361 ps
CPU time 0.92 seconds
Started Aug 11 06:21:30 PM PDT 24
Finished Aug 11 06:21:31 PM PDT 24
Peak memory 206752 kb
Host smart-e55dd4bf-d7ca-4707-9606-e36337d4ef27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2916371555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2916371555
Directory /workspace/16.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2002551369
Short name T3661
Test name
Test status
Simulation time 58351940 ps
CPU time 0.76 seconds
Started Aug 11 06:21:29 PM PDT 24
Finished Aug 11 06:21:30 PM PDT 24
Peak memory 206624 kb
Host smart-c7355ec7-ecdc-4a91-8d70-c78d6808b2b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2002551369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2002551369
Directory /workspace/16.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1788904815
Short name T3636
Test name
Test status
Simulation time 81014638 ps
CPU time 1.1 seconds
Started Aug 11 06:21:30 PM PDT 24
Finished Aug 11 06:21:32 PM PDT 24
Peak memory 206968 kb
Host smart-6f15ce6b-8afa-4cb9-bf36-7503dbcb206c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1788904815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1788904815
Directory /workspace/16.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2174939914
Short name T3709
Test name
Test status
Simulation time 75591706 ps
CPU time 1.69 seconds
Started Aug 11 06:21:29 PM PDT 24
Finished Aug 11 06:21:31 PM PDT 24
Peak memory 206884 kb
Host smart-d52be374-2746-4fbf-9611-a873b244b719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2174939914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2174939914
Directory /workspace/16.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3423661925
Short name T383
Test name
Test status
Simulation time 533199601 ps
CPU time 4.5 seconds
Started Aug 11 06:21:28 PM PDT 24
Finished Aug 11 06:21:33 PM PDT 24
Peak memory 206928 kb
Host smart-240578e9-6c29-4b83-97ec-7d30753aaa95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3423661925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3423661925
Directory /workspace/16.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1682223559
Short name T224
Test name
Test status
Simulation time 95485196 ps
CPU time 1.59 seconds
Started Aug 11 06:21:30 PM PDT 24
Finished Aug 11 06:21:32 PM PDT 24
Peak memory 215184 kb
Host smart-2b6c1936-dc9a-4129-aa60-29126ce25804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682223559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1682223559
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.447838195
Short name T3647
Test name
Test status
Simulation time 43362763 ps
CPU time 0.82 seconds
Started Aug 11 06:21:29 PM PDT 24
Finished Aug 11 06:21:30 PM PDT 24
Peak memory 206644 kb
Host smart-bbbce445-22b1-4cc3-a6db-c57d06eea928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=447838195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.447838195
Directory /workspace/17.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.301093861
Short name T334
Test name
Test status
Simulation time 42496036 ps
CPU time 0.74 seconds
Started Aug 11 06:21:41 PM PDT 24
Finished Aug 11 06:21:42 PM PDT 24
Peak memory 206600 kb
Host smart-dda16185-5b58-4254-97c5-11602196acb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=301093861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.301093861
Directory /workspace/17.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3802660407
Short name T3680
Test name
Test status
Simulation time 184115803 ps
CPU time 1.61 seconds
Started Aug 11 06:21:31 PM PDT 24
Finished Aug 11 06:21:33 PM PDT 24
Peak memory 206928 kb
Host smart-33d8404f-0edd-4133-91a9-494e466e20f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3802660407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3802660407
Directory /workspace/17.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3876190082
Short name T3715
Test name
Test status
Simulation time 86245852 ps
CPU time 2.26 seconds
Started Aug 11 06:21:32 PM PDT 24
Finished Aug 11 06:21:34 PM PDT 24
Peak memory 206844 kb
Host smart-7662f7ae-8dc9-4a5c-a72c-5b2e9ab07f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3876190082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3876190082
Directory /workspace/17.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3180205475
Short name T3703
Test name
Test status
Simulation time 80181054 ps
CPU time 1.22 seconds
Started Aug 11 06:21:28 PM PDT 24
Finished Aug 11 06:21:30 PM PDT 24
Peak memory 214888 kb
Host smart-798e706d-b17c-4217-8451-39399cdb4cdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180205475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3180205475
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4034146324
Short name T3718
Test name
Test status
Simulation time 144211233 ps
CPU time 1.09 seconds
Started Aug 11 06:21:31 PM PDT 24
Finished Aug 11 06:21:32 PM PDT 24
Peak memory 206732 kb
Host smart-449793a9-5efb-4df3-ba0d-9b0ffab83b30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4034146324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4034146324
Directory /workspace/18.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.436215827
Short name T3655
Test name
Test status
Simulation time 37232680 ps
CPU time 0.73 seconds
Started Aug 11 06:21:30 PM PDT 24
Finished Aug 11 06:21:31 PM PDT 24
Peak memory 206516 kb
Host smart-e7d24c56-9fd1-478f-8689-44c8ecf724c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=436215827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.436215827
Directory /workspace/18.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3547426171
Short name T314
Test name
Test status
Simulation time 236702624 ps
CPU time 1.68 seconds
Started Aug 11 06:21:30 PM PDT 24
Finished Aug 11 06:21:32 PM PDT 24
Peak memory 206908 kb
Host smart-f4ee3a00-be6d-461c-b592-443b85b368ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3547426171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3547426171
Directory /workspace/18.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3199484528
Short name T3710
Test name
Test status
Simulation time 111154779 ps
CPU time 2.5 seconds
Started Aug 11 06:21:29 PM PDT 24
Finished Aug 11 06:21:32 PM PDT 24
Peak memory 223396 kb
Host smart-9e06c2c7-2fea-4fa2-9110-bf5dfae14c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3199484528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3199484528
Directory /workspace/18.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.393839202
Short name T329
Test name
Test status
Simulation time 162594034 ps
CPU time 1.82 seconds
Started Aug 11 06:21:33 PM PDT 24
Finished Aug 11 06:21:35 PM PDT 24
Peak memory 215204 kb
Host smart-4dd72c2f-0152-477d-b0bc-ed2555f49074
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393839202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.393839202
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2698728984
Short name T3701
Test name
Test status
Simulation time 85281295 ps
CPU time 1.01 seconds
Started Aug 11 06:21:32 PM PDT 24
Finished Aug 11 06:21:33 PM PDT 24
Peak memory 206736 kb
Host smart-5fe56971-56ef-4e1f-8fa9-a853b20ade05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2698728984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2698728984
Directory /workspace/19.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3177177965
Short name T3708
Test name
Test status
Simulation time 41206299 ps
CPU time 0.73 seconds
Started Aug 11 06:21:27 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 206616 kb
Host smart-20ad26a4-6309-4ce5-8b0b-dcfde33c726c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3177177965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3177177965
Directory /workspace/19.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2563653834
Short name T313
Test name
Test status
Simulation time 134986017 ps
CPU time 1.47 seconds
Started Aug 11 06:21:28 PM PDT 24
Finished Aug 11 06:21:30 PM PDT 24
Peak memory 206980 kb
Host smart-66a65a74-c946-4a62-906b-45c36e91fe0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2563653834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2563653834
Directory /workspace/19.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2694885648
Short name T3666
Test name
Test status
Simulation time 183067633 ps
CPU time 2.39 seconds
Started Aug 11 06:21:29 PM PDT 24
Finished Aug 11 06:21:32 PM PDT 24
Peak memory 206968 kb
Host smart-7cbcc4d0-1678-4bda-97b9-dac0af431e52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2694885648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2694885648
Directory /workspace/19.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.274463779
Short name T381
Test name
Test status
Simulation time 521430663 ps
CPU time 3.99 seconds
Started Aug 11 06:21:26 PM PDT 24
Finished Aug 11 06:21:30 PM PDT 24
Peak memory 206984 kb
Host smart-48e42561-f131-482e-b37e-eb8da0b24d36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=274463779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.274463779
Directory /workspace/19.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3206480924
Short name T3737
Test name
Test status
Simulation time 357595047 ps
CPU time 3.57 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:18 PM PDT 24
Peak memory 206704 kb
Host smart-6602e7d9-0d60-469a-abcc-1a692818b79f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3206480924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3206480924
Directory /workspace/2.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3664966098
Short name T3635
Test name
Test status
Simulation time 682639428 ps
CPU time 4.29 seconds
Started Aug 11 06:21:09 PM PDT 24
Finished Aug 11 06:21:13 PM PDT 24
Peak memory 206952 kb
Host smart-eac122d8-4820-4bf5-9f75-987e5bc22913
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3664966098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3664966098
Directory /workspace/2.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3098618960
Short name T3736
Test name
Test status
Simulation time 198796162 ps
CPU time 0.93 seconds
Started Aug 11 06:21:11 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 206672 kb
Host smart-ab2dddb7-25bc-4ebe-a033-6a1b99963e16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3098618960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3098618960
Directory /workspace/2.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1940009113
Short name T284
Test name
Test status
Simulation time 144098662 ps
CPU time 1.36 seconds
Started Aug 11 06:21:11 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 215120 kb
Host smart-712c34de-63e2-4d3a-afba-dcd814d196b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940009113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1940009113
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1831028189
Short name T304
Test name
Test status
Simulation time 47762540 ps
CPU time 0.96 seconds
Started Aug 11 06:21:11 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 206736 kb
Host smart-3af80d11-42fa-4c6e-991d-b565087f8eda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1831028189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1831028189
Directory /workspace/2.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2477476558
Short name T3644
Test name
Test status
Simulation time 40047109 ps
CPU time 0.7 seconds
Started Aug 11 06:21:12 PM PDT 24
Finished Aug 11 06:21:13 PM PDT 24
Peak memory 206540 kb
Host smart-be2539bc-1e14-4855-922c-95ec160079c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2477476558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2477476558
Directory /workspace/2.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1926392261
Short name T303
Test name
Test status
Simulation time 96954108 ps
CPU time 1.44 seconds
Started Aug 11 06:21:11 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 215104 kb
Host smart-90488aa5-ed05-4b15-a3b4-d9b5582386ad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1926392261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1926392261
Directory /workspace/2.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1536572807
Short name T3638
Test name
Test status
Simulation time 97099072 ps
CPU time 2.39 seconds
Started Aug 11 06:21:13 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 206832 kb
Host smart-5a7770b8-21db-4ca0-9b0b-85f9fe0778f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1536572807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1536572807
Directory /workspace/2.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.271299934
Short name T3707
Test name
Test status
Simulation time 241860921 ps
CPU time 1.65 seconds
Started Aug 11 06:21:11 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 206852 kb
Host smart-2e2bcaf1-672e-44ed-b0ae-230a680fb29b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=271299934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.271299934
Directory /workspace/2.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1040458650
Short name T262
Test name
Test status
Simulation time 1316207694 ps
CPU time 5.21 seconds
Started Aug 11 06:21:10 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 206912 kb
Host smart-6bc7cafa-b9ff-4e18-b240-db7bbde28911
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1040458650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1040458650
Directory /workspace/2.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3696989050
Short name T3664
Test name
Test status
Simulation time 53077819 ps
CPU time 0.77 seconds
Started Aug 11 06:21:33 PM PDT 24
Finished Aug 11 06:21:33 PM PDT 24
Peak memory 206600 kb
Host smart-62e68ba2-f030-4443-ae95-2d955efbcd79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3696989050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3696989050
Directory /workspace/20.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.199472553
Short name T3727
Test name
Test status
Simulation time 33653888 ps
CPU time 0.72 seconds
Started Aug 11 06:21:32 PM PDT 24
Finished Aug 11 06:21:32 PM PDT 24
Peak memory 206572 kb
Host smart-f23a4ea1-2162-49f8-af01-74fbb2d02848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=199472553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.199472553
Directory /workspace/21.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.56545835
Short name T3693
Test name
Test status
Simulation time 104230265 ps
CPU time 0.87 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206600 kb
Host smart-6b092cc4-938f-4bca-8027-ee7b8068f23a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=56545835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.56545835
Directory /workspace/22.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3117632169
Short name T3720
Test name
Test status
Simulation time 38403340 ps
CPU time 0.75 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206612 kb
Host smart-6e365720-a962-4b98-b53e-ba10f01aba5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3117632169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3117632169
Directory /workspace/23.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3392253820
Short name T3711
Test name
Test status
Simulation time 57934766 ps
CPU time 0.72 seconds
Started Aug 11 06:21:36 PM PDT 24
Finished Aug 11 06:21:36 PM PDT 24
Peak memory 206536 kb
Host smart-67a25e8b-c361-4593-800d-48dc105ec152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3392253820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3392253820
Directory /workspace/25.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.383557893
Short name T3649
Test name
Test status
Simulation time 33571422 ps
CPU time 0.7 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206580 kb
Host smart-1235e8b2-bae3-4daa-921c-7305376a09d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=383557893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.383557893
Directory /workspace/26.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2619379643
Short name T333
Test name
Test status
Simulation time 73557748 ps
CPU time 0.75 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206496 kb
Host smart-83132474-f0b0-4933-99ff-1b586da052ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2619379643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2619379643
Directory /workspace/27.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1077933505
Short name T3650
Test name
Test status
Simulation time 38524873 ps
CPU time 0.77 seconds
Started Aug 11 06:21:39 PM PDT 24
Finished Aug 11 06:21:40 PM PDT 24
Peak memory 206552 kb
Host smart-31595d33-e117-441a-94b8-ce17e28faae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1077933505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1077933505
Directory /workspace/28.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1959325872
Short name T236
Test name
Test status
Simulation time 42360337 ps
CPU time 0.75 seconds
Started Aug 11 06:21:38 PM PDT 24
Finished Aug 11 06:21:39 PM PDT 24
Peak memory 206588 kb
Host smart-d6d632fc-793c-4883-ac20-6c45355db757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1959325872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1959325872
Directory /workspace/29.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.864927854
Short name T302
Test name
Test status
Simulation time 124525484 ps
CPU time 3.27 seconds
Started Aug 11 06:21:09 PM PDT 24
Finished Aug 11 06:21:13 PM PDT 24
Peak memory 206856 kb
Host smart-d96bc617-666d-4e48-8a49-058d25d93aec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=864927854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.864927854
Directory /workspace/3.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4087220942
Short name T3721
Test name
Test status
Simulation time 898603208 ps
CPU time 4.89 seconds
Started Aug 11 06:21:10 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 207108 kb
Host smart-939d9f74-4bb7-42ec-ba57-8c5e9dc2b8d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4087220942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.4087220942
Directory /workspace/3.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1278239090
Short name T3665
Test name
Test status
Simulation time 56336178 ps
CPU time 0.8 seconds
Started Aug 11 06:21:09 PM PDT 24
Finished Aug 11 06:21:10 PM PDT 24
Peak memory 206720 kb
Host smart-3bf56a84-894c-4f5e-a41c-1c4d39f91fb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1278239090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1278239090
Directory /workspace/3.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.926431554
Short name T3689
Test name
Test status
Simulation time 83451479 ps
CPU time 2.22 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 215028 kb
Host smart-d1e06a91-e861-4efe-a1fd-a16a8619662c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926431554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.926431554
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2968494040
Short name T3735
Test name
Test status
Simulation time 51650161 ps
CPU time 0.81 seconds
Started Aug 11 06:21:14 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 206584 kb
Host smart-9c02616e-2b73-4393-b514-ed19da9aa82e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2968494040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2968494040
Directory /workspace/3.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3677883037
Short name T3648
Test name
Test status
Simulation time 42273433 ps
CPU time 0.7 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 206432 kb
Host smart-adbf317c-24ee-4bc3-b6dd-cb0e4cb6de99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3677883037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3677883037
Directory /workspace/3.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1840910539
Short name T309
Test name
Test status
Simulation time 83923852 ps
CPU time 2.27 seconds
Started Aug 11 06:21:10 PM PDT 24
Finished Aug 11 06:21:12 PM PDT 24
Peak memory 215076 kb
Host smart-acf3388b-6c05-4b8f-8961-23743dd649c7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1840910539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1840910539
Directory /workspace/3.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2695900957
Short name T3658
Test name
Test status
Simulation time 126415077 ps
CPU time 2.36 seconds
Started Aug 11 06:21:14 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 206864 kb
Host smart-ac538614-be51-4324-91d3-8f813c0854fd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2695900957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2695900957
Directory /workspace/3.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3830947315
Short name T318
Test name
Test status
Simulation time 183746766 ps
CPU time 1.28 seconds
Started Aug 11 06:21:10 PM PDT 24
Finished Aug 11 06:21:11 PM PDT 24
Peak memory 206856 kb
Host smart-0c84297f-3779-4256-a87d-befeb6cb3e1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3830947315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3830947315
Directory /workspace/3.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.806858151
Short name T261
Test name
Test status
Simulation time 69029292 ps
CPU time 1.9 seconds
Started Aug 11 06:21:07 PM PDT 24
Finished Aug 11 06:21:09 PM PDT 24
Peak memory 215072 kb
Host smart-934440cd-1a52-47cd-bc1f-330207ba79d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=806858151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.806858151
Directory /workspace/3.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.18397345
Short name T3688
Test name
Test status
Simulation time 343483229 ps
CPU time 2.32 seconds
Started Aug 11 06:21:12 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 206880 kb
Host smart-c293d58f-a698-4661-bf75-48986ae33aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=18397345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.18397345
Directory /workspace/3.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3926477543
Short name T368
Test name
Test status
Simulation time 49826560 ps
CPU time 0.71 seconds
Started Aug 11 06:21:39 PM PDT 24
Finished Aug 11 06:21:40 PM PDT 24
Peak memory 206604 kb
Host smart-7668d707-ed2f-4b8f-b237-85be4008a7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3926477543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3926477543
Directory /workspace/30.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2737007080
Short name T3728
Test name
Test status
Simulation time 35810353 ps
CPU time 0.71 seconds
Started Aug 11 06:21:34 PM PDT 24
Finished Aug 11 06:21:35 PM PDT 24
Peak memory 206616 kb
Host smart-b242b99f-83cc-4e68-ab8e-28ac8101494e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2737007080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2737007080
Directory /workspace/31.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1258833507
Short name T3706
Test name
Test status
Simulation time 57841867 ps
CPU time 0.74 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206520 kb
Host smart-d9beb4b5-ef76-4412-af85-e39f05790a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1258833507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1258833507
Directory /workspace/32.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3574360861
Short name T3684
Test name
Test status
Simulation time 46674521 ps
CPU time 0.78 seconds
Started Aug 11 06:21:38 PM PDT 24
Finished Aug 11 06:21:39 PM PDT 24
Peak memory 206556 kb
Host smart-9ab0c8c7-80d1-4e95-917f-9430c24988f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3574360861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3574360861
Directory /workspace/33.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.368293732
Short name T231
Test name
Test status
Simulation time 34697915 ps
CPU time 0.76 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206532 kb
Host smart-6a42d184-bfdc-4389-830b-0b76f0e08bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=368293732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.368293732
Directory /workspace/34.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.495053423
Short name T3716
Test name
Test status
Simulation time 36179731 ps
CPU time 0.69 seconds
Started Aug 11 06:21:39 PM PDT 24
Finished Aug 11 06:21:39 PM PDT 24
Peak memory 206624 kb
Host smart-f7f85b7d-b3eb-48e0-b34e-1f04fa1fd6c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=495053423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.495053423
Directory /workspace/35.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.892748638
Short name T3722
Test name
Test status
Simulation time 60723519 ps
CPU time 0.81 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206532 kb
Host smart-b5ff9ef6-3e01-41c9-99e0-7ac1048a315d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=892748638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.892748638
Directory /workspace/36.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.403206723
Short name T366
Test name
Test status
Simulation time 38711236 ps
CPU time 0.75 seconds
Started Aug 11 06:21:36 PM PDT 24
Finished Aug 11 06:21:37 PM PDT 24
Peak memory 206536 kb
Host smart-0dc8b172-462e-4554-9ca3-b22654757e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=403206723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.403206723
Directory /workspace/37.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.996732635
Short name T3685
Test name
Test status
Simulation time 42834368 ps
CPU time 0.7 seconds
Started Aug 11 06:21:34 PM PDT 24
Finished Aug 11 06:21:35 PM PDT 24
Peak memory 206624 kb
Host smart-cb5becd9-83da-49b4-ac6e-0fec9c2b3a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=996732635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.996732635
Directory /workspace/38.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.994274601
Short name T3675
Test name
Test status
Simulation time 98122359 ps
CPU time 0.77 seconds
Started Aug 11 06:21:38 PM PDT 24
Finished Aug 11 06:21:39 PM PDT 24
Peak memory 206540 kb
Host smart-d9fb75e0-382d-481a-8ed3-b5063674928f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=994274601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.994274601
Directory /workspace/39.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.563972366
Short name T3692
Test name
Test status
Simulation time 183985450 ps
CPU time 2.18 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:18 PM PDT 24
Peak memory 206892 kb
Host smart-69a06705-678c-4624-bce1-8b0924ac333a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=563972366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.563972366
Directory /workspace/4.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1358317062
Short name T3634
Test name
Test status
Simulation time 752573228 ps
CPU time 8.21 seconds
Started Aug 11 06:21:20 PM PDT 24
Finished Aug 11 06:21:28 PM PDT 24
Peak memory 206956 kb
Host smart-8004f8b2-23b5-4e83-9906-7632ea12166d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1358317062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1358317062
Directory /workspace/4.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1298835046
Short name T306
Test name
Test status
Simulation time 66130931 ps
CPU time 0.8 seconds
Started Aug 11 06:21:20 PM PDT 24
Finished Aug 11 06:21:21 PM PDT 24
Peak memory 206632 kb
Host smart-827c868e-3a8a-4231-83d7-a56b13bea94c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1298835046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1298835046
Directory /workspace/4.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4049030466
Short name T3724
Test name
Test status
Simulation time 72106070 ps
CPU time 1.8 seconds
Started Aug 11 06:21:16 PM PDT 24
Finished Aug 11 06:21:18 PM PDT 24
Peak memory 215396 kb
Host smart-24bd3e75-76a2-440d-9bc9-19a971e9e95a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049030466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.4049030466
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2806209330
Short name T3699
Test name
Test status
Simulation time 41315200 ps
CPU time 0.78 seconds
Started Aug 11 06:21:16 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 206584 kb
Host smart-58ddb255-7c17-4725-b1a6-f18bf4a90168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2806209330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2806209330
Directory /workspace/4.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.580495228
Short name T3677
Test name
Test status
Simulation time 66813933 ps
CPU time 0.72 seconds
Started Aug 11 06:21:11 PM PDT 24
Finished Aug 11 06:21:11 PM PDT 24
Peak memory 206552 kb
Host smart-423f344e-9aae-4421-87fe-9722ac676cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=580495228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.580495228
Directory /workspace/4.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2677920483
Short name T3697
Test name
Test status
Simulation time 68883779 ps
CPU time 1.46 seconds
Started Aug 11 06:21:20 PM PDT 24
Finished Aug 11 06:21:22 PM PDT 24
Peak memory 215056 kb
Host smart-aed25394-0b36-42fc-ac6f-8ff7d485a2ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2677920483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2677920483
Directory /workspace/4.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3642633151
Short name T3639
Test name
Test status
Simulation time 501956567 ps
CPU time 4.52 seconds
Started Aug 11 06:21:07 PM PDT 24
Finished Aug 11 06:21:11 PM PDT 24
Peak memory 206836 kb
Host smart-e9f64256-9ca1-4a46-922a-4ce81d15feed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3642633151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3642633151
Directory /workspace/4.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.594892298
Short name T3702
Test name
Test status
Simulation time 102114226 ps
CPU time 1.1 seconds
Started Aug 11 06:21:17 PM PDT 24
Finished Aug 11 06:21:18 PM PDT 24
Peak memory 206808 kb
Host smart-1309d4ad-638c-4c07-82ad-3fa1829b7b6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=594892298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.594892298
Directory /workspace/4.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.5620345
Short name T380
Test name
Test status
Simulation time 1394889667 ps
CPU time 5.16 seconds
Started Aug 11 06:21:11 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 206896 kb
Host smart-45e90547-14fd-4955-aab9-d4e4e6b0d115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=5620345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.5620345
Directory /workspace/4.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.105496464
Short name T235
Test name
Test status
Simulation time 43038626 ps
CPU time 0.73 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206616 kb
Host smart-f4366dbc-28c2-4654-bdec-febf87baf787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=105496464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.105496464
Directory /workspace/41.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2413485651
Short name T370
Test name
Test status
Simulation time 52216559 ps
CPU time 0.76 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206584 kb
Host smart-386b302a-e746-41a0-9242-88ba82df3217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2413485651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2413485651
Directory /workspace/42.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2172378212
Short name T3717
Test name
Test status
Simulation time 37078080 ps
CPU time 0.73 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206576 kb
Host smart-90b24c9a-a196-46a7-acdf-6758eb7d4073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2172378212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2172378212
Directory /workspace/44.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2635467053
Short name T3732
Test name
Test status
Simulation time 45611031 ps
CPU time 0.78 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206564 kb
Host smart-1fe9dded-5f8a-4cc3-b9fa-79a54346fde7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2635467053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2635467053
Directory /workspace/45.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.950921896
Short name T3641
Test name
Test status
Simulation time 65945153 ps
CPU time 0.71 seconds
Started Aug 11 06:21:37 PM PDT 24
Finished Aug 11 06:21:38 PM PDT 24
Peak memory 206596 kb
Host smart-24dd56ff-5174-4e43-8bab-2d7c516b1418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=950921896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.950921896
Directory /workspace/46.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.67479912
Short name T3734
Test name
Test status
Simulation time 61966855 ps
CPU time 0.77 seconds
Started Aug 11 06:21:36 PM PDT 24
Finished Aug 11 06:21:37 PM PDT 24
Peak memory 206504 kb
Host smart-13ba7c3b-3fc8-47c3-bd1d-1adb7179ec50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=67479912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.67479912
Directory /workspace/47.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3337448602
Short name T3662
Test name
Test status
Simulation time 83070642 ps
CPU time 0.74 seconds
Started Aug 11 06:21:36 PM PDT 24
Finished Aug 11 06:21:37 PM PDT 24
Peak memory 206572 kb
Host smart-1aab5441-fddb-47f3-96fb-3a79b2a66344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3337448602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3337448602
Directory /workspace/48.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2323029921
Short name T234
Test name
Test status
Simulation time 52722024 ps
CPU time 0.76 seconds
Started Aug 11 06:21:38 PM PDT 24
Finished Aug 11 06:21:39 PM PDT 24
Peak memory 206592 kb
Host smart-b4887a2f-398c-4101-ab04-d215a9567096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2323029921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2323029921
Directory /workspace/49.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3037384166
Short name T3663
Test name
Test status
Simulation time 146921763 ps
CPU time 1.83 seconds
Started Aug 11 06:21:20 PM PDT 24
Finished Aug 11 06:21:22 PM PDT 24
Peak memory 215176 kb
Host smart-6f88ef35-e51b-49a2-ae2a-44dea4ebee56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037384166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.3037384166
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.868551019
Short name T308
Test name
Test status
Simulation time 56539758 ps
CPU time 0.93 seconds
Started Aug 11 06:21:20 PM PDT 24
Finished Aug 11 06:21:21 PM PDT 24
Peak memory 206696 kb
Host smart-78bad7ae-59d1-4cbc-85c0-a64abc78aa2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=868551019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.868551019
Directory /workspace/5.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3442494909
Short name T3672
Test name
Test status
Simulation time 46345398 ps
CPU time 0.74 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 206536 kb
Host smart-be190c5d-ec7d-41dc-909b-d0182f58d212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3442494909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3442494909
Directory /workspace/5.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2484176595
Short name T3660
Test name
Test status
Simulation time 124202554 ps
CPU time 1.16 seconds
Started Aug 11 06:21:16 PM PDT 24
Finished Aug 11 06:21:18 PM PDT 24
Peak memory 206896 kb
Host smart-20aa610f-d05d-4fcd-bcc2-3b43d340f829
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2484176595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2484176595
Directory /workspace/5.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1057153188
Short name T3657
Test name
Test status
Simulation time 71157190 ps
CPU time 1.69 seconds
Started Aug 11 06:21:16 PM PDT 24
Finished Aug 11 06:21:18 PM PDT 24
Peak memory 206996 kb
Host smart-25b34727-c953-4562-9a1e-84eac76bae8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1057153188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1057153188
Directory /workspace/5.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1559633184
Short name T374
Test name
Test status
Simulation time 1359877672 ps
CPU time 5.63 seconds
Started Aug 11 06:21:16 PM PDT 24
Finished Aug 11 06:21:22 PM PDT 24
Peak memory 206912 kb
Host smart-c486905f-c60d-470e-95ab-23236a531aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1559633184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1559633184
Directory /workspace/5.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.813826555
Short name T225
Test name
Test status
Simulation time 104971439 ps
CPU time 1.53 seconds
Started Aug 11 06:21:16 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 215172 kb
Host smart-cd05e48e-4dd7-49f3-b54d-b880d9e5824e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813826555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.813826555
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1949617252
Short name T3695
Test name
Test status
Simulation time 75601418 ps
CPU time 1.01 seconds
Started Aug 11 06:21:16 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 206680 kb
Host smart-1306aa28-7f71-49fa-b2e5-c86929ff9a61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1949617252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1949617252
Directory /workspace/6.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2161930742
Short name T3723
Test name
Test status
Simulation time 54944022 ps
CPU time 0.73 seconds
Started Aug 11 06:21:17 PM PDT 24
Finished Aug 11 06:21:18 PM PDT 24
Peak memory 206536 kb
Host smart-de13825d-00c4-42fd-a295-0fad82f7cb67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161930742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2161930742
Directory /workspace/6.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1951331037
Short name T330
Test name
Test status
Simulation time 242458592 ps
CPU time 1.77 seconds
Started Aug 11 06:21:16 PM PDT 24
Finished Aug 11 06:21:18 PM PDT 24
Peak memory 206920 kb
Host smart-2312a84a-3cf7-4d22-9e8f-8afa3570d8af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1951331037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1951331037
Directory /workspace/6.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.78014993
Short name T280
Test name
Test status
Simulation time 70550223 ps
CPU time 1.88 seconds
Started Aug 11 06:21:18 PM PDT 24
Finished Aug 11 06:21:20 PM PDT 24
Peak memory 207000 kb
Host smart-f7aa911b-93d7-44f1-bbf8-22b4342c41ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=78014993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.78014993
Directory /workspace/6.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3879452009
Short name T379
Test name
Test status
Simulation time 698708874 ps
CPU time 4.2 seconds
Started Aug 11 06:21:17 PM PDT 24
Finished Aug 11 06:21:21 PM PDT 24
Peak memory 206916 kb
Host smart-be011a02-fc9b-40d7-9173-1aed4d5ce1c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3879452009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3879452009
Directory /workspace/6.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3228522518
Short name T3656
Test name
Test status
Simulation time 79396180 ps
CPU time 1.42 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 215208 kb
Host smart-74d9e7e8-65bf-446d-84ae-22fb794f8b60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228522518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3228522518
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.463294939
Short name T315
Test name
Test status
Simulation time 96746827 ps
CPU time 0.89 seconds
Started Aug 11 06:21:14 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 206776 kb
Host smart-ac6a9fe2-a94d-4df2-94b0-8bcae3e481e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=463294939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.463294939
Directory /workspace/7.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2783929095
Short name T3705
Test name
Test status
Simulation time 66076836 ps
CPU time 0.77 seconds
Started Aug 11 06:21:14 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 206608 kb
Host smart-8deefb1e-09c4-4ad9-a6cb-01e6f8914b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2783929095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2783929095
Directory /workspace/7.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1870062593
Short name T3682
Test name
Test status
Simulation time 188462267 ps
CPU time 1.29 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 206736 kb
Host smart-53f038ec-071f-42b5-88b2-3319fe8ae961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1870062593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1870062593
Directory /workspace/7.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.363833021
Short name T3725
Test name
Test status
Simulation time 63269926 ps
CPU time 1.3 seconds
Started Aug 11 06:21:18 PM PDT 24
Finished Aug 11 06:21:19 PM PDT 24
Peak memory 206972 kb
Host smart-aa4466c6-aba7-4829-940f-59aafbd905f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=363833021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.363833021
Directory /workspace/7.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1669771873
Short name T384
Test name
Test status
Simulation time 531900580 ps
CPU time 2.86 seconds
Started Aug 11 06:21:16 PM PDT 24
Finished Aug 11 06:21:19 PM PDT 24
Peak memory 206964 kb
Host smart-d7e42881-3fda-4d61-aa09-b53495b1864a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1669771873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1669771873
Directory /workspace/7.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2563559622
Short name T3640
Test name
Test status
Simulation time 86010250 ps
CPU time 1.76 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 215128 kb
Host smart-405f8805-b734-4ae4-8c5f-f22e4d148f73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563559622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2563559622
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2920681076
Short name T3687
Test name
Test status
Simulation time 79305101 ps
CPU time 1.06 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:16 PM PDT 24
Peak memory 206588 kb
Host smart-2902bf34-aced-41fc-aecb-e164c862309b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2920681076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2920681076
Directory /workspace/8.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1497630000
Short name T369
Test name
Test status
Simulation time 60114474 ps
CPU time 0.75 seconds
Started Aug 11 06:21:20 PM PDT 24
Finished Aug 11 06:21:20 PM PDT 24
Peak memory 206628 kb
Host smart-160532f9-638e-42db-90dd-68ce8f1d5a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1497630000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1497630000
Directory /workspace/8.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1748657857
Short name T317
Test name
Test status
Simulation time 99178496 ps
CPU time 1.23 seconds
Started Aug 11 06:21:20 PM PDT 24
Finished Aug 11 06:21:21 PM PDT 24
Peak memory 206964 kb
Host smart-cfe3d4ab-d7d9-493e-8037-d8ec0821a5c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1748657857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1748657857
Directory /workspace/8.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.573602636
Short name T3671
Test name
Test status
Simulation time 55384634 ps
CPU time 1.54 seconds
Started Aug 11 06:21:14 PM PDT 24
Finished Aug 11 06:21:15 PM PDT 24
Peak memory 206984 kb
Host smart-8aa2f0d8-e192-4791-8a55-69c80aea646b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=573602636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.573602636
Directory /workspace/8.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.501896124
Short name T376
Test name
Test status
Simulation time 298061352 ps
CPU time 2.41 seconds
Started Aug 11 06:21:18 PM PDT 24
Finished Aug 11 06:21:20 PM PDT 24
Peak memory 206984 kb
Host smart-4603a3aa-2e33-45f8-a27d-0c96db278405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=501896124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.501896124
Directory /workspace/8.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.471851548
Short name T3726
Test name
Test status
Simulation time 194408835 ps
CPU time 1.96 seconds
Started Aug 11 06:21:21 PM PDT 24
Finished Aug 11 06:21:24 PM PDT 24
Peak memory 219500 kb
Host smart-78d61ec1-dbc9-4305-96ae-b0ce070a0e56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471851548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.471851548
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3890289423
Short name T264
Test name
Test status
Simulation time 50599859 ps
CPU time 0.97 seconds
Started Aug 11 06:21:22 PM PDT 24
Finished Aug 11 06:21:24 PM PDT 24
Peak memory 206636 kb
Host smart-7d7d2fc4-c029-49ca-bc29-c6c5002cf5e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3890289423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3890289423
Directory /workspace/9.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.377604438
Short name T3676
Test name
Test status
Simulation time 75168828 ps
CPU time 0.78 seconds
Started Aug 11 06:21:21 PM PDT 24
Finished Aug 11 06:21:22 PM PDT 24
Peak memory 206624 kb
Host smart-099d5e08-23d3-4233-893d-f2c6b17605b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=377604438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.377604438
Directory /workspace/9.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4239699802
Short name T3669
Test name
Test status
Simulation time 63532806 ps
CPU time 1.06 seconds
Started Aug 11 06:21:24 PM PDT 24
Finished Aug 11 06:21:25 PM PDT 24
Peak memory 206924 kb
Host smart-a392554c-2b2a-4b47-a8db-5cdbe3bee53d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4239699802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.4239699802
Directory /workspace/9.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1434680449
Short name T282
Test name
Test status
Simulation time 150858666 ps
CPU time 1.59 seconds
Started Aug 11 06:21:15 PM PDT 24
Finished Aug 11 06:21:17 PM PDT 24
Peak memory 206908 kb
Host smart-06f94037-abbf-4b11-81c8-38307e9fc56d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1434680449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1434680449
Directory /workspace/9.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3884198206
Short name T378
Test name
Test status
Simulation time 464984557 ps
CPU time 2.51 seconds
Started Aug 11 06:21:24 PM PDT 24
Finished Aug 11 06:21:26 PM PDT 24
Peak memory 206932 kb
Host smart-714ca2ef-6ad4-4e3c-aeee-f7a55de1ca04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3884198206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3884198206
Directory /workspace/9.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2705343136
Short name T1944
Test name
Test status
Simulation time 5112421887 ps
CPU time 6.93 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:08:34 PM PDT 24
Peak memory 215944 kb
Host smart-a69ce0dc-98fd-46f4-92c5-056817440d66
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705343136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.2705343136
Directory /workspace/0.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.876450015
Short name T14
Test name
Test status
Simulation time 15967162547 ps
CPU time 17.29 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:08:44 PM PDT 24
Peak memory 215956 kb
Host smart-c2b4a15b-34c7-448c-85ea-b57baec3c46d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=876450015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.876450015
Directory /workspace/0.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.31202599
Short name T1140
Test name
Test status
Simulation time 25326889453 ps
CPU time 37 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:09:04 PM PDT 24
Peak memory 216008 kb
Host smart-b57270c0-65e9-43c5-9d7f-24a3c3b4e293
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31202599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_
wake_resume.31202599
Directory /workspace/0.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/0.usbdev_av_buffer.86730928
Short name T2681
Test name
Test status
Simulation time 164781359 ps
CPU time 0.88 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 207584 kb
Host smart-8b109c3b-474b-4e0c-9920-be492e0d2c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86730
928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.86730928
Directory /workspace/0.usbdev_av_buffer/latest


Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3505220581
Short name T2663
Test name
Test status
Simulation time 166265671 ps
CPU time 0.93 seconds
Started Aug 11 07:08:23 PM PDT 24
Finished Aug 11 07:08:24 PM PDT 24
Peak memory 207560 kb
Host smart-059f590b-dd3d-4b72-84a8-265997ce79d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35052
20581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3505220581
Directory /workspace/0.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.4031755368
Short name T1616
Test name
Test status
Simulation time 145792860 ps
CPU time 0.88 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:32 PM PDT 24
Peak memory 207520 kb
Host smart-6ae49e85-c48a-42a5-a660-3326fb873be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40317
55368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.4031755368
Directory /workspace/0.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.1669629203
Short name T3293
Test name
Test status
Simulation time 489651129 ps
CPU time 1.5 seconds
Started Aug 11 07:08:24 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 207504 kb
Host smart-214d8c7a-93f0-4568-8fc8-b83e3710580e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1669629203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.1669629203
Directory /workspace/0.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/0.usbdev_device_address.1810697649
Short name T1790
Test name
Test status
Simulation time 16779901297 ps
CPU time 27.5 seconds
Started Aug 11 07:08:24 PM PDT 24
Finished Aug 11 07:08:51 PM PDT 24
Peak memory 208084 kb
Host smart-40d4de8a-2185-47c7-a50a-e99bcb03a347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18106
97649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1810697649
Directory /workspace/0.usbdev_device_address/latest


Test location /workspace/coverage/default/0.usbdev_device_timeout.3324648664
Short name T2845
Test name
Test status
Simulation time 610870183 ps
CPU time 5.01 seconds
Started Aug 11 07:08:26 PM PDT 24
Finished Aug 11 07:08:31 PM PDT 24
Peak memory 207724 kb
Host smart-b20c7e45-0b50-471d-bd97-5ad951db9ca8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324648664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.3324648664
Directory /workspace/0.usbdev_device_timeout/latest


Test location /workspace/coverage/default/0.usbdev_disable_endpoint.396366991
Short name T2343
Test name
Test status
Simulation time 359044756 ps
CPU time 1.46 seconds
Started Aug 11 07:08:26 PM PDT 24
Finished Aug 11 07:08:28 PM PDT 24
Peak memory 207488 kb
Host smart-d72a5c72-3218-4e74-8554-5521b34518b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39636
6991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.396366991
Directory /workspace/0.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/0.usbdev_enable.2917218298
Short name T1660
Test name
Test status
Simulation time 39089695 ps
CPU time 0.73 seconds
Started Aug 11 07:08:26 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 207444 kb
Host smart-66044119-e5f7-4eb5-b308-7cda4c7e3516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29172
18298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2917218298
Directory /workspace/0.usbdev_enable/latest


Test location /workspace/coverage/default/0.usbdev_endpoint_access.736280886
Short name T1953
Test name
Test status
Simulation time 803997789 ps
CPU time 2.28 seconds
Started Aug 11 07:08:28 PM PDT 24
Finished Aug 11 07:08:31 PM PDT 24
Peak memory 207696 kb
Host smart-58fc93a4-f503-4746-a0aa-d94a68d37969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73628
0886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.736280886
Directory /workspace/0.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/0.usbdev_fifo_rst.3604531562
Short name T3092
Test name
Test status
Simulation time 227846669 ps
CPU time 2.4 seconds
Started Aug 11 07:08:23 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 207644 kb
Host smart-65b8d94b-fe85-45f1-9bb2-dcca1f1134c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36045
31562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3604531562
Directory /workspace/0.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/0.usbdev_freq_hiclk.1725017772
Short name T859
Test name
Test status
Simulation time 100180908265 ps
CPU time 159.46 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:11:05 PM PDT 24
Peak memory 207876 kb
Host smart-f3f16de5-0236-44ec-a331-a9d7742caf0e
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1725017772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.1725017772
Directory /workspace/0.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2872738202
Short name T1737
Test name
Test status
Simulation time 105258289013 ps
CPU time 151.73 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:10:59 PM PDT 24
Peak memory 207808 kb
Host smart-60144309-f5ce-439c-b9cf-1a2b2c49988f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872738202 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2872738202
Directory /workspace/0.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/0.usbdev_freq_loclk.3008591347
Short name T363
Test name
Test status
Simulation time 86120119800 ps
CPU time 130.91 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:10:36 PM PDT 24
Peak memory 207864 kb
Host smart-82a14448-8fbd-42a0-b673-c3d01a7e0a2d
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3008591347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3008591347
Directory /workspace/0.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.1622511871
Short name T3000
Test name
Test status
Simulation time 87225503069 ps
CPU time 138.61 seconds
Started Aug 11 07:08:29 PM PDT 24
Finished Aug 11 07:10:48 PM PDT 24
Peak memory 207796 kb
Host smart-cbde5710-a50b-4b31-910c-9c18dba2cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622511871 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.1622511871
Directory /workspace/0.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/0.usbdev_freq_phase.641919756
Short name T1149
Test name
Test status
Simulation time 106114810481 ps
CPU time 176.02 seconds
Started Aug 11 07:08:26 PM PDT 24
Finished Aug 11 07:11:22 PM PDT 24
Peak memory 207828 kb
Host smart-6d397414-9953-4954-ac78-721e50d6bc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64191
9756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.641919756
Directory /workspace/0.usbdev_freq_phase/latest


Test location /workspace/coverage/default/0.usbdev_in_iso.3786482635
Short name T2351
Test name
Test status
Simulation time 210889508 ps
CPU time 1.09 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:08:28 PM PDT 24
Peak memory 215932 kb
Host smart-1b1d9872-8347-4fd8-80d6-02f93b7d0df4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3786482635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3786482635
Directory /workspace/0.usbdev_in_iso/latest


Test location /workspace/coverage/default/0.usbdev_in_stall.2289097863
Short name T3461
Test name
Test status
Simulation time 145301397 ps
CPU time 0.84 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:08:28 PM PDT 24
Peak memory 207516 kb
Host smart-bdf52aa8-f422-455b-bccd-560d6dc5e18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22890
97863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2289097863
Directory /workspace/0.usbdev_in_stall/latest


Test location /workspace/coverage/default/0.usbdev_in_trans.1448838650
Short name T2178
Test name
Test status
Simulation time 167042353 ps
CPU time 0.97 seconds
Started Aug 11 07:08:32 PM PDT 24
Finished Aug 11 07:08:33 PM PDT 24
Peak memory 207552 kb
Host smart-047f4bc0-3ad5-4e71-8a79-3cc7ecc5cce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
38650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1448838650
Directory /workspace/0.usbdev_in_trans/latest


Test location /workspace/coverage/default/0.usbdev_invalid_sync.572206839
Short name T2198
Test name
Test status
Simulation time 3786294924 ps
CPU time 38.4 seconds
Started Aug 11 07:08:28 PM PDT 24
Finished Aug 11 07:09:07 PM PDT 24
Peak memory 224244 kb
Host smart-218aaf2d-1e02-4401-8569-d1dea9e31e56
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=572206839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.572206839
Directory /workspace/0.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/0.usbdev_iso_retraction.1510422421
Short name T2006
Test name
Test status
Simulation time 6106411376 ps
CPU time 42.45 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:09:07 PM PDT 24
Peak memory 207860 kb
Host smart-2498887a-4895-4f51-8fb2-ad0fd6c6c594
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1510422421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1510422421
Directory /workspace/0.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/0.usbdev_link_in_err.2081097568
Short name T2536
Test name
Test status
Simulation time 208949359 ps
CPU time 1.04 seconds
Started Aug 11 07:08:28 PM PDT 24
Finished Aug 11 07:08:29 PM PDT 24
Peak memory 207148 kb
Host smart-47e6a652-4041-4c72-8024-edc9b3ac10a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20810
97568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2081097568
Directory /workspace/0.usbdev_link_in_err/latest


Test location /workspace/coverage/default/0.usbdev_link_out_err.389866802
Short name T75
Test name
Test status
Simulation time 475610488 ps
CPU time 1.43 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:08:27 PM PDT 24
Peak memory 207548 kb
Host smart-a15c2fa3-0152-47cd-8c40-b98a1519ee0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38986
6802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.389866802
Directory /workspace/0.usbdev_link_out_err/latest


Test location /workspace/coverage/default/0.usbdev_link_resume.2393154761
Short name T71
Test name
Test status
Simulation time 29930557514 ps
CPU time 50.09 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:09:17 PM PDT 24
Peak memory 207628 kb
Host smart-12f4d504-335c-4d5d-b038-8eb12d3e447c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23931
54761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2393154761
Directory /workspace/0.usbdev_link_resume/latest


Test location /workspace/coverage/default/0.usbdev_link_suspend.4222034620
Short name T3312
Test name
Test status
Simulation time 5429929159 ps
CPU time 7.8 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:38 PM PDT 24
Peak memory 215940 kb
Host smart-d1c1f970-b901-4915-82dc-7c47038ae0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42220
34620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.4222034620
Directory /workspace/0.usbdev_link_suspend/latest


Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.4058375766
Short name T128
Test name
Test status
Simulation time 4585571623 ps
CPU time 136.52 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:10:44 PM PDT 24
Peak memory 224284 kb
Host smart-a991baa5-1404-4d84-826e-8d3e061a6539
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4058375766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.4058375766
Directory /workspace/0.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1261348531
Short name T634
Test name
Test status
Simulation time 2315478396 ps
CPU time 64.08 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:09:31 PM PDT 24
Peak memory 224180 kb
Host smart-7995a0bb-0aea-4102-a9c9-f79e0a487516
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1261348531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1261348531
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1147386390
Short name T2215
Test name
Test status
Simulation time 256948394 ps
CPU time 1.07 seconds
Started Aug 11 07:08:32 PM PDT 24
Finished Aug 11 07:08:33 PM PDT 24
Peak memory 207548 kb
Host smart-d8ffc890-7123-468e-9742-e20b9862a55b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1147386390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1147386390
Directory /workspace/0.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.783731935
Short name T682
Test name
Test status
Simulation time 219149990 ps
CPU time 1 seconds
Started Aug 11 07:08:23 PM PDT 24
Finished Aug 11 07:08:24 PM PDT 24
Peak memory 207580 kb
Host smart-22a9e428-55c9-44f3-8450-0704c1ad2297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78373
1935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.783731935
Directory /workspace/0.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.3249507574
Short name T3506
Test name
Test status
Simulation time 2266799403 ps
CPU time 23.22 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 217928 kb
Host smart-a76b9e68-7d93-4e46-8596-86e34b22a7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32495
07574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.3249507574
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.846320912
Short name T1882
Test name
Test status
Simulation time 1475002060 ps
CPU time 41.72 seconds
Started Aug 11 07:08:26 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 215968 kb
Host smart-c01bbbb2-fcdf-45de-b1a7-5edf7651ead4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=846320912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.846320912
Directory /workspace/0.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.2000096146
Short name T2776
Test name
Test status
Simulation time 2809340523 ps
CPU time 84.18 seconds
Started Aug 11 07:08:24 PM PDT 24
Finished Aug 11 07:09:48 PM PDT 24
Peak memory 217316 kb
Host smart-f7c707bd-78f6-4f9b-b69e-31700e3a6f5b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2000096146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.2000096146
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.13735389
Short name T2996
Test name
Test status
Simulation time 159677585 ps
CPU time 0.83 seconds
Started Aug 11 07:08:32 PM PDT 24
Finished Aug 11 07:08:33 PM PDT 24
Peak memory 207548 kb
Host smart-b0a6ca8a-a2be-4fa4-bb8b-527464a95b89
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=13735389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.13735389
Directory /workspace/0.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2064161963
Short name T3309
Test name
Test status
Simulation time 173619114 ps
CPU time 0.87 seconds
Started Aug 11 07:08:23 PM PDT 24
Finished Aug 11 07:08:24 PM PDT 24
Peak memory 207512 kb
Host smart-d5c595aa-7e80-423b-80fd-9eddbf266ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20641
61963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2064161963
Directory /workspace/0.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3423655036
Short name T74
Test name
Test status
Simulation time 557195517 ps
CPU time 1.62 seconds
Started Aug 11 07:08:24 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 207452 kb
Host smart-5e4f0d7b-1fa2-4725-ab99-dc2fa89b5654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34236
55036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3423655036
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest


Test location /workspace/coverage/default/0.usbdev_out_iso.454630761
Short name T631
Test name
Test status
Simulation time 199187100 ps
CPU time 0.94 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:08:28 PM PDT 24
Peak memory 207524 kb
Host smart-829bea7d-62bd-4948-b47b-b03c641148c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45463
0761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.454630761
Directory /workspace/0.usbdev_out_iso/latest


Test location /workspace/coverage/default/0.usbdev_out_stall.285276044
Short name T2772
Test name
Test status
Simulation time 144128179 ps
CPU time 0.83 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 207480 kb
Host smart-a1e23ac4-2e5f-495e-8157-660b0b60a019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28527
6044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.285276044
Directory /workspace/0.usbdev_out_stall/latest


Test location /workspace/coverage/default/0.usbdev_out_trans_nak.4040633867
Short name T1761
Test name
Test status
Simulation time 160814231 ps
CPU time 0.87 seconds
Started Aug 11 07:08:24 PM PDT 24
Finished Aug 11 07:08:25 PM PDT 24
Peak memory 207572 kb
Host smart-7c714cda-1692-4f40-802c-60a51e053221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40406
33867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.4040633867
Directory /workspace/0.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/0.usbdev_pending_in_trans.577083563
Short name T2161
Test name
Test status
Simulation time 168989430 ps
CPU time 0.87 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 207544 kb
Host smart-1c7223f5-b274-4ab6-8eaa-3c003b0bbc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57708
3563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.577083563
Directory /workspace/0.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.843028230
Short name T1165
Test name
Test status
Simulation time 153223067 ps
CPU time 0.92 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:08:28 PM PDT 24
Peak memory 207364 kb
Host smart-61ae3cd4-f354-4200-94ab-2dbda4d1b299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84302
8230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.843028230
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3637852625
Short name T2713
Test name
Test status
Simulation time 265917037 ps
CPU time 1.07 seconds
Started Aug 11 07:08:25 PM PDT 24
Finished Aug 11 07:08:26 PM PDT 24
Peak memory 207516 kb
Host smart-24b6b674-fce0-45dd-87bd-a5df71a058e9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3637852625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3637852625
Directory /workspace/0.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.780409489
Short name T2683
Test name
Test status
Simulation time 200097337 ps
CPU time 1 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:32 PM PDT 24
Peak memory 207480 kb
Host smart-57a26a27-77db-4393-802a-f7f025ea12fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78040
9489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.780409489
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3098102895
Short name T781
Test name
Test status
Simulation time 215701142 ps
CPU time 0.97 seconds
Started Aug 11 07:08:30 PM PDT 24
Finished Aug 11 07:08:31 PM PDT 24
Peak memory 207552 kb
Host smart-db885e97-e214-442a-a211-99504b0035e3
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3098102895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3098102895
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.249409585
Short name T1178
Test name
Test status
Simulation time 299187747 ps
CPU time 1.13 seconds
Started Aug 11 07:08:29 PM PDT 24
Finished Aug 11 07:08:31 PM PDT 24
Peak memory 207584 kb
Host smart-56386034-e4e0-4134-9727-b64f6afb0c2f
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=249409585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.249409585
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1451415940
Short name T1163
Test name
Test status
Simulation time 141410914 ps
CPU time 0.87 seconds
Started Aug 11 07:08:30 PM PDT 24
Finished Aug 11 07:08:31 PM PDT 24
Peak memory 207540 kb
Host smart-9208fad3-e54c-4ea1-b747-960aba43cfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14514
15940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1451415940
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1810462072
Short name T1954
Test name
Test status
Simulation time 47424884 ps
CPU time 0.67 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:31 PM PDT 24
Peak memory 207468 kb
Host smart-3947084c-49cc-4ee2-b174-770c61f8348c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18104
62072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1810462072
Directory /workspace/0.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/0.usbdev_pkt_buffer.715649861
Short name T2383
Test name
Test status
Simulation time 7810480580 ps
CPU time 19.92 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:51 PM PDT 24
Peak memory 216080 kb
Host smart-9378ff9a-0d00-4eca-8be1-00cb763ccfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71564
9861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.715649861
Directory /workspace/0.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/0.usbdev_pkt_received.3726044559
Short name T1092
Test name
Test status
Simulation time 169477422 ps
CPU time 0.91 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:33 PM PDT 24
Peak memory 207544 kb
Host smart-6a73a02d-06bc-45e6-a9c8-8e58fc12d1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37260
44559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3726044559
Directory /workspace/0.usbdev_pkt_received/latest


Test location /workspace/coverage/default/0.usbdev_pkt_sent.148172124
Short name T681
Test name
Test status
Simulation time 201893357 ps
CPU time 0.92 seconds
Started Aug 11 07:08:32 PM PDT 24
Finished Aug 11 07:08:33 PM PDT 24
Peak memory 207492 kb
Host smart-2dc54f1f-8bfe-49da-be03-ff1406b4ef90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14817
2124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.148172124
Directory /workspace/0.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1151904376
Short name T3268
Test name
Test status
Simulation time 6250190752 ps
CPU time 55.35 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:09:27 PM PDT 24
Peak memory 218688 kb
Host smart-5a8b0f03-8ccd-4107-a3e4-6b41e9c116b6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151904376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1151904376
Directory /workspace/0.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.42826319
Short name T3238
Test name
Test status
Simulation time 6414211104 ps
CPU time 169.35 seconds
Started Aug 11 07:08:34 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 216112 kb
Host smart-90294c86-2e2e-4ecb-93f7-7f7af5da7efc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=42826319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.42826319
Directory /workspace/0.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/0.usbdev_rand_suspends.1584127574
Short name T2812
Test name
Test status
Simulation time 5252914353 ps
CPU time 20.27 seconds
Started Aug 11 07:08:32 PM PDT 24
Finished Aug 11 07:08:52 PM PDT 24
Peak memory 219540 kb
Host smart-c91eee94-5d5b-4d33-9742-d09dadfb22e6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584127574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1584127574
Directory /workspace/0.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.151475898
Short name T557
Test name
Test status
Simulation time 176545968 ps
CPU time 0.94 seconds
Started Aug 11 07:08:34 PM PDT 24
Finished Aug 11 07:08:35 PM PDT 24
Peak memory 207568 kb
Host smart-591a4a36-fb87-4ce5-89e3-f249eb61aaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15147
5898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.151475898
Directory /workspace/0.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3656000751
Short name T3258
Test name
Test status
Simulation time 172146251 ps
CPU time 0.92 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:32 PM PDT 24
Peak memory 207452 kb
Host smart-bbb157a1-a62a-4070-ba00-bcd6e161f720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36560
00751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3656000751
Directory /workspace/0.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_resume_link_active.4055637563
Short name T3317
Test name
Test status
Simulation time 20153767906 ps
CPU time 27.92 seconds
Started Aug 11 07:08:32 PM PDT 24
Finished Aug 11 07:09:00 PM PDT 24
Peak memory 207532 kb
Host smart-d2e6f0ca-5eb9-4a6a-9e31-3acd3781fd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40556
37563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.4055637563
Directory /workspace/0.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1022866470
Short name T1271
Test name
Test status
Simulation time 180069615 ps
CPU time 0.88 seconds
Started Aug 11 07:08:29 PM PDT 24
Finished Aug 11 07:08:30 PM PDT 24
Peak memory 207476 kb
Host smart-866fa36f-2960-4d49-9edc-52875cf2891e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10228
66470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1022866470
Directory /workspace/0.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/0.usbdev_rx_full.1173357532
Short name T3298
Test name
Test status
Simulation time 327050116 ps
CPU time 1.16 seconds
Started Aug 11 07:08:29 PM PDT 24
Finished Aug 11 07:08:30 PM PDT 24
Peak memory 207544 kb
Host smart-2b105a71-f4f2-4d20-b207-18bbe444359f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11733
57532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.1173357532
Directory /workspace/0.usbdev_rx_full/latest


Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2109429752
Short name T3254
Test name
Test status
Simulation time 228676996 ps
CPU time 1 seconds
Started Aug 11 07:08:33 PM PDT 24
Finished Aug 11 07:08:34 PM PDT 24
Peak memory 207756 kb
Host smart-7614cea4-5e63-4fca-98db-ea9e0d1c4170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21094
29752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2109429752
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/0.usbdev_setup_stage.774579746
Short name T2901
Test name
Test status
Simulation time 189853761 ps
CPU time 0.91 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:33 PM PDT 24
Peak memory 207536 kb
Host smart-776fe2aa-fba3-4317-bcdc-d27414896aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77457
9746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.774579746
Directory /workspace/0.usbdev_setup_stage/latest


Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.288423195
Short name T1072
Test name
Test status
Simulation time 192544543 ps
CPU time 0.91 seconds
Started Aug 11 07:08:32 PM PDT 24
Finished Aug 11 07:08:33 PM PDT 24
Peak memory 207532 kb
Host smart-ec1802c9-4383-45d8-aa06-da96503fa64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28842
3195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.288423195
Directory /workspace/0.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/0.usbdev_smoke.3357204101
Short name T862
Test name
Test status
Simulation time 220911937 ps
CPU time 0.99 seconds
Started Aug 11 07:08:30 PM PDT 24
Finished Aug 11 07:08:31 PM PDT 24
Peak memory 207596 kb
Host smart-2597b3de-8f88-43b8-afcc-5f00a3ed138e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33572
04101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3357204101
Directory /workspace/0.usbdev_smoke/latest


Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1847251082
Short name T1519
Test name
Test status
Simulation time 3091743699 ps
CPU time 89.83 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:10:01 PM PDT 24
Peak memory 216132 kb
Host smart-b901b528-67ff-42bf-a1f4-6616be1d994b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1847251082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1847251082
Directory /workspace/0.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3319832960
Short name T2803
Test name
Test status
Simulation time 189849329 ps
CPU time 0.94 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:32 PM PDT 24
Peak memory 207536 kb
Host smart-1d62d112-c1a5-417d-89b9-ee1764599a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
32960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3319832960
Directory /workspace/0.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/0.usbdev_stall_trans.663317846
Short name T3274
Test name
Test status
Simulation time 200252912 ps
CPU time 0.87 seconds
Started Aug 11 07:08:33 PM PDT 24
Finished Aug 11 07:08:34 PM PDT 24
Peak memory 207516 kb
Host smart-03524f93-e67a-4c2d-abe3-8058cbac7fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66331
7846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.663317846
Directory /workspace/0.usbdev_stall_trans/latest


Test location /workspace/coverage/default/0.usbdev_stream_len_max.1438508401
Short name T2207
Test name
Test status
Simulation time 1274019844 ps
CPU time 2.81 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:34 PM PDT 24
Peak memory 207680 kb
Host smart-1ef6e0f8-2e75-4544-9363-5fc24c49bbe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14385
08401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1438508401
Directory /workspace/0.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/0.usbdev_streaming_out.1871341692
Short name T1676
Test name
Test status
Simulation time 2594664209 ps
CPU time 76.93 seconds
Started Aug 11 07:08:34 PM PDT 24
Finished Aug 11 07:09:51 PM PDT 24
Peak memory 217644 kb
Host smart-ad0b8e2d-f217-469a-a13b-2d8fd0acff47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18713
41692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1871341692
Directory /workspace/0.usbdev_streaming_out/latest


Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.97547517
Short name T1257
Test name
Test status
Simulation time 2219905620 ps
CPU time 14.22 seconds
Started Aug 11 07:08:27 PM PDT 24
Finished Aug 11 07:08:41 PM PDT 24
Peak memory 207824 kb
Host smart-a6f8b632-31c7-405a-b676-712d69e43776
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97547517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host_h
andshake.97547517
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/0.usbdev_tx_rx_disruption.506132484
Short name T1017
Test name
Test status
Simulation time 526317326 ps
CPU time 1.52 seconds
Started Aug 11 07:08:32 PM PDT 24
Finished Aug 11 07:08:34 PM PDT 24
Peak memory 207520 kb
Host smart-2bf05283-bfd7-49d8-98e5-7e2b87fd41cd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506132484 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.usbdev_tx_rx_disruption.506132484
Directory /workspace/0.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/1.usbdev_alert_test.1953994051
Short name T3589
Test name
Test status
Simulation time 32015503 ps
CPU time 0.71 seconds
Started Aug 11 07:08:48 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 207556 kb
Host smart-52dd9c22-a425-4413-846d-33da831bd4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1953994051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1953994051
Directory /workspace/1.usbdev_alert_test/latest


Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2523734788
Short name T2168
Test name
Test status
Simulation time 12013682952 ps
CPU time 13.96 seconds
Started Aug 11 07:08:31 PM PDT 24
Finished Aug 11 07:08:45 PM PDT 24
Peak memory 207772 kb
Host smart-4286cf5a-535a-4da8-9534-d677cd901c8c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523734788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.2523734788
Directory /workspace/1.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3455521573
Short name T268
Test name
Test status
Simulation time 19806384741 ps
CPU time 23.76 seconds
Started Aug 11 07:08:44 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 207772 kb
Host smart-090c5c21-3893-4943-8d1b-9317c474924c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455521573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3455521573
Directory /workspace/1.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.335498901
Short name T690
Test name
Test status
Simulation time 29256915026 ps
CPU time 33.76 seconds
Started Aug 11 07:08:44 PM PDT 24
Finished Aug 11 07:09:17 PM PDT 24
Peak memory 207808 kb
Host smart-c8bb020a-e834-45eb-b2b1-d31b84dc47d8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335498901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon
_wake_resume.335498901
Directory /workspace/1.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/1.usbdev_av_buffer.2353582417
Short name T1825
Test name
Test status
Simulation time 165841488 ps
CPU time 0.9 seconds
Started Aug 11 07:08:37 PM PDT 24
Finished Aug 11 07:08:38 PM PDT 24
Peak memory 207576 kb
Host smart-96c93a02-7e92-458b-8775-096f15ffe03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23535
82417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2353582417
Directory /workspace/1.usbdev_av_buffer/latest


Test location /workspace/coverage/default/1.usbdev_av_overflow.3150750877
Short name T65
Test name
Test status
Simulation time 138233805 ps
CPU time 0.83 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:08:46 PM PDT 24
Peak memory 207512 kb
Host smart-63496d05-b964-4bff-ad51-ca621b51a0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507
50877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3150750877
Directory /workspace/1.usbdev_av_overflow/latest


Test location /workspace/coverage/default/1.usbdev_bitstuff_err.4279428177
Short name T3365
Test name
Test status
Simulation time 151479403 ps
CPU time 0.9 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:08:46 PM PDT 24
Peak memory 207468 kb
Host smart-f4c6d3e7-6a95-4c96-a7df-b56b0003ccda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42794
28177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.4279428177
Directory /workspace/1.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2729654117
Short name T929
Test name
Test status
Simulation time 201429530 ps
CPU time 0.9 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:08:46 PM PDT 24
Peak memory 207540 kb
Host smart-2b2b9acb-cd80-4aec-839d-92aa109a504c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27296
54117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2729654117
Directory /workspace/1.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.939068620
Short name T2353
Test name
Test status
Simulation time 1267765166 ps
CPU time 3.26 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 207728 kb
Host smart-39e79882-d00a-4ee6-be08-6c3a0cbf81f6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=939068620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.939068620
Directory /workspace/1.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/1.usbdev_device_address.695685915
Short name T391
Test name
Test status
Simulation time 48563506738 ps
CPU time 84.46 seconds
Started Aug 11 07:08:36 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 207812 kb
Host smart-8dbfe092-80ee-4d6f-a4ee-a9ac91ac5fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69568
5915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.695685915
Directory /workspace/1.usbdev_device_address/latest


Test location /workspace/coverage/default/1.usbdev_device_timeout.2291623763
Short name T3422
Test name
Test status
Simulation time 581854785 ps
CPU time 11.48 seconds
Started Aug 11 07:08:36 PM PDT 24
Finished Aug 11 07:08:48 PM PDT 24
Peak memory 207932 kb
Host smart-594820d4-b8b5-4405-9687-ef7146569f94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291623763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.2291623763
Directory /workspace/1.usbdev_device_timeout/latest


Test location /workspace/coverage/default/1.usbdev_disable_endpoint.23222002
Short name T852
Test name
Test status
Simulation time 747576080 ps
CPU time 1.72 seconds
Started Aug 11 07:08:36 PM PDT 24
Finished Aug 11 07:08:38 PM PDT 24
Peak memory 207468 kb
Host smart-bb1fb0c6-1def-4db1-bd38-4b7bdbe28def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23222
002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.23222002
Directory /workspace/1.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/1.usbdev_disconnected.3052475256
Short name T2479
Test name
Test status
Simulation time 133640912 ps
CPU time 0.8 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207472 kb
Host smart-78e1496d-c07e-4de9-9240-601f245d06cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30524
75256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3052475256
Directory /workspace/1.usbdev_disconnected/latest


Test location /workspace/coverage/default/1.usbdev_enable.1553182783
Short name T1661
Test name
Test status
Simulation time 38272572 ps
CPU time 0.7 seconds
Started Aug 11 07:08:34 PM PDT 24
Finished Aug 11 07:08:35 PM PDT 24
Peak memory 207520 kb
Host smart-aa930907-75b3-4806-ab1a-6158e3e8aaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15531
82783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1553182783
Directory /workspace/1.usbdev_enable/latest


Test location /workspace/coverage/default/1.usbdev_endpoint_access.1218996520
Short name T3414
Test name
Test status
Simulation time 1032930481 ps
CPU time 2.64 seconds
Started Aug 11 07:08:36 PM PDT 24
Finished Aug 11 07:08:39 PM PDT 24
Peak memory 207960 kb
Host smart-004f90cc-948b-4114-95d4-ca82727fd48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12189
96520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1218996520
Directory /workspace/1.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/1.usbdev_endpoint_types.1046961494
Short name T2718
Test name
Test status
Simulation time 336100815 ps
CPU time 1.15 seconds
Started Aug 11 07:08:48 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 207480 kb
Host smart-04a42ffc-a515-4025-ba14-f924b06128e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1046961494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.1046961494
Directory /workspace/1.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/1.usbdev_fifo_rst.2444110282
Short name T2752
Test name
Test status
Simulation time 157727481 ps
CPU time 1.59 seconds
Started Aug 11 07:08:38 PM PDT 24
Finished Aug 11 07:08:40 PM PDT 24
Peak memory 207764 kb
Host smart-285380ac-5d1b-4998-b6c8-8fceea0ff79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24441
10282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2444110282
Directory /workspace/1.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/1.usbdev_freq_hiclk.3123418226
Short name T1757
Test name
Test status
Simulation time 90178488696 ps
CPU time 150.26 seconds
Started Aug 11 07:08:43 PM PDT 24
Finished Aug 11 07:11:14 PM PDT 24
Peak memory 207828 kb
Host smart-fc315386-186b-4afc-bc0f-f72aec05cd37
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3123418226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.3123418226
Directory /workspace/1.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.1584026538
Short name T2813
Test name
Test status
Simulation time 104393490970 ps
CPU time 150.88 seconds
Started Aug 11 07:08:37 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207836 kb
Host smart-14c81f29-8e79-44fc-9060-ee67d91dca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584026538 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1584026538
Directory /workspace/1.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/1.usbdev_freq_loclk.3872088746
Short name T1216
Test name
Test status
Simulation time 105103623760 ps
CPU time 164.69 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:11:30 PM PDT 24
Peak memory 207848 kb
Host smart-2d16cfae-09b3-4448-9341-d707f0e0bc7e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3872088746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3872088746
Directory /workspace/1.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.2411752757
Short name T1026
Test name
Test status
Simulation time 116128010399 ps
CPU time 194.43 seconds
Started Aug 11 07:08:37 PM PDT 24
Finished Aug 11 07:11:52 PM PDT 24
Peak memory 207772 kb
Host smart-1692cd21-bec3-4112-8ee6-53951e6fbe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411752757 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.2411752757
Directory /workspace/1.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/1.usbdev_freq_phase.317113197
Short name T2243
Test name
Test status
Simulation time 119233750339 ps
CPU time 178.63 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 207740 kb
Host smart-56727f26-302e-4a3b-9c29-8e53478c3965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31711
3197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.317113197
Directory /workspace/1.usbdev_freq_phase/latest


Test location /workspace/coverage/default/1.usbdev_in_iso.3780980189
Short name T1832
Test name
Test status
Simulation time 220744880 ps
CPU time 1.03 seconds
Started Aug 11 07:08:35 PM PDT 24
Finished Aug 11 07:08:37 PM PDT 24
Peak memory 215840 kb
Host smart-434233d6-07a4-4ea5-9065-2613483761ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3780980189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3780980189
Directory /workspace/1.usbdev_in_iso/latest


Test location /workspace/coverage/default/1.usbdev_in_stall.676424111
Short name T2012
Test name
Test status
Simulation time 163852170 ps
CPU time 0.86 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207540 kb
Host smart-87676b76-1cc6-42d5-9e43-a01eedb43bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67642
4111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.676424111
Directory /workspace/1.usbdev_in_stall/latest


Test location /workspace/coverage/default/1.usbdev_in_trans.381412065
Short name T2269
Test name
Test status
Simulation time 259390299 ps
CPU time 1.02 seconds
Started Aug 11 07:08:36 PM PDT 24
Finished Aug 11 07:08:37 PM PDT 24
Peak memory 207508 kb
Host smart-371c86b0-5329-440d-86f7-7610fc5043b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38141
2065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.381412065
Directory /workspace/1.usbdev_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_invalid_sync.1469724498
Short name T1244
Test name
Test status
Simulation time 2831517156 ps
CPU time 21.83 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 224188 kb
Host smart-a167f90e-75f0-4ace-bcab-4fb7daeb2251
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1469724498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.1469724498
Directory /workspace/1.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/1.usbdev_link_in_err.2877536877
Short name T3237
Test name
Test status
Simulation time 158155647 ps
CPU time 0.83 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:08:46 PM PDT 24
Peak memory 207564 kb
Host smart-aedfb685-7685-44b5-b41a-fb3c9b0f03e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28775
36877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2877536877
Directory /workspace/1.usbdev_link_in_err/latest


Test location /workspace/coverage/default/1.usbdev_link_resume.2664627654
Short name T1622
Test name
Test status
Simulation time 6822169672 ps
CPU time 10.1 seconds
Started Aug 11 07:08:35 PM PDT 24
Finished Aug 11 07:08:45 PM PDT 24
Peak memory 216100 kb
Host smart-c326b68a-851f-4c9e-9859-e5dbf115cab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26646
27654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2664627654
Directory /workspace/1.usbdev_link_resume/latest


Test location /workspace/coverage/default/1.usbdev_link_suspend.1926775221
Short name T3558
Test name
Test status
Simulation time 4654745187 ps
CPU time 6.33 seconds
Started Aug 11 07:08:37 PM PDT 24
Finished Aug 11 07:08:44 PM PDT 24
Peak memory 216192 kb
Host smart-f5539929-a0c8-406e-b9b2-8da318078e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19267
75221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1926775221
Directory /workspace/1.usbdev_link_suspend/latest


Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.931372179
Short name T3027
Test name
Test status
Simulation time 2321675736 ps
CPU time 24.78 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:09:10 PM PDT 24
Peak memory 216092 kb
Host smart-8c04b5b5-360c-43cb-bc85-a97314af056a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=931372179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.931372179
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1087230550
Short name T2504
Test name
Test status
Simulation time 243257490 ps
CPU time 0.98 seconds
Started Aug 11 07:08:37 PM PDT 24
Finished Aug 11 07:08:39 PM PDT 24
Peak memory 207508 kb
Host smart-490cc229-aace-4bf0-a9c6-0ca58752ac95
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1087230550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1087230550
Directory /workspace/1.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2876983737
Short name T2173
Test name
Test status
Simulation time 201863621 ps
CPU time 0.93 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207576 kb
Host smart-4af0cea3-087f-42ad-b03c-1db4aeb7e163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28769
83737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2876983737
Directory /workspace/1.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.2698483326
Short name T1670
Test name
Test status
Simulation time 1381934285 ps
CPU time 37.77 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:09:24 PM PDT 24
Peak memory 217492 kb
Host smart-6338ccdf-2418-45a8-bf9d-42cbd810b14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26984
83326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.2698483326
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3627850301
Short name T1364
Test name
Test status
Simulation time 2943242709 ps
CPU time 87.28 seconds
Started Aug 11 07:08:45 PM PDT 24
Finished Aug 11 07:10:12 PM PDT 24
Peak memory 218308 kb
Host smart-51c0705f-789e-4468-9f9a-aecf26cefd8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3627850301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3627850301
Directory /workspace/1.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2073434562
Short name T3059
Test name
Test status
Simulation time 4084309616 ps
CPU time 33.93 seconds
Started Aug 11 07:08:44 PM PDT 24
Finished Aug 11 07:09:18 PM PDT 24
Peak memory 217812 kb
Host smart-01128922-96a0-4513-91cf-2f3fb67842f9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2073434562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2073434562
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2920659497
Short name T1419
Test name
Test status
Simulation time 164169338 ps
CPU time 0.9 seconds
Started Aug 11 07:08:49 PM PDT 24
Finished Aug 11 07:08:50 PM PDT 24
Peak memory 207476 kb
Host smart-45e8ba96-8f7d-448c-8072-2d5f79afa1bc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2920659497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2920659497
Directory /workspace/1.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1957626217
Short name T3021
Test name
Test status
Simulation time 162542810 ps
CPU time 0.85 seconds
Started Aug 11 07:08:44 PM PDT 24
Finished Aug 11 07:08:45 PM PDT 24
Peak memory 207572 kb
Host smart-d1174b5c-43d5-4bec-8b70-4ccf4a6db0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19576
26217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1957626217
Directory /workspace/1.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_nak_trans.4236222258
Short name T2428
Test name
Test status
Simulation time 247820289 ps
CPU time 0.96 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207440 kb
Host smart-49091523-424a-449d-b811-fc6f33f4542c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42362
22258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.4236222258
Directory /workspace/1.usbdev_nak_trans/latest


Test location /workspace/coverage/default/1.usbdev_out_iso.1273528656
Short name T1279
Test name
Test status
Simulation time 152266841 ps
CPU time 0.88 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207492 kb
Host smart-c1e29e2c-6aeb-4c42-a9cb-846a486047f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12735
28656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1273528656
Directory /workspace/1.usbdev_out_iso/latest


Test location /workspace/coverage/default/1.usbdev_out_stall.3149048276
Short name T2698
Test name
Test status
Simulation time 178173346 ps
CPU time 0.83 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207440 kb
Host smart-82093a16-a52e-49eb-a2ae-a273bdbd256e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31490
48276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3149048276
Directory /workspace/1.usbdev_out_stall/latest


Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3935730548
Short name T2578
Test name
Test status
Simulation time 178341840 ps
CPU time 0.87 seconds
Started Aug 11 07:08:43 PM PDT 24
Finished Aug 11 07:08:43 PM PDT 24
Peak memory 207560 kb
Host smart-8a9cf8f5-a6d4-452f-bee2-b077504766dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39357
30548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3935730548
Directory /workspace/1.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/1.usbdev_pending_in_trans.4056281191
Short name T3545
Test name
Test status
Simulation time 149859484 ps
CPU time 0.89 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207568 kb
Host smart-a6c091cd-4881-4cff-887f-33ec9afd20f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40562
81191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.4056281191
Directory /workspace/1.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1199555197
Short name T1727
Test name
Test status
Simulation time 225790643 ps
CPU time 1.09 seconds
Started Aug 11 07:08:48 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 207516 kb
Host smart-ca254034-2bd6-4009-a6dd-7c07469c1666
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1199555197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1199555197
Directory /workspace/1.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1283970808
Short name T3491
Test name
Test status
Simulation time 208723784 ps
CPU time 1.04 seconds
Started Aug 11 07:08:49 PM PDT 24
Finished Aug 11 07:08:50 PM PDT 24
Peak memory 207480 kb
Host smart-d1ede64b-813e-489c-b400-22f97c34c261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12839
70808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1283970808
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.404103956
Short name T1179
Test name
Test status
Simulation time 141938687 ps
CPU time 0.82 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207480 kb
Host smart-8a713048-90b0-4f02-bd98-60428c52771f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40410
3956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.404103956
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1497402665
Short name T3438
Test name
Test status
Simulation time 44861115 ps
CPU time 0.7 seconds
Started Aug 11 07:08:47 PM PDT 24
Finished Aug 11 07:08:48 PM PDT 24
Peak memory 207480 kb
Host smart-18acd1d4-66bf-4509-a582-57af046fd407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14974
02665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1497402665
Directory /workspace/1.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1351227388
Short name T2645
Test name
Test status
Simulation time 20296289382 ps
CPU time 54.5 seconds
Started Aug 11 07:08:48 PM PDT 24
Finished Aug 11 07:09:42 PM PDT 24
Peak memory 215956 kb
Host smart-f18562d3-2b39-48ba-8723-49ac88f04e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13512
27388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1351227388
Directory /workspace/1.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/1.usbdev_pkt_sent.853893712
Short name T621
Test name
Test status
Simulation time 195865929 ps
CPU time 0.9 seconds
Started Aug 11 07:08:44 PM PDT 24
Finished Aug 11 07:08:45 PM PDT 24
Peak memory 207448 kb
Host smart-83b42aa3-bbfb-4980-9e4a-6eac5aa5ba25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85389
3712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.853893712
Directory /workspace/1.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.577944359
Short name T1435
Test name
Test status
Simulation time 12862307134 ps
CPU time 104.16 seconds
Started Aug 11 07:08:44 PM PDT 24
Finished Aug 11 07:10:29 PM PDT 24
Peak memory 224236 kb
Host smart-2f428df0-a017-4682-ac29-0efa48922141
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=577944359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.577944359
Directory /workspace/1.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.44883471
Short name T927
Test name
Test status
Simulation time 3160417815 ps
CPU time 20.09 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:09:06 PM PDT 24
Peak memory 218460 kb
Host smart-3cb2957b-b80d-4dcf-8e2e-a9f637951090
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=44883471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.44883471
Directory /workspace/1.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/1.usbdev_rand_suspends.3578415841
Short name T1060
Test name
Test status
Simulation time 5841848155 ps
CPU time 25.24 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:09:11 PM PDT 24
Peak memory 219628 kb
Host smart-7717b5e4-5831-432a-bb9c-ded7bfaee5c9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578415841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3578415841
Directory /workspace/1.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2849015658
Short name T1841
Test name
Test status
Simulation time 194884710 ps
CPU time 0.95 seconds
Started Aug 11 07:08:43 PM PDT 24
Finished Aug 11 07:08:44 PM PDT 24
Peak memory 207500 kb
Host smart-fa8444cc-528b-45d9-8193-3bdd81e36d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28490
15658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2849015658
Directory /workspace/1.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.4287637769
Short name T2932
Test name
Test status
Simulation time 164792816 ps
CPU time 0.9 seconds
Started Aug 11 07:08:47 PM PDT 24
Finished Aug 11 07:08:48 PM PDT 24
Peak memory 207564 kb
Host smart-b9b7b140-cf2a-4c8a-9ec3-30eaf7578945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42876
37769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.4287637769
Directory /workspace/1.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_resume_link_active.162021326
Short name T2951
Test name
Test status
Simulation time 20158618983 ps
CPU time 22.4 seconds
Started Aug 11 07:08:52 PM PDT 24
Finished Aug 11 07:09:15 PM PDT 24
Peak memory 207652 kb
Host smart-7afef790-27ad-49f5-af51-a7d6be1e2773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16202
1326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.162021326
Directory /workspace/1.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3464645478
Short name T3514
Test name
Test status
Simulation time 165725993 ps
CPU time 0.95 seconds
Started Aug 11 07:08:50 PM PDT 24
Finished Aug 11 07:08:52 PM PDT 24
Peak memory 207516 kb
Host smart-24ee50ed-003d-44bc-a5d4-38648e230d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34646
45478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3464645478
Directory /workspace/1.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2234034340
Short name T1368
Test name
Test status
Simulation time 179392095 ps
CPU time 0.89 seconds
Started Aug 11 07:08:48 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 207552 kb
Host smart-2ce1cf32-6508-4b2a-9784-29d4d62c62d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22340
34340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2234034340
Directory /workspace/1.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/1.usbdev_sec_cm.1627045907
Short name T240
Test name
Test status
Simulation time 497960415 ps
CPU time 1.36 seconds
Started Aug 11 07:08:49 PM PDT 24
Finished Aug 11 07:08:51 PM PDT 24
Peak memory 223428 kb
Host smart-dc61bc70-daa9-4fea-864e-43a975fd048d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1627045907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1627045907
Directory /workspace/1.usbdev_sec_cm/latest


Test location /workspace/coverage/default/1.usbdev_setup_priority.475166790
Short name T3420
Test name
Test status
Simulation time 413172086 ps
CPU time 1.54 seconds
Started Aug 11 07:08:47 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 207492 kb
Host smart-8cf51421-df34-4999-b56c-84daeec263c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47516
6790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.475166790
Directory /workspace/1.usbdev_setup_priority/latest


Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.2460529047
Short name T552
Test name
Test status
Simulation time 216391038 ps
CPU time 0.95 seconds
Started Aug 11 07:08:54 PM PDT 24
Finished Aug 11 07:08:55 PM PDT 24
Peak memory 207536 kb
Host smart-2a3bfbd0-8789-4cbb-a960-f204cca0b980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24605
29047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2460529047
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/1.usbdev_setup_stage.1719259876
Short name T3
Test name
Test status
Simulation time 151940661 ps
CPU time 0.87 seconds
Started Aug 11 07:08:50 PM PDT 24
Finished Aug 11 07:08:51 PM PDT 24
Peak memory 207520 kb
Host smart-2fa69f6e-154b-4877-93a1-490c586cfefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17192
59876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1719259876
Directory /workspace/1.usbdev_setup_stage/latest


Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.357973586
Short name T1363
Test name
Test status
Simulation time 190398817 ps
CPU time 0.92 seconds
Started Aug 11 07:08:48 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 207520 kb
Host smart-01ef26b0-915b-4546-acc8-096bc519114d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35797
3586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.357973586
Directory /workspace/1.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/1.usbdev_smoke.2676746941
Short name T2832
Test name
Test status
Simulation time 235427880 ps
CPU time 1.01 seconds
Started Aug 11 07:08:50 PM PDT 24
Finished Aug 11 07:08:51 PM PDT 24
Peak memory 207504 kb
Host smart-2b850337-c319-4ace-851f-19becfcf8cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26767
46941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2676746941
Directory /workspace/1.usbdev_smoke/latest


Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.179119195
Short name T2087
Test name
Test status
Simulation time 2954629128 ps
CPU time 86.41 seconds
Started Aug 11 07:08:50 PM PDT 24
Finished Aug 11 07:10:16 PM PDT 24
Peak memory 224196 kb
Host smart-75184b88-c8fe-4c88-8e07-10a5866230ae
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=179119195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.179119195
Directory /workspace/1.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.4053193154
Short name T1982
Test name
Test status
Simulation time 173363389 ps
CPU time 0.88 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207576 kb
Host smart-bb7d51b1-fd9e-40fd-b9ae-daf790afc39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40531
93154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.4053193154
Directory /workspace/1.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/1.usbdev_stall_trans.661412874
Short name T2501
Test name
Test status
Simulation time 172465948 ps
CPU time 0.92 seconds
Started Aug 11 07:08:46 PM PDT 24
Finished Aug 11 07:08:47 PM PDT 24
Peak memory 207584 kb
Host smart-cbdc0548-cae1-4a9e-9c19-3a74e1ef6a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66141
2874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.661412874
Directory /workspace/1.usbdev_stall_trans/latest


Test location /workspace/coverage/default/1.usbdev_stream_len_max.848015128
Short name T2847
Test name
Test status
Simulation time 703986595 ps
CPU time 2.1 seconds
Started Aug 11 07:08:47 PM PDT 24
Finished Aug 11 07:08:50 PM PDT 24
Peak memory 207536 kb
Host smart-33030e52-73d2-496e-9f61-7c779a803303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84801
5128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.848015128
Directory /workspace/1.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/1.usbdev_streaming_out.2260557678
Short name T286
Test name
Test status
Simulation time 3572961991 ps
CPU time 107.02 seconds
Started Aug 11 07:08:54 PM PDT 24
Finished Aug 11 07:10:41 PM PDT 24
Peak memory 216096 kb
Host smart-7ca1d2e9-be19-4f22-9a05-54d96dba2872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22605
57678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2260557678
Directory /workspace/1.usbdev_streaming_out/latest


Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.1936038747
Short name T2921
Test name
Test status
Simulation time 3765721201 ps
CPU time 25.01 seconds
Started Aug 11 07:08:35 PM PDT 24
Finished Aug 11 07:09:01 PM PDT 24
Peak memory 207852 kb
Host smart-4c8017c6-a1d0-4837-987d-6eeb4a179e9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936038747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.1936038747
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/1.usbdev_tx_rx_disruption.2905669546
Short name T3143
Test name
Test status
Simulation time 491746174 ps
CPU time 1.52 seconds
Started Aug 11 07:08:52 PM PDT 24
Finished Aug 11 07:08:54 PM PDT 24
Peak memory 207584 kb
Host smart-d3cdca11-39ab-45bc-8111-8a716ec480b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905669546 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.usbdev_tx_rx_disruption.2905669546
Directory /workspace/1.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/10.usbdev_alert_test.2209567375
Short name T1436
Test name
Test status
Simulation time 33894787 ps
CPU time 0.66 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:10:54 PM PDT 24
Peak memory 207572 kb
Host smart-8b13916f-852a-4a81-897b-09cf97c8c723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2209567375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2209567375
Directory /workspace/10.usbdev_alert_test/latest


Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1702231454
Short name T966
Test name
Test status
Simulation time 6051895520 ps
CPU time 8.51 seconds
Started Aug 11 07:10:29 PM PDT 24
Finished Aug 11 07:10:38 PM PDT 24
Peak memory 216060 kb
Host smart-9588371e-7189-407a-aa36-2f38329463d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702231454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.1702231454
Directory /workspace/10.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3274475766
Short name T1107
Test name
Test status
Simulation time 16411866476 ps
CPU time 20.57 seconds
Started Aug 11 07:10:29 PM PDT 24
Finished Aug 11 07:10:50 PM PDT 24
Peak memory 216012 kb
Host smart-5278489e-cbfc-41c3-b9d3-d365324c8795
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274475766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3274475766
Directory /workspace/10.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.669707735
Short name T1219
Test name
Test status
Simulation time 23364549102 ps
CPU time 35.07 seconds
Started Aug 11 07:10:28 PM PDT 24
Finished Aug 11 07:11:04 PM PDT 24
Peak memory 216052 kb
Host smart-3ca11207-5a2f-4ad2-b026-ab53f24af882
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669707735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_ao
n_wake_resume.669707735
Directory /workspace/10.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/10.usbdev_av_buffer.1482071055
Short name T3626
Test name
Test status
Simulation time 150347824 ps
CPU time 0.83 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 207592 kb
Host smart-440cb24d-80d0-4136-a373-461554f1c046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14820
71055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1482071055
Directory /workspace/10.usbdev_av_buffer/latest


Test location /workspace/coverage/default/10.usbdev_bitstuff_err.4159430679
Short name T1430
Test name
Test status
Simulation time 161291266 ps
CPU time 0.9 seconds
Started Aug 11 07:10:32 PM PDT 24
Finished Aug 11 07:10:33 PM PDT 24
Peak memory 207472 kb
Host smart-86ea3a1c-97c1-4961-bd82-edd563b0cc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41594
30679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.4159430679
Directory /workspace/10.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.2913199168
Short name T1272
Test name
Test status
Simulation time 349783683 ps
CPU time 1.26 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 207504 kb
Host smart-714f5741-c7de-45d7-9dcc-fae5928e5aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29131
99168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2913199168
Directory /workspace/10.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.4229696550
Short name T357
Test name
Test status
Simulation time 660979641 ps
CPU time 1.88 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 207568 kb
Host smart-c5d65ac7-18ef-4bc7-af22-4ea9a3969b41
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4229696550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.4229696550
Directory /workspace/10.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/10.usbdev_device_timeout.611645538
Short name T2877
Test name
Test status
Simulation time 306750351 ps
CPU time 4.38 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:10:35 PM PDT 24
Peak memory 207692 kb
Host smart-06abaed1-cb1a-47bd-a0bf-6b787b17b4b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611645538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.611645538
Directory /workspace/10.usbdev_device_timeout/latest


Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1879705819
Short name T1598
Test name
Test status
Simulation time 900479013 ps
CPU time 1.89 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:10:33 PM PDT 24
Peak memory 207472 kb
Host smart-6c5f8777-02e5-4127-b484-780c13a900ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18797
05819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1879705819
Directory /workspace/10.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/10.usbdev_disconnected.56248183
Short name T2313
Test name
Test status
Simulation time 144052642 ps
CPU time 0.79 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 207568 kb
Host smart-41e3655c-88df-400e-bc05-047557f90dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56248
183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.56248183
Directory /workspace/10.usbdev_disconnected/latest


Test location /workspace/coverage/default/10.usbdev_enable.3796758997
Short name T2821
Test name
Test status
Simulation time 57753681 ps
CPU time 0.73 seconds
Started Aug 11 07:10:28 PM PDT 24
Finished Aug 11 07:10:29 PM PDT 24
Peak memory 207508 kb
Host smart-ef9582a0-2338-4306-ae4d-a41352fcc8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37967
58997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3796758997
Directory /workspace/10.usbdev_enable/latest


Test location /workspace/coverage/default/10.usbdev_endpoint_access.2106446046
Short name T586
Test name
Test status
Simulation time 896944300 ps
CPU time 2.64 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:10:41 PM PDT 24
Peak memory 207716 kb
Host smart-cca72f63-3e20-420b-a648-acc7e7f71950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21064
46046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2106446046
Directory /workspace/10.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/10.usbdev_fifo_rst.3554285860
Short name T1495
Test name
Test status
Simulation time 257725894 ps
CPU time 1.45 seconds
Started Aug 11 07:10:41 PM PDT 24
Finished Aug 11 07:10:43 PM PDT 24
Peak memory 207692 kb
Host smart-b41fb912-17fb-4a3e-8ab7-f961e16af5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
85860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3554285860
Directory /workspace/10.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/10.usbdev_in_iso.3676986205
Short name T3276
Test name
Test status
Simulation time 231169017 ps
CPU time 1.2 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:10:38 PM PDT 24
Peak memory 215940 kb
Host smart-d9dee6bb-eefe-41c3-9c8e-91c47d71bd21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3676986205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3676986205
Directory /workspace/10.usbdev_in_iso/latest


Test location /workspace/coverage/default/10.usbdev_in_stall.1769291184
Short name T2067
Test name
Test status
Simulation time 171111604 ps
CPU time 0.87 seconds
Started Aug 11 07:10:39 PM PDT 24
Finished Aug 11 07:10:40 PM PDT 24
Peak memory 207516 kb
Host smart-58513696-2211-4196-9bff-c2bdbac99c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17692
91184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1769291184
Directory /workspace/10.usbdev_in_stall/latest


Test location /workspace/coverage/default/10.usbdev_in_trans.3720595489
Short name T3342
Test name
Test status
Simulation time 226890337 ps
CPU time 0.98 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:10:39 PM PDT 24
Peak memory 207528 kb
Host smart-6a487dc4-eb05-4630-aad4-db81435ecc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37205
95489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3720595489
Directory /workspace/10.usbdev_in_trans/latest


Test location /workspace/coverage/default/10.usbdev_invalid_sync.2658664139
Short name T1085
Test name
Test status
Simulation time 4559305812 ps
CPU time 49.16 seconds
Started Aug 11 07:10:37 PM PDT 24
Finished Aug 11 07:11:27 PM PDT 24
Peak memory 224308 kb
Host smart-2b4b1727-64a2-4968-b7a4-46751b15e635
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2658664139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2658664139
Directory /workspace/10.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/10.usbdev_iso_retraction.1225677689
Short name T2701
Test name
Test status
Simulation time 12028663393 ps
CPU time 82.31 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:11:58 PM PDT 24
Peak memory 207792 kb
Host smart-6dc5607e-6e72-4ec9-9f2d-436b110be761
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1225677689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1225677689
Directory /workspace/10.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/10.usbdev_link_in_err.2721499041
Short name T2440
Test name
Test status
Simulation time 161231438 ps
CPU time 0.88 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:10:37 PM PDT 24
Peak memory 207532 kb
Host smart-7fcceb74-75f2-4648-8c0d-1015ef34ba09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27214
99041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.2721499041
Directory /workspace/10.usbdev_link_in_err/latest


Test location /workspace/coverage/default/10.usbdev_link_resume.1713232131
Short name T1348
Test name
Test status
Simulation time 13235530701 ps
CPU time 21.67 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:11:00 PM PDT 24
Peak memory 207868 kb
Host smart-6c6d1a9a-97a2-42e7-b03a-2d61c6243c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17132
32131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1713232131
Directory /workspace/10.usbdev_link_resume/latest


Test location /workspace/coverage/default/10.usbdev_link_suspend.1025580220
Short name T687
Test name
Test status
Simulation time 10697856282 ps
CPU time 16.02 seconds
Started Aug 11 07:10:45 PM PDT 24
Finished Aug 11 07:11:02 PM PDT 24
Peak memory 207812 kb
Host smart-cfd2e1de-d650-4925-9dd3-e37b6ce86791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10255
80220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1025580220
Directory /workspace/10.usbdev_link_suspend/latest


Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.4267086985
Short name T2424
Test name
Test status
Simulation time 3997881323 ps
CPU time 31.86 seconds
Started Aug 11 07:10:35 PM PDT 24
Finished Aug 11 07:11:07 PM PDT 24
Peak memory 218548 kb
Host smart-93a82012-98da-4395-9976-91a3e10b71c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4267086985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.4267086985
Directory /workspace/10.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3580137256
Short name T2980
Test name
Test status
Simulation time 2474300630 ps
CPU time 67.25 seconds
Started Aug 11 07:10:37 PM PDT 24
Finished Aug 11 07:11:45 PM PDT 24
Peak memory 216068 kb
Host smart-ce2b7996-473a-4aa1-b236-68e8b10218c1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3580137256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3580137256
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1297575451
Short name T1170
Test name
Test status
Simulation time 252249483 ps
CPU time 1.01 seconds
Started Aug 11 07:10:37 PM PDT 24
Finished Aug 11 07:10:38 PM PDT 24
Peak memory 207480 kb
Host smart-5e6081eb-b916-418f-b1d7-2e491555f83a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1297575451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1297575451
Directory /workspace/10.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.604048378
Short name T3299
Test name
Test status
Simulation time 188446329 ps
CPU time 0.96 seconds
Started Aug 11 07:10:40 PM PDT 24
Finished Aug 11 07:10:41 PM PDT 24
Peak memory 207548 kb
Host smart-4a5efe02-bbad-4cd2-b1e2-3832ee338818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60404
8378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.604048378
Directory /workspace/10.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.3127150657
Short name T3465
Test name
Test status
Simulation time 2411687015 ps
CPU time 19 seconds
Started Aug 11 07:10:46 PM PDT 24
Finished Aug 11 07:11:05 PM PDT 24
Peak memory 217892 kb
Host smart-18705128-a33e-4c33-a3c0-1509b1d6a868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31271
50657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.3127150657
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3542807286
Short name T129
Test name
Test status
Simulation time 3100797290 ps
CPU time 89.07 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 224192 kb
Host smart-4460e229-de25-46d4-b474-d604e8a1339b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3542807286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3542807286
Directory /workspace/10.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.4053843349
Short name T1962
Test name
Test status
Simulation time 2448910802 ps
CPU time 19.27 seconds
Started Aug 11 07:10:39 PM PDT 24
Finished Aug 11 07:10:58 PM PDT 24
Peak memory 224260 kb
Host smart-174d8374-39a1-48a0-80d1-160f43cb3b7c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4053843349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.4053843349
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.558281279
Short name T735
Test name
Test status
Simulation time 171171924 ps
CPU time 0.88 seconds
Started Aug 11 07:10:35 PM PDT 24
Finished Aug 11 07:10:36 PM PDT 24
Peak memory 207472 kb
Host smart-88800433-7c89-4a63-9d94-1e4c0984d537
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=558281279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.558281279
Directory /workspace/10.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1324657067
Short name T2175
Test name
Test status
Simulation time 155529096 ps
CPU time 0.83 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:10:39 PM PDT 24
Peak memory 207540 kb
Host smart-ff817dd0-ff67-4ac6-b65a-8abd4b67f743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13246
57067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1324657067
Directory /workspace/10.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_nak_trans.1460893328
Short name T161
Test name
Test status
Simulation time 196527705 ps
CPU time 0.95 seconds
Started Aug 11 07:10:35 PM PDT 24
Finished Aug 11 07:10:36 PM PDT 24
Peak memory 207576 kb
Host smart-6a5397a3-91b9-4bb3-a661-d4746fc8bc9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14608
93328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1460893328
Directory /workspace/10.usbdev_nak_trans/latest


Test location /workspace/coverage/default/10.usbdev_out_iso.968062377
Short name T568
Test name
Test status
Simulation time 217209323 ps
CPU time 0.95 seconds
Started Aug 11 07:10:46 PM PDT 24
Finished Aug 11 07:10:47 PM PDT 24
Peak memory 207204 kb
Host smart-be7aa056-085c-48f4-8896-043f0e8b7e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96806
2377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.968062377
Directory /workspace/10.usbdev_out_iso/latest


Test location /workspace/coverage/default/10.usbdev_out_stall.3769660601
Short name T1316
Test name
Test status
Simulation time 173415610 ps
CPU time 0.93 seconds
Started Aug 11 07:10:37 PM PDT 24
Finished Aug 11 07:10:38 PM PDT 24
Peak memory 207512 kb
Host smart-05bd97e2-b9b0-4c03-b2cb-7a7072cd6fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37696
60601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3769660601
Directory /workspace/10.usbdev_out_stall/latest


Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1652356300
Short name T1374
Test name
Test status
Simulation time 173406080 ps
CPU time 0.87 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:10:37 PM PDT 24
Peak memory 207576 kb
Host smart-e97c6334-06b6-4af0-bb90-6727b09fbc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16523
56300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1652356300
Directory /workspace/10.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1595184139
Short name T1019
Test name
Test status
Simulation time 170977219 ps
CPU time 0.89 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:10:37 PM PDT 24
Peak memory 207544 kb
Host smart-0158ddc5-6c79-409c-916f-00c3e613010a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15951
84139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1595184139
Directory /workspace/10.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.808697378
Short name T1610
Test name
Test status
Simulation time 218205161 ps
CPU time 0.97 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:10:39 PM PDT 24
Peak memory 207448 kb
Host smart-10649dcd-1bb7-4359-8934-cad1d1d72916
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=808697378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.808697378
Directory /workspace/10.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.4126779136
Short name T2112
Test name
Test status
Simulation time 149967949 ps
CPU time 0.82 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:10:39 PM PDT 24
Peak memory 207420 kb
Host smart-bded32ed-0a40-4845-ab8d-5d6a5c26619b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41267
79136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.4126779136
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2362348699
Short name T42
Test name
Test status
Simulation time 43973795 ps
CPU time 0.69 seconds
Started Aug 11 07:10:35 PM PDT 24
Finished Aug 11 07:10:36 PM PDT 24
Peak memory 207464 kb
Host smart-79183c78-7258-4889-a52d-ff55858b0192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23623
48699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2362348699
Directory /workspace/10.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/10.usbdev_pkt_buffer.77386948
Short name T296
Test name
Test status
Simulation time 15360935093 ps
CPU time 43.68 seconds
Started Aug 11 07:10:46 PM PDT 24
Finished Aug 11 07:11:30 PM PDT 24
Peak memory 224188 kb
Host smart-4e15194e-20b8-4769-995a-fc61211a395d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77386
948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.77386948
Directory /workspace/10.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/10.usbdev_pkt_received.511611771
Short name T2916
Test name
Test status
Simulation time 192701203 ps
CPU time 0.98 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:10:37 PM PDT 24
Peak memory 207440 kb
Host smart-bb2324d2-33a6-4ab8-9cfa-fa6a8e2c2a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51161
1771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.511611771
Directory /workspace/10.usbdev_pkt_received/latest


Test location /workspace/coverage/default/10.usbdev_pkt_sent.453669015
Short name T323
Test name
Test status
Simulation time 248312206 ps
CPU time 1.05 seconds
Started Aug 11 07:10:37 PM PDT 24
Finished Aug 11 07:10:39 PM PDT 24
Peak memory 207512 kb
Host smart-8797cada-3537-45d6-bd21-844d61d19171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45366
9015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.453669015
Directory /workspace/10.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3900424188
Short name T957
Test name
Test status
Simulation time 204345598 ps
CPU time 0.97 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:10:39 PM PDT 24
Peak memory 207544 kb
Host smart-f7d66df5-18a6-4075-aaf8-e6a9d9bcf93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39004
24188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3900424188
Directory /workspace/10.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1077988047
Short name T3231
Test name
Test status
Simulation time 180469425 ps
CPU time 0.9 seconds
Started Aug 11 07:10:39 PM PDT 24
Finished Aug 11 07:10:40 PM PDT 24
Peak memory 207548 kb
Host smart-e075e2e9-514c-4252-88ed-53369808dbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10779
88047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1077988047
Directory /workspace/10.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_resume_link_active.4131432869
Short name T3133
Test name
Test status
Simulation time 20156508179 ps
CPU time 22.52 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:11:01 PM PDT 24
Peak memory 207632 kb
Host smart-a4d26834-4eb6-4d26-bcd1-e24fc35cf0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41314
32869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.4131432869
Directory /workspace/10.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1014591222
Short name T1558
Test name
Test status
Simulation time 142353111 ps
CPU time 0.81 seconds
Started Aug 11 07:10:35 PM PDT 24
Finished Aug 11 07:10:36 PM PDT 24
Peak memory 207544 kb
Host smart-a7976082-2c74-4851-a0c9-604e9228e91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10145
91222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1014591222
Directory /workspace/10.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/10.usbdev_rx_full.1525684629
Short name T1508
Test name
Test status
Simulation time 319157476 ps
CPU time 1.15 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:10:40 PM PDT 24
Peak memory 207512 kb
Host smart-2ad956c1-d4a3-4adf-85e9-91221c938419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15256
84629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.1525684629
Directory /workspace/10.usbdev_rx_full/latest


Test location /workspace/coverage/default/10.usbdev_setup_stage.326789080
Short name T3295
Test name
Test status
Simulation time 168123995 ps
CPU time 0.83 seconds
Started Aug 11 07:10:37 PM PDT 24
Finished Aug 11 07:10:38 PM PDT 24
Peak memory 207500 kb
Host smart-508214df-b059-4567-bcd3-04a3ca2db3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32678
9080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.326789080
Directory /workspace/10.usbdev_setup_stage/latest


Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.332106695
Short name T2150
Test name
Test status
Simulation time 176583820 ps
CPU time 0.91 seconds
Started Aug 11 07:10:34 PM PDT 24
Finished Aug 11 07:10:35 PM PDT 24
Peak memory 207564 kb
Host smart-e53c538f-d67c-41f1-8bd8-fba8633cc922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210
6695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.332106695
Directory /workspace/10.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/10.usbdev_smoke.1246555586
Short name T1808
Test name
Test status
Simulation time 277377094 ps
CPU time 1.1 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:10:37 PM PDT 24
Peak memory 207592 kb
Host smart-83de552b-2b7e-455a-b82d-fcb29ca0a86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465
55586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1246555586
Directory /workspace/10.usbdev_smoke/latest


Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3231624441
Short name T3007
Test name
Test status
Simulation time 2091932777 ps
CPU time 21.66 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:10:58 PM PDT 24
Peak memory 217712 kb
Host smart-f0602de1-b40d-4d2e-858b-ae9f9cb260ab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3231624441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3231624441
Directory /workspace/10.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1384295938
Short name T1827
Test name
Test status
Simulation time 168387770 ps
CPU time 0.87 seconds
Started Aug 11 07:10:35 PM PDT 24
Finished Aug 11 07:10:36 PM PDT 24
Peak memory 207492 kb
Host smart-7e4adab2-153e-42f4-9ccf-d4c1833e9a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13842
95938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1384295938
Directory /workspace/10.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/10.usbdev_stall_trans.896271510
Short name T1433
Test name
Test status
Simulation time 151948486 ps
CPU time 0.85 seconds
Started Aug 11 07:10:38 PM PDT 24
Finished Aug 11 07:10:39 PM PDT 24
Peak memory 207488 kb
Host smart-8fbf3b4e-8cbd-4138-b689-59f0e0c65752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89627
1510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.896271510
Directory /workspace/10.usbdev_stall_trans/latest


Test location /workspace/coverage/default/10.usbdev_stream_len_max.3389935889
Short name T3113
Test name
Test status
Simulation time 757288102 ps
CPU time 1.93 seconds
Started Aug 11 07:10:37 PM PDT 24
Finished Aug 11 07:10:39 PM PDT 24
Peak memory 207504 kb
Host smart-327ad228-a164-4eac-9d3b-04399ee61b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
35889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3389935889
Directory /workspace/10.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/10.usbdev_streaming_out.2946190640
Short name T3093
Test name
Test status
Simulation time 2165385940 ps
CPU time 22.53 seconds
Started Aug 11 07:10:46 PM PDT 24
Finished Aug 11 07:11:09 PM PDT 24
Peak memory 216068 kb
Host smart-753c5469-3101-4d53-be1d-ecdd1a5250de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29461
90640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2946190640
Directory /workspace/10.usbdev_streaming_out/latest


Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.3613493786
Short name T3017
Test name
Test status
Simulation time 869306648 ps
CPU time 18.61 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207664 kb
Host smart-88627cb0-43d0-4d33-abb0-0d1bf6777121
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613493786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.3613493786
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/10.usbdev_tx_rx_disruption.453856032
Short name T193
Test name
Test status
Simulation time 488898545 ps
CPU time 1.42 seconds
Started Aug 11 07:10:36 PM PDT 24
Finished Aug 11 07:10:37 PM PDT 24
Peak memory 207504 kb
Host smart-a56c1ca2-e90a-4e45-bfcd-b39046d2e8c8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453856032 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.usbdev_tx_rx_disruption.453856032
Directory /workspace/10.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/100.usbdev_endpoint_types.1151348143
Short name T2755
Test name
Test status
Simulation time 304906852 ps
CPU time 1.14 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 207400 kb
Host smart-b3c5e1de-684b-4b2a-81ae-fc5bf248749b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1151348143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.1151348143
Directory /workspace/100.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/100.usbdev_tx_rx_disruption.1144248287
Short name T713
Test name
Test status
Simulation time 555631573 ps
CPU time 1.53 seconds
Started Aug 11 07:16:47 PM PDT 24
Finished Aug 11 07:16:49 PM PDT 24
Peak memory 207588 kb
Host smart-642d9661-a69a-40bd-a8d7-1a05d7663b7f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144248287 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.usbdev_tx_rx_disruption.1144248287
Directory /workspace/100.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/101.usbdev_endpoint_types.987023130
Short name T3331
Test name
Test status
Simulation time 814321143 ps
CPU time 1.84 seconds
Started Aug 11 07:16:49 PM PDT 24
Finished Aug 11 07:16:51 PM PDT 24
Peak memory 207500 kb
Host smart-881a5890-45b2-4d36-93de-457dcc608e94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=987023130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.987023130
Directory /workspace/101.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/101.usbdev_tx_rx_disruption.2682129048
Short name T648
Test name
Test status
Simulation time 613194371 ps
CPU time 1.69 seconds
Started Aug 11 07:16:59 PM PDT 24
Finished Aug 11 07:17:01 PM PDT 24
Peak memory 207596 kb
Host smart-7105455c-0283-4a53-97bd-90a7c76cd586
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682129048 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.usbdev_tx_rx_disruption.2682129048
Directory /workspace/101.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/102.usbdev_tx_rx_disruption.1640544413
Short name T1534
Test name
Test status
Simulation time 603913968 ps
CPU time 1.61 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 207564 kb
Host smart-3df04121-f382-4160-8406-3e12df618940
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640544413 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.usbdev_tx_rx_disruption.1640544413
Directory /workspace/102.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/103.usbdev_tx_rx_disruption.3873708146
Short name T2552
Test name
Test status
Simulation time 454104339 ps
CPU time 1.52 seconds
Started Aug 11 07:16:58 PM PDT 24
Finished Aug 11 07:17:00 PM PDT 24
Peak memory 207600 kb
Host smart-f1d23a31-6cde-41ac-b5bc-214255d8b7b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873708146 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.usbdev_tx_rx_disruption.3873708146
Directory /workspace/103.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/104.usbdev_endpoint_types.1162824541
Short name T3203
Test name
Test status
Simulation time 169835370 ps
CPU time 0.9 seconds
Started Aug 11 07:16:49 PM PDT 24
Finished Aug 11 07:16:50 PM PDT 24
Peak memory 207456 kb
Host smart-a1bc1be1-76ac-4cb6-bad0-fc66945ea304
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1162824541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.1162824541
Directory /workspace/104.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/104.usbdev_tx_rx_disruption.2665705600
Short name T1749
Test name
Test status
Simulation time 522465327 ps
CPU time 1.62 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 207544 kb
Host smart-a8470675-a5f1-4bf7-b78b-28ec1afa4d26
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665705600 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.usbdev_tx_rx_disruption.2665705600
Directory /workspace/104.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/105.usbdev_endpoint_types.1189498008
Short name T500
Test name
Test status
Simulation time 434563538 ps
CPU time 1.31 seconds
Started Aug 11 07:16:51 PM PDT 24
Finished Aug 11 07:16:52 PM PDT 24
Peak memory 207536 kb
Host smart-9bc6bd9b-efc6-44fe-a2f8-572185ae5759
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1189498008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.1189498008
Directory /workspace/105.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/105.usbdev_tx_rx_disruption.2379751494
Short name T2212
Test name
Test status
Simulation time 567431882 ps
CPU time 1.54 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207500 kb
Host smart-10fb1f12-a018-46be-958e-94bf43a3acf6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379751494 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.usbdev_tx_rx_disruption.2379751494
Directory /workspace/105.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/106.usbdev_endpoint_types.2916857081
Short name T2497
Test name
Test status
Simulation time 278641957 ps
CPU time 1.08 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207736 kb
Host smart-8919e005-cf80-4f56-a102-7b613831dd92
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2916857081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.2916857081
Directory /workspace/106.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/106.usbdev_tx_rx_disruption.714014324
Short name T701
Test name
Test status
Simulation time 560578286 ps
CPU time 1.77 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207544 kb
Host smart-a3b444aa-4d7c-4417-8812-bf29c6a881dc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714014324 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 106.usbdev_tx_rx_disruption.714014324
Directory /workspace/106.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/108.usbdev_tx_rx_disruption.3650927210
Short name T254
Test name
Test status
Simulation time 489031881 ps
CPU time 1.5 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207556 kb
Host smart-536e5026-df36-480d-a1d0-e29ed0d8798e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650927210 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.usbdev_tx_rx_disruption.3650927210
Directory /workspace/108.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/109.usbdev_endpoint_types.1167123157
Short name T411
Test name
Test status
Simulation time 287505758 ps
CPU time 1.06 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:06 PM PDT 24
Peak memory 207572 kb
Host smart-9fc907f2-bb7b-4220-b49d-cc515a78b45e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1167123157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.1167123157
Directory /workspace/109.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/109.usbdev_tx_rx_disruption.2895108947
Short name T1877
Test name
Test status
Simulation time 638998386 ps
CPU time 1.78 seconds
Started Aug 11 07:16:55 PM PDT 24
Finished Aug 11 07:16:57 PM PDT 24
Peak memory 207516 kb
Host smart-5646f10c-8154-47d5-8530-49f6325bd85c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895108947 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.usbdev_tx_rx_disruption.2895108947
Directory /workspace/109.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/11.usbdev_alert_test.3891946046
Short name T3009
Test name
Test status
Simulation time 73273791 ps
CPU time 0.72 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:10:54 PM PDT 24
Peak memory 207532 kb
Host smart-e7930c98-04be-4f79-b86d-0aa4b553559c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3891946046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3891946046
Directory /workspace/11.usbdev_alert_test/latest


Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1356531014
Short name T2677
Test name
Test status
Simulation time 3701009227 ps
CPU time 6.35 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:10:59 PM PDT 24
Peak memory 216012 kb
Host smart-10cdeb20-4eac-4b42-9077-c063a98b67f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356531014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.1356531014
Directory /workspace/11.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2201436687
Short name T2164
Test name
Test status
Simulation time 18810368715 ps
CPU time 22.32 seconds
Started Aug 11 07:10:41 PM PDT 24
Finished Aug 11 07:11:04 PM PDT 24
Peak memory 207780 kb
Host smart-b21a4ea3-5994-4644-9dc6-eff1ea04aaa4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201436687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2201436687
Directory /workspace/11.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.427084293
Short name T3281
Test name
Test status
Simulation time 25177452742 ps
CPU time 29.65 seconds
Started Aug 11 07:10:41 PM PDT 24
Finished Aug 11 07:11:11 PM PDT 24
Peak memory 215984 kb
Host smart-68d5b72b-53ea-4bca-9b46-1d21a32ca2b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427084293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ao
n_wake_resume.427084293
Directory /workspace/11.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/11.usbdev_av_buffer.517976055
Short name T2092
Test name
Test status
Simulation time 256881661 ps
CPU time 1.01 seconds
Started Aug 11 07:10:41 PM PDT 24
Finished Aug 11 07:10:42 PM PDT 24
Peak memory 207544 kb
Host smart-688c4d20-bb40-4058-a18d-4adca5752cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51797
6055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.517976055
Directory /workspace/11.usbdev_av_buffer/latest


Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3835202309
Short name T1535
Test name
Test status
Simulation time 158671400 ps
CPU time 0.89 seconds
Started Aug 11 07:10:43 PM PDT 24
Finished Aug 11 07:10:44 PM PDT 24
Peak memory 207576 kb
Host smart-6b635acf-fc49-47a4-9dd6-d680569fd4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38352
02309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3835202309
Directory /workspace/11.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.470015900
Short name T1354
Test name
Test status
Simulation time 473485247 ps
CPU time 1.73 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:10:55 PM PDT 24
Peak memory 207552 kb
Host smart-5b1c6785-4a4b-4bbc-9bc5-54bd3ccbdbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47001
5900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.470015900
Directory /workspace/11.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2697803141
Short name T353
Test name
Test status
Simulation time 957654140 ps
CPU time 2.39 seconds
Started Aug 11 07:10:44 PM PDT 24
Finished Aug 11 07:10:46 PM PDT 24
Peak memory 207684 kb
Host smart-7df24527-d0a4-4b71-96c1-163a48010cc1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2697803141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2697803141
Directory /workspace/11.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/11.usbdev_device_address.4292445853
Short name T1903
Test name
Test status
Simulation time 46762367740 ps
CPU time 82.91 seconds
Started Aug 11 07:10:44 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 207740 kb
Host smart-552d05fb-5418-4a33-974f-3ced2fd9fcef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42924
45853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.4292445853
Directory /workspace/11.usbdev_device_address/latest


Test location /workspace/coverage/default/11.usbdev_device_timeout.3348907153
Short name T2809
Test name
Test status
Simulation time 906476628 ps
CPU time 19.3 seconds
Started Aug 11 07:10:43 PM PDT 24
Finished Aug 11 07:11:02 PM PDT 24
Peak memory 207784 kb
Host smart-343ba3ec-ac28-4d06-ab1e-3f9bcac8a42f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348907153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.3348907153
Directory /workspace/11.usbdev_device_timeout/latest


Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2410702130
Short name T1591
Test name
Test status
Simulation time 758973156 ps
CPU time 1.98 seconds
Started Aug 11 07:10:43 PM PDT 24
Finished Aug 11 07:10:45 PM PDT 24
Peak memory 207720 kb
Host smart-9ffc2eea-ca33-4e32-a62a-dc7094e52ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24107
02130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2410702130
Directory /workspace/11.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/11.usbdev_disconnected.3727488411
Short name T2266
Test name
Test status
Simulation time 142233692 ps
CPU time 0.81 seconds
Started Aug 11 07:10:43 PM PDT 24
Finished Aug 11 07:10:44 PM PDT 24
Peak memory 207480 kb
Host smart-ae27011e-bad3-48c3-8aa8-53bd8a3d4e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37274
88411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3727488411
Directory /workspace/11.usbdev_disconnected/latest


Test location /workspace/coverage/default/11.usbdev_enable.2919445445
Short name T1991
Test name
Test status
Simulation time 33109018 ps
CPU time 0.73 seconds
Started Aug 11 07:10:44 PM PDT 24
Finished Aug 11 07:10:44 PM PDT 24
Peak memory 207448 kb
Host smart-2898d252-c0c1-4f35-af4a-1db70f8430a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29194
45445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2919445445
Directory /workspace/11.usbdev_enable/latest


Test location /workspace/coverage/default/11.usbdev_endpoint_access.1316418320
Short name T765
Test name
Test status
Simulation time 954163543 ps
CPU time 2.63 seconds
Started Aug 11 07:10:43 PM PDT 24
Finished Aug 11 07:10:45 PM PDT 24
Peak memory 207700 kb
Host smart-9a827d78-fc62-4c76-b6eb-7758d302d1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13164
18320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1316418320
Directory /workspace/11.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/11.usbdev_endpoint_types.3617728200
Short name T2653
Test name
Test status
Simulation time 170831753 ps
CPU time 0.96 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:10:54 PM PDT 24
Peak memory 207512 kb
Host smart-1957e9ec-4601-42d2-9df5-a68ff3d2203a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3617728200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.3617728200
Directory /workspace/11.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/11.usbdev_in_iso.2735448754
Short name T1043
Test name
Test status
Simulation time 241880271 ps
CPU time 1.15 seconds
Started Aug 11 07:10:43 PM PDT 24
Finished Aug 11 07:10:44 PM PDT 24
Peak memory 216156 kb
Host smart-380f97bc-a55c-4ebd-96bf-fd40ac22aead
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2735448754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2735448754
Directory /workspace/11.usbdev_in_iso/latest


Test location /workspace/coverage/default/11.usbdev_in_stall.3328873413
Short name T3378
Test name
Test status
Simulation time 158969377 ps
CPU time 0.91 seconds
Started Aug 11 07:10:42 PM PDT 24
Finished Aug 11 07:10:43 PM PDT 24
Peak memory 207536 kb
Host smart-4e60b580-9b35-4b1b-80e3-1ea59c1485a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33288
73413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3328873413
Directory /workspace/11.usbdev_in_stall/latest


Test location /workspace/coverage/default/11.usbdev_in_trans.501128817
Short name T2930
Test name
Test status
Simulation time 171209626 ps
CPU time 0.94 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:10:54 PM PDT 24
Peak memory 207548 kb
Host smart-4c88cd86-e5df-4e1a-b9b2-4630307af2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50112
8817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.501128817
Directory /workspace/11.usbdev_in_trans/latest


Test location /workspace/coverage/default/11.usbdev_invalid_sync.1149781165
Short name T2373
Test name
Test status
Simulation time 4077500568 ps
CPU time 106.47 seconds
Started Aug 11 07:10:41 PM PDT 24
Finished Aug 11 07:12:28 PM PDT 24
Peak memory 224168 kb
Host smart-66fe3581-fa03-481e-94c6-be6e61676a03
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1149781165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1149781165
Directory /workspace/11.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/11.usbdev_iso_retraction.3951207834
Short name T3186
Test name
Test status
Simulation time 8124345743 ps
CPU time 98.67 seconds
Started Aug 11 07:10:41 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207776 kb
Host smart-9dde661e-d14f-48b3-9406-be5c62cfad46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3951207834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.3951207834
Directory /workspace/11.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/11.usbdev_link_in_err.272708036
Short name T1401
Test name
Test status
Simulation time 156948526 ps
CPU time 0.91 seconds
Started Aug 11 07:10:45 PM PDT 24
Finished Aug 11 07:10:46 PM PDT 24
Peak memory 207484 kb
Host smart-b1d65bd3-77e5-494d-84de-927f7d1f17aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27270
8036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.272708036
Directory /workspace/11.usbdev_link_in_err/latest


Test location /workspace/coverage/default/11.usbdev_link_resume.2179765097
Short name T1925
Test name
Test status
Simulation time 8520361122 ps
CPU time 14.01 seconds
Started Aug 11 07:10:42 PM PDT 24
Finished Aug 11 07:10:56 PM PDT 24
Peak memory 216132 kb
Host smart-585656ab-ef38-4177-89fa-cc9ac4c447f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21797
65097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.2179765097
Directory /workspace/11.usbdev_link_resume/latest


Test location /workspace/coverage/default/11.usbdev_link_suspend.867323449
Short name T1104
Test name
Test status
Simulation time 3407797393 ps
CPU time 5.8 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:10:59 PM PDT 24
Peak memory 207808 kb
Host smart-ce11927e-6da9-4608-b3b5-9c228848b7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86732
3449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.867323449
Directory /workspace/11.usbdev_link_suspend/latest


Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.586531585
Short name T402
Test name
Test status
Simulation time 3147309425 ps
CPU time 23.36 seconds
Started Aug 11 07:10:42 PM PDT 24
Finished Aug 11 07:11:05 PM PDT 24
Peak memory 224276 kb
Host smart-b7c51807-eb27-46e0-9f60-6fffea5c6139
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=586531585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.586531585
Directory /workspace/11.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.1630968137
Short name T2799
Test name
Test status
Simulation time 2306045636 ps
CPU time 66.13 seconds
Started Aug 11 07:10:41 PM PDT 24
Finished Aug 11 07:11:47 PM PDT 24
Peak memory 216120 kb
Host smart-ef4d83ac-84e2-4abb-b5e3-3d14c6b178f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1630968137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.1630968137
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2811181981
Short name T2137
Test name
Test status
Simulation time 270324723 ps
CPU time 0.96 seconds
Started Aug 11 07:10:41 PM PDT 24
Finished Aug 11 07:10:42 PM PDT 24
Peak memory 207568 kb
Host smart-110a5bfc-e89c-4da1-9567-afbf692eb284
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2811181981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2811181981
Directory /workspace/11.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3235218890
Short name T846
Test name
Test status
Simulation time 198299513 ps
CPU time 1 seconds
Started Aug 11 07:10:42 PM PDT 24
Finished Aug 11 07:10:43 PM PDT 24
Peak memory 207580 kb
Host smart-a42573ee-bccf-4364-a488-2c48899dfa8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32352
18890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3235218890
Directory /workspace/11.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.660088100
Short name T1589
Test name
Test status
Simulation time 2637638788 ps
CPU time 20.3 seconds
Started Aug 11 07:10:40 PM PDT 24
Finished Aug 11 07:11:00 PM PDT 24
Peak memory 218148 kb
Host smart-659aeb94-baa4-47ab-abb9-b6a505b3b6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66008
8100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.660088100
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3163572049
Short name T1644
Test name
Test status
Simulation time 3307037646 ps
CPU time 92.95 seconds
Started Aug 11 07:10:44 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 215080 kb
Host smart-25fd8ca3-67c4-4144-8370-3ca0a318bfc2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3163572049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3163572049
Directory /workspace/11.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.903469846
Short name T3339
Test name
Test status
Simulation time 3128864052 ps
CPU time 91.09 seconds
Started Aug 11 07:10:42 PM PDT 24
Finished Aug 11 07:12:13 PM PDT 24
Peak memory 217576 kb
Host smart-cfadcf50-9722-490f-af11-07e3327df185
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=903469846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.903469846
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3893951634
Short name T2302
Test name
Test status
Simulation time 203711802 ps
CPU time 0.89 seconds
Started Aug 11 07:10:48 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207580 kb
Host smart-0ab86844-60bb-445e-b685-9d348c42dcce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3893951634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3893951634
Directory /workspace/11.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2152190880
Short name T868
Test name
Test status
Simulation time 147116838 ps
CPU time 0.81 seconds
Started Aug 11 07:10:48 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207576 kb
Host smart-67f01b26-8cda-41c9-8ba5-9e03902c5f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21521
90880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2152190880
Directory /workspace/11.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_out_iso.2629499273
Short name T3567
Test name
Test status
Simulation time 199138537 ps
CPU time 0.96 seconds
Started Aug 11 07:10:48 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207568 kb
Host smart-60b1c224-cc98-4917-a117-6808072aa575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26294
99273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2629499273
Directory /workspace/11.usbdev_out_iso/latest


Test location /workspace/coverage/default/11.usbdev_out_stall.1395886293
Short name T1086
Test name
Test status
Simulation time 165867123 ps
CPU time 0.86 seconds
Started Aug 11 07:10:49 PM PDT 24
Finished Aug 11 07:10:50 PM PDT 24
Peak memory 207580 kb
Host smart-d16494db-a30a-4264-b313-2ac317206da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13958
86293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1395886293
Directory /workspace/11.usbdev_out_stall/latest


Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2850316252
Short name T747
Test name
Test status
Simulation time 165407166 ps
CPU time 0.86 seconds
Started Aug 11 07:10:49 PM PDT 24
Finished Aug 11 07:10:50 PM PDT 24
Peak memory 207568 kb
Host smart-aa6983f9-f214-4d2b-aee2-9dfba7cdda6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28503
16252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2850316252
Directory /workspace/11.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1545592577
Short name T1846
Test name
Test status
Simulation time 151112260 ps
CPU time 0.88 seconds
Started Aug 11 07:10:48 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207480 kb
Host smart-9798ae03-7b68-4d7d-8693-cf369d35b1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15455
92577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1545592577
Directory /workspace/11.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.915902332
Short name T3107
Test name
Test status
Simulation time 256197467 ps
CPU time 1.17 seconds
Started Aug 11 07:10:47 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207508 kb
Host smart-30d9b717-84a4-4511-8f48-5fbf94f1e84b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=915902332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.915902332
Directory /workspace/11.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1753569428
Short name T2433
Test name
Test status
Simulation time 153670171 ps
CPU time 0.9 seconds
Started Aug 11 07:10:47 PM PDT 24
Finished Aug 11 07:10:48 PM PDT 24
Peak memory 207452 kb
Host smart-bf54603c-8ede-42b6-84a2-5e60f09c9ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17535
69428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1753569428
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3082258337
Short name T1683
Test name
Test status
Simulation time 36666463 ps
CPU time 0.67 seconds
Started Aug 11 07:10:47 PM PDT 24
Finished Aug 11 07:10:47 PM PDT 24
Peak memory 207536 kb
Host smart-b2416f7c-328e-4f1a-be8e-ff81c5a74af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30822
58337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3082258337
Directory /workspace/11.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3366235409
Short name T1898
Test name
Test status
Simulation time 18489600742 ps
CPU time 45.09 seconds
Started Aug 11 07:10:47 PM PDT 24
Finished Aug 11 07:11:32 PM PDT 24
Peak memory 216072 kb
Host smart-fae713df-814d-428b-85b9-9e8a8151e0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33662
35409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3366235409
Directory /workspace/11.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/11.usbdev_pkt_received.875127560
Short name T649
Test name
Test status
Simulation time 211451826 ps
CPU time 1.04 seconds
Started Aug 11 07:10:47 PM PDT 24
Finished Aug 11 07:10:48 PM PDT 24
Peak memory 207572 kb
Host smart-cac89bf0-44c8-49dc-bde4-bb20247e048f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87512
7560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.875127560
Directory /workspace/11.usbdev_pkt_received/latest


Test location /workspace/coverage/default/11.usbdev_pkt_sent.3591354815
Short name T2597
Test name
Test status
Simulation time 200160465 ps
CPU time 0.95 seconds
Started Aug 11 07:10:49 PM PDT 24
Finished Aug 11 07:10:50 PM PDT 24
Peak memory 207436 kb
Host smart-e2255d4f-b60e-421f-9a3d-fa7091690ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35913
54815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3591354815
Directory /workspace/11.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.1718958881
Short name T2423
Test name
Test status
Simulation time 273497634 ps
CPU time 1.09 seconds
Started Aug 11 07:10:48 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207520 kb
Host smart-0d7184e0-86fd-4a56-8b80-480f025dcb01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17189
58881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.1718958881
Directory /workspace/11.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2783071672
Short name T34
Test name
Test status
Simulation time 185348516 ps
CPU time 0.93 seconds
Started Aug 11 07:10:48 PM PDT 24
Finished Aug 11 07:10:50 PM PDT 24
Peak memory 207576 kb
Host smart-0b542378-b805-4cc6-9031-3f323239d7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27830
71672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2783071672
Directory /workspace/11.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_resume_link_active.149028285
Short name T1699
Test name
Test status
Simulation time 20253028203 ps
CPU time 26.78 seconds
Started Aug 11 07:10:51 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 206648 kb
Host smart-5ef98fbc-324d-451c-b860-9fe64272451a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14902
8285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.149028285
Directory /workspace/11.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/11.usbdev_rx_crc_err.956356399
Short name T2971
Test name
Test status
Simulation time 168975457 ps
CPU time 0.9 seconds
Started Aug 11 07:10:47 PM PDT 24
Finished Aug 11 07:10:47 PM PDT 24
Peak memory 207488 kb
Host smart-5e065a3f-f1c8-4192-9e14-8a58bdc3a220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95635
6399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.956356399
Directory /workspace/11.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/11.usbdev_rx_full.3338572276
Short name T653
Test name
Test status
Simulation time 372059023 ps
CPU time 1.4 seconds
Started Aug 11 07:10:49 PM PDT 24
Finished Aug 11 07:10:50 PM PDT 24
Peak memory 207576 kb
Host smart-78b94fe9-d5e0-4e60-9d91-24a2ea6a7756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33385
72276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.3338572276
Directory /workspace/11.usbdev_rx_full/latest


Test location /workspace/coverage/default/11.usbdev_setup_stage.1589872877
Short name T709
Test name
Test status
Simulation time 162650008 ps
CPU time 0.88 seconds
Started Aug 11 07:10:47 PM PDT 24
Finished Aug 11 07:10:48 PM PDT 24
Peak memory 207488 kb
Host smart-f5f5e83d-804a-49d0-b3e3-6516cfa7aae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15898
72877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1589872877
Directory /workspace/11.usbdev_setup_stage/latest


Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2988934406
Short name T1292
Test name
Test status
Simulation time 150114000 ps
CPU time 0.86 seconds
Started Aug 11 07:10:51 PM PDT 24
Finished Aug 11 07:10:52 PM PDT 24
Peak memory 206564 kb
Host smart-d706b3a4-659b-498b-bb0f-0f0d5f846387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29889
34406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2988934406
Directory /workspace/11.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/11.usbdev_smoke.220562525
Short name T1550
Test name
Test status
Simulation time 199652850 ps
CPU time 0.98 seconds
Started Aug 11 07:10:49 PM PDT 24
Finished Aug 11 07:10:50 PM PDT 24
Peak memory 207572 kb
Host smart-87e5b80f-6d4d-4d03-863f-37deb758ba72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22056
2525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.220562525
Directory /workspace/11.usbdev_smoke/latest


Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3276646308
Short name T3493
Test name
Test status
Simulation time 2015033770 ps
CPU time 16 seconds
Started Aug 11 07:10:51 PM PDT 24
Finished Aug 11 07:11:07 PM PDT 24
Peak memory 223144 kb
Host smart-4539e656-2367-41ab-845e-adbbd231638d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3276646308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3276646308
Directory /workspace/11.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2569897674
Short name T2525
Test name
Test status
Simulation time 223872183 ps
CPU time 0.93 seconds
Started Aug 11 07:10:48 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207520 kb
Host smart-8fe37eec-401b-4300-baea-ad085e220165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25698
97674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2569897674
Directory /workspace/11.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/11.usbdev_stall_trans.3624052896
Short name T2779
Test name
Test status
Simulation time 208126945 ps
CPU time 0.92 seconds
Started Aug 11 07:10:51 PM PDT 24
Finished Aug 11 07:10:52 PM PDT 24
Peak memory 206564 kb
Host smart-a405e575-f139-4275-b34e-f96ccd396400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36240
52896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3624052896
Directory /workspace/11.usbdev_stall_trans/latest


Test location /workspace/coverage/default/11.usbdev_stream_len_max.1294938694
Short name T2405
Test name
Test status
Simulation time 1287202319 ps
CPU time 3.08 seconds
Started Aug 11 07:10:56 PM PDT 24
Finished Aug 11 07:10:59 PM PDT 24
Peak memory 207720 kb
Host smart-1c0aea7a-77d2-4b8f-b684-6f8788f09904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12949
38694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.1294938694
Directory /workspace/11.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/11.usbdev_streaming_out.3597403105
Short name T744
Test name
Test status
Simulation time 1995228976 ps
CPU time 20.12 seconds
Started Aug 11 07:10:54 PM PDT 24
Finished Aug 11 07:11:15 PM PDT 24
Peak memory 217392 kb
Host smart-a4663de2-f461-48d9-9ac6-bab2f81aa1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35974
03105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3597403105
Directory /workspace/11.usbdev_streaming_out/latest


Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.1949197128
Short name T3280
Test name
Test status
Simulation time 7060841850 ps
CPU time 46.66 seconds
Started Aug 11 07:10:42 PM PDT 24
Finished Aug 11 07:11:29 PM PDT 24
Peak memory 207780 kb
Host smart-f83ee131-0b14-4432-b650-221532784aea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949197128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.1949197128
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/11.usbdev_tx_rx_disruption.3359206829
Short name T2074
Test name
Test status
Simulation time 413885309 ps
CPU time 1.31 seconds
Started Aug 11 07:10:58 PM PDT 24
Finished Aug 11 07:10:59 PM PDT 24
Peak memory 207572 kb
Host smart-8ab73798-f996-4dec-95c6-4289243896b8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359206829 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.usbdev_tx_rx_disruption.3359206829
Directory /workspace/11.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/110.usbdev_endpoint_types.3084184378
Short name T471
Test name
Test status
Simulation time 281332633 ps
CPU time 1.13 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207444 kb
Host smart-7b5c8978-f57c-44cd-8e05-10323ed4fe19
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3084184378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.3084184378
Directory /workspace/110.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/110.usbdev_tx_rx_disruption.2430806213
Short name T3270
Test name
Test status
Simulation time 597353748 ps
CPU time 1.75 seconds
Started Aug 11 07:17:01 PM PDT 24
Finished Aug 11 07:17:03 PM PDT 24
Peak memory 207500 kb
Host smart-b8569c67-985c-411f-84d2-a21d2e44b65c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430806213 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.usbdev_tx_rx_disruption.2430806213
Directory /workspace/110.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/111.usbdev_tx_rx_disruption.3841951866
Short name T2909
Test name
Test status
Simulation time 683023379 ps
CPU time 1.81 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 206572 kb
Host smart-a77e26ae-c2d7-4831-b781-ab508bcadd32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841951866 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.usbdev_tx_rx_disruption.3841951866
Directory /workspace/111.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/112.usbdev_tx_rx_disruption.1042871040
Short name T2983
Test name
Test status
Simulation time 586854689 ps
CPU time 1.71 seconds
Started Aug 11 07:17:01 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 207572 kb
Host smart-85c81389-64c7-48c8-b4dc-bff6644300a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042871040 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.usbdev_tx_rx_disruption.1042871040
Directory /workspace/112.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/113.usbdev_endpoint_types.871256848
Short name T462
Test name
Test status
Simulation time 839693710 ps
CPU time 2.01 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 207508 kb
Host smart-80656f4c-fe78-41a0-b4c1-7e62e72edc46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=871256848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.871256848
Directory /workspace/113.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/114.usbdev_endpoint_types.3094970804
Short name T530
Test name
Test status
Simulation time 181355430 ps
CPU time 0.98 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207492 kb
Host smart-149d4045-c4a0-480e-9860-a1e9f50d22ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3094970804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.3094970804
Directory /workspace/114.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/114.usbdev_tx_rx_disruption.2390195738
Short name T1693
Test name
Test status
Simulation time 484899819 ps
CPU time 1.47 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207540 kb
Host smart-92b3b17a-e28d-4780-924a-8435bf710727
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390195738 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.usbdev_tx_rx_disruption.2390195738
Directory /workspace/114.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/115.usbdev_tx_rx_disruption.377874224
Short name T1424
Test name
Test status
Simulation time 416084225 ps
CPU time 1.33 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:01 PM PDT 24
Peak memory 207544 kb
Host smart-eea72aff-8351-4945-b68a-bc91a7ac19ee
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377874224 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 115.usbdev_tx_rx_disruption.377874224
Directory /workspace/115.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/116.usbdev_endpoint_types.79253417
Short name T495
Test name
Test status
Simulation time 290254007 ps
CPU time 1.23 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 207544 kb
Host smart-63114329-e376-4753-9bdb-107e9e4ae29d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=79253417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.79253417
Directory /workspace/116.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/116.usbdev_tx_rx_disruption.3092376491
Short name T1200
Test name
Test status
Simulation time 585799138 ps
CPU time 1.58 seconds
Started Aug 11 07:17:11 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 207600 kb
Host smart-5690aa07-0a86-4cda-b982-9e69af6b8fe8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092376491 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.usbdev_tx_rx_disruption.3092376491
Directory /workspace/116.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/117.usbdev_endpoint_types.36245905
Short name T496
Test name
Test status
Simulation time 250914139 ps
CPU time 1.05 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 207448 kb
Host smart-eff00e82-54c1-4cf8-9de2-630163c22bad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=36245905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.36245905
Directory /workspace/117.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/117.usbdev_tx_rx_disruption.3093530407
Short name T3064
Test name
Test status
Simulation time 501894372 ps
CPU time 1.52 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 207500 kb
Host smart-9a00353b-2c89-4c78-8232-dc1a9749d34e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093530407 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.usbdev_tx_rx_disruption.3093530407
Directory /workspace/117.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/118.usbdev_endpoint_types.3988173664
Short name T474
Test name
Test status
Simulation time 475643706 ps
CPU time 1.35 seconds
Started Aug 11 07:17:01 PM PDT 24
Finished Aug 11 07:17:03 PM PDT 24
Peak memory 207544 kb
Host smart-71f79e83-62db-4591-9dc8-1949e885b999
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3988173664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.3988173664
Directory /workspace/118.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/12.usbdev_alert_test.1771578064
Short name T1359
Test name
Test status
Simulation time 49179500 ps
CPU time 0.71 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207528 kb
Host smart-16ebb584-db21-465f-a5d5-e4f21b772639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1771578064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.1771578064
Directory /workspace/12.usbdev_alert_test/latest


Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.2689081935
Short name T3152
Test name
Test status
Simulation time 11807976256 ps
CPU time 14.58 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207876 kb
Host smart-b2b43ddd-eb1b-4ac9-a315-0ebf3de8c815
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689081935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.2689081935
Directory /workspace/12.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.643652187
Short name T1114
Test name
Test status
Simulation time 20113587747 ps
CPU time 24.73 seconds
Started Aug 11 07:10:55 PM PDT 24
Finished Aug 11 07:11:20 PM PDT 24
Peak memory 207752 kb
Host smart-39e78c44-99d0-4a32-a256-97ef74a84505
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=643652187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.643652187
Directory /workspace/12.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.3099633547
Short name T2865
Test name
Test status
Simulation time 29982568613 ps
CPU time 46.7 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:11:40 PM PDT 24
Peak memory 207840 kb
Host smart-0dd167ad-617a-4ecf-badf-2e9d29edbab9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099633547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.3099633547
Directory /workspace/12.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/12.usbdev_av_buffer.1815883125
Short name T912
Test name
Test status
Simulation time 181055270 ps
CPU time 0.94 seconds
Started Aug 11 07:10:54 PM PDT 24
Finished Aug 11 07:10:55 PM PDT 24
Peak memory 207508 kb
Host smart-988632cd-d3a0-481a-a7ca-9c9c11a65c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18158
83125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1815883125
Directory /workspace/12.usbdev_av_buffer/latest


Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3239659615
Short name T952
Test name
Test status
Simulation time 150714858 ps
CPU time 0.87 seconds
Started Aug 11 07:10:56 PM PDT 24
Finished Aug 11 07:10:57 PM PDT 24
Peak memory 207536 kb
Host smart-a64c2c9e-cd9e-44e0-949d-7ee96e389378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
59615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3239659615
Directory /workspace/12.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2803323722
Short name T3109
Test name
Test status
Simulation time 264825957 ps
CPU time 1.09 seconds
Started Aug 11 07:10:55 PM PDT 24
Finished Aug 11 07:10:56 PM PDT 24
Peak memory 207464 kb
Host smart-96ddfe97-6d3d-46cc-b296-a44e5be2c420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
23722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2803323722
Directory /workspace/12.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.4238308130
Short name T1625
Test name
Test status
Simulation time 596677292 ps
CPU time 1.68 seconds
Started Aug 11 07:10:56 PM PDT 24
Finished Aug 11 07:10:58 PM PDT 24
Peak memory 207568 kb
Host smart-ba4352ae-1505-41e7-9533-db29cb0efb40
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4238308130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.4238308130
Directory /workspace/12.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/12.usbdev_device_address.2776272479
Short name T187
Test name
Test status
Simulation time 41264182388 ps
CPU time 66.52 seconds
Started Aug 11 07:10:56 PM PDT 24
Finished Aug 11 07:12:02 PM PDT 24
Peak memory 207840 kb
Host smart-a82fdd8a-1031-4de1-850d-d1019f28f5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27762
72479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2776272479
Directory /workspace/12.usbdev_device_address/latest


Test location /workspace/coverage/default/12.usbdev_device_timeout.638168292
Short name T838
Test name
Test status
Simulation time 5680625355 ps
CPU time 49.91 seconds
Started Aug 11 07:10:55 PM PDT 24
Finished Aug 11 07:11:45 PM PDT 24
Peak memory 207860 kb
Host smart-936b5691-5a4b-4ad0-a077-85386729f977
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638168292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.638168292
Directory /workspace/12.usbdev_device_timeout/latest


Test location /workspace/coverage/default/12.usbdev_disable_endpoint.2039623158
Short name T3330
Test name
Test status
Simulation time 586954249 ps
CPU time 1.51 seconds
Started Aug 11 07:10:56 PM PDT 24
Finished Aug 11 07:10:58 PM PDT 24
Peak memory 207444 kb
Host smart-0f43f5f7-de45-42ce-8927-875d4e0abfe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20396
23158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2039623158
Directory /workspace/12.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/12.usbdev_disconnected.4264912156
Short name T3004
Test name
Test status
Simulation time 148123815 ps
CPU time 0.87 seconds
Started Aug 11 07:11:02 PM PDT 24
Finished Aug 11 07:11:03 PM PDT 24
Peak memory 207540 kb
Host smart-69975b18-febc-492d-92aa-27b6d92ea18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42649
12156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.4264912156
Directory /workspace/12.usbdev_disconnected/latest


Test location /workspace/coverage/default/12.usbdev_enable.2635562581
Short name T2033
Test name
Test status
Simulation time 113891502 ps
CPU time 0.78 seconds
Started Aug 11 07:10:54 PM PDT 24
Finished Aug 11 07:10:55 PM PDT 24
Peak memory 207496 kb
Host smart-bc011e58-a92d-4e22-beda-8dcae1398487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26355
62581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2635562581
Directory /workspace/12.usbdev_enable/latest


Test location /workspace/coverage/default/12.usbdev_endpoint_access.403677003
Short name T1369
Test name
Test status
Simulation time 766146571 ps
CPU time 2.18 seconds
Started Aug 11 07:10:55 PM PDT 24
Finished Aug 11 07:10:57 PM PDT 24
Peak memory 207772 kb
Host smart-3840caa7-7f25-4085-845a-0ff812b73252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40367
7003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.403677003
Directory /workspace/12.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/12.usbdev_endpoint_types.2446973489
Short name T453
Test name
Test status
Simulation time 605476947 ps
CPU time 1.73 seconds
Started Aug 11 07:10:52 PM PDT 24
Finished Aug 11 07:10:54 PM PDT 24
Peak memory 207536 kb
Host smart-494548ff-4c04-4251-9e7a-e7a253a787ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2446973489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.2446973489
Directory /workspace/12.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/12.usbdev_fifo_rst.3572026843
Short name T213
Test name
Test status
Simulation time 332380055 ps
CPU time 2.45 seconds
Started Aug 11 07:10:54 PM PDT 24
Finished Aug 11 07:10:56 PM PDT 24
Peak memory 207668 kb
Host smart-3223c3ad-e6b8-405f-9140-ee195a72a451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35720
26843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3572026843
Directory /workspace/12.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/12.usbdev_in_iso.2150017676
Short name T2264
Test name
Test status
Simulation time 165520487 ps
CPU time 0.91 seconds
Started Aug 11 07:10:56 PM PDT 24
Finished Aug 11 07:10:57 PM PDT 24
Peak memory 207576 kb
Host smart-f7099349-fa6b-4a56-8fba-14412ce3dfde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2150017676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2150017676
Directory /workspace/12.usbdev_in_iso/latest


Test location /workspace/coverage/default/12.usbdev_in_stall.2515430970
Short name T733
Test name
Test status
Simulation time 135429873 ps
CPU time 0.81 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:10:54 PM PDT 24
Peak memory 207528 kb
Host smart-34e02101-7524-4db0-899f-5b78ef3cb748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25154
30970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2515430970
Directory /workspace/12.usbdev_in_stall/latest


Test location /workspace/coverage/default/12.usbdev_in_trans.3953275571
Short name T2907
Test name
Test status
Simulation time 203572422 ps
CPU time 0.96 seconds
Started Aug 11 07:10:54 PM PDT 24
Finished Aug 11 07:10:55 PM PDT 24
Peak memory 207568 kb
Host smart-3f16ea8c-f176-4fd4-a44c-d7eff5d14270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39532
75571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3953275571
Directory /workspace/12.usbdev_in_trans/latest


Test location /workspace/coverage/default/12.usbdev_invalid_sync.1644406961
Short name T2871
Test name
Test status
Simulation time 5112148265 ps
CPU time 52.7 seconds
Started Aug 11 07:10:52 PM PDT 24
Finished Aug 11 07:11:45 PM PDT 24
Peak memory 217940 kb
Host smart-63f610bb-56e2-46be-8484-30e8a2e80007
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1644406961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1644406961
Directory /workspace/12.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/12.usbdev_iso_retraction.2917929789
Short name T2962
Test name
Test status
Simulation time 11749994173 ps
CPU time 138.69 seconds
Started Aug 11 07:10:55 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 207800 kb
Host smart-e7e83d16-0ff8-4f24-af18-73ced8863862
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2917929789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2917929789
Directory /workspace/12.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/12.usbdev_link_in_err.2092976689
Short name T2902
Test name
Test status
Simulation time 165193037 ps
CPU time 0.95 seconds
Started Aug 11 07:10:53 PM PDT 24
Finished Aug 11 07:10:54 PM PDT 24
Peak memory 207544 kb
Host smart-abe386c1-3803-4a5e-b5c8-242164260eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20929
76689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2092976689
Directory /workspace/12.usbdev_link_in_err/latest


Test location /workspace/coverage/default/12.usbdev_link_resume.435263085
Short name T1911
Test name
Test status
Simulation time 31420464404 ps
CPU time 51.45 seconds
Started Aug 11 07:10:55 PM PDT 24
Finished Aug 11 07:11:46 PM PDT 24
Peak memory 207800 kb
Host smart-fde59431-e365-4d50-a93f-e9da597d97e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43526
3085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.435263085
Directory /workspace/12.usbdev_link_resume/latest


Test location /workspace/coverage/default/12.usbdev_link_suspend.970100537
Short name T3459
Test name
Test status
Simulation time 10259132418 ps
CPU time 11.81 seconds
Started Aug 11 07:10:56 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207900 kb
Host smart-57efd95b-1a4a-4e8b-8a5b-5b1f8714ef71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97010
0537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.970100537
Directory /workspace/12.usbdev_link_suspend/latest


Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.4198166103
Short name T1546
Test name
Test status
Simulation time 2671876215 ps
CPU time 72.14 seconds
Started Aug 11 07:10:55 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 224256 kb
Host smart-5c39b27d-1d10-4a24-bf8b-6e1e3dbd47cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4198166103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.4198166103
Directory /workspace/12.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3560725439
Short name T3621
Test name
Test status
Simulation time 1888502539 ps
CPU time 14.21 seconds
Started Aug 11 07:10:59 PM PDT 24
Finished Aug 11 07:11:14 PM PDT 24
Peak memory 217624 kb
Host smart-ef0754eb-0fe2-4a7d-995e-8bc37dbfcc2a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3560725439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3560725439
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.464368672
Short name T3120
Test name
Test status
Simulation time 235715725 ps
CPU time 1.12 seconds
Started Aug 11 07:11:02 PM PDT 24
Finished Aug 11 07:11:03 PM PDT 24
Peak memory 207532 kb
Host smart-75005740-73be-4487-b46a-6f4c9c8e71f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=464368672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.464368672
Directory /workspace/12.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2059129536
Short name T1238
Test name
Test status
Simulation time 196082111 ps
CPU time 1.05 seconds
Started Aug 11 07:11:03 PM PDT 24
Finished Aug 11 07:11:04 PM PDT 24
Peak memory 207512 kb
Host smart-1f794798-38bd-4bdb-b8dd-aa745027b965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20591
29536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2059129536
Directory /workspace/12.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.1501871292
Short name T851
Test name
Test status
Simulation time 3084379738 ps
CPU time 32.31 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:40 PM PDT 24
Peak memory 217904 kb
Host smart-c44dff99-0a86-4c05-bbe8-bc6f1e83bc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15018
71292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.1501871292
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1179247007
Short name T1011
Test name
Test status
Simulation time 3343466507 ps
CPU time 97.92 seconds
Started Aug 11 07:11:02 PM PDT 24
Finished Aug 11 07:12:40 PM PDT 24
Peak memory 218288 kb
Host smart-a27560e4-c0b1-40ec-8a7d-9449c6b86c4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1179247007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1179247007
Directory /workspace/12.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1665325727
Short name T812
Test name
Test status
Simulation time 1993444118 ps
CPU time 19.07 seconds
Started Aug 11 07:11:01 PM PDT 24
Finished Aug 11 07:11:20 PM PDT 24
Peak memory 217364 kb
Host smart-341b74cf-24eb-457a-b779-3126bdf9be80
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1665325727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1665325727
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2775743112
Short name T1763
Test name
Test status
Simulation time 215222468 ps
CPU time 0.95 seconds
Started Aug 11 07:11:01 PM PDT 24
Finished Aug 11 07:11:02 PM PDT 24
Peak memory 207500 kb
Host smart-12b29e2f-dcfd-4d0c-9ea2-ce8541fea97c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2775743112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2775743112
Directory /workspace/12.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.167092571
Short name T2652
Test name
Test status
Simulation time 189442140 ps
CPU time 0.96 seconds
Started Aug 11 07:11:00 PM PDT 24
Finished Aug 11 07:11:01 PM PDT 24
Peak memory 207520 kb
Host smart-78d104da-970b-4087-912c-975f3612a7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16709
2571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.167092571
Directory /workspace/12.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_nak_trans.3415959142
Short name T2935
Test name
Test status
Simulation time 173696883 ps
CPU time 0.85 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207556 kb
Host smart-899abf72-5f01-4f90-ae39-f241ab9b22ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34159
59142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3415959142
Directory /workspace/12.usbdev_nak_trans/latest


Test location /workspace/coverage/default/12.usbdev_out_iso.3541687246
Short name T905
Test name
Test status
Simulation time 142252766 ps
CPU time 0.8 seconds
Started Aug 11 07:11:00 PM PDT 24
Finished Aug 11 07:11:01 PM PDT 24
Peak memory 207572 kb
Host smart-1b89d544-ea15-4291-9ae6-271ccc3049e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35416
87246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3541687246
Directory /workspace/12.usbdev_out_iso/latest


Test location /workspace/coverage/default/12.usbdev_out_stall.66025692
Short name T3241
Test name
Test status
Simulation time 163881154 ps
CPU time 0.82 seconds
Started Aug 11 07:10:59 PM PDT 24
Finished Aug 11 07:11:00 PM PDT 24
Peak memory 207568 kb
Host smart-ed5250b2-3786-4880-b730-8a23ea247ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66025
692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.66025692
Directory /workspace/12.usbdev_out_stall/latest


Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1502194315
Short name T1520
Test name
Test status
Simulation time 164193518 ps
CPU time 0.86 seconds
Started Aug 11 07:11:00 PM PDT 24
Finished Aug 11 07:11:01 PM PDT 24
Peak memory 207544 kb
Host smart-479cc559-ec7f-4c98-ba59-159de921dd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15021
94315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1502194315
Directory /workspace/12.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1226586758
Short name T2125
Test name
Test status
Simulation time 149182049 ps
CPU time 0.85 seconds
Started Aug 11 07:10:59 PM PDT 24
Finished Aug 11 07:11:00 PM PDT 24
Peak memory 207492 kb
Host smart-aad7631b-c8b3-4ef9-a320-44ff50f1da72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12265
86758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1226586758
Directory /workspace/12.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.733812079
Short name T3421
Test name
Test status
Simulation time 223227920 ps
CPU time 1.03 seconds
Started Aug 11 07:11:01 PM PDT 24
Finished Aug 11 07:11:02 PM PDT 24
Peak memory 207596 kb
Host smart-936fff82-6963-477a-b5f7-58d495ee095c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=733812079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.733812079
Directory /workspace/12.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.30950990
Short name T3504
Test name
Test status
Simulation time 178817405 ps
CPU time 0.91 seconds
Started Aug 11 07:11:06 PM PDT 24
Finished Aug 11 07:11:07 PM PDT 24
Peak memory 207448 kb
Host smart-20677130-79b0-461f-b1df-355ca1bd0921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30950
990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.30950990
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.382620277
Short name T1880
Test name
Test status
Simulation time 39244142 ps
CPU time 0.79 seconds
Started Aug 11 07:11:02 PM PDT 24
Finished Aug 11 07:11:03 PM PDT 24
Peak memory 207536 kb
Host smart-19e460ad-9205-4cf7-ae77-6f6b67933919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38262
0277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.382620277
Directory /workspace/12.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/12.usbdev_pkt_buffer.558853352
Short name T285
Test name
Test status
Simulation time 12452601382 ps
CPU time 30.98 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 215812 kb
Host smart-020d9060-5b15-453d-962a-53c9bb53e62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55885
3352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.558853352
Directory /workspace/12.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/12.usbdev_pkt_received.527830258
Short name T1879
Test name
Test status
Simulation time 187071744 ps
CPU time 0.95 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207232 kb
Host smart-6481f543-b6d8-40cc-9a27-1e364f5a5f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52783
0258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.527830258
Directory /workspace/12.usbdev_pkt_received/latest


Test location /workspace/coverage/default/12.usbdev_pkt_sent.2853264756
Short name T2246
Test name
Test status
Simulation time 159621945 ps
CPU time 0.91 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207460 kb
Host smart-cf33258f-7509-4932-b5e0-1cba50973c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28532
64756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2853264756
Directory /workspace/12.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.2908021135
Short name T3613
Test name
Test status
Simulation time 201408931 ps
CPU time 0.93 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:09 PM PDT 24
Peak memory 207556 kb
Host smart-54cee507-d3ee-44d9-82f2-5550feb46d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29080
21135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2908021135
Directory /workspace/12.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3089311790
Short name T3213
Test name
Test status
Simulation time 234757033 ps
CPU time 1.02 seconds
Started Aug 11 07:11:03 PM PDT 24
Finished Aug 11 07:11:04 PM PDT 24
Peak memory 207480 kb
Host smart-c6eaf8ae-6c9d-4ff7-9d8e-2b8eb7020161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30893
11790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3089311790
Directory /workspace/12.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_resume_link_active.1099046464
Short name T121
Test name
Test status
Simulation time 20149045391 ps
CPU time 25.14 seconds
Started Aug 11 07:11:01 PM PDT 24
Finished Aug 11 07:11:26 PM PDT 24
Peak memory 207832 kb
Host smart-f358db35-6d48-421f-a557-a8cf76f4430b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10990
46464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.1099046464
Directory /workspace/12.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2791293321
Short name T2710
Test name
Test status
Simulation time 158682827 ps
CPU time 0.81 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207516 kb
Host smart-76ab6b17-a074-4bcd-a91e-0ccb77f994dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27912
93321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2791293321
Directory /workspace/12.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/12.usbdev_rx_full.3255851921
Short name T1934
Test name
Test status
Simulation time 348932906 ps
CPU time 1.34 seconds
Started Aug 11 07:11:00 PM PDT 24
Finished Aug 11 07:11:01 PM PDT 24
Peak memory 207572 kb
Host smart-9aac4a39-c257-446f-b505-c88c2601dff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32558
51921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.3255851921
Directory /workspace/12.usbdev_rx_full/latest


Test location /workspace/coverage/default/12.usbdev_setup_stage.1743469754
Short name T2629
Test name
Test status
Simulation time 151556663 ps
CPU time 0.82 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:09 PM PDT 24
Peak memory 207540 kb
Host smart-7e26c109-7a5b-4ea9-84ad-c92d8a6856b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17434
69754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1743469754
Directory /workspace/12.usbdev_setup_stage/latest


Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1847791467
Short name T2843
Test name
Test status
Simulation time 146805450 ps
CPU time 0.88 seconds
Started Aug 11 07:11:00 PM PDT 24
Finished Aug 11 07:11:01 PM PDT 24
Peak memory 207548 kb
Host smart-dc221da7-6161-47f5-a65f-7c8719c56d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18477
91467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1847791467
Directory /workspace/12.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/12.usbdev_smoke.103474235
Short name T628
Test name
Test status
Simulation time 236241348 ps
CPU time 1.09 seconds
Started Aug 11 07:11:01 PM PDT 24
Finished Aug 11 07:11:03 PM PDT 24
Peak memory 207596 kb
Host smart-ab498520-8c0b-46de-8fc5-103a6d1f60f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10347
4235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.103474235
Directory /workspace/12.usbdev_smoke/latest


Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.798488548
Short name T3500
Test name
Test status
Simulation time 2529411076 ps
CPU time 72.78 seconds
Started Aug 11 07:10:59 PM PDT 24
Finished Aug 11 07:12:12 PM PDT 24
Peak memory 217952 kb
Host smart-2043ffc7-2a3b-483c-a0aa-81c35880f5bf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=798488548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.798488548
Directory /workspace/12.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.4172489557
Short name T547
Test name
Test status
Simulation time 214457666 ps
CPU time 1.01 seconds
Started Aug 11 07:11:02 PM PDT 24
Finished Aug 11 07:11:03 PM PDT 24
Peak memory 207572 kb
Host smart-b805ad56-ad9b-4615-9f52-24fb780d0ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41724
89557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.4172489557
Directory /workspace/12.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/12.usbdev_stall_trans.1146694068
Short name T1483
Test name
Test status
Simulation time 153124093 ps
CPU time 0.92 seconds
Started Aug 11 07:11:01 PM PDT 24
Finished Aug 11 07:11:02 PM PDT 24
Peak memory 207600 kb
Host smart-c7dafef4-63f7-4a34-bfde-2ea7effc4dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11466
94068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1146694068
Directory /workspace/12.usbdev_stall_trans/latest


Test location /workspace/coverage/default/12.usbdev_stream_len_max.2551143245
Short name T3583
Test name
Test status
Simulation time 1084828299 ps
CPU time 2.41 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:09 PM PDT 24
Peak memory 207700 kb
Host smart-7c419dad-a22c-4995-a589-0359fbf7cfe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25511
43245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.2551143245
Directory /workspace/12.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/12.usbdev_streaming_out.560444392
Short name T1074
Test name
Test status
Simulation time 2835624916 ps
CPU time 20.51 seconds
Started Aug 11 07:11:02 PM PDT 24
Finished Aug 11 07:11:23 PM PDT 24
Peak memory 217776 kb
Host smart-c2ab6350-ff95-44b6-bc21-5ae142fbf6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56044
4392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.560444392
Directory /workspace/12.usbdev_streaming_out/latest


Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.2889064345
Short name T2193
Test name
Test status
Simulation time 8448542782 ps
CPU time 57.56 seconds
Started Aug 11 07:10:59 PM PDT 24
Finished Aug 11 07:11:57 PM PDT 24
Peak memory 207760 kb
Host smart-cd4af211-1b28-4b7c-a820-eff603e21e84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889064345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.2889064345
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/12.usbdev_tx_rx_disruption.4264633762
Short name T229
Test name
Test status
Simulation time 515938433 ps
CPU time 1.54 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:10 PM PDT 24
Peak memory 207572 kb
Host smart-3ec6065a-0317-4cf4-8b22-2622e1221aaa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264633762 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.usbdev_tx_rx_disruption.4264633762
Directory /workspace/12.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/120.usbdev_endpoint_types.4035337661
Short name T2584
Test name
Test status
Simulation time 281825662 ps
CPU time 1.08 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207468 kb
Host smart-0c25040d-a6b8-424a-ab1f-1332c0c00d58
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4035337661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.4035337661
Directory /workspace/120.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/120.usbdev_tx_rx_disruption.2451064172
Short name T3055
Test name
Test status
Simulation time 613750442 ps
CPU time 1.79 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207552 kb
Host smart-f505ed48-78fc-4aeb-b9fc-18a711cd202f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451064172 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.usbdev_tx_rx_disruption.2451064172
Directory /workspace/120.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/121.usbdev_endpoint_types.1110560045
Short name T503
Test name
Test status
Simulation time 340079217 ps
CPU time 1.17 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207496 kb
Host smart-6a4b2608-42c8-49e6-8d01-1f2c297f94a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1110560045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.1110560045
Directory /workspace/121.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/121.usbdev_tx_rx_disruption.3179612799
Short name T3591
Test name
Test status
Simulation time 547112011 ps
CPU time 1.69 seconds
Started Aug 11 07:17:04 PM PDT 24
Finished Aug 11 07:17:06 PM PDT 24
Peak memory 207572 kb
Host smart-79162be1-9ada-4f28-be60-dc339a6e6f9d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179612799 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.usbdev_tx_rx_disruption.3179612799
Directory /workspace/121.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/122.usbdev_endpoint_types.754219205
Short name T1927
Test name
Test status
Simulation time 150518823 ps
CPU time 0.88 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:01 PM PDT 24
Peak memory 207516 kb
Host smart-9bd7054b-1cc9-4970-81b3-962063756b94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=754219205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.754219205
Directory /workspace/122.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/122.usbdev_tx_rx_disruption.1929431308
Short name T2991
Test name
Test status
Simulation time 569327334 ps
CPU time 1.91 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207488 kb
Host smart-f3995802-03b4-41da-baf4-f2ac62a5586e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929431308 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.usbdev_tx_rx_disruption.1929431308
Directory /workspace/122.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/123.usbdev_endpoint_types.2229700745
Short name T3390
Test name
Test status
Simulation time 256938654 ps
CPU time 1.03 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207568 kb
Host smart-a14b34df-ecdd-48f5-8b25-0431a5202a09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2229700745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.2229700745
Directory /workspace/123.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/123.usbdev_tx_rx_disruption.75190578
Short name T3206
Test name
Test status
Simulation time 512316576 ps
CPU time 1.71 seconds
Started Aug 11 07:17:20 PM PDT 24
Finished Aug 11 07:17:22 PM PDT 24
Peak memory 207564 kb
Host smart-d9eaf5ca-ff67-425a-b090-33e7bd14f5f0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75190578 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 123.usbdev_tx_rx_disruption.75190578
Directory /workspace/123.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/124.usbdev_tx_rx_disruption.2566951076
Short name T895
Test name
Test status
Simulation time 528521154 ps
CPU time 1.62 seconds
Started Aug 11 07:17:11 PM PDT 24
Finished Aug 11 07:17:13 PM PDT 24
Peak memory 207452 kb
Host smart-aa7ed049-607b-4ddf-841f-1d219b331ebf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566951076 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.usbdev_tx_rx_disruption.2566951076
Directory /workspace/124.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/125.usbdev_endpoint_types.2640499528
Short name T3405
Test name
Test status
Simulation time 636210154 ps
CPU time 1.57 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 206528 kb
Host smart-42fb86dd-ea8d-4220-bf7a-284a4360c17f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2640499528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.2640499528
Directory /workspace/125.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/125.usbdev_tx_rx_disruption.3550927244
Short name T258
Test name
Test status
Simulation time 474277489 ps
CPU time 1.54 seconds
Started Aug 11 07:16:58 PM PDT 24
Finished Aug 11 07:17:00 PM PDT 24
Peak memory 207552 kb
Host smart-d177bb37-b7d8-4cfc-9d97-df06efbb4110
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550927244 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.usbdev_tx_rx_disruption.3550927244
Directory /workspace/125.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/126.usbdev_endpoint_types.1422956405
Short name T412
Test name
Test status
Simulation time 453959163 ps
CPU time 1.46 seconds
Started Aug 11 07:16:57 PM PDT 24
Finished Aug 11 07:16:58 PM PDT 24
Peak memory 207540 kb
Host smart-7b3c20a7-7917-4c82-8186-0b375a8a40b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1422956405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.1422956405
Directory /workspace/126.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/126.usbdev_tx_rx_disruption.3519768799
Short name T2550
Test name
Test status
Simulation time 577050381 ps
CPU time 1.57 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207508 kb
Host smart-7df26526-3b4a-43c0-aeef-fd7cfa25704b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519768799 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.usbdev_tx_rx_disruption.3519768799
Directory /workspace/126.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/127.usbdev_endpoint_types.47362573
Short name T1277
Test name
Test status
Simulation time 145117722 ps
CPU time 0.88 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207520 kb
Host smart-d8297439-b746-4c72-b892-a4b6d0361b25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=47362573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.47362573
Directory /workspace/127.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/127.usbdev_tx_rx_disruption.1807611681
Short name T655
Test name
Test status
Simulation time 468713235 ps
CPU time 1.49 seconds
Started Aug 11 07:16:56 PM PDT 24
Finished Aug 11 07:16:58 PM PDT 24
Peak memory 207480 kb
Host smart-2479ef4a-654e-4dcd-9986-db716bd620a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807611681 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.usbdev_tx_rx_disruption.1807611681
Directory /workspace/127.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/128.usbdev_endpoint_types.2379511617
Short name T504
Test name
Test status
Simulation time 369493348 ps
CPU time 1.29 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:06 PM PDT 24
Peak memory 207536 kb
Host smart-66fc39fc-1055-47df-84a2-981b87a6075d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2379511617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.2379511617
Directory /workspace/128.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/128.usbdev_tx_rx_disruption.414534966
Short name T1278
Test name
Test status
Simulation time 599134425 ps
CPU time 1.68 seconds
Started Aug 11 07:16:56 PM PDT 24
Finished Aug 11 07:16:58 PM PDT 24
Peak memory 207500 kb
Host smart-7e50413b-c4ef-4aaa-b8ad-25f89737db5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414534966 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 128.usbdev_tx_rx_disruption.414534966
Directory /workspace/128.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/13.usbdev_alert_test.4280309428
Short name T1580
Test name
Test status
Simulation time 74301251 ps
CPU time 0.68 seconds
Started Aug 11 07:11:15 PM PDT 24
Finished Aug 11 07:11:15 PM PDT 24
Peak memory 207576 kb
Host smart-7b46066b-5ace-4e41-b614-146c927acf7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4280309428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.4280309428
Directory /workspace/13.usbdev_alert_test/latest


Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3789466468
Short name T3220
Test name
Test status
Simulation time 11141649053 ps
CPU time 14.88 seconds
Started Aug 11 07:11:03 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207744 kb
Host smart-6394f75a-5cf2-4baf-af01-0f86852711b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789466468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.3789466468
Directory /workspace/13.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3805413585
Short name T2457
Test name
Test status
Simulation time 14387202251 ps
CPU time 18.77 seconds
Started Aug 11 07:11:06 PM PDT 24
Finished Aug 11 07:11:25 PM PDT 24
Peak memory 216012 kb
Host smart-690f1390-4214-4614-9884-c59f502e3e06
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805413585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3805413585
Directory /workspace/13.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.916337688
Short name T2939
Test name
Test status
Simulation time 31091136098 ps
CPU time 48.31 seconds
Started Aug 11 07:11:04 PM PDT 24
Finished Aug 11 07:11:53 PM PDT 24
Peak memory 207744 kb
Host smart-5f9f6c4a-22b9-47d8-9f88-1b490d6820f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916337688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ao
n_wake_resume.916337688
Directory /workspace/13.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/13.usbdev_av_buffer.602306962
Short name T3210
Test name
Test status
Simulation time 147747535 ps
CPU time 0.83 seconds
Started Aug 11 07:11:06 PM PDT 24
Finished Aug 11 07:11:07 PM PDT 24
Peak memory 207476 kb
Host smart-a968fee5-39d7-4b8d-9699-e93fb0c04a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60230
6962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.602306962
Directory /workspace/13.usbdev_av_buffer/latest


Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3899358100
Short name T2050
Test name
Test status
Simulation time 153387648 ps
CPU time 0.85 seconds
Started Aug 11 07:11:00 PM PDT 24
Finished Aug 11 07:11:01 PM PDT 24
Peak memory 207548 kb
Host smart-288b31ce-3ff2-4009-adb4-a9c97157f06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38993
58100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3899358100
Directory /workspace/13.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.991460785
Short name T2524
Test name
Test status
Simulation time 337832709 ps
CPU time 1.33 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:09 PM PDT 24
Peak memory 207500 kb
Host smart-c1c8a1a9-7e85-43de-a6ca-fc80ec97695c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99146
0785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.991460785
Directory /workspace/13.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2332717032
Short name T62
Test name
Test status
Simulation time 941194126 ps
CPU time 2.43 seconds
Started Aug 11 07:11:06 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207656 kb
Host smart-5225a5f5-d295-4d3e-97a4-f4e7492f5d54
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2332717032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2332717032
Directory /workspace/13.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/13.usbdev_device_address.833767031
Short name T2385
Test name
Test status
Simulation time 22160441292 ps
CPU time 38.86 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:46 PM PDT 24
Peak memory 207804 kb
Host smart-ca575963-ba45-4843-a320-53156bf7ad72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83376
7031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.833767031
Directory /workspace/13.usbdev_device_address/latest


Test location /workspace/coverage/default/13.usbdev_device_timeout.4067337741
Short name T2474
Test name
Test status
Simulation time 270173335 ps
CPU time 4.49 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:13 PM PDT 24
Peak memory 207744 kb
Host smart-3e1c3fa1-c9f4-4eed-a3c2-c94a038eecf6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067337741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.4067337741
Directory /workspace/13.usbdev_device_timeout/latest


Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2046351244
Short name T1256
Test name
Test status
Simulation time 704555110 ps
CPU time 2.08 seconds
Started Aug 11 07:11:06 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207520 kb
Host smart-1a4fe3a3-3c35-46d8-a724-8f2fa4455150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20463
51244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2046351244
Directory /workspace/13.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/13.usbdev_disconnected.2933761696
Short name T2342
Test name
Test status
Simulation time 164762178 ps
CPU time 0.84 seconds
Started Aug 11 07:11:12 PM PDT 24
Finished Aug 11 07:11:13 PM PDT 24
Peak memory 207480 kb
Host smart-11a8aab6-d3f3-4c67-af2f-3687911e43cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29337
61696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2933761696
Directory /workspace/13.usbdev_disconnected/latest


Test location /workspace/coverage/default/13.usbdev_enable.3821866477
Short name T3442
Test name
Test status
Simulation time 65370676 ps
CPU time 0.74 seconds
Started Aug 11 07:11:09 PM PDT 24
Finished Aug 11 07:11:10 PM PDT 24
Peak memory 207532 kb
Host smart-a7ff1eba-5bce-4f0c-8417-bd46ffbd4735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38218
66477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3821866477
Directory /workspace/13.usbdev_enable/latest


Test location /workspace/coverage/default/13.usbdev_endpoint_access.197305830
Short name T2975
Test name
Test status
Simulation time 923134340 ps
CPU time 2.41 seconds
Started Aug 11 07:11:09 PM PDT 24
Finished Aug 11 07:11:12 PM PDT 24
Peak memory 207676 kb
Host smart-f1cc60e6-ef8a-4211-945a-2fb13a5209ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19730
5830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.197305830
Directory /workspace/13.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/13.usbdev_endpoint_types.3663901689
Short name T475
Test name
Test status
Simulation time 258493948 ps
CPU time 1 seconds
Started Aug 11 07:11:09 PM PDT 24
Finished Aug 11 07:11:10 PM PDT 24
Peak memory 207532 kb
Host smart-b9851beb-fd47-4e61-be17-79fbd6adaf93
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3663901689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.3663901689
Directory /workspace/13.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/13.usbdev_fifo_rst.3576063083
Short name T1503
Test name
Test status
Simulation time 352858945 ps
CPU time 2.76 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:10 PM PDT 24
Peak memory 207608 kb
Host smart-05c1abaa-a339-45e8-9279-350cfdec2e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35760
63083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3576063083
Directory /workspace/13.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/13.usbdev_in_iso.798719934
Short name T805
Test name
Test status
Simulation time 163441126 ps
CPU time 0.93 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:09 PM PDT 24
Peak memory 207488 kb
Host smart-97edaccc-468f-478f-a3ac-ce486cb454e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=798719934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.798719934
Directory /workspace/13.usbdev_in_iso/latest


Test location /workspace/coverage/default/13.usbdev_in_stall.3743031782
Short name T1235
Test name
Test status
Simulation time 159022353 ps
CPU time 0.94 seconds
Started Aug 11 07:11:12 PM PDT 24
Finished Aug 11 07:11:13 PM PDT 24
Peak memory 207452 kb
Host smart-9fabc01d-a775-4e5e-9c76-2031004fe798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37430
31782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3743031782
Directory /workspace/13.usbdev_in_stall/latest


Test location /workspace/coverage/default/13.usbdev_in_trans.827302536
Short name T2904
Test name
Test status
Simulation time 282625496 ps
CPU time 1.02 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207576 kb
Host smart-bf431487-6f64-4a2f-9727-a58ebcf0e7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82730
2536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.827302536
Directory /workspace/13.usbdev_in_trans/latest


Test location /workspace/coverage/default/13.usbdev_invalid_sync.2668204102
Short name T2052
Test name
Test status
Simulation time 2685847808 ps
CPU time 19.68 seconds
Started Aug 11 07:11:09 PM PDT 24
Finished Aug 11 07:11:28 PM PDT 24
Peak memory 216156 kb
Host smart-e60c2f9e-2377-4b59-826b-a7f946ee0edf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2668204102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.2668204102
Directory /workspace/13.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/13.usbdev_iso_retraction.3132752103
Short name T2922
Test name
Test status
Simulation time 4269389872 ps
CPU time 29.95 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:39 PM PDT 24
Peak memory 207812 kb
Host smart-5c546ba4-48f2-4f05-8c1e-1af006320bd1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3132752103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.3132752103
Directory /workspace/13.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/13.usbdev_link_in_err.3806927433
Short name T920
Test name
Test status
Simulation time 199135039 ps
CPU time 0.93 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 207544 kb
Host smart-9526dd07-fc38-486f-be84-3882300b6a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38069
27433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3806927433
Directory /workspace/13.usbdev_link_in_err/latest


Test location /workspace/coverage/default/13.usbdev_link_suspend.2598897986
Short name T111
Test name
Test status
Simulation time 6213019137 ps
CPU time 8.77 seconds
Started Aug 11 07:11:10 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 216092 kb
Host smart-b73ba80e-cf4a-452d-af93-06555b25b2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25988
97986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2598897986
Directory /workspace/13.usbdev_link_suspend/latest


Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2710954985
Short name T1642
Test name
Test status
Simulation time 5618934474 ps
CPU time 48.76 seconds
Started Aug 11 07:11:09 PM PDT 24
Finished Aug 11 07:11:58 PM PDT 24
Peak memory 224252 kb
Host smart-47cefd45-00bf-4d6e-b597-e12166dfe62c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2710954985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2710954985
Directory /workspace/13.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.615513764
Short name T1649
Test name
Test status
Simulation time 2245285357 ps
CPU time 16.28 seconds
Started Aug 11 07:11:09 PM PDT 24
Finished Aug 11 07:11:25 PM PDT 24
Peak memory 216088 kb
Host smart-9476024a-9c55-4829-8263-e4c354e3081e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=615513764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.615513764
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2668245688
Short name T3285
Test name
Test status
Simulation time 265844806 ps
CPU time 1.12 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:09 PM PDT 24
Peak memory 207568 kb
Host smart-9ab8739a-797b-4404-b221-511a42e56fab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2668245688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2668245688
Directory /workspace/13.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1539333962
Short name T2416
Test name
Test status
Simulation time 196189509 ps
CPU time 0.93 seconds
Started Aug 11 07:11:09 PM PDT 24
Finished Aug 11 07:11:10 PM PDT 24
Peak memory 207540 kb
Host smart-2a88123e-f4a9-41bd-93fb-ccd511e266d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15393
33962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1539333962
Directory /workspace/13.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.351537908
Short name T1310
Test name
Test status
Simulation time 2882703193 ps
CPU time 23.64 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:32 PM PDT 24
Peak memory 224248 kb
Host smart-3549bb2e-59a5-4f35-85e2-1b91333a5e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35153
7908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.351537908
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1534751553
Short name T1429
Test name
Test status
Simulation time 1763112442 ps
CPU time 14.47 seconds
Started Aug 11 07:11:10 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 215992 kb
Host smart-b9027e41-3920-4621-a396-953b42b8a1b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1534751553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1534751553
Directory /workspace/13.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.2162800637
Short name T1696
Test name
Test status
Simulation time 3612546014 ps
CPU time 27.11 seconds
Started Aug 11 07:11:07 PM PDT 24
Finished Aug 11 07:11:34 PM PDT 24
Peak memory 217756 kb
Host smart-4b5a5d60-698d-472e-ae0d-d77632013bdb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2162800637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2162800637
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3696219995
Short name T3060
Test name
Test status
Simulation time 158472822 ps
CPU time 0.84 seconds
Started Aug 11 07:11:08 PM PDT 24
Finished Aug 11 07:11:09 PM PDT 24
Peak memory 207596 kb
Host smart-dc43d64f-fb3d-4f0a-9da6-83d349065dcd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3696219995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3696219995
Directory /workspace/13.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1580620041
Short name T2616
Test name
Test status
Simulation time 141598939 ps
CPU time 0.85 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207544 kb
Host smart-b6a9323d-58e9-4b70-8b43-2a27f828dd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
20041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1580620041
Directory /workspace/13.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_out_iso.2807054084
Short name T1936
Test name
Test status
Simulation time 195951563 ps
CPU time 0.91 seconds
Started Aug 11 07:11:18 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207572 kb
Host smart-40c9ed26-e0e5-4429-b9dd-d5f449257171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28070
54084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.2807054084
Directory /workspace/13.usbdev_out_iso/latest


Test location /workspace/coverage/default/13.usbdev_out_stall.4128135648
Short name T3082
Test name
Test status
Simulation time 154357948 ps
CPU time 0.89 seconds
Started Aug 11 07:11:18 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207572 kb
Host smart-5cf8c805-0223-43d3-b85c-4df112ace19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
35648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.4128135648
Directory /workspace/13.usbdev_out_stall/latest


Test location /workspace/coverage/default/13.usbdev_out_trans_nak.305251014
Short name T960
Test name
Test status
Simulation time 200379880 ps
CPU time 0.96 seconds
Started Aug 11 07:11:14 PM PDT 24
Finished Aug 11 07:11:15 PM PDT 24
Peak memory 207568 kb
Host smart-d761981d-64b9-4f05-bf2e-0d3872be47ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30525
1014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.305251014
Directory /workspace/13.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2223890845
Short name T3251
Test name
Test status
Simulation time 155064099 ps
CPU time 0.89 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:17 PM PDT 24
Peak memory 207508 kb
Host smart-c9364e76-49ea-47cd-8c2e-7e8454fea17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22238
90845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2223890845
Directory /workspace/13.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2538568321
Short name T584
Test name
Test status
Simulation time 231124380 ps
CPU time 1.04 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207596 kb
Host smart-2177e223-b572-4821-aa6b-2657f7666ac1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2538568321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2538568321
Directory /workspace/13.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.4203354644
Short name T3303
Test name
Test status
Simulation time 139840095 ps
CPU time 0.92 seconds
Started Aug 11 07:11:15 PM PDT 24
Finished Aug 11 07:11:16 PM PDT 24
Peak memory 207452 kb
Host smart-dd58e960-6c71-4f5b-8176-1ff19f581882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42033
54644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.4203354644
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.409403701
Short name T2714
Test name
Test status
Simulation time 42678441 ps
CPU time 0.69 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:17 PM PDT 24
Peak memory 207404 kb
Host smart-42e42d19-52ac-4848-b765-a0a079e1c567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40940
3701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.409403701
Directory /workspace/13.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1364031349
Short name T295
Test name
Test status
Simulation time 9890765527 ps
CPU time 25.98 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:42 PM PDT 24
Peak memory 215984 kb
Host smart-4bc67855-5c2b-40e3-a4a4-1dbfedcbd768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13640
31349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1364031349
Directory /workspace/13.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/13.usbdev_pkt_received.450841963
Short name T1315
Test name
Test status
Simulation time 196576780 ps
CPU time 0.92 seconds
Started Aug 11 07:11:20 PM PDT 24
Finished Aug 11 07:11:21 PM PDT 24
Peak memory 207476 kb
Host smart-22492069-98ea-4e02-9080-17c1892ea488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45084
1963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.450841963
Directory /workspace/13.usbdev_pkt_received/latest


Test location /workspace/coverage/default/13.usbdev_pkt_sent.1079141189
Short name T3362
Test name
Test status
Simulation time 232236319 ps
CPU time 0.98 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207520 kb
Host smart-3980f9b9-a732-4b92-9190-605a373c4395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10791
41189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1079141189
Directory /workspace/13.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2089901678
Short name T2
Test name
Test status
Simulation time 281805620 ps
CPU time 1.08 seconds
Started Aug 11 07:11:15 PM PDT 24
Finished Aug 11 07:11:16 PM PDT 24
Peak memory 207544 kb
Host smart-83891d77-87b5-452b-a9aa-11a973a5fce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20899
01678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2089901678
Directory /workspace/13.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1182118143
Short name T275
Test name
Test status
Simulation time 204227210 ps
CPU time 0.94 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207572 kb
Host smart-8a83a6b4-9c98-4ac8-8bde-0a16a63a7335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11821
18143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1182118143
Directory /workspace/13.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_resume_link_active.3489488815
Short name T2905
Test name
Test status
Simulation time 20162491812 ps
CPU time 25.62 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:43 PM PDT 24
Peak memory 207656 kb
Host smart-46526b52-e2a7-4c42-abe4-beb6c99ea511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34894
88815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.3489488815
Directory /workspace/13.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/13.usbdev_rx_full.12474808
Short name T3181
Test name
Test status
Simulation time 362374077 ps
CPU time 1.28 seconds
Started Aug 11 07:11:14 PM PDT 24
Finished Aug 11 07:11:15 PM PDT 24
Peak memory 207520 kb
Host smart-e5eb05c0-8171-47ad-a559-25a9b342ef20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12474
808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.12474808
Directory /workspace/13.usbdev_rx_full/latest


Test location /workspace/coverage/default/13.usbdev_setup_stage.131136877
Short name T1445
Test name
Test status
Simulation time 148537270 ps
CPU time 0.85 seconds
Started Aug 11 07:11:18 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207500 kb
Host smart-37bb9ca1-c590-4687-b263-36968c513492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13113
6877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.131136877
Directory /workspace/13.usbdev_setup_stage/latest


Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3185201575
Short name T1319
Test name
Test status
Simulation time 157168981 ps
CPU time 0.85 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207568 kb
Host smart-f6801991-81d3-454e-84a0-7cb28cd28703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31852
01575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3185201575
Directory /workspace/13.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/13.usbdev_smoke.1777109334
Short name T2807
Test name
Test status
Simulation time 245441099 ps
CPU time 1.09 seconds
Started Aug 11 07:11:18 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207512 kb
Host smart-f1bf989b-7e68-48bf-ad0a-cd5064e8989f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17771
09334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1777109334
Directory /workspace/13.usbdev_smoke/latest


Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2164859804
Short name T1059
Test name
Test status
Simulation time 3548872030 ps
CPU time 101.93 seconds
Started Aug 11 07:11:14 PM PDT 24
Finished Aug 11 07:12:56 PM PDT 24
Peak memory 224204 kb
Host smart-0644827a-b02f-4573-9f05-6907761ff176
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2164859804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2164859804
Directory /workspace/13.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2687191082
Short name T2636
Test name
Test status
Simulation time 203243194 ps
CPU time 0.97 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207548 kb
Host smart-408f1265-8afe-4db0-8e39-d384c63c8dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871
91082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2687191082
Directory /workspace/13.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/13.usbdev_stall_trans.4087446939
Short name T3022
Test name
Test status
Simulation time 191255680 ps
CPU time 0.9 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:17 PM PDT 24
Peak memory 207540 kb
Host smart-ce71c18f-252b-491f-b0e8-aa948feec626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40874
46939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.4087446939
Directory /workspace/13.usbdev_stall_trans/latest


Test location /workspace/coverage/default/13.usbdev_stream_len_max.2743234324
Short name T563
Test name
Test status
Simulation time 504511863 ps
CPU time 1.51 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207544 kb
Host smart-993ab8da-9391-45ec-8374-7a1c5e36bf40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27432
34324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2743234324
Directory /workspace/13.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/13.usbdev_streaming_out.1591470124
Short name T3243
Test name
Test status
Simulation time 3082431495 ps
CPU time 92.29 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:12:49 PM PDT 24
Peak memory 217616 kb
Host smart-b773ab03-d99a-4f2b-a3a6-65b1d6aa1f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15914
70124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1591470124
Directory /workspace/13.usbdev_streaming_out/latest


Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.3171585117
Short name T1674
Test name
Test status
Simulation time 1262234678 ps
CPU time 30.55 seconds
Started Aug 11 07:11:11 PM PDT 24
Finished Aug 11 07:11:42 PM PDT 24
Peak memory 207664 kb
Host smart-a75d92dd-133a-4847-a075-f77fbe940ec5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171585117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.3171585117
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/13.usbdev_tx_rx_disruption.13279740
Short name T647
Test name
Test status
Simulation time 436539871 ps
CPU time 1.37 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:17 PM PDT 24
Peak memory 207488 kb
Host smart-9df6b7f5-cfa6-41c6-a342-aee6e96a5b81
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13279740 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 13.usbdev_tx_rx_disruption.13279740
Directory /workspace/13.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/130.usbdev_endpoint_types.1435303765
Short name T420
Test name
Test status
Simulation time 351054651 ps
CPU time 1.25 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:03 PM PDT 24
Peak memory 207520 kb
Host smart-24e21579-db35-4228-a585-9b4e402d13af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1435303765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.1435303765
Directory /workspace/130.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/130.usbdev_tx_rx_disruption.3503865643
Short name T1121
Test name
Test status
Simulation time 504855674 ps
CPU time 1.52 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207532 kb
Host smart-bae59e94-ac23-4447-8175-3b736aa6757a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503865643 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.usbdev_tx_rx_disruption.3503865643
Directory /workspace/130.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/131.usbdev_endpoint_types.1056153638
Short name T519
Test name
Test status
Simulation time 422064481 ps
CPU time 1.44 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207536 kb
Host smart-16b73db0-d836-4919-bea1-ea329d117135
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1056153638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.1056153638
Directory /workspace/131.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/131.usbdev_tx_rx_disruption.2568191840
Short name T583
Test name
Test status
Simulation time 498808752 ps
CPU time 1.57 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:06 PM PDT 24
Peak memory 207548 kb
Host smart-68eb6156-02e5-47c4-b147-5f8c7e33e813
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568191840 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.usbdev_tx_rx_disruption.2568191840
Directory /workspace/131.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/132.usbdev_endpoint_types.1183115538
Short name T450
Test name
Test status
Simulation time 257648229 ps
CPU time 1.01 seconds
Started Aug 11 07:17:04 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 206528 kb
Host smart-05c27748-6772-4b60-9bef-f1b564309e9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1183115538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.1183115538
Directory /workspace/132.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/132.usbdev_tx_rx_disruption.359431613
Short name T3155
Test name
Test status
Simulation time 442731758 ps
CPU time 1.47 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207552 kb
Host smart-0acda20f-8ec9-4c98-8f8a-38364666e944
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359431613 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 132.usbdev_tx_rx_disruption.359431613
Directory /workspace/132.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/133.usbdev_endpoint_types.2897353043
Short name T472
Test name
Test status
Simulation time 312463418 ps
CPU time 1.04 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:01 PM PDT 24
Peak memory 207520 kb
Host smart-9123495d-8b65-49e0-af9d-5a261f8c2cbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2897353043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.2897353043
Directory /workspace/133.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/133.usbdev_tx_rx_disruption.2987725443
Short name T759
Test name
Test status
Simulation time 621256384 ps
CPU time 1.5 seconds
Started Aug 11 07:16:56 PM PDT 24
Finished Aug 11 07:16:57 PM PDT 24
Peak memory 206568 kb
Host smart-49183c40-12f7-4bdd-972d-02d2440202fd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987725443 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.usbdev_tx_rx_disruption.2987725443
Directory /workspace/133.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/134.usbdev_endpoint_types.526197574
Short name T550
Test name
Test status
Simulation time 480957029 ps
CPU time 1.4 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207532 kb
Host smart-c4850542-1067-4e9e-8557-8d1ba7ca418e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=526197574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.526197574
Directory /workspace/134.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/134.usbdev_tx_rx_disruption.3654014771
Short name T1821
Test name
Test status
Simulation time 429193597 ps
CPU time 1.35 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207572 kb
Host smart-927d8233-fc44-40d6-84d6-94fcdf5ca8bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654014771 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.usbdev_tx_rx_disruption.3654014771
Directory /workspace/134.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/135.usbdev_endpoint_types.3240352715
Short name T413
Test name
Test status
Simulation time 237937569 ps
CPU time 1.08 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:06 PM PDT 24
Peak memory 207472 kb
Host smart-e8ed0215-a61b-4e47-b75a-97d48c5e4277
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3240352715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.3240352715
Directory /workspace/135.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/135.usbdev_tx_rx_disruption.2673929087
Short name T250
Test name
Test status
Simulation time 517038920 ps
CPU time 1.56 seconds
Started Aug 11 07:17:11 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 207516 kb
Host smart-cc1d8e66-a1b1-4fe8-9b45-f6021f073729
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673929087 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.usbdev_tx_rx_disruption.2673929087
Directory /workspace/135.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/136.usbdev_tx_rx_disruption.3908654157
Short name T2055
Test name
Test status
Simulation time 612443461 ps
CPU time 1.66 seconds
Started Aug 11 07:17:04 PM PDT 24
Finished Aug 11 07:17:06 PM PDT 24
Peak memory 207572 kb
Host smart-9c109f63-2628-418f-b84c-bf2bdf2f920f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908654157 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.usbdev_tx_rx_disruption.3908654157
Directory /workspace/136.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/137.usbdev_endpoint_types.1287332023
Short name T520
Test name
Test status
Simulation time 404439256 ps
CPU time 1.22 seconds
Started Aug 11 07:16:57 PM PDT 24
Finished Aug 11 07:16:58 PM PDT 24
Peak memory 207536 kb
Host smart-9459f812-00c2-448c-ba0e-0857f5fabaf2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1287332023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.1287332023
Directory /workspace/137.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/137.usbdev_tx_rx_disruption.3991418721
Short name T2130
Test name
Test status
Simulation time 608855083 ps
CPU time 1.67 seconds
Started Aug 11 07:17:04 PM PDT 24
Finished Aug 11 07:17:06 PM PDT 24
Peak memory 207552 kb
Host smart-c1b7e31d-0deb-468d-beb3-594916244a5b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991418721 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.usbdev_tx_rx_disruption.3991418721
Directory /workspace/137.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/138.usbdev_endpoint_types.2904984655
Short name T486
Test name
Test status
Simulation time 444385175 ps
CPU time 1.3 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:03 PM PDT 24
Peak memory 207440 kb
Host smart-13b4c36e-ef16-4f9b-8fbc-2e45185e8f4f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2904984655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.2904984655
Directory /workspace/138.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/139.usbdev_endpoint_types.3875486982
Short name T2317
Test name
Test status
Simulation time 240694405 ps
CPU time 0.94 seconds
Started Aug 11 07:17:09 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207540 kb
Host smart-e2440e39-283f-4be1-977c-b40c0c54e230
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3875486982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.3875486982
Directory /workspace/139.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/139.usbdev_tx_rx_disruption.4241258725
Short name T3052
Test name
Test status
Simulation time 477794226 ps
CPU time 1.41 seconds
Started Aug 11 07:16:55 PM PDT 24
Finished Aug 11 07:16:57 PM PDT 24
Peak memory 207512 kb
Host smart-7f4ed380-f8dd-4e8d-9a48-442ce3a6e431
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241258725 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.usbdev_tx_rx_disruption.4241258725
Directory /workspace/139.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/14.usbdev_alert_test.2461352110
Short name T3541
Test name
Test status
Simulation time 100508967 ps
CPU time 0.73 seconds
Started Aug 11 07:11:20 PM PDT 24
Finished Aug 11 07:11:21 PM PDT 24
Peak memory 207556 kb
Host smart-224a94eb-869c-48d1-b9b6-af161f1865c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2461352110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2461352110
Directory /workspace/14.usbdev_alert_test/latest


Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1286481424
Short name T1945
Test name
Test status
Simulation time 15616807403 ps
CPU time 19.28 seconds
Started Aug 11 07:11:14 PM PDT 24
Finished Aug 11 07:11:33 PM PDT 24
Peak memory 216048 kb
Host smart-49b6138f-d3af-4485-9fbc-13b9300c22cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286481424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1286481424
Directory /workspace/14.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3588192577
Short name T742
Test name
Test status
Simulation time 25994374010 ps
CPU time 30.51 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:47 PM PDT 24
Peak memory 216024 kb
Host smart-0c202f8b-184f-419e-84a4-722e850d22df
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588192577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.3588192577
Directory /workspace/14.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/14.usbdev_av_buffer.2071542282
Short name T3617
Test name
Test status
Simulation time 153459387 ps
CPU time 0.89 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:17 PM PDT 24
Peak memory 207536 kb
Host smart-551d76cb-e12d-4b51-82ee-7bff3c12a8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715
42282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2071542282
Directory /workspace/14.usbdev_av_buffer/latest


Test location /workspace/coverage/default/14.usbdev_bitstuff_err.1520506575
Short name T3261
Test name
Test status
Simulation time 175888000 ps
CPU time 0.95 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207484 kb
Host smart-217ed6e8-a8eb-4993-aa9d-df62d4b06d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15205
06575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1520506575
Directory /workspace/14.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.4277064746
Short name T562
Test name
Test status
Simulation time 484851322 ps
CPU time 1.59 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207452 kb
Host smart-15bc68fd-e7a0-4898-b56f-a2b506198595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
64746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.4277064746
Directory /workspace/14.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.4274086710
Short name T3015
Test name
Test status
Simulation time 784196508 ps
CPU time 2.26 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 207808 kb
Host smart-09405e41-a3c4-4eb9-9489-34c308eb5dd1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4274086710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.4274086710
Directory /workspace/14.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/14.usbdev_device_address.384561554
Short name T464
Test name
Test status
Simulation time 31729210984 ps
CPU time 53.95 seconds
Started Aug 11 07:11:19 PM PDT 24
Finished Aug 11 07:12:13 PM PDT 24
Peak memory 207784 kb
Host smart-edc6f633-5ee8-4930-8173-4d4618275b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38456
1554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.384561554
Directory /workspace/14.usbdev_device_address/latest


Test location /workspace/coverage/default/14.usbdev_device_timeout.869315684
Short name T3136
Test name
Test status
Simulation time 1112318557 ps
CPU time 9.08 seconds
Started Aug 11 07:11:19 PM PDT 24
Finished Aug 11 07:11:28 PM PDT 24
Peak memory 207728 kb
Host smart-0b80272a-ec9f-48b7-89d1-bb631a7139ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869315684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.869315684
Directory /workspace/14.usbdev_device_timeout/latest


Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3716252338
Short name T1643
Test name
Test status
Simulation time 827554106 ps
CPU time 2.02 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207528 kb
Host smart-1b13eb07-876a-44cc-86d9-2a91b2271805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37162
52338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3716252338
Directory /workspace/14.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/14.usbdev_disconnected.2134556324
Short name T45
Test name
Test status
Simulation time 139481948 ps
CPU time 0.84 seconds
Started Aug 11 07:11:18 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207516 kb
Host smart-c6f09d29-363b-4816-88b4-c76f76d39e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
56324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2134556324
Directory /workspace/14.usbdev_disconnected/latest


Test location /workspace/coverage/default/14.usbdev_enable.597525555
Short name T2908
Test name
Test status
Simulation time 31802076 ps
CPU time 0.7 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:17 PM PDT 24
Peak memory 207520 kb
Host smart-a1040613-29f4-4c8a-a142-977ffec82512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59752
5555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.597525555
Directory /workspace/14.usbdev_enable/latest


Test location /workspace/coverage/default/14.usbdev_endpoint_access.4278646568
Short name T731
Test name
Test status
Simulation time 899581246 ps
CPU time 2.29 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207692 kb
Host smart-652816b7-bdf9-405d-8ddf-ce5da3989873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42786
46568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.4278646568
Directory /workspace/14.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/14.usbdev_endpoint_types.4226987677
Short name T2771
Test name
Test status
Simulation time 167803569 ps
CPU time 0.91 seconds
Started Aug 11 07:11:19 PM PDT 24
Finished Aug 11 07:11:20 PM PDT 24
Peak memory 207504 kb
Host smart-d44b95b1-a941-4d1f-ba5b-b86b3c39f891
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4226987677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.4226987677
Directory /workspace/14.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/14.usbdev_fifo_rst.1518299726
Short name T39
Test name
Test status
Simulation time 231009240 ps
CPU time 1.69 seconds
Started Aug 11 07:11:18 PM PDT 24
Finished Aug 11 07:11:20 PM PDT 24
Peak memory 207652 kb
Host smart-a3de26e5-89b0-4b55-934c-028413f84094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15182
99726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1518299726
Directory /workspace/14.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/14.usbdev_in_iso.3074058202
Short name T3222
Test name
Test status
Simulation time 176129169 ps
CPU time 0.98 seconds
Started Aug 11 07:11:18 PM PDT 24
Finished Aug 11 07:11:20 PM PDT 24
Peak memory 215808 kb
Host smart-9ecd1f48-4c0b-4cb1-8f0a-5971e3adba65
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3074058202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3074058202
Directory /workspace/14.usbdev_in_iso/latest


Test location /workspace/coverage/default/14.usbdev_in_stall.3697431067
Short name T3023
Test name
Test status
Simulation time 146655817 ps
CPU time 0.81 seconds
Started Aug 11 07:11:20 PM PDT 24
Finished Aug 11 07:11:21 PM PDT 24
Peak memory 207480 kb
Host smart-bc013757-a921-40eb-b1da-0c6926c60c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36974
31067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3697431067
Directory /workspace/14.usbdev_in_stall/latest


Test location /workspace/coverage/default/14.usbdev_in_trans.225494502
Short name T833
Test name
Test status
Simulation time 173034829 ps
CPU time 0.87 seconds
Started Aug 11 07:11:15 PM PDT 24
Finished Aug 11 07:11:16 PM PDT 24
Peak memory 207580 kb
Host smart-e4e7d489-8810-46c5-acfb-769216107ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22549
4502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.225494502
Directory /workspace/14.usbdev_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_invalid_sync.722859402
Short name T766
Test name
Test status
Simulation time 3333628810 ps
CPU time 98.93 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:12:56 PM PDT 24
Peak memory 224248 kb
Host smart-88e22eb1-a8f5-4659-b4d7-b9d907feb46e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=722859402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.722859402
Directory /workspace/14.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/14.usbdev_iso_retraction.3547825753
Short name T1529
Test name
Test status
Simulation time 6311171810 ps
CPU time 83.08 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:12:40 PM PDT 24
Peak memory 207836 kb
Host smart-14dbb867-a130-4f04-ab27-fff43386ce8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3547825753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3547825753
Directory /workspace/14.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/14.usbdev_link_in_err.4259955959
Short name T785
Test name
Test status
Simulation time 246642233 ps
CPU time 1.02 seconds
Started Aug 11 07:11:18 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207480 kb
Host smart-325020c2-f61f-497a-91a0-3d02a373c2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42599
55959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.4259955959
Directory /workspace/14.usbdev_link_in_err/latest


Test location /workspace/coverage/default/14.usbdev_link_resume.356285487
Short name T2965
Test name
Test status
Simulation time 29470847096 ps
CPU time 43.98 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 207800 kb
Host smart-9ede0e4e-82ed-4091-8c49-18eaac7ee632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35628
5487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.356285487
Directory /workspace/14.usbdev_link_resume/latest


Test location /workspace/coverage/default/14.usbdev_link_suspend.1769296389
Short name T1555
Test name
Test status
Simulation time 3459177309 ps
CPU time 5.46 seconds
Started Aug 11 07:11:19 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 216008 kb
Host smart-623e4e96-1777-4d48-9e2b-ef077da6aaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17692
96389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1769296389
Directory /workspace/14.usbdev_link_suspend/latest


Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.4004078591
Short name T644
Test name
Test status
Simulation time 2625468707 ps
CPU time 76.1 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:12:32 PM PDT 24
Peak memory 218496 kb
Host smart-037130c9-6013-4b37-9225-aa4def5be806
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4004078591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.4004078591
Directory /workspace/14.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1302967916
Short name T207
Test name
Test status
Simulation time 2172165648 ps
CPU time 17.15 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:34 PM PDT 24
Peak memory 217672 kb
Host smart-01b4240b-4167-4a9d-bb17-3a78bd82c245
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1302967916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1302967916
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1607748
Short name T1521
Test name
Test status
Simulation time 242627594 ps
CPU time 1.04 seconds
Started Aug 11 07:11:18 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207536 kb
Host smart-092e0f95-a0cd-4816-843c-9d146fa874b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1607748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1607748
Directory /workspace/14.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.404343428
Short name T705
Test name
Test status
Simulation time 194041605 ps
CPU time 0.99 seconds
Started Aug 11 07:11:19 PM PDT 24
Finished Aug 11 07:11:20 PM PDT 24
Peak memory 207548 kb
Host smart-f884ecef-3129-41fc-8258-28e43803a86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40434
3428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.404343428
Directory /workspace/14.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.2394814154
Short name T2831
Test name
Test status
Simulation time 3086762344 ps
CPU time 29.44 seconds
Started Aug 11 07:11:16 PM PDT 24
Finished Aug 11 07:11:46 PM PDT 24
Peak memory 218144 kb
Host smart-281fa0a1-cc63-4d88-afae-e59cbce0ebf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23948
14154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.2394814154
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1602144965
Short name T1385
Test name
Test status
Simulation time 3299063700 ps
CPU time 36.6 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:54 PM PDT 24
Peak memory 217888 kb
Host smart-49a01bea-d842-4b16-a303-ce5d3c5adcb6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1602144965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1602144965
Directory /workspace/14.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.71296416
Short name T3112
Test name
Test status
Simulation time 3476717574 ps
CPU time 34.04 seconds
Started Aug 11 07:11:17 PM PDT 24
Finished Aug 11 07:11:51 PM PDT 24
Peak memory 216044 kb
Host smart-bf3875ca-ea48-4643-9731-34a01c3778c9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=71296416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.71296416
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3088653840
Short name T1008
Test name
Test status
Simulation time 160606516 ps
CPU time 0.86 seconds
Started Aug 11 07:11:22 PM PDT 24
Finished Aug 11 07:11:23 PM PDT 24
Peak memory 207476 kb
Host smart-a8ff818e-ccd1-4e22-aca5-c029663aa194
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3088653840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3088653840
Directory /workspace/14.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3919588550
Short name T2876
Test name
Test status
Simulation time 181481231 ps
CPU time 0.87 seconds
Started Aug 11 07:11:22 PM PDT 24
Finished Aug 11 07:11:23 PM PDT 24
Peak memory 207528 kb
Host smart-59443940-d461-413c-8e2e-bb7935291cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39195
88550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3919588550
Directory /workspace/14.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_nak_trans.2834351347
Short name T163
Test name
Test status
Simulation time 208700653 ps
CPU time 0.97 seconds
Started Aug 11 07:11:27 PM PDT 24
Finished Aug 11 07:11:28 PM PDT 24
Peak memory 207572 kb
Host smart-7970f7a1-f78b-4511-a02e-20c218cc01bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28343
51347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2834351347
Directory /workspace/14.usbdev_nak_trans/latest


Test location /workspace/coverage/default/14.usbdev_out_iso.1448720260
Short name T1759
Test name
Test status
Simulation time 168142944 ps
CPU time 0.85 seconds
Started Aug 11 07:11:21 PM PDT 24
Finished Aug 11 07:11:22 PM PDT 24
Peak memory 207548 kb
Host smart-b1cbf323-8988-4f02-82de-6751a0a29852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14487
20260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1448720260
Directory /workspace/14.usbdev_out_iso/latest


Test location /workspace/coverage/default/14.usbdev_out_stall.772722804
Short name T3347
Test name
Test status
Simulation time 196900610 ps
CPU time 0.9 seconds
Started Aug 11 07:11:21 PM PDT 24
Finished Aug 11 07:11:22 PM PDT 24
Peak memory 207460 kb
Host smart-3151980c-a77b-46b8-8128-06f65ebd6205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77272
2804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.772722804
Directory /workspace/14.usbdev_out_stall/latest


Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2265993652
Short name T885
Test name
Test status
Simulation time 213950666 ps
CPU time 0.92 seconds
Started Aug 11 07:11:25 PM PDT 24
Finished Aug 11 07:11:26 PM PDT 24
Peak memory 207544 kb
Host smart-5ade4fa7-c5a4-4e54-ae4a-8da4c9550998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22659
93652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2265993652
Directory /workspace/14.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1677946112
Short name T181
Test name
Test status
Simulation time 148189266 ps
CPU time 0.87 seconds
Started Aug 11 07:11:21 PM PDT 24
Finished Aug 11 07:11:22 PM PDT 24
Peak memory 207592 kb
Host smart-5d43400b-b798-4e76-860b-c857cb5e793b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16779
46112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1677946112
Directory /workspace/14.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1094047474
Short name T614
Test name
Test status
Simulation time 222316416 ps
CPU time 1.11 seconds
Started Aug 11 07:11:23 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 207528 kb
Host smart-8399890f-52c1-4b50-83d2-fc4b1734e2f7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1094047474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1094047474
Directory /workspace/14.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.4004228142
Short name T2252
Test name
Test status
Simulation time 152339366 ps
CPU time 0.85 seconds
Started Aug 11 07:11:26 PM PDT 24
Finished Aug 11 07:11:27 PM PDT 24
Peak memory 207516 kb
Host smart-5cfb7cfd-c150-44af-91af-e3643e56d400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042
28142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.4004228142
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3579522736
Short name T1376
Test name
Test status
Simulation time 44240047 ps
CPU time 0.71 seconds
Started Aug 11 07:11:22 PM PDT 24
Finished Aug 11 07:11:22 PM PDT 24
Peak memory 207480 kb
Host smart-f56685b1-813e-4c50-b7f2-e092fa6619fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35795
22736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3579522736
Directory /workspace/14.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3509122100
Short name T298
Test name
Test status
Simulation time 21798303276 ps
CPU time 54.08 seconds
Started Aug 11 07:11:23 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 216064 kb
Host smart-ac2bad14-2cfd-403f-8627-a7769aa0913a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091
22100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3509122100
Directory /workspace/14.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/14.usbdev_pkt_received.4288270008
Short name T2575
Test name
Test status
Simulation time 162558833 ps
CPU time 0.9 seconds
Started Aug 11 07:11:24 PM PDT 24
Finished Aug 11 07:11:25 PM PDT 24
Peak memory 207572 kb
Host smart-58191980-3f72-4c56-92ef-10dbdeea5781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42882
70008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4288270008
Directory /workspace/14.usbdev_pkt_received/latest


Test location /workspace/coverage/default/14.usbdev_pkt_sent.499742034
Short name T289
Test name
Test status
Simulation time 186771695 ps
CPU time 0.89 seconds
Started Aug 11 07:11:21 PM PDT 24
Finished Aug 11 07:11:22 PM PDT 24
Peak memory 207496 kb
Host smart-1dfcc453-d35e-4f9e-a0c7-2a65dc6094b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49974
2034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.499742034
Directory /workspace/14.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.1941712469
Short name T3351
Test name
Test status
Simulation time 214541059 ps
CPU time 0.92 seconds
Started Aug 11 07:11:24 PM PDT 24
Finished Aug 11 07:11:25 PM PDT 24
Peak memory 207536 kb
Host smart-cab38f3d-0cff-453e-9081-47493d83e8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19417
12469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.1941712469
Directory /workspace/14.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2635281340
Short name T2984
Test name
Test status
Simulation time 153729682 ps
CPU time 0.84 seconds
Started Aug 11 07:11:22 PM PDT 24
Finished Aug 11 07:11:23 PM PDT 24
Peak memory 207572 kb
Host smart-b6f7f07e-bd8a-4871-a0a9-70b596f78ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26352
81340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2635281340
Directory /workspace/14.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_resume_link_active.3217179561
Short name T2255
Test name
Test status
Simulation time 20184428923 ps
CPU time 26.62 seconds
Started Aug 11 07:11:25 PM PDT 24
Finished Aug 11 07:11:52 PM PDT 24
Peak memory 207600 kb
Host smart-178ecd95-86f1-42b7-9dab-593878935a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32171
79561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.3217179561
Directory /workspace/14.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/14.usbdev_rx_crc_err.519914708
Short name T962
Test name
Test status
Simulation time 195781835 ps
CPU time 0.92 seconds
Started Aug 11 07:11:26 PM PDT 24
Finished Aug 11 07:11:27 PM PDT 24
Peak memory 207548 kb
Host smart-e0dabf50-98b9-4be9-8a95-cdede5e2c9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51991
4708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.519914708
Directory /workspace/14.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/14.usbdev_rx_full.179666365
Short name T1298
Test name
Test status
Simulation time 429567689 ps
CPU time 1.45 seconds
Started Aug 11 07:11:23 PM PDT 24
Finished Aug 11 07:11:25 PM PDT 24
Peak memory 207580 kb
Host smart-6d3b42df-f38d-48a7-9119-1ecf4edfcc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17966
6365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.179666365
Directory /workspace/14.usbdev_rx_full/latest


Test location /workspace/coverage/default/14.usbdev_setup_stage.37103351
Short name T753
Test name
Test status
Simulation time 156223787 ps
CPU time 0.91 seconds
Started Aug 11 07:11:23 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 207512 kb
Host smart-b8ae6b12-39f0-49f3-8ae4-f008e4eaa047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37103
351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.37103351
Directory /workspace/14.usbdev_setup_stage/latest


Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2849638977
Short name T2938
Test name
Test status
Simulation time 149961402 ps
CPU time 0.85 seconds
Started Aug 11 07:11:25 PM PDT 24
Finished Aug 11 07:11:26 PM PDT 24
Peak memory 207544 kb
Host smart-d1b08b00-8687-436b-af6e-0ee4b3b52ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28496
38977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2849638977
Directory /workspace/14.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/14.usbdev_smoke.738357766
Short name T1795
Test name
Test status
Simulation time 234863298 ps
CPU time 1.07 seconds
Started Aug 11 07:11:26 PM PDT 24
Finished Aug 11 07:11:27 PM PDT 24
Peak memory 207476 kb
Host smart-25e80c96-f5a5-4a6e-9d84-c3813bc9efdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73835
7766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.738357766
Directory /workspace/14.usbdev_smoke/latest


Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2800791434
Short name T1021
Test name
Test status
Simulation time 3171052463 ps
CPU time 88.93 seconds
Started Aug 11 07:11:26 PM PDT 24
Finished Aug 11 07:12:55 PM PDT 24
Peak memory 217560 kb
Host smart-f706a6f8-b1b7-4511-a066-84c5b08d11c1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2800791434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2800791434
Directory /workspace/14.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2714993447
Short name T672
Test name
Test status
Simulation time 149905354 ps
CPU time 0.85 seconds
Started Aug 11 07:11:22 PM PDT 24
Finished Aug 11 07:11:23 PM PDT 24
Peak memory 207524 kb
Host smart-c6e89d12-718e-4ba6-a613-23dfa3b99997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27149
93447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2714993447
Directory /workspace/14.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/14.usbdev_stall_trans.2251243649
Short name T1941
Test name
Test status
Simulation time 236616624 ps
CPU time 1.01 seconds
Started Aug 11 07:11:20 PM PDT 24
Finished Aug 11 07:11:21 PM PDT 24
Peak memory 207576 kb
Host smart-9a3345cc-b5b0-4e0f-851b-0274c5ade403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22512
43649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2251243649
Directory /workspace/14.usbdev_stall_trans/latest


Test location /workspace/coverage/default/14.usbdev_stream_len_max.535897081
Short name T2038
Test name
Test status
Simulation time 264743014 ps
CPU time 1.12 seconds
Started Aug 11 07:11:22 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 207716 kb
Host smart-2e983167-77f0-4553-86b6-acced81dce74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53589
7081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.535897081
Directory /workspace/14.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/14.usbdev_streaming_out.463189685
Short name T2515
Test name
Test status
Simulation time 3084468907 ps
CPU time 32.08 seconds
Started Aug 11 07:11:25 PM PDT 24
Finished Aug 11 07:11:58 PM PDT 24
Peak memory 217744 kb
Host smart-3eb32354-dc0d-4525-8295-10d2feed5f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46318
9685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.463189685
Directory /workspace/14.usbdev_streaming_out/latest


Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.2841721482
Short name T2064
Test name
Test status
Simulation time 3574653449 ps
CPU time 22.05 seconds
Started Aug 11 07:11:15 PM PDT 24
Finished Aug 11 07:11:37 PM PDT 24
Peak memory 207816 kb
Host smart-c07d9ecf-3c1c-461e-bb63-be947cd25073
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841721482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.2841721482
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/14.usbdev_tx_rx_disruption.1337623088
Short name T2258
Test name
Test status
Simulation time 597068036 ps
CPU time 1.63 seconds
Started Aug 11 07:11:23 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 207552 kb
Host smart-54a7429e-dd6f-4de9-b178-560bc76ded48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337623088 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.usbdev_tx_rx_disruption.1337623088
Directory /workspace/14.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/140.usbdev_endpoint_types.1466836243
Short name T524
Test name
Test status
Simulation time 261424002 ps
CPU time 1.1 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207532 kb
Host smart-74642e15-d6ad-40af-a586-964b9f4bf5aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1466836243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.1466836243
Directory /workspace/140.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/140.usbdev_tx_rx_disruption.1735600882
Short name T3426
Test name
Test status
Simulation time 575762139 ps
CPU time 1.73 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207600 kb
Host smart-98c3ff15-bf94-44d1-af36-ae9e8303e168
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735600882 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.usbdev_tx_rx_disruption.1735600882
Directory /workspace/140.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/141.usbdev_tx_rx_disruption.2009600280
Short name T2648
Test name
Test status
Simulation time 501698913 ps
CPU time 1.55 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207528 kb
Host smart-e00d22b0-b998-4a53-a41d-986234cabc0e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009600280 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.usbdev_tx_rx_disruption.2009600280
Directory /workspace/141.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/142.usbdev_endpoint_types.1425022390
Short name T3179
Test name
Test status
Simulation time 571034112 ps
CPU time 1.58 seconds
Started Aug 11 07:17:17 PM PDT 24
Finished Aug 11 07:17:19 PM PDT 24
Peak memory 207540 kb
Host smart-5d84dafa-e305-4549-b802-2b37bf927376
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1425022390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.1425022390
Directory /workspace/142.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/142.usbdev_tx_rx_disruption.2399322862
Short name T178
Test name
Test status
Simulation time 527032621 ps
CPU time 1.59 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207524 kb
Host smart-cc70440c-3180-4b8f-a7b2-006abf49c5a2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399322862 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.usbdev_tx_rx_disruption.2399322862
Directory /workspace/142.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/143.usbdev_endpoint_types.3037933933
Short name T441
Test name
Test status
Simulation time 707063201 ps
CPU time 1.53 seconds
Started Aug 11 07:17:15 PM PDT 24
Finished Aug 11 07:17:16 PM PDT 24
Peak memory 207456 kb
Host smart-721492c7-45c5-4f6b-9a59-e95278e03a08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3037933933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.3037933933
Directory /workspace/143.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/143.usbdev_tx_rx_disruption.3842284169
Short name T1439
Test name
Test status
Simulation time 472493353 ps
CPU time 1.46 seconds
Started Aug 11 07:17:10 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 207592 kb
Host smart-b0d44f48-4346-46ad-b293-38099d0123c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842284169 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.usbdev_tx_rx_disruption.3842284169
Directory /workspace/143.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/144.usbdev_tx_rx_disruption.582671724
Short name T208
Test name
Test status
Simulation time 656454641 ps
CPU time 1.63 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 207548 kb
Host smart-6217b39e-26c5-45ab-b350-0c561f3814ae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582671724 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 144.usbdev_tx_rx_disruption.582671724
Directory /workspace/144.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/145.usbdev_endpoint_types.3069135660
Short name T484
Test name
Test status
Simulation time 665149557 ps
CPU time 1.64 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207560 kb
Host smart-d81d02bf-3f85-42fd-a907-16f85eddb799
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3069135660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.3069135660
Directory /workspace/145.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/145.usbdev_tx_rx_disruption.2051738973
Short name T3048
Test name
Test status
Simulation time 557813492 ps
CPU time 1.58 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 207584 kb
Host smart-b5624757-d8ac-4938-8b75-88a40d1a4b3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051738973 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.usbdev_tx_rx_disruption.2051738973
Directory /workspace/145.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/146.usbdev_endpoint_types.1738465742
Short name T3058
Test name
Test status
Simulation time 534388852 ps
CPU time 1.42 seconds
Started Aug 11 07:17:28 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207544 kb
Host smart-7c371f7c-007a-4dd8-904e-f0e877d69ee6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1738465742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.1738465742
Directory /workspace/146.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/146.usbdev_tx_rx_disruption.1667402622
Short name T883
Test name
Test status
Simulation time 637548844 ps
CPU time 1.67 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207568 kb
Host smart-d84a1e71-53a0-46ad-83d5-d07fecf93ecc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667402622 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.usbdev_tx_rx_disruption.1667402622
Directory /workspace/146.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/147.usbdev_endpoint_types.3352258970
Short name T404
Test name
Test status
Simulation time 443385133 ps
CPU time 1.42 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207524 kb
Host smart-6d14600e-5ca1-4521-b79c-8aa1b6db625d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3352258970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.3352258970
Directory /workspace/147.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/148.usbdev_tx_rx_disruption.3470481243
Short name T195
Test name
Test status
Simulation time 416246629 ps
CPU time 1.37 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207524 kb
Host smart-e8bf8b12-ddd5-417d-ad77-0463962950d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470481243 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.usbdev_tx_rx_disruption.3470481243
Directory /workspace/148.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/149.usbdev_endpoint_types.1076442008
Short name T2982
Test name
Test status
Simulation time 379039316 ps
CPU time 1.17 seconds
Started Aug 11 07:17:04 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207468 kb
Host smart-d3983b09-6570-4db6-813a-58f190e9f872
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1076442008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.1076442008
Directory /workspace/149.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/149.usbdev_tx_rx_disruption.2505956788
Short name T798
Test name
Test status
Simulation time 501563810 ps
CPU time 1.58 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207548 kb
Host smart-858103fd-8b77-4e4c-a58d-6f506392e470
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505956788 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.usbdev_tx_rx_disruption.2505956788
Directory /workspace/149.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/15.usbdev_alert_test.3114014963
Short name T724
Test name
Test status
Simulation time 65214543 ps
CPU time 0.7 seconds
Started Aug 11 07:11:35 PM PDT 24
Finished Aug 11 07:11:36 PM PDT 24
Peak memory 207572 kb
Host smart-1d2083fb-f63f-4fa0-b2d0-b7b620fd9ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3114014963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3114014963
Directory /workspace/15.usbdev_alert_test/latest


Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3341991575
Short name T2152
Test name
Test status
Simulation time 6574739568 ps
CPU time 10.5 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:39 PM PDT 24
Peak memory 215944 kb
Host smart-4e06d8b7-b05d-400a-a8d5-d4a54c186ab0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341991575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.3341991575
Directory /workspace/15.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3913658919
Short name T2594
Test name
Test status
Simulation time 19297123500 ps
CPU time 21.9 seconds
Started Aug 11 07:11:20 PM PDT 24
Finished Aug 11 07:11:42 PM PDT 24
Peak memory 207876 kb
Host smart-d6debbd7-e2c0-4663-8261-b60200d542c7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913658919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3913658919
Directory /workspace/15.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1165093659
Short name T1536
Test name
Test status
Simulation time 29662136979 ps
CPU time 37.86 seconds
Started Aug 11 07:11:23 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 207792 kb
Host smart-a354bae2-9748-4e9a-be77-39fe00838ee0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165093659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.1165093659
Directory /workspace/15.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/15.usbdev_av_buffer.2971786863
Short name T576
Test name
Test status
Simulation time 172173161 ps
CPU time 0.88 seconds
Started Aug 11 07:11:24 PM PDT 24
Finished Aug 11 07:11:25 PM PDT 24
Peak memory 207552 kb
Host smart-aca64242-6a71-403b-b01f-842290e0c2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29717
86863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2971786863
Directory /workspace/15.usbdev_av_buffer/latest


Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1883083418
Short name T3150
Test name
Test status
Simulation time 144192072 ps
CPU time 0.87 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:31 PM PDT 24
Peak memory 207544 kb
Host smart-8a8f69eb-13e9-4328-8450-064f66863d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18830
83418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1883083418
Directory /workspace/15.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.3943091712
Short name T3343
Test name
Test status
Simulation time 285869995 ps
CPU time 1.12 seconds
Started Aug 11 07:11:28 PM PDT 24
Finished Aug 11 07:11:29 PM PDT 24
Peak memory 207572 kb
Host smart-89a4bd41-2421-47f8-8fa9-c7c9413f9c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39430
91712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.3943091712
Directory /workspace/15.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2624110207
Short name T2940
Test name
Test status
Simulation time 1377449990 ps
CPU time 3.66 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:34 PM PDT 24
Peak memory 207728 kb
Host smart-31b6c681-6523-40c8-b44f-249f78f44430
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2624110207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2624110207
Directory /workspace/15.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/15.usbdev_device_address.3246488424
Short name T1627
Test name
Test status
Simulation time 32703608893 ps
CPU time 50.8 seconds
Started Aug 11 07:11:28 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207868 kb
Host smart-7f66f7f4-b6fe-4615-b72f-c8bc9e9e1922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32464
88424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3246488424
Directory /workspace/15.usbdev_device_address/latest


Test location /workspace/coverage/default/15.usbdev_device_timeout.541052355
Short name T2017
Test name
Test status
Simulation time 947400733 ps
CPU time 18.4 seconds
Started Aug 11 07:11:33 PM PDT 24
Finished Aug 11 07:11:51 PM PDT 24
Peak memory 207688 kb
Host smart-1bb978b5-adc2-4fbe-a865-6415f1fded01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541052355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.541052355
Directory /workspace/15.usbdev_device_timeout/latest


Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2291811180
Short name T1326
Test name
Test status
Simulation time 609748121 ps
CPU time 1.59 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:30 PM PDT 24
Peak memory 207492 kb
Host smart-44c5cc05-5286-45ff-80f0-594f5456f49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22918
11180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2291811180
Directory /workspace/15.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/15.usbdev_disconnected.3862281083
Short name T2096
Test name
Test status
Simulation time 157805806 ps
CPU time 0.84 seconds
Started Aug 11 07:11:28 PM PDT 24
Finished Aug 11 07:11:29 PM PDT 24
Peak memory 207448 kb
Host smart-a9814a96-3c33-4c70-9909-aa3e2ac3e67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
81083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3862281083
Directory /workspace/15.usbdev_disconnected/latest


Test location /workspace/coverage/default/15.usbdev_enable.1658200362
Short name T1218
Test name
Test status
Simulation time 78790556 ps
CPU time 0.76 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:30 PM PDT 24
Peak memory 207424 kb
Host smart-91f89b0a-ab92-49bc-9d6c-d9aad6c1e056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16582
00362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1658200362
Directory /workspace/15.usbdev_enable/latest


Test location /workspace/coverage/default/15.usbdev_endpoint_access.2780150075
Short name T2712
Test name
Test status
Simulation time 785272675 ps
CPU time 2.2 seconds
Started Aug 11 07:11:28 PM PDT 24
Finished Aug 11 07:11:31 PM PDT 24
Peak memory 207764 kb
Host smart-8d5a37a4-a18e-478f-a312-807cc97fabd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27801
50075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2780150075
Directory /workspace/15.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/15.usbdev_fifo_rst.391634646
Short name T1180
Test name
Test status
Simulation time 168071347 ps
CPU time 1.46 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:32 PM PDT 24
Peak memory 207640 kb
Host smart-75d48777-3762-4da4-89be-19fccf8f6ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39163
4646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.391634646
Directory /workspace/15.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/15.usbdev_in_iso.4055356260
Short name T2305
Test name
Test status
Simulation time 254700264 ps
CPU time 1.2 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:31 PM PDT 24
Peak memory 215864 kb
Host smart-60602e9d-4772-4fec-94b9-15a4f46799ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4055356260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.4055356260
Directory /workspace/15.usbdev_in_iso/latest


Test location /workspace/coverage/default/15.usbdev_in_stall.774265837
Short name T1266
Test name
Test status
Simulation time 143184194 ps
CPU time 0.84 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:30 PM PDT 24
Peak memory 207500 kb
Host smart-d87a87b6-75d2-4cdb-8d3a-72e9aa3d2dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77426
5837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.774265837
Directory /workspace/15.usbdev_in_stall/latest


Test location /workspace/coverage/default/15.usbdev_in_trans.3798658850
Short name T637
Test name
Test status
Simulation time 233187108 ps
CPU time 1.04 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:31 PM PDT 24
Peak memory 207480 kb
Host smart-0b2d69ba-308a-497a-b095-23b765a522db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37986
58850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3798658850
Directory /workspace/15.usbdev_in_trans/latest


Test location /workspace/coverage/default/15.usbdev_invalid_sync.1972935855
Short name T3216
Test name
Test status
Simulation time 4620550162 ps
CPU time 44.79 seconds
Started Aug 11 07:11:27 PM PDT 24
Finished Aug 11 07:12:12 PM PDT 24
Peak memory 224232 kb
Host smart-0cbe8e3d-d336-4331-bbd6-f8b402cfa2e4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1972935855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1972935855
Directory /workspace/15.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/15.usbdev_iso_retraction.2629287354
Short name T1770
Test name
Test status
Simulation time 7276486344 ps
CPU time 53.62 seconds
Started Aug 11 07:11:28 PM PDT 24
Finished Aug 11 07:12:22 PM PDT 24
Peak memory 207824 kb
Host smart-2394c3e9-1787-403a-8750-5943d4f252f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2629287354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.2629287354
Directory /workspace/15.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/15.usbdev_link_in_err.2786805284
Short name T1314
Test name
Test status
Simulation time 219047157 ps
CPU time 1 seconds
Started Aug 11 07:11:28 PM PDT 24
Finished Aug 11 07:11:29 PM PDT 24
Peak memory 207532 kb
Host smart-e6203099-7f6f-419e-9acd-3bc339ce6ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27868
05284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2786805284
Directory /workspace/15.usbdev_link_in_err/latest


Test location /workspace/coverage/default/15.usbdev_link_resume.336337205
Short name T2439
Test name
Test status
Simulation time 23840002947 ps
CPU time 29.18 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:59 PM PDT 24
Peak memory 216032 kb
Host smart-b01171c6-c01d-43b2-b01a-de536265978c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
7205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.336337205
Directory /workspace/15.usbdev_link_resume/latest


Test location /workspace/coverage/default/15.usbdev_link_suspend.1000828569
Short name T843
Test name
Test status
Simulation time 4945929039 ps
CPU time 6.52 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:37 PM PDT 24
Peak memory 216860 kb
Host smart-f4365c57-e800-4855-8650-79379f6ded2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10008
28569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1000828569
Directory /workspace/15.usbdev_link_suspend/latest


Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2883931574
Short name T1297
Test name
Test status
Simulation time 3118081795 ps
CPU time 91.65 seconds
Started Aug 11 07:11:36 PM PDT 24
Finished Aug 11 07:13:08 PM PDT 24
Peak memory 218432 kb
Host smart-856b5f0d-7ffc-4af5-93ba-8ce71d984619
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2883931574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2883931574
Directory /workspace/15.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2112959714
Short name T2742
Test name
Test status
Simulation time 3909287679 ps
CPU time 113.24 seconds
Started Aug 11 07:11:28 PM PDT 24
Finished Aug 11 07:13:21 PM PDT 24
Peak memory 216096 kb
Host smart-f7cff86b-80c3-4254-9a2a-c1d5dcc05c6c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2112959714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2112959714
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.4036843646
Short name T1681
Test name
Test status
Simulation time 241082754 ps
CPU time 0.96 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:31 PM PDT 24
Peak memory 207492 kb
Host smart-00910c24-eb35-482d-b242-82a59a0598fb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4036843646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.4036843646
Directory /workspace/15.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3135988746
Short name T2724
Test name
Test status
Simulation time 191288857 ps
CPU time 0.9 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:30 PM PDT 24
Peak memory 207552 kb
Host smart-b9c54288-dcaa-4e6a-9a51-09e0d19f5fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31359
88746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3135988746
Directory /workspace/15.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.1135177048
Short name T1892
Test name
Test status
Simulation time 3395978637 ps
CPU time 99.74 seconds
Started Aug 11 07:11:31 PM PDT 24
Finished Aug 11 07:13:10 PM PDT 24
Peak memory 217852 kb
Host smart-33e39f55-8c30-427a-bc67-703b367162e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
77048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.1135177048
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3116168768
Short name T2259
Test name
Test status
Simulation time 4051393045 ps
CPU time 121.16 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:13:31 PM PDT 24
Peak memory 216124 kb
Host smart-04a45b7d-24d6-49e0-9ca1-81db16846e87
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3116168768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3116168768
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.365866237
Short name T1265
Test name
Test status
Simulation time 193814793 ps
CPU time 0.86 seconds
Started Aug 11 07:11:27 PM PDT 24
Finished Aug 11 07:11:28 PM PDT 24
Peak memory 207524 kb
Host smart-912f6b79-4c45-457a-af72-3d8b18aa0265
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=365866237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.365866237
Directory /workspace/15.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.900208916
Short name T3087
Test name
Test status
Simulation time 159812876 ps
CPU time 0.86 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:30 PM PDT 24
Peak memory 207496 kb
Host smart-d2e344a1-b2e0-4246-9ec3-be0418bfdb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90020
8916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.900208916
Directory /workspace/15.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_out_iso.3748463120
Short name T616
Test name
Test status
Simulation time 160736000 ps
CPU time 0.87 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:31 PM PDT 24
Peak memory 207484 kb
Host smart-e18417c8-8c8b-4599-9ab8-b73f85f3d949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37484
63120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3748463120
Directory /workspace/15.usbdev_out_iso/latest


Test location /workspace/coverage/default/15.usbdev_out_stall.2047623435
Short name T618
Test name
Test status
Simulation time 184849641 ps
CPU time 0.95 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:30 PM PDT 24
Peak memory 207596 kb
Host smart-0a004af8-5582-41f9-8c2c-d19c28b19b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20476
23435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2047623435
Directory /workspace/15.usbdev_out_stall/latest


Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3856753334
Short name T3531
Test name
Test status
Simulation time 149002100 ps
CPU time 0.84 seconds
Started Aug 11 07:11:27 PM PDT 24
Finished Aug 11 07:11:28 PM PDT 24
Peak memory 207544 kb
Host smart-e3868ca2-2536-4c97-9f16-3e248ea212c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567
53334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3856753334
Directory /workspace/15.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/15.usbdev_pending_in_trans.714580165
Short name T3340
Test name
Test status
Simulation time 166742637 ps
CPU time 0.86 seconds
Started Aug 11 07:11:28 PM PDT 24
Finished Aug 11 07:11:29 PM PDT 24
Peak memory 207504 kb
Host smart-0a4856e9-d6d3-4284-bcf1-88034303241f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71458
0165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.714580165
Directory /workspace/15.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.775705005
Short name T700
Test name
Test status
Simulation time 290207316 ps
CPU time 1.07 seconds
Started Aug 11 07:11:31 PM PDT 24
Finished Aug 11 07:11:32 PM PDT 24
Peak memory 207564 kb
Host smart-582b6348-1e98-455b-8ac6-663a575fea7a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=775705005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.775705005
Directory /workspace/15.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2928228237
Short name T2464
Test name
Test status
Simulation time 161382056 ps
CPU time 0.83 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:31 PM PDT 24
Peak memory 207548 kb
Host smart-c1991f8d-b2e1-4169-acad-4cae295de610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29282
28237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2928228237
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.395687472
Short name T1096
Test name
Test status
Simulation time 38483968 ps
CPU time 0.69 seconds
Started Aug 11 07:11:32 PM PDT 24
Finished Aug 11 07:11:33 PM PDT 24
Peak memory 207448 kb
Host smart-43a7a7ac-7076-4772-8715-a201f6bac80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39568
7472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.395687472
Directory /workspace/15.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2649654931
Short name T3245
Test name
Test status
Simulation time 18973172482 ps
CPU time 56.24 seconds
Started Aug 11 07:11:28 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 216048 kb
Host smart-f98b096c-b7af-44ba-a332-c2a49217e3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26496
54931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2649654931
Directory /workspace/15.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/15.usbdev_pkt_received.4164940879
Short name T1958
Test name
Test status
Simulation time 235165198 ps
CPU time 0.98 seconds
Started Aug 11 07:11:29 PM PDT 24
Finished Aug 11 07:11:30 PM PDT 24
Peak memory 207576 kb
Host smart-f7c54493-e0e4-494d-823f-60c9e5ea1f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41649
40879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.4164940879
Directory /workspace/15.usbdev_pkt_received/latest


Test location /workspace/coverage/default/15.usbdev_pkt_sent.1251537576
Short name T778
Test name
Test status
Simulation time 218963058 ps
CPU time 1.01 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:31 PM PDT 24
Peak memory 207452 kb
Host smart-e2b1e00c-e391-4dca-81b8-02dac5f3ba05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12515
37576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1251537576
Directory /workspace/15.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2482217501
Short name T30
Test name
Test status
Simulation time 173404277 ps
CPU time 0.92 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 207496 kb
Host smart-0bfaabaa-8082-4962-afa4-698f03ccb48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24822
17501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2482217501
Directory /workspace/15.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.3623247224
Short name T940
Test name
Test status
Simulation time 243011633 ps
CPU time 1.08 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 207572 kb
Host smart-8f9540bd-870f-4a7a-9c1d-62abbede3214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36232
47224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.3623247224
Directory /workspace/15.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_resume_link_active.3388466138
Short name T1051
Test name
Test status
Simulation time 20187918329 ps
CPU time 22.67 seconds
Started Aug 11 07:11:39 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 207560 kb
Host smart-c491d75e-33bb-405d-9920-49f69047a61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33884
66138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.3388466138
Directory /workspace/15.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2660869531
Short name T2535
Test name
Test status
Simulation time 188449328 ps
CPU time 0.88 seconds
Started Aug 11 07:11:36 PM PDT 24
Finished Aug 11 07:11:37 PM PDT 24
Peak memory 207528 kb
Host smart-a2b451f9-974f-40e7-9183-8a3eacb90f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26608
69531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2660869531
Directory /workspace/15.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/15.usbdev_rx_full.1002182651
Short name T53
Test name
Test status
Simulation time 388424822 ps
CPU time 1.63 seconds
Started Aug 11 07:11:42 PM PDT 24
Finished Aug 11 07:11:43 PM PDT 24
Peak memory 207576 kb
Host smart-5caf6fe5-ee50-44ea-977b-e0755b2a006c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10021
82651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.1002182651
Directory /workspace/15.usbdev_rx_full/latest


Test location /workspace/coverage/default/15.usbdev_setup_stage.758311400
Short name T2577
Test name
Test status
Simulation time 180006471 ps
CPU time 0.89 seconds
Started Aug 11 07:11:38 PM PDT 24
Finished Aug 11 07:11:39 PM PDT 24
Peak memory 207540 kb
Host smart-3424b86e-642d-446a-8414-c2e0f726b5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75831
1400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.758311400
Directory /workspace/15.usbdev_setup_stage/latest


Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2393770911
Short name T127
Test name
Test status
Simulation time 160029167 ps
CPU time 0.84 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 207508 kb
Host smart-ec5a0689-0cc8-4744-bae2-2395c39e9e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23937
70911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2393770911
Directory /workspace/15.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/15.usbdev_smoke.1467745404
Short name T2154
Test name
Test status
Simulation time 253589376 ps
CPU time 1.08 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 207440 kb
Host smart-e5354eb5-1ace-4ca9-a711-b96fb890fb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14677
45404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1467745404
Directory /workspace/15.usbdev_smoke/latest


Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.961748250
Short name T1117
Test name
Test status
Simulation time 2947839081 ps
CPU time 82.95 seconds
Started Aug 11 07:11:35 PM PDT 24
Finished Aug 11 07:12:58 PM PDT 24
Peak memory 218092 kb
Host smart-1c151662-480d-40f6-9f3e-c8e396457bec
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=961748250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.961748250
Directory /workspace/15.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2156328920
Short name T2442
Test name
Test status
Simulation time 204711956 ps
CPU time 0.95 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 207548 kb
Host smart-fe4484ab-b10c-43d7-bbe8-6ba3f5b64e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21563
28920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2156328920
Directory /workspace/15.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/15.usbdev_stall_trans.1732023857
Short name T3110
Test name
Test status
Simulation time 158661493 ps
CPU time 0.83 seconds
Started Aug 11 07:11:36 PM PDT 24
Finished Aug 11 07:11:37 PM PDT 24
Peak memory 207572 kb
Host smart-1212bd9e-2270-4d64-ba9a-ccaa6e416323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17320
23857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1732023857
Directory /workspace/15.usbdev_stall_trans/latest


Test location /workspace/coverage/default/15.usbdev_stream_len_max.2832121801
Short name T1214
Test name
Test status
Simulation time 1188210874 ps
CPU time 2.69 seconds
Started Aug 11 07:11:35 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 207680 kb
Host smart-726d36a3-ffe0-46ca-8ba5-1c837ad85d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28321
21801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2832121801
Directory /workspace/15.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/15.usbdev_streaming_out.572404639
Short name T1351
Test name
Test status
Simulation time 2445807660 ps
CPU time 72.39 seconds
Started Aug 11 07:11:34 PM PDT 24
Finished Aug 11 07:12:46 PM PDT 24
Peak memory 216036 kb
Host smart-bc9b9859-abc5-4326-a8c1-067b44aa41dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57240
4639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.572404639
Directory /workspace/15.usbdev_streaming_out/latest


Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.3148832347
Short name T1291
Test name
Test status
Simulation time 890103442 ps
CPU time 5.77 seconds
Started Aug 11 07:11:30 PM PDT 24
Finished Aug 11 07:11:35 PM PDT 24
Peak memory 207652 kb
Host smart-936a6cf6-88af-4d7d-b4e1-2cfec9d6ba43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148832347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.3148832347
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/15.usbdev_tx_rx_disruption.869076791
Short name T2717
Test name
Test status
Simulation time 522700745 ps
CPU time 1.54 seconds
Started Aug 11 07:11:42 PM PDT 24
Finished Aug 11 07:11:43 PM PDT 24
Peak memory 207600 kb
Host smart-360423ef-ab6e-440a-8b1e-c8ff87f56aeb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869076791 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.usbdev_tx_rx_disruption.869076791
Directory /workspace/15.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/150.usbdev_tx_rx_disruption.628394269
Short name T791
Test name
Test status
Simulation time 606111114 ps
CPU time 1.74 seconds
Started Aug 11 07:17:17 PM PDT 24
Finished Aug 11 07:17:18 PM PDT 24
Peak memory 207536 kb
Host smart-b7c39a4a-6342-45aa-8b17-dc2f74242c65
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628394269 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 150.usbdev_tx_rx_disruption.628394269
Directory /workspace/150.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/151.usbdev_endpoint_types.290268694
Short name T443
Test name
Test status
Simulation time 458165942 ps
CPU time 1.32 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:03 PM PDT 24
Peak memory 207544 kb
Host smart-dc4d7acf-5e0a-422b-bbb7-a74537e55822
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=290268694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.290268694
Directory /workspace/151.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/151.usbdev_tx_rx_disruption.3704370461
Short name T3215
Test name
Test status
Simulation time 500286256 ps
CPU time 1.61 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207548 kb
Host smart-b8eeb2a5-492f-4204-bc16-13c610488ee9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704370461 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.usbdev_tx_rx_disruption.3704370461
Directory /workspace/151.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/152.usbdev_endpoint_types.3889412849
Short name T427
Test name
Test status
Simulation time 811947030 ps
CPU time 1.96 seconds
Started Aug 11 07:17:09 PM PDT 24
Finished Aug 11 07:17:11 PM PDT 24
Peak memory 207484 kb
Host smart-07a30b27-0f8f-4709-b7a3-c32c40bcaa8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3889412849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.3889412849
Directory /workspace/152.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/152.usbdev_tx_rx_disruption.3696642116
Short name T1191
Test name
Test status
Simulation time 379088325 ps
CPU time 1.28 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 207568 kb
Host smart-6b00f0d0-e564-4a96-ad52-8b5b80dff625
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696642116 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.usbdev_tx_rx_disruption.3696642116
Directory /workspace/152.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/153.usbdev_endpoint_types.536860371
Short name T456
Test name
Test status
Simulation time 618592859 ps
CPU time 1.49 seconds
Started Aug 11 07:17:12 PM PDT 24
Finished Aug 11 07:17:14 PM PDT 24
Peak memory 207532 kb
Host smart-eb7655f7-db98-4fd1-92d9-da0ca4909a16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=536860371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.536860371
Directory /workspace/153.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/153.usbdev_tx_rx_disruption.3650953505
Short name T3191
Test name
Test status
Simulation time 518074019 ps
CPU time 1.6 seconds
Started Aug 11 07:17:18 PM PDT 24
Finished Aug 11 07:17:19 PM PDT 24
Peak memory 207572 kb
Host smart-a87e2ac3-7f8b-4ae3-ab6b-627f760a1233
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650953505 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.usbdev_tx_rx_disruption.3650953505
Directory /workspace/153.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/154.usbdev_endpoint_types.3268369415
Short name T403
Test name
Test status
Simulation time 642486121 ps
CPU time 1.64 seconds
Started Aug 11 07:17:12 PM PDT 24
Finished Aug 11 07:17:19 PM PDT 24
Peak memory 207540 kb
Host smart-da6f1f7d-74f2-43b5-a9ad-e587d1d91a3e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3268369415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.3268369415
Directory /workspace/154.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/154.usbdev_tx_rx_disruption.3391774726
Short name T3627
Test name
Test status
Simulation time 554253554 ps
CPU time 1.5 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207548 kb
Host smart-80452a2f-cdbf-4fbf-be38-9b7b7f078593
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391774726 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.usbdev_tx_rx_disruption.3391774726
Directory /workspace/154.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/155.usbdev_endpoint_types.1573052868
Short name T444
Test name
Test status
Simulation time 695549563 ps
CPU time 1.66 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207536 kb
Host smart-855bf8b1-ce67-4568-a8a4-b9bce37f4165
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1573052868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.1573052868
Directory /workspace/155.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/155.usbdev_tx_rx_disruption.1032685910
Short name T2682
Test name
Test status
Simulation time 532399816 ps
CPU time 1.73 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207528 kb
Host smart-83e859fe-3e13-4d06-a186-fae95bce8826
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032685910 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.usbdev_tx_rx_disruption.1032685910
Directory /workspace/155.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/156.usbdev_endpoint_types.3392658238
Short name T522
Test name
Test status
Simulation time 425826205 ps
CPU time 1.32 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207536 kb
Host smart-9b2c0761-b641-4ef6-b974-f6fcf1d135c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3392658238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.3392658238
Directory /workspace/156.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/156.usbdev_tx_rx_disruption.92222399
Short name T2307
Test name
Test status
Simulation time 558128912 ps
CPU time 1.68 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207580 kb
Host smart-2ce9d83b-7879-40aa-b94e-1310a69c5164
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92222399 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 156.usbdev_tx_rx_disruption.92222399
Directory /workspace/156.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/157.usbdev_tx_rx_disruption.1285294241
Short name T2844
Test name
Test status
Simulation time 636033924 ps
CPU time 1.68 seconds
Started Aug 11 07:17:09 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207516 kb
Host smart-6ae6af4b-dd2b-4584-ab2c-fb1b2191d393
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285294241 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.usbdev_tx_rx_disruption.1285294241
Directory /workspace/157.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/158.usbdev_endpoint_types.1198001088
Short name T448
Test name
Test status
Simulation time 483261271 ps
CPU time 1.3 seconds
Started Aug 11 07:17:10 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 207508 kb
Host smart-3ef666f9-1ba6-4ca0-9130-bf31a80f9ae4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1198001088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.1198001088
Directory /workspace/158.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/158.usbdev_tx_rx_disruption.4081689450
Short name T196
Test name
Test status
Simulation time 575477288 ps
CPU time 1.64 seconds
Started Aug 11 07:17:09 PM PDT 24
Finished Aug 11 07:17:11 PM PDT 24
Peak memory 207580 kb
Host smart-78281878-26a6-44e9-b859-bd15663cbd7e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081689450 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.usbdev_tx_rx_disruption.4081689450
Directory /workspace/158.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/159.usbdev_endpoint_types.1812090102
Short name T2053
Test name
Test status
Simulation time 166191464 ps
CPU time 0.92 seconds
Started Aug 11 07:17:09 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207512 kb
Host smart-35b5f988-74b5-4321-9d93-3a431b3a9d50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1812090102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.1812090102
Directory /workspace/159.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/159.usbdev_tx_rx_disruption.2240482050
Short name T588
Test name
Test status
Simulation time 523908523 ps
CPU time 1.54 seconds
Started Aug 11 07:17:13 PM PDT 24
Finished Aug 11 07:17:14 PM PDT 24
Peak memory 207600 kb
Host smart-27fc1cc5-0333-497a-8a1b-e63a94baf3e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240482050 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.usbdev_tx_rx_disruption.2240482050
Directory /workspace/159.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/16.usbdev_alert_test.1262426135
Short name T2065
Test name
Test status
Simulation time 77905527 ps
CPU time 0.72 seconds
Started Aug 11 07:11:50 PM PDT 24
Finished Aug 11 07:11:51 PM PDT 24
Peak memory 207540 kb
Host smart-f7cc3f3d-7e52-44a2-9569-53c7c6c5a3a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1262426135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1262426135
Directory /workspace/16.usbdev_alert_test/latest


Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.552988064
Short name T230
Test name
Test status
Simulation time 11257465013 ps
CPU time 13.83 seconds
Started Aug 11 07:11:39 PM PDT 24
Finished Aug 11 07:11:53 PM PDT 24
Peak memory 206972 kb
Host smart-36d09461-3c15-4074-ad90-6619171313b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552988064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_disconnect.552988064
Directory /workspace/16.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1902075446
Short name T3030
Test name
Test status
Simulation time 14786641737 ps
CPU time 16.45 seconds
Started Aug 11 07:11:39 PM PDT 24
Finished Aug 11 07:11:55 PM PDT 24
Peak memory 215264 kb
Host smart-b81fbf74-e9d8-46d4-adb3-fe5acc503d97
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902075446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1902075446
Directory /workspace/16.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/16.usbdev_av_buffer.1624400427
Short name T2446
Test name
Test status
Simulation time 145794896 ps
CPU time 0.82 seconds
Started Aug 11 07:11:36 PM PDT 24
Finished Aug 11 07:11:37 PM PDT 24
Peak memory 207548 kb
Host smart-aa652716-037a-46b6-84f8-d370dcc4e2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16244
00427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1624400427
Directory /workspace/16.usbdev_av_buffer/latest


Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1134807958
Short name T1295
Test name
Test status
Simulation time 209152412 ps
CPU time 0.9 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 207520 kb
Host smart-998bab0d-02b7-453d-8cea-36b122b07a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11348
07958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1134807958
Directory /workspace/16.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2774199648
Short name T2419
Test name
Test status
Simulation time 312233710 ps
CPU time 1.21 seconds
Started Aug 11 07:11:38 PM PDT 24
Finished Aug 11 07:11:40 PM PDT 24
Peak memory 207576 kb
Host smart-6b1755eb-aba4-4753-b21a-a3080f4df352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27741
99648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2774199648
Directory /workspace/16.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1413914924
Short name T2194
Test name
Test status
Simulation time 1163931513 ps
CPU time 3.14 seconds
Started Aug 11 07:11:38 PM PDT 24
Finished Aug 11 07:11:41 PM PDT 24
Peak memory 207696 kb
Host smart-ad3900a3-b52f-421c-b899-e7f506b60da8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1413914924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1413914924
Directory /workspace/16.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/16.usbdev_device_address.534824794
Short name T3469
Test name
Test status
Simulation time 13175248654 ps
CPU time 22.4 seconds
Started Aug 11 07:11:42 PM PDT 24
Finished Aug 11 07:12:05 PM PDT 24
Peak memory 207880 kb
Host smart-899135b1-d4e3-4409-8941-b933e44b8670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53482
4794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.534824794
Directory /workspace/16.usbdev_device_address/latest


Test location /workspace/coverage/default/16.usbdev_device_timeout.3453169030
Short name T2915
Test name
Test status
Simulation time 161325518 ps
CPU time 0.88 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 207564 kb
Host smart-f8a70482-7bcf-47c4-b1a4-041016d7a32b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453169030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.3453169030
Directory /workspace/16.usbdev_device_timeout/latest


Test location /workspace/coverage/default/16.usbdev_disable_endpoint.4178509145
Short name T2071
Test name
Test status
Simulation time 650143057 ps
CPU time 1.61 seconds
Started Aug 11 07:11:36 PM PDT 24
Finished Aug 11 07:11:37 PM PDT 24
Peak memory 207516 kb
Host smart-6c738898-d984-409d-8cbf-41db7ecc8d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41785
09145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.4178509145
Directory /workspace/16.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/16.usbdev_disconnected.1834857852
Short name T2899
Test name
Test status
Simulation time 182704426 ps
CPU time 0.84 seconds
Started Aug 11 07:11:42 PM PDT 24
Finished Aug 11 07:11:43 PM PDT 24
Peak memory 207520 kb
Host smart-7e48420f-d15c-4c1a-beea-6b6ac1dbb440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18348
57852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1834857852
Directory /workspace/16.usbdev_disconnected/latest


Test location /workspace/coverage/default/16.usbdev_enable.3648148974
Short name T1388
Test name
Test status
Simulation time 41368116 ps
CPU time 0.7 seconds
Started Aug 11 07:11:36 PM PDT 24
Finished Aug 11 07:11:37 PM PDT 24
Peak memory 207420 kb
Host smart-d68ed0f2-8fc0-4f92-9716-af99c8f83ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36481
48974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3648148974
Directory /workspace/16.usbdev_enable/latest


Test location /workspace/coverage/default/16.usbdev_endpoint_access.1763148559
Short name T3466
Test name
Test status
Simulation time 827326976 ps
CPU time 2.08 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:11:39 PM PDT 24
Peak memory 207648 kb
Host smart-d7ae9dc9-daca-40b3-bf4b-d62abe40cdf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17631
48559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1763148559
Directory /workspace/16.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/16.usbdev_endpoint_types.1979629030
Short name T446
Test name
Test status
Simulation time 361552326 ps
CPU time 1.23 seconds
Started Aug 11 07:11:42 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 207568 kb
Host smart-8fd9b6ea-5295-4ee2-b0da-1409c93ff63b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1979629030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.1979629030
Directory /workspace/16.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/16.usbdev_fifo_rst.213902932
Short name T2822
Test name
Test status
Simulation time 350435071 ps
CPU time 2.83 seconds
Started Aug 11 07:11:42 PM PDT 24
Finished Aug 11 07:11:45 PM PDT 24
Peak memory 207712 kb
Host smart-b16aff09-3adf-448f-9ba8-312721818347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21390
2932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.213902932
Directory /workspace/16.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/16.usbdev_in_iso.1668990046
Short name T1355
Test name
Test status
Simulation time 209521130 ps
CPU time 1.07 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:11:38 PM PDT 24
Peak memory 215916 kb
Host smart-4bb85963-02d2-479e-b446-a404b6342e30
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1668990046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1668990046
Directory /workspace/16.usbdev_in_iso/latest


Test location /workspace/coverage/default/16.usbdev_in_stall.3813821589
Short name T3141
Test name
Test status
Simulation time 164294342 ps
CPU time 0.87 seconds
Started Aug 11 07:11:38 PM PDT 24
Finished Aug 11 07:11:39 PM PDT 24
Peak memory 207492 kb
Host smart-1f25a164-ce93-4110-bb9f-ad39bf3b4e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38138
21589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3813821589
Directory /workspace/16.usbdev_in_stall/latest


Test location /workspace/coverage/default/16.usbdev_in_trans.351154832
Short name T1007
Test name
Test status
Simulation time 198786755 ps
CPU time 0.91 seconds
Started Aug 11 07:11:38 PM PDT 24
Finished Aug 11 07:11:39 PM PDT 24
Peak memory 207476 kb
Host smart-40d6d707-5258-4911-b1c3-6704c1d08872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35115
4832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.351154832
Directory /workspace/16.usbdev_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_iso_retraction.2412788241
Short name T1357
Test name
Test status
Simulation time 9248275959 ps
CPU time 61.93 seconds
Started Aug 11 07:11:37 PM PDT 24
Finished Aug 11 07:12:39 PM PDT 24
Peak memory 207828 kb
Host smart-5af28a3e-3a35-4ec7-b5e6-752afc2f278b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2412788241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.2412788241
Directory /workspace/16.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/16.usbdev_link_in_err.3799381056
Short name T3448
Test name
Test status
Simulation time 235714908 ps
CPU time 1 seconds
Started Aug 11 07:11:35 PM PDT 24
Finished Aug 11 07:11:36 PM PDT 24
Peak memory 207552 kb
Host smart-33baec42-dbc2-46a3-a56a-c251219892f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37993
81056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3799381056
Directory /workspace/16.usbdev_link_in_err/latest


Test location /workspace/coverage/default/16.usbdev_link_resume.1967834811
Short name T1036
Test name
Test status
Simulation time 33105320017 ps
CPU time 48.19 seconds
Started Aug 11 07:11:39 PM PDT 24
Finished Aug 11 07:12:27 PM PDT 24
Peak memory 207772 kb
Host smart-d5d4aff4-e8bf-463f-a845-bd358a41afe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19678
34811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1967834811
Directory /workspace/16.usbdev_link_resume/latest


Test location /workspace/coverage/default/16.usbdev_link_suspend.2490473368
Short name T670
Test name
Test status
Simulation time 8746313536 ps
CPU time 13.9 seconds
Started Aug 11 07:11:44 PM PDT 24
Finished Aug 11 07:11:58 PM PDT 24
Peak memory 207868 kb
Host smart-ea4b3b19-83e7-4799-902b-0f1613ed0cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24904
73368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2490473368
Directory /workspace/16.usbdev_link_suspend/latest


Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.490100803
Short name T2898
Test name
Test status
Simulation time 4170338819 ps
CPU time 41.2 seconds
Started Aug 11 07:11:41 PM PDT 24
Finished Aug 11 07:12:22 PM PDT 24
Peak memory 216044 kb
Host smart-db946b33-7fc7-4ff6-8d44-df7d4143bd61
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=490100803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.490100803
Directory /workspace/16.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1289728261
Short name T3391
Test name
Test status
Simulation time 2983327895 ps
CPU time 23.63 seconds
Started Aug 11 07:11:39 PM PDT 24
Finished Aug 11 07:12:03 PM PDT 24
Peak memory 224248 kb
Host smart-f052f30f-8914-4bb3-ae17-4d0a7f7fb4a3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1289728261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1289728261
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2452297100
Short name T1415
Test name
Test status
Simulation time 240819801 ps
CPU time 0.98 seconds
Started Aug 11 07:11:40 PM PDT 24
Finished Aug 11 07:11:41 PM PDT 24
Peak memory 207588 kb
Host smart-feefcb26-d570-46b2-a76a-1818526fa299
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2452297100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2452297100
Directory /workspace/16.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1464301937
Short name T2655
Test name
Test status
Simulation time 204129012 ps
CPU time 0.95 seconds
Started Aug 11 07:11:40 PM PDT 24
Finished Aug 11 07:11:41 PM PDT 24
Peak memory 207520 kb
Host smart-55571d5c-1b31-420b-935a-de7316a98327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14643
01937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1464301937
Directory /workspace/16.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.2449850176
Short name T1282
Test name
Test status
Simulation time 3350432817 ps
CPU time 33.42 seconds
Started Aug 11 07:11:40 PM PDT 24
Finished Aug 11 07:12:14 PM PDT 24
Peak memory 218276 kb
Host smart-91e11c28-f255-4a13-b803-c0dec333d531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24498
50176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.2449850176
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1502026484
Short name T1386
Test name
Test status
Simulation time 2264744784 ps
CPU time 17.6 seconds
Started Aug 11 07:11:44 PM PDT 24
Finished Aug 11 07:12:02 PM PDT 24
Peak memory 223908 kb
Host smart-28800799-c148-4fcd-8fcb-c8f3e72e4540
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1502026484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1502026484
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.280677027
Short name T2441
Test name
Test status
Simulation time 207283099 ps
CPU time 0.91 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:11:48 PM PDT 24
Peak memory 207516 kb
Host smart-2d03ecb8-cee7-4075-a151-a5a30a1d3d9c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=280677027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.280677027
Directory /workspace/16.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.4092298760
Short name T2190
Test name
Test status
Simulation time 145649099 ps
CPU time 0.87 seconds
Started Aug 11 07:11:44 PM PDT 24
Finished Aug 11 07:11:45 PM PDT 24
Peak memory 207564 kb
Host smart-e444f574-bf2a-4403-a580-395596c07cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
98760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.4092298760
Directory /workspace/16.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_out_iso.1234131310
Short name T2917
Test name
Test status
Simulation time 206030389 ps
CPU time 1 seconds
Started Aug 11 07:11:41 PM PDT 24
Finished Aug 11 07:11:42 PM PDT 24
Peak memory 207544 kb
Host smart-a0b54a62-1b7e-48c6-8dc3-40fa158c64f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12341
31310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1234131310
Directory /workspace/16.usbdev_out_iso/latest


Test location /workspace/coverage/default/16.usbdev_out_stall.1072035934
Short name T579
Test name
Test status
Simulation time 178446618 ps
CPU time 0.9 seconds
Started Aug 11 07:11:43 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 207584 kb
Host smart-0011e9d0-323f-40c7-b4d9-3025d3d8bd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10720
35934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1072035934
Directory /workspace/16.usbdev_out_stall/latest


Test location /workspace/coverage/default/16.usbdev_out_trans_nak.4122318445
Short name T1159
Test name
Test status
Simulation time 181828634 ps
CPU time 0.89 seconds
Started Aug 11 07:11:43 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 207572 kb
Host smart-32d86e8e-3a90-49df-b968-84c125ea5e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41223
18445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.4122318445
Directory /workspace/16.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3540971542
Short name T3255
Test name
Test status
Simulation time 184357195 ps
CPU time 0.92 seconds
Started Aug 11 07:11:43 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 207588 kb
Host smart-8ce6d63b-d72a-48a9-98bc-7e6dc0b1d3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35409
71542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3540971542
Directory /workspace/16.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3181491761
Short name T2444
Test name
Test status
Simulation time 240847959 ps
CPU time 1.07 seconds
Started Aug 11 07:11:41 PM PDT 24
Finished Aug 11 07:11:42 PM PDT 24
Peak memory 207540 kb
Host smart-3a0e20d8-e44a-4585-9d40-fe2051086757
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3181491761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3181491761
Directory /workspace/16.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1730979703
Short name T2630
Test name
Test status
Simulation time 144613354 ps
CPU time 0.86 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:11:48 PM PDT 24
Peak memory 207484 kb
Host smart-a1d64342-cfe3-45e5-886c-559ce153d4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17309
79703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1730979703
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2723907325
Short name T3308
Test name
Test status
Simulation time 86800045 ps
CPU time 0.76 seconds
Started Aug 11 07:11:42 PM PDT 24
Finished Aug 11 07:11:43 PM PDT 24
Peak memory 207508 kb
Host smart-dc15d51f-0069-4d34-a098-052403cef40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27239
07325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2723907325
Directory /workspace/16.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2818663820
Short name T3242
Test name
Test status
Simulation time 21025034335 ps
CPU time 56.01 seconds
Started Aug 11 07:11:48 PM PDT 24
Finished Aug 11 07:12:44 PM PDT 24
Peak memory 216060 kb
Host smart-138dd1f6-1966-4cb5-bd93-e0e0bdd93180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28186
63820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2818663820
Directory /workspace/16.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/16.usbdev_pkt_received.4051215993
Short name T2159
Test name
Test status
Simulation time 177734594 ps
CPU time 0.93 seconds
Started Aug 11 07:11:43 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 207572 kb
Host smart-be764c85-6519-4607-9583-054b25eb58e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40512
15993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.4051215993
Directory /workspace/16.usbdev_pkt_received/latest


Test location /workspace/coverage/default/16.usbdev_pkt_sent.593177929
Short name T2722
Test name
Test status
Simulation time 207181454 ps
CPU time 0.92 seconds
Started Aug 11 07:11:41 PM PDT 24
Finished Aug 11 07:11:42 PM PDT 24
Peak memory 207452 kb
Host smart-27028402-366d-4b73-9e1d-9927416208c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59317
7929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.593177929
Directory /workspace/16.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.2153867721
Short name T3542
Test name
Test status
Simulation time 228622973 ps
CPU time 0.96 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:11:48 PM PDT 24
Peak memory 207520 kb
Host smart-5f49bd45-7a98-40a9-bf41-11eaf2a00fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21538
67721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.2153867721
Directory /workspace/16.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.441707223
Short name T1793
Test name
Test status
Simulation time 239606144 ps
CPU time 0.98 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:11:48 PM PDT 24
Peak memory 207568 kb
Host smart-bbb9201b-db4e-4e67-98de-3801e12dcefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44170
7223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.441707223
Directory /workspace/16.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_resume_link_active.3910100230
Short name T1908
Test name
Test status
Simulation time 20203122547 ps
CPU time 27.94 seconds
Started Aug 11 07:11:40 PM PDT 24
Finished Aug 11 07:12:08 PM PDT 24
Peak memory 207568 kb
Host smart-8eea2127-f8d3-4855-9536-d7e0ffc21681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39101
00230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.3910100230
Directory /workspace/16.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1838119065
Short name T930
Test name
Test status
Simulation time 193401827 ps
CPU time 0.84 seconds
Started Aug 11 07:11:44 PM PDT 24
Finished Aug 11 07:11:45 PM PDT 24
Peak memory 207540 kb
Host smart-36d5b50f-48a0-4b5d-ac27-bcc108e678d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18381
19065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1838119065
Directory /workspace/16.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/16.usbdev_rx_full.1124768886
Short name T2985
Test name
Test status
Simulation time 265585051 ps
CPU time 1.11 seconds
Started Aug 11 07:11:44 PM PDT 24
Finished Aug 11 07:11:45 PM PDT 24
Peak memory 207572 kb
Host smart-e8938e68-7324-4047-8575-11e14373ef75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11247
68886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.1124768886
Directory /workspace/16.usbdev_rx_full/latest


Test location /workspace/coverage/default/16.usbdev_setup_stage.1536808417
Short name T3605
Test name
Test status
Simulation time 184047856 ps
CPU time 0.85 seconds
Started Aug 11 07:11:41 PM PDT 24
Finished Aug 11 07:11:41 PM PDT 24
Peak memory 207544 kb
Host smart-b2d2c490-19a0-4c9a-a7b6-48fda18b877a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15368
08417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1536808417
Directory /workspace/16.usbdev_setup_stage/latest


Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.964609631
Short name T3056
Test name
Test status
Simulation time 221847842 ps
CPU time 0.92 seconds
Started Aug 11 07:11:43 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 207556 kb
Host smart-0d5e7ae1-116a-4fd3-aaeb-caa5be91ca84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96460
9631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.964609631
Directory /workspace/16.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/16.usbdev_smoke.1421248564
Short name T729
Test name
Test status
Simulation time 266999850 ps
CPU time 1.19 seconds
Started Aug 11 07:11:44 PM PDT 24
Finished Aug 11 07:11:46 PM PDT 24
Peak memory 207552 kb
Host smart-4c86f90b-7b69-4131-b2db-25be2a878112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14212
48564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1421248564
Directory /workspace/16.usbdev_smoke/latest


Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.3722963453
Short name T2498
Test name
Test status
Simulation time 1569642780 ps
CPU time 14.77 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:12:02 PM PDT 24
Peak memory 217760 kb
Host smart-7882794c-7c45-442f-99b0-a84480d5de17
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3722963453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.3722963453
Directory /workspace/16.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.205866438
Short name T3061
Test name
Test status
Simulation time 188931943 ps
CPU time 0.9 seconds
Started Aug 11 07:11:41 PM PDT 24
Finished Aug 11 07:11:42 PM PDT 24
Peak memory 207492 kb
Host smart-7e0afb28-daaf-4b8e-b36d-87b946c284cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20586
6438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.205866438
Directory /workspace/16.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/16.usbdev_stall_trans.2357886896
Short name T1528
Test name
Test status
Simulation time 176251267 ps
CPU time 0.91 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:11:48 PM PDT 24
Peak memory 207592 kb
Host smart-ae71dd6e-ed40-4e29-8698-00da530c6f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23578
86896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2357886896
Directory /workspace/16.usbdev_stall_trans/latest


Test location /workspace/coverage/default/16.usbdev_stream_len_max.1534062596
Short name T3026
Test name
Test status
Simulation time 851288749 ps
CPU time 2.22 seconds
Started Aug 11 07:11:45 PM PDT 24
Finished Aug 11 07:11:47 PM PDT 24
Peak memory 207760 kb
Host smart-fae2957a-0cfb-4b44-8eb5-dc4323b25a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15340
62596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.1534062596
Directory /workspace/16.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/16.usbdev_streaming_out.1048797632
Short name T2671
Test name
Test status
Simulation time 3203114332 ps
CPU time 89.32 seconds
Started Aug 11 07:11:39 PM PDT 24
Finished Aug 11 07:13:08 PM PDT 24
Peak memory 216088 kb
Host smart-58fb2d15-b633-4d17-b427-cfa03254ad6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10487
97632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1048797632
Directory /workspace/16.usbdev_streaming_out/latest


Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.3972760371
Short name T2659
Test name
Test status
Simulation time 1089243538 ps
CPU time 9.5 seconds
Started Aug 11 07:11:35 PM PDT 24
Finished Aug 11 07:11:45 PM PDT 24
Peak memory 207644 kb
Host smart-e0e4639e-3ec3-4c15-8db6-3565f5fc434f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972760371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.3972760371
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/16.usbdev_tx_rx_disruption.3296930634
Short name T1544
Test name
Test status
Simulation time 637553456 ps
CPU time 1.71 seconds
Started Aug 11 07:11:44 PM PDT 24
Finished Aug 11 07:11:46 PM PDT 24
Peak memory 207296 kb
Host smart-2a34cb0e-6f9b-4c3c-a0cb-a52510267de1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296930634 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.usbdev_tx_rx_disruption.3296930634
Directory /workspace/16.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/160.usbdev_endpoint_types.2412366373
Short name T3239
Test name
Test status
Simulation time 242471439 ps
CPU time 0.99 seconds
Started Aug 11 07:17:13 PM PDT 24
Finished Aug 11 07:17:14 PM PDT 24
Peak memory 207520 kb
Host smart-accd4307-bccf-4aff-8f12-7578b242d841
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2412366373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.2412366373
Directory /workspace/160.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/160.usbdev_tx_rx_disruption.3060854137
Short name T902
Test name
Test status
Simulation time 647861741 ps
CPU time 1.71 seconds
Started Aug 11 07:17:28 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207576 kb
Host smart-151d5a6d-c0be-4739-8bf1-bd5fe25fe7e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060854137 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.usbdev_tx_rx_disruption.3060854137
Directory /workspace/160.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/161.usbdev_endpoint_types.1726216494
Short name T512
Test name
Test status
Simulation time 349177989 ps
CPU time 1.18 seconds
Started Aug 11 07:17:26 PM PDT 24
Finished Aug 11 07:17:27 PM PDT 24
Peak memory 207560 kb
Host smart-e14dde3d-9a5f-4fd8-a17f-2ac3ea1e78ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1726216494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.1726216494
Directory /workspace/161.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/161.usbdev_tx_rx_disruption.1425751381
Short name T1721
Test name
Test status
Simulation time 496341889 ps
CPU time 1.52 seconds
Started Aug 11 07:17:11 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 207608 kb
Host smart-e184c570-c872-4a26-8ee0-64dcf6d1307c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425751381 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 161.usbdev_tx_rx_disruption.1425751381
Directory /workspace/161.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/162.usbdev_tx_rx_disruption.2390386465
Short name T2754
Test name
Test status
Simulation time 513218301 ps
CPU time 1.62 seconds
Started Aug 11 07:17:12 PM PDT 24
Finished Aug 11 07:17:14 PM PDT 24
Peak memory 207484 kb
Host smart-b4d54773-b189-4bd5-b4fb-ea9708c0c323
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390386465 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.usbdev_tx_rx_disruption.2390386465
Directory /workspace/162.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/163.usbdev_endpoint_types.3895235179
Short name T2986
Test name
Test status
Simulation time 409639368 ps
CPU time 1.3 seconds
Started Aug 11 07:17:11 PM PDT 24
Finished Aug 11 07:17:13 PM PDT 24
Peak memory 207456 kb
Host smart-5202183a-5357-48a6-94e6-d532aa3012e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3895235179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.3895235179
Directory /workspace/163.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/163.usbdev_tx_rx_disruption.1768002943
Short name T2684
Test name
Test status
Simulation time 524426749 ps
CPU time 1.52 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 207564 kb
Host smart-d10f5d48-f35f-4933-968d-5af3a2f68ebf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768002943 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.usbdev_tx_rx_disruption.1768002943
Directory /workspace/163.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/164.usbdev_endpoint_types.2212518531
Short name T534
Test name
Test status
Simulation time 248179698 ps
CPU time 1.07 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207540 kb
Host smart-4ab15449-e62a-4a09-be10-b520e824a630
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2212518531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.2212518531
Directory /workspace/164.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/164.usbdev_tx_rx_disruption.2520879483
Short name T1702
Test name
Test status
Simulation time 607174513 ps
CPU time 1.55 seconds
Started Aug 11 07:17:23 PM PDT 24
Finished Aug 11 07:17:24 PM PDT 24
Peak memory 207512 kb
Host smart-3e57beae-4b46-456e-a885-de6c3bd16b63
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520879483 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.usbdev_tx_rx_disruption.2520879483
Directory /workspace/164.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/165.usbdev_endpoint_types.423136415
Short name T407
Test name
Test status
Simulation time 289730851 ps
CPU time 1.2 seconds
Started Aug 11 07:17:13 PM PDT 24
Finished Aug 11 07:17:15 PM PDT 24
Peak memory 207512 kb
Host smart-b15ba90b-d594-4aa6-bb81-c328c9de6924
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=423136415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.423136415
Directory /workspace/165.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/165.usbdev_tx_rx_disruption.1673505733
Short name T2685
Test name
Test status
Simulation time 534292643 ps
CPU time 1.68 seconds
Started Aug 11 07:17:26 PM PDT 24
Finished Aug 11 07:17:28 PM PDT 24
Peak memory 207500 kb
Host smart-6487638b-f0ef-413b-aa40-da0b26459cfb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673505733 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.usbdev_tx_rx_disruption.1673505733
Directory /workspace/165.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/166.usbdev_endpoint_types.1841425450
Short name T507
Test name
Test status
Simulation time 413284985 ps
CPU time 1.36 seconds
Started Aug 11 07:17:22 PM PDT 24
Finished Aug 11 07:17:23 PM PDT 24
Peak memory 207560 kb
Host smart-d9b30ba4-b831-49e7-a810-3d69a1859819
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1841425450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.1841425450
Directory /workspace/166.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/166.usbdev_tx_rx_disruption.648677906
Short name T1248
Test name
Test status
Simulation time 510549127 ps
CPU time 1.55 seconds
Started Aug 11 07:17:13 PM PDT 24
Finished Aug 11 07:17:15 PM PDT 24
Peak memory 207528 kb
Host smart-a1fc624e-7cca-4744-b10f-741d8b8a6d19
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648677906 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 166.usbdev_tx_rx_disruption.648677906
Directory /workspace/166.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/167.usbdev_endpoint_types.1065253951
Short name T437
Test name
Test status
Simulation time 683636740 ps
CPU time 1.63 seconds
Started Aug 11 07:17:14 PM PDT 24
Finished Aug 11 07:17:16 PM PDT 24
Peak memory 207452 kb
Host smart-ffbc17ef-417b-44ba-8097-f485f43a07d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1065253951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.1065253951
Directory /workspace/167.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/167.usbdev_tx_rx_disruption.3558546772
Short name T172
Test name
Test status
Simulation time 414238037 ps
CPU time 1.37 seconds
Started Aug 11 07:17:19 PM PDT 24
Finished Aug 11 07:17:20 PM PDT 24
Peak memory 207496 kb
Host smart-d52cad46-6365-40bf-8e1e-5a0ce49a0137
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558546772 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.usbdev_tx_rx_disruption.3558546772
Directory /workspace/167.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/168.usbdev_endpoint_types.3766984802
Short name T2686
Test name
Test status
Simulation time 253361907 ps
CPU time 1.01 seconds
Started Aug 11 07:17:13 PM PDT 24
Finished Aug 11 07:17:14 PM PDT 24
Peak memory 207536 kb
Host smart-c8334eb4-8e22-46f7-952a-cc9f5a4d270c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3766984802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.3766984802
Directory /workspace/168.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/168.usbdev_tx_rx_disruption.3811912047
Short name T662
Test name
Test status
Simulation time 609246023 ps
CPU time 1.61 seconds
Started Aug 11 07:17:29 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 207516 kb
Host smart-cb8cf5ee-450c-46cb-ae5c-76702ad9aa02
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811912047 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.usbdev_tx_rx_disruption.3811912047
Directory /workspace/168.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/169.usbdev_endpoint_types.2989649167
Short name T536
Test name
Test status
Simulation time 323304754 ps
CPU time 1.2 seconds
Started Aug 11 07:17:11 PM PDT 24
Finished Aug 11 07:17:13 PM PDT 24
Peak memory 207404 kb
Host smart-dc0e35ae-35bc-47c2-9f4f-b44b67f20714
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2989649167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.2989649167
Directory /workspace/169.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/169.usbdev_tx_rx_disruption.1841500462
Short name T3628
Test name
Test status
Simulation time 684099600 ps
CPU time 1.89 seconds
Started Aug 11 07:17:16 PM PDT 24
Finished Aug 11 07:17:18 PM PDT 24
Peak memory 207456 kb
Host smart-6b85cba5-5714-4066-959f-af2521a02e84
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841500462 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 169.usbdev_tx_rx_disruption.1841500462
Directory /workspace/169.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/17.usbdev_alert_test.3019925380
Short name T2200
Test name
Test status
Simulation time 37805419 ps
CPU time 0.65 seconds
Started Aug 11 07:11:54 PM PDT 24
Finished Aug 11 07:11:55 PM PDT 24
Peak memory 207512 kb
Host smart-85eb8e05-ee6a-40cb-808d-cb505f35f6bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3019925380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3019925380
Directory /workspace/17.usbdev_alert_test/latest


Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1909837575
Short name T953
Test name
Test status
Simulation time 4784618597 ps
CPU time 8.06 seconds
Started Aug 11 07:11:45 PM PDT 24
Finished Aug 11 07:11:54 PM PDT 24
Peak memory 215968 kb
Host smart-7d82e5e5-96c2-43d9-b636-c9adbaa6cc7e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909837575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.1909837575
Directory /workspace/17.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2657245146
Short name T2767
Test name
Test status
Simulation time 20723422830 ps
CPU time 23.9 seconds
Started Aug 11 07:11:46 PM PDT 24
Finished Aug 11 07:12:10 PM PDT 24
Peak memory 207692 kb
Host smart-768aef8d-d28e-43cf-933a-3428a3bd6945
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657245146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2657245146
Directory /workspace/17.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2989178745
Short name T2818
Test name
Test status
Simulation time 30123804840 ps
CPU time 45.65 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:12:33 PM PDT 24
Peak memory 207872 kb
Host smart-22b1f65d-16b3-461d-b4f6-0c9f2f9c2949
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989178745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.2989178745
Directory /workspace/17.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/17.usbdev_av_buffer.3514930820
Short name T1828
Test name
Test status
Simulation time 222202860 ps
CPU time 0.94 seconds
Started Aug 11 07:11:48 PM PDT 24
Finished Aug 11 07:11:49 PM PDT 24
Peak memory 207556 kb
Host smart-76dc66ef-511a-4d53-b339-610fb08ca3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35149
30820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3514930820
Directory /workspace/17.usbdev_av_buffer/latest


Test location /workspace/coverage/default/17.usbdev_bitstuff_err.4213160247
Short name T1815
Test name
Test status
Simulation time 151620845 ps
CPU time 0.87 seconds
Started Aug 11 07:11:51 PM PDT 24
Finished Aug 11 07:11:52 PM PDT 24
Peak memory 206780 kb
Host smart-e45a327a-1f46-4d47-abe7-1bd64a4445a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42131
60247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.4213160247
Directory /workspace/17.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.925283398
Short name T1108
Test name
Test status
Simulation time 365634806 ps
CPU time 1.43 seconds
Started Aug 11 07:11:46 PM PDT 24
Finished Aug 11 07:11:48 PM PDT 24
Peak memory 207552 kb
Host smart-704442cd-6f72-4f0b-9fd5-effddb0bd3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92528
3398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.925283398
Directory /workspace/17.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/17.usbdev_device_address.748777657
Short name T1498
Test name
Test status
Simulation time 18630827485 ps
CPU time 32.11 seconds
Started Aug 11 07:11:45 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207772 kb
Host smart-bfe0917f-a221-4f7d-9e61-cf6586e3cf98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74877
7657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.748777657
Directory /workspace/17.usbdev_device_address/latest


Test location /workspace/coverage/default/17.usbdev_device_timeout.2571093354
Short name T671
Test name
Test status
Simulation time 442830156 ps
CPU time 8.41 seconds
Started Aug 11 07:11:48 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207700 kb
Host smart-c344b920-5261-4009-ab9e-bb81e69f23ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571093354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.2571093354
Directory /workspace/17.usbdev_device_timeout/latest


Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1522324769
Short name T951
Test name
Test status
Simulation time 337049562 ps
CPU time 1.26 seconds
Started Aug 11 07:11:48 PM PDT 24
Finished Aug 11 07:11:49 PM PDT 24
Peak memory 207452 kb
Host smart-b744d7dd-3e09-46fb-8635-666162db8b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15223
24769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1522324769
Directory /workspace/17.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/17.usbdev_disconnected.2942066480
Short name T1753
Test name
Test status
Simulation time 169345831 ps
CPU time 0.84 seconds
Started Aug 11 07:11:52 PM PDT 24
Finished Aug 11 07:11:53 PM PDT 24
Peak memory 207516 kb
Host smart-e6830611-627a-4bd6-b83c-7cde3956f646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29420
66480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2942066480
Directory /workspace/17.usbdev_disconnected/latest


Test location /workspace/coverage/default/17.usbdev_enable.3176982028
Short name T1405
Test name
Test status
Simulation time 68816178 ps
CPU time 0.73 seconds
Started Aug 11 07:11:48 PM PDT 24
Finished Aug 11 07:11:49 PM PDT 24
Peak memory 207468 kb
Host smart-949baace-cfb4-4ad9-8325-cefc61ed44c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769
82028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3176982028
Directory /workspace/17.usbdev_enable/latest


Test location /workspace/coverage/default/17.usbdev_endpoint_access.1188384686
Short name T1609
Test name
Test status
Simulation time 890627099 ps
CPU time 2.4 seconds
Started Aug 11 07:11:50 PM PDT 24
Finished Aug 11 07:11:53 PM PDT 24
Peak memory 207764 kb
Host smart-aa7ff05a-c431-4b45-bf7b-e85a72db9bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11883
84686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1188384686
Directory /workspace/17.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/17.usbdev_endpoint_types.2251634102
Short name T2350
Test name
Test status
Simulation time 163288898 ps
CPU time 0.87 seconds
Started Aug 11 07:11:45 PM PDT 24
Finished Aug 11 07:11:46 PM PDT 24
Peak memory 207508 kb
Host smart-023e3c08-79f7-4aac-9e80-eae3a7d82987
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2251634102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.2251634102
Directory /workspace/17.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/17.usbdev_fifo_rst.1932273725
Short name T2770
Test name
Test status
Simulation time 166327645 ps
CPU time 1.5 seconds
Started Aug 11 07:11:48 PM PDT 24
Finished Aug 11 07:11:50 PM PDT 24
Peak memory 207760 kb
Host smart-f773cff4-6c14-4879-bb50-eb599173efdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19322
73725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1932273725
Directory /workspace/17.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/17.usbdev_in_iso.1654128787
Short name T2530
Test name
Test status
Simulation time 224883457 ps
CPU time 1.18 seconds
Started Aug 11 07:11:49 PM PDT 24
Finished Aug 11 07:11:51 PM PDT 24
Peak memory 215948 kb
Host smart-739a5993-fc0e-4b2d-966a-e443c42d1fdc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1654128787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1654128787
Directory /workspace/17.usbdev_in_iso/latest


Test location /workspace/coverage/default/17.usbdev_in_stall.2277416873
Short name T1275
Test name
Test status
Simulation time 139812231 ps
CPU time 0.83 seconds
Started Aug 11 07:11:50 PM PDT 24
Finished Aug 11 07:11:52 PM PDT 24
Peak memory 207460 kb
Host smart-c7451827-bc59-444b-bdc1-d21614905a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22774
16873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2277416873
Directory /workspace/17.usbdev_in_stall/latest


Test location /workspace/coverage/default/17.usbdev_in_trans.2826020707
Short name T3091
Test name
Test status
Simulation time 180509727 ps
CPU time 0.93 seconds
Started Aug 11 07:11:52 PM PDT 24
Finished Aug 11 07:11:53 PM PDT 24
Peak memory 207548 kb
Host smart-2ee55d98-66e9-4371-891e-0a8219aab150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28260
20707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2826020707
Directory /workspace/17.usbdev_in_trans/latest


Test location /workspace/coverage/default/17.usbdev_invalid_sync.3969518293
Short name T2213
Test name
Test status
Simulation time 3954235483 ps
CPU time 117.06 seconds
Started Aug 11 07:11:49 PM PDT 24
Finished Aug 11 07:13:46 PM PDT 24
Peak memory 217880 kb
Host smart-cad1cd5d-b93f-4363-bf16-d725cdb4ebc3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3969518293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3969518293
Directory /workspace/17.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/17.usbdev_iso_retraction.3840944963
Short name T2335
Test name
Test status
Simulation time 3629607943 ps
CPU time 25.56 seconds
Started Aug 11 07:11:50 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207880 kb
Host smart-daf5dd39-0ac7-4a29-a11c-76730b655949
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3840944963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.3840944963
Directory /workspace/17.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/17.usbdev_link_in_err.1484119844
Short name T2761
Test name
Test status
Simulation time 151320054 ps
CPU time 0.85 seconds
Started Aug 11 07:11:56 PM PDT 24
Finished Aug 11 07:11:57 PM PDT 24
Peak memory 207456 kb
Host smart-00d66fb0-06ef-4339-a2d0-7d6d43120bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14841
19844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1484119844
Directory /workspace/17.usbdev_link_in_err/latest


Test location /workspace/coverage/default/17.usbdev_link_resume.830774982
Short name T1956
Test name
Test status
Simulation time 27753768848 ps
CPU time 42.35 seconds
Started Aug 11 07:11:51 PM PDT 24
Finished Aug 11 07:12:34 PM PDT 24
Peak memory 207776 kb
Host smart-454d45dc-b634-4175-a94b-8207f16d744a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83077
4982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.830774982
Directory /workspace/17.usbdev_link_resume/latest


Test location /workspace/coverage/default/17.usbdev_link_suspend.3414912229
Short name T2894
Test name
Test status
Simulation time 5712938365 ps
CPU time 7.49 seconds
Started Aug 11 07:11:46 PM PDT 24
Finished Aug 11 07:11:54 PM PDT 24
Peak memory 216068 kb
Host smart-9ae763f8-a406-4956-aa80-e91fed4e75a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34149
12229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3414912229
Directory /workspace/17.usbdev_link_suspend/latest


Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.4266293077
Short name T2958
Test name
Test status
Simulation time 3528798631 ps
CPU time 29.48 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 216096 kb
Host smart-dfef4a6b-b464-4370-bd8c-02acf49549c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4266293077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.4266293077
Directory /workspace/17.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1187129965
Short name T2222
Test name
Test status
Simulation time 3232223561 ps
CPU time 26.47 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 217648 kb
Host smart-85dbdf53-2b72-4f35-a7d3-679927ac865c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1187129965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1187129965
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1163377153
Short name T2773
Test name
Test status
Simulation time 290695901 ps
CPU time 1.05 seconds
Started Aug 11 07:11:51 PM PDT 24
Finished Aug 11 07:11:52 PM PDT 24
Peak memory 206820 kb
Host smart-a7de2016-5944-491c-9bd4-1c96db9f619b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1163377153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1163377153
Directory /workspace/17.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1087102582
Short name T1665
Test name
Test status
Simulation time 191773799 ps
CPU time 0.93 seconds
Started Aug 11 07:11:48 PM PDT 24
Finished Aug 11 07:11:49 PM PDT 24
Peak memory 207496 kb
Host smart-2d6dac5d-b3cc-4487-ab96-a77700a7471d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10871
02582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1087102582
Directory /workspace/17.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.3577094092
Short name T1772
Test name
Test status
Simulation time 2351678879 ps
CPU time 17.27 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:12:04 PM PDT 24
Peak memory 224264 kb
Host smart-cd49beb4-26e6-4da3-b082-d46b93193562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35770
94092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.3577094092
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3515963269
Short name T2387
Test name
Test status
Simulation time 2970565370 ps
CPU time 84.27 seconds
Started Aug 11 07:11:50 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 216020 kb
Host smart-c3106eaa-fc6c-43a6-b73c-6cace4e33eb7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3515963269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3515963269
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.2259634737
Short name T1935
Test name
Test status
Simulation time 169568774 ps
CPU time 0.87 seconds
Started Aug 11 07:11:52 PM PDT 24
Finished Aug 11 07:11:53 PM PDT 24
Peak memory 207568 kb
Host smart-7f7ab95c-4340-4baa-8dc9-1cc484ab0230
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2259634737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.2259634737
Directory /workspace/17.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.86533715
Short name T3538
Test name
Test status
Simulation time 162214500 ps
CPU time 0.95 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:11:54 PM PDT 24
Peak memory 207556 kb
Host smart-7591dd11-2b4b-4e76-937b-a61d2970aaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86533
715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.86533715
Directory /workspace/17.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_nak_trans.4088563613
Short name T135
Test name
Test status
Simulation time 173336938 ps
CPU time 0.87 seconds
Started Aug 11 07:11:46 PM PDT 24
Finished Aug 11 07:11:47 PM PDT 24
Peak memory 207520 kb
Host smart-3320694a-27f4-4e00-a6e9-a62ae89c75a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40885
63613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4088563613
Directory /workspace/17.usbdev_nak_trans/latest


Test location /workspace/coverage/default/17.usbdev_out_iso.2524542615
Short name T321
Test name
Test status
Simulation time 154260155 ps
CPU time 0.93 seconds
Started Aug 11 07:11:49 PM PDT 24
Finished Aug 11 07:11:50 PM PDT 24
Peak memory 207480 kb
Host smart-9d315c7f-598e-4820-b530-98bcf9b43ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245
42615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2524542615
Directory /workspace/17.usbdev_out_iso/latest


Test location /workspace/coverage/default/17.usbdev_out_stall.1694635130
Short name T1997
Test name
Test status
Simulation time 157123955 ps
CPU time 0.88 seconds
Started Aug 11 07:11:49 PM PDT 24
Finished Aug 11 07:11:50 PM PDT 24
Peak memory 207496 kb
Host smart-64e193fd-8b33-442a-9868-1dc26a1ae376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16946
35130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1694635130
Directory /workspace/17.usbdev_out_stall/latest


Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1642106934
Short name T2097
Test name
Test status
Simulation time 171378847 ps
CPU time 0.89 seconds
Started Aug 11 07:11:47 PM PDT 24
Finished Aug 11 07:11:48 PM PDT 24
Peak memory 207504 kb
Host smart-e2968ee9-ccb4-4a29-8343-ccaebba279ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16421
06934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1642106934
Directory /workspace/17.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1031530161
Short name T2644
Test name
Test status
Simulation time 152162179 ps
CPU time 0.89 seconds
Started Aug 11 07:11:45 PM PDT 24
Finished Aug 11 07:11:46 PM PDT 24
Peak memory 207596 kb
Host smart-03d6554a-f864-4710-9874-5c941f267dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10315
30161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1031530161
Directory /workspace/17.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.2570855852
Short name T1863
Test name
Test status
Simulation time 211370549 ps
CPU time 1 seconds
Started Aug 11 07:11:49 PM PDT 24
Finished Aug 11 07:11:50 PM PDT 24
Peak memory 207500 kb
Host smart-587c51e7-4a56-49ac-b1fa-f5e229164cca
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2570855852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.2570855852
Directory /workspace/17.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.572534938
Short name T1547
Test name
Test status
Simulation time 192162446 ps
CPU time 0.91 seconds
Started Aug 11 07:11:54 PM PDT 24
Finished Aug 11 07:11:55 PM PDT 24
Peak memory 207552 kb
Host smart-17ec500b-9c15-4b21-818a-171def2749e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57253
4938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.572534938
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3861239134
Short name T2340
Test name
Test status
Simulation time 43863356 ps
CPU time 0.69 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:11:53 PM PDT 24
Peak memory 207472 kb
Host smart-9eb5ff18-48b3-43fc-bba0-462e5256dcd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38612
39134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3861239134
Directory /workspace/17.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2760948733
Short name T2561
Test name
Test status
Simulation time 12859398766 ps
CPU time 33.65 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:12:27 PM PDT 24
Peak memory 216040 kb
Host smart-4509745d-3f4a-4f7d-a421-343a636d10f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27609
48733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2760948733
Directory /workspace/17.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/17.usbdev_pkt_received.3451714818
Short name T3401
Test name
Test status
Simulation time 153783198 ps
CPU time 0.92 seconds
Started Aug 11 07:11:54 PM PDT 24
Finished Aug 11 07:11:55 PM PDT 24
Peak memory 207504 kb
Host smart-d0d5b1e2-f25c-4db4-91d2-1721637378e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34517
14818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3451714818
Directory /workspace/17.usbdev_pkt_received/latest


Test location /workspace/coverage/default/17.usbdev_pkt_sent.339981564
Short name T3467
Test name
Test status
Simulation time 202942586 ps
CPU time 0.98 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:11:57 PM PDT 24
Peak memory 207544 kb
Host smart-81854872-25e9-4f22-a434-fbcf1db4e97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33998
1564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.339981564
Directory /workspace/17.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2631537222
Short name T3225
Test name
Test status
Simulation time 169785572 ps
CPU time 0.9 seconds
Started Aug 11 07:12:01 PM PDT 24
Finished Aug 11 07:12:02 PM PDT 24
Peak memory 207760 kb
Host smart-4970a590-8b23-4f93-9808-d84b3dde0fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26315
37222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2631537222
Directory /workspace/17.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3592823412
Short name T1745
Test name
Test status
Simulation time 168435960 ps
CPU time 0.89 seconds
Started Aug 11 07:12:00 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 207360 kb
Host smart-1311b064-3e7d-4d0a-a218-7d3937959f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35928
23412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3592823412
Directory /workspace/17.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_resume_link_active.2218794164
Short name T3011
Test name
Test status
Simulation time 20228198413 ps
CPU time 22.4 seconds
Started Aug 11 07:11:56 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207624 kb
Host smart-80b969ae-609c-46c3-b9ae-b0bcaea3c896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22187
94164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.2218794164
Directory /workspace/17.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1449543912
Short name T2341
Test name
Test status
Simulation time 148869119 ps
CPU time 0.87 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:11:54 PM PDT 24
Peak memory 207492 kb
Host smart-531db632-f27a-407b-902c-677c4324c1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14495
43912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1449543912
Directory /workspace/17.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/17.usbdev_rx_full.2911751598
Short name T1857
Test name
Test status
Simulation time 256887328 ps
CPU time 1.12 seconds
Started Aug 11 07:11:57 PM PDT 24
Finished Aug 11 07:11:58 PM PDT 24
Peak memory 207440 kb
Host smart-c6bb596d-4c00-4e73-97c8-d78e82a685aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29117
51598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.2911751598
Directory /workspace/17.usbdev_rx_full/latest


Test location /workspace/coverage/default/17.usbdev_setup_stage.1779830436
Short name T2782
Test name
Test status
Simulation time 149682485 ps
CPU time 0.86 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207472 kb
Host smart-59636b33-c381-461a-b7a2-740d15e7a48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17798
30436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1779830436
Directory /workspace/17.usbdev_setup_stage/latest


Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1419563013
Short name T1979
Test name
Test status
Simulation time 155967736 ps
CPU time 0.84 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207552 kb
Host smart-95bcc215-cc44-45ed-a140-ad14a36805d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14195
63013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1419563013
Directory /workspace/17.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/17.usbdev_smoke.4289909937
Short name T1241
Test name
Test status
Simulation time 206256910 ps
CPU time 1.03 seconds
Started Aug 11 07:11:58 PM PDT 24
Finished Aug 11 07:11:59 PM PDT 24
Peak memory 207516 kb
Host smart-476f8688-bcdf-4781-95d3-480830ac8898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42899
09937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.4289909937
Directory /workspace/17.usbdev_smoke/latest


Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2978468264
Short name T910
Test name
Test status
Simulation time 2478195379 ps
CPU time 72.95 seconds
Started Aug 11 07:11:58 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 224228 kb
Host smart-dc12e67d-dbb3-4ef0-9644-52c1bc869f19
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2978468264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2978468264
Directory /workspace/17.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2813739420
Short name T2297
Test name
Test status
Simulation time 170641772 ps
CPU time 0.9 seconds
Started Aug 11 07:12:02 PM PDT 24
Finished Aug 11 07:12:03 PM PDT 24
Peak memory 207760 kb
Host smart-314f0db2-05f1-4250-89cc-4763820c8110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28137
39420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2813739420
Directory /workspace/17.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/17.usbdev_stall_trans.885730328
Short name T1584
Test name
Test status
Simulation time 193274794 ps
CPU time 0.92 seconds
Started Aug 11 07:12:00 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 207552 kb
Host smart-304c047b-3b5a-4fb7-95a6-4a5e18661201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88573
0328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.885730328
Directory /workspace/17.usbdev_stall_trans/latest


Test location /workspace/coverage/default/17.usbdev_stream_len_max.3972822459
Short name T1002
Test name
Test status
Simulation time 760620480 ps
CPU time 2.03 seconds
Started Aug 11 07:11:54 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207524 kb
Host smart-e612ed24-2769-488a-8048-6d944d695fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39728
22459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3972822459
Directory /workspace/17.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/17.usbdev_streaming_out.724725200
Short name T762
Test name
Test status
Simulation time 2764399458 ps
CPU time 76.46 seconds
Started Aug 11 07:11:56 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 217500 kb
Host smart-92de11b3-4547-4b9a-9ea8-ccfb1b0c5dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72472
5200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.724725200
Directory /workspace/17.usbdev_streaming_out/latest


Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.269487364
Short name T790
Test name
Test status
Simulation time 549492073 ps
CPU time 12.54 seconds
Started Aug 11 07:11:48 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 207768 kb
Host smart-5bb6bca9-8428-43af-b43b-5139f1c9f96a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269487364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_host
_handshake.269487364
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/17.usbdev_tx_rx_disruption.321046469
Short name T1119
Test name
Test status
Simulation time 544684838 ps
CPU time 1.81 seconds
Started Aug 11 07:12:02 PM PDT 24
Finished Aug 11 07:12:04 PM PDT 24
Peak memory 207540 kb
Host smart-0783a677-d4b9-498d-a279-75278d795e48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321046469 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.usbdev_tx_rx_disruption.321046469
Directory /workspace/17.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/170.usbdev_endpoint_types.671389433
Short name T516
Test name
Test status
Simulation time 211208129 ps
CPU time 1.1 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207532 kb
Host smart-02466ce4-485f-4d51-b207-b5ba903d4989
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=671389433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.671389433
Directory /workspace/170.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/170.usbdev_tx_rx_disruption.355865763
Short name T164
Test name
Test status
Simulation time 573161841 ps
CPU time 1.56 seconds
Started Aug 11 07:17:17 PM PDT 24
Finished Aug 11 07:17:18 PM PDT 24
Peak memory 207576 kb
Host smart-60de0504-4ee2-4ecc-8839-a67f345c47ed
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355865763 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 170.usbdev_tx_rx_disruption.355865763
Directory /workspace/170.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/171.usbdev_endpoint_types.218958807
Short name T1824
Test name
Test status
Simulation time 404162430 ps
CPU time 1.18 seconds
Started Aug 11 07:17:13 PM PDT 24
Finished Aug 11 07:17:14 PM PDT 24
Peak memory 207560 kb
Host smart-d606f261-868e-4cd4-93ee-e9b25ae8c881
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=218958807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.218958807
Directory /workspace/171.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/171.usbdev_tx_rx_disruption.2900822474
Short name T2768
Test name
Test status
Simulation time 614242556 ps
CPU time 1.7 seconds
Started Aug 11 07:17:24 PM PDT 24
Finished Aug 11 07:17:25 PM PDT 24
Peak memory 207548 kb
Host smart-c24f241a-8ce6-4226-82e2-b8e3fb6d023f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900822474 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.usbdev_tx_rx_disruption.2900822474
Directory /workspace/171.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/172.usbdev_endpoint_types.1097119263
Short name T434
Test name
Test status
Simulation time 426828258 ps
CPU time 1.24 seconds
Started Aug 11 07:17:22 PM PDT 24
Finished Aug 11 07:17:23 PM PDT 24
Peak memory 207568 kb
Host smart-04ca275d-3e6e-4142-beba-36b73dd007bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1097119263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.1097119263
Directory /workspace/172.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/172.usbdev_tx_rx_disruption.1608804251
Short name T1706
Test name
Test status
Simulation time 404463318 ps
CPU time 1.43 seconds
Started Aug 11 07:17:20 PM PDT 24
Finished Aug 11 07:17:22 PM PDT 24
Peak memory 207572 kb
Host smart-f4463fc4-7361-4a5f-83db-58687505c2dc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608804251 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.usbdev_tx_rx_disruption.1608804251
Directory /workspace/172.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/173.usbdev_endpoint_types.2796635925
Short name T3625
Test name
Test status
Simulation time 887037959 ps
CPU time 1.79 seconds
Started Aug 11 07:17:19 PM PDT 24
Finished Aug 11 07:17:21 PM PDT 24
Peak memory 207472 kb
Host smart-45dbf8ab-4304-474d-8c64-bca8a9e958ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2796635925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.2796635925
Directory /workspace/173.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/173.usbdev_tx_rx_disruption.461351145
Short name T3523
Test name
Test status
Simulation time 516928516 ps
CPU time 1.61 seconds
Started Aug 11 07:17:23 PM PDT 24
Finished Aug 11 07:17:25 PM PDT 24
Peak memory 207568 kb
Host smart-d67afeb9-009c-47c8-84cc-f0757e68abb7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461351145 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 173.usbdev_tx_rx_disruption.461351145
Directory /workspace/173.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/174.usbdev_endpoint_types.3334685772
Short name T2687
Test name
Test status
Simulation time 264503926 ps
CPU time 1 seconds
Started Aug 11 07:17:14 PM PDT 24
Finished Aug 11 07:17:15 PM PDT 24
Peak memory 207544 kb
Host smart-725f6036-4bef-4e65-af51-bb27bad9a774
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3334685772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.3334685772
Directory /workspace/174.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/175.usbdev_endpoint_types.977116817
Short name T491
Test name
Test status
Simulation time 386552708 ps
CPU time 1.35 seconds
Started Aug 11 07:17:29 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207492 kb
Host smart-1fb292e8-6715-4037-9756-7e81f857f4cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=977116817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.977116817
Directory /workspace/175.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/175.usbdev_tx_rx_disruption.203652916
Short name T1918
Test name
Test status
Simulation time 548671672 ps
CPU time 1.46 seconds
Started Aug 11 07:17:24 PM PDT 24
Finished Aug 11 07:17:26 PM PDT 24
Peak memory 207476 kb
Host smart-1ccb06ba-9d1a-4c24-aea9-74d7cd76cdf6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203652916 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 175.usbdev_tx_rx_disruption.203652916
Directory /workspace/175.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/176.usbdev_endpoint_types.46187718
Short name T455
Test name
Test status
Simulation time 435179487 ps
CPU time 1.46 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207540 kb
Host smart-9c394f14-6a06-4743-817c-04d4b35f4978
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=46187718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.46187718
Directory /workspace/176.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/176.usbdev_tx_rx_disruption.2322128691
Short name T2737
Test name
Test status
Simulation time 583954720 ps
CPU time 1.76 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207580 kb
Host smart-bb5ae047-80f7-41bc-99ed-4d4af01d27ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322128691 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.usbdev_tx_rx_disruption.2322128691
Directory /workspace/176.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/177.usbdev_tx_rx_disruption.1691274040
Short name T800
Test name
Test status
Simulation time 509754029 ps
CPU time 1.7 seconds
Started Aug 11 07:17:17 PM PDT 24
Finished Aug 11 07:17:19 PM PDT 24
Peak memory 207528 kb
Host smart-de4feab6-4945-46f1-a6ff-4499a44bec32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691274040 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.usbdev_tx_rx_disruption.1691274040
Directory /workspace/177.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/178.usbdev_endpoint_types.2920675013
Short name T461
Test name
Test status
Simulation time 412230424 ps
CPU time 1.26 seconds
Started Aug 11 07:17:13 PM PDT 24
Finished Aug 11 07:17:19 PM PDT 24
Peak memory 207452 kb
Host smart-21eeaaae-ab24-49fc-a751-14231e1a979d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2920675013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.2920675013
Directory /workspace/178.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/178.usbdev_tx_rx_disruption.1874513527
Short name T3292
Test name
Test status
Simulation time 515413425 ps
CPU time 1.79 seconds
Started Aug 11 07:17:09 PM PDT 24
Finished Aug 11 07:17:11 PM PDT 24
Peak memory 207780 kb
Host smart-f0635651-0c01-4637-8e8a-0ed196a2965d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874513527 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.usbdev_tx_rx_disruption.1874513527
Directory /workspace/178.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/179.usbdev_endpoint_types.351275303
Short name T481
Test name
Test status
Simulation time 326433883 ps
CPU time 1.14 seconds
Started Aug 11 07:17:11 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 207536 kb
Host smart-98bb0716-dd50-4583-91f5-5f11fa8b604e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=351275303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.351275303
Directory /workspace/179.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/179.usbdev_tx_rx_disruption.1658568751
Short name T2363
Test name
Test status
Simulation time 554929109 ps
CPU time 1.57 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207440 kb
Host smart-18846b8f-4f08-4ee6-9e08-c3d02478ba16
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658568751 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.usbdev_tx_rx_disruption.1658568751
Directory /workspace/179.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/18.usbdev_alert_test.4085593794
Short name T2460
Test name
Test status
Simulation time 105534287 ps
CPU time 0.78 seconds
Started Aug 11 07:12:07 PM PDT 24
Finished Aug 11 07:12:08 PM PDT 24
Peak memory 207548 kb
Host smart-bb211072-0e39-496d-a10a-7af91e8ec4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4085593794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.4085593794
Directory /workspace/18.usbdev_alert_test/latest


Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2349286037
Short name T1378
Test name
Test status
Simulation time 10098534678 ps
CPU time 13.75 seconds
Started Aug 11 07:12:01 PM PDT 24
Finished Aug 11 07:12:15 PM PDT 24
Peak memory 207840 kb
Host smart-6c026c6f-9b29-4da3-8f1f-eb3d48bb1298
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349286037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.2349286037
Directory /workspace/18.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.773004628
Short name T1122
Test name
Test status
Simulation time 21349131670 ps
CPU time 23.46 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207828 kb
Host smart-7422fee8-f525-4f2a-9371-b9832a04d206
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=773004628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.773004628
Directory /workspace/18.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3785304766
Short name T689
Test name
Test status
Simulation time 30363032013 ps
CPU time 38.23 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:12:32 PM PDT 24
Peak memory 207848 kb
Host smart-7f809201-837a-4119-ab90-de219d0ee029
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785304766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.3785304766
Directory /workspace/18.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/18.usbdev_av_buffer.1666204128
Short name T754
Test name
Test status
Simulation time 161064688 ps
CPU time 0.86 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207572 kb
Host smart-5394b043-c3a3-4d4f-846e-18bf7e52eb42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16662
04128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1666204128
Directory /workspace/18.usbdev_av_buffer/latest


Test location /workspace/coverage/default/18.usbdev_bitstuff_err.784377962
Short name T2573
Test name
Test status
Simulation time 150736113 ps
CPU time 0.87 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207492 kb
Host smart-db124b3e-519c-441d-9cdc-766ccc109f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78437
7962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.784377962
Directory /workspace/18.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3865477800
Short name T3577
Test name
Test status
Simulation time 565935681 ps
CPU time 1.85 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:11:57 PM PDT 24
Peak memory 207572 kb
Host smart-14d6704d-6eef-40fa-9815-372862cbc8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38654
77800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3865477800
Directory /workspace/18.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3897023110
Short name T1742
Test name
Test status
Simulation time 721578461 ps
CPU time 2.19 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207556 kb
Host smart-11551400-d022-4fa7-814d-169f182cef68
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3897023110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3897023110
Directory /workspace/18.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/18.usbdev_device_address.605910138
Short name T396
Test name
Test status
Simulation time 30003925601 ps
CPU time 48.08 seconds
Started Aug 11 07:12:01 PM PDT 24
Finished Aug 11 07:12:50 PM PDT 24
Peak memory 208028 kb
Host smart-c85ad7be-3e1b-40f7-93dc-a05ce6b99d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60591
0138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.605910138
Directory /workspace/18.usbdev_device_address/latest


Test location /workspace/coverage/default/18.usbdev_device_timeout.3071012100
Short name T861
Test name
Test status
Simulation time 1132575834 ps
CPU time 8.88 seconds
Started Aug 11 07:11:57 PM PDT 24
Finished Aug 11 07:12:06 PM PDT 24
Peak memory 207560 kb
Host smart-8d11b57e-247d-4616-aee5-055333b09c35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071012100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.3071012100
Directory /workspace/18.usbdev_device_timeout/latest


Test location /workspace/coverage/default/18.usbdev_disable_endpoint.4076907904
Short name T2571
Test name
Test status
Simulation time 1082295986 ps
CPU time 2.53 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207552 kb
Host smart-30887f65-153c-4d08-b98a-1c9bc4f8a71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40769
07904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.4076907904
Directory /workspace/18.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/18.usbdev_disconnected.1264010352
Short name T3185
Test name
Test status
Simulation time 146773047 ps
CPU time 0.83 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:11:56 PM PDT 24
Peak memory 207524 kb
Host smart-f09832af-b6a1-44d8-9db0-5159fed5a857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12640
10352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1264010352
Directory /workspace/18.usbdev_disconnected/latest


Test location /workspace/coverage/default/18.usbdev_enable.1653339430
Short name T574
Test name
Test status
Simulation time 74933242 ps
CPU time 0.87 seconds
Started Aug 11 07:12:02 PM PDT 24
Finished Aug 11 07:12:03 PM PDT 24
Peak memory 207476 kb
Host smart-b9182196-969b-41a6-826c-be3b2193e812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16533
39430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1653339430
Directory /workspace/18.usbdev_enable/latest


Test location /workspace/coverage/default/18.usbdev_endpoint_access.2069588302
Short name T1000
Test name
Test status
Simulation time 943644152 ps
CPU time 2.42 seconds
Started Aug 11 07:11:57 PM PDT 24
Finished Aug 11 07:12:00 PM PDT 24
Peak memory 207648 kb
Host smart-27360e6b-8e67-4a41-8756-8ec85c91844f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20695
88302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2069588302
Directory /workspace/18.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/18.usbdev_endpoint_types.3611993588
Short name T553
Test name
Test status
Simulation time 265398640 ps
CPU time 1.05 seconds
Started Aug 11 07:12:01 PM PDT 24
Finished Aug 11 07:12:02 PM PDT 24
Peak memory 207728 kb
Host smart-df5424b0-c56c-48be-8948-574d3e770d7c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3611993588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.3611993588
Directory /workspace/18.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/18.usbdev_fifo_rst.141046752
Short name T3144
Test name
Test status
Simulation time 196148451 ps
CPU time 2.58 seconds
Started Aug 11 07:12:00 PM PDT 24
Finished Aug 11 07:12:03 PM PDT 24
Peak memory 207724 kb
Host smart-6e5b7970-31fa-4b3e-89e7-3afd852761ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14104
6752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.141046752
Directory /workspace/18.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/18.usbdev_in_iso.2310852842
Short name T3307
Test name
Test status
Simulation time 166664733 ps
CPU time 0.89 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:11:54 PM PDT 24
Peak memory 207560 kb
Host smart-86199d4b-07d3-447d-b32c-d61cde397f20
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2310852842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2310852842
Directory /workspace/18.usbdev_in_iso/latest


Test location /workspace/coverage/default/18.usbdev_in_stall.3897399033
Short name T3443
Test name
Test status
Simulation time 155022197 ps
CPU time 0.82 seconds
Started Aug 11 07:12:01 PM PDT 24
Finished Aug 11 07:12:02 PM PDT 24
Peak memory 207480 kb
Host smart-914fd8fb-6185-4543-a56f-b9085c2b8057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38973
99033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3897399033
Directory /workspace/18.usbdev_in_stall/latest


Test location /workspace/coverage/default/18.usbdev_in_trans.3007803924
Short name T3585
Test name
Test status
Simulation time 262677357 ps
CPU time 1.05 seconds
Started Aug 11 07:12:02 PM PDT 24
Finished Aug 11 07:12:03 PM PDT 24
Peak memory 207756 kb
Host smart-69483109-f306-48ef-bb10-6b6a475590db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30078
03924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3007803924
Directory /workspace/18.usbdev_in_trans/latest


Test location /workspace/coverage/default/18.usbdev_invalid_sync.2926701623
Short name T2456
Test name
Test status
Simulation time 2934404398 ps
CPU time 23.3 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 217688 kb
Host smart-98593bf6-241e-422c-903e-524a22a70637
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2926701623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2926701623
Directory /workspace/18.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/18.usbdev_iso_retraction.3768564526
Short name T1174
Test name
Test status
Simulation time 7238565445 ps
CPU time 94.72 seconds
Started Aug 11 07:11:54 PM PDT 24
Finished Aug 11 07:13:29 PM PDT 24
Peak memory 207856 kb
Host smart-3e184c4b-07b0-4a27-b14d-e1afac640aad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3768564526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.3768564526
Directory /workspace/18.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/18.usbdev_link_in_err.3462672520
Short name T1607
Test name
Test status
Simulation time 188950035 ps
CPU time 1 seconds
Started Aug 11 07:12:01 PM PDT 24
Finished Aug 11 07:12:02 PM PDT 24
Peak memory 207768 kb
Host smart-e8a71fb8-cc9c-41c6-aa0a-cd679bb03cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34626
72520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3462672520
Directory /workspace/18.usbdev_link_in_err/latest


Test location /workspace/coverage/default/18.usbdev_link_resume.2885518299
Short name T710
Test name
Test status
Simulation time 6270408166 ps
CPU time 9.12 seconds
Started Aug 11 07:12:00 PM PDT 24
Finished Aug 11 07:12:09 PM PDT 24
Peak memory 215852 kb
Host smart-cf7fe397-6796-49f5-a6a0-f99eb03faeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28855
18299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.2885518299
Directory /workspace/18.usbdev_link_resume/latest


Test location /workspace/coverage/default/18.usbdev_link_suspend.1576139639
Short name T3147
Test name
Test status
Simulation time 8441493514 ps
CPU time 9.92 seconds
Started Aug 11 07:11:53 PM PDT 24
Finished Aug 11 07:12:03 PM PDT 24
Peak memory 207860 kb
Host smart-e90ee3e7-a35a-4028-8156-8b2d4e027230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15761
39639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1576139639
Directory /workspace/18.usbdev_link_suspend/latest


Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3365914299
Short name T3038
Test name
Test status
Simulation time 3765894950 ps
CPU time 30.69 seconds
Started Aug 11 07:12:02 PM PDT 24
Finished Aug 11 07:12:33 PM PDT 24
Peak memory 224248 kb
Host smart-b7f25872-a688-4dd6-b874-95dc912c2314
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3365914299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3365914299
Directory /workspace/18.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.596050213
Short name T3525
Test name
Test status
Simulation time 2470757604 ps
CPU time 20.72 seconds
Started Aug 11 07:11:54 PM PDT 24
Finished Aug 11 07:12:15 PM PDT 24
Peak memory 207844 kb
Host smart-86be0f65-7c52-4e6c-a36e-6fc278bd594a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=596050213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.596050213
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2829364897
Short name T1632
Test name
Test status
Simulation time 238853614 ps
CPU time 1.06 seconds
Started Aug 11 07:12:04 PM PDT 24
Finished Aug 11 07:12:05 PM PDT 24
Peak memory 207544 kb
Host smart-c9666cb7-553b-43f3-9c2c-903b8f6c953b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2829364897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2829364897
Directory /workspace/18.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1516361966
Short name T2122
Test name
Test status
Simulation time 199986863 ps
CPU time 1.03 seconds
Started Aug 11 07:12:04 PM PDT 24
Finished Aug 11 07:12:05 PM PDT 24
Peak memory 207572 kb
Host smart-57fae706-27a4-4ede-a238-d27d960db2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15163
61966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1516361966
Directory /workspace/18.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.371925771
Short name T3376
Test name
Test status
Simulation time 1773848702 ps
CPU time 13.13 seconds
Started Aug 11 07:12:04 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207764 kb
Host smart-02b5a353-4cc3-4ffa-972e-05edc92112ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37192
5771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.371925771
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1597176264
Short name T1565
Test name
Test status
Simulation time 2046648076 ps
CPU time 15.23 seconds
Started Aug 11 07:12:03 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207840 kb
Host smart-6274d08c-1863-48c9-b933-9f11c6304d68
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1597176264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1597176264
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.2739516718
Short name T1387
Test name
Test status
Simulation time 191717949 ps
CPU time 0.92 seconds
Started Aug 11 07:12:02 PM PDT 24
Finished Aug 11 07:12:04 PM PDT 24
Peak memory 207584 kb
Host smart-5480e1dd-af8e-4d83-a95f-f4a459e67ff3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2739516718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.2739516718
Directory /workspace/18.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.360019152
Short name T2079
Test name
Test status
Simulation time 152047121 ps
CPU time 0.89 seconds
Started Aug 11 07:12:03 PM PDT 24
Finished Aug 11 07:12:05 PM PDT 24
Peak memory 207572 kb
Host smart-84251640-7d22-4f20-bea9-bd3545878740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36001
9152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.360019152
Directory /workspace/18.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_nak_trans.2347032383
Short name T3499
Test name
Test status
Simulation time 176116026 ps
CPU time 0.91 seconds
Started Aug 11 07:12:03 PM PDT 24
Finished Aug 11 07:12:04 PM PDT 24
Peak memory 207564 kb
Host smart-67fe3827-e8ad-4dac-8c59-334f397b91e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23470
32383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2347032383
Directory /workspace/18.usbdev_nak_trans/latest


Test location /workspace/coverage/default/18.usbdev_out_iso.3183812040
Short name T1254
Test name
Test status
Simulation time 197376309 ps
CPU time 0.93 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:06 PM PDT 24
Peak memory 207504 kb
Host smart-bb6966d9-7e42-4f35-ad75-fa378d204c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31838
12040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3183812040
Directory /workspace/18.usbdev_out_iso/latest


Test location /workspace/coverage/default/18.usbdev_out_stall.4161682184
Short name T2412
Test name
Test status
Simulation time 190660593 ps
CPU time 0.98 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 207580 kb
Host smart-05102a9a-3121-4557-86f5-fe35319fbdfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41616
82184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4161682184
Directory /workspace/18.usbdev_out_stall/latest


Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1742095422
Short name T2665
Test name
Test status
Simulation time 255944920 ps
CPU time 1.01 seconds
Started Aug 11 07:12:02 PM PDT 24
Finished Aug 11 07:12:03 PM PDT 24
Peak memory 207480 kb
Host smart-c307c4da-1788-410a-b29b-eefd2456dd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17420
95422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1742095422
Directory /workspace/18.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1191476774
Short name T2271
Test name
Test status
Simulation time 162851351 ps
CPU time 0.84 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:06 PM PDT 24
Peak memory 207576 kb
Host smart-64f26011-499f-4404-9684-4282a86959fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11914
76774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1191476774
Directory /workspace/18.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.728521506
Short name T3115
Test name
Test status
Simulation time 270234755 ps
CPU time 1.18 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:06 PM PDT 24
Peak memory 207532 kb
Host smart-f5c59b6d-4229-473b-8315-7f1c47e18396
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=728521506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.728521506
Directory /workspace/18.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1711394136
Short name T1127
Test name
Test status
Simulation time 160234045 ps
CPU time 0.9 seconds
Started Aug 11 07:12:03 PM PDT 24
Finished Aug 11 07:12:04 PM PDT 24
Peak memory 207512 kb
Host smart-a5612312-40bd-4167-b23a-f903a5fc3f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17113
94136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1711394136
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1016453360
Short name T1318
Test name
Test status
Simulation time 37655367 ps
CPU time 0.72 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 207452 kb
Host smart-bb51d4df-55ca-4663-8317-c62938dbbd0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
53360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1016453360
Directory /workspace/18.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3850395767
Short name T2107
Test name
Test status
Simulation time 11086951442 ps
CPU time 29.56 seconds
Started Aug 11 07:12:04 PM PDT 24
Finished Aug 11 07:12:33 PM PDT 24
Peak memory 220332 kb
Host smart-1d46ca6a-6ce7-46f8-910d-21da1ff7783e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38503
95767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3850395767
Directory /workspace/18.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/18.usbdev_pkt_received.919524256
Short name T372
Test name
Test status
Simulation time 184819228 ps
CPU time 0.96 seconds
Started Aug 11 07:12:04 PM PDT 24
Finished Aug 11 07:12:05 PM PDT 24
Peak memory 207568 kb
Host smart-e96c6402-2dd5-4454-aa4e-5ade91c1ad32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91952
4256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.919524256
Directory /workspace/18.usbdev_pkt_received/latest


Test location /workspace/coverage/default/18.usbdev_pkt_sent.448267713
Short name T3624
Test name
Test status
Simulation time 191456468 ps
CPU time 0.92 seconds
Started Aug 11 07:12:04 PM PDT 24
Finished Aug 11 07:12:05 PM PDT 24
Peak memory 207520 kb
Host smart-7d69dbee-ace1-4922-851a-915ca2608ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44826
7713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.448267713
Directory /workspace/18.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2021714705
Short name T2127
Test name
Test status
Simulation time 218179102 ps
CPU time 0.98 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:06 PM PDT 24
Peak memory 207468 kb
Host smart-ae931826-68d8-4a2c-97fa-8ff0b8912fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20217
14705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2021714705
Directory /workspace/18.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.1589592971
Short name T2527
Test name
Test status
Simulation time 194414690 ps
CPU time 0.93 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 207580 kb
Host smart-118ef15b-4817-4fce-89f7-e5472479a15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15895
92971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.1589592971
Directory /workspace/18.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_resume_link_active.3472607868
Short name T3175
Test name
Test status
Simulation time 20171013650 ps
CPU time 25.57 seconds
Started Aug 11 07:12:07 PM PDT 24
Finished Aug 11 07:12:33 PM PDT 24
Peak memory 207652 kb
Host smart-c93eddaf-dfc4-4028-a5fb-50774fbb3cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34726
07868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.3472607868
Directory /workspace/18.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2574345136
Short name T3314
Test name
Test status
Simulation time 159577552 ps
CPU time 0.92 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 207568 kb
Host smart-a93bc80e-5c30-4b19-bbf8-21943277ba3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25743
45136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2574345136
Directory /workspace/18.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/18.usbdev_setup_stage.3993922966
Short name T2211
Test name
Test status
Simulation time 150414751 ps
CPU time 0.86 seconds
Started Aug 11 07:12:04 PM PDT 24
Finished Aug 11 07:12:05 PM PDT 24
Peak memory 207484 kb
Host smart-b95cf785-705a-4461-82d6-e223e1f9f9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39939
22966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3993922966
Directory /workspace/18.usbdev_setup_stage/latest


Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.205990040
Short name T758
Test name
Test status
Simulation time 150261603 ps
CPU time 0.81 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:06 PM PDT 24
Peak memory 207476 kb
Host smart-c752cef8-94d3-4733-9612-f3cc071d3981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20599
0040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.205990040
Directory /workspace/18.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/18.usbdev_smoke.440371777
Short name T1239
Test name
Test status
Simulation time 193986579 ps
CPU time 0.96 seconds
Started Aug 11 07:12:03 PM PDT 24
Finished Aug 11 07:12:04 PM PDT 24
Peak memory 207488 kb
Host smart-de40dc4e-b285-47be-af05-36954837a233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44037
1777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.440371777
Directory /workspace/18.usbdev_smoke/latest


Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.327449988
Short name T3178
Test name
Test status
Simulation time 2035187235 ps
CPU time 15.7 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:22 PM PDT 24
Peak memory 224168 kb
Host smart-526c96c3-6258-4b8e-b1e8-903ef0a9169f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=327449988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.327449988
Directory /workspace/18.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3887130534
Short name T1460
Test name
Test status
Simulation time 175163984 ps
CPU time 0.92 seconds
Started Aug 11 07:12:07 PM PDT 24
Finished Aug 11 07:12:08 PM PDT 24
Peak memory 207520 kb
Host smart-89031c60-16c3-4df0-8214-73ccdf1fffee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38871
30534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3887130534
Directory /workspace/18.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/18.usbdev_stall_trans.766175256
Short name T2199
Test name
Test status
Simulation time 174045746 ps
CPU time 0.91 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 207568 kb
Host smart-0e93e274-d1d4-485d-bde2-5274716b2cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76617
5256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.766175256
Directory /workspace/18.usbdev_stall_trans/latest


Test location /workspace/coverage/default/18.usbdev_stream_len_max.3373267322
Short name T2187
Test name
Test status
Simulation time 1258486894 ps
CPU time 2.84 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:09 PM PDT 24
Peak memory 207740 kb
Host smart-8782c995-15ab-4e3f-8672-481d4ec0e450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33732
67322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3373267322
Directory /workspace/18.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/18.usbdev_streaming_out.2928074355
Short name T795
Test name
Test status
Simulation time 3076048602 ps
CPU time 88.02 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 217444 kb
Host smart-aca6a380-1255-4355-a805-69fb5dfa976d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29280
74355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2928074355
Directory /workspace/18.usbdev_streaming_out/latest


Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.2047893582
Short name T604
Test name
Test status
Simulation time 3580010864 ps
CPU time 22.41 seconds
Started Aug 11 07:11:55 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207832 kb
Host smart-8fcfcb0e-0f7b-4bfe-8e2d-f5b4316cc29c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047893582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.2047893582
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/18.usbdev_tx_rx_disruption.2347073490
Short name T3474
Test name
Test status
Simulation time 502472477 ps
CPU time 1.49 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:08 PM PDT 24
Peak memory 207568 kb
Host smart-f5f06b9c-c71f-4496-aba6-9b534935a1ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347073490 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.usbdev_tx_rx_disruption.2347073490
Directory /workspace/18.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/180.usbdev_endpoint_types.4214405557
Short name T3264
Test name
Test status
Simulation time 220258903 ps
CPU time 1.06 seconds
Started Aug 11 07:17:18 PM PDT 24
Finished Aug 11 07:17:19 PM PDT 24
Peak memory 207516 kb
Host smart-e76092cf-b880-4f74-896a-bf6927ecea51
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4214405557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.4214405557
Directory /workspace/180.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/180.usbdev_tx_rx_disruption.3157531760
Short name T2957
Test name
Test status
Simulation time 625918595 ps
CPU time 1.63 seconds
Started Aug 11 07:17:11 PM PDT 24
Finished Aug 11 07:17:13 PM PDT 24
Peak memory 207544 kb
Host smart-78c35a7e-0877-41a5-96f6-efaedb205fa4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157531760 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.usbdev_tx_rx_disruption.3157531760
Directory /workspace/180.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/181.usbdev_endpoint_types.1290928034
Short name T556
Test name
Test status
Simulation time 167853168 ps
CPU time 0.87 seconds
Started Aug 11 07:17:23 PM PDT 24
Finished Aug 11 07:17:24 PM PDT 24
Peak memory 207536 kb
Host smart-3f5850b0-7d6e-4259-8678-fbfb4c0eae35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1290928034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.1290928034
Directory /workspace/181.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/181.usbdev_tx_rx_disruption.2488897823
Short name T2171
Test name
Test status
Simulation time 482751015 ps
CPU time 1.47 seconds
Started Aug 11 07:17:17 PM PDT 24
Finished Aug 11 07:17:19 PM PDT 24
Peak memory 207568 kb
Host smart-530a05ea-15eb-403f-bff7-5cb918082ca7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488897823 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.usbdev_tx_rx_disruption.2488897823
Directory /workspace/181.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/182.usbdev_endpoint_types.3362151545
Short name T415
Test name
Test status
Simulation time 490812981 ps
CPU time 1.46 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207508 kb
Host smart-0a928a7c-52f4-43da-b478-a16144edeeff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3362151545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.3362151545
Directory /workspace/182.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/182.usbdev_tx_rx_disruption.352394883
Short name T1564
Test name
Test status
Simulation time 473964335 ps
CPU time 1.48 seconds
Started Aug 11 07:17:15 PM PDT 24
Finished Aug 11 07:17:17 PM PDT 24
Peak memory 207592 kb
Host smart-1d7a0ca8-2bd6-46ff-9f02-875872cca280
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352394883 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 182.usbdev_tx_rx_disruption.352394883
Directory /workspace/182.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/183.usbdev_endpoint_types.3331204303
Short name T2814
Test name
Test status
Simulation time 467814129 ps
CPU time 1.31 seconds
Started Aug 11 07:17:14 PM PDT 24
Finished Aug 11 07:17:15 PM PDT 24
Peak memory 207468 kb
Host smart-a999fcd1-b28c-419c-88e5-907298aff248
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3331204303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.3331204303
Directory /workspace/183.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/183.usbdev_tx_rx_disruption.1524116285
Short name T3488
Test name
Test status
Simulation time 483548810 ps
CPU time 1.38 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207556 kb
Host smart-22568817-ebc2-4045-8b4f-4d4b30ea40bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524116285 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.usbdev_tx_rx_disruption.1524116285
Directory /workspace/183.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/184.usbdev_endpoint_types.3126689659
Short name T501
Test name
Test status
Simulation time 407947685 ps
CPU time 1.13 seconds
Started Aug 11 07:17:10 PM PDT 24
Finished Aug 11 07:17:11 PM PDT 24
Peak memory 207536 kb
Host smart-0d80e0a8-f913-4783-aa31-feff3295fb8a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3126689659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.3126689659
Directory /workspace/184.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/184.usbdev_tx_rx_disruption.2381600397
Short name T2625
Test name
Test status
Simulation time 505276607 ps
CPU time 1.58 seconds
Started Aug 11 07:17:12 PM PDT 24
Finished Aug 11 07:17:14 PM PDT 24
Peak memory 207536 kb
Host smart-bd97c819-8ce9-430a-8721-6ea7dc5df5d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381600397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.usbdev_tx_rx_disruption.2381600397
Directory /workspace/184.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/185.usbdev_endpoint_types.1056937058
Short name T431
Test name
Test status
Simulation time 477326727 ps
CPU time 1.35 seconds
Started Aug 11 07:17:21 PM PDT 24
Finished Aug 11 07:17:23 PM PDT 24
Peak memory 207484 kb
Host smart-59f6c1da-f5a2-45cd-b04d-65b4274688ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1056937058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.1056937058
Directory /workspace/185.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/185.usbdev_tx_rx_disruption.93983593
Short name T2384
Test name
Test status
Simulation time 569804676 ps
CPU time 1.71 seconds
Started Aug 11 07:17:18 PM PDT 24
Finished Aug 11 07:17:19 PM PDT 24
Peak memory 207572 kb
Host smart-2c708775-aeb5-4546-bedf-4fcad33950bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93983593 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 185.usbdev_tx_rx_disruption.93983593
Directory /workspace/185.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/186.usbdev_endpoint_types.2588152670
Short name T477
Test name
Test status
Simulation time 528299026 ps
CPU time 1.39 seconds
Started Aug 11 07:17:23 PM PDT 24
Finished Aug 11 07:17:24 PM PDT 24
Peak memory 207500 kb
Host smart-e641e390-dc16-4cdd-8b3a-fb5b7db0d7db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2588152670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.2588152670
Directory /workspace/186.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/186.usbdev_tx_rx_disruption.1167173966
Short name T726
Test name
Test status
Simulation time 584997742 ps
CPU time 1.8 seconds
Started Aug 11 07:17:11 PM PDT 24
Finished Aug 11 07:17:13 PM PDT 24
Peak memory 207500 kb
Host smart-904fc47f-a0ca-4be0-92b2-2211996f57e3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167173966 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 186.usbdev_tx_rx_disruption.1167173966
Directory /workspace/186.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/187.usbdev_endpoint_types.2951015779
Short name T499
Test name
Test status
Simulation time 342372795 ps
CPU time 1.31 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:36 PM PDT 24
Peak memory 207508 kb
Host smart-f4dd4312-ad5c-4723-9f29-7d2c2b911e27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2951015779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.2951015779
Directory /workspace/187.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/187.usbdev_tx_rx_disruption.1136060171
Short name T773
Test name
Test status
Simulation time 571236979 ps
CPU time 1.61 seconds
Started Aug 11 07:17:37 PM PDT 24
Finished Aug 11 07:17:39 PM PDT 24
Peak memory 207552 kb
Host smart-c81e1a68-ecf7-4a09-b985-52a5ace92777
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136060171 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.usbdev_tx_rx_disruption.1136060171
Directory /workspace/187.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/188.usbdev_endpoint_types.3473067389
Short name T3197
Test name
Test status
Simulation time 522940116 ps
CPU time 1.43 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:40 PM PDT 24
Peak memory 207444 kb
Host smart-2b925fec-02e9-4315-a250-5b2741e7e673
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3473067389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.3473067389
Directory /workspace/188.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/188.usbdev_tx_rx_disruption.591778036
Short name T2320
Test name
Test status
Simulation time 552008773 ps
CPU time 1.59 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207556 kb
Host smart-016565e4-de06-44a0-9110-3429f9427eaf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591778036 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 188.usbdev_tx_rx_disruption.591778036
Directory /workspace/188.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/189.usbdev_tx_rx_disruption.2455507927
Short name T2256
Test name
Test status
Simulation time 605696923 ps
CPU time 1.55 seconds
Started Aug 11 07:17:28 PM PDT 24
Finished Aug 11 07:17:29 PM PDT 24
Peak memory 207572 kb
Host smart-12662392-ffe1-47eb-8656-855f9892eab9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455507927 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.usbdev_tx_rx_disruption.2455507927
Directory /workspace/189.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/19.usbdev_alert_test.1347292973
Short name T2604
Test name
Test status
Simulation time 46801793 ps
CPU time 0.69 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207524 kb
Host smart-21bf7178-30f4-4790-9b44-1dfb89278624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1347292973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.1347292973
Directory /workspace/19.usbdev_alert_test/latest


Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1945818339
Short name T2070
Test name
Test status
Simulation time 9786334638 ps
CPU time 13.07 seconds
Started Aug 11 07:12:07 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207828 kb
Host smart-c2a0b6ec-739d-44d9-a1cd-354b4201a506
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945818339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.1945818339
Directory /workspace/19.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.4112008276
Short name T8
Test name
Test status
Simulation time 16337768873 ps
CPU time 19.11 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 215888 kb
Host smart-f084758c-a7e0-4652-8d34-2e1e2814831a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112008276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.4112008276
Directory /workspace/19.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.3066900033
Short name T1099
Test name
Test status
Simulation time 31319371073 ps
CPU time 38.39 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:44 PM PDT 24
Peak memory 207728 kb
Host smart-3dd7e710-bd7d-4d7d-a8c6-18ea6018f3a5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066900033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.3066900033
Directory /workspace/19.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/19.usbdev_av_buffer.175664478
Short name T1899
Test name
Test status
Simulation time 160854128 ps
CPU time 0.9 seconds
Started Aug 11 07:12:07 PM PDT 24
Finished Aug 11 07:12:08 PM PDT 24
Peak memory 207584 kb
Host smart-50a35993-fdff-428a-8d1c-7064327c24c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17566
4478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.175664478
Directory /workspace/19.usbdev_av_buffer/latest


Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3439253296
Short name T943
Test name
Test status
Simulation time 145349104 ps
CPU time 0.86 seconds
Started Aug 11 07:12:07 PM PDT 24
Finished Aug 11 07:12:08 PM PDT 24
Peak memory 207580 kb
Host smart-4ca46ae5-4537-45d5-ae49-f4f813b50acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392
53296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3439253296
Directory /workspace/19.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1309783252
Short name T620
Test name
Test status
Simulation time 424951615 ps
CPU time 1.39 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 207500 kb
Host smart-24e6023f-7030-4d16-9234-865bc932e92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13097
83252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1309783252
Directory /workspace/19.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.897743962
Short name T354
Test name
Test status
Simulation time 726309609 ps
CPU time 1.95 seconds
Started Aug 11 07:12:06 PM PDT 24
Finished Aug 11 07:12:08 PM PDT 24
Peak memory 207564 kb
Host smart-dad1642b-4e82-4fd5-90a5-7fea1570bd73
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=897743962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.897743962
Directory /workspace/19.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/19.usbdev_device_timeout.860183223
Short name T1959
Test name
Test status
Simulation time 1116904167 ps
CPU time 8.94 seconds
Started Aug 11 07:12:05 PM PDT 24
Finished Aug 11 07:12:15 PM PDT 24
Peak memory 207668 kb
Host smart-e7756620-7699-40cc-a597-8610ce1801e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860183223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.860183223
Directory /workspace/19.usbdev_device_timeout/latest


Test location /workspace/coverage/default/19.usbdev_disable_endpoint.4149379100
Short name T2732
Test name
Test status
Simulation time 1015019763 ps
CPU time 2.38 seconds
Started Aug 11 07:12:10 PM PDT 24
Finished Aug 11 07:12:12 PM PDT 24
Peak memory 207528 kb
Host smart-5a3032c4-43cb-45ee-905f-f79ab294f6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41493
79100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.4149379100
Directory /workspace/19.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/19.usbdev_disconnected.523912688
Short name T1442
Test name
Test status
Simulation time 144042430 ps
CPU time 0.88 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207560 kb
Host smart-65a70e28-281a-425c-8277-7f98f86665c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52391
2688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.523912688
Directory /workspace/19.usbdev_disconnected/latest


Test location /workspace/coverage/default/19.usbdev_enable.4280021770
Short name T2780
Test name
Test status
Simulation time 84783601 ps
CPU time 0.84 seconds
Started Aug 11 07:12:14 PM PDT 24
Finished Aug 11 07:12:15 PM PDT 24
Peak memory 207504 kb
Host smart-2d6d5f5e-7b4d-4196-a7cd-2875b0f63b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42800
21770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.4280021770
Directory /workspace/19.usbdev_enable/latest


Test location /workspace/coverage/default/19.usbdev_endpoint_access.471463555
Short name T1371
Test name
Test status
Simulation time 899220292 ps
CPU time 2.49 seconds
Started Aug 11 07:12:13 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207728 kb
Host smart-cc82750c-b9d6-4a74-9b8f-2ace0a99c46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47146
3555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.471463555
Directory /workspace/19.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/19.usbdev_endpoint_types.3864670154
Short name T2927
Test name
Test status
Simulation time 221200442 ps
CPU time 1.05 seconds
Started Aug 11 07:12:13 PM PDT 24
Finished Aug 11 07:12:14 PM PDT 24
Peak memory 207504 kb
Host smart-62c35cf6-3518-4b4b-a4fc-87218760c3a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3864670154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.3864670154
Directory /workspace/19.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/19.usbdev_fifo_rst.785599779
Short name T1205
Test name
Test status
Simulation time 303923969 ps
CPU time 2.13 seconds
Started Aug 11 07:12:13 PM PDT 24
Finished Aug 11 07:12:15 PM PDT 24
Peak memory 207640 kb
Host smart-e5ee5b18-8bcd-44cd-8299-670c52f77fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78559
9779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.785599779
Directory /workspace/19.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/19.usbdev_in_iso.3323345058
Short name T638
Test name
Test status
Simulation time 219938387 ps
CPU time 1.16 seconds
Started Aug 11 07:12:11 PM PDT 24
Finished Aug 11 07:12:12 PM PDT 24
Peak memory 215864 kb
Host smart-293b3778-252c-4236-afd5-59be2c84c813
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3323345058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3323345058
Directory /workspace/19.usbdev_in_iso/latest


Test location /workspace/coverage/default/19.usbdev_in_stall.4186994525
Short name T1087
Test name
Test status
Simulation time 161027546 ps
CPU time 0.85 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207448 kb
Host smart-b7d0ced4-23c2-41d6-a4a6-87ff25d3c396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41869
94525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.4186994525
Directory /workspace/19.usbdev_in_stall/latest


Test location /workspace/coverage/default/19.usbdev_in_trans.2103288003
Short name T715
Test name
Test status
Simulation time 231416261 ps
CPU time 0.92 seconds
Started Aug 11 07:12:12 PM PDT 24
Finished Aug 11 07:12:13 PM PDT 24
Peak memory 207556 kb
Host smart-4234b3bd-bf85-430f-a22e-79600edbf2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21032
88003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2103288003
Directory /workspace/19.usbdev_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_invalid_sync.180112395
Short name T1181
Test name
Test status
Simulation time 5009332846 ps
CPU time 144.26 seconds
Started Aug 11 07:12:11 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 224176 kb
Host smart-add50106-bb88-4c61-9890-581073982c8b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=180112395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.180112395
Directory /workspace/19.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/19.usbdev_iso_retraction.127132949
Short name T2229
Test name
Test status
Simulation time 7743571614 ps
CPU time 58.25 seconds
Started Aug 11 07:12:14 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207780 kb
Host smart-daae5048-a287-4788-b0f7-ec0cee2e9c84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=127132949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.127132949
Directory /workspace/19.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/19.usbdev_link_in_err.544826814
Short name T900
Test name
Test status
Simulation time 181491316 ps
CPU time 0.85 seconds
Started Aug 11 07:12:13 PM PDT 24
Finished Aug 11 07:12:14 PM PDT 24
Peak memory 207504 kb
Host smart-3ecd149b-a729-4413-8a9b-70ba5064ece0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54482
6814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.544826814
Directory /workspace/19.usbdev_link_in_err/latest


Test location /workspace/coverage/default/19.usbdev_link_resume.2444157998
Short name T3232
Test name
Test status
Simulation time 34024881795 ps
CPU time 56.04 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207892 kb
Host smart-a74259aa-0be8-42e0-b6f0-e9bf5e1d2238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24441
57998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.2444157998
Directory /workspace/19.usbdev_link_resume/latest


Test location /workspace/coverage/default/19.usbdev_link_suspend.3460471683
Short name T3134
Test name
Test status
Simulation time 3816810263 ps
CPU time 5.91 seconds
Started Aug 11 07:12:12 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 216184 kb
Host smart-0b347f24-e6e8-418a-9a99-d36499f2f9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34604
71683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3460471683
Directory /workspace/19.usbdev_link_suspend/latest


Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2151961301
Short name T3540
Test name
Test status
Simulation time 4220889993 ps
CPU time 121 seconds
Started Aug 11 07:12:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 219180 kb
Host smart-773cfec8-1e2c-44b9-a4ff-7f6675d96fae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2151961301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2151961301
Directory /workspace/19.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1343422940
Short name T608
Test name
Test status
Simulation time 2164520525 ps
CPU time 61.28 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:13:16 PM PDT 24
Peak memory 216048 kb
Host smart-8baf97a6-0bde-4701-b82b-a1ff84ab91a4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1343422940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1343422940
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2439544416
Short name T3123
Test name
Test status
Simulation time 241163724 ps
CPU time 1.04 seconds
Started Aug 11 07:12:14 PM PDT 24
Finished Aug 11 07:12:15 PM PDT 24
Peak memory 207492 kb
Host smart-72428649-7dff-4667-8fb4-a19f0380e090
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2439544416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2439544416
Directory /workspace/19.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1606803641
Short name T1101
Test name
Test status
Simulation time 191197958 ps
CPU time 0.94 seconds
Started Aug 11 07:12:13 PM PDT 24
Finished Aug 11 07:12:14 PM PDT 24
Peak memory 207564 kb
Host smart-4e918649-2114-4ab5-aa86-1263569b6a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16068
03641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1606803641
Directory /workspace/19.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.1203285480
Short name T743
Test name
Test status
Simulation time 2400222807 ps
CPU time 19.1 seconds
Started Aug 11 07:12:14 PM PDT 24
Finished Aug 11 07:12:33 PM PDT 24
Peak memory 217864 kb
Host smart-ca599b6d-890c-4804-b0b0-a9c086b93b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
85480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.1203285480
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1021536680
Short name T888
Test name
Test status
Simulation time 2336496896 ps
CPU time 17.74 seconds
Started Aug 11 07:12:13 PM PDT 24
Finished Aug 11 07:12:31 PM PDT 24
Peak memory 207992 kb
Host smart-9441334a-1033-4274-a39c-25d5c1d8cfb0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1021536680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1021536680
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.455811443
Short name T2244
Test name
Test status
Simulation time 150493780 ps
CPU time 0.82 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207604 kb
Host smart-9e2ee5d4-8d7d-47f8-b3cf-8dde9d5ff680
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=455811443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.455811443
Directory /workspace/19.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1523134547
Short name T849
Test name
Test status
Simulation time 152808686 ps
CPU time 0.83 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207572 kb
Host smart-cb3fb5ff-d31d-4311-bbfa-36528abcc164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15231
34547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1523134547
Directory /workspace/19.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_nak_trans.1107870437
Short name T137
Test name
Test status
Simulation time 218815010 ps
CPU time 1.07 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207552 kb
Host smart-69cc4893-702e-41a7-b460-88777c7dd8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11078
70437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1107870437
Directory /workspace/19.usbdev_nak_trans/latest


Test location /workspace/coverage/default/19.usbdev_out_iso.3123984656
Short name T2048
Test name
Test status
Simulation time 226334112 ps
CPU time 0.94 seconds
Started Aug 11 07:12:13 PM PDT 24
Finished Aug 11 07:12:14 PM PDT 24
Peak memory 207576 kb
Host smart-56c3e965-307e-4b1c-9acb-8ab488b38fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31239
84656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3123984656
Directory /workspace/19.usbdev_out_iso/latest


Test location /workspace/coverage/default/19.usbdev_out_stall.3510990008
Short name T2516
Test name
Test status
Simulation time 189868432 ps
CPU time 0.89 seconds
Started Aug 11 07:12:16 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207556 kb
Host smart-17bedcbd-149c-423f-ae02-26257d40b3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35109
90008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3510990008
Directory /workspace/19.usbdev_out_stall/latest


Test location /workspace/coverage/default/19.usbdev_out_trans_nak.703125506
Short name T850
Test name
Test status
Simulation time 192898284 ps
CPU time 0.92 seconds
Started Aug 11 07:12:13 PM PDT 24
Finished Aug 11 07:12:14 PM PDT 24
Peak memory 207544 kb
Host smart-34dffd87-9d0e-44c2-91c7-e9724dfcc85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70312
5506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.703125506
Directory /workspace/19.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/19.usbdev_pending_in_trans.727543502
Short name T2141
Test name
Test status
Simulation time 165520437 ps
CPU time 0.9 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207508 kb
Host smart-e59f37c6-a3f1-4798-a206-6df375af50c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72754
3502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.727543502
Directory /workspace/19.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3896788608
Short name T1568
Test name
Test status
Simulation time 216788972 ps
CPU time 0.98 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207604 kb
Host smart-f2722401-36ad-4308-8633-70bce66a743c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3896788608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3896788608
Directory /workspace/19.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.165025212
Short name T3582
Test name
Test status
Simulation time 148185562 ps
CPU time 0.9 seconds
Started Aug 11 07:12:16 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207516 kb
Host smart-e895b999-bc41-4cb3-a5f4-4bd1b53066d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16502
5212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.165025212
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2385330267
Short name T3492
Test name
Test status
Simulation time 126504982 ps
CPU time 0.81 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207512 kb
Host smart-d0960734-dddd-4f40-9ea2-31604680f291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23853
30267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2385330267
Directory /workspace/19.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3837967672
Short name T2924
Test name
Test status
Simulation time 22802416323 ps
CPU time 59.62 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 216112 kb
Host smart-c7b9fa28-26d3-45e6-8994-d2a6529f27a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38379
67672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3837967672
Directory /workspace/19.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/19.usbdev_pkt_received.1075486109
Short name T3062
Test name
Test status
Simulation time 203360921 ps
CPU time 0.96 seconds
Started Aug 11 07:12:16 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207548 kb
Host smart-da9879bd-d8a5-4787-96a0-ab1c47002f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10754
86109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1075486109
Directory /workspace/19.usbdev_pkt_received/latest


Test location /workspace/coverage/default/19.usbdev_pkt_sent.3642732592
Short name T1236
Test name
Test status
Simulation time 244816435 ps
CPU time 1.01 seconds
Started Aug 11 07:12:16 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207544 kb
Host smart-879ef535-906b-4437-832d-f2a1e7824f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36427
32592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3642732592
Directory /workspace/19.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2357971921
Short name T2496
Test name
Test status
Simulation time 171519463 ps
CPU time 0.86 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207552 kb
Host smart-df3d928b-61bc-474f-926c-8b38c6af65cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23579
71921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2357971921
Directory /workspace/19.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3899340391
Short name T1603
Test name
Test status
Simulation time 174287929 ps
CPU time 0.95 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207544 kb
Host smart-5b87fb3b-69b0-4f44-892a-e64a07d5e82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38993
40391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3899340391
Directory /workspace/19.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_resume_link_active.3979957373
Short name T1138
Test name
Test status
Simulation time 20186342762 ps
CPU time 23.94 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:39 PM PDT 24
Peak memory 207620 kb
Host smart-6bf8855f-aa3e-4740-85a4-091a6e91531e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39799
57373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.3979957373
Directory /workspace/19.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2895361378
Short name T2906
Test name
Test status
Simulation time 175706597 ps
CPU time 0.85 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207516 kb
Host smart-7fb48128-8dc5-467d-91d6-b89099db1fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28953
61378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2895361378
Directory /workspace/19.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/19.usbdev_rx_full.3199125567
Short name T52
Test name
Test status
Simulation time 269121353 ps
CPU time 1.08 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207476 kb
Host smart-c099c630-7c86-4f93-9b24-58b779069685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31991
25567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.3199125567
Directory /workspace/19.usbdev_rx_full/latest


Test location /workspace/coverage/default/19.usbdev_setup_stage.2757408801
Short name T1182
Test name
Test status
Simulation time 156844501 ps
CPU time 0.92 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:16 PM PDT 24
Peak memory 207544 kb
Host smart-798b46f2-e53c-43ba-8b6a-c555e14ad439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27574
08801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2757408801
Directory /workspace/19.usbdev_setup_stage/latest


Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1964278211
Short name T994
Test name
Test status
Simulation time 177458495 ps
CPU time 0.92 seconds
Started Aug 11 07:12:16 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207544 kb
Host smart-8eb90e9f-6c2b-4200-a549-89b9902105dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19642
78211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1964278211
Directory /workspace/19.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/19.usbdev_smoke.1203830517
Short name T3171
Test name
Test status
Simulation time 259442339 ps
CPU time 1.11 seconds
Started Aug 11 07:12:18 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207576 kb
Host smart-2e266f5c-5ac8-42be-a7b3-d86a2613fe55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12038
30517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1203830517
Directory /workspace/19.usbdev_smoke/latest


Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1900817052
Short name T3326
Test name
Test status
Simulation time 2096514015 ps
CPU time 57.77 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 216012 kb
Host smart-e2ae70c0-2548-48d6-a2d9-ab775d8fbf0b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1900817052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1900817052
Directory /workspace/19.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.826072204
Short name T1166
Test name
Test status
Simulation time 168081864 ps
CPU time 0.91 seconds
Started Aug 11 07:12:18 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207572 kb
Host smart-14ea8337-d09b-4bfe-8429-7f95f71f088c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82607
2204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.826072204
Directory /workspace/19.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/19.usbdev_stall_trans.1009866996
Short name T2036
Test name
Test status
Simulation time 177604951 ps
CPU time 0.98 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207572 kb
Host smart-7b11ae22-de41-444e-998d-7c5ea33b5146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10098
66996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1009866996
Directory /workspace/19.usbdev_stall_trans/latest


Test location /workspace/coverage/default/19.usbdev_stream_len_max.3941538565
Short name T3104
Test name
Test status
Simulation time 223413799 ps
CPU time 0.94 seconds
Started Aug 11 07:12:21 PM PDT 24
Finished Aug 11 07:12:23 PM PDT 24
Peak memory 207460 kb
Host smart-6c6e965a-23c4-408f-8094-bbc2fac6f8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39415
38565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.3941538565
Directory /workspace/19.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/19.usbdev_streaming_out.1108149566
Short name T2820
Test name
Test status
Simulation time 2338778048 ps
CPU time 69.52 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:13:25 PM PDT 24
Peak memory 217508 kb
Host smart-2fb9b267-0932-41d4-819c-eb6fd56a22e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
49566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1108149566
Directory /workspace/19.usbdev_streaming_out/latest


Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.918180413
Short name T3221
Test name
Test status
Simulation time 277023306 ps
CPU time 4.53 seconds
Started Aug 11 07:12:12 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207728 kb
Host smart-0f8e992a-5d9a-4e8e-ba83-0a4f74fbc001
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918180413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_host
_handshake.918180413
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/19.usbdev_tx_rx_disruption.1373240862
Short name T1414
Test name
Test status
Simulation time 543228906 ps
CPU time 1.66 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207516 kb
Host smart-0c635a76-459d-42e8-8c41-d7976a19d093
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373240862 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.usbdev_tx_rx_disruption.1373240862
Directory /workspace/19.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/190.usbdev_tx_rx_disruption.475214407
Short name T80
Test name
Test status
Simulation time 616460529 ps
CPU time 1.67 seconds
Started Aug 11 07:17:38 PM PDT 24
Finished Aug 11 07:17:40 PM PDT 24
Peak memory 207560 kb
Host smart-3ac7a15e-77fd-4f8e-b471-03944b25f5cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475214407 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 190.usbdev_tx_rx_disruption.475214407
Directory /workspace/190.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/191.usbdev_endpoint_types.3337042567
Short name T498
Test name
Test status
Simulation time 464862623 ps
CPU time 1.48 seconds
Started Aug 11 07:17:26 PM PDT 24
Finished Aug 11 07:17:27 PM PDT 24
Peak memory 207468 kb
Host smart-7614f736-d3d7-4497-a189-ebfa19d58228
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3337042567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.3337042567
Directory /workspace/191.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/191.usbdev_tx_rx_disruption.959974523
Short name T3226
Test name
Test status
Simulation time 554239842 ps
CPU time 1.78 seconds
Started Aug 11 07:17:37 PM PDT 24
Finished Aug 11 07:17:39 PM PDT 24
Peak memory 207536 kb
Host smart-afe09978-f249-4d49-bec5-873f0b89b2c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959974523 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 191.usbdev_tx_rx_disruption.959974523
Directory /workspace/191.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/192.usbdev_endpoint_types.480025726
Short name T1
Test name
Test status
Simulation time 508673277 ps
CPU time 1.48 seconds
Started Aug 11 07:17:22 PM PDT 24
Finished Aug 11 07:17:23 PM PDT 24
Peak memory 207560 kb
Host smart-e5a754d6-84ec-40cb-b1bb-253bab65a752
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=480025726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.480025726
Directory /workspace/192.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/192.usbdev_tx_rx_disruption.1919904225
Short name T2954
Test name
Test status
Simulation time 588551361 ps
CPU time 1.58 seconds
Started Aug 11 07:17:40 PM PDT 24
Finished Aug 11 07:17:42 PM PDT 24
Peak memory 207484 kb
Host smart-02dad507-fb35-4ae3-9eb3-e1dfeeab85da
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919904225 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.usbdev_tx_rx_disruption.1919904225
Directory /workspace/192.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/193.usbdev_endpoint_types.745456363
Short name T2518
Test name
Test status
Simulation time 334435950 ps
CPU time 1.11 seconds
Started Aug 11 07:17:29 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207532 kb
Host smart-027de9d8-dbe5-4971-a4e5-fd36159967c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=745456363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.745456363
Directory /workspace/193.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/193.usbdev_tx_rx_disruption.512592963
Short name T2992
Test name
Test status
Simulation time 552469599 ps
CPU time 1.65 seconds
Started Aug 11 07:17:28 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207480 kb
Host smart-9f8dfb18-392f-4a84-86e2-4a35aa33efac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512592963 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 193.usbdev_tx_rx_disruption.512592963
Directory /workspace/193.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/194.usbdev_tx_rx_disruption.3247974817
Short name T99
Test name
Test status
Simulation time 522013479 ps
CPU time 1.47 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:35 PM PDT 24
Peak memory 207572 kb
Host smart-08dad542-4e7c-4f70-9a73-d7d31519b2dd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247974817 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.usbdev_tx_rx_disruption.3247974817
Directory /workspace/194.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/195.usbdev_tx_rx_disruption.402099067
Short name T1120
Test name
Test status
Simulation time 581087047 ps
CPU time 1.67 seconds
Started Aug 11 07:17:20 PM PDT 24
Finished Aug 11 07:17:21 PM PDT 24
Peak memory 207564 kb
Host smart-8cc06896-38aa-497e-889d-e4e2653e4495
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402099067 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 195.usbdev_tx_rx_disruption.402099067
Directory /workspace/195.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/196.usbdev_endpoint_types.3688475825
Short name T469
Test name
Test status
Simulation time 746980512 ps
CPU time 1.97 seconds
Started Aug 11 07:17:27 PM PDT 24
Finished Aug 11 07:17:29 PM PDT 24
Peak memory 207716 kb
Host smart-25d54ca3-1b70-4fc3-a9d5-f8defa0c81e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3688475825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.3688475825
Directory /workspace/196.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/196.usbdev_tx_rx_disruption.1606290515
Short name T2617
Test name
Test status
Simulation time 528976445 ps
CPU time 1.57 seconds
Started Aug 11 07:17:17 PM PDT 24
Finished Aug 11 07:17:19 PM PDT 24
Peak memory 207576 kb
Host smart-aec4f7c0-5132-4873-93f1-4c9da763d5cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606290515 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.usbdev_tx_rx_disruption.1606290515
Directory /workspace/196.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/197.usbdev_endpoint_types.4102260952
Short name T493
Test name
Test status
Simulation time 537457369 ps
CPU time 1.52 seconds
Started Aug 11 07:17:30 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 207484 kb
Host smart-a1e1b4db-ba6d-4489-a5ed-70998a9b5edb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4102260952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.4102260952
Directory /workspace/197.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/197.usbdev_tx_rx_disruption.2625951986
Short name T1904
Test name
Test status
Simulation time 588378276 ps
CPU time 1.76 seconds
Started Aug 11 07:17:28 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207572 kb
Host smart-f130b028-91b2-4c6d-82b9-99b4f1ca9027
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625951986 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.usbdev_tx_rx_disruption.2625951986
Directory /workspace/197.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/198.usbdev_endpoint_types.201317087
Short name T1331
Test name
Test status
Simulation time 195452233 ps
CPU time 0.92 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207508 kb
Host smart-99711852-29ee-463a-a1c9-00f1f9c999c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=201317087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.201317087
Directory /workspace/198.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/198.usbdev_tx_rx_disruption.140111596
Short name T1788
Test name
Test status
Simulation time 541374684 ps
CPU time 1.66 seconds
Started Aug 11 07:17:36 PM PDT 24
Finished Aug 11 07:17:37 PM PDT 24
Peak memory 207568 kb
Host smart-e9be6ccf-87ee-44c4-96e1-7bf481b467e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140111596 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 198.usbdev_tx_rx_disruption.140111596
Directory /workspace/198.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/199.usbdev_endpoint_types.3659602458
Short name T529
Test name
Test status
Simulation time 195176042 ps
CPU time 0.96 seconds
Started Aug 11 07:17:30 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 207564 kb
Host smart-8b8f55a7-c765-4b9d-a52c-a23550798f44
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3659602458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.3659602458
Directory /workspace/199.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/199.usbdev_tx_rx_disruption.2003690148
Short name T1999
Test name
Test status
Simulation time 483254748 ps
CPU time 1.55 seconds
Started Aug 11 07:17:24 PM PDT 24
Finished Aug 11 07:17:25 PM PDT 24
Peak memory 207508 kb
Host smart-c6c2cafa-6ea2-4968-a302-d034da10acac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003690148 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.usbdev_tx_rx_disruption.2003690148
Directory /workspace/199.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/2.usbdev_alert_test.881926200
Short name T718
Test name
Test status
Simulation time 32336514 ps
CPU time 0.66 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:09:05 PM PDT 24
Peak memory 207568 kb
Host smart-7e78d8bd-8dbb-4b05-9398-45ee0c5ef610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=881926200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.881926200
Directory /workspace/2.usbdev_alert_test/latest


Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3950057467
Short name T1810
Test name
Test status
Simulation time 4187280953 ps
CPU time 5.62 seconds
Started Aug 11 07:08:50 PM PDT 24
Finished Aug 11 07:08:56 PM PDT 24
Peak memory 216012 kb
Host smart-f9d4e90f-1710-492c-9645-015aeaa0f61e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950057467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.3950057467
Directory /workspace/2.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.867277534
Short name T1486
Test name
Test status
Simulation time 14143294901 ps
CPU time 19.39 seconds
Started Aug 11 07:08:50 PM PDT 24
Finished Aug 11 07:09:10 PM PDT 24
Peak memory 216012 kb
Host smart-130ade55-9d03-4bf4-92a1-142906eba1a5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=867277534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.867277534
Directory /workspace/2.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1880054883
Short name T3145
Test name
Test status
Simulation time 29153540107 ps
CPU time 37.84 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:09:31 PM PDT 24
Peak memory 207864 kb
Host smart-4ea84551-0c0a-4884-a8a3-b490604308b1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880054883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.1880054883
Directory /workspace/2.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/2.usbdev_av_buffer.2038428435
Short name T865
Test name
Test status
Simulation time 153123711 ps
CPU time 0.87 seconds
Started Aug 11 07:08:49 PM PDT 24
Finished Aug 11 07:08:50 PM PDT 24
Peak memory 207512 kb
Host smart-564f44bd-1708-414a-8206-d289c316a23a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20384
28435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2038428435
Directory /workspace/2.usbdev_av_buffer/latest


Test location /workspace/coverage/default/2.usbdev_av_empty.829715154
Short name T49
Test name
Test status
Simulation time 177865177 ps
CPU time 0.94 seconds
Started Aug 11 07:08:49 PM PDT 24
Finished Aug 11 07:08:50 PM PDT 24
Peak memory 207512 kb
Host smart-4e9a1d4d-4028-46fa-893b-82ff4a9cc917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82971
5154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.829715154
Directory /workspace/2.usbdev_av_empty/latest


Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2025904642
Short name T1023
Test name
Test status
Simulation time 164019661 ps
CPU time 0.86 seconds
Started Aug 11 07:08:54 PM PDT 24
Finished Aug 11 07:08:55 PM PDT 24
Peak memory 207500 kb
Host smart-8f76f45a-b862-44a5-9abf-8676b231f75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20259
04642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2025904642
Directory /workspace/2.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.1953599757
Short name T935
Test name
Test status
Simulation time 349108631 ps
CPU time 1.24 seconds
Started Aug 11 07:08:52 PM PDT 24
Finished Aug 11 07:08:54 PM PDT 24
Peak memory 207512 kb
Host smart-e1422e5d-db27-4f04-993a-92cc903f1720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19535
99757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1953599757
Directory /workspace/2.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/2.usbdev_device_address.1651702180
Short name T2738
Test name
Test status
Simulation time 14561747811 ps
CPU time 26 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:09:20 PM PDT 24
Peak memory 207828 kb
Host smart-fcc50ac7-08ba-4548-8f85-ddd4d89085d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16517
02180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1651702180
Directory /workspace/2.usbdev_device_address/latest


Test location /workspace/coverage/default/2.usbdev_device_timeout.75012843
Short name T2072
Test name
Test status
Simulation time 1567930164 ps
CPU time 13.81 seconds
Started Aug 11 07:08:56 PM PDT 24
Finished Aug 11 07:09:10 PM PDT 24
Peak memory 207680 kb
Host smart-610fd6cd-6f97-416d-8b20-86952b73e950
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75012843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.75012843
Directory /workspace/2.usbdev_device_timeout/latest


Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2223168665
Short name T2612
Test name
Test status
Simulation time 642696441 ps
CPU time 1.75 seconds
Started Aug 11 07:08:56 PM PDT 24
Finished Aug 11 07:08:58 PM PDT 24
Peak memory 207456 kb
Host smart-3058aa7a-c7a8-486b-8a6c-d0a2710bd0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22231
68665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2223168665
Directory /workspace/2.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/2.usbdev_disconnected.1016672223
Short name T2369
Test name
Test status
Simulation time 174381108 ps
CPU time 0.9 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:08:54 PM PDT 24
Peak memory 207480 kb
Host smart-435485ef-fe0c-404a-aa51-9f41468e90db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10166
72223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1016672223
Directory /workspace/2.usbdev_disconnected/latest


Test location /workspace/coverage/default/2.usbdev_enable.1320426588
Short name T776
Test name
Test status
Simulation time 40931950 ps
CPU time 0.74 seconds
Started Aug 11 07:08:56 PM PDT 24
Finished Aug 11 07:08:56 PM PDT 24
Peak memory 207488 kb
Host smart-a8e8e292-b658-4b56-a16a-d58ed0e0edc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13204
26588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1320426588
Directory /workspace/2.usbdev_enable/latest


Test location /workspace/coverage/default/2.usbdev_endpoint_access.745071330
Short name T3024
Test name
Test status
Simulation time 783198633 ps
CPU time 2.2 seconds
Started Aug 11 07:08:55 PM PDT 24
Finished Aug 11 07:08:58 PM PDT 24
Peak memory 207708 kb
Host smart-4e25d04f-3001-4a0f-9677-9ffb4444896e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74507
1330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.745071330
Directory /workspace/2.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/2.usbdev_endpoint_types.1217148449
Short name T1033
Test name
Test status
Simulation time 167236271 ps
CPU time 0.89 seconds
Started Aug 11 07:08:56 PM PDT 24
Finished Aug 11 07:08:57 PM PDT 24
Peak memory 207484 kb
Host smart-1da30e14-5d22-48f4-ab97-73a72dc593e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1217148449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.1217148449
Directory /workspace/2.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/2.usbdev_fifo_rst.4157979535
Short name T1340
Test name
Test status
Simulation time 408034133 ps
CPU time 2.88 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:08:57 PM PDT 24
Peak memory 207724 kb
Host smart-a3454119-e17a-4a46-8287-5730c81cdc7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41579
79535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.4157979535
Directory /workspace/2.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3831544908
Short name T3146
Test name
Test status
Simulation time 107189632162 ps
CPU time 177.34 seconds
Started Aug 11 07:08:55 PM PDT 24
Finished Aug 11 07:11:53 PM PDT 24
Peak memory 207852 kb
Host smart-73e00502-a665-4d1b-a91c-e87c22576a9b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3831544908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3831544908
Directory /workspace/2.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.3331564459
Short name T362
Test name
Test status
Simulation time 83211755744 ps
CPU time 129.4 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:11:03 PM PDT 24
Peak memory 207896 kb
Host smart-85b52d9a-0b23-4769-8b10-902a30f61a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331564459 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.3331564459
Directory /workspace/2.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.3917220172
Short name T2061
Test name
Test status
Simulation time 92058759609 ps
CPU time 142.14 seconds
Started Aug 11 07:08:52 PM PDT 24
Finished Aug 11 07:11:14 PM PDT 24
Peak memory 207812 kb
Host smart-0fb14dd8-76b8-4b96-96ed-0ee6eb1e9998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917220172 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.3917220172
Directory /workspace/2.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/2.usbdev_freq_phase.3961244972
Short name T2430
Test name
Test status
Simulation time 95144497961 ps
CPU time 173.87 seconds
Started Aug 11 07:08:57 PM PDT 24
Finished Aug 11 07:11:51 PM PDT 24
Peak memory 207824 kb
Host smart-da2f4f8d-6fcb-4180-b876-002be4c52b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39612
44972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3961244972
Directory /workspace/2.usbdev_freq_phase/latest


Test location /workspace/coverage/default/2.usbdev_in_iso.1589817955
Short name T3370
Test name
Test status
Simulation time 221026200 ps
CPU time 1.05 seconds
Started Aug 11 07:08:56 PM PDT 24
Finished Aug 11 07:08:57 PM PDT 24
Peak memory 215852 kb
Host smart-339bec11-cd2c-4b1c-9f86-b2ba22a7d7b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1589817955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1589817955
Directory /workspace/2.usbdev_in_iso/latest


Test location /workspace/coverage/default/2.usbdev_in_stall.3714712635
Short name T3188
Test name
Test status
Simulation time 143427641 ps
CPU time 0.88 seconds
Started Aug 11 07:08:56 PM PDT 24
Finished Aug 11 07:08:57 PM PDT 24
Peak memory 207484 kb
Host smart-5fd9ca16-6b39-427e-86d2-2fe1b3a4a227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37147
12635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3714712635
Directory /workspace/2.usbdev_in_stall/latest


Test location /workspace/coverage/default/2.usbdev_in_trans.2822394971
Short name T2565
Test name
Test status
Simulation time 260226187 ps
CPU time 1.11 seconds
Started Aug 11 07:08:54 PM PDT 24
Finished Aug 11 07:08:55 PM PDT 24
Peak memory 207448 kb
Host smart-38c7d3d8-90d7-4519-b3df-7c66333f5b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28223
94971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2822394971
Directory /workspace/2.usbdev_in_trans/latest


Test location /workspace/coverage/default/2.usbdev_invalid_sync.2892588943
Short name T3388
Test name
Test status
Simulation time 3963624624 ps
CPU time 120.55 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:10:54 PM PDT 24
Peak memory 217624 kb
Host smart-999fbc00-69e7-404f-a31e-39b253aa6ad5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2892588943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.2892588943
Directory /workspace/2.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/2.usbdev_iso_retraction.3261112716
Short name T3412
Test name
Test status
Simulation time 10182567583 ps
CPU time 70.26 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:10:03 PM PDT 24
Peak memory 207764 kb
Host smart-b2fd1868-467a-490e-a785-e9274618b353
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3261112716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3261112716
Directory /workspace/2.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/2.usbdev_link_in_err.1216282690
Short name T3248
Test name
Test status
Simulation time 250100823 ps
CPU time 1.03 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:08:55 PM PDT 24
Peak memory 207484 kb
Host smart-544cb436-fc0b-4075-966a-7928cc192fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12162
82690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1216282690
Directory /workspace/2.usbdev_link_in_err/latest


Test location /workspace/coverage/default/2.usbdev_link_resume.953369015
Short name T2855
Test name
Test status
Simulation time 8684054424 ps
CPU time 12.22 seconds
Started Aug 11 07:08:57 PM PDT 24
Finished Aug 11 07:09:09 PM PDT 24
Peak memory 216336 kb
Host smart-549aa450-1b23-4798-a3d7-7b4dadec0b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95336
9015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.953369015
Directory /workspace/2.usbdev_link_resume/latest


Test location /workspace/coverage/default/2.usbdev_link_suspend.1185702732
Short name T2826
Test name
Test status
Simulation time 6098161872 ps
CPU time 8.34 seconds
Started Aug 11 07:08:56 PM PDT 24
Finished Aug 11 07:09:04 PM PDT 24
Peak memory 207844 kb
Host smart-f5e02a2b-a599-4210-8e81-8df50d5c950f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11857
02732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1185702732
Directory /workspace/2.usbdev_link_suspend/latest


Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3000217750
Short name T2945
Test name
Test status
Simulation time 5378001152 ps
CPU time 43.49 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:09:37 PM PDT 24
Peak memory 219772 kb
Host smart-aca202f6-a12a-4277-aa1c-8c7c38bd9ed0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3000217750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3000217750
Directory /workspace/2.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1845379111
Short name T693
Test name
Test status
Simulation time 264814102 ps
CPU time 1.02 seconds
Started Aug 11 07:08:56 PM PDT 24
Finished Aug 11 07:08:57 PM PDT 24
Peak memory 207512 kb
Host smart-8e390ab7-e96a-462d-ba58-e0d41a6a209b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1845379111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1845379111
Directory /workspace/2.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3615963611
Short name T1691
Test name
Test status
Simulation time 183188522 ps
CPU time 0.97 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:08:54 PM PDT 24
Peak memory 207548 kb
Host smart-2aa06f4f-a471-4d46-93c1-0ac193a139b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36159
63611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3615963611
Directory /workspace/2.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.284447523
Short name T1549
Test name
Test status
Simulation time 1902253254 ps
CPU time 18.75 seconds
Started Aug 11 07:08:54 PM PDT 24
Finished Aug 11 07:09:13 PM PDT 24
Peak memory 224052 kb
Host smart-6305c557-92a4-48d6-9d6c-c470e1c4f571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28444
7523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.284447523
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2501309358
Short name T2365
Test name
Test status
Simulation time 3486371680 ps
CPU time 40.51 seconds
Started Aug 11 07:08:59 PM PDT 24
Finished Aug 11 07:09:40 PM PDT 24
Peak memory 218744 kb
Host smart-8bf2aa5b-e0a2-4934-8f32-efb5763c069a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2501309358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2501309358
Directory /workspace/2.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3232685121
Short name T1854
Test name
Test status
Simulation time 2043357291 ps
CPU time 57.47 seconds
Started Aug 11 07:08:58 PM PDT 24
Finished Aug 11 07:09:56 PM PDT 24
Peak memory 217372 kb
Host smart-24667dc2-56fe-4fe9-a29f-ae70c983165f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3232685121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3232685121
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1569149279
Short name T2955
Test name
Test status
Simulation time 175338633 ps
CPU time 0.85 seconds
Started Aug 11 07:08:59 PM PDT 24
Finished Aug 11 07:09:00 PM PDT 24
Peak memory 207580 kb
Host smart-123f0020-0381-4c4d-b78f-f9ae757748a4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1569149279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1569149279
Directory /workspace/2.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3807794723
Short name T871
Test name
Test status
Simulation time 147159971 ps
CPU time 0.85 seconds
Started Aug 11 07:08:58 PM PDT 24
Finished Aug 11 07:08:59 PM PDT 24
Peak memory 207532 kb
Host smart-4201e152-6e2f-4f8d-9d03-9db9d03226bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38077
94723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3807794723
Directory /workspace/2.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_out_iso.2424601195
Short name T592
Test name
Test status
Simulation time 180683197 ps
CPU time 0.94 seconds
Started Aug 11 07:09:02 PM PDT 24
Finished Aug 11 07:09:03 PM PDT 24
Peak memory 207596 kb
Host smart-b6052d50-aafc-4802-bcf0-e3808c75c85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24246
01195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2424601195
Directory /workspace/2.usbdev_out_iso/latest


Test location /workspace/coverage/default/2.usbdev_out_stall.3986456543
Short name T792
Test name
Test status
Simulation time 158971356 ps
CPU time 0.87 seconds
Started Aug 11 07:09:03 PM PDT 24
Finished Aug 11 07:09:04 PM PDT 24
Peak memory 207532 kb
Host smart-f6512401-25d4-41b6-b591-91fcb9bdf954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39864
56543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3986456543
Directory /workspace/2.usbdev_out_stall/latest


Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2459491107
Short name T1362
Test name
Test status
Simulation time 146275219 ps
CPU time 0.84 seconds
Started Aug 11 07:09:02 PM PDT 24
Finished Aug 11 07:09:02 PM PDT 24
Peak memory 207496 kb
Host smart-66249716-db8f-40a7-86c4-e734d6c0e6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24594
91107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2459491107
Directory /workspace/2.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1795552644
Short name T2285
Test name
Test status
Simulation time 147157546 ps
CPU time 0.86 seconds
Started Aug 11 07:08:58 PM PDT 24
Finished Aug 11 07:08:59 PM PDT 24
Peak memory 207572 kb
Host smart-0005825a-0a1d-49cb-a660-82c38e3df14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17955
52644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1795552644
Directory /workspace/2.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1348194967
Short name T2402
Test name
Test status
Simulation time 215831567 ps
CPU time 1.02 seconds
Started Aug 11 07:09:02 PM PDT 24
Finished Aug 11 07:09:03 PM PDT 24
Peak memory 207764 kb
Host smart-c8161c9f-e502-4e7b-8bf2-6d2474eb0fa4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1348194967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1348194967
Directory /workspace/2.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.96416857
Short name T1735
Test name
Test status
Simulation time 248219109 ps
CPU time 1.13 seconds
Started Aug 11 07:09:00 PM PDT 24
Finished Aug 11 07:09:02 PM PDT 24
Peak memory 207484 kb
Host smart-2ee6242c-d86b-4e39-93b2-6dfbbbf6a243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96416
857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.96416857
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2446010469
Short name T1947
Test name
Test status
Simulation time 178418382 ps
CPU time 0.87 seconds
Started Aug 11 07:09:03 PM PDT 24
Finished Aug 11 07:09:04 PM PDT 24
Peak memory 207496 kb
Host smart-68f2b300-9224-47d0-b6bd-80cbb10430d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24460
10469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2446010469
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.328341392
Short name T2471
Test name
Test status
Simulation time 61711656 ps
CPU time 0.77 seconds
Started Aug 11 07:09:01 PM PDT 24
Finished Aug 11 07:09:02 PM PDT 24
Peak memory 207460 kb
Host smart-c8721b02-377c-4473-a105-4de39341a092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32834
1392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.328341392
Directory /workspace/2.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1381251748
Short name T2923
Test name
Test status
Simulation time 13673683316 ps
CPU time 37.57 seconds
Started Aug 11 07:09:01 PM PDT 24
Finished Aug 11 07:09:39 PM PDT 24
Peak memory 216012 kb
Host smart-b26c40f4-80f5-4c27-b27a-8f9a6e27c2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13812
51748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1381251748
Directory /workspace/2.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/2.usbdev_pkt_received.3506206640
Short name T1116
Test name
Test status
Simulation time 195761814 ps
CPU time 0.94 seconds
Started Aug 11 07:09:03 PM PDT 24
Finished Aug 11 07:09:04 PM PDT 24
Peak memory 207548 kb
Host smart-a2cee7cf-a52d-464c-9155-16381ed5c4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35062
06640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3506206640
Directory /workspace/2.usbdev_pkt_received/latest


Test location /workspace/coverage/default/2.usbdev_pkt_sent.3358596135
Short name T1748
Test name
Test status
Simulation time 214225704 ps
CPU time 0.99 seconds
Started Aug 11 07:09:00 PM PDT 24
Finished Aug 11 07:09:01 PM PDT 24
Peak memory 207544 kb
Host smart-046cb00d-96a5-4cdf-90ec-7cef6faf2da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33585
96135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3358596135
Directory /workspace/2.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.699235984
Short name T2825
Test name
Test status
Simulation time 6917383017 ps
CPU time 94.04 seconds
Started Aug 11 07:09:02 PM PDT 24
Finished Aug 11 07:10:36 PM PDT 24
Peak memory 219092 kb
Host smart-d75e011f-9d7a-480c-9063-09d0a3c38950
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=699235984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.699235984
Directory /workspace/2.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2325139806
Short name T630
Test name
Test status
Simulation time 5640694683 ps
CPU time 27.47 seconds
Started Aug 11 07:09:00 PM PDT 24
Finished Aug 11 07:09:28 PM PDT 24
Peak memory 219248 kb
Host smart-b9fd01ea-8565-4215-9afd-1cbdd221ad3e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2325139806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2325139806
Directory /workspace/2.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/2.usbdev_rand_suspends.2111716997
Short name T3481
Test name
Test status
Simulation time 14659655759 ps
CPU time 327.96 seconds
Started Aug 11 07:09:00 PM PDT 24
Finished Aug 11 07:14:28 PM PDT 24
Peak memory 217756 kb
Host smart-d4b7c344-0082-4d80-8e59-3c7c28b6d31c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111716997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2111716997
Directory /workspace/2.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1676393797
Short name T2021
Test name
Test status
Simulation time 160094879 ps
CPU time 0.89 seconds
Started Aug 11 07:08:58 PM PDT 24
Finished Aug 11 07:08:59 PM PDT 24
Peak memory 207548 kb
Host smart-97feacf3-be1a-485f-94a4-01e56c1147d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16763
93797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1676393797
Directory /workspace/2.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.4116594338
Short name T2185
Test name
Test status
Simulation time 169515104 ps
CPU time 0.87 seconds
Started Aug 11 07:09:01 PM PDT 24
Finished Aug 11 07:09:02 PM PDT 24
Peak memory 207484 kb
Host smart-396c8909-1036-43ca-8f03-06a1b36eade1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41165
94338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.4116594338
Directory /workspace/2.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_resume_link_active.2346381496
Short name T3596
Test name
Test status
Simulation time 20156821881 ps
CPU time 24.5 seconds
Started Aug 11 07:08:59 PM PDT 24
Finished Aug 11 07:09:23 PM PDT 24
Peak memory 207664 kb
Host smart-e33be37c-d267-40b7-ab63-06fa6d13d53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23463
81496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.2346381496
Directory /workspace/2.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1772892518
Short name T2104
Test name
Test status
Simulation time 192747418 ps
CPU time 0.93 seconds
Started Aug 11 07:08:57 PM PDT 24
Finished Aug 11 07:08:58 PM PDT 24
Peak memory 207572 kb
Host smart-58458796-32b1-4f9d-9055-d158163ce3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17728
92518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1772892518
Directory /workspace/2.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/2.usbdev_rx_full.243184065
Short name T1829
Test name
Test status
Simulation time 246019129 ps
CPU time 1.05 seconds
Started Aug 11 07:09:02 PM PDT 24
Finished Aug 11 07:09:04 PM PDT 24
Peak memory 207568 kb
Host smart-b352d3c0-8957-43c9-8f34-dca29b6d6c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24318
4065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.243184065
Directory /workspace/2.usbdev_rx_full/latest


Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1689032403
Short name T82
Test name
Test status
Simulation time 165996887 ps
CPU time 0.87 seconds
Started Aug 11 07:08:59 PM PDT 24
Finished Aug 11 07:09:00 PM PDT 24
Peak memory 207572 kb
Host smart-1d02d813-8b9d-4e59-afda-6e06b6eaff44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16890
32403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1689032403
Directory /workspace/2.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/2.usbdev_sec_cm.2299233081
Short name T239
Test name
Test status
Simulation time 786304436 ps
CPU time 1.67 seconds
Started Aug 11 07:09:03 PM PDT 24
Finished Aug 11 07:09:05 PM PDT 24
Peak memory 224596 kb
Host smart-e8ecb5c9-5925-4ada-a0d2-c038df357c57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2299233081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2299233081
Directory /workspace/2.usbdev_sec_cm/latest


Test location /workspace/coverage/default/2.usbdev_setup_priority.2866931931
Short name T38
Test name
Test status
Simulation time 412596298 ps
CPU time 1.4 seconds
Started Aug 11 07:08:59 PM PDT 24
Finished Aug 11 07:09:01 PM PDT 24
Peak memory 207580 kb
Host smart-953e5fd9-698a-484f-8fc9-5d4b4adbcb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28669
31931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2866931931
Directory /workspace/2.usbdev_setup_priority/latest


Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3350221094
Short name T1807
Test name
Test status
Simulation time 211253634 ps
CPU time 1.02 seconds
Started Aug 11 07:09:01 PM PDT 24
Finished Aug 11 07:09:02 PM PDT 24
Peak memory 207496 kb
Host smart-add5f378-bfcc-451c-ae18-38fd967b7d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33502
21094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3350221094
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/2.usbdev_setup_stage.603612899
Short name T582
Test name
Test status
Simulation time 157783553 ps
CPU time 0.89 seconds
Started Aug 11 07:09:00 PM PDT 24
Finished Aug 11 07:09:01 PM PDT 24
Peak memory 207512 kb
Host smart-35b9e5fa-7e73-4a84-96da-425bfd53542e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60361
2899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.603612899
Directory /workspace/2.usbdev_setup_stage/latest


Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.206228081
Short name T2051
Test name
Test status
Simulation time 163981351 ps
CPU time 0.85 seconds
Started Aug 11 07:08:59 PM PDT 24
Finished Aug 11 07:09:00 PM PDT 24
Peak memory 207508 kb
Host smart-3b8520bd-5ca1-43d9-b6a4-ded9ac2b26b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
8081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.206228081
Directory /workspace/2.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/2.usbdev_smoke.3255036938
Short name T3164
Test name
Test status
Simulation time 215080354 ps
CPU time 1 seconds
Started Aug 11 07:09:00 PM PDT 24
Finished Aug 11 07:09:01 PM PDT 24
Peak memory 207544 kb
Host smart-87e4f42a-b0d7-4456-978a-f48dae54e905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32550
36938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3255036938
Directory /workspace/2.usbdev_smoke/latest


Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3605793040
Short name T1124
Test name
Test status
Simulation time 2734835318 ps
CPU time 80.21 seconds
Started Aug 11 07:09:05 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 218028 kb
Host smart-2c4f948a-2d97-4934-a428-0737c1b6ee2e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3605793040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3605793040
Directory /workspace/2.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1067026130
Short name T1431
Test name
Test status
Simulation time 190569404 ps
CPU time 0.89 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 207480 kb
Host smart-27fe1ddd-b93e-490a-8c86-33da3b7fd758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10670
26130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1067026130
Directory /workspace/2.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/2.usbdev_stall_trans.492491246
Short name T1428
Test name
Test status
Simulation time 220578559 ps
CPU time 0.93 seconds
Started Aug 11 07:09:03 PM PDT 24
Finished Aug 11 07:09:04 PM PDT 24
Peak memory 207560 kb
Host smart-d6d9ac5d-6c14-4944-88b0-88418537edb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49249
1246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.492491246
Directory /workspace/2.usbdev_stall_trans/latest


Test location /workspace/coverage/default/2.usbdev_stream_len_max.2426950826
Short name T1736
Test name
Test status
Simulation time 527993769 ps
CPU time 1.6 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:09:06 PM PDT 24
Peak memory 207464 kb
Host smart-db27d33e-3329-4350-9547-b105a835ea56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269
50826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2426950826
Directory /workspace/2.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/2.usbdev_streaming_out.4181975940
Short name T3005
Test name
Test status
Simulation time 3566762788 ps
CPU time 34.92 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 216096 kb
Host smart-024e2016-01f8-4d31-a2c3-24ece875b72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41819
75940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.4181975940
Directory /workspace/2.usbdev_streaming_out/latest


Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3203048330
Short name T85
Test name
Test status
Simulation time 7670606241 ps
CPU time 112.26 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:10:57 PM PDT 24
Peak memory 219148 kb
Host smart-fdfc249f-9fb2-4bc0-982d-5be390b0b597
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203048330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.3203048330
Directory /workspace/2.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.3523200929
Short name T1606
Test name
Test status
Simulation time 2288674175 ps
CPU time 15.16 seconds
Started Aug 11 07:08:53 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 207848 kb
Host smart-ed58fe27-9d9b-4fde-9807-9d23d48394db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523200929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.3523200929
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/2.usbdev_tx_rx_disruption.3136548771
Short name T2277
Test name
Test status
Simulation time 560967151 ps
CPU time 1.55 seconds
Started Aug 11 07:09:07 PM PDT 24
Finished Aug 11 07:09:09 PM PDT 24
Peak memory 207560 kb
Host smart-66ed4d1a-80b6-431c-aa3f-9ca3ac5e449b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136548771 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.usbdev_tx_rx_disruption.3136548771
Directory /workspace/2.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/20.usbdev_alert_test.1023302073
Short name T1893
Test name
Test status
Simulation time 102679286 ps
CPU time 0.75 seconds
Started Aug 11 07:12:28 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207536 kb
Host smart-93e670c5-8faf-45bb-abd4-91a27f2a099c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1023302073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.1023302073
Directory /workspace/20.usbdev_alert_test/latest


Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2516889644
Short name T3047
Test name
Test status
Simulation time 6430010645 ps
CPU time 9.09 seconds
Started Aug 11 07:12:20 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 215376 kb
Host smart-e4bc0e39-8993-4396-a35d-382c45127bf7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516889644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.2516889644
Directory /workspace/20.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.780221960
Short name T2280
Test name
Test status
Simulation time 19680375290 ps
CPU time 24.01 seconds
Started Aug 11 07:12:21 PM PDT 24
Finished Aug 11 07:12:45 PM PDT 24
Peak memory 207860 kb
Host smart-e10f17e2-b021-40e2-823b-d5ae71ef7abe
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=780221960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.780221960
Directory /workspace/20.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3091311932
Short name T3165
Test name
Test status
Simulation time 28534199588 ps
CPU time 36.76 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:54 PM PDT 24
Peak memory 207768 kb
Host smart-cf32236b-4789-439f-b552-f91737ee4130
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091311932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.3091311932
Directory /workspace/20.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/20.usbdev_av_buffer.1562532804
Short name T2041
Test name
Test status
Simulation time 151816008 ps
CPU time 0.88 seconds
Started Aug 11 07:12:16 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207556 kb
Host smart-c026b816-969e-438f-bf50-6e5af3ec3eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15625
32804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1562532804
Directory /workspace/20.usbdev_av_buffer/latest


Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2151969297
Short name T676
Test name
Test status
Simulation time 141337308 ps
CPU time 0.92 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207456 kb
Host smart-8e9124f9-dddf-40c3-8e21-e9f94c39cf00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21519
69297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2151969297
Directory /workspace/20.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2304552173
Short name T3286
Test name
Test status
Simulation time 381347791 ps
CPU time 1.39 seconds
Started Aug 11 07:12:16 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207552 kb
Host smart-8c3b81cb-6d2a-4fa0-80e9-f9e7cd31b4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23045
52173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2304552173
Directory /workspace/20.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1463132919
Short name T3392
Test name
Test status
Simulation time 540576952 ps
CPU time 1.49 seconds
Started Aug 11 07:12:15 PM PDT 24
Finished Aug 11 07:12:17 PM PDT 24
Peak memory 207536 kb
Host smart-5aef2283-78ff-4762-a314-b6dea0743759
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1463132919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1463132919
Directory /workspace/20.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/20.usbdev_device_timeout.2759833965
Short name T2911
Test name
Test status
Simulation time 1087725126 ps
CPU time 9.26 seconds
Started Aug 11 07:12:20 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207752 kb
Host smart-df217d94-be46-40ba-8a07-2f1be2a501af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759833965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.2759833965
Directory /workspace/20.usbdev_device_timeout/latest


Test location /workspace/coverage/default/20.usbdev_disable_endpoint.701945093
Short name T3555
Test name
Test status
Simulation time 780298421 ps
CPU time 1.95 seconds
Started Aug 11 07:12:21 PM PDT 24
Finished Aug 11 07:12:23 PM PDT 24
Peak memory 207500 kb
Host smart-df92a430-14f1-403f-8d8e-996ff564b564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70194
5093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.701945093
Directory /workspace/20.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/20.usbdev_disconnected.2054756694
Short name T40
Test name
Test status
Simulation time 149476965 ps
CPU time 0.88 seconds
Started Aug 11 07:12:22 PM PDT 24
Finished Aug 11 07:12:23 PM PDT 24
Peak memory 207516 kb
Host smart-1f0c2f43-aada-40ac-9d4b-e302eecc2720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20547
56694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2054756694
Directory /workspace/20.usbdev_disconnected/latest


Test location /workspace/coverage/default/20.usbdev_enable.1938338852
Short name T3409
Test name
Test status
Simulation time 30800712 ps
CPU time 0.72 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207708 kb
Host smart-42c5c552-4381-4a73-87c2-3be76e7635a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19383
38852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1938338852
Directory /workspace/20.usbdev_enable/latest


Test location /workspace/coverage/default/20.usbdev_endpoint_access.3909388275
Short name T3158
Test name
Test status
Simulation time 893287463 ps
CPU time 2.47 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:21 PM PDT 24
Peak memory 207724 kb
Host smart-e7f9873f-ebb1-43cb-886e-b7d90600a3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39093
88275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3909388275
Directory /workspace/20.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/20.usbdev_endpoint_types.671408675
Short name T466
Test name
Test status
Simulation time 533819303 ps
CPU time 1.53 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207512 kb
Host smart-704339ac-097b-46be-b5fe-775a528f5603
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=671408675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.671408675
Directory /workspace/20.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/20.usbdev_fifo_rst.3366646257
Short name T3406
Test name
Test status
Simulation time 405591565 ps
CPU time 2.8 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207692 kb
Host smart-c7ccd48d-58fe-428e-8088-7e19f8d972da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33666
46257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3366646257
Directory /workspace/20.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/20.usbdev_in_iso.284012617
Short name T36
Test name
Test status
Simulation time 296599787 ps
CPU time 1.4 seconds
Started Aug 11 07:12:20 PM PDT 24
Finished Aug 11 07:12:21 PM PDT 24
Peak memory 216928 kb
Host smart-7e7359b2-2849-4ce1-9c8d-934a8d95e648
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=284012617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.284012617
Directory /workspace/20.usbdev_in_iso/latest


Test location /workspace/coverage/default/20.usbdev_in_stall.836035515
Short name T1377
Test name
Test status
Simulation time 151482246 ps
CPU time 0.82 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 207444 kb
Host smart-f19e5183-822d-48bd-a2f1-1c8bf4dbea95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83603
5515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.836035515
Directory /workspace/20.usbdev_in_stall/latest


Test location /workspace/coverage/default/20.usbdev_in_trans.1050938726
Short name T1577
Test name
Test status
Simulation time 232300913 ps
CPU time 1.05 seconds
Started Aug 11 07:12:20 PM PDT 24
Finished Aug 11 07:12:21 PM PDT 24
Peak memory 207552 kb
Host smart-70caab90-4e7d-4e46-9620-e9a973e214fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10509
38726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1050938726
Directory /workspace/20.usbdev_in_trans/latest


Test location /workspace/coverage/default/20.usbdev_invalid_sync.646002448
Short name T2790
Test name
Test status
Simulation time 3114804698 ps
CPU time 24.1 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:43 PM PDT 24
Peak memory 218260 kb
Host smart-ea363f1c-6dd7-4c3c-a718-f1235805b63f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=646002448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.646002448
Directory /workspace/20.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/20.usbdev_iso_retraction.3926306785
Short name T815
Test name
Test status
Simulation time 9913278565 ps
CPU time 118.1 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:14:15 PM PDT 24
Peak memory 207796 kb
Host smart-c579195d-d256-4fb4-8a0f-7250288ba908
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3926306785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.3926306785
Directory /workspace/20.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/20.usbdev_link_in_err.1389234232
Short name T990
Test name
Test status
Simulation time 265741788 ps
CPU time 1.05 seconds
Started Aug 11 07:12:18 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207596 kb
Host smart-086b034f-635e-4f7f-8168-e4f611a34b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13892
34232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1389234232
Directory /workspace/20.usbdev_link_in_err/latest


Test location /workspace/coverage/default/20.usbdev_link_resume.3140541865
Short name T1440
Test name
Test status
Simulation time 8893315094 ps
CPU time 15.63 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:34 PM PDT 24
Peak memory 216036 kb
Host smart-7d33c2c1-81d5-41ac-a487-103bfa488ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31405
41865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3140541865
Directory /workspace/20.usbdev_link_resume/latest


Test location /workspace/coverage/default/20.usbdev_link_suspend.1436376449
Short name T1198
Test name
Test status
Simulation time 6377257524 ps
CPU time 7.61 seconds
Started Aug 11 07:12:18 PM PDT 24
Finished Aug 11 07:12:26 PM PDT 24
Peak memory 207808 kb
Host smart-fd9aa6f9-79e3-4b78-9596-ba0471a9c39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14363
76449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1436376449
Directory /workspace/20.usbdev_link_suspend/latest


Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.1504595107
Short name T2462
Test name
Test status
Simulation time 3034373510 ps
CPU time 29.52 seconds
Started Aug 11 07:12:21 PM PDT 24
Finished Aug 11 07:12:51 PM PDT 24
Peak memory 224216 kb
Host smart-3342cae1-81f3-49c0-83bd-e1632f7eb885
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1504595107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.1504595107
Directory /workspace/20.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2717100554
Short name T1211
Test name
Test status
Simulation time 3993935842 ps
CPU time 29.93 seconds
Started Aug 11 07:12:18 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 216096 kb
Host smart-6427d1ef-7a74-4c4b-96ea-4be7e6cc6111
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2717100554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2717100554
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.392213567
Short name T2830
Test name
Test status
Simulation time 231481043 ps
CPU time 0.99 seconds
Started Aug 11 07:12:20 PM PDT 24
Finished Aug 11 07:12:21 PM PDT 24
Peak memory 207544 kb
Host smart-b6007bb3-18e5-45c3-924c-f8f9614d4c5d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=392213567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.392213567
Directory /workspace/20.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3214825519
Short name T1015
Test name
Test status
Simulation time 200193583 ps
CPU time 0.94 seconds
Started Aug 11 07:12:17 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207480 kb
Host smart-38ca44ca-9d19-427a-9736-86f831fa53ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32148
25519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3214825519
Directory /workspace/20.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.2910006727
Short name T1799
Test name
Test status
Simulation time 2644473899 ps
CPU time 77.19 seconds
Started Aug 11 07:12:18 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 224256 kb
Host smart-5d7c3f1f-97f3-4bf8-bfd4-7021811163a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29100
06727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.2910006727
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2236484658
Short name T740
Test name
Test status
Simulation time 4326713859 ps
CPU time 127.68 seconds
Started Aug 11 07:12:18 PM PDT 24
Finished Aug 11 07:14:26 PM PDT 24
Peak memory 217536 kb
Host smart-acb812e7-d513-4c1c-987f-b5588255ac30
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2236484658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2236484658
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1060812121
Short name T1399
Test name
Test status
Simulation time 215760365 ps
CPU time 0.94 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207544 kb
Host smart-6828876d-e5f2-4f40-adc5-24e5bb19d266
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1060812121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1060812121
Directory /workspace/20.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2416331966
Short name T686
Test name
Test status
Simulation time 152254802 ps
CPU time 0.87 seconds
Started Aug 11 07:12:18 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207480 kb
Host smart-44b00cfd-5d23-41e6-892f-9559d3e62990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24163
31966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2416331966
Directory /workspace/20.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_nak_trans.3630386529
Short name T149
Test name
Test status
Simulation time 258731962 ps
CPU time 0.99 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:21 PM PDT 24
Peak memory 207524 kb
Host smart-4987ff03-d518-43f7-a32c-192a65d1ac84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303
86529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3630386529
Directory /workspace/20.usbdev_nak_trans/latest


Test location /workspace/coverage/default/20.usbdev_out_iso.2302305169
Short name T968
Test name
Test status
Simulation time 227146854 ps
CPU time 0.99 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207568 kb
Host smart-e48897d3-787c-4f28-8aa6-d45e0daaf0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23023
05169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2302305169
Directory /workspace/20.usbdev_out_iso/latest


Test location /workspace/coverage/default/20.usbdev_out_stall.1951489066
Short name T1285
Test name
Test status
Simulation time 146667445 ps
CPU time 0.8 seconds
Started Aug 11 07:12:20 PM PDT 24
Finished Aug 11 07:12:21 PM PDT 24
Peak memory 207536 kb
Host smart-2cc60daa-ed1c-4822-98d1-eb14e5759d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19514
89066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1951489066
Directory /workspace/20.usbdev_out_stall/latest


Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2580921263
Short name T2382
Test name
Test status
Simulation time 163895757 ps
CPU time 0.87 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207548 kb
Host smart-42b78c90-cf6d-4a9b-975a-448f6fbf3e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25809
21263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2580921263
Directory /workspace/20.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/20.usbdev_pending_in_trans.343989084
Short name T2023
Test name
Test status
Simulation time 158363304 ps
CPU time 0.96 seconds
Started Aug 11 07:12:22 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207524 kb
Host smart-2f6ab242-fab8-4552-9faa-8d31f35325fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34398
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.343989084
Directory /workspace/20.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1363800068
Short name T1836
Test name
Test status
Simulation time 231804496 ps
CPU time 1.03 seconds
Started Aug 11 07:12:21 PM PDT 24
Finished Aug 11 07:12:22 PM PDT 24
Peak memory 207520 kb
Host smart-940d33d5-c29f-401a-a150-10d4059cb36d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1363800068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1363800068
Directory /workspace/20.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2606473504
Short name T1859
Test name
Test status
Simulation time 147248394 ps
CPU time 0.8 seconds
Started Aug 11 07:12:23 PM PDT 24
Finished Aug 11 07:12:24 PM PDT 24
Peak memory 207496 kb
Host smart-a7494229-0b29-4a6e-86a6-7d9ee7693f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26064
73504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2606473504
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2521958237
Short name T3040
Test name
Test status
Simulation time 92655732 ps
CPU time 0.75 seconds
Started Aug 11 07:12:21 PM PDT 24
Finished Aug 11 07:12:22 PM PDT 24
Peak memory 207496 kb
Host smart-3e01fd43-115a-4d9e-b4f5-4b7691355ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25219
58237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2521958237
Directory /workspace/20.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3211603362
Short name T1843
Test name
Test status
Simulation time 18608083123 ps
CPU time 46.86 seconds
Started Aug 11 07:12:22 PM PDT 24
Finished Aug 11 07:13:09 PM PDT 24
Peak memory 216020 kb
Host smart-2fc74e46-ae4d-4d5c-8445-3aa7aac69063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32116
03362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3211603362
Directory /workspace/20.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/20.usbdev_pkt_received.3269885354
Short name T1113
Test name
Test status
Simulation time 155809020 ps
CPU time 0.95 seconds
Started Aug 11 07:12:20 PM PDT 24
Finished Aug 11 07:12:22 PM PDT 24
Peak memory 207524 kb
Host smart-3855b57f-5c48-4495-b13e-fc9b0f50bde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32698
85354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3269885354
Directory /workspace/20.usbdev_pkt_received/latest


Test location /workspace/coverage/default/20.usbdev_pkt_sent.2122819999
Short name T3031
Test name
Test status
Simulation time 246455217 ps
CPU time 1.02 seconds
Started Aug 11 07:12:21 PM PDT 24
Finished Aug 11 07:12:23 PM PDT 24
Peak memory 207492 kb
Host smart-6f47267d-daa2-496a-8ecd-32f3930eaa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21228
19999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2122819999
Directory /workspace/20.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.4287951790
Short name T903
Test name
Test status
Simulation time 311549293 ps
CPU time 1.02 seconds
Started Aug 11 07:12:18 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207576 kb
Host smart-fc816f2b-2069-4262-a324-4637686e5b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42879
51790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.4287951790
Directory /workspace/20.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1334534585
Short name T606
Test name
Test status
Simulation time 160490785 ps
CPU time 0.89 seconds
Started Aug 11 07:12:20 PM PDT 24
Finished Aug 11 07:12:21 PM PDT 24
Peak memory 207544 kb
Host smart-48a0c4fd-cb6b-4b14-8643-ef260ebebaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13345
34585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1334534585
Directory /workspace/20.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3123330700
Short name T907
Test name
Test status
Simulation time 138380269 ps
CPU time 0.86 seconds
Started Aug 11 07:12:22 PM PDT 24
Finished Aug 11 07:12:23 PM PDT 24
Peak memory 207476 kb
Host smart-ead4fdba-f224-49b2-955a-f0e8833ef157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31233
30700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3123330700
Directory /workspace/20.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/20.usbdev_rx_full.1373288384
Short name T2247
Test name
Test status
Simulation time 421092451 ps
CPU time 1.4 seconds
Started Aug 11 07:12:19 PM PDT 24
Finished Aug 11 07:12:20 PM PDT 24
Peak memory 207744 kb
Host smart-1b5c5451-58fb-4fe9-bf56-908c2562ea62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13732
88384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.1373288384
Directory /workspace/20.usbdev_rx_full/latest


Test location /workspace/coverage/default/20.usbdev_setup_stage.3333724600
Short name T2480
Test name
Test status
Simulation time 153522580 ps
CPU time 0.88 seconds
Started Aug 11 07:12:20 PM PDT 24
Finished Aug 11 07:12:21 PM PDT 24
Peak memory 206860 kb
Host smart-ef99445b-a87a-4efb-8199-600b1903c82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33337
24600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3333724600
Directory /workspace/20.usbdev_setup_stage/latest


Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2421614751
Short name T1058
Test name
Test status
Simulation time 142319522 ps
CPU time 0.87 seconds
Started Aug 11 07:12:30 PM PDT 24
Finished Aug 11 07:12:31 PM PDT 24
Peak memory 207548 kb
Host smart-95333194-af1c-4612-9c10-5238986ac6d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
14751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2421614751
Directory /workspace/20.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/20.usbdev_smoke.3765652563
Short name T1987
Test name
Test status
Simulation time 257784623 ps
CPU time 1 seconds
Started Aug 11 07:12:26 PM PDT 24
Finished Aug 11 07:12:27 PM PDT 24
Peak memory 207484 kb
Host smart-0a88f432-eaaa-4c22-ab58-c1a2cd9db197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37656
52563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3765652563
Directory /workspace/20.usbdev_smoke/latest


Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1011943015
Short name T1613
Test name
Test status
Simulation time 3119898595 ps
CPU time 23.71 seconds
Started Aug 11 07:12:25 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 217980 kb
Host smart-33ae37b6-de32-4dda-8004-1120b4cd7eb9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1011943015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1011943015
Directory /workspace/20.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1980542310
Short name T1022
Test name
Test status
Simulation time 183147174 ps
CPU time 0.87 seconds
Started Aug 11 07:12:24 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 207484 kb
Host smart-ee12137b-40b1-402a-ab83-06b20842bb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19805
42310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1980542310
Directory /workspace/20.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/20.usbdev_stall_trans.2513218641
Short name T1061
Test name
Test status
Simulation time 180479469 ps
CPU time 0.91 seconds
Started Aug 11 07:12:24 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 207520 kb
Host smart-d0d12cd4-c1ba-4f0d-9fea-94b384311407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25132
18641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2513218641
Directory /workspace/20.usbdev_stall_trans/latest


Test location /workspace/coverage/default/20.usbdev_stream_len_max.2683143253
Short name T2789
Test name
Test status
Simulation time 1387274596 ps
CPU time 3.63 seconds
Started Aug 11 07:12:41 PM PDT 24
Finished Aug 11 07:12:45 PM PDT 24
Peak memory 207720 kb
Host smart-146b1510-8de9-4375-a848-110dbc22d95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26831
43253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2683143253
Directory /workspace/20.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/20.usbdev_streaming_out.1019024211
Short name T2250
Test name
Test status
Simulation time 2080512322 ps
CPU time 16.16 seconds
Started Aug 11 07:12:25 PM PDT 24
Finished Aug 11 07:12:41 PM PDT 24
Peak memory 217596 kb
Host smart-10170633-de12-43dc-ae4c-ffda257fb25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10190
24211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.1019024211
Directory /workspace/20.usbdev_streaming_out/latest


Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.767133878
Short name T1367
Test name
Test status
Simulation time 912081021 ps
CPU time 18.82 seconds
Started Aug 11 07:12:21 PM PDT 24
Finished Aug 11 07:12:40 PM PDT 24
Peak memory 207748 kb
Host smart-8ea28256-d25a-42d7-9f63-f0e598ad9ca1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767133878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_host
_handshake.767133878
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/20.usbdev_tx_rx_disruption.520302393
Short name T204
Test name
Test status
Simulation time 493033163 ps
CPU time 1.55 seconds
Started Aug 11 07:12:29 PM PDT 24
Finished Aug 11 07:12:31 PM PDT 24
Peak memory 207600 kb
Host smart-16b3b9d8-5a44-4101-aa88-46cef3a32b6e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520302393 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.usbdev_tx_rx_disruption.520302393
Directory /workspace/20.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/200.usbdev_tx_rx_disruption.4040633463
Short name T1685
Test name
Test status
Simulation time 634023460 ps
CPU time 1.67 seconds
Started Aug 11 07:17:26 PM PDT 24
Finished Aug 11 07:17:28 PM PDT 24
Peak memory 207572 kb
Host smart-6ade2fc5-9892-4875-afc4-bbf7db2ea4d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040633463 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.usbdev_tx_rx_disruption.4040633463
Directory /workspace/200.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/201.usbdev_tx_rx_disruption.198351683
Short name T1207
Test name
Test status
Simulation time 486903723 ps
CPU time 1.59 seconds
Started Aug 11 07:17:30 PM PDT 24
Finished Aug 11 07:17:32 PM PDT 24
Peak memory 207564 kb
Host smart-6882ba12-a731-456e-a80f-3b4b5f20f841
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198351683 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 201.usbdev_tx_rx_disruption.198351683
Directory /workspace/201.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/202.usbdev_tx_rx_disruption.4131255022
Short name T174
Test name
Test status
Simulation time 570000562 ps
CPU time 1.49 seconds
Started Aug 11 07:17:38 PM PDT 24
Finished Aug 11 07:17:39 PM PDT 24
Peak memory 207484 kb
Host smart-33366882-4eac-49df-b33e-a3cf62c21115
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131255022 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.usbdev_tx_rx_disruption.4131255022
Directory /workspace/202.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/203.usbdev_tx_rx_disruption.2395439573
Short name T2673
Test name
Test status
Simulation time 464145146 ps
CPU time 1.41 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:35 PM PDT 24
Peak memory 207524 kb
Host smart-c443f11d-d398-4180-ac36-6a4d01088483
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395439573 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.usbdev_tx_rx_disruption.2395439573
Directory /workspace/203.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/204.usbdev_tx_rx_disruption.2370973760
Short name T3217
Test name
Test status
Simulation time 488864865 ps
CPU time 1.53 seconds
Started Aug 11 07:17:20 PM PDT 24
Finished Aug 11 07:17:22 PM PDT 24
Peak memory 207552 kb
Host smart-4424abcf-ce9b-4ff1-9734-e47a2f7f833a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370973760 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.usbdev_tx_rx_disruption.2370973760
Directory /workspace/204.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/205.usbdev_tx_rx_disruption.3452649680
Short name T827
Test name
Test status
Simulation time 583399910 ps
CPU time 1.58 seconds
Started Aug 11 07:17:43 PM PDT 24
Finished Aug 11 07:17:45 PM PDT 24
Peak memory 207516 kb
Host smart-6a3ec931-ba43-45b5-a393-b7b3f1ceb426
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452649680 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.usbdev_tx_rx_disruption.3452649680
Directory /workspace/205.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/206.usbdev_tx_rx_disruption.1457755444
Short name T1775
Test name
Test status
Simulation time 592334639 ps
CPU time 1.6 seconds
Started Aug 11 07:17:26 PM PDT 24
Finished Aug 11 07:17:27 PM PDT 24
Peak memory 207576 kb
Host smart-be394bc8-1155-4308-94ab-be2d494c73ea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457755444 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.usbdev_tx_rx_disruption.1457755444
Directory /workspace/206.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/207.usbdev_tx_rx_disruption.3978114578
Short name T1393
Test name
Test status
Simulation time 463450945 ps
CPU time 1.41 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207568 kb
Host smart-7d9a50fb-bd52-483c-a123-dc8755221720
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978114578 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.usbdev_tx_rx_disruption.3978114578
Directory /workspace/207.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/208.usbdev_tx_rx_disruption.1689835701
Short name T209
Test name
Test status
Simulation time 486704261 ps
CPU time 1.48 seconds
Started Aug 11 07:17:29 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207548 kb
Host smart-fbddbfd9-bcf2-48f3-b6c0-a5b0be679c7a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689835701 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.usbdev_tx_rx_disruption.1689835701
Directory /workspace/208.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/209.usbdev_tx_rx_disruption.1189695186
Short name T3375
Test name
Test status
Simulation time 518024465 ps
CPU time 1.55 seconds
Started Aug 11 07:17:29 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 207500 kb
Host smart-3db13fdd-07f0-4304-a8ca-cf1b25eb81b6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189695186 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.usbdev_tx_rx_disruption.1189695186
Directory /workspace/209.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/21.usbdev_alert_test.2643723599
Short name T3288
Test name
Test status
Simulation time 52726371 ps
CPU time 0.71 seconds
Started Aug 11 07:12:31 PM PDT 24
Finished Aug 11 07:12:32 PM PDT 24
Peak memory 207612 kb
Host smart-da23eb15-a817-47e9-a841-61208f05a251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2643723599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.2643723599
Directory /workspace/21.usbdev_alert_test/latest


Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.112739155
Short name T2763
Test name
Test status
Simulation time 10512763189 ps
CPU time 14.67 seconds
Started Aug 11 07:12:26 PM PDT 24
Finished Aug 11 07:12:41 PM PDT 24
Peak memory 207856 kb
Host smart-77cddf89-4933-492b-ac4e-6e164b38db2d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112739155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ao
n_wake_disconnect.112739155
Directory /workspace/21.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3357086637
Short name T3473
Test name
Test status
Simulation time 14487285555 ps
CPU time 18.2 seconds
Started Aug 11 07:12:27 PM PDT 24
Finished Aug 11 07:12:45 PM PDT 24
Peak memory 215936 kb
Host smart-1a641d9e-3f07-4744-a3dc-20608f31fa45
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357086637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3357086637
Directory /workspace/21.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1710345940
Short name T3550
Test name
Test status
Simulation time 24358276534 ps
CPU time 29.76 seconds
Started Aug 11 07:12:29 PM PDT 24
Finished Aug 11 07:12:59 PM PDT 24
Peak memory 215976 kb
Host smart-b8655da0-4bd0-42b6-8051-0c99f28f8ddf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710345940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.1710345940
Directory /workspace/21.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/21.usbdev_av_buffer.2247409258
Short name T626
Test name
Test status
Simulation time 204159601 ps
CPU time 0.89 seconds
Started Aug 11 07:12:27 PM PDT 24
Finished Aug 11 07:12:28 PM PDT 24
Peak memory 207520 kb
Host smart-faaa1b6e-5e6a-491d-857b-b7ec8895b83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22474
09258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2247409258
Directory /workspace/21.usbdev_av_buffer/latest


Test location /workspace/coverage/default/21.usbdev_bitstuff_err.1717671369
Short name T1554
Test name
Test status
Simulation time 177029105 ps
CPU time 0.83 seconds
Started Aug 11 07:12:25 PM PDT 24
Finished Aug 11 07:12:26 PM PDT 24
Peak memory 207500 kb
Host smart-2b014f0a-e8a3-4911-ad84-3a3baf3d0d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17176
71369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1717671369
Directory /workspace/21.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.936114747
Short name T1692
Test name
Test status
Simulation time 250275398 ps
CPU time 1.13 seconds
Started Aug 11 07:12:24 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 207524 kb
Host smart-f7142657-93f3-4aae-82ea-557ca4b32b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93611
4747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.936114747
Directory /workspace/21.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.4088513754
Short name T2352
Test name
Test status
Simulation time 329446674 ps
CPU time 1.15 seconds
Started Aug 11 07:12:26 PM PDT 24
Finished Aug 11 07:12:27 PM PDT 24
Peak memory 207576 kb
Host smart-8efdfdd3-a17e-4794-8e97-569240f328f1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4088513754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.4088513754
Directory /workspace/21.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/21.usbdev_device_address.2033174650
Short name T1290
Test name
Test status
Simulation time 39591398688 ps
CPU time 68.42 seconds
Started Aug 11 07:12:22 PM PDT 24
Finished Aug 11 07:13:31 PM PDT 24
Peak memory 207848 kb
Host smart-cf86e8a7-2769-4341-9c14-3b757e929d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20331
74650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2033174650
Directory /workspace/21.usbdev_device_address/latest


Test location /workspace/coverage/default/21.usbdev_device_timeout.1431614018
Short name T2762
Test name
Test status
Simulation time 2075534941 ps
CPU time 53.3 seconds
Started Aug 11 07:12:27 PM PDT 24
Finished Aug 11 07:13:20 PM PDT 24
Peak memory 207664 kb
Host smart-1d0da696-6e2a-452c-96b8-02bfca649f87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431614018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.1431614018
Directory /workspace/21.usbdev_device_timeout/latest


Test location /workspace/coverage/default/21.usbdev_disable_endpoint.1081867217
Short name T2328
Test name
Test status
Simulation time 1014880314 ps
CPU time 2.18 seconds
Started Aug 11 07:12:26 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207512 kb
Host smart-6ed85e91-f13e-4e86-83bc-cd31f7e81c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10818
67217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.1081867217
Directory /workspace/21.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/21.usbdev_disconnected.1292835749
Short name T3364
Test name
Test status
Simulation time 143095901 ps
CPU time 0.8 seconds
Started Aug 11 07:12:25 PM PDT 24
Finished Aug 11 07:12:26 PM PDT 24
Peak memory 207516 kb
Host smart-85b53403-ff0c-4e98-8246-a48e2b1d732e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
35749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1292835749
Directory /workspace/21.usbdev_disconnected/latest


Test location /workspace/coverage/default/21.usbdev_enable.923806288
Short name T1413
Test name
Test status
Simulation time 48329857 ps
CPU time 0.69 seconds
Started Aug 11 07:12:38 PM PDT 24
Finished Aug 11 07:12:39 PM PDT 24
Peak memory 207540 kb
Host smart-72d713db-2fbb-4720-b156-b967b850be19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92380
6288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.923806288
Directory /workspace/21.usbdev_enable/latest


Test location /workspace/coverage/default/21.usbdev_endpoint_access.459119394
Short name T982
Test name
Test status
Simulation time 922923151 ps
CPU time 2.29 seconds
Started Aug 11 07:12:25 PM PDT 24
Finished Aug 11 07:12:27 PM PDT 24
Peak memory 207704 kb
Host smart-e3c8f02e-25db-4d93-a6da-ef8e0a8ee1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45911
9394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.459119394
Directory /workspace/21.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/21.usbdev_fifo_rst.807831180
Short name T2667
Test name
Test status
Simulation time 261306562 ps
CPU time 1.73 seconds
Started Aug 11 07:12:27 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207660 kb
Host smart-a79368b7-22d9-4970-9a35-8b77de610c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80783
1180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.807831180
Directory /workspace/21.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/21.usbdev_in_iso.659772916
Short name T3565
Test name
Test status
Simulation time 230018598 ps
CPU time 1.15 seconds
Started Aug 11 07:12:28 PM PDT 24
Finished Aug 11 07:12:30 PM PDT 24
Peak memory 215892 kb
Host smart-a0c3db7f-6c9a-4456-9c73-9dd94f935acd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=659772916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.659772916
Directory /workspace/21.usbdev_in_iso/latest


Test location /workspace/coverage/default/21.usbdev_in_stall.1646774506
Short name T2505
Test name
Test status
Simulation time 143392730 ps
CPU time 0.84 seconds
Started Aug 11 07:12:24 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 207524 kb
Host smart-9c29238e-4281-495f-b6cb-366bbfd219d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16467
74506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1646774506
Directory /workspace/21.usbdev_in_stall/latest


Test location /workspace/coverage/default/21.usbdev_in_trans.1020775773
Short name T2308
Test name
Test status
Simulation time 177535534 ps
CPU time 0.92 seconds
Started Aug 11 07:12:25 PM PDT 24
Finished Aug 11 07:12:26 PM PDT 24
Peak memory 207580 kb
Host smart-fe51f78e-79f9-4ce7-9423-d0026534fa92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10207
75773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1020775773
Directory /workspace/21.usbdev_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_invalid_sync.239325623
Short name T1228
Test name
Test status
Simulation time 4227809560 ps
CPU time 118.14 seconds
Started Aug 11 07:12:38 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 224276 kb
Host smart-2fdd59d7-7dd3-40e5-afa4-168d0b5c65e1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=239325623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.239325623
Directory /workspace/21.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/21.usbdev_iso_retraction.3445421920
Short name T2045
Test name
Test status
Simulation time 5235511425 ps
CPU time 65.96 seconds
Started Aug 11 07:12:25 PM PDT 24
Finished Aug 11 07:13:31 PM PDT 24
Peak memory 207736 kb
Host smart-0e9bd2e2-51f9-4751-b47b-07c858ffa94c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3445421920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.3445421920
Directory /workspace/21.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/21.usbdev_link_in_err.3175217627
Short name T2503
Test name
Test status
Simulation time 202158307 ps
CPU time 0.92 seconds
Started Aug 11 07:12:29 PM PDT 24
Finished Aug 11 07:12:30 PM PDT 24
Peak memory 207600 kb
Host smart-f8be4576-2be5-4ab8-b44a-5d8a7fefcf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31752
17627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3175217627
Directory /workspace/21.usbdev_link_in_err/latest


Test location /workspace/coverage/default/21.usbdev_link_resume.1647249220
Short name T2106
Test name
Test status
Simulation time 26827703799 ps
CPU time 40.7 seconds
Started Aug 11 07:12:34 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 216196 kb
Host smart-299f5bf5-1124-48e6-8dfd-519bfb4c8eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16472
49220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1647249220
Directory /workspace/21.usbdev_link_resume/latest


Test location /workspace/coverage/default/21.usbdev_link_suspend.3484870412
Short name T1532
Test name
Test status
Simulation time 9519711481 ps
CPU time 14.92 seconds
Started Aug 11 07:12:28 PM PDT 24
Finished Aug 11 07:12:43 PM PDT 24
Peak memory 207804 kb
Host smart-cea7a6da-daec-44d3-8358-3a930df43798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34848
70412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3484870412
Directory /workspace/21.usbdev_link_suspend/latest


Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.2688400588
Short name T2069
Test name
Test status
Simulation time 4861374652 ps
CPU time 134.58 seconds
Started Aug 11 07:12:29 PM PDT 24
Finished Aug 11 07:14:44 PM PDT 24
Peak memory 218620 kb
Host smart-cd0b4354-21f0-48eb-97dd-56340207a8ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2688400588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.2688400588
Directory /workspace/21.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.811737120
Short name T1130
Test name
Test status
Simulation time 2586628309 ps
CPU time 25.83 seconds
Started Aug 11 07:12:25 PM PDT 24
Finished Aug 11 07:12:51 PM PDT 24
Peak memory 216060 kb
Host smart-ba98a3cf-cb82-4b4b-b88e-16176a069e89
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=811737120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.811737120
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2687420659
Short name T1047
Test name
Test status
Simulation time 282989458 ps
CPU time 1.1 seconds
Started Aug 11 07:12:24 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 207568 kb
Host smart-76baf233-15ed-4f33-9576-910422bd309d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2687420659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2687420659
Directory /workspace/21.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.625062619
Short name T746
Test name
Test status
Simulation time 192414904 ps
CPU time 0.92 seconds
Started Aug 11 07:12:24 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 207572 kb
Host smart-94afed5c-d367-49d0-bbe1-907dc32ec48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62506
2619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.625062619
Directory /workspace/21.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.342109962
Short name T1243
Test name
Test status
Simulation time 2006861298 ps
CPU time 15.47 seconds
Started Aug 11 07:12:31 PM PDT 24
Finished Aug 11 07:12:47 PM PDT 24
Peak memory 224176 kb
Host smart-4bb8b9b1-0397-4573-9609-01e5318f7deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34210
9962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.342109962
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1337705273
Short name T2610
Test name
Test status
Simulation time 2559855329 ps
CPU time 73.03 seconds
Started Aug 11 07:12:27 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 217468 kb
Host smart-5fecde4d-2ca6-4413-b6d4-480ded2d8c74
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1337705273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1337705273
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.143173766
Short name T1038
Test name
Test status
Simulation time 151596257 ps
CPU time 0.85 seconds
Started Aug 11 07:12:26 PM PDT 24
Finished Aug 11 07:12:27 PM PDT 24
Peak memory 207520 kb
Host smart-de64872a-b7b6-4631-a5e0-1acff321845d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=143173766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.143173766
Directory /workspace/21.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2191076512
Short name T2166
Test name
Test status
Simulation time 146017886 ps
CPU time 0.85 seconds
Started Aug 11 07:12:28 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207572 kb
Host smart-7d8a255e-25e8-43cc-8bba-96b52e081ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21910
76512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2191076512
Directory /workspace/21.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_nak_trans.3004920528
Short name T157
Test name
Test status
Simulation time 203049328 ps
CPU time 0.94 seconds
Started Aug 11 07:12:29 PM PDT 24
Finished Aug 11 07:12:30 PM PDT 24
Peak memory 207520 kb
Host smart-3d02f606-1e50-4d06-9f50-b0a3cdf38297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30049
20528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3004920528
Directory /workspace/21.usbdev_nak_trans/latest


Test location /workspace/coverage/default/21.usbdev_out_iso.4152076383
Short name T2867
Test name
Test status
Simulation time 183770834 ps
CPU time 0.91 seconds
Started Aug 11 07:12:28 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207524 kb
Host smart-87a51838-2e72-4f5f-a39a-5677311ef3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41520
76383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.4152076383
Directory /workspace/21.usbdev_out_iso/latest


Test location /workspace/coverage/default/21.usbdev_out_stall.3184097971
Short name T1611
Test name
Test status
Simulation time 185600643 ps
CPU time 0.88 seconds
Started Aug 11 07:12:29 PM PDT 24
Finished Aug 11 07:12:30 PM PDT 24
Peak memory 207516 kb
Host smart-e9ccc5ff-526e-4216-af3f-dd19646b3c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31840
97971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3184097971
Directory /workspace/21.usbdev_out_stall/latest


Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2330831456
Short name T3559
Test name
Test status
Simulation time 168387692 ps
CPU time 0.89 seconds
Started Aug 11 07:12:43 PM PDT 24
Finished Aug 11 07:12:44 PM PDT 24
Peak memory 207568 kb
Host smart-e974bc0b-81a6-4e37-b69a-1f20983bfe89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23308
31456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2330831456
Directory /workspace/21.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1765070866
Short name T1817
Test name
Test status
Simulation time 156521254 ps
CPU time 0.85 seconds
Started Aug 11 07:12:29 PM PDT 24
Finished Aug 11 07:12:30 PM PDT 24
Peak memory 207520 kb
Host smart-be2a089f-18f9-405a-955a-1002170f2c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17650
70866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1765070866
Directory /workspace/21.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3630406192
Short name T1860
Test name
Test status
Simulation time 245083423 ps
CPU time 0.98 seconds
Started Aug 11 07:12:39 PM PDT 24
Finished Aug 11 07:12:41 PM PDT 24
Peak memory 207592 kb
Host smart-9bf1f67b-d645-4805-b04d-155a14532773
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3630406192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3630406192
Directory /workspace/21.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3806677171
Short name T1715
Test name
Test status
Simulation time 159556984 ps
CPU time 0.87 seconds
Started Aug 11 07:12:25 PM PDT 24
Finished Aug 11 07:12:26 PM PDT 24
Peak memory 207536 kb
Host smart-2f8f0355-20b0-4b14-bd9e-f94b9f5d4fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066
77171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3806677171
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2877630459
Short name T2730
Test name
Test status
Simulation time 46800197 ps
CPU time 0.69 seconds
Started Aug 11 07:12:43 PM PDT 24
Finished Aug 11 07:12:44 PM PDT 24
Peak memory 207536 kb
Host smart-2771088c-0601-4408-aa90-7aab6291a631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
30459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2877630459
Directory /workspace/21.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2870121435
Short name T2265
Test name
Test status
Simulation time 7951917702 ps
CPU time 20.42 seconds
Started Aug 11 07:12:31 PM PDT 24
Finished Aug 11 07:12:52 PM PDT 24
Peak memory 215980 kb
Host smart-19719f65-c7d9-4fc3-8628-ac7c69c845f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28701
21435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2870121435
Directory /workspace/21.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/21.usbdev_pkt_received.2508427135
Short name T392
Test name
Test status
Simulation time 190983044 ps
CPU time 0.99 seconds
Started Aug 11 07:12:31 PM PDT 24
Finished Aug 11 07:12:32 PM PDT 24
Peak memory 207476 kb
Host smart-475b02e2-5eec-49c0-ad00-2e757e52a676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
27135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2508427135
Directory /workspace/21.usbdev_pkt_received/latest


Test location /workspace/coverage/default/21.usbdev_pkt_sent.4274276059
Short name T2113
Test name
Test status
Simulation time 242817651 ps
CPU time 1.07 seconds
Started Aug 11 07:12:34 PM PDT 24
Finished Aug 11 07:12:36 PM PDT 24
Peak memory 207544 kb
Host smart-d6a5018d-68cb-4ed8-bf32-9ca814824167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42742
76059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.4274276059
Directory /workspace/21.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.259958191
Short name T1032
Test name
Test status
Simulation time 179813689 ps
CPU time 0.92 seconds
Started Aug 11 07:12:30 PM PDT 24
Finished Aug 11 07:12:31 PM PDT 24
Peak memory 207548 kb
Host smart-313ed0e2-8c4a-4a03-8e3d-70353acb0d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25995
8191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.259958191
Directory /workspace/21.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.155566367
Short name T2791
Test name
Test status
Simulation time 185349230 ps
CPU time 0.91 seconds
Started Aug 11 07:12:40 PM PDT 24
Finished Aug 11 07:12:41 PM PDT 24
Peak memory 207516 kb
Host smart-2b6d8143-cc30-4893-b621-908011f2e10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15556
6367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.155566367
Directory /workspace/21.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2737238533
Short name T1195
Test name
Test status
Simulation time 207145718 ps
CPU time 0.94 seconds
Started Aug 11 07:12:28 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207476 kb
Host smart-8b6cf012-f7ac-4e21-80c6-f10e5e24447a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27372
38533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2737238533
Directory /workspace/21.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/21.usbdev_rx_full.1409219722
Short name T1302
Test name
Test status
Simulation time 323742744 ps
CPU time 1.15 seconds
Started Aug 11 07:12:38 PM PDT 24
Finished Aug 11 07:12:39 PM PDT 24
Peak memory 207568 kb
Host smart-aef0d639-5542-4bbd-a5c3-ce5bd4c9e0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14092
19722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.1409219722
Directory /workspace/21.usbdev_rx_full/latest


Test location /workspace/coverage/default/21.usbdev_setup_stage.2267367128
Short name T2413
Test name
Test status
Simulation time 163277227 ps
CPU time 0.87 seconds
Started Aug 11 07:12:30 PM PDT 24
Finished Aug 11 07:12:31 PM PDT 24
Peak memory 207524 kb
Host smart-b628f2f9-0950-4007-a159-95b2399c31aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22673
67128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2267367128
Directory /workspace/21.usbdev_setup_stage/latest


Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2273004330
Short name T2086
Test name
Test status
Simulation time 148679346 ps
CPU time 0.84 seconds
Started Aug 11 07:12:32 PM PDT 24
Finished Aug 11 07:12:33 PM PDT 24
Peak memory 207572 kb
Host smart-1b71942b-6f4a-4a83-a932-ae026c13c987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22730
04330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2273004330
Directory /workspace/21.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/21.usbdev_smoke.3355623830
Short name T3163
Test name
Test status
Simulation time 228740822 ps
CPU time 0.98 seconds
Started Aug 11 07:12:28 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207504 kb
Host smart-010c3788-38d0-4646-9f90-065d14591ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33556
23830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3355623830
Directory /workspace/21.usbdev_smoke/latest


Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1003979221
Short name T2267
Test name
Test status
Simulation time 2361767294 ps
CPU time 17.25 seconds
Started Aug 11 07:12:43 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 217996 kb
Host smart-89bd47d2-3374-4483-add3-fe22f8e66e3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1003979221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1003979221
Directory /workspace/21.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2931801820
Short name T2008
Test name
Test status
Simulation time 181019338 ps
CPU time 0.9 seconds
Started Aug 11 07:12:30 PM PDT 24
Finished Aug 11 07:12:31 PM PDT 24
Peak memory 207504 kb
Host smart-356b92a2-12ea-4f42-9f0c-a5b37999a7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
01820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2931801820
Directory /workspace/21.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/21.usbdev_stall_trans.28207566
Short name T1835
Test name
Test status
Simulation time 204924187 ps
CPU time 0.96 seconds
Started Aug 11 07:12:37 PM PDT 24
Finished Aug 11 07:12:38 PM PDT 24
Peak memory 207576 kb
Host smart-de35f979-3bf2-457c-866f-d715354fe1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.28207566
Directory /workspace/21.usbdev_stall_trans/latest


Test location /workspace/coverage/default/21.usbdev_stream_len_max.2070131666
Short name T1172
Test name
Test status
Simulation time 342623472 ps
CPU time 1.23 seconds
Started Aug 11 07:12:39 PM PDT 24
Finished Aug 11 07:12:41 PM PDT 24
Peak memory 207536 kb
Host smart-3ae8f795-fb52-4bcf-afed-608b2d891fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20701
31666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.2070131666
Directory /workspace/21.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/21.usbdev_streaming_out.2515992995
Short name T3297
Test name
Test status
Simulation time 2024918709 ps
CPU time 58.17 seconds
Started Aug 11 07:12:31 PM PDT 24
Finished Aug 11 07:13:29 PM PDT 24
Peak memory 217256 kb
Host smart-5e3e8383-53ca-4bc9-a6ee-5dffa94a1ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25159
92995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2515992995
Directory /workspace/21.usbdev_streaming_out/latest


Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.2784518942
Short name T2135
Test name
Test status
Simulation time 300349484 ps
CPU time 4.31 seconds
Started Aug 11 07:12:27 PM PDT 24
Finished Aug 11 07:12:32 PM PDT 24
Peak memory 207708 kb
Host smart-5e431aa4-581b-4608-8562-e41d00b26ca1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784518942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.2784518942
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/21.usbdev_tx_rx_disruption.2899085228
Short name T1714
Test name
Test status
Simulation time 573805838 ps
CPU time 1.56 seconds
Started Aug 11 07:12:29 PM PDT 24
Finished Aug 11 07:12:31 PM PDT 24
Peak memory 207572 kb
Host smart-04ff0a2d-763b-4753-9e20-950225bc81f0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899085228 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.usbdev_tx_rx_disruption.2899085228
Directory /workspace/21.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/210.usbdev_tx_rx_disruption.47997885
Short name T2997
Test name
Test status
Simulation time 577365965 ps
CPU time 1.53 seconds
Started Aug 11 07:17:25 PM PDT 24
Finished Aug 11 07:17:26 PM PDT 24
Peak memory 207540 kb
Host smart-b7b4bab2-830c-4915-8d38-a01e34075ea8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47997885 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 210.usbdev_tx_rx_disruption.47997885
Directory /workspace/210.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/211.usbdev_tx_rx_disruption.279656300
Short name T1309
Test name
Test status
Simulation time 605874074 ps
CPU time 1.68 seconds
Started Aug 11 07:17:35 PM PDT 24
Finished Aug 11 07:17:37 PM PDT 24
Peak memory 207572 kb
Host smart-cee277b0-94ca-4d3c-a9c5-186d3d85850d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279656300 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 211.usbdev_tx_rx_disruption.279656300
Directory /workspace/211.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/212.usbdev_tx_rx_disruption.494736624
Short name T944
Test name
Test status
Simulation time 675827614 ps
CPU time 1.81 seconds
Started Aug 11 07:17:30 PM PDT 24
Finished Aug 11 07:17:32 PM PDT 24
Peak memory 207536 kb
Host smart-57f594c5-1ac4-4017-971d-6fc7d6a22e40
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494736624 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 212.usbdev_tx_rx_disruption.494736624
Directory /workspace/212.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/213.usbdev_tx_rx_disruption.2487592041
Short name T1878
Test name
Test status
Simulation time 602939429 ps
CPU time 1.61 seconds
Started Aug 11 07:17:27 PM PDT 24
Finished Aug 11 07:17:29 PM PDT 24
Peak memory 207564 kb
Host smart-6c950214-a76a-4ca7-9858-1f426a5043c4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487592041 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.usbdev_tx_rx_disruption.2487592041
Directory /workspace/213.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/214.usbdev_tx_rx_disruption.781311092
Short name T197
Test name
Test status
Simulation time 465624565 ps
CPU time 1.46 seconds
Started Aug 11 07:17:36 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207520 kb
Host smart-bc7028c3-9126-4319-8dfb-434330cab9ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781311092 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 214.usbdev_tx_rx_disruption.781311092
Directory /workspace/214.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/215.usbdev_tx_rx_disruption.3337524811
Short name T3464
Test name
Test status
Simulation time 482753875 ps
CPU time 1.57 seconds
Started Aug 11 07:17:28 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207532 kb
Host smart-6185a9b6-d448-4898-bbef-25b8c4cec55d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337524811 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.usbdev_tx_rx_disruption.3337524811
Directory /workspace/215.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/216.usbdev_tx_rx_disruption.4176244495
Short name T2080
Test name
Test status
Simulation time 454017953 ps
CPU time 1.47 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:35 PM PDT 24
Peak memory 207552 kb
Host smart-2b1477b5-1457-42ed-9b5d-bad1566ea299
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176244495 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 216.usbdev_tx_rx_disruption.4176244495
Directory /workspace/216.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/217.usbdev_tx_rx_disruption.3255843054
Short name T1081
Test name
Test status
Simulation time 502977838 ps
CPU time 1.56 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:35 PM PDT 24
Peak memory 207556 kb
Host smart-d3e2dc86-de15-4d0f-8fdd-1e725648d123
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255843054 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.usbdev_tx_rx_disruption.3255843054
Directory /workspace/217.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/218.usbdev_tx_rx_disruption.1265148465
Short name T1968
Test name
Test status
Simulation time 476665429 ps
CPU time 1.48 seconds
Started Aug 11 07:17:30 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 207564 kb
Host smart-eecf64be-7e3b-42fd-80df-9d83c5eb6390
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265148465 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.usbdev_tx_rx_disruption.1265148465
Directory /workspace/218.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/219.usbdev_tx_rx_disruption.636085782
Short name T1806
Test name
Test status
Simulation time 644968020 ps
CPU time 1.7 seconds
Started Aug 11 07:17:41 PM PDT 24
Finished Aug 11 07:17:43 PM PDT 24
Peak memory 207556 kb
Host smart-0ed7070c-6a76-4179-a7a8-4359a8a3d764
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636085782 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 219.usbdev_tx_rx_disruption.636085782
Directory /workspace/219.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/22.usbdev_alert_test.83897427
Short name T1645
Test name
Test status
Simulation time 45829599 ps
CPU time 0.67 seconds
Started Aug 11 07:12:46 PM PDT 24
Finished Aug 11 07:12:47 PM PDT 24
Peak memory 207448 kb
Host smart-7c3e8bc3-7c83-4801-ae4e-8ad43cbc1893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=83897427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.83897427
Directory /workspace/22.usbdev_alert_test/latest


Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.634056691
Short name T2408
Test name
Test status
Simulation time 4065727372 ps
CPU time 6.82 seconds
Started Aug 11 07:12:30 PM PDT 24
Finished Aug 11 07:12:37 PM PDT 24
Peak memory 216024 kb
Host smart-4b1f00d2-6836-4ef9-b077-5d3199123c25
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634056691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_disconnect.634056691
Directory /workspace/22.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.2925075267
Short name T1970
Test name
Test status
Simulation time 15947426085 ps
CPU time 17.84 seconds
Started Aug 11 07:12:39 PM PDT 24
Finished Aug 11 07:12:57 PM PDT 24
Peak memory 216032 kb
Host smart-6e22147f-7a60-4fff-aa75-c97476f1887a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925075267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.2925075267
Directory /workspace/22.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.3298147146
Short name T1054
Test name
Test status
Simulation time 25993989192 ps
CPU time 31.79 seconds
Started Aug 11 07:12:43 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 216036 kb
Host smart-563f5245-c755-4994-a568-dea0cb957f06
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298147146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_resume.3298147146
Directory /workspace/22.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/22.usbdev_av_buffer.1020870141
Short name T1204
Test name
Test status
Simulation time 158473439 ps
CPU time 0.89 seconds
Started Aug 11 07:12:43 PM PDT 24
Finished Aug 11 07:12:44 PM PDT 24
Peak memory 207572 kb
Host smart-16d6cffc-00e8-4734-af9b-0fe49ec5e793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10208
70141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1020870141
Directory /workspace/22.usbdev_av_buffer/latest


Test location /workspace/coverage/default/22.usbdev_bitstuff_err.1578684783
Short name T1834
Test name
Test status
Simulation time 162447833 ps
CPU time 0.85 seconds
Started Aug 11 07:12:30 PM PDT 24
Finished Aug 11 07:12:31 PM PDT 24
Peak memory 207472 kb
Host smart-e9e9fc1e-0925-4369-bb85-1e20f09b362c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15786
84783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1578684783
Directory /workspace/22.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.474469118
Short name T1920
Test name
Test status
Simulation time 499540089 ps
CPU time 1.68 seconds
Started Aug 11 07:12:32 PM PDT 24
Finished Aug 11 07:12:33 PM PDT 24
Peak memory 207572 kb
Host smart-b713d74b-3dea-42b4-8192-57fb691952bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47446
9118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.474469118
Directory /workspace/22.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1175725997
Short name T3630
Test name
Test status
Simulation time 777755894 ps
CPU time 2.06 seconds
Started Aug 11 07:12:35 PM PDT 24
Finished Aug 11 07:12:37 PM PDT 24
Peak memory 207644 kb
Host smart-dbf553a8-ba93-435e-bb2e-dbdca246f759
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1175725997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1175725997
Directory /workspace/22.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/22.usbdev_device_address.3787972465
Short name T1475
Test name
Test status
Simulation time 46633342572 ps
CPU time 79.62 seconds
Started Aug 11 07:12:30 PM PDT 24
Finished Aug 11 07:13:50 PM PDT 24
Peak memory 207868 kb
Host smart-20a453a8-7d1e-427f-a536-864568633a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37879
72465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3787972465
Directory /workspace/22.usbdev_device_address/latest


Test location /workspace/coverage/default/22.usbdev_device_timeout.1458784037
Short name T919
Test name
Test status
Simulation time 834487285 ps
CPU time 15.62 seconds
Started Aug 11 07:12:32 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 207708 kb
Host smart-119510c4-fe0a-467d-b73d-8a15cde044ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458784037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.1458784037
Directory /workspace/22.usbdev_device_timeout/latest


Test location /workspace/coverage/default/22.usbdev_disable_endpoint.1835837484
Short name T319
Test name
Test status
Simulation time 605062475 ps
CPU time 1.57 seconds
Started Aug 11 07:12:38 PM PDT 24
Finished Aug 11 07:12:40 PM PDT 24
Peak memory 207532 kb
Host smart-a54d1e0b-b943-4afb-bda2-043c4699f7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18358
37484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.1835837484
Directory /workspace/22.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/22.usbdev_disconnected.1052644594
Short name T1342
Test name
Test status
Simulation time 135752626 ps
CPU time 0.83 seconds
Started Aug 11 07:12:31 PM PDT 24
Finished Aug 11 07:12:32 PM PDT 24
Peak memory 207564 kb
Host smart-077f98ad-9e87-4a46-9331-c8e03ad82c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526
44594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1052644594
Directory /workspace/22.usbdev_disconnected/latest


Test location /workspace/coverage/default/22.usbdev_enable.4111759219
Short name T887
Test name
Test status
Simulation time 56010695 ps
CPU time 0.72 seconds
Started Aug 11 07:12:31 PM PDT 24
Finished Aug 11 07:12:31 PM PDT 24
Peak memory 207540 kb
Host smart-35f4eb95-bced-4eaa-8f43-747c251f6c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117
59219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.4111759219
Directory /workspace/22.usbdev_enable/latest


Test location /workspace/coverage/default/22.usbdev_endpoint_access.3483055948
Short name T3074
Test name
Test status
Simulation time 982812180 ps
CPU time 2.74 seconds
Started Aug 11 07:12:30 PM PDT 24
Finished Aug 11 07:12:33 PM PDT 24
Peak memory 207676 kb
Host smart-f353c404-7ae9-4364-be32-03d15c65e38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34830
55948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3483055948
Directory /workspace/22.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/22.usbdev_endpoint_types.1224926852
Short name T2103
Test name
Test status
Simulation time 302429530 ps
CPU time 1.16 seconds
Started Aug 11 07:12:36 PM PDT 24
Finished Aug 11 07:12:38 PM PDT 24
Peak memory 207480 kb
Host smart-331a836e-73d3-43f9-bb35-9b9cb3b1b8c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1224926852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.1224926852
Directory /workspace/22.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/22.usbdev_fifo_rst.3496502810
Short name T828
Test name
Test status
Simulation time 299611924 ps
CPU time 2.18 seconds
Started Aug 11 07:12:31 PM PDT 24
Finished Aug 11 07:12:33 PM PDT 24
Peak memory 207660 kb
Host smart-06f701b8-2f05-4968-86f7-dca92dee6142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34965
02810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3496502810
Directory /workspace/22.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/22.usbdev_in_iso.3301028337
Short name T1557
Test name
Test status
Simulation time 257930368 ps
CPU time 1.12 seconds
Started Aug 11 07:12:43 PM PDT 24
Finished Aug 11 07:12:44 PM PDT 24
Peak memory 215932 kb
Host smart-3a5f06fd-05e5-47cd-9e81-683411ecd31f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3301028337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3301028337
Directory /workspace/22.usbdev_in_iso/latest


Test location /workspace/coverage/default/22.usbdev_in_stall.2835345957
Short name T1994
Test name
Test status
Simulation time 142629715 ps
CPU time 0.85 seconds
Started Aug 11 07:12:41 PM PDT 24
Finished Aug 11 07:12:42 PM PDT 24
Peak memory 207464 kb
Host smart-36cdc2da-928a-4d5b-8e36-ac25166ddbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28353
45957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2835345957
Directory /workspace/22.usbdev_in_stall/latest


Test location /workspace/coverage/default/22.usbdev_in_trans.2817255992
Short name T1679
Test name
Test status
Simulation time 162997259 ps
CPU time 0.87 seconds
Started Aug 11 07:12:33 PM PDT 24
Finished Aug 11 07:12:34 PM PDT 24
Peak memory 207516 kb
Host smart-366ff5e4-0947-4aa9-96ca-569c5ad0aa44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28172
55992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2817255992
Directory /workspace/22.usbdev_in_trans/latest


Test location /workspace/coverage/default/22.usbdev_invalid_sync.2680745292
Short name T2666
Test name
Test status
Simulation time 3385705752 ps
CPU time 36.46 seconds
Started Aug 11 07:12:31 PM PDT 24
Finished Aug 11 07:13:07 PM PDT 24
Peak memory 224204 kb
Host smart-29b87460-cdb6-472f-a0d3-eddd8613ab6f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2680745292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.2680745292
Directory /workspace/22.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/22.usbdev_iso_retraction.1285841672
Short name T3486
Test name
Test status
Simulation time 11731958207 ps
CPU time 73.05 seconds
Started Aug 11 07:12:32 PM PDT 24
Finished Aug 11 07:13:45 PM PDT 24
Peak memory 207752 kb
Host smart-30be0241-73d6-43d9-b23a-a881435051fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1285841672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1285841672
Directory /workspace/22.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/22.usbdev_link_in_err.3182503963
Short name T2947
Test name
Test status
Simulation time 310337807 ps
CPU time 1.02 seconds
Started Aug 11 07:12:38 PM PDT 24
Finished Aug 11 07:12:39 PM PDT 24
Peak memory 207564 kb
Host smart-84d21eb5-29e2-4927-8697-e0513665e2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31825
03963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3182503963
Directory /workspace/22.usbdev_link_in_err/latest


Test location /workspace/coverage/default/22.usbdev_link_resume.1829302459
Short name T2829
Test name
Test status
Simulation time 34388795007 ps
CPU time 53.87 seconds
Started Aug 11 07:12:34 PM PDT 24
Finished Aug 11 07:13:28 PM PDT 24
Peak memory 207872 kb
Host smart-de55ac94-1325-4640-8744-20287ff2b505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18293
02459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1829302459
Directory /workspace/22.usbdev_link_resume/latest


Test location /workspace/coverage/default/22.usbdev_link_suspend.1781991985
Short name T1624
Test name
Test status
Simulation time 4723986866 ps
CPU time 7.7 seconds
Started Aug 11 07:12:34 PM PDT 24
Finished Aug 11 07:12:42 PM PDT 24
Peak memory 207832 kb
Host smart-88d40187-a41c-4d08-8be6-3912755a2fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819
91985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1781991985
Directory /workspace/22.usbdev_link_suspend/latest


Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1566364262
Short name T635
Test name
Test status
Simulation time 2928887297 ps
CPU time 33.17 seconds
Started Aug 11 07:12:43 PM PDT 24
Finished Aug 11 07:13:16 PM PDT 24
Peak memory 218680 kb
Host smart-8ce1685a-b319-4c89-be7b-0f8e788dfed2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1566364262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1566364262
Directory /workspace/22.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.87692942
Short name T2638
Test name
Test status
Simulation time 2708477140 ps
CPU time 26.36 seconds
Started Aug 11 07:12:33 PM PDT 24
Finished Aug 11 07:12:59 PM PDT 24
Peak memory 217704 kb
Host smart-cd998b56-d034-4542-ab33-5de457dc8229
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=87692942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.87692942
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.203405848
Short name T1789
Test name
Test status
Simulation time 234815445 ps
CPU time 0.99 seconds
Started Aug 11 07:12:39 PM PDT 24
Finished Aug 11 07:12:40 PM PDT 24
Peak memory 207568 kb
Host smart-cf0a2ba6-a5d8-42a5-9f81-8006f357d2f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=203405848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.203405848
Directory /workspace/22.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3401032834
Short name T2587
Test name
Test status
Simulation time 195377483 ps
CPU time 0.97 seconds
Started Aug 11 07:12:34 PM PDT 24
Finished Aug 11 07:12:36 PM PDT 24
Peak memory 207564 kb
Host smart-3f510a95-2c0d-4931-847d-61fdd012f218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
32834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3401032834
Directory /workspace/22.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.3061167239
Short name T1294
Test name
Test status
Simulation time 3324232128 ps
CPU time 25.53 seconds
Started Aug 11 07:12:39 PM PDT 24
Finished Aug 11 07:13:05 PM PDT 24
Peak memory 224144 kb
Host smart-baa2d4ec-bd90-4eae-95fa-d511ac7195af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30611
67239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.3061167239
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3535747222
Short name T1465
Test name
Test status
Simulation time 4038330645 ps
CPU time 111.22 seconds
Started Aug 11 07:12:41 PM PDT 24
Finished Aug 11 07:14:32 PM PDT 24
Peak memory 217412 kb
Host smart-51ad9ba1-d6f9-42cf-948e-c48a45f20545
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3535747222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3535747222
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.3433907399
Short name T2348
Test name
Test status
Simulation time 167486629 ps
CPU time 0.94 seconds
Started Aug 11 07:12:37 PM PDT 24
Finished Aug 11 07:12:38 PM PDT 24
Peak memory 207568 kb
Host smart-1e65abbb-0c9c-4455-a364-92a710ef1f70
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3433907399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.3433907399
Directory /workspace/22.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3554566776
Short name T1497
Test name
Test status
Simulation time 136104741 ps
CPU time 0.79 seconds
Started Aug 11 07:12:50 PM PDT 24
Finished Aug 11 07:12:51 PM PDT 24
Peak memory 207584 kb
Host smart-01e54db6-464f-4ab1-bf3a-dc3a0e97804f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35545
66776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3554566776
Directory /workspace/22.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_nak_trans.241698690
Short name T3252
Test name
Test status
Simulation time 195157893 ps
CPU time 0.9 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:12:46 PM PDT 24
Peak memory 207544 kb
Host smart-8fcec774-e2ef-4e83-8fbc-f64b5b87c45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24169
8690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.241698690
Directory /workspace/22.usbdev_nak_trans/latest


Test location /workspace/coverage/default/22.usbdev_out_iso.2272723517
Short name T2834
Test name
Test status
Simulation time 200020106 ps
CPU time 0.93 seconds
Started Aug 11 07:12:37 PM PDT 24
Finished Aug 11 07:12:38 PM PDT 24
Peak memory 207548 kb
Host smart-5f8963da-0992-4663-b8b7-34a0ee5ce981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22727
23517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2272723517
Directory /workspace/22.usbdev_out_iso/latest


Test location /workspace/coverage/default/22.usbdev_out_stall.2535611451
Short name T1335
Test name
Test status
Simulation time 187004609 ps
CPU time 0.97 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:12:46 PM PDT 24
Peak memory 207496 kb
Host smart-ec3c719b-cf99-428e-a2e8-6a039d3ab16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25356
11451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2535611451
Directory /workspace/22.usbdev_out_stall/latest


Test location /workspace/coverage/default/22.usbdev_out_trans_nak.886708518
Short name T539
Test name
Test status
Simulation time 152944685 ps
CPU time 0.85 seconds
Started Aug 11 07:12:36 PM PDT 24
Finished Aug 11 07:12:37 PM PDT 24
Peak memory 207524 kb
Host smart-53d21026-ae87-4fad-8a00-cb9f6afab467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88670
8518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.886708518
Directory /workspace/22.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/22.usbdev_pending_in_trans.994789743
Short name T1853
Test name
Test status
Simulation time 181180239 ps
CPU time 0.94 seconds
Started Aug 11 07:12:39 PM PDT 24
Finished Aug 11 07:12:40 PM PDT 24
Peak memory 207556 kb
Host smart-57e15857-9119-4e8a-af69-8161ea029bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99478
9743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.994789743
Directory /workspace/22.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2956465665
Short name T2261
Test name
Test status
Simulation time 206824007 ps
CPU time 1 seconds
Started Aug 11 07:12:51 PM PDT 24
Finished Aug 11 07:12:52 PM PDT 24
Peak memory 207604 kb
Host smart-bcaef900-c193-44bf-b6be-71cb7fc31ae5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2956465665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2956465665
Directory /workspace/22.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.532906070
Short name T3116
Test name
Test status
Simulation time 74178182 ps
CPU time 0.76 seconds
Started Aug 11 07:12:38 PM PDT 24
Finished Aug 11 07:12:39 PM PDT 24
Peak memory 207524 kb
Host smart-fa73cdd5-0640-4df5-ab61-54c90d3b04a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53290
6070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.532906070
Directory /workspace/22.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3161056892
Short name T2851
Test name
Test status
Simulation time 6458732603 ps
CPU time 16.31 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:17 PM PDT 24
Peak memory 216072 kb
Host smart-9ff34be1-c468-4421-91f1-119a317c99bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
56892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3161056892
Directory /workspace/22.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/22.usbdev_pkt_received.2364095073
Short name T3452
Test name
Test status
Simulation time 177524165 ps
CPU time 0.93 seconds
Started Aug 11 07:12:40 PM PDT 24
Finished Aug 11 07:12:41 PM PDT 24
Peak memory 207576 kb
Host smart-54e2ba34-72f0-470f-8bd7-9e38d06c4f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23640
95073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2364095073
Directory /workspace/22.usbdev_pkt_received/latest


Test location /workspace/coverage/default/22.usbdev_pkt_sent.1756363856
Short name T2774
Test name
Test status
Simulation time 276401887 ps
CPU time 1.05 seconds
Started Aug 11 07:12:42 PM PDT 24
Finished Aug 11 07:12:43 PM PDT 24
Peak memory 207548 kb
Host smart-c21626db-1f78-4715-a42e-c4f8ef6dc094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17563
63856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1756363856
Directory /workspace/22.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.496162610
Short name T736
Test name
Test status
Simulation time 234392985 ps
CPU time 1.01 seconds
Started Aug 11 07:12:49 PM PDT 24
Finished Aug 11 07:12:50 PM PDT 24
Peak memory 207536 kb
Host smart-8a473455-6548-488f-bc06-42bd5079b422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49616
2610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.496162610
Directory /workspace/22.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3980527818
Short name T2016
Test name
Test status
Simulation time 193300432 ps
CPU time 0.93 seconds
Started Aug 11 07:12:38 PM PDT 24
Finished Aug 11 07:12:39 PM PDT 24
Peak memory 207572 kb
Host smart-90decd63-25df-4626-bc11-44361f9f629f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39805
27818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3980527818
Directory /workspace/22.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_rx_crc_err.140922622
Short name T3078
Test name
Test status
Simulation time 148590274 ps
CPU time 0.83 seconds
Started Aug 11 07:12:48 PM PDT 24
Finished Aug 11 07:12:49 PM PDT 24
Peak memory 207472 kb
Host smart-6d17f286-db8a-4f25-b96c-40a1b4e205ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14092
2622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.140922622
Directory /workspace/22.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/22.usbdev_rx_full.3158044074
Short name T2542
Test name
Test status
Simulation time 442051049 ps
CPU time 1.39 seconds
Started Aug 11 07:12:42 PM PDT 24
Finished Aug 11 07:12:44 PM PDT 24
Peak memory 207500 kb
Host smart-5d8b7d43-59e6-4e12-a5c4-a52537203133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31580
44074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.3158044074
Directory /workspace/22.usbdev_rx_full/latest


Test location /workspace/coverage/default/22.usbdev_setup_stage.171493101
Short name T1972
Test name
Test status
Simulation time 160213746 ps
CPU time 0.84 seconds
Started Aug 11 07:12:38 PM PDT 24
Finished Aug 11 07:12:39 PM PDT 24
Peak memory 207524 kb
Host smart-f5efedd2-c4a3-4ca6-9fa4-c27bd5192874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17149
3101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.171493101
Directory /workspace/22.usbdev_setup_stage/latest


Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.305572054
Short name T1105
Test name
Test status
Simulation time 176581931 ps
CPU time 0.89 seconds
Started Aug 11 07:12:36 PM PDT 24
Finished Aug 11 07:12:37 PM PDT 24
Peak memory 207488 kb
Host smart-d1425ad1-7b00-4b33-b1f0-19410d3310ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30557
2054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.305572054
Directory /workspace/22.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/22.usbdev_smoke.1049143468
Short name T1930
Test name
Test status
Simulation time 225433568 ps
CPU time 1.09 seconds
Started Aug 11 07:12:47 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 207584 kb
Host smart-f8664c59-2421-4d46-ba23-f55cfbb3d6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10491
43468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1049143468
Directory /workspace/22.usbdev_smoke/latest


Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2289243181
Short name T2769
Test name
Test status
Simulation time 2579641057 ps
CPU time 20.63 seconds
Started Aug 11 07:12:40 PM PDT 24
Finished Aug 11 07:13:01 PM PDT 24
Peak memory 217948 kb
Host smart-bbe87d59-cd9d-40b3-9251-b2828b918568
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2289243181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2289243181
Directory /workspace/22.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3884581131
Short name T2775
Test name
Test status
Simulation time 241199586 ps
CPU time 0.94 seconds
Started Aug 11 07:12:36 PM PDT 24
Finished Aug 11 07:12:37 PM PDT 24
Peak memory 207568 kb
Host smart-af451344-454c-4b7e-88d7-23366f9cc94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38845
81131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3884581131
Directory /workspace/22.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/22.usbdev_stall_trans.381488215
Short name T1057
Test name
Test status
Simulation time 235890451 ps
CPU time 0.92 seconds
Started Aug 11 07:12:41 PM PDT 24
Finished Aug 11 07:12:42 PM PDT 24
Peak memory 207564 kb
Host smart-bddfcc49-f910-4526-ab25-50d31756b8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38148
8215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.381488215
Directory /workspace/22.usbdev_stall_trans/latest


Test location /workspace/coverage/default/22.usbdev_stream_len_max.1350275170
Short name T2952
Test name
Test status
Simulation time 672472305 ps
CPU time 1.81 seconds
Started Aug 11 07:12:41 PM PDT 24
Finished Aug 11 07:12:43 PM PDT 24
Peak memory 207484 kb
Host smart-4305a0bc-d147-4c06-b87e-c280e158b73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13502
75170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1350275170
Directory /workspace/22.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/22.usbdev_streaming_out.3696300131
Short name T292
Test name
Test status
Simulation time 2820004798 ps
CPU time 79.44 seconds
Started Aug 11 07:12:38 PM PDT 24
Finished Aug 11 07:13:57 PM PDT 24
Peak memory 217788 kb
Host smart-1d56b6da-5cdf-49b4-a586-2efbf40aed90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36963
00131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3696300131
Directory /workspace/22.usbdev_streaming_out/latest


Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.4276968807
Short name T2837
Test name
Test status
Simulation time 1183133291 ps
CPU time 26.36 seconds
Started Aug 11 07:12:37 PM PDT 24
Finished Aug 11 07:13:03 PM PDT 24
Peak memory 207760 kb
Host smart-cb9325a9-01af-4a88-acf0-15d25739ecff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276968807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.4276968807
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/22.usbdev_tx_rx_disruption.2570975510
Short name T2290
Test name
Test status
Simulation time 572899835 ps
CPU time 1.76 seconds
Started Aug 11 07:12:42 PM PDT 24
Finished Aug 11 07:12:45 PM PDT 24
Peak memory 207552 kb
Host smart-1ec2ad74-1514-4588-b9a6-34598d64c621
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570975510 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.usbdev_tx_rx_disruption.2570975510
Directory /workspace/22.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/220.usbdev_tx_rx_disruption.1334708886
Short name T2601
Test name
Test status
Simulation time 547489358 ps
CPU time 1.64 seconds
Started Aug 11 07:17:36 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207600 kb
Host smart-ddde2aff-1f24-455f-8182-c53a7f533785
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334708886 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.usbdev_tx_rx_disruption.1334708886
Directory /workspace/220.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/221.usbdev_tx_rx_disruption.830687697
Short name T1240
Test name
Test status
Simulation time 646860822 ps
CPU time 1.81 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207536 kb
Host smart-f4ce6c6f-fdd4-4c02-9d47-269ae58b4e04
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830687697 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 221.usbdev_tx_rx_disruption.830687697
Directory /workspace/221.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/222.usbdev_tx_rx_disruption.4278697733
Short name T2931
Test name
Test status
Simulation time 567889451 ps
CPU time 1.76 seconds
Started Aug 11 07:17:36 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207548 kb
Host smart-4a5e56ad-2373-4acc-b3c5-7982daf54330
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278697733 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.usbdev_tx_rx_disruption.4278697733
Directory /workspace/222.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/223.usbdev_tx_rx_disruption.3964413541
Short name T1855
Test name
Test status
Simulation time 543407020 ps
CPU time 1.69 seconds
Started Aug 11 07:17:42 PM PDT 24
Finished Aug 11 07:17:44 PM PDT 24
Peak memory 207540 kb
Host smart-039e5a3e-ba47-41ce-85e5-d9a569f7ed8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964413541 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.usbdev_tx_rx_disruption.3964413541
Directory /workspace/223.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/224.usbdev_tx_rx_disruption.981957667
Short name T1996
Test name
Test status
Simulation time 457243069 ps
CPU time 1.36 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:36 PM PDT 24
Peak memory 207572 kb
Host smart-f77a1be8-7985-40a3-9b9a-2c3eafdd5fdc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981957667 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 224.usbdev_tx_rx_disruption.981957667
Directory /workspace/224.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/225.usbdev_tx_rx_disruption.2984845316
Short name T1463
Test name
Test status
Simulation time 534966315 ps
CPU time 1.58 seconds
Started Aug 11 07:17:38 PM PDT 24
Finished Aug 11 07:17:40 PM PDT 24
Peak memory 207500 kb
Host smart-5c92a9eb-3818-44e4-9009-f3d680eaf755
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984845316 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.usbdev_tx_rx_disruption.2984845316
Directory /workspace/225.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/226.usbdev_tx_rx_disruption.2284149559
Short name T3278
Test name
Test status
Simulation time 542188802 ps
CPU time 1.75 seconds
Started Aug 11 07:17:30 PM PDT 24
Finished Aug 11 07:17:32 PM PDT 24
Peak memory 207548 kb
Host smart-9af7e808-ed1a-43cb-8fa8-d932bde6b32b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284149559 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.usbdev_tx_rx_disruption.2284149559
Directory /workspace/226.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/227.usbdev_tx_rx_disruption.3026683864
Short name T2696
Test name
Test status
Simulation time 491800066 ps
CPU time 1.47 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:40 PM PDT 24
Peak memory 207544 kb
Host smart-3c245072-9592-4757-8d51-a48c53a63074
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026683864 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.usbdev_tx_rx_disruption.3026683864
Directory /workspace/227.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/228.usbdev_tx_rx_disruption.1295188896
Short name T3034
Test name
Test status
Simulation time 464705848 ps
CPU time 1.39 seconds
Started Aug 11 07:17:51 PM PDT 24
Finished Aug 11 07:17:52 PM PDT 24
Peak memory 207564 kb
Host smart-c9ce293d-83fd-41c9-9cae-cda8c80c748b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295188896 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.usbdev_tx_rx_disruption.1295188896
Directory /workspace/228.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/229.usbdev_tx_rx_disruption.2287708110
Short name T3139
Test name
Test status
Simulation time 528510546 ps
CPU time 1.53 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:35 PM PDT 24
Peak memory 207588 kb
Host smart-36e4b9c3-c205-4e76-918c-cab325fd52bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287708110 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.usbdev_tx_rx_disruption.2287708110
Directory /workspace/229.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/23.usbdev_alert_test.773830854
Short name T3524
Test name
Test status
Simulation time 44213145 ps
CPU time 0.68 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:04 PM PDT 24
Peak memory 207624 kb
Host smart-950ae8b7-71b4-4c37-a9ec-7d8180e4199a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=773830854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.773830854
Directory /workspace/23.usbdev_alert_test/latest


Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.397566690
Short name T2062
Test name
Test status
Simulation time 9237490193 ps
CPU time 11.71 seconds
Started Aug 11 07:12:57 PM PDT 24
Finished Aug 11 07:13:09 PM PDT 24
Peak memory 207768 kb
Host smart-27ab226c-79fa-4de1-9822-643da5920304
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397566690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_ao
n_wake_disconnect.397566690
Directory /workspace/23.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2807176718
Short name T3618
Test name
Test status
Simulation time 14157214624 ps
CPU time 15.41 seconds
Started Aug 11 07:12:48 PM PDT 24
Finished Aug 11 07:13:03 PM PDT 24
Peak memory 215976 kb
Host smart-78d4eff1-bd61-493b-8277-a700bdaa4546
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807176718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2807176718
Directory /workspace/23.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3963850573
Short name T1891
Test name
Test status
Simulation time 25541566703 ps
CPU time 29.52 seconds
Started Aug 11 07:12:46 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 216012 kb
Host smart-ab11d5e9-3aa1-4608-aea2-9698a9ebf1e6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963850573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.3963850573
Directory /workspace/23.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/23.usbdev_av_buffer.2435954231
Short name T2502
Test name
Test status
Simulation time 215464109 ps
CPU time 0.92 seconds
Started Aug 11 07:12:47 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 207480 kb
Host smart-9d2d0882-fea0-4bd6-b659-980fc204264d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24359
54231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2435954231
Directory /workspace/23.usbdev_av_buffer/latest


Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1391734597
Short name T2944
Test name
Test status
Simulation time 372471359 ps
CPU time 1.4 seconds
Started Aug 11 07:12:41 PM PDT 24
Finished Aug 11 07:12:43 PM PDT 24
Peak memory 207596 kb
Host smart-7984edc0-d835-4ab0-a820-14947f91c37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13917
34597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1391734597
Directory /workspace/23.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3715254322
Short name T2519
Test name
Test status
Simulation time 862009919 ps
CPU time 2.29 seconds
Started Aug 11 07:12:47 PM PDT 24
Finished Aug 11 07:12:49 PM PDT 24
Peak memory 207704 kb
Host smart-6165a5eb-e001-4fa8-ba29-4f65144bb0f8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3715254322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3715254322
Directory /workspace/23.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/23.usbdev_device_address.2827088385
Short name T390
Test name
Test status
Simulation time 48571662068 ps
CPU time 73.87 seconds
Started Aug 11 07:12:44 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207820 kb
Host smart-c9e6202f-1e1c-404b-8756-95c62203bd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28270
88385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2827088385
Directory /workspace/23.usbdev_device_address/latest


Test location /workspace/coverage/default/23.usbdev_device_timeout.79631348
Short name T3119
Test name
Test status
Simulation time 801412634 ps
CPU time 14.9 seconds
Started Aug 11 07:12:44 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 207684 kb
Host smart-7ac36e1f-a475-4142-a850-880a4fd1e72c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79631348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.79631348
Directory /workspace/23.usbdev_device_timeout/latest


Test location /workspace/coverage/default/23.usbdev_disable_endpoint.693012439
Short name T1931
Test name
Test status
Simulation time 640332341 ps
CPU time 1.87 seconds
Started Aug 11 07:12:47 PM PDT 24
Finished Aug 11 07:12:49 PM PDT 24
Peak memory 207544 kb
Host smart-12e38010-eb0c-426f-8a76-f01053f04e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69301
2439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.693012439
Directory /workspace/23.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/23.usbdev_disconnected.3903729839
Short name T1600
Test name
Test status
Simulation time 136845075 ps
CPU time 0.82 seconds
Started Aug 11 07:12:48 PM PDT 24
Finished Aug 11 07:12:49 PM PDT 24
Peak memory 207492 kb
Host smart-742b3fbb-064a-4189-b1ce-43c88005ba10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39037
29839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3903729839
Directory /workspace/23.usbdev_disconnected/latest


Test location /workspace/coverage/default/23.usbdev_enable.986289542
Short name T875
Test name
Test status
Simulation time 39391186 ps
CPU time 0.7 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:12:46 PM PDT 24
Peak memory 207520 kb
Host smart-8909c673-3754-4b0b-874c-af9796d54724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98628
9542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.986289542
Directory /workspace/23.usbdev_enable/latest


Test location /workspace/coverage/default/23.usbdev_endpoint_access.138631326
Short name T1917
Test name
Test status
Simulation time 813083539 ps
CPU time 2.28 seconds
Started Aug 11 07:12:46 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 207748 kb
Host smart-d4289d6a-fe3c-417e-adf9-6d71ceb440a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13863
1326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.138631326
Directory /workspace/23.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/23.usbdev_fifo_rst.387029378
Short name T3063
Test name
Test status
Simulation time 316490769 ps
CPU time 2.14 seconds
Started Aug 11 07:12:47 PM PDT 24
Finished Aug 11 07:12:50 PM PDT 24
Peak memory 207692 kb
Host smart-204f3b0e-0bd8-48fa-a7d0-f0089c9f0483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38702
9378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.387029378
Directory /workspace/23.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/23.usbdev_in_iso.2717495835
Short name T2650
Test name
Test status
Simulation time 287242636 ps
CPU time 1.28 seconds
Started Aug 11 07:12:47 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 216140 kb
Host smart-2b3f6758-81e4-4fcf-a95b-31bd18927735
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2717495835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2717495835
Directory /workspace/23.usbdev_in_iso/latest


Test location /workspace/coverage/default/23.usbdev_in_stall.3370896468
Short name T1048
Test name
Test status
Simulation time 151575654 ps
CPU time 0.82 seconds
Started Aug 11 07:12:46 PM PDT 24
Finished Aug 11 07:12:47 PM PDT 24
Peak memory 207460 kb
Host smart-8a7ebdd4-6ab6-445a-ba4a-5e9af2f22a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33708
96468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3370896468
Directory /workspace/23.usbdev_in_stall/latest


Test location /workspace/coverage/default/23.usbdev_in_trans.463777901
Short name T1567
Test name
Test status
Simulation time 183631501 ps
CPU time 0.95 seconds
Started Aug 11 07:12:53 PM PDT 24
Finished Aug 11 07:12:54 PM PDT 24
Peak memory 207712 kb
Host smart-79c4a745-a69f-40f5-884d-09ac1d98b604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46377
7901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.463777901
Directory /workspace/23.usbdev_in_trans/latest


Test location /workspace/coverage/default/23.usbdev_invalid_sync.3296999233
Short name T3419
Test name
Test status
Simulation time 4344358907 ps
CPU time 42.1 seconds
Started Aug 11 07:12:46 PM PDT 24
Finished Aug 11 07:13:28 PM PDT 24
Peak memory 224220 kb
Host smart-c5d5afd1-236b-451c-8f03-daf50050c15c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3296999233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3296999233
Directory /workspace/23.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/23.usbdev_iso_retraction.2684555244
Short name T1847
Test name
Test status
Simulation time 11648469609 ps
CPU time 147.69 seconds
Started Aug 11 07:12:49 PM PDT 24
Finished Aug 11 07:15:17 PM PDT 24
Peak memory 207852 kb
Host smart-cdd5b0b2-0902-4619-9c96-d2b8e4adb0f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2684555244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.2684555244
Directory /workspace/23.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/23.usbdev_link_in_err.3926590651
Short name T2073
Test name
Test status
Simulation time 204818237 ps
CPU time 0.98 seconds
Started Aug 11 07:12:55 PM PDT 24
Finished Aug 11 07:12:56 PM PDT 24
Peak memory 207516 kb
Host smart-8ba6e46d-a4df-44a7-ab84-57d6e5fedc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
90651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3926590651
Directory /workspace/23.usbdev_link_in_err/latest


Test location /workspace/coverage/default/23.usbdev_link_resume.2331133468
Short name T1274
Test name
Test status
Simulation time 23732125217 ps
CPU time 43.05 seconds
Started Aug 11 07:12:49 PM PDT 24
Finished Aug 11 07:13:32 PM PDT 24
Peak memory 216056 kb
Host smart-e63a4e73-0dc9-4019-aea0-daf1384e7bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23311
33468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2331133468
Directory /workspace/23.usbdev_link_resume/latest


Test location /workspace/coverage/default/23.usbdev_link_suspend.2626187285
Short name T1461
Test name
Test status
Simulation time 10397126548 ps
CPU time 14 seconds
Started Aug 11 07:13:06 PM PDT 24
Finished Aug 11 07:13:20 PM PDT 24
Peak memory 207844 kb
Host smart-4a4da29d-3b75-44d3-b534-1c49cffada3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26261
87285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2626187285
Directory /workspace/23.usbdev_link_suspend/latest


Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.2630341583
Short name T1818
Test name
Test status
Simulation time 4664869135 ps
CPU time 145.32 seconds
Started Aug 11 07:12:50 PM PDT 24
Finished Aug 11 07:15:16 PM PDT 24
Peak memory 218916 kb
Host smart-8e8d80eb-b5d9-4822-ab4a-a1ff379a0e19
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2630341583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.2630341583
Directory /workspace/23.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.80725252
Short name T1157
Test name
Test status
Simulation time 1886859102 ps
CPU time 18.84 seconds
Started Aug 11 07:12:44 PM PDT 24
Finished Aug 11 07:13:03 PM PDT 24
Peak memory 216776 kb
Host smart-28cfb618-df8f-4704-a603-56f054b38a6b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=80725252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.80725252
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.1106774089
Short name T2878
Test name
Test status
Simulation time 264360372 ps
CPU time 1 seconds
Started Aug 11 07:12:48 PM PDT 24
Finished Aug 11 07:12:49 PM PDT 24
Peak memory 207448 kb
Host smart-fbbdf831-d32d-4b18-b2fc-41828e3a1a7d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1106774089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.1106774089
Directory /workspace/23.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1240651755
Short name T1837
Test name
Test status
Simulation time 185176345 ps
CPU time 0.92 seconds
Started Aug 11 07:12:52 PM PDT 24
Finished Aug 11 07:12:53 PM PDT 24
Peak memory 207552 kb
Host smart-ef851ca2-aaf3-4cbf-aa2b-31ba8a8147e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12406
51755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1240651755
Directory /workspace/23.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.1052779726
Short name T291
Test name
Test status
Simulation time 2251247498 ps
CPU time 16.92 seconds
Started Aug 11 07:12:57 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 217732 kb
Host smart-1f0248da-9886-4ccb-957b-e2a12a028639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10527
79726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.1052779726
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.332090066
Short name T2549
Test name
Test status
Simulation time 1599955447 ps
CPU time 16.22 seconds
Started Aug 11 07:12:43 PM PDT 24
Finished Aug 11 07:12:59 PM PDT 24
Peak memory 217488 kb
Host smart-39974365-310d-4b1f-b274-fa2a5035d5c4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=332090066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.332090066
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1849196851
Short name T2668
Test name
Test status
Simulation time 155608620 ps
CPU time 0.88 seconds
Started Aug 11 07:12:50 PM PDT 24
Finished Aug 11 07:12:51 PM PDT 24
Peak memory 207564 kb
Host smart-fea77f5a-1b50-4a80-a095-0a960048a937
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1849196851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1849196851
Directory /workspace/23.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1607886109
Short name T1208
Test name
Test status
Simulation time 149125912 ps
CPU time 0.85 seconds
Started Aug 11 07:12:53 PM PDT 24
Finished Aug 11 07:12:54 PM PDT 24
Peak memory 207544 kb
Host smart-739a9d23-7962-40c1-8301-78cfd2e44a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16078
86109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1607886109
Directory /workspace/23.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_nak_trans.15690624
Short name T2595
Test name
Test status
Simulation time 275798966 ps
CPU time 1.06 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:12:46 PM PDT 24
Peak memory 207572 kb
Host smart-e1a8bb01-a6e5-46bf-9fb4-7013029724d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15690
624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.15690624
Directory /workspace/23.usbdev_nak_trans/latest


Test location /workspace/coverage/default/23.usbdev_out_iso.3465184425
Short name T2694
Test name
Test status
Simulation time 197677470 ps
CPU time 0.93 seconds
Started Aug 11 07:12:46 PM PDT 24
Finished Aug 11 07:12:47 PM PDT 24
Peak memory 207564 kb
Host smart-2811743c-330e-498d-8c4b-315eebe3e7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34651
84425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3465184425
Directory /workspace/23.usbdev_out_iso/latest


Test location /workspace/coverage/default/23.usbdev_out_stall.2530781968
Short name T1738
Test name
Test status
Simulation time 150510883 ps
CPU time 0.87 seconds
Started Aug 11 07:12:58 PM PDT 24
Finished Aug 11 07:12:59 PM PDT 24
Peak memory 207748 kb
Host smart-d2f0aebb-c68a-4364-a7f3-958321673086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25307
81968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2530781968
Directory /workspace/23.usbdev_out_stall/latest


Test location /workspace/coverage/default/23.usbdev_out_trans_nak.162698908
Short name T2312
Test name
Test status
Simulation time 173553025 ps
CPU time 0.88 seconds
Started Aug 11 07:12:50 PM PDT 24
Finished Aug 11 07:12:52 PM PDT 24
Peak memory 207548 kb
Host smart-b8a00c6b-4f9a-408a-9553-b9b8499d02aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16269
8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.162698908
Directory /workspace/23.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/23.usbdev_pending_in_trans.348983721
Short name T1615
Test name
Test status
Simulation time 169768539 ps
CPU time 0.86 seconds
Started Aug 11 07:12:42 PM PDT 24
Finished Aug 11 07:12:43 PM PDT 24
Peak memory 207564 kb
Host smart-58055fcc-5933-4168-8a89-9ba3d65cd36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34898
3721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.348983721
Directory /workspace/23.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1040703431
Short name T974
Test name
Test status
Simulation time 236203346 ps
CPU time 1 seconds
Started Aug 11 07:12:58 PM PDT 24
Finished Aug 11 07:12:59 PM PDT 24
Peak memory 207580 kb
Host smart-9a16eceb-d6e9-4142-b3b8-32dc956a61ef
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1040703431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1040703431
Directory /workspace/23.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.207999195
Short name T1993
Test name
Test status
Simulation time 150126256 ps
CPU time 0.89 seconds
Started Aug 11 07:12:48 PM PDT 24
Finished Aug 11 07:12:49 PM PDT 24
Peak memory 207428 kb
Host smart-042ed078-1dc8-45e7-a406-5659432b2828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20799
9195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.207999195
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3872850017
Short name T2396
Test name
Test status
Simulation time 32765666 ps
CPU time 0.68 seconds
Started Aug 11 07:12:50 PM PDT 24
Finished Aug 11 07:12:51 PM PDT 24
Peak memory 207548 kb
Host smart-f23bb535-4023-41ec-a2fd-f47a6f3abea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38728
50017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3872850017
Directory /workspace/23.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/23.usbdev_pkt_buffer.712735900
Short name T2132
Test name
Test status
Simulation time 8799505243 ps
CPU time 21.45 seconds
Started Aug 11 07:12:51 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 216008 kb
Host smart-c40ebd64-0794-4b3a-8536-ff838e9e57d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71273
5900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.712735900
Directory /workspace/23.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/23.usbdev_pkt_received.1476103082
Short name T245
Test name
Test status
Simulation time 221654579 ps
CPU time 0.95 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:02 PM PDT 24
Peak memory 207492 kb
Host smart-fc683eab-12fa-4a97-9c9b-6037f0265133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14761
03082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1476103082
Directory /workspace/23.usbdev_pkt_received/latest


Test location /workspace/coverage/default/23.usbdev_pkt_sent.1909396535
Short name T3236
Test name
Test status
Simulation time 223958783 ps
CPU time 0.96 seconds
Started Aug 11 07:12:59 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 207468 kb
Host smart-a7338bdf-815d-40b4-a7f5-82b6517f8896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19093
96535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1909396535
Directory /workspace/23.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.2997034481
Short name T3463
Test name
Test status
Simulation time 241830401 ps
CPU time 0.99 seconds
Started Aug 11 07:12:52 PM PDT 24
Finished Aug 11 07:12:53 PM PDT 24
Peak memory 207500 kb
Host smart-da2d16dc-0781-4c8a-8e68-ac55423c4610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29970
34481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.2997034481
Directory /workspace/23.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1730050956
Short name T3036
Test name
Test status
Simulation time 199665947 ps
CPU time 0.94 seconds
Started Aug 11 07:12:47 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 207552 kb
Host smart-88c0bbcb-704d-4620-adee-f212286cc09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17300
50956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1730050956
Directory /workspace/23.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_rx_crc_err.473230131
Short name T2749
Test name
Test status
Simulation time 139541755 ps
CPU time 0.84 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:12:46 PM PDT 24
Peak memory 207516 kb
Host smart-a5258244-0a4b-4199-a2e5-7c0ee417dda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47323
0131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.473230131
Directory /workspace/23.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/23.usbdev_rx_full.558431081
Short name T889
Test name
Test status
Simulation time 344088488 ps
CPU time 1.23 seconds
Started Aug 11 07:12:49 PM PDT 24
Finished Aug 11 07:12:50 PM PDT 24
Peak memory 207512 kb
Host smart-b7fbc386-c3d2-4261-9ca6-f3ec4fd4bf67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55843
1081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.558431081
Directory /workspace/23.usbdev_rx_full/latest


Test location /workspace/coverage/default/23.usbdev_setup_stage.2216654804
Short name T1491
Test name
Test status
Simulation time 154337707 ps
CPU time 0.83 seconds
Started Aug 11 07:12:48 PM PDT 24
Finished Aug 11 07:12:49 PM PDT 24
Peak memory 207508 kb
Host smart-f458dd0e-58aa-4dfb-af6e-e6f2510a9e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22166
54804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2216654804
Directory /workspace/23.usbdev_setup_stage/latest


Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3948006025
Short name T2291
Test name
Test status
Simulation time 209743215 ps
CPU time 0.94 seconds
Started Aug 11 07:12:52 PM PDT 24
Finished Aug 11 07:12:53 PM PDT 24
Peak memory 207604 kb
Host smart-cc2d5597-a4a1-40d0-b6ac-b81d8609f1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39480
06025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3948006025
Directory /workspace/23.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/23.usbdev_smoke.2115165034
Short name T1493
Test name
Test status
Simulation time 250146954 ps
CPU time 1.04 seconds
Started Aug 11 07:12:47 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 207484 kb
Host smart-ce4ae7f2-f4cd-45ce-82f7-086a4ba62922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21151
65034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2115165034
Directory /workspace/23.usbdev_smoke/latest


Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1446224307
Short name T699
Test name
Test status
Simulation time 2343218111 ps
CPU time 67.67 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 217728 kb
Host smart-c8348278-aaf5-49f1-b27c-7938c1492171
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1446224307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1446224307
Directory /workspace/23.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.118847739
Short name T2662
Test name
Test status
Simulation time 195440374 ps
CPU time 1 seconds
Started Aug 11 07:12:59 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 207604 kb
Host smart-7474c946-f598-4f7a-a794-9c48b4a583ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11884
7739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.118847739
Directory /workspace/23.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/23.usbdev_stall_trans.1020660630
Short name T683
Test name
Test status
Simulation time 164376429 ps
CPU time 0.88 seconds
Started Aug 11 07:12:54 PM PDT 24
Finished Aug 11 07:12:55 PM PDT 24
Peak memory 207768 kb
Host smart-94bf0eb7-332d-4dd5-aa79-106f8293adc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10206
60630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1020660630
Directory /workspace/23.usbdev_stall_trans/latest


Test location /workspace/coverage/default/23.usbdev_stream_len_max.2246926621
Short name T3435
Test name
Test status
Simulation time 380537853 ps
CPU time 1.28 seconds
Started Aug 11 07:12:50 PM PDT 24
Finished Aug 11 07:12:51 PM PDT 24
Peak memory 207520 kb
Host smart-5d9e0d08-1ec6-4871-a40b-811302b9972c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22469
26621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2246926621
Directory /workspace/23.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/23.usbdev_streaming_out.3182076012
Short name T1633
Test name
Test status
Simulation time 2601744133 ps
CPU time 73.19 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 216028 kb
Host smart-f5093018-2dd5-4abb-bc9d-e558546621ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31820
76012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3182076012
Directory /workspace/23.usbdev_streaming_out/latest


Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.4154220503
Short name T751
Test name
Test status
Simulation time 1528330882 ps
CPU time 14.08 seconds
Started Aug 11 07:12:50 PM PDT 24
Finished Aug 11 07:13:05 PM PDT 24
Peak memory 207660 kb
Host smart-21e4a2fb-c018-40fc-8769-51d4d7a32a20
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154220503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.4154220503
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/23.usbdev_tx_rx_disruption.2743408597
Short name T2609
Test name
Test status
Simulation time 511874363 ps
CPU time 1.54 seconds
Started Aug 11 07:12:55 PM PDT 24
Finished Aug 11 07:12:57 PM PDT 24
Peak memory 207568 kb
Host smart-48fea878-a05c-44ef-adb0-2c00a6b47ce6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743408597 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.usbdev_tx_rx_disruption.2743408597
Directory /workspace/23.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/230.usbdev_tx_rx_disruption.2513353636
Short name T3263
Test name
Test status
Simulation time 491523155 ps
CPU time 1.47 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:35 PM PDT 24
Peak memory 207588 kb
Host smart-d921fab2-fad6-41f9-9860-d5d5101c8ca3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513353636 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.usbdev_tx_rx_disruption.2513353636
Directory /workspace/230.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/231.usbdev_tx_rx_disruption.1050793107
Short name T3418
Test name
Test status
Simulation time 493866207 ps
CPU time 1.49 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207592 kb
Host smart-bcc6742f-1276-4d5c-b8e9-11db188f57f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050793107 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.usbdev_tx_rx_disruption.1050793107
Directory /workspace/231.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/232.usbdev_tx_rx_disruption.576825703
Short name T2689
Test name
Test status
Simulation time 608880605 ps
CPU time 1.69 seconds
Started Aug 11 07:17:32 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207576 kb
Host smart-c9a4263a-d06e-417f-a71b-2f1eccdac48f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576825703 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 232.usbdev_tx_rx_disruption.576825703
Directory /workspace/232.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/233.usbdev_tx_rx_disruption.4238420114
Short name T2495
Test name
Test status
Simulation time 669485546 ps
CPU time 1.66 seconds
Started Aug 11 07:17:29 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 207568 kb
Host smart-9a18f322-655e-4cd7-8314-9119be481295
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238420114 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.usbdev_tx_rx_disruption.4238420114
Directory /workspace/233.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/234.usbdev_tx_rx_disruption.3287823319
Short name T1767
Test name
Test status
Simulation time 557932011 ps
CPU time 1.57 seconds
Started Aug 11 07:17:41 PM PDT 24
Finished Aug 11 07:17:43 PM PDT 24
Peak memory 207480 kb
Host smart-4bd6b955-14fe-4693-a8c9-4fcae308c93f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287823319 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.usbdev_tx_rx_disruption.3287823319
Directory /workspace/234.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/236.usbdev_tx_rx_disruption.1106765711
Short name T2102
Test name
Test status
Simulation time 650439094 ps
CPU time 1.79 seconds
Started Aug 11 07:17:43 PM PDT 24
Finished Aug 11 07:17:45 PM PDT 24
Peak memory 207500 kb
Host smart-e7170de1-29a7-4658-893f-0ae6659a13d6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106765711 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.usbdev_tx_rx_disruption.1106765711
Directory /workspace/236.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/237.usbdev_tx_rx_disruption.3065887722
Short name T993
Test name
Test status
Simulation time 550952073 ps
CPU time 1.63 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207528 kb
Host smart-48aeebb7-d065-4f33-9ba2-28d61187235d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065887722 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.usbdev_tx_rx_disruption.3065887722
Directory /workspace/237.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/238.usbdev_tx_rx_disruption.1540497623
Short name T3513
Test name
Test status
Simulation time 560351301 ps
CPU time 1.57 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207776 kb
Host smart-9ea12236-9d4c-4228-b816-4a7e0b667ff9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540497623 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.usbdev_tx_rx_disruption.1540497623
Directory /workspace/238.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/239.usbdev_tx_rx_disruption.2410285631
Short name T108
Test name
Test status
Simulation time 678702797 ps
CPU time 1.76 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207544 kb
Host smart-22b67c82-5bac-4c63-adf1-df234003cc8e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410285631 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.usbdev_tx_rx_disruption.2410285631
Directory /workspace/239.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/24.usbdev_alert_test.2623887070
Short name T3160
Test name
Test status
Simulation time 69923633 ps
CPU time 0.78 seconds
Started Aug 11 07:13:04 PM PDT 24
Finished Aug 11 07:13:05 PM PDT 24
Peak memory 207596 kb
Host smart-27f72b0f-11ea-431a-a986-a8c2d6fd81bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2623887070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2623887070
Directory /workspace/24.usbdev_alert_test/latest


Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.494929561
Short name T226
Test name
Test status
Simulation time 10728496200 ps
CPU time 15 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:13:23 PM PDT 24
Peak memory 207820 kb
Host smart-d41b4cf8-d260-4768-abd7-4c04d1b3b568
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494929561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_disconnect.494929561
Directory /workspace/24.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1340561806
Short name T2926
Test name
Test status
Simulation time 14986464188 ps
CPU time 16.16 seconds
Started Aug 11 07:12:52 PM PDT 24
Finished Aug 11 07:13:08 PM PDT 24
Peak memory 215968 kb
Host smart-73be2306-0d34-4dd4-83e9-292037cbb639
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340561806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1340561806
Directory /workspace/24.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3719147363
Short name T1249
Test name
Test status
Simulation time 24428029628 ps
CPU time 28.89 seconds
Started Aug 11 07:12:45 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 216012 kb
Host smart-1f634859-69a1-4011-b7af-29134b27c043
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719147363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.3719147363
Directory /workspace/24.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/24.usbdev_av_buffer.2277768303
Short name T3223
Test name
Test status
Simulation time 245644025 ps
CPU time 0.96 seconds
Started Aug 11 07:12:46 PM PDT 24
Finished Aug 11 07:12:47 PM PDT 24
Peak memory 207472 kb
Host smart-ee7b9555-34b2-40ce-8f15-49a1b51989aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22777
68303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2277768303
Directory /workspace/24.usbdev_av_buffer/latest


Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3839299715
Short name T1410
Test name
Test status
Simulation time 166970853 ps
CPU time 0.85 seconds
Started Aug 11 07:12:47 PM PDT 24
Finished Aug 11 07:12:48 PM PDT 24
Peak memory 207540 kb
Host smart-86ff59d4-b102-4d8b-aa2d-7ba2fb89f6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38392
99715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3839299715
Directory /workspace/24.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1025298554
Short name T1390
Test name
Test status
Simulation time 328134309 ps
CPU time 1.32 seconds
Started Aug 11 07:13:02 PM PDT 24
Finished Aug 11 07:13:04 PM PDT 24
Peak memory 207496 kb
Host smart-b7c6e604-dd4c-4f32-b0b4-deec571a9bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10252
98554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1025298554
Directory /workspace/24.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.319473185
Short name T3610
Test name
Test status
Simulation time 398666166 ps
CPU time 1.36 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:03 PM PDT 24
Peak memory 207572 kb
Host smart-167c1279-9c28-40b5-be94-0fcd920cc1e3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=319473185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.319473185
Directory /workspace/24.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/24.usbdev_device_address.3382451535
Short name T3234
Test name
Test status
Simulation time 28446149509 ps
CPU time 44.64 seconds
Started Aug 11 07:12:57 PM PDT 24
Finished Aug 11 07:13:42 PM PDT 24
Peak memory 207860 kb
Host smart-00ec06a7-a4bc-4afa-b88f-6d46607a0b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33824
51535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3382451535
Directory /workspace/24.usbdev_device_address/latest


Test location /workspace/coverage/default/24.usbdev_device_timeout.3574479563
Short name T627
Test name
Test status
Simulation time 6344213731 ps
CPU time 41.17 seconds
Started Aug 11 07:12:51 PM PDT 24
Finished Aug 11 07:13:32 PM PDT 24
Peak memory 207860 kb
Host smart-f5e801db-9f81-4638-a841-d1866ed2a8e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574479563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.3574479563
Directory /workspace/24.usbdev_device_timeout/latest


Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2018258574
Short name T3111
Test name
Test status
Simulation time 765602957 ps
CPU time 2.05 seconds
Started Aug 11 07:12:51 PM PDT 24
Finished Aug 11 07:12:54 PM PDT 24
Peak memory 207476 kb
Host smart-e2c76ecb-b233-46a8-9f24-6d0a2c85b202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20182
58574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2018258574
Directory /workspace/24.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/24.usbdev_disconnected.3360837697
Short name T946
Test name
Test status
Simulation time 144699003 ps
CPU time 0.86 seconds
Started Aug 11 07:12:56 PM PDT 24
Finished Aug 11 07:12:57 PM PDT 24
Peak memory 207536 kb
Host smart-3f3fecaa-20ff-4815-933e-159a0c029fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33608
37697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3360837697
Directory /workspace/24.usbdev_disconnected/latest


Test location /workspace/coverage/default/24.usbdev_enable.3975201201
Short name T3327
Test name
Test status
Simulation time 53522688 ps
CPU time 0.73 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:13:09 PM PDT 24
Peak memory 207464 kb
Host smart-792edb33-7212-4586-a909-434ec3eb0bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39752
01201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3975201201
Directory /workspace/24.usbdev_enable/latest


Test location /workspace/coverage/default/24.usbdev_endpoint_access.3643770440
Short name T3148
Test name
Test status
Simulation time 876491951 ps
CPU time 2.37 seconds
Started Aug 11 07:12:57 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 207684 kb
Host smart-1cc3c535-26a3-415e-aee2-498cfb1b82d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36437
70440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3643770440
Directory /workspace/24.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/24.usbdev_endpoint_types.605032823
Short name T3337
Test name
Test status
Simulation time 272771770 ps
CPU time 1.08 seconds
Started Aug 11 07:13:09 PM PDT 24
Finished Aug 11 07:13:10 PM PDT 24
Peak memory 207540 kb
Host smart-d911b5a3-61f8-4918-aebb-817594baf455
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=605032823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.605032823
Directory /workspace/24.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/24.usbdev_fifo_rst.3810107471
Short name T2223
Test name
Test status
Simulation time 339867038 ps
CPU time 2.62 seconds
Started Aug 11 07:13:16 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207720 kb
Host smart-340201b7-2e64-48aa-a319-b44a9d7dd9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38101
07471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3810107471
Directory /workspace/24.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/24.usbdev_in_iso.535774832
Short name T3044
Test name
Test status
Simulation time 286233176 ps
CPU time 1.3 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:05 PM PDT 24
Peak memory 215952 kb
Host smart-23d34ac7-1895-4909-9013-495cc24b713d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=535774832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.535774832
Directory /workspace/24.usbdev_in_iso/latest


Test location /workspace/coverage/default/24.usbdev_in_stall.4193740832
Short name T2521
Test name
Test status
Simulation time 204464482 ps
CPU time 0.89 seconds
Started Aug 11 07:12:56 PM PDT 24
Finished Aug 11 07:12:57 PM PDT 24
Peak memory 207512 kb
Host smart-62871db1-201f-4109-90a9-4b6d5a50701a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41937
40832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.4193740832
Directory /workspace/24.usbdev_in_stall/latest


Test location /workspace/coverage/default/24.usbdev_in_trans.3104529124
Short name T290
Test name
Test status
Simulation time 177905304 ps
CPU time 0.91 seconds
Started Aug 11 07:13:04 PM PDT 24
Finished Aug 11 07:13:05 PM PDT 24
Peak memory 207548 kb
Host smart-3c251afe-7711-4422-9155-0d84dcc5ac53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31045
29124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3104529124
Directory /workspace/24.usbdev_in_trans/latest


Test location /workspace/coverage/default/24.usbdev_invalid_sync.2241588189
Short name T2903
Test name
Test status
Simulation time 2645340664 ps
CPU time 72.38 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:14:18 PM PDT 24
Peak memory 216120 kb
Host smart-68f3af42-7b85-401b-8e86-3064472cd11e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2241588189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.2241588189
Directory /workspace/24.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/24.usbdev_iso_retraction.1522538753
Short name T4
Test name
Test status
Simulation time 7700365376 ps
CPU time 96.92 seconds
Started Aug 11 07:13:04 PM PDT 24
Finished Aug 11 07:14:41 PM PDT 24
Peak memory 207800 kb
Host smart-dc5a1a0f-7b61-4a41-9f0b-fde9777b36a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1522538753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.1522538753
Directory /workspace/24.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/24.usbdev_link_in_err.1644963328
Short name T1687
Test name
Test status
Simulation time 187952264 ps
CPU time 0.96 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207540 kb
Host smart-e8f285ac-14f3-4f98-8a76-d9be1895c08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16449
63328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.1644963328
Directory /workspace/24.usbdev_link_in_err/latest


Test location /workspace/coverage/default/24.usbdev_link_resume.3705954973
Short name T2941
Test name
Test status
Simulation time 30553367719 ps
CPU time 49.2 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:50 PM PDT 24
Peak memory 207780 kb
Host smart-f85adbf6-442a-4cc6-88fd-8a79730832e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37059
54973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3705954973
Directory /workspace/24.usbdev_link_resume/latest


Test location /workspace/coverage/default/24.usbdev_link_suspend.2358061673
Short name T2129
Test name
Test status
Simulation time 3565012530 ps
CPU time 5.3 seconds
Started Aug 11 07:13:02 PM PDT 24
Finished Aug 11 07:13:08 PM PDT 24
Peak memory 207828 kb
Host smart-fb026f6c-71c4-4915-9b76-e5330c5a1d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23580
61673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2358061673
Directory /workspace/24.usbdev_link_suspend/latest


Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.302982043
Short name T1255
Test name
Test status
Simulation time 3820199612 ps
CPU time 110.02 seconds
Started Aug 11 07:12:57 PM PDT 24
Finished Aug 11 07:14:47 PM PDT 24
Peak memory 218552 kb
Host smart-02992447-cb55-4bd9-bce0-ed63332f6b48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=302982043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.302982043
Directory /workspace/24.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.2663246534
Short name T2282
Test name
Test status
Simulation time 1730023927 ps
CPU time 50.12 seconds
Started Aug 11 07:12:57 PM PDT 24
Finished Aug 11 07:13:47 PM PDT 24
Peak memory 215896 kb
Host smart-be0e3414-3220-4af3-a4f4-b8607c2da61e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2663246534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2663246534
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3953310015
Short name T1412
Test name
Test status
Simulation time 328898517 ps
CPU time 1.11 seconds
Started Aug 11 07:12:53 PM PDT 24
Finished Aug 11 07:12:55 PM PDT 24
Peak memory 207500 kb
Host smart-49fa7d34-6380-4d42-a8ec-780a17cab5b2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3953310015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3953310015
Directory /workspace/24.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3414947120
Short name T1197
Test name
Test status
Simulation time 204704373 ps
CPU time 1.01 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:01 PM PDT 24
Peak memory 207472 kb
Host smart-654f0049-e6be-45ea-9be1-8c539e420064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34149
47120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3414947120
Directory /workspace/24.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.1656164337
Short name T3354
Test name
Test status
Simulation time 1935084306 ps
CPU time 18.58 seconds
Started Aug 11 07:12:57 PM PDT 24
Finished Aug 11 07:13:16 PM PDT 24
Peak memory 224136 kb
Host smart-ca25cd68-3ec3-499b-9ad8-85a62db11bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
64337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.1656164337
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.540094459
Short name T2450
Test name
Test status
Simulation time 2980998204 ps
CPU time 23.47 seconds
Started Aug 11 07:13:04 PM PDT 24
Finished Aug 11 07:13:28 PM PDT 24
Peak memory 217804 kb
Host smart-2d4a4b5e-6795-4fed-983a-5dc56d6bb270
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=540094459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.540094459
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.467270687
Short name T2764
Test name
Test status
Simulation time 147765968 ps
CPU time 0.86 seconds
Started Aug 11 07:13:02 PM PDT 24
Finished Aug 11 07:13:03 PM PDT 24
Peak memory 207500 kb
Host smart-18ffd6cd-a561-41ba-a8b4-9392c4ebb4db
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=467270687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.467270687
Directory /workspace/24.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3577507080
Short name T2438
Test name
Test status
Simulation time 151657769 ps
CPU time 0.84 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:04 PM PDT 24
Peak memory 207556 kb
Host smart-32d0c9b4-8880-468c-9f22-e3e54934c24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35775
07080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3577507080
Directory /workspace/24.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_nak_trans.4218750237
Short name T145
Test name
Test status
Simulation time 172820471 ps
CPU time 0.9 seconds
Started Aug 11 07:12:59 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 207556 kb
Host smart-80a0b184-85d9-45b0-a681-6a587957eb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42187
50237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.4218750237
Directory /workspace/24.usbdev_nak_trans/latest


Test location /workspace/coverage/default/24.usbdev_out_iso.2874681110
Short name T2743
Test name
Test status
Simulation time 146768194 ps
CPU time 0.86 seconds
Started Aug 11 07:13:06 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207584 kb
Host smart-aa5fb93a-9c0b-4d71-b518-50e140acbf03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28746
81110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2874681110
Directory /workspace/24.usbdev_out_iso/latest


Test location /workspace/coverage/default/24.usbdev_out_stall.252377207
Short name T2920
Test name
Test status
Simulation time 208816514 ps
CPU time 0.96 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:13:09 PM PDT 24
Peak memory 207548 kb
Host smart-7bda1798-6043-4dbe-a1a0-4fc8ae4b7894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25237
7207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.252377207
Directory /workspace/24.usbdev_out_stall/latest


Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1306903326
Short name T1542
Test name
Test status
Simulation time 160714994 ps
CPU time 0.86 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207500 kb
Host smart-b72ce8e5-4e6a-4557-974d-887ee844fe7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13069
03326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1306903326
Directory /workspace/24.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/24.usbdev_pending_in_trans.4258914705
Short name T2022
Test name
Test status
Simulation time 206556039 ps
CPU time 0.94 seconds
Started Aug 11 07:13:07 PM PDT 24
Finished Aug 11 07:13:08 PM PDT 24
Peak memory 207544 kb
Host smart-ca4a9bbc-0329-4299-8c5f-d794af1394e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42589
14705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.4258914705
Directory /workspace/24.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1724060285
Short name T2039
Test name
Test status
Simulation time 257776790 ps
CPU time 1.04 seconds
Started Aug 11 07:12:56 PM PDT 24
Finished Aug 11 07:12:57 PM PDT 24
Peak memory 207488 kb
Host smart-25d6b9c6-2505-450a-af00-6652a729985d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1724060285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1724060285
Directory /workspace/24.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.686571317
Short name T3404
Test name
Test status
Simulation time 159034650 ps
CPU time 0.9 seconds
Started Aug 11 07:13:06 PM PDT 24
Finished Aug 11 07:13:07 PM PDT 24
Peak memory 207516 kb
Host smart-df3d0f57-ad13-45c8-bc30-7724c2f8c8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68657
1317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.686571317
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2100865133
Short name T3598
Test name
Test status
Simulation time 48892326 ps
CPU time 0.74 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:04 PM PDT 24
Peak memory 207464 kb
Host smart-fb2c1c3c-ddbf-4148-b8bf-c517830bd944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21008
65133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2100865133
Directory /workspace/24.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1435047115
Short name T3130
Test name
Test status
Simulation time 10346511512 ps
CPU time 25.68 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:29 PM PDT 24
Peak memory 224108 kb
Host smart-af1b1384-2c1e-424a-8d32-2265ed649392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14350
47115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1435047115
Directory /workspace/24.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/24.usbdev_pkt_received.2249386933
Short name T3496
Test name
Test status
Simulation time 185825717 ps
CPU time 0.95 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:02 PM PDT 24
Peak memory 207436 kb
Host smart-f71d103f-e99f-4f93-ba5b-4bf8404ee1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22493
86933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2249386933
Directory /workspace/24.usbdev_pkt_received/latest


Test location /workspace/coverage/default/24.usbdev_pkt_sent.4250763278
Short name T2009
Test name
Test status
Simulation time 205634482 ps
CPU time 0.98 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:02 PM PDT 24
Peak memory 207488 kb
Host smart-aaf64538-9445-499b-9bf2-135baac15b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42507
63278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.4250763278
Directory /workspace/24.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.103491043
Short name T1325
Test name
Test status
Simulation time 164048809 ps
CPU time 0.89 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:02 PM PDT 24
Peak memory 207584 kb
Host smart-fe333837-e407-4fb9-b1de-671b77f173da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10349
1043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.103491043
Directory /workspace/24.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.1924128051
Short name T2404
Test name
Test status
Simulation time 180043535 ps
CPU time 0.89 seconds
Started Aug 11 07:12:55 PM PDT 24
Finished Aug 11 07:12:56 PM PDT 24
Peak memory 207564 kb
Host smart-a31af564-2019-4146-9faf-530c63e5e878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19241
28051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1924128051
Directory /workspace/24.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3889719337
Short name T1067
Test name
Test status
Simulation time 195332928 ps
CPU time 0.89 seconds
Started Aug 11 07:12:59 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 207476 kb
Host smart-a2f545ed-ada3-4918-92cb-919b87a358ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38897
19337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3889719337
Directory /workspace/24.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/24.usbdev_setup_stage.2755561819
Short name T1014
Test name
Test status
Simulation time 190719752 ps
CPU time 0.94 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:01 PM PDT 24
Peak memory 207536 kb
Host smart-63097b6c-02c4-4f72-8014-d51d1d80c7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27555
61819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2755561819
Directory /workspace/24.usbdev_setup_stage/latest


Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.4249894736
Short name T3578
Test name
Test status
Simulation time 207874321 ps
CPU time 0.98 seconds
Started Aug 11 07:13:04 PM PDT 24
Finished Aug 11 07:13:05 PM PDT 24
Peak memory 207572 kb
Host smart-6a97306e-956c-4bcd-a0e6-91a725bd69d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42498
94736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.4249894736
Directory /workspace/24.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/24.usbdev_smoke.292080401
Short name T707
Test name
Test status
Simulation time 222332115 ps
CPU time 1 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:01 PM PDT 24
Peak memory 207544 kb
Host smart-8171407b-0bb4-4713-aff7-a209243f527d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29208
0401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.292080401
Directory /workspace/24.usbdev_smoke/latest


Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1425362171
Short name T1425
Test name
Test status
Simulation time 3641170172 ps
CPU time 104.94 seconds
Started Aug 11 07:13:02 PM PDT 24
Finished Aug 11 07:14:47 PM PDT 24
Peak memory 217892 kb
Host smart-068ff96c-f758-4db9-8e2e-570b2e70f7db
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1425362171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1425362171
Directory /workspace/24.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1822139096
Short name T3349
Test name
Test status
Simulation time 237523846 ps
CPU time 0.94 seconds
Started Aug 11 07:13:09 PM PDT 24
Finished Aug 11 07:13:10 PM PDT 24
Peak memory 207556 kb
Host smart-e723d273-ca1f-4e5c-b7c1-50dc8201d1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18221
39096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1822139096
Directory /workspace/24.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/24.usbdev_stall_trans.634778590
Short name T2331
Test name
Test status
Simulation time 175621297 ps
CPU time 0.88 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207612 kb
Host smart-0ead69bf-d756-4cb2-9155-274cc114dd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63477
8590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.634778590
Directory /workspace/24.usbdev_stall_trans/latest


Test location /workspace/coverage/default/24.usbdev_stream_len_max.3436309213
Short name T3205
Test name
Test status
Simulation time 1020744148 ps
CPU time 2.64 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207668 kb
Host smart-5ff9c2aa-00cf-40c7-b2cd-ce0c56b05522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34363
09213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3436309213
Directory /workspace/24.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/24.usbdev_streaming_out.4290119468
Short name T2884
Test name
Test status
Simulation time 3132747802 ps
CPU time 25.18 seconds
Started Aug 11 07:13:02 PM PDT 24
Finished Aug 11 07:13:27 PM PDT 24
Peak memory 216044 kb
Host smart-52c79f19-e467-47b8-9a88-3c1ef6d6d70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42901
19468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.4290119468
Directory /workspace/24.usbdev_streaming_out/latest


Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.211049665
Short name T3579
Test name
Test status
Simulation time 827173160 ps
CPU time 5.45 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:07 PM PDT 24
Peak memory 207700 kb
Host smart-d1c0ca3a-e345-4856-aaa0-e35d9cf3631d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211049665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_host
_handshake.211049665
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/24.usbdev_tx_rx_disruption.360617996
Short name T3098
Test name
Test status
Simulation time 524366704 ps
CPU time 1.57 seconds
Started Aug 11 07:12:57 PM PDT 24
Finished Aug 11 07:12:59 PM PDT 24
Peak memory 207576 kb
Host smart-ce8fdad9-34e9-47ce-b189-df4a1d2b4009
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360617996 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.usbdev_tx_rx_disruption.360617996
Directory /workspace/24.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/240.usbdev_tx_rx_disruption.2392553647
Short name T3332
Test name
Test status
Simulation time 472909345 ps
CPU time 1.46 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207776 kb
Host smart-e2c2d7b2-ead0-4cfe-a3c6-029d90af2304
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392553647 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.usbdev_tx_rx_disruption.2392553647
Directory /workspace/240.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/241.usbdev_tx_rx_disruption.3454489670
Short name T2011
Test name
Test status
Simulation time 434128787 ps
CPU time 1.37 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:32 PM PDT 24
Peak memory 207564 kb
Host smart-f2d51a13-165f-46a4-98fc-a59301a60949
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454489670 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.usbdev_tx_rx_disruption.3454489670
Directory /workspace/241.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/242.usbdev_tx_rx_disruption.2241511487
Short name T1967
Test name
Test status
Simulation time 532067300 ps
CPU time 1.64 seconds
Started Aug 11 07:17:32 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207564 kb
Host smart-5b23ce08-4764-4c7e-b956-58c4be1f477f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241511487 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.usbdev_tx_rx_disruption.2241511487
Directory /workspace/242.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/243.usbdev_tx_rx_disruption.3256540668
Short name T3377
Test name
Test status
Simulation time 454729783 ps
CPU time 1.57 seconds
Started Aug 11 07:17:41 PM PDT 24
Finished Aug 11 07:17:47 PM PDT 24
Peak memory 207580 kb
Host smart-1fdbe7f9-3d08-4ca3-9f54-1bd3cb1b1ff2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256540668 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.usbdev_tx_rx_disruption.3256540668
Directory /workspace/243.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/244.usbdev_tx_rx_disruption.93129855
Short name T1894
Test name
Test status
Simulation time 645164526 ps
CPU time 1.72 seconds
Started Aug 11 07:17:46 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207456 kb
Host smart-d4d9b4ad-1f74-4843-b309-9066bee14151
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93129855 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 244.usbdev_tx_rx_disruption.93129855
Directory /workspace/244.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/245.usbdev_tx_rx_disruption.2453307334
Short name T2376
Test name
Test status
Simulation time 525280589 ps
CPU time 1.72 seconds
Started Aug 11 07:17:40 PM PDT 24
Finished Aug 11 07:17:47 PM PDT 24
Peak memory 207456 kb
Host smart-727bad6a-6cf3-4cf7-ae03-47a51e2764ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453307334 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 245.usbdev_tx_rx_disruption.2453307334
Directory /workspace/245.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/246.usbdev_tx_rx_disruption.3259758400
Short name T572
Test name
Test status
Simulation time 490565840 ps
CPU time 1.52 seconds
Started Aug 11 07:17:50 PM PDT 24
Finished Aug 11 07:17:51 PM PDT 24
Peak memory 207520 kb
Host smart-49a26720-094d-44e0-bf46-af82e843397b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259758400 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.usbdev_tx_rx_disruption.3259758400
Directory /workspace/246.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/247.usbdev_tx_rx_disruption.2028827020
Short name T904
Test name
Test status
Simulation time 620193418 ps
CPU time 1.7 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207592 kb
Host smart-bfe1fcdf-9774-4707-973c-fb9d61900312
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028827020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.usbdev_tx_rx_disruption.2028827020
Directory /workspace/247.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/248.usbdev_tx_rx_disruption.1871662071
Short name T3597
Test name
Test status
Simulation time 469483662 ps
CPU time 1.48 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207592 kb
Host smart-9a2cfd4f-7430-4007-a336-68b8ab8c9527
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871662071 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.usbdev_tx_rx_disruption.1871662071
Directory /workspace/248.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/249.usbdev_tx_rx_disruption.1879066290
Short name T3408
Test name
Test status
Simulation time 526117962 ps
CPU time 1.84 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:35 PM PDT 24
Peak memory 207520 kb
Host smart-258f646a-d892-4d0e-be44-ba9b608669a0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879066290 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.usbdev_tx_rx_disruption.1879066290
Directory /workspace/249.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/25.usbdev_alert_test.3879879642
Short name T2323
Test name
Test status
Simulation time 36197260 ps
CPU time 0.7 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207584 kb
Host smart-10edfdd0-4b73-4f1a-b606-7e669e931f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3879879642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.3879879642
Directory /workspace/25.usbdev_alert_test/latest


Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1814295281
Short name T2263
Test name
Test status
Simulation time 6273984095 ps
CPU time 8.46 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:13:17 PM PDT 24
Peak memory 215940 kb
Host smart-0606164e-c017-4f1e-9792-5fa21feb3522
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814295281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.1814295281
Directory /workspace/25.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2985489958
Short name T1150
Test name
Test status
Simulation time 21340220385 ps
CPU time 25.64 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207764 kb
Host smart-bc7a078f-7cb9-4933-95a5-8fea71d6db9f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985489958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2985489958
Directory /workspace/25.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.3983580206
Short name T2131
Test name
Test status
Simulation time 30538091492 ps
CPU time 34.35 seconds
Started Aug 11 07:12:56 PM PDT 24
Finished Aug 11 07:13:30 PM PDT 24
Peak memory 207848 kb
Host smart-5137da56-edf8-4685-aa2e-83d9ea68e806
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983580206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.3983580206
Directory /workspace/25.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/25.usbdev_av_buffer.2944660645
Short name T1639
Test name
Test status
Simulation time 159481434 ps
CPU time 0.87 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:13:09 PM PDT 24
Peak memory 207560 kb
Host smart-2c314453-bee1-4b4a-b2be-5b09c0807e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29446
60645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2944660645
Directory /workspace/25.usbdev_av_buffer/latest


Test location /workspace/coverage/default/25.usbdev_bitstuff_err.31253451
Short name T1582
Test name
Test status
Simulation time 146096037 ps
CPU time 0.91 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:02 PM PDT 24
Peak memory 207512 kb
Host smart-f8233955-07c7-41af-b380-d7f0513773a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31253
451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.31253451
Directory /workspace/25.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.904658151
Short name T2134
Test name
Test status
Simulation time 413868844 ps
CPU time 1.52 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:07 PM PDT 24
Peak memory 207584 kb
Host smart-43dc839e-d8ca-42be-9d51-ee39e837cc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90465
8151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.904658151
Directory /workspace/25.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2871436028
Short name T988
Test name
Test status
Simulation time 794065718 ps
CPU time 2.14 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:05 PM PDT 24
Peak memory 207788 kb
Host smart-d143d645-3a63-47ab-b5ec-d3c308756924
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2871436028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2871436028
Directory /workspace/25.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/25.usbdev_device_address.2355113362
Short name T1648
Test name
Test status
Simulation time 47438364573 ps
CPU time 72.71 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207776 kb
Host smart-72698ff0-f59c-4e33-99c2-27fd1bc5a2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23551
13362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2355113362
Directory /workspace/25.usbdev_device_address/latest


Test location /workspace/coverage/default/25.usbdev_device_timeout.3520156881
Short name T1196
Test name
Test status
Simulation time 1569934766 ps
CPU time 35.98 seconds
Started Aug 11 07:13:06 PM PDT 24
Finished Aug 11 07:13:42 PM PDT 24
Peak memory 207740 kb
Host smart-84a79902-0bf4-4161-bc15-0f5b3ac5bc81
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520156881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.3520156881
Directory /workspace/25.usbdev_device_timeout/latest


Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3764635879
Short name T2886
Test name
Test status
Simulation time 401027721 ps
CPU time 1.31 seconds
Started Aug 11 07:13:09 PM PDT 24
Finished Aug 11 07:13:10 PM PDT 24
Peak memory 207452 kb
Host smart-384c90b6-2a17-4072-bb46-930ddb5a1469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37646
35879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3764635879
Directory /workspace/25.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/25.usbdev_disconnected.3235035058
Short name T1814
Test name
Test status
Simulation time 175337556 ps
CPU time 0.88 seconds
Started Aug 11 07:13:06 PM PDT 24
Finished Aug 11 07:13:07 PM PDT 24
Peak memory 207448 kb
Host smart-108200fe-aa37-4f66-87d9-ee9ffd4b96f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32350
35058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3235035058
Directory /workspace/25.usbdev_disconnected/latest


Test location /workspace/coverage/default/25.usbdev_enable.3749500048
Short name T3053
Test name
Test status
Simulation time 63308461 ps
CPU time 0.75 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:02 PM PDT 24
Peak memory 207556 kb
Host smart-ee5dbc48-5f5e-4e20-a556-9eda5aa924da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37495
00048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3749500048
Directory /workspace/25.usbdev_enable/latest


Test location /workspace/coverage/default/25.usbdev_endpoint_access.3379725796
Short name T3042
Test name
Test status
Simulation time 859226991 ps
CPU time 2.38 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 207652 kb
Host smart-37784055-0507-4ec1-9034-150f7782fd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33797
25796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.3379725796
Directory /workspace/25.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/25.usbdev_endpoint_types.2731034004
Short name T2778
Test name
Test status
Simulation time 306827848 ps
CPU time 1.09 seconds
Started Aug 11 07:13:04 PM PDT 24
Finished Aug 11 07:13:05 PM PDT 24
Peak memory 207524 kb
Host smart-5aebbb12-8fa9-401e-a86f-1c2e51367f7e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2731034004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.2731034004
Directory /workspace/25.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/25.usbdev_fifo_rst.364685926
Short name T2325
Test name
Test status
Simulation time 153834591 ps
CPU time 1.51 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:04 PM PDT 24
Peak memory 207680 kb
Host smart-0e99eaf7-5f17-4514-b506-dfe687322cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36468
5926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.364685926
Directory /workspace/25.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/25.usbdev_in_iso.1718782879
Short name T1167
Test name
Test status
Simulation time 235189860 ps
CPU time 1.08 seconds
Started Aug 11 07:12:59 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 215920 kb
Host smart-c2e04e94-8697-4809-a3e3-d915a1838f62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1718782879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1718782879
Directory /workspace/25.usbdev_in_iso/latest


Test location /workspace/coverage/default/25.usbdev_in_stall.33102394
Short name T1912
Test name
Test status
Simulation time 138413226 ps
CPU time 0.79 seconds
Started Aug 11 07:13:06 PM PDT 24
Finished Aug 11 07:13:07 PM PDT 24
Peak memory 207520 kb
Host smart-94a2509f-61a3-4625-833e-f1b0bda920f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33102
394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.33102394
Directory /workspace/25.usbdev_in_stall/latest


Test location /workspace/coverage/default/25.usbdev_in_trans.1845474811
Short name T3357
Test name
Test status
Simulation time 210237080 ps
CPU time 0.96 seconds
Started Aug 11 07:13:16 PM PDT 24
Finished Aug 11 07:13:17 PM PDT 24
Peak memory 207524 kb
Host smart-84ba44a0-e5ba-49e3-9565-31825c2a7407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18454
74811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1845474811
Directory /workspace/25.usbdev_in_trans/latest


Test location /workspace/coverage/default/25.usbdev_invalid_sync.2011671446
Short name T1016
Test name
Test status
Simulation time 3781417642 ps
CPU time 37.84 seconds
Started Aug 11 07:13:06 PM PDT 24
Finished Aug 11 07:13:44 PM PDT 24
Peak memory 218476 kb
Host smart-2cb79588-1cf5-462a-b8c7-309fa423386a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2011671446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2011671446
Directory /workspace/25.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/25.usbdev_iso_retraction.870936459
Short name T2988
Test name
Test status
Simulation time 6921670097 ps
CPU time 90.46 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:14:41 PM PDT 24
Peak memory 207820 kb
Host smart-5b4d89e2-6f73-4c29-abe5-66ba4456c716
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=870936459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.870936459
Directory /workspace/25.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/25.usbdev_link_in_err.2693301297
Short name T1773
Test name
Test status
Simulation time 202028037 ps
CPU time 0.9 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:01 PM PDT 24
Peak memory 207528 kb
Host smart-636eeb7b-7192-4acb-a8fd-de7d33492532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26933
01297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2693301297
Directory /workspace/25.usbdev_link_in_err/latest


Test location /workspace/coverage/default/25.usbdev_link_resume.737169343
Short name T1890
Test name
Test status
Simulation time 6768263006 ps
CPU time 10.44 seconds
Started Aug 11 07:13:06 PM PDT 24
Finished Aug 11 07:13:22 PM PDT 24
Peak memory 216220 kb
Host smart-4540c780-dae9-4ce6-871b-32520a047c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73716
9343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.737169343
Directory /workspace/25.usbdev_link_resume/latest


Test location /workspace/coverage/default/25.usbdev_link_suspend.3430014430
Short name T2632
Test name
Test status
Simulation time 9535659830 ps
CPU time 13.85 seconds
Started Aug 11 07:13:09 PM PDT 24
Finished Aug 11 07:13:23 PM PDT 24
Peak memory 207788 kb
Host smart-28deaab4-3048-4654-8eef-185ab9fe9ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34300
14430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3430014430
Directory /workspace/25.usbdev_link_suspend/latest


Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.759993334
Short name T399
Test name
Test status
Simulation time 3541691351 ps
CPU time 26.85 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:30 PM PDT 24
Peak memory 218664 kb
Host smart-0199024b-0604-4d5d-8f02-a16ee7d7fb9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=759993334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.759993334
Directory /workspace/25.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3863166749
Short name T2170
Test name
Test status
Simulation time 1966535488 ps
CPU time 55.49 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 215984 kb
Host smart-3238ac16-bdf8-4ca7-9caa-d971c14744e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3863166749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3863166749
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1365678474
Short name T965
Test name
Test status
Simulation time 253308986 ps
CPU time 1 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:01 PM PDT 24
Peak memory 207500 kb
Host smart-f1523d61-3375-49be-bc4b-5d85282cf0dc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1365678474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1365678474
Directory /workspace/25.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1986310716
Short name T2925
Test name
Test status
Simulation time 207365287 ps
CPU time 0.97 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:01 PM PDT 24
Peak memory 207528 kb
Host smart-d819f771-b6b8-408e-a4c6-61cd0749bb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19863
10716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1986310716
Directory /workspace/25.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2882335016
Short name T3549
Test name
Test status
Simulation time 1743755714 ps
CPU time 13.54 seconds
Started Aug 11 07:13:04 PM PDT 24
Finished Aug 11 07:13:18 PM PDT 24
Peak memory 217348 kb
Host smart-6b9404d7-d808-4ce6-9ef1-ae2ae2a9bd46
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2882335016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2882335016
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.123372769
Short name T3594
Test name
Test status
Simulation time 205816420 ps
CPU time 0.96 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207540 kb
Host smart-2045a1bb-1257-44a3-86c9-5539cc93df10
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=123372769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.123372769
Directory /workspace/25.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.867835398
Short name T1106
Test name
Test status
Simulation time 148069180 ps
CPU time 0.85 seconds
Started Aug 11 07:13:09 PM PDT 24
Finished Aug 11 07:13:10 PM PDT 24
Peak memory 207548 kb
Host smart-e4f26ccb-12ff-422d-818e-1cc2bc2d04c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86783
5398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.867835398
Directory /workspace/25.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_out_iso.4038762081
Short name T1347
Test name
Test status
Simulation time 204037568 ps
CPU time 0.96 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:07 PM PDT 24
Peak memory 207496 kb
Host smart-ed734658-f88b-44c1-96d1-b62caf93e491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40387
62081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.4038762081
Directory /workspace/25.usbdev_out_iso/latest


Test location /workspace/coverage/default/25.usbdev_out_stall.1143938598
Short name T1523
Test name
Test status
Simulation time 155914527 ps
CPU time 0.91 seconds
Started Aug 11 07:13:16 PM PDT 24
Finished Aug 11 07:13:17 PM PDT 24
Peak memory 207572 kb
Host smart-ea277bee-72de-46ee-8e93-78b75514406f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11439
38598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1143938598
Directory /workspace/25.usbdev_out_stall/latest


Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1407032998
Short name T1771
Test name
Test status
Simulation time 218481597 ps
CPU time 0.99 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:04 PM PDT 24
Peak memory 207548 kb
Host smart-566d6a8a-518e-4717-83e8-ab225e2a3a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14070
32998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1407032998
Directory /workspace/25.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3594234308
Short name T1651
Test name
Test status
Simulation time 144447054 ps
CPU time 0.8 seconds
Started Aug 11 07:13:09 PM PDT 24
Finished Aug 11 07:13:10 PM PDT 24
Peak memory 207568 kb
Host smart-1083e902-2b93-4cb9-921f-3511d4b22dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35942
34308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3594234308
Directory /workspace/25.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2170379448
Short name T1321
Test name
Test status
Simulation time 227760757 ps
CPU time 1.08 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207504 kb
Host smart-f18125a6-264d-4d56-81c3-1f25e25a90dc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2170379448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2170379448
Directory /workspace/25.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1056530051
Short name T2403
Test name
Test status
Simulation time 144385125 ps
CPU time 0.82 seconds
Started Aug 11 07:12:59 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 207520 kb
Host smart-ac1f7178-ab42-424d-8977-d9aad9656eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10565
30051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1056530051
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3080554434
Short name T1398
Test name
Test status
Simulation time 66743833 ps
CPU time 0.71 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:01 PM PDT 24
Peak memory 207532 kb
Host smart-29ca2aea-ed8c-4ee9-a73c-b0290fef7bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30805
54434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3080554434
Directory /workspace/25.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3980067567
Short name T958
Test name
Test status
Simulation time 8447842438 ps
CPU time 22.55 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 216032 kb
Host smart-394d886b-c447-4a1b-83f7-575a0b2c20c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39800
67567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3980067567
Directory /workspace/25.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/25.usbdev_pkt_received.3207355519
Short name T737
Test name
Test status
Simulation time 165485361 ps
CPU time 0.87 seconds
Started Aug 11 07:13:04 PM PDT 24
Finished Aug 11 07:13:05 PM PDT 24
Peak memory 207552 kb
Host smart-90463440-ead6-4b04-970b-e97e8c2e0824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
55519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3207355519
Directory /workspace/25.usbdev_pkt_received/latest


Test location /workspace/coverage/default/25.usbdev_pkt_sent.57595082
Short name T559
Test name
Test status
Simulation time 229235543 ps
CPU time 1.03 seconds
Started Aug 11 07:12:58 PM PDT 24
Finished Aug 11 07:12:59 PM PDT 24
Peak memory 207572 kb
Host smart-bbda3d17-c612-435e-a6bc-c3b56802c365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57595
082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.57595082
Directory /workspace/25.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2458889060
Short name T1454
Test name
Test status
Simulation time 218413440 ps
CPU time 1 seconds
Started Aug 11 07:13:03 PM PDT 24
Finished Aug 11 07:13:04 PM PDT 24
Peak memory 207484 kb
Host smart-ca76b803-b0e5-486f-b6a0-5fe43a779ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24588
89060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2458889060
Directory /workspace/25.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.1531477981
Short name T2108
Test name
Test status
Simulation time 186749002 ps
CPU time 0.92 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207544 kb
Host smart-651613f7-57df-4ffa-9f65-13153c416af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15314
77981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.1531477981
Directory /workspace/25.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_rx_crc_err.912779698
Short name T3386
Test name
Test status
Simulation time 211200523 ps
CPU time 0.92 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207568 kb
Host smart-86dfc907-2f92-428c-8a78-65e84428830f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91277
9698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.912779698
Directory /workspace/25.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/25.usbdev_rx_full.729448801
Short name T3132
Test name
Test status
Simulation time 314801793 ps
CPU time 1.22 seconds
Started Aug 11 07:13:15 PM PDT 24
Finished Aug 11 07:13:17 PM PDT 24
Peak memory 207544 kb
Host smart-884cafe6-c9c0-4ff6-9593-51c7ec74256a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72944
8801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.729448801
Directory /workspace/25.usbdev_rx_full/latest


Test location /workspace/coverage/default/25.usbdev_setup_stage.936769944
Short name T3361
Test name
Test status
Simulation time 145636014 ps
CPU time 0.88 seconds
Started Aug 11 07:12:59 PM PDT 24
Finished Aug 11 07:13:00 PM PDT 24
Peak memory 207540 kb
Host smart-166ddc90-d7ef-4d80-8d4a-b2e297070a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93676
9944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.936769944
Directory /workspace/25.usbdev_setup_stage/latest


Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3535761574
Short name T3211
Test name
Test status
Simulation time 156911118 ps
CPU time 0.91 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 207572 kb
Host smart-f18cd213-f0f4-4aca-ae4b-d54f1bfee737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35357
61574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3535761574
Directory /workspace/25.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/25.usbdev_smoke.2255338297
Short name T1452
Test name
Test status
Simulation time 236764526 ps
CPU time 1.07 seconds
Started Aug 11 07:13:04 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207560 kb
Host smart-9825eaf9-c653-4492-9aa4-b81d00e788f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22553
38297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2255338297
Directory /workspace/25.usbdev_smoke/latest


Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.446081789
Short name T2427
Test name
Test status
Simulation time 2790164834 ps
CPU time 79.47 seconds
Started Aug 11 07:13:02 PM PDT 24
Finished Aug 11 07:14:22 PM PDT 24
Peak memory 216132 kb
Host smart-27ad789c-8e09-49f5-aff5-e18f57a160bd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=446081789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.446081789
Directory /workspace/25.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2783460664
Short name T2451
Test name
Test status
Simulation time 184705393 ps
CPU time 0.92 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207600 kb
Host smart-8bb74527-674e-4b5a-949b-49ce7e3c4034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27834
60664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2783460664
Directory /workspace/25.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/25.usbdev_stall_trans.942450360
Short name T734
Test name
Test status
Simulation time 169053031 ps
CPU time 0.88 seconds
Started Aug 11 07:13:06 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207540 kb
Host smart-3a59bb16-bbd8-44f6-9c45-a37f41265c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94245
0360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.942450360
Directory /workspace/25.usbdev_stall_trans/latest


Test location /workspace/coverage/default/25.usbdev_stream_len_max.2960878294
Short name T605
Test name
Test status
Simulation time 813976289 ps
CPU time 2.08 seconds
Started Aug 11 07:13:01 PM PDT 24
Finished Aug 11 07:13:03 PM PDT 24
Peak memory 207452 kb
Host smart-aee838b9-1ffa-48e6-9179-110814edb0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29608
78294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2960878294
Directory /workspace/25.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/25.usbdev_streaming_out.4123691433
Short name T2322
Test name
Test status
Simulation time 2987586838 ps
CPU time 21.45 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:22 PM PDT 24
Peak memory 217792 kb
Host smart-ecc86226-4e51-49ee-983f-5e0b9f3c23fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41236
91433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.4123691433
Directory /workspace/25.usbdev_streaming_out/latest


Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.3834291421
Short name T625
Test name
Test status
Simulation time 4412363433 ps
CPU time 31.41 seconds
Started Aug 11 07:13:00 PM PDT 24
Finished Aug 11 07:13:32 PM PDT 24
Peak memory 207856 kb
Host smart-2cf2e707-5090-4228-ba5c-da26d310161d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834291421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.3834291421
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/25.usbdev_tx_rx_disruption.1635310195
Short name T252
Test name
Test status
Simulation time 718517940 ps
CPU time 1.84 seconds
Started Aug 11 07:13:07 PM PDT 24
Finished Aug 11 07:13:09 PM PDT 24
Peak memory 207548 kb
Host smart-9b539b35-48a2-4a9e-9fb6-dff3e84ba18b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635310195 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.usbdev_tx_rx_disruption.1635310195
Directory /workspace/25.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/250.usbdev_tx_rx_disruption.945390417
Short name T1478
Test name
Test status
Simulation time 622234016 ps
CPU time 1.79 seconds
Started Aug 11 07:17:32 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207596 kb
Host smart-dd6af5b8-1c74-4ba8-a616-05aede576278
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945390417 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 250.usbdev_tx_rx_disruption.945390417
Directory /workspace/250.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/251.usbdev_tx_rx_disruption.2665565519
Short name T190
Test name
Test status
Simulation time 664408842 ps
CPU time 1.79 seconds
Started Aug 11 07:17:46 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207520 kb
Host smart-5954b4bd-fcc8-4dbc-8f43-9c1ae667d8cd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665565519 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.usbdev_tx_rx_disruption.2665565519
Directory /workspace/251.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/252.usbdev_tx_rx_disruption.870003249
Short name T1823
Test name
Test status
Simulation time 542849689 ps
CPU time 1.51 seconds
Started Aug 11 07:17:32 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207580 kb
Host smart-e7446128-9d70-4536-aed7-ab021d1ff2f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870003249 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 252.usbdev_tx_rx_disruption.870003249
Directory /workspace/252.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/253.usbdev_tx_rx_disruption.1360723319
Short name T1926
Test name
Test status
Simulation time 583677263 ps
CPU time 1.73 seconds
Started Aug 11 07:17:30 PM PDT 24
Finished Aug 11 07:17:32 PM PDT 24
Peak memory 207516 kb
Host smart-3ab1169f-6869-4029-9485-d73bd5f41f3c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360723319 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.usbdev_tx_rx_disruption.1360723319
Directory /workspace/253.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/254.usbdev_tx_rx_disruption.2503874513
Short name T3608
Test name
Test status
Simulation time 518111155 ps
CPU time 1.48 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:41 PM PDT 24
Peak memory 207540 kb
Host smart-66ffe888-e209-474f-8865-ca9f89c4f4f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503874513 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.usbdev_tx_rx_disruption.2503874513
Directory /workspace/254.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/255.usbdev_tx_rx_disruption.2803001937
Short name T1158
Test name
Test status
Simulation time 550855911 ps
CPU time 1.65 seconds
Started Aug 11 07:17:46 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207540 kb
Host smart-f8afda3f-ac3f-4b94-b00d-ef00914b591c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803001937 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.usbdev_tx_rx_disruption.2803001937
Directory /workspace/255.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/256.usbdev_tx_rx_disruption.1615238409
Short name T2270
Test name
Test status
Simulation time 566435378 ps
CPU time 1.65 seconds
Started Aug 11 07:17:43 PM PDT 24
Finished Aug 11 07:17:45 PM PDT 24
Peak memory 207568 kb
Host smart-8871468c-8514-4fd7-9f47-fee8798639be
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615238409 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.usbdev_tx_rx_disruption.1615238409
Directory /workspace/256.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/257.usbdev_tx_rx_disruption.2037136139
Short name T2979
Test name
Test status
Simulation time 436878481 ps
CPU time 1.45 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:32 PM PDT 24
Peak memory 207492 kb
Host smart-1b3e774e-cf2d-4217-a28f-d8e4903eac22
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037136139 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.usbdev_tx_rx_disruption.2037136139
Directory /workspace/257.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/258.usbdev_tx_rx_disruption.3302137540
Short name T3289
Test name
Test status
Simulation time 540584409 ps
CPU time 1.62 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207528 kb
Host smart-3c4a174c-2e7c-4c20-8473-a4b2f1ef4b98
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302137540 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.usbdev_tx_rx_disruption.3302137540
Directory /workspace/258.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/259.usbdev_tx_rx_disruption.2742456841
Short name T3318
Test name
Test status
Simulation time 625441141 ps
CPU time 1.65 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:41 PM PDT 24
Peak memory 207540 kb
Host smart-496ac468-9340-4cdd-bc6f-436d8452e5a4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742456841 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.usbdev_tx_rx_disruption.2742456841
Directory /workspace/259.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/26.usbdev_alert_test.598192330
Short name T3367
Test name
Test status
Simulation time 89380486 ps
CPU time 0.74 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 207560 kb
Host smart-0e2276cb-afa3-40c1-bb86-d9f2440d0f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=598192330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.598192330
Directory /workspace/26.usbdev_alert_test/latest


Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.620502798
Short name T2208
Test name
Test status
Simulation time 5490677398 ps
CPU time 9.16 seconds
Started Aug 11 07:13:07 PM PDT 24
Finished Aug 11 07:13:16 PM PDT 24
Peak memory 215972 kb
Host smart-f8e55e8f-aa24-4ec9-ad41-abeff0c3bfc0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620502798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ao
n_wake_disconnect.620502798
Directory /workspace/26.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2324235976
Short name T3355
Test name
Test status
Simulation time 14113625294 ps
CPU time 17.71 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:29 PM PDT 24
Peak memory 216016 kb
Host smart-a4cff89f-c04f-4e63-9e16-ff66ec472e8f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324235976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2324235976
Directory /workspace/26.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.423534143
Short name T3547
Test name
Test status
Simulation time 25214122222 ps
CPU time 37.46 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:56 PM PDT 24
Peak memory 216036 kb
Host smart-1f8ce75c-b2e4-4cd1-a08b-7dadbb066cae
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423534143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ao
n_wake_resume.423534143
Directory /workspace/26.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/26.usbdev_av_buffer.1409705389
Short name T1543
Test name
Test status
Simulation time 170490098 ps
CPU time 0.86 seconds
Started Aug 11 07:13:16 PM PDT 24
Finished Aug 11 07:13:17 PM PDT 24
Peak memory 207552 kb
Host smart-dbac3efd-a526-402c-97f2-f8117ae3e073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14097
05389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1409705389
Directory /workspace/26.usbdev_av_buffer/latest


Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2372135749
Short name T2856
Test name
Test status
Simulation time 148666552 ps
CPU time 0.88 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:13:09 PM PDT 24
Peak memory 207536 kb
Host smart-314d7da2-530c-4f70-9a43-0f48e5dc276f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23721
35749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2372135749
Directory /workspace/26.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.540676730
Short name T2680
Test name
Test status
Simulation time 256708288 ps
CPU time 1.12 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207524 kb
Host smart-03d08408-59c1-43da-9703-294798f5b364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54067
6730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.540676730
Directory /workspace/26.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.106753893
Short name T356
Test name
Test status
Simulation time 1077618354 ps
CPU time 2.97 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 207692 kb
Host smart-8b48ed39-afab-466e-8810-a9dda5f8e1fb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=106753893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.106753893
Directory /workspace/26.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/26.usbdev_device_address.2629183096
Short name T182
Test name
Test status
Simulation time 17678006469 ps
CPU time 28.97 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:46 PM PDT 24
Peak memory 207888 kb
Host smart-a35bfb88-853a-48b6-b485-a45af76dab2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26291
83096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2629183096
Directory /workspace/26.usbdev_device_address/latest


Test location /workspace/coverage/default/26.usbdev_device_timeout.2746237585
Short name T1151
Test name
Test status
Simulation time 969268929 ps
CPU time 19.54 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:30 PM PDT 24
Peak memory 207728 kb
Host smart-b69b6b76-deed-4f2a-8799-b7b8cd580b66
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746237585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.2746237585
Directory /workspace/26.usbdev_device_timeout/latest


Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3446975650
Short name T1937
Test name
Test status
Simulation time 1030952354 ps
CPU time 2.23 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 207532 kb
Host smart-f7c120c9-8c9d-48cc-8d5e-4987542ffdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34469
75650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3446975650
Directory /workspace/26.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/26.usbdev_disconnected.2764874996
Short name T2880
Test name
Test status
Simulation time 150600600 ps
CPU time 0.84 seconds
Started Aug 11 07:13:07 PM PDT 24
Finished Aug 11 07:13:08 PM PDT 24
Peak memory 207460 kb
Host smart-f1288818-b229-4709-99b6-f52bda214cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
74996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2764874996
Directory /workspace/26.usbdev_disconnected/latest


Test location /workspace/coverage/default/26.usbdev_enable.2798838286
Short name T2731
Test name
Test status
Simulation time 30004782 ps
CPU time 0.73 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 207452 kb
Host smart-ea8c2530-7a09-45d6-993f-7fec84f90d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27988
38286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2798838286
Directory /workspace/26.usbdev_enable/latest


Test location /workspace/coverage/default/26.usbdev_endpoint_access.2532194127
Short name T248
Test name
Test status
Simulation time 886906299 ps
CPU time 2.27 seconds
Started Aug 11 07:13:09 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207720 kb
Host smart-f0feb7ac-2f05-4141-a380-60fc922bc0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
94127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2532194127
Directory /workspace/26.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/26.usbdev_fifo_rst.3017368630
Short name T3399
Test name
Test status
Simulation time 169503772 ps
CPU time 1.81 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 207708 kb
Host smart-17777b22-e49d-443f-8782-291596bb3979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173
68630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3017368630
Directory /workspace/26.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/26.usbdev_in_iso.884349764
Short name T2393
Test name
Test status
Simulation time 223171993 ps
CPU time 1.17 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 215928 kb
Host smart-65d4458e-7c98-4603-8c9c-2097e9c75a99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=884349764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.884349764
Directory /workspace/26.usbdev_in_iso/latest


Test location /workspace/coverage/default/26.usbdev_in_stall.372665015
Short name T1438
Test name
Test status
Simulation time 145735299 ps
CPU time 0.82 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207464 kb
Host smart-56c35ca3-7e61-4b14-a3e7-8bb4794f0efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37266
5015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.372665015
Directory /workspace/26.usbdev_in_stall/latest


Test location /workspace/coverage/default/26.usbdev_in_trans.2839987557
Short name T24
Test name
Test status
Simulation time 213876417 ps
CPU time 0.98 seconds
Started Aug 11 07:13:14 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 207556 kb
Host smart-82294be7-8cff-4cce-a5ff-7d436b8b0858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28399
87557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2839987557
Directory /workspace/26.usbdev_in_trans/latest


Test location /workspace/coverage/default/26.usbdev_invalid_sync.2756677413
Short name T2370
Test name
Test status
Simulation time 4497758343 ps
CPU time 125.29 seconds
Started Aug 11 07:13:15 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 216044 kb
Host smart-ebeb4008-a643-46f6-90d7-2ebb86a4f33c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2756677413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.2756677413
Directory /workspace/26.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/26.usbdev_iso_retraction.3304631699
Short name T96
Test name
Test status
Simulation time 5396936174 ps
CPU time 67.5 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:14:15 PM PDT 24
Peak memory 207812 kb
Host smart-d85d9032-00e8-4beb-a4f0-f332f30b3ec0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3304631699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3304631699
Directory /workspace/26.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/26.usbdev_link_in_err.3147170613
Short name T2418
Test name
Test status
Simulation time 187268536 ps
CPU time 0.92 seconds
Started Aug 11 07:13:14 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 207528 kb
Host smart-a074c1a1-e3bd-493b-aec6-9d01ee5abfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31471
70613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3147170613
Directory /workspace/26.usbdev_link_in_err/latest


Test location /workspace/coverage/default/26.usbdev_link_resume.1619864078
Short name T2143
Test name
Test status
Simulation time 24135918292 ps
CPU time 41.05 seconds
Started Aug 11 07:13:14 PM PDT 24
Finished Aug 11 07:13:56 PM PDT 24
Peak memory 216176 kb
Host smart-5776e72a-3eb8-4f1e-9e6c-f601b70251e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16198
64078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.1619864078
Directory /workspace/26.usbdev_link_resume/latest


Test location /workspace/coverage/default/26.usbdev_link_suspend.3978682774
Short name T659
Test name
Test status
Simulation time 5514012130 ps
CPU time 7.73 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:26 PM PDT 24
Peak memory 207716 kb
Host smart-d199a601-9aa9-4fa4-971d-6cc89ae42760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39786
82774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.3978682774
Directory /workspace/26.usbdev_link_suspend/latest


Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2324586621
Short name T837
Test name
Test status
Simulation time 3693015817 ps
CPU time 105.91 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:14:59 PM PDT 24
Peak memory 218624 kb
Host smart-79fb47fd-061d-452d-bce3-d9dad846223c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2324586621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2324586621
Directory /workspace/26.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.247179581
Short name T1871
Test name
Test status
Simulation time 2366092056 ps
CPU time 65.76 seconds
Started Aug 11 07:13:07 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 217476 kb
Host smart-56a837f1-670c-4513-b501-74ea8551e85a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=247179581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.247179581
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.936788866
Short name T2288
Test name
Test status
Simulation time 254586291 ps
CPU time 1.03 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 207496 kb
Host smart-e87fda97-39a7-4c5d-a75b-fd34a5f49929
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=936788866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.936788866
Directory /workspace/26.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3023074772
Short name T1262
Test name
Test status
Simulation time 200886465 ps
CPU time 0.95 seconds
Started Aug 11 07:13:13 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 207564 kb
Host smart-1be714ba-028c-4426-b434-edf2bcb9f267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30230
74772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3023074772
Directory /workspace/26.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.3129753384
Short name T2528
Test name
Test status
Simulation time 2498704036 ps
CPU time 25.23 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:13:33 PM PDT 24
Peak memory 217736 kb
Host smart-914a2831-fbdc-42e5-a7d3-90ccd9eebb40
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3129753384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3129753384
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3079281011
Short name T826
Test name
Test status
Simulation time 173424203 ps
CPU time 0.87 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207512 kb
Host smart-4fa13c9c-c5f1-4bf9-a6fc-d46fa0c2d27b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3079281011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3079281011
Directory /workspace/26.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3557124855
Short name T867
Test name
Test status
Simulation time 149786623 ps
CPU time 0.9 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207548 kb
Host smart-b5023e3e-6885-4b8e-ad0e-371301fe7868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35571
24855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3557124855
Directory /workspace/26.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_nak_trans.2610725386
Short name T160
Test name
Test status
Simulation time 192186628 ps
CPU time 0.9 seconds
Started Aug 11 07:13:12 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 207572 kb
Host smart-3b3294c6-1a16-4926-b319-e852ca271084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26107
25386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2610725386
Directory /workspace/26.usbdev_nak_trans/latest


Test location /workspace/coverage/default/26.usbdev_out_iso.1659258382
Short name T3335
Test name
Test status
Simulation time 151964539 ps
CPU time 0.82 seconds
Started Aug 11 07:13:14 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 207548 kb
Host smart-5a12a355-7285-42f9-8819-2b4e40e33799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16592
58382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1659258382
Directory /workspace/26.usbdev_out_iso/latest


Test location /workspace/coverage/default/26.usbdev_out_stall.3206396345
Short name T3066
Test name
Test status
Simulation time 170359871 ps
CPU time 0.86 seconds
Started Aug 11 07:13:15 PM PDT 24
Finished Aug 11 07:13:16 PM PDT 24
Peak memory 207552 kb
Host smart-6662bd17-ae22-47b8-9fcb-00c1fadad112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32063
96345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3206396345
Directory /workspace/26.usbdev_out_stall/latest


Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2888737237
Short name T948
Test name
Test status
Simulation time 170714658 ps
CPU time 0.93 seconds
Started Aug 11 07:13:13 PM PDT 24
Finished Aug 11 07:13:14 PM PDT 24
Peak memory 207740 kb
Host smart-d0088166-f3af-4314-977c-1bb9ad4bc9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28887
37237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2888737237
Directory /workspace/26.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/26.usbdev_pending_in_trans.585975384
Short name T1447
Test name
Test status
Simulation time 186656954 ps
CPU time 0.94 seconds
Started Aug 11 07:13:07 PM PDT 24
Finished Aug 11 07:13:08 PM PDT 24
Peak memory 207536 kb
Host smart-e1f9375b-14d5-4de3-9d9c-11c408629e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58597
5384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.585975384
Directory /workspace/26.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2185521909
Short name T2564
Test name
Test status
Simulation time 234007711 ps
CPU time 1 seconds
Started Aug 11 07:13:14 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 207568 kb
Host smart-08c8a930-dd61-49c5-bcd7-f2a8ed4b451a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2185521909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2185521909
Directory /workspace/26.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2751602267
Short name T1756
Test name
Test status
Simulation time 150261168 ps
CPU time 0.85 seconds
Started Aug 11 07:13:15 PM PDT 24
Finished Aug 11 07:13:17 PM PDT 24
Peak memory 207540 kb
Host smart-5769ce35-e6a6-4a5b-aeed-e0abf7085750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27516
02267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2751602267
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.403771521
Short name T2839
Test name
Test status
Simulation time 43551667 ps
CPU time 0.73 seconds
Started Aug 11 07:13:05 PM PDT 24
Finished Aug 11 07:13:06 PM PDT 24
Peak memory 207512 kb
Host smart-860cd4de-6494-4cf2-903b-281ab104ef46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40377
1521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.403771521
Directory /workspace/26.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/26.usbdev_pkt_buffer.545285919
Short name T2195
Test name
Test status
Simulation time 11459905812 ps
CPU time 26.14 seconds
Started Aug 11 07:13:08 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 216004 kb
Host smart-288cc071-53e9-4b15-b7de-31dd52b796f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54528
5919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.545285919
Directory /workspace/26.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/26.usbdev_pkt_received.426652428
Short name T1869
Test name
Test status
Simulation time 243509496 ps
CPU time 0.95 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207588 kb
Host smart-fd8f6e12-29a3-451e-a0ad-ca3bd4cc21de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42665
2428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.426652428
Directory /workspace/26.usbdev_pkt_received/latest


Test location /workspace/coverage/default/26.usbdev_pkt_sent.2241842439
Short name T1112
Test name
Test status
Simulation time 165451424 ps
CPU time 0.92 seconds
Started Aug 11 07:13:14 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 207592 kb
Host smart-793914d1-e677-4d6a-900e-2bec0d33718e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22418
42439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2241842439
Directory /workspace/26.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1339508293
Short name T3170
Test name
Test status
Simulation time 205162743 ps
CPU time 0.9 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207484 kb
Host smart-c6ee8203-d96a-4467-bc27-4c29a5d19839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13395
08293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1339508293
Directory /workspace/26.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.3446703235
Short name T1462
Test name
Test status
Simulation time 210386327 ps
CPU time 0.96 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:11 PM PDT 24
Peak memory 207744 kb
Host smart-822eeaa9-cd9d-44dc-923f-b42560fa6f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34467
03235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.3446703235
Directory /workspace/26.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3709049053
Short name T1637
Test name
Test status
Simulation time 150080497 ps
CPU time 0.82 seconds
Started Aug 11 07:13:17 PM PDT 24
Finished Aug 11 07:13:18 PM PDT 24
Peak memory 207524 kb
Host smart-06515f40-c847-48d6-baa2-5312966cd373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
49053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3709049053
Directory /workspace/26.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/26.usbdev_rx_full.1664142752
Short name T1900
Test name
Test status
Simulation time 263154760 ps
CPU time 1.11 seconds
Started Aug 11 07:13:15 PM PDT 24
Finished Aug 11 07:13:17 PM PDT 24
Peak memory 207452 kb
Host smart-43382588-7aa1-4543-87fa-c718c4d88314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16641
42752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.1664142752
Directory /workspace/26.usbdev_rx_full/latest


Test location /workspace/coverage/default/26.usbdev_setup_stage.364221782
Short name T2850
Test name
Test status
Simulation time 150974196 ps
CPU time 0.83 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207504 kb
Host smart-9cb4274d-ba0c-4537-ac0d-9b38efe206bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36422
1782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.364221782
Directory /workspace/26.usbdev_setup_stage/latest


Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2319626900
Short name T2364
Test name
Test status
Simulation time 152919491 ps
CPU time 0.89 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207548 kb
Host smart-adf97da9-8039-4bf3-9e52-fd7ad99b713d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23196
26900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2319626900
Directory /workspace/26.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/26.usbdev_smoke.84949815
Short name T1084
Test name
Test status
Simulation time 226844184 ps
CPU time 1.01 seconds
Started Aug 11 07:13:16 PM PDT 24
Finished Aug 11 07:13:17 PM PDT 24
Peak memory 207556 kb
Host smart-dd8fc089-2f81-47d3-b1be-e54e4066767a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84949
815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.84949815
Directory /workspace/26.usbdev_smoke/latest


Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2521039887
Short name T2344
Test name
Test status
Simulation time 2122645117 ps
CPU time 22.22 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:32 PM PDT 24
Peak memory 217848 kb
Host smart-b1eeb6e7-fc21-4300-995e-6a5c8c4e4e67
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2521039887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2521039887
Directory /workspace/26.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2060065598
Short name T1976
Test name
Test status
Simulation time 160904678 ps
CPU time 0.88 seconds
Started Aug 11 07:13:23 PM PDT 24
Finished Aug 11 07:13:24 PM PDT 24
Peak memory 207576 kb
Host smart-f9045bd9-a335-4bb3-bf03-86db70018f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20600
65598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2060065598
Directory /workspace/26.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/26.usbdev_stall_trans.3759802944
Short name T3256
Test name
Test status
Simulation time 149656758 ps
CPU time 0.84 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207536 kb
Host smart-7896864b-6656-433e-a5b1-332448b22b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37598
02944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3759802944
Directory /workspace/26.usbdev_stall_trans/latest


Test location /workspace/coverage/default/26.usbdev_stream_len_max.1781075780
Short name T3551
Test name
Test status
Simulation time 984267823 ps
CPU time 2.55 seconds
Started Aug 11 07:13:17 PM PDT 24
Finished Aug 11 07:13:20 PM PDT 24
Peak memory 207716 kb
Host smart-7fe82851-b8bd-4ecd-ab1a-93039e4c5832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17810
75780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.1781075780
Directory /workspace/26.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/26.usbdev_streaming_out.51704332
Short name T2858
Test name
Test status
Simulation time 2431245705 ps
CPU time 66.8 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:14:25 PM PDT 24
Peak memory 215980 kb
Host smart-48d75f3f-49ae-4a3c-ab25-67cba6918e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51704
332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.51704332
Directory /workspace/26.usbdev_streaming_out/latest


Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.413817230
Short name T2756
Test name
Test status
Simulation time 4365195540 ps
CPU time 28.17 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:38 PM PDT 24
Peak memory 207800 kb
Host smart-6be53433-0882-4ea2-a720-039418d8dc5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413817230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_host
_handshake.413817230
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/26.usbdev_tx_rx_disruption.49241081
Short name T3616
Test name
Test status
Simulation time 534700000 ps
CPU time 1.57 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:20 PM PDT 24
Peak memory 207572 kb
Host smart-4b6e0d64-e455-475b-8284-6bbe75792d0c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49241081 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 26.usbdev_tx_rx_disruption.49241081
Directory /workspace/26.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/260.usbdev_tx_rx_disruption.35118667
Short name T947
Test name
Test status
Simulation time 488731911 ps
CPU time 1.56 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207512 kb
Host smart-ed3c9535-c192-4d0f-ac58-47b40ad0c00c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35118667 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 260.usbdev_tx_rx_disruption.35118667
Directory /workspace/260.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/261.usbdev_tx_rx_disruption.3938451748
Short name T210
Test name
Test status
Simulation time 479223761 ps
CPU time 1.45 seconds
Started Aug 11 07:17:35 PM PDT 24
Finished Aug 11 07:17:37 PM PDT 24
Peak memory 207504 kb
Host smart-9e421e12-4def-4a55-9bb5-3a2b78a8f491
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938451748 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.usbdev_tx_rx_disruption.3938451748
Directory /workspace/261.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/262.usbdev_tx_rx_disruption.1542277306
Short name T35
Test name
Test status
Simulation time 530044904 ps
CPU time 1.7 seconds
Started Aug 11 07:17:42 PM PDT 24
Finished Aug 11 07:17:44 PM PDT 24
Peak memory 207576 kb
Host smart-b3af9153-3d49-427a-b121-576d18ad972a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542277306 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.usbdev_tx_rx_disruption.1542277306
Directory /workspace/262.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/263.usbdev_tx_rx_disruption.3228770875
Short name T3253
Test name
Test status
Simulation time 497274534 ps
CPU time 1.54 seconds
Started Aug 11 07:17:40 PM PDT 24
Finished Aug 11 07:17:42 PM PDT 24
Peak memory 207576 kb
Host smart-b2f9e6f9-fb46-4cc6-b0fa-2714ee4a0f16
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228770875 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.usbdev_tx_rx_disruption.3228770875
Directory /workspace/263.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/264.usbdev_tx_rx_disruption.2974737156
Short name T2795
Test name
Test status
Simulation time 532266767 ps
CPU time 1.51 seconds
Started Aug 11 07:17:57 PM PDT 24
Finished Aug 11 07:17:59 PM PDT 24
Peak memory 207492 kb
Host smart-351125d4-decf-42b7-8288-ffd523c53571
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974737156 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.usbdev_tx_rx_disruption.2974737156
Directory /workspace/264.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/265.usbdev_tx_rx_disruption.4251753265
Short name T2298
Test name
Test status
Simulation time 639688022 ps
CPU time 1.81 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207500 kb
Host smart-bad059fd-1e29-4d52-8f81-4e5f6db014a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251753265 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 265.usbdev_tx_rx_disruption.4251753265
Directory /workspace/265.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/266.usbdev_tx_rx_disruption.1021812256
Short name T933
Test name
Test status
Simulation time 637920585 ps
CPU time 1.69 seconds
Started Aug 11 07:17:46 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207576 kb
Host smart-3eab1db8-aedd-45d9-8442-ec8d6fac7210
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021812256 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.usbdev_tx_rx_disruption.1021812256
Directory /workspace/266.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/267.usbdev_tx_rx_disruption.2349787954
Short name T3441
Test name
Test status
Simulation time 579829087 ps
CPU time 1.59 seconds
Started Aug 11 07:17:43 PM PDT 24
Finished Aug 11 07:17:44 PM PDT 24
Peak memory 207504 kb
Host smart-6c4a184a-284f-46fb-9484-11ab244ce3b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349787954 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.usbdev_tx_rx_disruption.2349787954
Directory /workspace/267.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/268.usbdev_tx_rx_disruption.115935504
Short name T3385
Test name
Test status
Simulation time 529679144 ps
CPU time 1.5 seconds
Started Aug 11 07:17:44 PM PDT 24
Finished Aug 11 07:17:46 PM PDT 24
Peak memory 207440 kb
Host smart-73678107-cb58-457f-af70-b2d83cb60333
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115935504 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 268.usbdev_tx_rx_disruption.115935504
Directory /workspace/268.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/269.usbdev_tx_rx_disruption.1008797883
Short name T3041
Test name
Test status
Simulation time 513091574 ps
CPU time 1.56 seconds
Started Aug 11 07:17:45 PM PDT 24
Finished Aug 11 07:17:46 PM PDT 24
Peak memory 207520 kb
Host smart-6ec3707e-55af-4222-a643-6df45328e048
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008797883 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.usbdev_tx_rx_disruption.1008797883
Directory /workspace/269.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/27.usbdev_alert_test.713057678
Short name T1041
Test name
Test status
Simulation time 47440832 ps
CPU time 0.72 seconds
Started Aug 11 07:13:39 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 207592 kb
Host smart-3bebd4a5-68be-4364-9302-60779f8309cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=713057678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.713057678
Directory /workspace/27.usbdev_alert_test/latest


Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2315990005
Short name T227
Test name
Test status
Simulation time 9035291761 ps
CPU time 11.39 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:44 PM PDT 24
Peak memory 207836 kb
Host smart-cb26df4f-e56c-4c34-adac-4cea985679b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315990005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.2315990005
Directory /workspace/27.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1358931065
Short name T1161
Test name
Test status
Simulation time 18950380274 ps
CPU time 23.75 seconds
Started Aug 11 07:13:21 PM PDT 24
Finished Aug 11 07:13:45 PM PDT 24
Peak memory 207796 kb
Host smart-c60f9d10-74ac-4be5-b94f-f82d6352192c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358931065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1358931065
Directory /workspace/27.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2245582053
Short name T2848
Test name
Test status
Simulation time 28813702461 ps
CPU time 37.09 seconds
Started Aug 11 07:13:21 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207864 kb
Host smart-5705196d-c599-471e-a7d1-dfaa3b59e0a9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245582053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.2245582053
Directory /workspace/27.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/27.usbdev_av_buffer.3790290408
Short name T320
Test name
Test status
Simulation time 175131772 ps
CPU time 0.91 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207548 kb
Host smart-fbb9e821-4270-4c19-80fd-135a06b2b3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37902
90408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3790290408
Directory /workspace/27.usbdev_av_buffer/latest


Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3758606149
Short name T928
Test name
Test status
Simulation time 158080630 ps
CPU time 0.89 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207576 kb
Host smart-d867d208-7a69-43a9-a105-82ebde4d9c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37586
06149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3758606149
Directory /workspace/27.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.798439843
Short name T3615
Test name
Test status
Simulation time 349638203 ps
CPU time 1.32 seconds
Started Aug 11 07:13:19 PM PDT 24
Finished Aug 11 07:13:21 PM PDT 24
Peak memory 207576 kb
Host smart-5b22bf31-27f9-4607-8ad8-b82692bc0c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79843
9843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.798439843
Directory /workspace/27.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.4078332668
Short name T617
Test name
Test status
Simulation time 316088391 ps
CPU time 1.1 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:12 PM PDT 24
Peak memory 207504 kb
Host smart-72f6a4d8-6094-4b11-b5bc-25737958a524
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4078332668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.4078332668
Directory /workspace/27.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/27.usbdev_device_address.1421272548
Short name T176
Test name
Test status
Simulation time 49558538536 ps
CPU time 76.68 seconds
Started Aug 11 07:13:17 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 207800 kb
Host smart-7188d885-b598-4064-b138-1d98cc1dc417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14212
72548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.1421272548
Directory /workspace/27.usbdev_device_address/latest


Test location /workspace/coverage/default/27.usbdev_device_timeout.2420784638
Short name T2292
Test name
Test status
Simulation time 5700543419 ps
CPU time 49.17 seconds
Started Aug 11 07:13:09 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207768 kb
Host smart-fab97d8e-e8f8-4180-b70c-1e699791c7a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420784638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.2420784638
Directory /workspace/27.usbdev_device_timeout/latest


Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3623352520
Short name T3433
Test name
Test status
Simulation time 822095830 ps
CPU time 2.03 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 207448 kb
Host smart-8d2fef3f-348c-4e09-aea9-abf301e84bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36233
52520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3623352520
Directory /workspace/27.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/27.usbdev_disconnected.1241181338
Short name T3162
Test name
Test status
Simulation time 138098268 ps
CPU time 0.86 seconds
Started Aug 11 07:13:17 PM PDT 24
Finished Aug 11 07:13:18 PM PDT 24
Peak memory 207540 kb
Host smart-64b013de-4d14-41d3-8ef0-29324878967e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12411
81338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1241181338
Directory /workspace/27.usbdev_disconnected/latest


Test location /workspace/coverage/default/27.usbdev_enable.2031678262
Short name T573
Test name
Test status
Simulation time 44891592 ps
CPU time 0.74 seconds
Started Aug 11 07:13:14 PM PDT 24
Finished Aug 11 07:13:15 PM PDT 24
Peak memory 207452 kb
Host smart-c44ed8e5-d9b4-4f00-9ef3-7daafd95c366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20316
78262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2031678262
Directory /workspace/27.usbdev_enable/latest


Test location /workspace/coverage/default/27.usbdev_endpoint_access.3458328029
Short name T956
Test name
Test status
Simulation time 1078825255 ps
CPU time 2.69 seconds
Started Aug 11 07:13:10 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 207724 kb
Host smart-e24ec3b9-8f7e-41d7-8a7c-e295028ccd61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34583
28029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3458328029
Directory /workspace/27.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/27.usbdev_endpoint_types.1784514533
Short name T531
Test name
Test status
Simulation time 407810057 ps
CPU time 1.27 seconds
Started Aug 11 07:13:11 PM PDT 24
Finished Aug 11 07:13:13 PM PDT 24
Peak memory 207452 kb
Host smart-e72ec829-75e6-4455-8edd-82eec8dbf978
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1784514533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.1784514533
Directory /workspace/27.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/27.usbdev_fifo_rst.537942742
Short name T1049
Test name
Test status
Simulation time 353057038 ps
CPU time 2.18 seconds
Started Aug 11 07:13:30 PM PDT 24
Finished Aug 11 07:13:32 PM PDT 24
Peak memory 207620 kb
Host smart-6f3bcd74-e025-4af4-a317-272badd6ae97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53794
2742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.537942742
Directory /workspace/27.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/27.usbdev_in_iso.3911261603
Short name T755
Test name
Test status
Simulation time 230890193 ps
CPU time 1.14 seconds
Started Aug 11 07:13:29 PM PDT 24
Finished Aug 11 07:13:30 PM PDT 24
Peak memory 215844 kb
Host smart-ed56e491-fc3e-4ede-9169-c5b00859389a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3911261603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3911261603
Directory /workspace/27.usbdev_in_iso/latest


Test location /workspace/coverage/default/27.usbdev_in_stall.863555210
Short name T942
Test name
Test status
Simulation time 141546581 ps
CPU time 0.81 seconds
Started Aug 11 07:13:32 PM PDT 24
Finished Aug 11 07:13:33 PM PDT 24
Peak memory 207444 kb
Host smart-7c38b6a0-de87-44e7-bda8-1d850f82f269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86355
5210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.863555210
Directory /workspace/27.usbdev_in_stall/latest


Test location /workspace/coverage/default/27.usbdev_in_trans.516665152
Short name T3033
Test name
Test status
Simulation time 206033991 ps
CPU time 0.96 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207524 kb
Host smart-3cc40843-0484-4ef0-8727-9e7dcd73641e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51666
5152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.516665152
Directory /workspace/27.usbdev_in_trans/latest


Test location /workspace/coverage/default/27.usbdev_invalid_sync.3205347539
Short name T1794
Test name
Test status
Simulation time 2806718443 ps
CPU time 78.9 seconds
Started Aug 11 07:13:14 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 216112 kb
Host smart-8157d19b-93a6-4648-83ef-00c0fea896a2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3205347539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3205347539
Directory /workspace/27.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/27.usbdev_iso_retraction.574041340
Short name T1515
Test name
Test status
Simulation time 3466428959 ps
CPU time 21.55 seconds
Started Aug 11 07:13:16 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207880 kb
Host smart-757b95dd-abc1-4183-a5f8-4be1c1c445ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=574041340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.574041340
Directory /workspace/27.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/27.usbdev_link_in_err.1095868130
Short name T1459
Test name
Test status
Simulation time 270082214 ps
CPU time 1.04 seconds
Started Aug 11 07:13:25 PM PDT 24
Finished Aug 11 07:13:26 PM PDT 24
Peak memory 207540 kb
Host smart-924b1bb8-3fda-4369-8d7f-8933cec9f018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10958
68130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1095868130
Directory /workspace/27.usbdev_link_in_err/latest


Test location /workspace/coverage/default/27.usbdev_link_resume.99532140
Short name T2179
Test name
Test status
Simulation time 10655156690 ps
CPU time 13.37 seconds
Started Aug 11 07:13:28 PM PDT 24
Finished Aug 11 07:13:41 PM PDT 24
Peak memory 207784 kb
Host smart-a2a5213d-5f96-448a-86f0-31b748a8f7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99532
140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.99532140
Directory /workspace/27.usbdev_link_resume/latest


Test location /workspace/coverage/default/27.usbdev_link_suspend.2033149078
Short name T2133
Test name
Test status
Simulation time 3361252824 ps
CPU time 5.41 seconds
Started Aug 11 07:13:28 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 216028 kb
Host smart-3af58510-6d0a-426a-88e5-f24c1d0424c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20331
49078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2033149078
Directory /workspace/27.usbdev_link_suspend/latest


Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.4161100129
Short name T1332
Test name
Test status
Simulation time 3532287665 ps
CPU time 29.97 seconds
Started Aug 11 07:13:16 PM PDT 24
Finished Aug 11 07:13:46 PM PDT 24
Peak memory 216156 kb
Host smart-0b0fc4c4-1c70-42c5-bda8-8af774deae33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4161100129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.4161100129
Directory /workspace/27.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1201593128
Short name T2623
Test name
Test status
Simulation time 2091094164 ps
CPU time 15.33 seconds
Started Aug 11 07:13:40 PM PDT 24
Finished Aug 11 07:13:56 PM PDT 24
Peak memory 217512 kb
Host smart-9875b729-843a-48ed-958b-3aa46ee19e1e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1201593128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1201593128
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1950159222
Short name T2500
Test name
Test status
Simulation time 236651288 ps
CPU time 1 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207564 kb
Host smart-8618ad83-41d8-472f-b025-bf603b604bc0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1950159222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1950159222
Directory /workspace/27.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2245769060
Short name T2360
Test name
Test status
Simulation time 230249077 ps
CPU time 0.93 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207488 kb
Host smart-9af35a55-00d0-4b02-bb1a-a69e5aab1ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22457
69060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2245769060
Directory /workspace/27.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.3107884366
Short name T1406
Test name
Test status
Simulation time 1842334961 ps
CPU time 51.98 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:14:25 PM PDT 24
Peak memory 215924 kb
Host smart-b1fe6911-8533-44ab-b17a-cab733c0ab1b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3107884366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.3107884366
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.374850465
Short name T1304
Test name
Test status
Simulation time 158200237 ps
CPU time 0.82 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207596 kb
Host smart-38dade33-aab9-4cfd-897c-850db7a88e58
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=374850465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.374850465
Directory /workspace/27.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.811596218
Short name T2004
Test name
Test status
Simulation time 158456285 ps
CPU time 0.87 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207572 kb
Host smart-ca5ed070-e9fd-41e5-aab3-a652c7931b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81159
6218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.811596218
Directory /workspace/27.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_nak_trans.4107925496
Short name T3468
Test name
Test status
Simulation time 200842384 ps
CPU time 0.89 seconds
Started Aug 11 07:13:22 PM PDT 24
Finished Aug 11 07:13:23 PM PDT 24
Peak memory 207580 kb
Host smart-65a7f292-91c0-4b65-ac4c-8bb9a0251102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41079
25496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.4107925496
Directory /workspace/27.usbdev_nak_trans/latest


Test location /workspace/coverage/default/27.usbdev_out_iso.375101480
Short name T602
Test name
Test status
Simulation time 169510021 ps
CPU time 0.9 seconds
Started Aug 11 07:13:23 PM PDT 24
Finished Aug 11 07:13:24 PM PDT 24
Peak memory 207508 kb
Host smart-ca40942d-cddc-400c-92f7-8fb76bc3f3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
1480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.375101480
Directory /workspace/27.usbdev_out_iso/latest


Test location /workspace/coverage/default/27.usbdev_out_stall.186948294
Short name T1682
Test name
Test status
Simulation time 203398591 ps
CPU time 0.9 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207528 kb
Host smart-b67a39d8-9afc-4cdc-8ec7-65b1bd86a8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18694
8294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.186948294
Directory /workspace/27.usbdev_out_stall/latest


Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1753562346
Short name T2607
Test name
Test status
Simulation time 212624410 ps
CPU time 0.88 seconds
Started Aug 11 07:13:26 PM PDT 24
Finished Aug 11 07:13:28 PM PDT 24
Peak memory 207572 kb
Host smart-c3a0794d-80a3-400d-ae96-76ba3609be78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17535
62346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1753562346
Directory /workspace/27.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2428589315
Short name T738
Test name
Test status
Simulation time 190837621 ps
CPU time 0.85 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:13:36 PM PDT 24
Peak memory 207556 kb
Host smart-7084a0d0-cfd0-4945-9c79-1d6304326198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24285
89315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2428589315
Directory /workspace/27.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2094176889
Short name T1513
Test name
Test status
Simulation time 235000619 ps
CPU time 1.05 seconds
Started Aug 11 07:13:21 PM PDT 24
Finished Aug 11 07:13:22 PM PDT 24
Peak memory 207540 kb
Host smart-cd866dca-e92a-4c7c-8b42-e3cab86ca9e9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2094176889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2094176889
Directory /workspace/27.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2650496720
Short name T745
Test name
Test status
Simulation time 200829869 ps
CPU time 0.87 seconds
Started Aug 11 07:13:19 PM PDT 24
Finished Aug 11 07:13:20 PM PDT 24
Peak memory 207540 kb
Host smart-0a040a3b-254d-4f73-b109-ae5b5c468fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26504
96720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2650496720
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2766039267
Short name T860
Test name
Test status
Simulation time 82486763 ps
CPU time 0.76 seconds
Started Aug 11 07:13:28 PM PDT 24
Finished Aug 11 07:13:28 PM PDT 24
Peak memory 207480 kb
Host smart-e8ef0d57-92b9-4e02-9916-c178b900d4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27660
39267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2766039267
Directory /workspace/27.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2150691082
Short name T1867
Test name
Test status
Simulation time 17754748758 ps
CPU time 42.49 seconds
Started Aug 11 07:13:20 PM PDT 24
Finished Aug 11 07:14:02 PM PDT 24
Peak memory 216020 kb
Host smart-19a62f3e-622e-4e57-a82e-af8e464e2ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21506
91082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2150691082
Directory /workspace/27.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/27.usbdev_pkt_received.1454819870
Short name T3050
Test name
Test status
Simulation time 175507368 ps
CPU time 1.01 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 207488 kb
Host smart-be8a813a-0b35-4c39-8abe-73de98185afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14548
19870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1454819870
Directory /workspace/27.usbdev_pkt_received/latest


Test location /workspace/coverage/default/27.usbdev_pkt_sent.1051730602
Short name T322
Test name
Test status
Simulation time 216943852 ps
CPU time 0.94 seconds
Started Aug 11 07:13:17 PM PDT 24
Finished Aug 11 07:13:18 PM PDT 24
Peak memory 207568 kb
Host smart-f6bb2ce1-1820-46c1-84ee-29b6ca10bc09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10517
30602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1051730602
Directory /workspace/27.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3305166037
Short name T1341
Test name
Test status
Simulation time 193352117 ps
CPU time 0.93 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:19 PM PDT 24
Peak memory 207548 kb
Host smart-ec15887d-b47e-43c3-abce-252b56324807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33051
66037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3305166037
Directory /workspace/27.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3658653522
Short name T3096
Test name
Test status
Simulation time 187357028 ps
CPU time 0.96 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207540 kb
Host smart-8519342a-ee64-4fd2-8038-3c3fa3de821d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36586
53522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3658653522
Directory /workspace/27.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3729002172
Short name T3088
Test name
Test status
Simulation time 145642966 ps
CPU time 0.84 seconds
Started Aug 11 07:13:37 PM PDT 24
Finished Aug 11 07:13:38 PM PDT 24
Peak memory 207512 kb
Host smart-1a3966dc-e0d6-4bf8-a11e-5199e5c47c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37290
02172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3729002172
Directory /workspace/27.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/27.usbdev_rx_full.943258478
Short name T337
Test name
Test status
Simulation time 307872503 ps
CPU time 1.11 seconds
Started Aug 11 07:13:37 PM PDT 24
Finished Aug 11 07:13:38 PM PDT 24
Peak memory 207540 kb
Host smart-5417b65d-a720-417e-85dd-8b04cfd05c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94325
8478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.943258478
Directory /workspace/27.usbdev_rx_full/latest


Test location /workspace/coverage/default/27.usbdev_setup_stage.860594180
Short name T2600
Test name
Test status
Simulation time 187051622 ps
CPU time 0.86 seconds
Started Aug 11 07:13:28 PM PDT 24
Finished Aug 11 07:13:29 PM PDT 24
Peak memory 207448 kb
Host smart-92f1bf4f-25bd-4565-afd3-33520a0386cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86059
4180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.860594180
Directory /workspace/27.usbdev_setup_stage/latest


Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1997301071
Short name T1570
Test name
Test status
Simulation time 235182546 ps
CPU time 0.92 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:13:36 PM PDT 24
Peak memory 207564 kb
Host smart-08adc98e-aaeb-45cc-bca5-ff327daeabee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19973
01071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1997301071
Directory /workspace/27.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/27.usbdev_smoke.1013431544
Short name T1320
Test name
Test status
Simulation time 229362951 ps
CPU time 0.96 seconds
Started Aug 11 07:13:32 PM PDT 24
Finished Aug 11 07:13:33 PM PDT 24
Peak memory 207524 kb
Host smart-9c876901-3160-43e0-811a-919652bc4e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10134
31544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1013431544
Directory /workspace/27.usbdev_smoke/latest


Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.555876440
Short name T995
Test name
Test status
Simulation time 3312497530 ps
CPU time 33.95 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:14:09 PM PDT 24
Peak memory 224224 kb
Host smart-3ab87345-921f-49c3-8a5b-4726fb0f4279
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=555876440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.555876440
Directory /workspace/27.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2862741823
Short name T1039
Test name
Test status
Simulation time 207672749 ps
CPU time 0.93 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207592 kb
Host smart-6079a889-3b1f-4918-94df-bc0712340ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28627
41823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2862741823
Directory /workspace/27.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/27.usbdev_stall_trans.1766602788
Short name T869
Test name
Test status
Simulation time 248944084 ps
CPU time 0.97 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207456 kb
Host smart-bfee10e4-bc2a-43f4-b32a-09f486b200b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17666
02788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1766602788
Directory /workspace/27.usbdev_stall_trans/latest


Test location /workspace/coverage/default/27.usbdev_stream_len_max.1093276320
Short name T3519
Test name
Test status
Simulation time 529968990 ps
CPU time 1.53 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:13:38 PM PDT 24
Peak memory 207540 kb
Host smart-fabd34e6-0a51-49d4-9b0f-53c1d3aff2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10932
76320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.1093276320
Directory /workspace/27.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/27.usbdev_streaming_out.4236513225
Short name T2543
Test name
Test status
Simulation time 2819154408 ps
CPU time 28.48 seconds
Started Aug 11 07:13:37 PM PDT 24
Finished Aug 11 07:14:05 PM PDT 24
Peak memory 216096 kb
Host smart-736bcb19-bd69-451e-9f2c-0332c5c5a978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42365
13225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.4236513225
Directory /workspace/27.usbdev_streaming_out/latest


Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.1687009224
Short name T1184
Test name
Test status
Simulation time 1175563128 ps
CPU time 27.39 seconds
Started Aug 11 07:13:18 PM PDT 24
Finished Aug 11 07:13:46 PM PDT 24
Peak memory 207680 kb
Host smart-5cb2ec7c-0a1a-4142-80ef-29aee7cfb7bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687009224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.1687009224
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/27.usbdev_tx_rx_disruption.1972514000
Short name T2508
Test name
Test status
Simulation time 501148643 ps
CPU time 1.61 seconds
Started Aug 11 07:13:37 PM PDT 24
Finished Aug 11 07:13:38 PM PDT 24
Peak memory 207536 kb
Host smart-69d2d80b-5f3b-4548-93f8-2ffd1c398310
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972514000 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.usbdev_tx_rx_disruption.1972514000
Directory /workspace/27.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/270.usbdev_tx_rx_disruption.3507424423
Short name T192
Test name
Test status
Simulation time 493417937 ps
CPU time 1.55 seconds
Started Aug 11 07:17:29 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 207588 kb
Host smart-8474a0bf-d062-4b69-b638-7259920f5bda
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507424423 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.usbdev_tx_rx_disruption.3507424423
Directory /workspace/270.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/271.usbdev_tx_rx_disruption.1729904380
Short name T3214
Test name
Test status
Simulation time 458883447 ps
CPU time 1.32 seconds
Started Aug 11 07:17:44 PM PDT 24
Finished Aug 11 07:17:45 PM PDT 24
Peak memory 207556 kb
Host smart-c5ce3454-7266-448c-b634-1565fc527d71
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729904380 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.usbdev_tx_rx_disruption.1729904380
Directory /workspace/271.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/272.usbdev_tx_rx_disruption.844043390
Short name T2477
Test name
Test status
Simulation time 491196054 ps
CPU time 1.53 seconds
Started Aug 11 07:17:27 PM PDT 24
Finished Aug 11 07:17:28 PM PDT 24
Peak memory 207548 kb
Host smart-de29d2ac-7daa-43f4-8e2c-25cc6e476af8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844043390 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 272.usbdev_tx_rx_disruption.844043390
Directory /workspace/272.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/273.usbdev_tx_rx_disruption.2239295423
Short name T2757
Test name
Test status
Simulation time 499070940 ps
CPU time 1.45 seconds
Started Aug 11 07:17:53 PM PDT 24
Finished Aug 11 07:17:54 PM PDT 24
Peak memory 207492 kb
Host smart-c4fa5515-8ab6-46a0-99c6-a3ee6db004da
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239295423 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.usbdev_tx_rx_disruption.2239295423
Directory /workspace/273.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/274.usbdev_tx_rx_disruption.3526038909
Short name T2338
Test name
Test status
Simulation time 641066110 ps
CPU time 1.72 seconds
Started Aug 11 07:17:36 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207544 kb
Host smart-d722ee1f-ac64-443f-a064-c0f274fbe607
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526038909 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.usbdev_tx_rx_disruption.3526038909
Directory /workspace/274.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/275.usbdev_tx_rx_disruption.1175838955
Short name T2657
Test name
Test status
Simulation time 550760385 ps
CPU time 1.53 seconds
Started Aug 11 07:17:32 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207524 kb
Host smart-d6e8e535-8670-4213-afb7-bbfca293fed6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175838955 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.usbdev_tx_rx_disruption.1175838955
Directory /workspace/275.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/276.usbdev_tx_rx_disruption.1708536466
Short name T1251
Test name
Test status
Simulation time 488468444 ps
CPU time 1.61 seconds
Started Aug 11 07:17:40 PM PDT 24
Finished Aug 11 07:17:42 PM PDT 24
Peak memory 207548 kb
Host smart-60bb96b0-b6b7-40ab-a487-0eb887cfc580
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708536466 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.usbdev_tx_rx_disruption.1708536466
Directory /workspace/276.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/277.usbdev_tx_rx_disruption.4091674057
Short name T2357
Test name
Test status
Simulation time 511407695 ps
CPU time 1.56 seconds
Started Aug 11 07:17:36 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207552 kb
Host smart-0dd48d08-37ca-49dd-8ed8-5bcb290540c4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091674057 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.usbdev_tx_rx_disruption.4091674057
Directory /workspace/277.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/278.usbdev_tx_rx_disruption.2014959720
Short name T1932
Test name
Test status
Simulation time 491928447 ps
CPU time 1.59 seconds
Started Aug 11 07:17:41 PM PDT 24
Finished Aug 11 07:17:43 PM PDT 24
Peak memory 207568 kb
Host smart-64230dd4-6e23-4c13-903f-d50e0feeaea7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014959720 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.usbdev_tx_rx_disruption.2014959720
Directory /workspace/278.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/279.usbdev_tx_rx_disruption.3470631897
Short name T3187
Test name
Test status
Simulation time 597851769 ps
CPU time 1.63 seconds
Started Aug 11 07:17:40 PM PDT 24
Finished Aug 11 07:17:41 PM PDT 24
Peak memory 207548 kb
Host smart-3f3025a5-8570-4507-90e7-17433670e48a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470631897 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.usbdev_tx_rx_disruption.3470631897
Directory /workspace/279.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/28.usbdev_alert_test.1829558194
Short name T114
Test name
Test status
Simulation time 39229179 ps
CPU time 0.64 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207500 kb
Host smart-34cdc35a-c06c-48f3-84a2-e1edfd24397c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1829558194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1829558194
Directory /workspace/28.usbdev_alert_test/latest


Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3471636932
Short name T2658
Test name
Test status
Simulation time 5792476764 ps
CPU time 7.46 seconds
Started Aug 11 07:13:25 PM PDT 24
Finished Aug 11 07:13:33 PM PDT 24
Peak memory 215992 kb
Host smart-dea4a8f8-41c9-4e47-8f23-89041a143faf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471636932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.3471636932
Directory /workspace/28.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1474942956
Short name T1111
Test name
Test status
Simulation time 15904337270 ps
CPU time 18.32 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:13:55 PM PDT 24
Peak memory 215980 kb
Host smart-79ca42f4-5463-462a-a169-0376737d8638
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474942956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1474942956
Directory /workspace/28.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2359832910
Short name T122
Test name
Test status
Simulation time 23970286909 ps
CPU time 28.47 seconds
Started Aug 11 07:13:38 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 216024 kb
Host smart-c2867547-07fc-415a-9d84-6ee3c469a7ba
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359832910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.2359832910
Directory /workspace/28.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/28.usbdev_av_buffer.3323670353
Short name T3366
Test name
Test status
Simulation time 162459178 ps
CPU time 0.87 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207548 kb
Host smart-b3194a83-ca72-4a0a-bf24-fcdac043e27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33236
70353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3323670353
Directory /workspace/28.usbdev_av_buffer/latest


Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1767325905
Short name T1785
Test name
Test status
Simulation time 165464560 ps
CPU time 0.84 seconds
Started Aug 11 07:13:39 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 207532 kb
Host smart-dba6b348-79b9-4b9c-a231-45b015b4a54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17673
25905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1767325905
Directory /workspace/28.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1551748638
Short name T955
Test name
Test status
Simulation time 197142651 ps
CPU time 0.94 seconds
Started Aug 11 07:13:30 PM PDT 24
Finished Aug 11 07:13:31 PM PDT 24
Peak memory 207576 kb
Host smart-61716bd1-2177-4bcd-a2d9-3f4a18e266a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15517
48638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1551748638
Directory /workspace/28.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1755418761
Short name T3371
Test name
Test status
Simulation time 1126979013 ps
CPU time 2.86 seconds
Started Aug 11 07:13:32 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207748 kb
Host smart-0e6240b6-8b48-4d14-8a1c-eb28e2398bec
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1755418761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1755418761
Directory /workspace/28.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/28.usbdev_device_address.221790968
Short name T2146
Test name
Test status
Simulation time 44750090221 ps
CPU time 69.34 seconds
Started Aug 11 07:13:30 PM PDT 24
Finished Aug 11 07:14:40 PM PDT 24
Peak memory 207772 kb
Host smart-83c971a3-cb61-42a0-a20a-44e3f6e69159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22179
0968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.221790968
Directory /workspace/28.usbdev_device_address/latest


Test location /workspace/coverage/default/28.usbdev_device_timeout.3643347088
Short name T1082
Test name
Test status
Simulation time 620476844 ps
CPU time 4.92 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:13:41 PM PDT 24
Peak memory 207572 kb
Host smart-fc2a4eab-a34e-4154-8fd2-ad8b0a2bd01d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643347088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.3643347088
Directory /workspace/28.usbdev_device_timeout/latest


Test location /workspace/coverage/default/28.usbdev_disable_endpoint.2967463463
Short name T2679
Test name
Test status
Simulation time 730062834 ps
CPU time 1.68 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207548 kb
Host smart-72569f33-cbc3-4f8e-9e5a-de6fa65aa6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29674
63463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.2967463463
Directory /workspace/28.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/28.usbdev_disconnected.1103642454
Short name T1420
Test name
Test status
Simulation time 149179217 ps
CPU time 0.86 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207488 kb
Host smart-b8a2b3e6-f875-4cac-b138-1740ac265d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11036
42454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1103642454
Directory /workspace/28.usbdev_disconnected/latest


Test location /workspace/coverage/default/28.usbdev_enable.2486189952
Short name T1190
Test name
Test status
Simulation time 38553497 ps
CPU time 0.71 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 207536 kb
Host smart-53626a0c-210d-4bb4-9cd2-455a1b02522d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24861
89952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2486189952
Directory /workspace/28.usbdev_enable/latest


Test location /workspace/coverage/default/28.usbdev_endpoint_access.3254297371
Short name T969
Test name
Test status
Simulation time 1037652481 ps
CPU time 2.82 seconds
Started Aug 11 07:13:37 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 207740 kb
Host smart-daefed76-512e-4be9-9230-57e2337be55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32542
97371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3254297371
Directory /workspace/28.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/28.usbdev_endpoint_types.1745146288
Short name T1284
Test name
Test status
Simulation time 317514036 ps
CPU time 1.12 seconds
Started Aug 11 07:13:37 PM PDT 24
Finished Aug 11 07:13:38 PM PDT 24
Peak memory 207508 kb
Host smart-7fff116e-415a-47ee-a705-119c2d12cfc1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1745146288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.1745146288
Directory /workspace/28.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/28.usbdev_fifo_rst.902856332
Short name T3511
Test name
Test status
Simulation time 220270587 ps
CPU time 2.03 seconds
Started Aug 11 07:13:28 PM PDT 24
Finished Aug 11 07:13:30 PM PDT 24
Peak memory 207684 kb
Host smart-1ab9a9f6-044e-4901-80b4-ea65a3d1471e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90285
6332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.902856332
Directory /workspace/28.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/28.usbdev_in_iso.584661186
Short name T1141
Test name
Test status
Simulation time 157031031 ps
CPU time 0.95 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:13:36 PM PDT 24
Peak memory 207556 kb
Host smart-b1735a89-e6ea-4b53-8a4b-6b7f50c109e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=584661186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.584661186
Directory /workspace/28.usbdev_in_iso/latest


Test location /workspace/coverage/default/28.usbdev_in_stall.2940597865
Short name T2182
Test name
Test status
Simulation time 142634077 ps
CPU time 0.88 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207480 kb
Host smart-dab9b841-b1af-41c5-992e-39a55a3496b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29405
97865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2940597865
Directory /workspace/28.usbdev_in_stall/latest


Test location /workspace/coverage/default/28.usbdev_in_trans.1150483253
Short name T3536
Test name
Test status
Simulation time 229534160 ps
CPU time 1.06 seconds
Started Aug 11 07:13:37 PM PDT 24
Finished Aug 11 07:13:38 PM PDT 24
Peak memory 207548 kb
Host smart-700ce243-7e7c-49a6-8e39-88205038b842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
83253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1150483253
Directory /workspace/28.usbdev_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_invalid_sync.543057689
Short name T1273
Test name
Test status
Simulation time 4594179478 ps
CPU time 35.51 seconds
Started Aug 11 07:13:32 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 224456 kb
Host smart-4ae758b7-dd89-4837-a27f-5e61368a034a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=543057689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.543057689
Directory /workspace/28.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/28.usbdev_iso_retraction.153805639
Short name T1269
Test name
Test status
Simulation time 7561449330 ps
CPU time 85.06 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:14:59 PM PDT 24
Peak memory 207800 kb
Host smart-a818767f-8f15-4c01-b162-3dbb18d1d40c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=153805639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.153805639
Directory /workspace/28.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/28.usbdev_link_in_err.3559493593
Short name T1800
Test name
Test status
Simulation time 155361740 ps
CPU time 0.83 seconds
Started Aug 11 07:13:32 PM PDT 24
Finished Aug 11 07:13:33 PM PDT 24
Peak memory 207552 kb
Host smart-5a24ccd6-33b7-4699-99af-95d20f48a1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
93593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3559493593
Directory /workspace/28.usbdev_link_in_err/latest


Test location /workspace/coverage/default/28.usbdev_link_resume.1826771164
Short name T730
Test name
Test status
Simulation time 27605243487 ps
CPU time 38.5 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207712 kb
Host smart-3c31975c-38e8-4dc6-8c5b-cd38f43bbad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18267
71164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1826771164
Directory /workspace/28.usbdev_link_resume/latest


Test location /workspace/coverage/default/28.usbdev_link_suspend.709596225
Short name T1798
Test name
Test status
Simulation time 8594685609 ps
CPU time 10.35 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:43 PM PDT 24
Peak memory 207788 kb
Host smart-feb916ff-d7ed-457f-bf73-ddf75bc733e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70959
6225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.709596225
Directory /workspace/28.usbdev_link_suspend/latest


Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2235506976
Short name T3075
Test name
Test status
Simulation time 4878233283 ps
CPU time 140.28 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:15:55 PM PDT 24
Peak memory 218888 kb
Host smart-fe77a8ef-e993-444d-b266-6d372001bd51
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2235506976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2235506976
Directory /workspace/28.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2651922207
Short name T2192
Test name
Test status
Simulation time 2861504639 ps
CPU time 83.58 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 216108 kb
Host smart-36e1dfcf-873f-4abd-9a90-2ba1af4691f3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2651922207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2651922207
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1887152722
Short name T3008
Test name
Test status
Simulation time 257782022 ps
CPU time 1.03 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:13:36 PM PDT 24
Peak memory 207560 kb
Host smart-6be20581-f8b0-4c02-8b20-e5817b091900
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1887152722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1887152722
Directory /workspace/28.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2557875973
Short name T3494
Test name
Test status
Simulation time 192486880 ps
CPU time 0.93 seconds
Started Aug 11 07:13:31 PM PDT 24
Finished Aug 11 07:13:32 PM PDT 24
Peak memory 207556 kb
Host smart-54b3457a-cce6-4895-ae51-d578ae34c152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25578
75973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2557875973
Directory /workspace/28.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1820527494
Short name T813
Test name
Test status
Simulation time 3498801418 ps
CPU time 37.28 seconds
Started Aug 11 07:13:29 PM PDT 24
Finished Aug 11 07:14:06 PM PDT 24
Peak memory 217664 kb
Host smart-461bffa1-6603-4d1e-b955-3c39b0232fe0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1820527494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1820527494
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2792857397
Short name T1849
Test name
Test status
Simulation time 146140203 ps
CPU time 0.8 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 207408 kb
Host smart-02576b97-4f29-42f9-806a-d2269751b5a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2792857397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2792857397
Directory /workspace/28.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3022374185
Short name T3410
Test name
Test status
Simulation time 143293526 ps
CPU time 0.83 seconds
Started Aug 11 07:13:39 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 207572 kb
Host smart-e0a8bf00-7e0c-4761-a0e6-2510bdc11ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30223
74185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3022374185
Directory /workspace/28.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_nak_trans.3577034509
Short name T151
Test name
Test status
Simulation time 204810577 ps
CPU time 0.86 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207528 kb
Host smart-a91f3f14-56d7-4237-aab9-6553606ab124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35770
34509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3577034509
Directory /workspace/28.usbdev_nak_trans/latest


Test location /workspace/coverage/default/28.usbdev_out_iso.303522886
Short name T1246
Test name
Test status
Simulation time 165298788 ps
CPU time 0.86 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:13:36 PM PDT 24
Peak memory 207568 kb
Host smart-7946fe2a-3566-47f6-8bee-27b70d5d831f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
2886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.303522886
Directory /workspace/28.usbdev_out_iso/latest


Test location /workspace/coverage/default/28.usbdev_out_stall.1073644267
Short name T2707
Test name
Test status
Simulation time 170998331 ps
CPU time 0.91 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207572 kb
Host smart-1d5c297a-adc4-4f83-b4c4-6b09deccf0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10736
44267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1073644267
Directory /workspace/28.usbdev_out_stall/latest


Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2831393892
Short name T3470
Test name
Test status
Simulation time 187931959 ps
CPU time 0.86 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 207524 kb
Host smart-a8dd7d43-c2d2-47e5-813f-d2a74443a4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28313
93892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2831393892
Directory /workspace/28.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3938399720
Short name T708
Test name
Test status
Simulation time 157510396 ps
CPU time 0.94 seconds
Started Aug 11 07:13:30 PM PDT 24
Finished Aug 11 07:13:31 PM PDT 24
Peak memory 207556 kb
Host smart-b469b0bd-d353-4900-92bb-cea76a27cd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39383
99720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3938399720
Directory /workspace/28.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.330480845
Short name T2626
Test name
Test status
Simulation time 225549855 ps
CPU time 1.09 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 207572 kb
Host smart-47a9e983-e010-4d4c-961d-e68bb1fbbbbc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=330480845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.330480845
Directory /workspace/28.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1521965764
Short name T1747
Test name
Test status
Simulation time 195624089 ps
CPU time 0.88 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207452 kb
Host smart-b67feb19-4c23-43aa-9b3e-c817b15018cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15219
65764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1521965764
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/28.usbdev_pkt_buffer.272027449
Short name T3272
Test name
Test status
Simulation time 12072203328 ps
CPU time 29.71 seconds
Started Aug 11 07:13:39 PM PDT 24
Finished Aug 11 07:14:09 PM PDT 24
Peak memory 216068 kb
Host smart-b8236606-b9e2-4dc5-924b-6c70a4e20687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
7449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.272027449
Directory /workspace/28.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/28.usbdev_pkt_received.265021480
Short name T2995
Test name
Test status
Simulation time 170532765 ps
CPU time 0.94 seconds
Started Aug 11 07:13:43 PM PDT 24
Finished Aug 11 07:13:44 PM PDT 24
Peak memory 207596 kb
Host smart-fcf07130-2793-480e-a250-fb32eee7b9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26502
1480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.265021480
Directory /workspace/28.usbdev_pkt_received/latest


Test location /workspace/coverage/default/28.usbdev_pkt_sent.198130335
Short name T1561
Test name
Test status
Simulation time 207637565 ps
CPU time 0.93 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207544 kb
Host smart-3fb0f9a4-f6fb-4e9e-8c81-b6b7ae254f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19813
0335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.198130335
Directory /workspace/28.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2748500694
Short name T3430
Test name
Test status
Simulation time 197584297 ps
CPU time 0.91 seconds
Started Aug 11 07:13:41 PM PDT 24
Finished Aug 11 07:13:42 PM PDT 24
Peak memory 207552 kb
Host smart-c8bf07db-264a-4d56-90c2-fcf34f7be838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27485
00694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2748500694
Directory /workspace/28.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.872202348
Short name T1175
Test name
Test status
Simulation time 159678048 ps
CPU time 0.86 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207568 kb
Host smart-41de4805-e917-4868-bae1-53335b747fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87220
2348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.872202348
Directory /workspace/28.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2776835613
Short name T270
Test name
Test status
Simulation time 141761352 ps
CPU time 0.83 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:13:36 PM PDT 24
Peak memory 207492 kb
Host smart-bc3076b8-98d6-4932-ad34-1a56701b7cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768
35613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2776835613
Directory /workspace/28.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/28.usbdev_rx_full.3262944830
Short name T2651
Test name
Test status
Simulation time 254127946 ps
CPU time 1.11 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207544 kb
Host smart-c42c63a5-36ff-4711-81a9-4ec3208284b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32629
44830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.3262944830
Directory /workspace/28.usbdev_rx_full/latest


Test location /workspace/coverage/default/28.usbdev_setup_stage.1834760535
Short name T704
Test name
Test status
Simulation time 158110734 ps
CPU time 0.86 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 207512 kb
Host smart-22ae4e22-f638-4ae7-a246-982e6ec0575f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18347
60535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1834760535
Directory /workspace/28.usbdev_setup_stage/latest


Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2400972484
Short name T2678
Test name
Test status
Simulation time 180587747 ps
CPU time 0.92 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 207596 kb
Host smart-aa3fbeb1-9035-4743-bb91-7c92a559f07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24009
72484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2400972484
Directory /workspace/28.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/28.usbdev_smoke.2944196259
Short name T2111
Test name
Test status
Simulation time 247486934 ps
CPU time 1.07 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:36 PM PDT 24
Peak memory 207576 kb
Host smart-84db1e2b-2d85-4ff7-b5d0-55d8fe292e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29441
96259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2944196259
Directory /workspace/28.usbdev_smoke/latest


Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1180650414
Short name T110
Test name
Test status
Simulation time 2956867423 ps
CPU time 90.11 seconds
Started Aug 11 07:13:38 PM PDT 24
Finished Aug 11 07:15:09 PM PDT 24
Peak memory 217692 kb
Host smart-304ea09a-0ad9-445a-81ac-5357b43a7efd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1180650414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1180650414
Directory /workspace/28.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2659625918
Short name T894
Test name
Test status
Simulation time 166992297 ps
CPU time 0.88 seconds
Started Aug 11 07:13:33 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 207440 kb
Host smart-8e3b7c67-2c88-461a-babe-d7cdd19fd4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26596
25918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2659625918
Directory /workspace/28.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/28.usbdev_stall_trans.2457828359
Short name T2661
Test name
Test status
Simulation time 172388449 ps
CPU time 0.87 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207548 kb
Host smart-e28eda5a-35ba-4e6b-ac8d-66d73efffa35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24578
28359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2457828359
Directory /workspace/28.usbdev_stall_trans/latest


Test location /workspace/coverage/default/28.usbdev_stream_len_max.380808488
Short name T789
Test name
Test status
Simulation time 1207750516 ps
CPU time 2.94 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:13:39 PM PDT 24
Peak memory 207732 kb
Host smart-831831c6-237e-44c3-8f0d-296ace262fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38080
8488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.380808488
Directory /workspace/28.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/28.usbdev_streaming_out.2807619889
Short name T2695
Test name
Test status
Simulation time 2140382591 ps
CPU time 16.14 seconds
Started Aug 11 07:13:42 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 217540 kb
Host smart-3a845eb0-67d5-4b56-92ed-0d4561a1ea2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28076
19889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2807619889
Directory /workspace/28.usbdev_streaming_out/latest


Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.4212842413
Short name T1524
Test name
Test status
Simulation time 1553325042 ps
CPU time 9.47 seconds
Started Aug 11 07:13:31 PM PDT 24
Finished Aug 11 07:13:41 PM PDT 24
Peak memory 207764 kb
Host smart-82bbbb6c-4599-4f7c-b386-0b77aec59b6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212842413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.4212842413
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/28.usbdev_tx_rx_disruption.896671187
Short name T2972
Test name
Test status
Simulation time 481768348 ps
CPU time 1.52 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207568 kb
Host smart-55f25181-313a-440e-a85d-926ded11880b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896671187 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.usbdev_tx_rx_disruption.896671187
Directory /workspace/28.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/280.usbdev_tx_rx_disruption.815699906
Short name T641
Test name
Test status
Simulation time 462834852 ps
CPU time 1.51 seconds
Started Aug 11 07:17:44 PM PDT 24
Finished Aug 11 07:17:46 PM PDT 24
Peak memory 207544 kb
Host smart-27645c54-1ffa-4f97-9e97-74113cce1d02
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815699906 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 280.usbdev_tx_rx_disruption.815699906
Directory /workspace/280.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/281.usbdev_tx_rx_disruption.3454652442
Short name T175
Test name
Test status
Simulation time 597779929 ps
CPU time 1.66 seconds
Started Aug 11 07:17:29 PM PDT 24
Finished Aug 11 07:17:30 PM PDT 24
Peak memory 207552 kb
Host smart-c4225d88-b0f1-4b90-826d-8ed063319eba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454652442 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.usbdev_tx_rx_disruption.3454652442
Directory /workspace/281.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/282.usbdev_tx_rx_disruption.1985354524
Short name T817
Test name
Test status
Simulation time 485096116 ps
CPU time 1.67 seconds
Started Aug 11 07:17:44 PM PDT 24
Finished Aug 11 07:17:46 PM PDT 24
Peak memory 207544 kb
Host smart-159e4d5f-4652-4f96-b19a-06843a3e6b8c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985354524 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.usbdev_tx_rx_disruption.1985354524
Directory /workspace/282.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/283.usbdev_tx_rx_disruption.200102886
Short name T1480
Test name
Test status
Simulation time 520438761 ps
CPU time 1.53 seconds
Started Aug 11 07:17:41 PM PDT 24
Finished Aug 11 07:17:43 PM PDT 24
Peak memory 207500 kb
Host smart-781757a0-fb00-446a-aefc-8fa9e2cae60f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200102886 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 283.usbdev_tx_rx_disruption.200102886
Directory /workspace/283.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/284.usbdev_tx_rx_disruption.2337982066
Short name T3560
Test name
Test status
Simulation time 537475126 ps
CPU time 1.61 seconds
Started Aug 11 07:17:35 PM PDT 24
Finished Aug 11 07:17:37 PM PDT 24
Peak memory 207524 kb
Host smart-ded2037c-4e99-4c17-a1f9-6d36a3548a68
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337982066 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.usbdev_tx_rx_disruption.2337982066
Directory /workspace/284.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/285.usbdev_tx_rx_disruption.2066643395
Short name T1194
Test name
Test status
Simulation time 518280721 ps
CPU time 1.56 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:40 PM PDT 24
Peak memory 207580 kb
Host smart-7e9f8726-de8e-4c38-911e-da9c918290eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066643395 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.usbdev_tx_rx_disruption.2066643395
Directory /workspace/285.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/286.usbdev_tx_rx_disruption.110166813
Short name T1027
Test name
Test status
Simulation time 588785793 ps
CPU time 1.54 seconds
Started Aug 11 07:17:53 PM PDT 24
Finished Aug 11 07:17:54 PM PDT 24
Peak memory 207540 kb
Host smart-e64e324e-6b66-4b0c-b1a3-97487f35e7ca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110166813 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 286.usbdev_tx_rx_disruption.110166813
Directory /workspace/286.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/287.usbdev_tx_rx_disruption.1867789731
Short name T1328
Test name
Test status
Simulation time 624446762 ps
CPU time 1.59 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:32 PM PDT 24
Peak memory 207772 kb
Host smart-3ebbe0ee-8254-415b-88a3-ca2ba071f041
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867789731 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.usbdev_tx_rx_disruption.1867789731
Directory /workspace/287.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/288.usbdev_tx_rx_disruption.2713690862
Short name T2184
Test name
Test status
Simulation time 563751032 ps
CPU time 1.67 seconds
Started Aug 11 07:17:40 PM PDT 24
Finished Aug 11 07:17:41 PM PDT 24
Peak memory 207504 kb
Host smart-a4dfe5bf-2df6-4554-9085-73b85e495fe3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713690862 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.usbdev_tx_rx_disruption.2713690862
Directory /workspace/288.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/289.usbdev_tx_rx_disruption.844963059
Short name T1758
Test name
Test status
Simulation time 572750350 ps
CPU time 1.6 seconds
Started Aug 11 07:17:51 PM PDT 24
Finished Aug 11 07:17:53 PM PDT 24
Peak memory 207548 kb
Host smart-8ee69b76-d6b8-4310-87f1-66024201b876
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844963059 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 289.usbdev_tx_rx_disruption.844963059
Directory /workspace/289.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/29.usbdev_alert_test.1723957037
Short name T3606
Test name
Test status
Simulation time 63015943 ps
CPU time 0.69 seconds
Started Aug 11 07:13:56 PM PDT 24
Finished Aug 11 07:13:56 PM PDT 24
Peak memory 207504 kb
Host smart-0218c3db-f89d-4b31-9da5-c841c171b79e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1723957037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1723957037
Directory /workspace/29.usbdev_alert_test/latest


Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.803240052
Short name T1906
Test name
Test status
Simulation time 18967572100 ps
CPU time 24.73 seconds
Started Aug 11 07:13:37 PM PDT 24
Finished Aug 11 07:14:01 PM PDT 24
Peak memory 207816 kb
Host smart-172045c0-3630-4200-b7cb-a59af2f3970b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=803240052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.803240052
Directory /workspace/29.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.1280810949
Short name T219
Test name
Test status
Simulation time 25207565198 ps
CPU time 29.96 seconds
Started Aug 11 07:13:37 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 216060 kb
Host smart-ef083e6a-0600-487a-bf49-f7c87b8aeef9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280810949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.1280810949
Directory /workspace/29.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/29.usbdev_av_buffer.1511705923
Short name T3576
Test name
Test status
Simulation time 209960916 ps
CPU time 0.96 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207456 kb
Host smart-6329dcb5-6759-4a28-956f-72bc05359dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15117
05923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1511705923
Directory /workspace/29.usbdev_av_buffer/latest


Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2079528203
Short name T654
Test name
Test status
Simulation time 148125741 ps
CPU time 0.84 seconds
Started Aug 11 07:13:43 PM PDT 24
Finished Aug 11 07:13:44 PM PDT 24
Peak memory 207516 kb
Host smart-ba327206-5c62-42c2-bddb-e74ba4fc0b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20795
28203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2079528203
Directory /workspace/29.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.50219283
Short name T2155
Test name
Test status
Simulation time 527145605 ps
CPU time 1.95 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:36 PM PDT 24
Peak memory 207572 kb
Host smart-bf0d237f-b0d7-49fb-b6a9-b7626d140961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50219
283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.50219283
Directory /workspace/29.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1859752041
Short name T3054
Test name
Test status
Simulation time 1186472934 ps
CPU time 3.07 seconds
Started Aug 11 07:13:35 PM PDT 24
Finished Aug 11 07:13:38 PM PDT 24
Peak memory 207720 kb
Host smart-ed074078-c9d1-49c4-85bc-2a92c5dec91d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1859752041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1859752041
Directory /workspace/29.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/29.usbdev_device_address.3284855409
Short name T1950
Test name
Test status
Simulation time 35016094005 ps
CPU time 57.9 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 207776 kb
Host smart-e2515e1e-1af1-4066-aed8-4fe2c45597e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32848
55409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3284855409
Directory /workspace/29.usbdev_device_address/latest


Test location /workspace/coverage/default/29.usbdev_device_timeout.230265839
Short name T2000
Test name
Test status
Simulation time 446140537 ps
CPU time 8.22 seconds
Started Aug 11 07:13:31 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 207648 kb
Host smart-5a630b0a-e845-4f5b-8643-2f16e866e4a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230265839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.230265839
Directory /workspace/29.usbdev_device_timeout/latest


Test location /workspace/coverage/default/29.usbdev_disable_endpoint.4045524807
Short name T3479
Test name
Test status
Simulation time 652960651 ps
CPU time 1.83 seconds
Started Aug 11 07:13:40 PM PDT 24
Finished Aug 11 07:13:42 PM PDT 24
Peak memory 207524 kb
Host smart-209f8b81-0a0a-4209-8616-4ce4bf670c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40455
24807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.4045524807
Directory /workspace/29.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/29.usbdev_disconnected.4125367240
Short name T3368
Test name
Test status
Simulation time 188436389 ps
CPU time 0.86 seconds
Started Aug 11 07:13:57 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207508 kb
Host smart-c81e608d-b42e-4d53-b4cb-98adef35ceea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41253
67240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.4125367240
Directory /workspace/29.usbdev_disconnected/latest


Test location /workspace/coverage/default/29.usbdev_enable.2278305431
Short name T2896
Test name
Test status
Simulation time 45570247 ps
CPU time 0.71 seconds
Started Aug 11 07:13:39 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 207452 kb
Host smart-dea7af33-eed6-46dc-afe1-478e2ca15d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
05431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2278305431
Directory /workspace/29.usbdev_enable/latest


Test location /workspace/coverage/default/29.usbdev_endpoint_access.3561319085
Short name T1874
Test name
Test status
Simulation time 762932570 ps
CPU time 2.14 seconds
Started Aug 11 07:13:47 PM PDT 24
Finished Aug 11 07:13:50 PM PDT 24
Peak memory 207764 kb
Host smart-c82d5d12-f5d9-4c82-85d7-cc540fe3db2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35613
19085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3561319085
Directory /workspace/29.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/29.usbdev_endpoint_types.328286366
Short name T482
Test name
Test status
Simulation time 363820886 ps
CPU time 1.08 seconds
Started Aug 11 07:13:41 PM PDT 24
Finished Aug 11 07:13:42 PM PDT 24
Peak memory 207536 kb
Host smart-d8b370b0-36f8-42bc-b6c2-1f4b1b1e993e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=328286366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.328286366
Directory /workspace/29.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/29.usbdev_fifo_rst.195987166
Short name T1391
Test name
Test status
Simulation time 182313405 ps
CPU time 2.2 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:37 PM PDT 24
Peak memory 207648 kb
Host smart-03143fa5-cf55-4d50-b359-73bb651a5f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19598
7166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.195987166
Directory /workspace/29.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/29.usbdev_in_iso.3264289840
Short name T2690
Test name
Test status
Simulation time 160189166 ps
CPU time 0.87 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207592 kb
Host smart-51768d3e-493c-427b-b638-f9a9824cf55a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3264289840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3264289840
Directory /workspace/29.usbdev_in_iso/latest


Test location /workspace/coverage/default/29.usbdev_in_stall.2885299151
Short name T1307
Test name
Test status
Simulation time 143351761 ps
CPU time 0.85 seconds
Started Aug 11 07:13:46 PM PDT 24
Finished Aug 11 07:13:47 PM PDT 24
Peak memory 207516 kb
Host smart-b7ae54bb-8fc0-49c2-8b9b-510d0d312095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28852
99151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2885299151
Directory /workspace/29.usbdev_in_stall/latest


Test location /workspace/coverage/default/29.usbdev_in_trans.2803440497
Short name T2533
Test name
Test status
Simulation time 201092076 ps
CPU time 1 seconds
Started Aug 11 07:13:43 PM PDT 24
Finished Aug 11 07:13:44 PM PDT 24
Peak memory 207508 kb
Host smart-fc2e51b0-a519-40fb-b159-87a1096a9f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28034
40497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2803440497
Directory /workspace/29.usbdev_in_trans/latest


Test location /workspace/coverage/default/29.usbdev_invalid_sync.2826234761
Short name T1395
Test name
Test status
Simulation time 4065708831 ps
CPU time 40.92 seconds
Started Aug 11 07:13:38 PM PDT 24
Finished Aug 11 07:14:19 PM PDT 24
Peak memory 224136 kb
Host smart-bd02467c-1ac8-4993-a0c3-79919d857c2a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2826234761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2826234761
Directory /workspace/29.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/29.usbdev_iso_retraction.2215676671
Short name T1604
Test name
Test status
Simulation time 12052199219 ps
CPU time 142.08 seconds
Started Aug 11 07:13:41 PM PDT 24
Finished Aug 11 07:16:03 PM PDT 24
Peak memory 207748 kb
Host smart-832a8a7c-f964-455c-a408-7bbb703a2bd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2215676671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.2215676671
Directory /workspace/29.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/29.usbdev_link_in_err.2229128124
Short name T878
Test name
Test status
Simulation time 202882215 ps
CPU time 0.95 seconds
Started Aug 11 07:13:34 PM PDT 24
Finished Aug 11 07:13:35 PM PDT 24
Peak memory 207548 kb
Host smart-1876982b-3dc6-4c20-b706-089564a6a3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22291
28124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2229128124
Directory /workspace/29.usbdev_link_in_err/latest


Test location /workspace/coverage/default/29.usbdev_link_resume.199456426
Short name T1394
Test name
Test status
Simulation time 31845403996 ps
CPU time 48.52 seconds
Started Aug 11 07:13:36 PM PDT 24
Finished Aug 11 07:14:25 PM PDT 24
Peak memory 207872 kb
Host smart-7ab72232-6002-4a4f-a250-1f5226d9b983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19945
6426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.199456426
Directory /workspace/29.usbdev_link_resume/latest


Test location /workspace/coverage/default/29.usbdev_link_suspend.3621868733
Short name T2989
Test name
Test status
Simulation time 5836106953 ps
CPU time 8.22 seconds
Started Aug 11 07:13:41 PM PDT 24
Finished Aug 11 07:13:49 PM PDT 24
Peak memory 216120 kb
Host smart-656ad980-dd23-4595-aae9-16fa47eb0175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36218
68733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3621868733
Directory /workspace/29.usbdev_link_suspend/latest


Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.1607488226
Short name T1083
Test name
Test status
Simulation time 3165094790 ps
CPU time 89.04 seconds
Started Aug 11 07:13:45 PM PDT 24
Finished Aug 11 07:15:14 PM PDT 24
Peak memory 218780 kb
Host smart-97d1cdc7-8476-4414-b935-3e515f36f2d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1607488226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1607488226
Directory /workspace/29.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.3451785985
Short name T1840
Test name
Test status
Simulation time 1815144098 ps
CPU time 16.93 seconds
Started Aug 11 07:13:39 PM PDT 24
Finished Aug 11 07:13:56 PM PDT 24
Peak memory 224040 kb
Host smart-ff3679de-29d2-4f6a-a233-29e3e1be1dd4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3451785985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3451785985
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1926864005
Short name T2891
Test name
Test status
Simulation time 233556491 ps
CPU time 1.03 seconds
Started Aug 11 07:13:45 PM PDT 24
Finished Aug 11 07:13:46 PM PDT 24
Peak memory 207556 kb
Host smart-011e9d44-1f7d-4b81-848c-4fe2e83daff0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1926864005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1926864005
Directory /workspace/29.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2084574013
Short name T20
Test name
Test status
Simulation time 233053226 ps
CPU time 0.98 seconds
Started Aug 11 07:13:50 PM PDT 24
Finished Aug 11 07:13:51 PM PDT 24
Peak memory 207564 kb
Host smart-571913ae-8a33-45aa-8ce4-5c38d2aca0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20845
74013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2084574013
Directory /workspace/29.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.220827128
Short name T1723
Test name
Test status
Simulation time 2739895737 ps
CPU time 27.96 seconds
Started Aug 11 07:13:40 PM PDT 24
Finished Aug 11 07:14:08 PM PDT 24
Peak memory 217820 kb
Host smart-3bb6b464-63e7-4292-a155-4471cff61398
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=220827128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.220827128
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2504480449
Short name T3353
Test name
Test status
Simulation time 191039393 ps
CPU time 0.86 seconds
Started Aug 11 07:13:43 PM PDT 24
Finished Aug 11 07:13:44 PM PDT 24
Peak memory 207568 kb
Host smart-5768eb69-f1d0-4808-b9e4-de54021cc2dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2504480449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2504480449
Directory /workspace/29.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2102464190
Short name T2509
Test name
Test status
Simulation time 140468189 ps
CPU time 0.85 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207552 kb
Host smart-a31edb35-08a8-4066-9d05-f4b00d2aac57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21024
64190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2102464190
Directory /workspace/29.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_nak_trans.208606984
Short name T3564
Test name
Test status
Simulation time 222327555 ps
CPU time 1 seconds
Started Aug 11 07:13:53 PM PDT 24
Finished Aug 11 07:13:54 PM PDT 24
Peak memory 207480 kb
Host smart-9de25883-6771-47c6-a220-3a66ec88cc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20860
6984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.208606984
Directory /workspace/29.usbdev_nak_trans/latest


Test location /workspace/coverage/default/29.usbdev_out_iso.2154131919
Short name T610
Test name
Test status
Simulation time 193317491 ps
CPU time 0.97 seconds
Started Aug 11 07:14:00 PM PDT 24
Finished Aug 11 07:14:01 PM PDT 24
Peak memory 207492 kb
Host smart-eb8fbdd2-36d7-4a02-bffc-68ef0cec804b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21541
31919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2154131919
Directory /workspace/29.usbdev_out_iso/latest


Test location /workspace/coverage/default/29.usbdev_out_stall.2145978424
Short name T2574
Test name
Test status
Simulation time 157773832 ps
CPU time 0.85 seconds
Started Aug 11 07:13:50 PM PDT 24
Finished Aug 11 07:13:51 PM PDT 24
Peak memory 207560 kb
Host smart-a4d94db3-0650-4f1e-aac3-bb3907514e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21459
78424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2145978424
Directory /workspace/29.usbdev_out_stall/latest


Test location /workspace/coverage/default/29.usbdev_out_trans_nak.56960410
Short name T2631
Test name
Test status
Simulation time 200614095 ps
CPU time 0.86 seconds
Started Aug 11 07:13:39 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 207488 kb
Host smart-98d87ec1-63c7-4632-8031-222b0b38fec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56960
410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.56960410
Directory /workspace/29.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/29.usbdev_pending_in_trans.315700162
Short name T1384
Test name
Test status
Simulation time 160540019 ps
CPU time 0.88 seconds
Started Aug 11 07:13:40 PM PDT 24
Finished Aug 11 07:13:41 PM PDT 24
Peak memory 207552 kb
Host smart-119bdaa2-9352-418c-b010-dd27bdc3e875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31570
0162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.315700162
Directory /workspace/29.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.4159420828
Short name T3554
Test name
Test status
Simulation time 240492177 ps
CPU time 1.07 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 207572 kb
Host smart-888d5b59-8d5b-40c9-8650-a7782050f09e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4159420828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.4159420828
Directory /workspace/29.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3240623335
Short name T222
Test name
Test status
Simulation time 220443055 ps
CPU time 0.93 seconds
Started Aug 11 07:13:46 PM PDT 24
Finished Aug 11 07:13:47 PM PDT 24
Peak memory 207520 kb
Host smart-d91ed6d0-6620-4821-9d17-ebebceab1f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32406
23335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3240623335
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3688551033
Short name T3114
Test name
Test status
Simulation time 45570402 ps
CPU time 0.72 seconds
Started Aug 11 07:13:44 PM PDT 24
Finished Aug 11 07:13:45 PM PDT 24
Peak memory 207468 kb
Host smart-e38ac38b-4f97-4333-8111-5e9b3cf3208e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36885
51033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3688551033
Directory /workspace/29.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/29.usbdev_pkt_buffer.115458657
Short name T2670
Test name
Test status
Simulation time 18991966084 ps
CPU time 51.28 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:14:42 PM PDT 24
Peak memory 220704 kb
Host smart-22a98882-9058-4ac8-9223-706faa030850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11545
8657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.115458657
Directory /workspace/29.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/29.usbdev_pkt_received.717732633
Short name T931
Test name
Test status
Simulation time 192271016 ps
CPU time 0.93 seconds
Started Aug 11 07:13:39 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 207480 kb
Host smart-864364f2-2864-4bd6-86d7-2b41d4068c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71773
2633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.717732633
Directory /workspace/29.usbdev_pkt_received/latest


Test location /workspace/coverage/default/29.usbdev_pkt_sent.694605594
Short name T2304
Test name
Test status
Simulation time 207519141 ps
CPU time 0.97 seconds
Started Aug 11 07:13:49 PM PDT 24
Finished Aug 11 07:13:50 PM PDT 24
Peak memory 207532 kb
Host smart-034915c1-7c3c-44ad-b2c6-4daefe57aa04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69460
5594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.694605594
Directory /workspace/29.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2050360289
Short name T595
Test name
Test status
Simulation time 171779422 ps
CPU time 0.9 seconds
Started Aug 11 07:13:53 PM PDT 24
Finished Aug 11 07:13:54 PM PDT 24
Peak memory 207568 kb
Host smart-aa4f48cd-abc3-43c1-a91f-78cf75224e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20503
60289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2050360289
Directory /workspace/29.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1880394760
Short name T945
Test name
Test status
Simulation time 187792518 ps
CPU time 0.95 seconds
Started Aug 11 07:14:04 PM PDT 24
Finished Aug 11 07:14:05 PM PDT 24
Peak memory 207572 kb
Host smart-c249957b-b940-458b-a039-55705bb62e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18803
94760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1880394760
Directory /workspace/29.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3155263717
Short name T3029
Test name
Test status
Simulation time 168611490 ps
CPU time 0.85 seconds
Started Aug 11 07:13:53 PM PDT 24
Finished Aug 11 07:13:54 PM PDT 24
Peak memory 207584 kb
Host smart-c2cdfaa1-1c08-4322-ac3f-053cfa44154e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31552
63717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3155263717
Directory /workspace/29.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/29.usbdev_rx_full.4149466620
Short name T3569
Test name
Test status
Simulation time 359582367 ps
CPU time 1.33 seconds
Started Aug 11 07:13:46 PM PDT 24
Finished Aug 11 07:13:47 PM PDT 24
Peak memory 207584 kb
Host smart-aec738c6-c680-423e-a6e0-80bff4fa6a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41494
66620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.4149466620
Directory /workspace/29.usbdev_rx_full/latest


Test location /workspace/coverage/default/29.usbdev_setup_stage.378375935
Short name T2059
Test name
Test status
Simulation time 190458051 ps
CPU time 0.85 seconds
Started Aug 11 07:14:06 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 207536 kb
Host smart-ccbfb2a0-35c2-4130-b47c-2708fb053d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37837
5935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.378375935
Directory /workspace/29.usbdev_setup_stage/latest


Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1613265121
Short name T941
Test name
Test status
Simulation time 154282083 ps
CPU time 0.91 seconds
Started Aug 11 07:13:53 PM PDT 24
Finished Aug 11 07:13:54 PM PDT 24
Peak memory 207576 kb
Host smart-dff74f43-ef20-4790-ab18-ea6da6a17779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16132
65121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1613265121
Directory /workspace/29.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/29.usbdev_smoke.2579655689
Short name T1080
Test name
Test status
Simulation time 226209029 ps
CPU time 1.02 seconds
Started Aug 11 07:14:05 PM PDT 24
Finished Aug 11 07:14:06 PM PDT 24
Peak memory 207516 kb
Host smart-9de5d1da-3fed-4dfb-a206-17dd7aa520b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25796
55689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2579655689
Directory /workspace/29.usbdev_smoke/latest


Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2810941457
Short name T1396
Test name
Test status
Simulation time 3420988561 ps
CPU time 101.57 seconds
Started Aug 11 07:13:45 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 216100 kb
Host smart-77f899e0-746a-48c6-a308-c9fc82c717cb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2810941457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2810941457
Directory /workspace/29.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.864162446
Short name T1423
Test name
Test status
Simulation time 182104125 ps
CPU time 0.86 seconds
Started Aug 11 07:13:40 PM PDT 24
Finished Aug 11 07:13:41 PM PDT 24
Peak memory 207572 kb
Host smart-74d89758-3628-40a2-bec0-1d022ad40413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86416
2446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.864162446
Directory /workspace/29.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/29.usbdev_stall_trans.341782599
Short name T1224
Test name
Test status
Simulation time 157469707 ps
CPU time 0.85 seconds
Started Aug 11 07:13:46 PM PDT 24
Finished Aug 11 07:13:47 PM PDT 24
Peak memory 207600 kb
Host smart-0bdf0209-9939-4e53-a358-ba19e4c9dfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34178
2599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.341782599
Directory /workspace/29.usbdev_stall_trans/latest


Test location /workspace/coverage/default/29.usbdev_stream_len_max.1890942985
Short name T914
Test name
Test status
Simulation time 968100052 ps
CPU time 2.24 seconds
Started Aug 11 07:13:55 PM PDT 24
Finished Aug 11 07:13:57 PM PDT 24
Peak memory 207576 kb
Host smart-4e38abcc-0162-49b3-8885-feaae2d73c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18909
42985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1890942985
Directory /workspace/29.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/29.usbdev_streaming_out.2149197092
Short name T3379
Test name
Test status
Simulation time 1928998628 ps
CPU time 19.83 seconds
Started Aug 11 07:14:01 PM PDT 24
Finished Aug 11 07:14:21 PM PDT 24
Peak memory 216740 kb
Host smart-46504a8a-3513-4ea5-bfd6-441c9cf8f32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21491
97092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.2149197092
Directory /workspace/29.usbdev_streaming_out/latest


Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.323366598
Short name T814
Test name
Test status
Simulation time 2493977716 ps
CPU time 22.42 seconds
Started Aug 11 07:13:31 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 207860 kb
Host smart-c49b2e43-135f-4ebd-8054-3a4519a629b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323366598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_host
_handshake.323366598
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/29.usbdev_tx_rx_disruption.2743099327
Short name T3484
Test name
Test status
Simulation time 629791491 ps
CPU time 1.65 seconds
Started Aug 11 07:13:57 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207512 kb
Host smart-86a22b69-d487-48cb-ae68-3f36bc541449
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743099327 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.usbdev_tx_rx_disruption.2743099327
Directory /workspace/29.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/290.usbdev_tx_rx_disruption.1334532998
Short name T764
Test name
Test status
Simulation time 503121404 ps
CPU time 1.53 seconds
Started Aug 11 07:17:52 PM PDT 24
Finished Aug 11 07:17:54 PM PDT 24
Peak memory 207516 kb
Host smart-e363584c-1c2f-4f13-9c91-6b66ac7d509c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334532998 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.usbdev_tx_rx_disruption.1334532998
Directory /workspace/290.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/291.usbdev_tx_rx_disruption.3354954923
Short name T636
Test name
Test status
Simulation time 440691016 ps
CPU time 1.4 seconds
Started Aug 11 07:17:46 PM PDT 24
Finished Aug 11 07:17:47 PM PDT 24
Peak memory 207552 kb
Host smart-f5c58234-4657-4d6a-94e5-7d682a47c242
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354954923 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.usbdev_tx_rx_disruption.3354954923
Directory /workspace/291.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/292.usbdev_tx_rx_disruption.388685617
Short name T2964
Test name
Test status
Simulation time 471660946 ps
CPU time 1.52 seconds
Started Aug 11 07:17:44 PM PDT 24
Finished Aug 11 07:17:46 PM PDT 24
Peak memory 207504 kb
Host smart-60b23c38-4789-4a7d-af99-9d7cb9603874
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388685617 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 292.usbdev_tx_rx_disruption.388685617
Directory /workspace/292.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/293.usbdev_tx_rx_disruption.2922988687
Short name T2929
Test name
Test status
Simulation time 505191946 ps
CPU time 1.51 seconds
Started Aug 11 07:17:47 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207572 kb
Host smart-f69f88a4-b01f-4da5-9f76-c098ec38d8e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922988687 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.usbdev_tx_rx_disruption.2922988687
Directory /workspace/293.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/294.usbdev_tx_rx_disruption.1605110517
Short name T1482
Test name
Test status
Simulation time 551614769 ps
CPU time 1.57 seconds
Started Aug 11 07:17:33 PM PDT 24
Finished Aug 11 07:17:35 PM PDT 24
Peak memory 207764 kb
Host smart-142db915-8599-4c2e-89c4-b927a8a4398f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605110517 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.usbdev_tx_rx_disruption.1605110517
Directory /workspace/294.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/295.usbdev_tx_rx_disruption.555943332
Short name T864
Test name
Test status
Simulation time 478331100 ps
CPU time 1.44 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:36 PM PDT 24
Peak memory 207776 kb
Host smart-55c0bb59-b0e8-4d9d-8c6e-af2b8019a997
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555943332 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 295.usbdev_tx_rx_disruption.555943332
Directory /workspace/295.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/296.usbdev_tx_rx_disruption.2602884074
Short name T2805
Test name
Test status
Simulation time 528444491 ps
CPU time 1.64 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:32 PM PDT 24
Peak memory 207592 kb
Host smart-cf871256-98f2-4494-94a7-88ee576a79ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602884074 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.usbdev_tx_rx_disruption.2602884074
Directory /workspace/296.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/297.usbdev_tx_rx_disruption.2474463164
Short name T199
Test name
Test status
Simulation time 512346451 ps
CPU time 1.61 seconds
Started Aug 11 07:17:48 PM PDT 24
Finished Aug 11 07:17:50 PM PDT 24
Peak memory 207516 kb
Host smart-cdd86e6f-7902-41e6-aea7-36d1407084eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474463164 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.usbdev_tx_rx_disruption.2474463164
Directory /workspace/297.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/298.usbdev_tx_rx_disruption.4161132562
Short name T1118
Test name
Test status
Simulation time 586184719 ps
CPU time 1.72 seconds
Started Aug 11 07:17:51 PM PDT 24
Finished Aug 11 07:17:52 PM PDT 24
Peak memory 207456 kb
Host smart-9eaa1661-5689-425f-a9d2-a2830fcd286b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161132562 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.usbdev_tx_rx_disruption.4161132562
Directory /workspace/298.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/299.usbdev_tx_rx_disruption.986364316
Short name T2864
Test name
Test status
Simulation time 642254415 ps
CPU time 1.72 seconds
Started Aug 11 07:17:48 PM PDT 24
Finished Aug 11 07:17:50 PM PDT 24
Peak memory 207564 kb
Host smart-ec75ef59-3017-4cff-b75b-4c9a4d2b4848
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986364316 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 299.usbdev_tx_rx_disruption.986364316
Directory /workspace/299.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/3.usbdev_alert_test.3635864936
Short name T3001
Test name
Test status
Simulation time 37367794 ps
CPU time 0.66 seconds
Started Aug 11 07:09:12 PM PDT 24
Finished Aug 11 07:09:12 PM PDT 24
Peak memory 207548 kb
Host smart-979d3734-8ac1-4e38-bddf-8194bcf2df63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3635864936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3635864936
Directory /workspace/3.usbdev_alert_test/latest


Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3486835193
Short name T3396
Test name
Test status
Simulation time 11044048962 ps
CPU time 14.7 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:09:19 PM PDT 24
Peak memory 207840 kb
Host smart-76c10149-839f-4fc6-b976-9c8fe3d1daea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486835193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.3486835193
Directory /workspace/3.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.4074556971
Short name T2236
Test name
Test status
Simulation time 19567503878 ps
CPU time 27.51 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:33 PM PDT 24
Peak memory 207856 kb
Host smart-345e31a5-e72a-4a0d-a9cf-a932d7525607
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074556971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.4074556971
Directory /workspace/3.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3410091657
Short name T890
Test name
Test status
Simulation time 26362323015 ps
CPU time 31 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:09:35 PM PDT 24
Peak memory 215980 kb
Host smart-980d8375-0591-46ab-be22-d3019bec3d16
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410091657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.3410091657
Directory /workspace/3.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/3.usbdev_av_buffer.3188700511
Short name T401
Test name
Test status
Simulation time 158192249 ps
CPU time 0.9 seconds
Started Aug 11 07:09:08 PM PDT 24
Finished Aug 11 07:09:09 PM PDT 24
Peak memory 207584 kb
Host smart-57a996a9-e325-4112-bb2d-1c20f4d7a062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31887
00511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3188700511
Directory /workspace/3.usbdev_av_buffer/latest


Test location /workspace/coverage/default/3.usbdev_av_empty.1227480172
Short name T57
Test name
Test status
Simulation time 173905747 ps
CPU time 0.96 seconds
Started Aug 11 07:09:07 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 207548 kb
Host smart-b08f8275-3e4f-4d1c-a32f-67ee99a7de61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12274
80172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1227480172
Directory /workspace/3.usbdev_av_empty/latest


Test location /workspace/coverage/default/3.usbdev_av_overflow.2024785827
Short name T91
Test name
Test status
Simulation time 130511100 ps
CPU time 0.82 seconds
Started Aug 11 07:09:05 PM PDT 24
Finished Aug 11 07:09:06 PM PDT 24
Peak memory 207568 kb
Host smart-5885c77d-dbfe-478d-9f25-265f34da920c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20247
85827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2024785827
Directory /workspace/3.usbdev_av_overflow/latest


Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1559146570
Short name T1587
Test name
Test status
Simulation time 151417805 ps
CPU time 0.81 seconds
Started Aug 11 07:09:05 PM PDT 24
Finished Aug 11 07:09:05 PM PDT 24
Peak memory 207488 kb
Host smart-a1487afb-7d3c-4291-adc4-b04b0df5c3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15591
46570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1559146570
Directory /workspace/3.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1549230434
Short name T3445
Test name
Test status
Simulation time 306333539 ps
CPU time 1.28 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 207516 kb
Host smart-43aec17c-0423-492a-980b-93f6ee5d21df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
30434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1549230434
Directory /workspace/3.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.31482535
Short name T3501
Test name
Test status
Simulation time 921398686 ps
CPU time 2.51 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:09:07 PM PDT 24
Peak memory 207660 kb
Host smart-931d9115-d7ce-4866-ba85-8e89699cfec1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=31482535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.31482535
Directory /workspace/3.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/3.usbdev_device_timeout.1651643258
Short name T981
Test name
Test status
Simulation time 1333259619 ps
CPU time 29.91 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:09:34 PM PDT 24
Peak memory 207772 kb
Host smart-a8f0b600-baae-48b5-a0b8-e66281fc4c2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651643258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.1651643258
Directory /workspace/3.usbdev_device_timeout/latest


Test location /workspace/coverage/default/3.usbdev_disable_endpoint.312072485
Short name T2318
Test name
Test status
Simulation time 926914295 ps
CPU time 2 seconds
Started Aug 11 07:09:07 PM PDT 24
Finished Aug 11 07:09:09 PM PDT 24
Peak memory 207488 kb
Host smart-e8cf7f34-be0c-42e2-b8cf-fb4aea18b316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31207
2485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.312072485
Directory /workspace/3.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/3.usbdev_disconnected.1440829766
Short name T782
Test name
Test status
Simulation time 149104383 ps
CPU time 0.86 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:07 PM PDT 24
Peak memory 207528 kb
Host smart-3889daec-84d5-455e-854d-3f998347dce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14408
29766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1440829766
Directory /workspace/3.usbdev_disconnected/latest


Test location /workspace/coverage/default/3.usbdev_enable.4108362098
Short name T2620
Test name
Test status
Simulation time 29800048 ps
CPU time 0.69 seconds
Started Aug 11 07:09:05 PM PDT 24
Finished Aug 11 07:09:06 PM PDT 24
Peak memory 207484 kb
Host smart-7596e370-663d-4f84-8473-3c822f95f240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41083
62098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.4108362098
Directory /workspace/3.usbdev_enable/latest


Test location /workspace/coverage/default/3.usbdev_endpoint_access.232964026
Short name T2030
Test name
Test status
Simulation time 828876285 ps
CPU time 2.31 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 207744 kb
Host smart-aee15889-8553-4277-92cb-52997413d971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23296
4026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.232964026
Directory /workspace/3.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/3.usbdev_endpoint_types.1798644870
Short name T541
Test name
Test status
Simulation time 439022932 ps
CPU time 1.39 seconds
Started Aug 11 07:09:05 PM PDT 24
Finished Aug 11 07:09:07 PM PDT 24
Peak memory 207512 kb
Host smart-16f9102b-1fec-40a7-ba2b-4d1b5efd475d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1798644870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.1798644870
Directory /workspace/3.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/3.usbdev_fifo_rst.4112504684
Short name T2639
Test name
Test status
Simulation time 250279376 ps
CPU time 1.7 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:09:06 PM PDT 24
Peak memory 207696 kb
Host smart-6bce1bdc-e6ee-4cf1-8a23-c41f4c491649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41125
04684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.4112504684
Directory /workspace/3.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/3.usbdev_freq_hiclk.1144426799
Short name T361
Test name
Test status
Simulation time 100256159974 ps
CPU time 159.76 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 207784 kb
Host smart-3f7e2c9c-c9b3-4f27-9759-b5a8ee997400
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1144426799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.1144426799
Directory /workspace/3.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.1417684457
Short name T365
Test name
Test status
Simulation time 114012401226 ps
CPU time 182.45 seconds
Started Aug 11 07:09:05 PM PDT 24
Finished Aug 11 07:12:07 PM PDT 24
Peak memory 207908 kb
Host smart-9c72f6ce-7600-4d03-a8f1-65ed5734645b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417684457 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.1417684457
Directory /workspace/3.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/3.usbdev_freq_loclk.2647102192
Short name T831
Test name
Test status
Simulation time 114133339975 ps
CPU time 172.91 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:11:57 PM PDT 24
Peak memory 207716 kb
Host smart-396fade6-72ca-412a-afd2-47d0c8f6df79
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2647102192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.2647102192
Directory /workspace/3.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.555094839
Short name T600
Test name
Test status
Simulation time 88962635577 ps
CPU time 137.44 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 207776 kb
Host smart-4520b7d8-066f-4e9f-9fdf-69bc23f8558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555094839 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.555094839
Directory /workspace/3.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/3.usbdev_freq_phase.1069117745
Short name T873
Test name
Test status
Simulation time 87166439224 ps
CPU time 134.72 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 207756 kb
Host smart-2ffb8e87-9761-48f7-85cb-bbefbdc8cfa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10691
17745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.1069117745
Directory /workspace/3.usbdev_freq_phase/latest


Test location /workspace/coverage/default/3.usbdev_in_iso.661191104
Short name T1373
Test name
Test status
Simulation time 224047283 ps
CPU time 1.15 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 215880 kb
Host smart-cd71e39d-fc38-4f76-9da8-ddda2e949dec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=661191104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.661191104
Directory /workspace/3.usbdev_in_iso/latest


Test location /workspace/coverage/default/3.usbdev_in_stall.2559726277
Short name T1437
Test name
Test status
Simulation time 137304219 ps
CPU time 0.87 seconds
Started Aug 11 07:09:10 PM PDT 24
Finished Aug 11 07:09:11 PM PDT 24
Peak memory 207448 kb
Host smart-60249992-4916-486e-8869-fff5b317a0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25597
26277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2559726277
Directory /workspace/3.usbdev_in_stall/latest


Test location /workspace/coverage/default/3.usbdev_in_trans.607139188
Short name T997
Test name
Test status
Simulation time 194339671 ps
CPU time 0.99 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:09:05 PM PDT 24
Peak memory 207564 kb
Host smart-bb752590-2d6b-4cea-8135-d367a0972ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60713
9188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.607139188
Directory /workspace/3.usbdev_in_trans/latest


Test location /workspace/coverage/default/3.usbdev_invalid_sync.3745472602
Short name T2367
Test name
Test status
Simulation time 2841647429 ps
CPU time 22.43 seconds
Started Aug 11 07:09:07 PM PDT 24
Finished Aug 11 07:09:29 PM PDT 24
Peak memory 218396 kb
Host smart-f0b0eb1f-9a72-4435-8646-fd9f757dfb69
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3745472602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3745472602
Directory /workspace/3.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/3.usbdev_iso_retraction.1150432856
Short name T1153
Test name
Test status
Simulation time 4343298455 ps
CPU time 53.99 seconds
Started Aug 11 07:09:05 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 207824 kb
Host smart-4d573149-819f-4c9f-ac13-018a197471ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1150432856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.1150432856
Directory /workspace/3.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/3.usbdev_link_in_err.2968775866
Short name T2946
Test name
Test status
Simulation time 215867503 ps
CPU time 0.98 seconds
Started Aug 11 07:09:07 PM PDT 24
Finished Aug 11 07:09:08 PM PDT 24
Peak memory 207520 kb
Host smart-27db3d93-6082-43bd-a82f-bad2789138ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29687
75866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2968775866
Directory /workspace/3.usbdev_link_in_err/latest


Test location /workspace/coverage/default/3.usbdev_link_resume.281946861
Short name T896
Test name
Test status
Simulation time 32297158376 ps
CPU time 52.06 seconds
Started Aug 11 07:09:07 PM PDT 24
Finished Aug 11 07:09:59 PM PDT 24
Peak memory 207844 kb
Host smart-84e329e0-94f2-4c69-94e9-7da0200ce579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28194
6861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.281946861
Directory /workspace/3.usbdev_link_resume/latest


Test location /workspace/coverage/default/3.usbdev_link_suspend.869071229
Short name T1339
Test name
Test status
Simulation time 11048312674 ps
CPU time 13.65 seconds
Started Aug 11 07:09:10 PM PDT 24
Finished Aug 11 07:09:24 PM PDT 24
Peak memory 207780 kb
Host smart-39b66bd2-07f2-4492-af06-2b9b237c2da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86907
1229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.869071229
Directory /workspace/3.usbdev_link_suspend/latest


Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.328019402
Short name T3019
Test name
Test status
Simulation time 3793017834 ps
CPU time 112.02 seconds
Started Aug 11 07:09:04 PM PDT 24
Finished Aug 11 07:10:56 PM PDT 24
Peak memory 219052 kb
Host smart-a2ce484f-e40d-4f4f-9c2e-e17deca34d7f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=328019402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.328019402
Directory /workspace/3.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1589152846
Short name T1004
Test name
Test status
Simulation time 2466407736 ps
CPU time 24.78 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:30 PM PDT 24
Peak memory 217740 kb
Host smart-034283fd-e61b-4fd3-904b-3eba51c4e5c5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1589152846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1589152846
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2619388681
Short name T819
Test name
Test status
Simulation time 239607946 ps
CPU time 1.01 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:07 PM PDT 24
Peak memory 207512 kb
Host smart-cedee740-f3e9-4f89-9675-0fa2138b8efc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2619388681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2619388681
Directory /workspace/3.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3438011415
Short name T3105
Test name
Test status
Simulation time 229344043 ps
CPU time 1.03 seconds
Started Aug 11 07:09:06 PM PDT 24
Finished Aug 11 07:09:07 PM PDT 24
Peak memory 207504 kb
Host smart-0863bd30-d815-4b49-ae1a-c2d9bf6deb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34380
11415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3438011415
Directory /workspace/3.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.4099981983
Short name T797
Test name
Test status
Simulation time 2649735259 ps
CPU time 21.39 seconds
Started Aug 11 07:09:07 PM PDT 24
Finished Aug 11 07:09:28 PM PDT 24
Peak memory 217136 kb
Host smart-5ec8c9b0-3bd9-48ed-917b-e97fd00b509c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40999
81983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.4099981983
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.575346072
Short name T1743
Test name
Test status
Simulation time 1748653603 ps
CPU time 20.67 seconds
Started Aug 11 07:09:14 PM PDT 24
Finished Aug 11 07:09:35 PM PDT 24
Peak memory 218156 kb
Host smart-2072d4d3-411d-4080-be78-d668128c2139
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=575346072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.575346072
Directory /workspace/3.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.2192046523
Short name T1136
Test name
Test status
Simulation time 2671308761 ps
CPU time 26.56 seconds
Started Aug 11 07:09:12 PM PDT 24
Finished Aug 11 07:09:39 PM PDT 24
Peak memory 217668 kb
Host smart-d0b4de62-5c57-41b8-ac8c-fcf0602a358b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2192046523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.2192046523
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2856626840
Short name T3224
Test name
Test status
Simulation time 179083706 ps
CPU time 0.89 seconds
Started Aug 11 07:09:14 PM PDT 24
Finished Aug 11 07:09:15 PM PDT 24
Peak memory 207548 kb
Host smart-b8699309-5c97-496d-a4e4-22105a68b76c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2856626840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2856626840
Directory /workspace/3.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1858512342
Short name T3425
Test name
Test status
Simulation time 149468692 ps
CPU time 0.85 seconds
Started Aug 11 07:09:10 PM PDT 24
Finished Aug 11 07:09:11 PM PDT 24
Peak memory 207564 kb
Host smart-c773568c-bfb3-461b-ab63-12ef08921741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18585
12342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1858512342
Directory /workspace/3.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_nak_trans.3199021228
Short name T133
Test name
Test status
Simulation time 271504840 ps
CPU time 1.14 seconds
Started Aug 11 07:09:12 PM PDT 24
Finished Aug 11 07:09:13 PM PDT 24
Peak memory 207520 kb
Host smart-7cab3b7d-a28f-4fc9-8920-8acb0c9eb286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31990
21228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3199021228
Directory /workspace/3.usbdev_nak_trans/latest


Test location /workspace/coverage/default/3.usbdev_out_iso.3096003431
Short name T1988
Test name
Test status
Simulation time 216738590 ps
CPU time 0.99 seconds
Started Aug 11 07:09:12 PM PDT 24
Finished Aug 11 07:09:13 PM PDT 24
Peak memory 207476 kb
Host smart-81498439-52b0-4fc7-9d76-1621a9130e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30960
03431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3096003431
Directory /workspace/3.usbdev_out_iso/latest


Test location /workspace/coverage/default/3.usbdev_out_stall.1047880879
Short name T3108
Test name
Test status
Simulation time 178425699 ps
CPU time 0.88 seconds
Started Aug 11 07:09:12 PM PDT 24
Finished Aug 11 07:09:13 PM PDT 24
Peak memory 207456 kb
Host smart-552feea3-4b21-4190-80e2-6a5dd35af421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10478
80879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1047880879
Directory /workspace/3.usbdev_out_stall/latest


Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2552039492
Short name T2729
Test name
Test status
Simulation time 180778897 ps
CPU time 0.91 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:12 PM PDT 24
Peak memory 207544 kb
Host smart-5819d878-098d-427e-8cb3-5daf72ee81c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
39492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2552039492
Directory /workspace/3.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1928636273
Short name T1154
Test name
Test status
Simulation time 163911352 ps
CPU time 0.83 seconds
Started Aug 11 07:09:10 PM PDT 24
Finished Aug 11 07:09:11 PM PDT 24
Peak memory 207500 kb
Host smart-60b5ea18-1943-4348-90b1-4312b976ccc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19286
36273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1928636273
Directory /workspace/3.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.768249127
Short name T1722
Test name
Test status
Simulation time 230752964 ps
CPU time 1.04 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:12 PM PDT 24
Peak memory 207484 kb
Host smart-68814915-cec7-4928-8d9a-3ffbf851e136
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=768249127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.768249127
Directory /workspace/3.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2091237840
Short name T657
Test name
Test status
Simulation time 216897076 ps
CPU time 1.04 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:12 PM PDT 24
Peak memory 207556 kb
Host smart-be4b93df-7948-4eae-915c-99fcff237ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20912
37840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2091237840
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.768491585
Short name T1974
Test name
Test status
Simulation time 155869989 ps
CPU time 0.87 seconds
Started Aug 11 07:09:14 PM PDT 24
Finished Aug 11 07:09:15 PM PDT 24
Peak memory 207488 kb
Host smart-a05d7852-b75e-4490-b960-557df669c627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76849
1585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.768491585
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.4290925240
Short name T1710
Test name
Test status
Simulation time 75719415 ps
CPU time 0.77 seconds
Started Aug 11 07:09:13 PM PDT 24
Finished Aug 11 07:09:14 PM PDT 24
Peak memory 207532 kb
Host smart-5b318504-d7e7-4914-a719-4f8376d7281d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42909
25240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.4290925240
Directory /workspace/3.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/3.usbdev_pkt_buffer.413885296
Short name T301
Test name
Test status
Simulation time 12600047780 ps
CPU time 31.2 seconds
Started Aug 11 07:09:13 PM PDT 24
Finished Aug 11 07:09:44 PM PDT 24
Peak memory 216008 kb
Host smart-448d696f-7c9b-4297-8ea8-7fb93f7d92a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41388
5296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.413885296
Directory /workspace/3.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/3.usbdev_pkt_received.2630739860
Short name T2324
Test name
Test status
Simulation time 181692865 ps
CPU time 0.94 seconds
Started Aug 11 07:09:13 PM PDT 24
Finished Aug 11 07:09:14 PM PDT 24
Peak memory 207708 kb
Host smart-1955d11a-9f81-488d-a69b-0d2a244206f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26307
39860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2630739860
Directory /workspace/3.usbdev_pkt_received/latest


Test location /workspace/coverage/default/3.usbdev_pkt_sent.1665972276
Short name T794
Test name
Test status
Simulation time 198570262 ps
CPU time 0.96 seconds
Started Aug 11 07:09:10 PM PDT 24
Finished Aug 11 07:09:11 PM PDT 24
Peak memory 207456 kb
Host smart-fb88f1f9-d9d7-451f-8b74-1faaf58bc320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16659
72276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1665972276
Directory /workspace/3.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.448212166
Short name T2078
Test name
Test status
Simulation time 5926388422 ps
CPU time 69.64 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:10:20 PM PDT 24
Peak memory 224240 kb
Host smart-46b38b57-3146-4ba9-9f02-5bb581157d7e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=448212166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.448212166
Directory /workspace/3.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/3.usbdev_rand_suspends.1221237505
Short name T624
Test name
Test status
Simulation time 6315599935 ps
CPU time 25.24 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:37 PM PDT 24
Peak memory 224268 kb
Host smart-c53edbc4-c9e8-4c86-8578-8d7b9b75e3a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221237505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.1221237505
Directory /workspace/3.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3846460291
Short name T2866
Test name
Test status
Simulation time 240211651 ps
CPU time 1.03 seconds
Started Aug 11 07:09:13 PM PDT 24
Finished Aug 11 07:09:14 PM PDT 24
Peak memory 207480 kb
Host smart-f8938f49-235d-4137-9f15-08b423153489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38464
60291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3846460291
Directory /workspace/3.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1920889918
Short name T570
Test name
Test status
Simulation time 203149296 ps
CPU time 0.94 seconds
Started Aug 11 07:09:10 PM PDT 24
Finished Aug 11 07:09:12 PM PDT 24
Peak memory 207584 kb
Host smart-fd2fc7c2-6b67-4da2-a8ec-246f05f3e13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19208
89918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1920889918
Directory /workspace/3.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_resume_link_active.181523651
Short name T3153
Test name
Test status
Simulation time 20232882066 ps
CPU time 24.11 seconds
Started Aug 11 07:09:14 PM PDT 24
Finished Aug 11 07:09:38 PM PDT 24
Peak memory 207656 kb
Host smart-5d2293eb-7404-4459-b9fb-3be939f83deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18152
3651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.181523651
Directory /workspace/3.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/3.usbdev_rx_crc_err.666900372
Short name T2593
Test name
Test status
Simulation time 194850426 ps
CPU time 0.91 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:12 PM PDT 24
Peak memory 207524 kb
Host smart-84f4c3e0-03be-4eaa-ba29-6631e1d579e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66690
0372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.666900372
Directory /workspace/3.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/3.usbdev_rx_full.1003296172
Short name T345
Test name
Test status
Simulation time 355573526 ps
CPU time 1.27 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:13 PM PDT 24
Peak memory 207500 kb
Host smart-93a3e4a8-f9c7-455e-aee1-0a1176ee3b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10032
96172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.1003296172
Directory /workspace/3.usbdev_rx_full/latest


Test location /workspace/coverage/default/3.usbdev_rx_pid_err.273603981
Short name T83
Test name
Test status
Simulation time 155510091 ps
CPU time 0.87 seconds
Started Aug 11 07:09:15 PM PDT 24
Finished Aug 11 07:09:16 PM PDT 24
Peak memory 207524 kb
Host smart-323e9dbe-b8b9-4a1b-add1-e966e894e849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27360
3981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.273603981
Directory /workspace/3.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/3.usbdev_sec_cm.1509113915
Short name T241
Test name
Test status
Simulation time 432940897 ps
CPU time 1.29 seconds
Started Aug 11 07:09:12 PM PDT 24
Finished Aug 11 07:09:13 PM PDT 24
Peak memory 223456 kb
Host smart-c65670f7-4ac2-478d-adc6-12fce964437c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1509113915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1509113915
Directory /workspace/3.usbdev_sec_cm/latest


Test location /workspace/coverage/default/3.usbdev_setup_priority.459590192
Short name T2183
Test name
Test status
Simulation time 406733887 ps
CPU time 1.46 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:09:17 PM PDT 24
Peak memory 207524 kb
Host smart-4dbfb728-fc4b-45b9-bf78-09f83310702c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45959
0192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.459590192
Directory /workspace/3.usbdev_setup_priority/latest


Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2883306424
Short name T203
Test name
Test status
Simulation time 187604847 ps
CPU time 0.92 seconds
Started Aug 11 07:09:13 PM PDT 24
Finished Aug 11 07:09:14 PM PDT 24
Peak memory 207756 kb
Host smart-e7532465-482f-44e3-bf87-7448ab26bac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28833
06424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2883306424
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/3.usbdev_setup_stage.1371791377
Short name T3135
Test name
Test status
Simulation time 155606940 ps
CPU time 0.84 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:12 PM PDT 24
Peak memory 207540 kb
Host smart-93c352bc-7629-40b5-a174-f3b07a6b47ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717
91377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1371791377
Directory /workspace/3.usbdev_setup_stage/latest


Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2155468927
Short name T1466
Test name
Test status
Simulation time 150678754 ps
CPU time 0.87 seconds
Started Aug 11 07:09:14 PM PDT 24
Finished Aug 11 07:09:14 PM PDT 24
Peak memory 207556 kb
Host smart-480612a0-9d06-47fc-a479-0f970f4251a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21554
68927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2155468927
Directory /workspace/3.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/3.usbdev_smoke.2179093961
Short name T1006
Test name
Test status
Simulation time 232766273 ps
CPU time 1 seconds
Started Aug 11 07:09:15 PM PDT 24
Finished Aug 11 07:09:16 PM PDT 24
Peak memory 207480 kb
Host smart-ec92b092-d2b3-4a75-b85d-1963abb0f306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21790
93961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2179093961
Directory /workspace/3.usbdev_smoke/latest


Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2168382740
Short name T5
Test name
Test status
Simulation time 3144555227 ps
CPU time 90.66 seconds
Started Aug 11 07:09:10 PM PDT 24
Finished Aug 11 07:10:41 PM PDT 24
Peak memory 216120 kb
Host smart-d7f7d4a1-138e-4386-8165-d6d7fa8ca853
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2168382740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2168382740
Directory /workspace/3.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.106543655
Short name T1301
Test name
Test status
Simulation time 193106846 ps
CPU time 0.95 seconds
Started Aug 11 07:09:13 PM PDT 24
Finished Aug 11 07:09:14 PM PDT 24
Peak memory 207480 kb
Host smart-3427d346-f32f-4214-94e2-2142a7d71bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10654
3655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.106543655
Directory /workspace/3.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/3.usbdev_stall_trans.3174459401
Short name T3125
Test name
Test status
Simulation time 183032770 ps
CPU time 0.87 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:12 PM PDT 24
Peak memory 207568 kb
Host smart-cd839b0c-0450-4de2-b6e7-d18967dc1fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31744
59401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3174459401
Directory /workspace/3.usbdev_stall_trans/latest


Test location /workspace/coverage/default/3.usbdev_stream_len_max.1688439899
Short name T1726
Test name
Test status
Simulation time 1158085168 ps
CPU time 2.73 seconds
Started Aug 11 07:09:12 PM PDT 24
Finished Aug 11 07:09:15 PM PDT 24
Peak memory 207640 kb
Host smart-a2093c73-e6e5-4a86-896e-3c42a340ceb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16884
39899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1688439899
Directory /workspace/3.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/3.usbdev_streaming_out.41861926
Short name T2475
Test name
Test status
Simulation time 1973806132 ps
CPU time 20.01 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:31 PM PDT 24
Peak memory 224128 kb
Host smart-f43b02c0-8060-4d84-a403-7e4a58d8f0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41861
926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.41861926
Directory /workspace/3.usbdev_streaming_out/latest


Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1012608978
Short name T2582
Test name
Test status
Simulation time 8031130112 ps
CPU time 56.93 seconds
Started Aug 11 07:09:15 PM PDT 24
Finished Aug 11 07:10:12 PM PDT 24
Peak memory 218236 kb
Host smart-3f9d2064-a0d0-4376-aed3-c037b77aa083
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012608978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1012608978
Directory /workspace/3.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.2737239649
Short name T2075
Test name
Test status
Simulation time 777650050 ps
CPU time 15.76 seconds
Started Aug 11 07:09:03 PM PDT 24
Finished Aug 11 07:09:19 PM PDT 24
Peak memory 207768 kb
Host smart-3f4763a2-6912-42ef-a12b-dc57c171a37d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737239649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.2737239649
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/3.usbdev_tx_rx_disruption.2296525734
Short name T855
Test name
Test status
Simulation time 491715929 ps
CPU time 1.6 seconds
Started Aug 11 07:09:11 PM PDT 24
Finished Aug 11 07:09:13 PM PDT 24
Peak memory 207552 kb
Host smart-f9d5011a-d52b-435b-97d6-11d7085fdc66
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296525734 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.usbdev_tx_rx_disruption.2296525734
Directory /workspace/3.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/30.usbdev_alert_test.1236105400
Short name T3013
Test name
Test status
Simulation time 51322544 ps
CPU time 0.69 seconds
Started Aug 11 07:13:57 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207536 kb
Host smart-c915929b-9883-4ff9-89bd-559140b5e36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1236105400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.1236105400
Directory /workspace/30.usbdev_alert_test/latest


Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3327828469
Short name T3382
Test name
Test status
Simulation time 4456793880 ps
CPU time 6.76 seconds
Started Aug 11 07:13:46 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 216012 kb
Host smart-a9f98f71-4fe7-4cfa-985f-16a42386e35f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327828469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.3327828469
Directory /workspace/30.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1524016539
Short name T2241
Test name
Test status
Simulation time 19860532152 ps
CPU time 25.37 seconds
Started Aug 11 07:13:54 PM PDT 24
Finished Aug 11 07:14:19 PM PDT 24
Peak memory 207836 kb
Host smart-50e24acf-eef0-4c88-a104-8c411146563a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524016539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1524016539
Directory /workspace/30.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2188811334
Short name T1631
Test name
Test status
Simulation time 25702508525 ps
CPU time 30.41 seconds
Started Aug 11 07:13:49 PM PDT 24
Finished Aug 11 07:14:20 PM PDT 24
Peak memory 215896 kb
Host smart-b142bc18-3a20-4281-b997-ef915503c614
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188811334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.2188811334
Directory /workspace/30.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/30.usbdev_av_buffer.1622932155
Short name T768
Test name
Test status
Simulation time 185086060 ps
CPU time 0.86 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 207568 kb
Host smart-b6741182-fcd8-4173-862f-92fce13750f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16229
32155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1622932155
Directory /workspace/30.usbdev_av_buffer/latest


Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1274226320
Short name T1171
Test name
Test status
Simulation time 186880147 ps
CPU time 0.92 seconds
Started Aug 11 07:13:55 PM PDT 24
Finished Aug 11 07:13:56 PM PDT 24
Peak memory 207488 kb
Host smart-6dadcaa3-7f0f-46ce-9ff3-8c17e10d95e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12742
26320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1274226320
Directory /workspace/30.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.2164966240
Short name T863
Test name
Test status
Simulation time 466140121 ps
CPU time 1.62 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:05 PM PDT 24
Peak memory 207552 kb
Host smart-907fcd0f-7ad9-46e5-9138-2eff1b47f039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21649
66240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.2164966240
Directory /workspace/30.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.4051595499
Short name T3084
Test name
Test status
Simulation time 1068274918 ps
CPU time 2.89 seconds
Started Aug 11 07:13:59 PM PDT 24
Finished Aug 11 07:14:02 PM PDT 24
Peak memory 207696 kb
Host smart-27f3af26-73ec-4aa0-b111-76e5c192e457
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4051595499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.4051595499
Directory /workspace/30.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/30.usbdev_device_address.600767268
Short name T1234
Test name
Test status
Simulation time 41509926981 ps
CPU time 62.41 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:14:54 PM PDT 24
Peak memory 207772 kb
Host smart-5c3573f9-286b-44ba-b396-766361b1d662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60076
7268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.600767268
Directory /workspace/30.usbdev_device_address/latest


Test location /workspace/coverage/default/30.usbdev_device_timeout.879502569
Short name T1389
Test name
Test status
Simulation time 1058976647 ps
CPU time 9.02 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 207748 kb
Host smart-d9506a58-8e4e-409f-bfb6-2627c33e77db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879502569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.879502569
Directory /workspace/30.usbdev_device_timeout/latest


Test location /workspace/coverage/default/30.usbdev_disable_endpoint.4212234693
Short name T2709
Test name
Test status
Simulation time 678556396 ps
CPU time 1.65 seconds
Started Aug 11 07:13:50 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207540 kb
Host smart-7cb2adf7-a044-4236-bfee-2d3a16da2f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42122
34693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.4212234693
Directory /workspace/30.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/30.usbdev_disconnected.1950598125
Short name T1527
Test name
Test status
Simulation time 139817328 ps
CPU time 0.82 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 207476 kb
Host smart-a390096c-31e5-485f-b385-16dd2575d223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19505
98125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1950598125
Directory /workspace/30.usbdev_disconnected/latest


Test location /workspace/coverage/default/30.usbdev_enable.433630138
Short name T2506
Test name
Test status
Simulation time 32951874 ps
CPU time 0.7 seconds
Started Aug 11 07:13:49 PM PDT 24
Finished Aug 11 07:13:50 PM PDT 24
Peak memory 207544 kb
Host smart-ad593ed4-06bb-4b15-8019-40020da5ce1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43363
0138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.433630138
Directory /workspace/30.usbdev_enable/latest


Test location /workspace/coverage/default/30.usbdev_endpoint_access.3394991287
Short name T2513
Test name
Test status
Simulation time 976626560 ps
CPU time 2.52 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 207748 kb
Host smart-28851e75-838a-4755-8488-ec78203c22cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33949
91287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3394991287
Directory /workspace/30.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/30.usbdev_fifo_rst.2911079929
Short name T2060
Test name
Test status
Simulation time 219520584 ps
CPU time 1.37 seconds
Started Aug 11 07:14:05 PM PDT 24
Finished Aug 11 07:14:06 PM PDT 24
Peak memory 207716 kb
Host smart-4eda915a-489d-4dff-852b-360167d45ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29110
79929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2911079929
Directory /workspace/30.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/30.usbdev_in_iso.2933514937
Short name T1562
Test name
Test status
Simulation time 210725918 ps
CPU time 1.13 seconds
Started Aug 11 07:14:04 PM PDT 24
Finished Aug 11 07:14:05 PM PDT 24
Peak memory 215940 kb
Host smart-a9a8b126-6336-48ca-828b-4e39cd337bd3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2933514937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2933514937
Directory /workspace/30.usbdev_in_iso/latest


Test location /workspace/coverage/default/30.usbdev_in_stall.1703748561
Short name T3189
Test name
Test status
Simulation time 148957145 ps
CPU time 0.81 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 207532 kb
Host smart-f45d6bae-8e1e-458d-bfa8-3b54ea4014d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17037
48561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1703748561
Directory /workspace/30.usbdev_in_stall/latest


Test location /workspace/coverage/default/30.usbdev_in_trans.653715001
Short name T1115
Test name
Test status
Simulation time 164630030 ps
CPU time 0.88 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207504 kb
Host smart-64183512-8314-4e17-837f-4366a81d6c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65371
5001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.653715001
Directory /workspace/30.usbdev_in_trans/latest


Test location /workspace/coverage/default/30.usbdev_invalid_sync.3597089339
Short name T1071
Test name
Test status
Simulation time 4591254904 ps
CPU time 46.92 seconds
Started Aug 11 07:13:49 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 224212 kb
Host smart-1da36a2b-c5d3-4fb9-9acf-1f2f6ab12c56
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3597089339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.3597089339
Directory /workspace/30.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/30.usbdev_iso_retraction.1102145127
Short name T3190
Test name
Test status
Simulation time 7581295454 ps
CPU time 49.42 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:14:40 PM PDT 24
Peak memory 207828 kb
Host smart-111e32a3-58e1-49be-bb0f-e1a74d749b1b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1102145127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1102145127
Directory /workspace/30.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/30.usbdev_link_in_err.745047266
Short name T1563
Test name
Test status
Simulation time 237560268 ps
CPU time 0.98 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207552 kb
Host smart-eed26024-7f23-43f3-a527-b69efeb18c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74504
7266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.745047266
Directory /workspace/30.usbdev_link_in_err/latest


Test location /workspace/coverage/default/30.usbdev_link_resume.2717133380
Short name T2007
Test name
Test status
Simulation time 6727090239 ps
CPU time 10.31 seconds
Started Aug 11 07:13:47 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207808 kb
Host smart-103a00d1-e490-42ea-a127-4ebdac63a1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27171
33380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2717133380
Directory /workspace/30.usbdev_link_resume/latest


Test location /workspace/coverage/default/30.usbdev_link_suspend.3288774036
Short name T124
Test name
Test status
Simulation time 4184005301 ps
CPU time 6.05 seconds
Started Aug 11 07:14:05 PM PDT 24
Finished Aug 11 07:14:11 PM PDT 24
Peak memory 207832 kb
Host smart-55531469-9dc5-4f81-8337-8f93a7ef513f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32887
74036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3288774036
Directory /workspace/30.usbdev_link_suspend/latest


Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2965706184
Short name T417
Test name
Test status
Simulation time 4162416540 ps
CPU time 118.42 seconds
Started Aug 11 07:14:00 PM PDT 24
Finished Aug 11 07:15:59 PM PDT 24
Peak memory 218872 kb
Host smart-d9a7368c-70b7-4d56-b394-2284c8aa2594
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2965706184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2965706184
Directory /workspace/30.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1210888171
Short name T2089
Test name
Test status
Simulation time 2435218270 ps
CPU time 19.46 seconds
Started Aug 11 07:13:49 PM PDT 24
Finished Aug 11 07:14:09 PM PDT 24
Peak memory 217852 kb
Host smart-a8f212ba-9cff-4003-aed4-b4a33bd4f4ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1210888171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1210888171
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2609475934
Short name T774
Test name
Test status
Simulation time 242445487 ps
CPU time 1.02 seconds
Started Aug 11 07:13:49 PM PDT 24
Finished Aug 11 07:13:50 PM PDT 24
Peak memory 207588 kb
Host smart-001d4b0c-0123-44a4-98be-94eda7b6f4af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2609475934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2609475934
Directory /workspace/30.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.368405276
Short name T882
Test name
Test status
Simulation time 231851801 ps
CPU time 0.99 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207568 kb
Host smart-33d868af-3a0e-49cc-b9c8-e84f6f5d7609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36840
5276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.368405276
Directory /workspace/30.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2777080117
Short name T3611
Test name
Test status
Simulation time 3043410709 ps
CPU time 87.31 seconds
Started Aug 11 07:13:54 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 216084 kb
Host smart-adaf00b6-b76d-4f6f-af9f-fb8e68c80dc1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2777080117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2777080117
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3425047020
Short name T3167
Test name
Test status
Simulation time 168603279 ps
CPU time 0.86 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207572 kb
Host smart-577f4ad0-f81e-4962-ad6f-d6237251a121
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3425047020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3425047020
Directory /workspace/30.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.4190811304
Short name T3229
Test name
Test status
Simulation time 144726565 ps
CPU time 0.85 seconds
Started Aug 11 07:13:47 PM PDT 24
Finished Aug 11 07:13:48 PM PDT 24
Peak memory 207480 kb
Host smart-c4583080-2f54-4254-b269-00b2f9c90adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41908
11304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.4190811304
Directory /workspace/30.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_nak_trans.3704157852
Short name T2366
Test name
Test status
Simulation time 199917062 ps
CPU time 0.93 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:14:08 PM PDT 24
Peak memory 207572 kb
Host smart-b8cedd81-7f24-4437-a8b0-f93d000b6a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37041
57852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3704157852
Directory /workspace/30.usbdev_nak_trans/latest


Test location /workspace/coverage/default/30.usbdev_out_iso.1505089925
Short name T3587
Test name
Test status
Simulation time 181836307 ps
CPU time 0.91 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207520 kb
Host smart-0a4ef1b4-e07a-49e3-acc8-d8bd28d3c25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15050
89925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1505089925
Directory /workspace/30.usbdev_out_iso/latest


Test location /workspace/coverage/default/30.usbdev_out_stall.851186273
Short name T1336
Test name
Test status
Simulation time 197971887 ps
CPU time 0.87 seconds
Started Aug 11 07:13:48 PM PDT 24
Finished Aug 11 07:13:49 PM PDT 24
Peak memory 207576 kb
Host smart-f35cb176-562c-4ac1-b36d-3c9432e15ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85118
6273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.851186273
Directory /workspace/30.usbdev_out_stall/latest


Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1646306166
Short name T1704
Test name
Test status
Simulation time 178265650 ps
CPU time 0.92 seconds
Started Aug 11 07:13:56 PM PDT 24
Finished Aug 11 07:13:57 PM PDT 24
Peak memory 207520 kb
Host smart-bd1c3cba-e421-4547-8ee2-0ca6cb5d2ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16463
06166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1646306166
Directory /workspace/30.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3284328695
Short name T2910
Test name
Test status
Simulation time 193164101 ps
CPU time 0.91 seconds
Started Aug 11 07:13:53 PM PDT 24
Finished Aug 11 07:13:54 PM PDT 24
Peak memory 207524 kb
Host smart-2a9aabb4-6000-41e7-8344-bf732eeab07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32843
28695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3284328695
Directory /workspace/30.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.87605424
Short name T1511
Test name
Test status
Simulation time 241933671 ps
CPU time 1.01 seconds
Started Aug 11 07:13:57 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207588 kb
Host smart-5a433327-b940-4850-817a-06c12b3fac46
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=87605424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.87605424
Directory /workspace/30.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1868019635
Short name T1091
Test name
Test status
Simulation time 157435132 ps
CPU time 0.78 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:13:51 PM PDT 24
Peak memory 207520 kb
Host smart-cfb175d4-276b-49b3-a335-e56c4f4b8a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18680
19635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1868019635
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2347669752
Short name T1245
Test name
Test status
Simulation time 34839197 ps
CPU time 0.68 seconds
Started Aug 11 07:13:57 PM PDT 24
Finished Aug 11 07:13:57 PM PDT 24
Peak memory 206528 kb
Host smart-22cf789b-774e-4d61-b629-5a753a4fcb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23476
69752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2347669752
Directory /workspace/30.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/30.usbdev_pkt_received.1847826732
Short name T2233
Test name
Test status
Simulation time 152719008 ps
CPU time 0.86 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207480 kb
Host smart-2663f256-e736-4e4d-a7a2-27bfa6c636c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
26732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1847826732
Directory /workspace/30.usbdev_pkt_received/latest


Test location /workspace/coverage/default/30.usbdev_pkt_sent.296045497
Short name T3089
Test name
Test status
Simulation time 175329231 ps
CPU time 0.9 seconds
Started Aug 11 07:13:56 PM PDT 24
Finished Aug 11 07:13:57 PM PDT 24
Peak memory 207528 kb
Host smart-33cef6ca-84e9-474e-83a0-30cebc06bd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29604
5497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.296045497
Directory /workspace/30.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.4098188231
Short name T1471
Test name
Test status
Simulation time 178513128 ps
CPU time 0.88 seconds
Started Aug 11 07:14:06 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 207572 kb
Host smart-b4d8e6e8-701a-4509-9fa0-9a62ae168ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40981
88231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.4098188231
Directory /workspace/30.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.3786317190
Short name T1360
Test name
Test status
Simulation time 191243369 ps
CPU time 0.93 seconds
Started Aug 11 07:13:50 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207528 kb
Host smart-25f949db-0cb3-46c1-962f-57559ea7b1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37863
17190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.3786317190
Directory /workspace/30.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3110662182
Short name T3622
Test name
Test status
Simulation time 205490844 ps
CPU time 0.92 seconds
Started Aug 11 07:13:48 PM PDT 24
Finished Aug 11 07:13:49 PM PDT 24
Peak memory 207512 kb
Host smart-91c4d1a0-676c-4222-a988-fba05d6818b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31106
62182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3110662182
Directory /workspace/30.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/30.usbdev_rx_full.4060020758
Short name T2177
Test name
Test status
Simulation time 302429054 ps
CPU time 1.11 seconds
Started Aug 11 07:13:48 PM PDT 24
Finished Aug 11 07:13:49 PM PDT 24
Peak memory 207492 kb
Host smart-51d5337a-b80f-4620-a1df-815042d1fd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40600
20758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.4060020758
Directory /workspace/30.usbdev_rx_full/latest


Test location /workspace/coverage/default/30.usbdev_setup_stage.3076127424
Short name T2691
Test name
Test status
Simulation time 152408371 ps
CPU time 0.86 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207536 kb
Host smart-4a46bed8-ddee-412d-b58c-bc5dd9921865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30761
27424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3076127424
Directory /workspace/30.usbdev_setup_stage/latest


Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3575159483
Short name T1664
Test name
Test status
Simulation time 149937944 ps
CPU time 0.86 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207520 kb
Host smart-9817af44-9591-4bfb-905e-7e13570c8314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35751
59483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3575159483
Directory /workspace/30.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/30.usbdev_smoke.4204818273
Short name T607
Test name
Test status
Simulation time 240023819 ps
CPU time 1.1 seconds
Started Aug 11 07:13:54 PM PDT 24
Finished Aug 11 07:13:55 PM PDT 24
Peak memory 207556 kb
Host smart-3625da79-b01b-4bec-b83e-64f027dcac87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42048
18273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.4204818273
Directory /workspace/30.usbdev_smoke/latest


Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1366174512
Short name T1467
Test name
Test status
Simulation time 2523250415 ps
CPU time 74.89 seconds
Started Aug 11 07:13:48 PM PDT 24
Finished Aug 11 07:15:03 PM PDT 24
Peak memory 224192 kb
Host smart-10c4acdc-b92d-425a-880b-5f7d85c76e56
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1366174512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1366174512
Directory /workspace/30.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2686276385
Short name T1725
Test name
Test status
Simulation time 179314662 ps
CPU time 0.89 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207568 kb
Host smart-4bb54094-5879-4a8c-a09f-23996c81e61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26862
76385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2686276385
Directory /workspace/30.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/30.usbdev_stall_trans.2965931191
Short name T3199
Test name
Test status
Simulation time 178331200 ps
CPU time 0.93 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207568 kb
Host smart-2eb27d70-c763-464d-ab57-70bf4c4c1544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29659
31191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2965931191
Directory /workspace/30.usbdev_stall_trans/latest


Test location /workspace/coverage/default/30.usbdev_stream_len_max.3334038256
Short name T1537
Test name
Test status
Simulation time 1099217571 ps
CPU time 2.41 seconds
Started Aug 11 07:13:54 PM PDT 24
Finished Aug 11 07:13:57 PM PDT 24
Peak memory 207764 kb
Host smart-edf2ecef-1b1f-44d7-9bae-da2716d8d49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
38256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3334038256
Directory /workspace/30.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/30.usbdev_streaming_out.3051378715
Short name T996
Test name
Test status
Simulation time 2673298652 ps
CPU time 19.83 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207876 kb
Host smart-901b46a7-9c3d-4ecc-83b3-6fe28e098bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30513
78715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3051378715
Directory /workspace/30.usbdev_streaming_out/latest


Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.2888809069
Short name T3002
Test name
Test status
Simulation time 603730493 ps
CPU time 4.99 seconds
Started Aug 11 07:13:55 PM PDT 24
Finished Aug 11 07:14:00 PM PDT 24
Peak memory 207620 kb
Host smart-1a6c3b69-db3f-47fe-a746-e500ce4a8afc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888809069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.2888809069
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/30.usbdev_tx_rx_disruption.4131980461
Short name T1712
Test name
Test status
Simulation time 449683397 ps
CPU time 1.43 seconds
Started Aug 11 07:14:02 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207564 kb
Host smart-6c28faae-af5a-42e9-8bd2-9da6e73a7653
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131980461 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.usbdev_tx_rx_disruption.4131980461
Directory /workspace/30.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/300.usbdev_tx_rx_disruption.647646436
Short name T1678
Test name
Test status
Simulation time 504676415 ps
CPU time 1.51 seconds
Started Aug 11 07:17:32 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207476 kb
Host smart-ee191591-44d5-41ae-b0db-7409e9079112
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647646436 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 300.usbdev_tx_rx_disruption.647646436
Directory /workspace/300.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/301.usbdev_tx_rx_disruption.599919869
Short name T1573
Test name
Test status
Simulation time 559829562 ps
CPU time 1.52 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:41 PM PDT 24
Peak memory 207556 kb
Host smart-fe79f0c8-818a-40c7-90a9-b1d6de078e6f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599919869 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 301.usbdev_tx_rx_disruption.599919869
Directory /workspace/301.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/302.usbdev_tx_rx_disruption.2354426797
Short name T2963
Test name
Test status
Simulation time 476175587 ps
CPU time 1.53 seconds
Started Aug 11 07:17:48 PM PDT 24
Finished Aug 11 07:17:49 PM PDT 24
Peak memory 207492 kb
Host smart-d5b50afd-956c-4d6a-bd2d-f0a16fde87c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354426797 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 302.usbdev_tx_rx_disruption.2354426797
Directory /workspace/302.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/303.usbdev_tx_rx_disruption.905639817
Short name T166
Test name
Test status
Simulation time 590918117 ps
CPU time 1.59 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:40 PM PDT 24
Peak memory 207520 kb
Host smart-0e573061-5a13-4f66-94dc-87d8973d6087
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905639817 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 303.usbdev_tx_rx_disruption.905639817
Directory /workspace/303.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/304.usbdev_tx_rx_disruption.749505609
Short name T2374
Test name
Test status
Simulation time 444698728 ps
CPU time 1.39 seconds
Started Aug 11 07:17:56 PM PDT 24
Finished Aug 11 07:17:58 PM PDT 24
Peak memory 207512 kb
Host smart-a997f19e-95bd-496a-ad9b-dee10d7a0413
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749505609 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 304.usbdev_tx_rx_disruption.749505609
Directory /workspace/304.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/305.usbdev_tx_rx_disruption.2859409122
Short name T2449
Test name
Test status
Simulation time 632375049 ps
CPU time 1.66 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207572 kb
Host smart-846cb18c-b083-4a7e-9409-14982dbed942
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859409122 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 305.usbdev_tx_rx_disruption.2859409122
Directory /workspace/305.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/306.usbdev_tx_rx_disruption.179186106
Short name T1231
Test name
Test status
Simulation time 444098896 ps
CPU time 1.36 seconds
Started Aug 11 07:17:44 PM PDT 24
Finished Aug 11 07:17:46 PM PDT 24
Peak memory 207468 kb
Host smart-57788f47-df7e-4da9-ac62-05f52539a16c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179186106 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 306.usbdev_tx_rx_disruption.179186106
Directory /workspace/306.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/307.usbdev_tx_rx_disruption.3902778556
Short name T1131
Test name
Test status
Simulation time 617977486 ps
CPU time 1.66 seconds
Started Aug 11 07:17:41 PM PDT 24
Finished Aug 11 07:17:43 PM PDT 24
Peak memory 207520 kb
Host smart-847ca16a-6a5f-4165-ac09-f6201dd65ba3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902778556 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 307.usbdev_tx_rx_disruption.3902778556
Directory /workspace/307.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/308.usbdev_tx_rx_disruption.1730032498
Short name T2969
Test name
Test status
Simulation time 532012860 ps
CPU time 1.61 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207464 kb
Host smart-da4ebeea-69ae-48a9-9228-3e0eee2560f6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730032498 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 308.usbdev_tx_rx_disruption.1730032498
Directory /workspace/308.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/309.usbdev_tx_rx_disruption.606206368
Short name T2853
Test name
Test status
Simulation time 648819896 ps
CPU time 1.68 seconds
Started Aug 11 07:17:41 PM PDT 24
Finished Aug 11 07:17:43 PM PDT 24
Peak memory 207548 kb
Host smart-b4251575-6714-42d2-be8f-6149851f56a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606206368 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 309.usbdev_tx_rx_disruption.606206368
Directory /workspace/309.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/31.usbdev_alert_test.3477152731
Short name T2545
Test name
Test status
Simulation time 70721955 ps
CPU time 0.72 seconds
Started Aug 11 07:13:56 PM PDT 24
Finished Aug 11 07:13:57 PM PDT 24
Peak memory 207620 kb
Host smart-ca620850-b727-45af-b141-77b25591ec09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3477152731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3477152731
Directory /workspace/31.usbdev_alert_test/latest


Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2473261244
Short name T1977
Test name
Test status
Simulation time 12309275510 ps
CPU time 15.68 seconds
Started Aug 11 07:13:57 PM PDT 24
Finished Aug 11 07:14:13 PM PDT 24
Peak memory 207820 kb
Host smart-5783c9bc-37aa-4410-b4ce-818981d1398c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473261244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.2473261244
Directory /workspace/31.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3954329573
Short name T1095
Test name
Test status
Simulation time 19408881369 ps
CPU time 23.5 seconds
Started Aug 11 07:14:08 PM PDT 24
Finished Aug 11 07:14:31 PM PDT 24
Peak memory 207868 kb
Host smart-e1f4189d-61bb-40a9-8dda-250a93e5e8ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954329573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3954329573
Directory /workspace/31.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.1595217799
Short name T16
Test name
Test status
Simulation time 23387839094 ps
CPU time 27.67 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:14:18 PM PDT 24
Peak memory 215020 kb
Host smart-3c757f1d-4de3-49d4-95b4-12852fd898c3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595217799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.1595217799
Directory /workspace/31.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/31.usbdev_av_buffer.1410752672
Short name T1168
Test name
Test status
Simulation time 166621108 ps
CPU time 0.95 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:14:08 PM PDT 24
Peak memory 207572 kb
Host smart-3df4c97b-2517-40d7-a5e1-31fb0ad5880a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14107
52672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1410752672
Directory /workspace/31.usbdev_av_buffer/latest


Test location /workspace/coverage/default/31.usbdev_bitstuff_err.190336745
Short name T739
Test name
Test status
Simulation time 143643572 ps
CPU time 0.9 seconds
Started Aug 11 07:14:06 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 207520 kb
Host smart-0339bcf5-0ebc-4af4-bfdd-db0c1fde947b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19033
6745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.190336745
Directory /workspace/31.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1265013344
Short name T2094
Test name
Test status
Simulation time 159879530 ps
CPU time 0.88 seconds
Started Aug 11 07:13:57 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207520 kb
Host smart-24760bbd-4334-4f3d-9063-62cb565c88ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12650
13344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1265013344
Directory /workspace/31.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2170552348
Short name T1887
Test name
Test status
Simulation time 339124566 ps
CPU time 1.16 seconds
Started Aug 11 07:13:50 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207484 kb
Host smart-f7306ca8-f235-4884-9c23-8180d865ffac
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2170552348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2170552348
Directory /workspace/31.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/31.usbdev_device_address.1833341689
Short name T1525
Test name
Test status
Simulation time 27893699549 ps
CPU time 49.23 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:14:41 PM PDT 24
Peak memory 207184 kb
Host smart-323cfa4d-220b-4d56-8a58-b9477c7a4b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
41689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1833341689
Directory /workspace/31.usbdev_device_address/latest


Test location /workspace/coverage/default/31.usbdev_device_timeout.2001301270
Short name T1381
Test name
Test status
Simulation time 1056825192 ps
CPU time 8.6 seconds
Started Aug 11 07:14:16 PM PDT 24
Finished Aug 11 07:14:24 PM PDT 24
Peak memory 207704 kb
Host smart-87a7b6d8-8f59-45be-ab52-1e86d2be94cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001301270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.2001301270
Directory /workspace/31.usbdev_device_timeout/latest


Test location /workspace/coverage/default/31.usbdev_disable_endpoint.757638042
Short name T1865
Test name
Test status
Simulation time 709672070 ps
CPU time 1.84 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:13:54 PM PDT 24
Peak memory 207556 kb
Host smart-56d85d52-1194-4e86-99b4-b3d8409b778e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75763
8042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.757638042
Directory /workspace/31.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/31.usbdev_disconnected.576932504
Short name T2445
Test name
Test status
Simulation time 152364670 ps
CPU time 0.86 seconds
Started Aug 11 07:13:51 PM PDT 24
Finished Aug 11 07:13:52 PM PDT 24
Peak memory 207536 kb
Host smart-fe57a15c-4f1f-4f4f-ba76-771aecbd98f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57693
2504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.576932504
Directory /workspace/31.usbdev_disconnected/latest


Test location /workspace/coverage/default/31.usbdev_enable.958890474
Short name T756
Test name
Test status
Simulation time 62558647 ps
CPU time 0.76 seconds
Started Aug 11 07:13:50 PM PDT 24
Finished Aug 11 07:13:51 PM PDT 24
Peak memory 207536 kb
Host smart-986f27bd-2b6e-49b0-95d6-7726f6185335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95889
0474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.958890474
Directory /workspace/31.usbdev_enable/latest


Test location /workspace/coverage/default/31.usbdev_endpoint_access.3888626851
Short name T47
Test name
Test status
Simulation time 961254398 ps
CPU time 2.4 seconds
Started Aug 11 07:13:46 PM PDT 24
Finished Aug 11 07:13:48 PM PDT 24
Peak memory 207744 kb
Host smart-58764b9a-5988-4052-b30c-8c25b439b227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38886
26851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3888626851
Directory /workspace/31.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/31.usbdev_endpoint_types.2893903944
Short name T505
Test name
Test status
Simulation time 261716654 ps
CPU time 1.06 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207528 kb
Host smart-a75d23ad-77e7-4bc4-9e39-f0fb133f9337
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2893903944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.2893903944
Directory /workspace/31.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/31.usbdev_fifo_rst.3189141333
Short name T2160
Test name
Test status
Simulation time 191953093 ps
CPU time 2.39 seconds
Started Aug 11 07:14:04 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 207628 kb
Host smart-93326877-4103-431f-b819-c16397a9f666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31891
41333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3189141333
Directory /workspace/31.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/31.usbdev_in_iso.1915056686
Short name T2034
Test name
Test status
Simulation time 178592571 ps
CPU time 0.94 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207556 kb
Host smart-b7127a6d-1ce4-4b18-ad59-20b49e96726f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1915056686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1915056686
Directory /workspace/31.usbdev_in_iso/latest


Test location /workspace/coverage/default/31.usbdev_in_stall.1088181257
Short name T667
Test name
Test status
Simulation time 148392624 ps
CPU time 0.8 seconds
Started Aug 11 07:13:56 PM PDT 24
Finished Aug 11 07:13:57 PM PDT 24
Peak memory 207500 kb
Host smart-dbbdb20d-d796-4b40-9c0f-01aa9684cee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10881
81257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1088181257
Directory /workspace/31.usbdev_in_stall/latest


Test location /workspace/coverage/default/31.usbdev_in_trans.639177392
Short name T1796
Test name
Test status
Simulation time 238555228 ps
CPU time 0.99 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207568 kb
Host smart-77173e7e-14b8-4743-bf3d-52cfa74b1060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63917
7392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.639177392
Directory /workspace/31.usbdev_in_trans/latest


Test location /workspace/coverage/default/31.usbdev_invalid_sync.4279988663
Short name T1070
Test name
Test status
Simulation time 3884617834 ps
CPU time 29.04 seconds
Started Aug 11 07:13:55 PM PDT 24
Finished Aug 11 07:14:25 PM PDT 24
Peak memory 216056 kb
Host smart-cc9602db-2c04-4c5d-9455-87b30d01d8e0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4279988663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.4279988663
Directory /workspace/31.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/31.usbdev_iso_retraction.1335546479
Short name T1961
Test name
Test status
Simulation time 10413654134 ps
CPU time 126.35 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:15:58 PM PDT 24
Peak memory 207800 kb
Host smart-92828f2f-7f7a-47a2-9f76-1c196a19f3e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1335546479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.1335546479
Directory /workspace/31.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/31.usbdev_link_in_err.2741749155
Short name T2739
Test name
Test status
Simulation time 187125211 ps
CPU time 0.93 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 206880 kb
Host smart-2c8692ee-483e-45e1-b381-cb0ee48cd40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27417
49155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2741749155
Directory /workspace/31.usbdev_link_in_err/latest


Test location /workspace/coverage/default/31.usbdev_link_resume.2578565189
Short name T2553
Test name
Test status
Simulation time 33355073681 ps
CPU time 50.13 seconds
Started Aug 11 07:14:04 PM PDT 24
Finished Aug 11 07:14:54 PM PDT 24
Peak memory 207776 kb
Host smart-174c205c-5c4f-434a-b453-f00f20c2bc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25785
65189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.2578565189
Directory /workspace/31.usbdev_link_resume/latest


Test location /workspace/coverage/default/31.usbdev_link_suspend.3553739977
Short name T892
Test name
Test status
Simulation time 5382542078 ps
CPU time 6.98 seconds
Started Aug 11 07:14:00 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 216780 kb
Host smart-3a23342f-8d56-477d-8d4a-b4399c7408b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35537
39977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3553739977
Directory /workspace/31.usbdev_link_suspend/latest


Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1970925744
Short name T2356
Test name
Test status
Simulation time 3923546356 ps
CPU time 41.07 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 219076 kb
Host smart-5bc07b2b-2adc-4652-ae2a-ab01aa479b1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1970925744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1970925744
Directory /workspace/31.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2823604469
Short name T1365
Test name
Test status
Simulation time 3406814927 ps
CPU time 33.51 seconds
Started Aug 11 07:13:56 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 217852 kb
Host smart-b2e69544-8fa6-4ef2-ad92-7307a61c4745
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2823604469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2823604469
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.210234405
Short name T2310
Test name
Test status
Simulation time 248904866 ps
CPU time 0.96 seconds
Started Aug 11 07:13:48 PM PDT 24
Finished Aug 11 07:13:49 PM PDT 24
Peak memory 207512 kb
Host smart-c257a993-7766-4a3a-ad36-bbcbd84130f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=210234405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.210234405
Directory /workspace/31.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.669972610
Short name T3283
Test name
Test status
Simulation time 200234556 ps
CPU time 0.95 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207568 kb
Host smart-66b3a750-f73b-4419-92dd-63be3c8f2080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66997
2610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.669972610
Directory /workspace/31.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3408218727
Short name T2109
Test name
Test status
Simulation time 2663099364 ps
CPU time 25.32 seconds
Started Aug 11 07:14:02 PM PDT 24
Finished Aug 11 07:14:28 PM PDT 24
Peak memory 216968 kb
Host smart-87a5ff23-4469-4b2f-ac46-ff57fc0da020
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3408218727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3408218727
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1130565335
Short name T1093
Test name
Test status
Simulation time 208989523 ps
CPU time 1 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207568 kb
Host smart-95823336-84ba-44e4-b28d-faf6654a7483
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1130565335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1130565335
Directory /workspace/31.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1654067892
Short name T2399
Test name
Test status
Simulation time 166261364 ps
CPU time 0.83 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 206564 kb
Host smart-472e26e2-0029-4820-a19d-8304384041fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16540
67892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1654067892
Directory /workspace/31.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_nak_trans.3497302577
Short name T1822
Test name
Test status
Simulation time 204556394 ps
CPU time 0.95 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:14:08 PM PDT 24
Peak memory 206560 kb
Host smart-c81e2903-2c62-4250-a967-2bb8bb36f9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34973
02577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3497302577
Directory /workspace/31.usbdev_nak_trans/latest


Test location /workspace/coverage/default/31.usbdev_out_iso.3447816175
Short name T1029
Test name
Test status
Simulation time 186641291 ps
CPU time 0.97 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207564 kb
Host smart-0f04e692-8249-4175-90e6-a453636abbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34478
16175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3447816175
Directory /workspace/31.usbdev_out_iso/latest


Test location /workspace/coverage/default/31.usbdev_out_stall.2844034458
Short name T1037
Test name
Test status
Simulation time 175960574 ps
CPU time 0.9 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:14:08 PM PDT 24
Peak memory 206560 kb
Host smart-dcc1c8f3-8657-49aa-bb87-8a1acce3db74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440
34458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2844034458
Directory /workspace/31.usbdev_out_stall/latest


Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1549369773
Short name T2189
Test name
Test status
Simulation time 157438797 ps
CPU time 0.86 seconds
Started Aug 11 07:13:50 PM PDT 24
Finished Aug 11 07:13:51 PM PDT 24
Peak memory 207480 kb
Host smart-7535f2e7-1588-4a7c-8a6c-2b7cc4d086af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15493
69773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1549369773
Directory /workspace/31.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/31.usbdev_pending_in_trans.4260097095
Short name T1380
Test name
Test status
Simulation time 150767238 ps
CPU time 0.9 seconds
Started Aug 11 07:13:52 PM PDT 24
Finished Aug 11 07:13:53 PM PDT 24
Peak memory 207592 kb
Host smart-90236d1e-8db7-4846-b05b-156686f8bdc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42600
97095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.4260097095
Directory /workspace/31.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.1672263457
Short name T565
Test name
Test status
Simulation time 206788503 ps
CPU time 0.96 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207564 kb
Host smart-0efcd0c6-40c6-4181-873f-6d5db4ce6199
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1672263457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1672263457
Directory /workspace/31.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2472517266
Short name T3537
Test name
Test status
Simulation time 145248423 ps
CPU time 0.88 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207520 kb
Host smart-8ebb6777-3980-4c12-9618-fd5f9f58ce3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24725
17266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2472517266
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.971415257
Short name T3451
Test name
Test status
Simulation time 51544963 ps
CPU time 0.75 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207488 kb
Host smart-ea494d9b-60b7-4a64-a3ed-a83b6811ad39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97141
5257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.971415257
Directory /workspace/31.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1977255693
Short name T299
Test name
Test status
Simulation time 18223524166 ps
CPU time 49.5 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 215972 kb
Host smart-febb9f73-0fc5-4f5d-96e4-14c03230595e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
55693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1977255693
Directory /workspace/31.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/31.usbdev_pkt_received.3824767185
Short name T1030
Test name
Test status
Simulation time 170922556 ps
CPU time 0.88 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207568 kb
Host smart-ae4ed9aa-dc47-4028-8753-7062aecb4952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
67185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3824767185
Directory /workspace/31.usbdev_pkt_received/latest


Test location /workspace/coverage/default/31.usbdev_pkt_sent.1298808597
Short name T1192
Test name
Test status
Simulation time 196230463 ps
CPU time 0.89 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207568 kb
Host smart-43cf33be-fc06-4dd8-af90-ebbdc60dc792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12988
08597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1298808597
Directory /workspace/31.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2540477962
Short name T288
Test name
Test status
Simulation time 155027811 ps
CPU time 0.84 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207552 kb
Host smart-f2f928ee-b338-4b46-a1d0-8b4deadc75b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25404
77962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2540477962
Directory /workspace/31.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.817197974
Short name T2987
Test name
Test status
Simulation time 193646646 ps
CPU time 0.93 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207544 kb
Host smart-4c2c08f7-6073-4b6f-a116-03cd9945eafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81719
7974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.817197974
Directory /workspace/31.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2920715688
Short name T2484
Test name
Test status
Simulation time 151403358 ps
CPU time 0.81 seconds
Started Aug 11 07:13:57 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207552 kb
Host smart-7f3bf710-1123-473f-a177-a5bf0249bace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207
15688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2920715688
Directory /workspace/31.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/31.usbdev_rx_full.2596433413
Short name T1895
Test name
Test status
Simulation time 375945447 ps
CPU time 1.25 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207572 kb
Host smart-785215a9-2851-4c22-8f5f-0fd322fc8daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25964
33413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.2596433413
Directory /workspace/31.usbdev_rx_full/latest


Test location /workspace/coverage/default/31.usbdev_setup_stage.2601367380
Short name T2719
Test name
Test status
Simulation time 158454571 ps
CPU time 0.84 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207500 kb
Host smart-6028a55e-c309-4f93-9d47-915e134c2bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26013
67380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2601367380
Directory /workspace/31.usbdev_setup_stage/latest


Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2341126249
Short name T3402
Test name
Test status
Simulation time 189600915 ps
CPU time 0.95 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:14:08 PM PDT 24
Peak memory 207564 kb
Host smart-776274f6-9997-4479-9e84-fd6d57485161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23411
26249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2341126249
Directory /workspace/31.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/31.usbdev_smoke.2541594892
Short name T787
Test name
Test status
Simulation time 212490388 ps
CPU time 0.99 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207508 kb
Host smart-67c83641-0333-418c-bc1f-83d9b1b3c21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25415
94892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2541594892
Directory /workspace/31.usbdev_smoke/latest


Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3962928500
Short name T1416
Test name
Test status
Simulation time 2459020450 ps
CPU time 19.31 seconds
Started Aug 11 07:14:09 PM PDT 24
Finished Aug 11 07:14:28 PM PDT 24
Peak memory 218100 kb
Host smart-551c5634-d65c-4294-8276-ecc06b7c38d5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3962928500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3962928500
Directory /workspace/31.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3257114033
Short name T2176
Test name
Test status
Simulation time 177445480 ps
CPU time 0.9 seconds
Started Aug 11 07:14:01 PM PDT 24
Finished Aug 11 07:14:02 PM PDT 24
Peak memory 207552 kb
Host smart-a4b166e5-70b5-46a0-8d6b-a337127a34de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32571
14033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3257114033
Directory /workspace/31.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/31.usbdev_stall_trans.2842852142
Short name T1407
Test name
Test status
Simulation time 164997642 ps
CPU time 0.88 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207580 kb
Host smart-5ca53ce2-e42e-4d18-84e6-13a5aefdfd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28428
52142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2842852142
Directory /workspace/31.usbdev_stall_trans/latest


Test location /workspace/coverage/default/31.usbdev_stream_len_max.495205039
Short name T597
Test name
Test status
Simulation time 401729891 ps
CPU time 1.33 seconds
Started Aug 11 07:14:02 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207472 kb
Host smart-5fb87601-62cd-449a-9f09-286929f4c81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49520
5039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.495205039
Directory /workspace/31.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/31.usbdev_streaming_out.3818842332
Short name T2702
Test name
Test status
Simulation time 1962007115 ps
CPU time 19.83 seconds
Started Aug 11 07:13:56 PM PDT 24
Finished Aug 11 07:14:17 PM PDT 24
Peak memory 217524 kb
Host smart-5cf9e83b-9522-4e14-a6a2-cdf2afd56dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38188
42332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3818842332
Directory /workspace/31.usbdev_streaming_out/latest


Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.1337627637
Short name T901
Test name
Test status
Simulation time 5002665653 ps
CPU time 33.7 seconds
Started Aug 11 07:14:05 PM PDT 24
Finished Aug 11 07:14:39 PM PDT 24
Peak memory 207864 kb
Host smart-6cf52071-1023-4538-b12e-26afb554a8ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337627637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.1337627637
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/31.usbdev_tx_rx_disruption.3392553231
Short name T1700
Test name
Test status
Simulation time 600929250 ps
CPU time 1.69 seconds
Started Aug 11 07:14:08 PM PDT 24
Finished Aug 11 07:14:10 PM PDT 24
Peak memory 207572 kb
Host smart-917a931a-2def-4500-b985-e5319b4ba921
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392553231 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.usbdev_tx_rx_disruption.3392553231
Directory /workspace/31.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/310.usbdev_tx_rx_disruption.2939160741
Short name T1652
Test name
Test status
Simulation time 519508786 ps
CPU time 1.56 seconds
Started Aug 11 07:18:02 PM PDT 24
Finished Aug 11 07:18:04 PM PDT 24
Peak memory 207548 kb
Host smart-3babafdc-204a-44ee-b674-f3e78b31c728
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939160741 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 310.usbdev_tx_rx_disruption.2939160741
Directory /workspace/310.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/311.usbdev_tx_rx_disruption.3535616002
Short name T3138
Test name
Test status
Simulation time 667883955 ps
CPU time 1.73 seconds
Started Aug 11 07:17:54 PM PDT 24
Finished Aug 11 07:17:56 PM PDT 24
Peak memory 207492 kb
Host smart-93b7590e-61a1-4259-9ad7-5f7b11043ca0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535616002 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 311.usbdev_tx_rx_disruption.3535616002
Directory /workspace/311.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/312.usbdev_tx_rx_disruption.3006450655
Short name T3453
Test name
Test status
Simulation time 510658080 ps
CPU time 1.46 seconds
Started Aug 11 07:17:48 PM PDT 24
Finished Aug 11 07:17:49 PM PDT 24
Peak memory 207516 kb
Host smart-16658ab5-008a-47b0-adfb-6d50abdf0f3b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006450655 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 312.usbdev_tx_rx_disruption.3006450655
Directory /workspace/312.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/313.usbdev_tx_rx_disruption.856124175
Short name T2392
Test name
Test status
Simulation time 583069714 ps
CPU time 1.74 seconds
Started Aug 11 07:17:48 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207468 kb
Host smart-0e860278-c6f7-4af6-9ecf-2cf263d81850
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856124175 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 313.usbdev_tx_rx_disruption.856124175
Directory /workspace/313.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/314.usbdev_tx_rx_disruption.308675532
Short name T587
Test name
Test status
Simulation time 519316711 ps
CPU time 1.6 seconds
Started Aug 11 07:17:48 PM PDT 24
Finished Aug 11 07:17:49 PM PDT 24
Peak memory 207568 kb
Host smart-4349e3a3-1346-4639-8d26-809292ced864
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308675532 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 314.usbdev_tx_rx_disruption.308675532
Directory /workspace/314.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/315.usbdev_tx_rx_disruption.2687066980
Short name T3275
Test name
Test status
Simulation time 478005600 ps
CPU time 1.43 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207388 kb
Host smart-868a5fd1-5118-499a-b7fd-ec0b4cb65619
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687066980 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 315.usbdev_tx_rx_disruption.2687066980
Directory /workspace/315.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/316.usbdev_tx_rx_disruption.3393964535
Short name T703
Test name
Test status
Simulation time 458291916 ps
CPU time 1.34 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:40 PM PDT 24
Peak memory 207568 kb
Host smart-eb09fcf2-cbb8-4594-a407-7b2bce6e738e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393964535 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 316.usbdev_tx_rx_disruption.3393964535
Directory /workspace/316.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/317.usbdev_tx_rx_disruption.3463570357
Short name T2895
Test name
Test status
Simulation time 607377971 ps
CPU time 1.63 seconds
Started Aug 11 07:17:50 PM PDT 24
Finished Aug 11 07:17:51 PM PDT 24
Peak memory 207568 kb
Host smart-516209a3-0577-4b49-926a-e5ebf40df9a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463570357 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 317.usbdev_tx_rx_disruption.3463570357
Directory /workspace/317.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/318.usbdev_tx_rx_disruption.612701595
Short name T987
Test name
Test status
Simulation time 562804060 ps
CPU time 1.62 seconds
Started Aug 11 07:17:52 PM PDT 24
Finished Aug 11 07:17:54 PM PDT 24
Peak memory 207548 kb
Host smart-4794e9c0-dbb2-4554-b48d-ba923a1cb8f4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612701595 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 318.usbdev_tx_rx_disruption.612701595
Directory /workspace/318.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/319.usbdev_tx_rx_disruption.2600343542
Short name T2230
Test name
Test status
Simulation time 484233864 ps
CPU time 1.49 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207564 kb
Host smart-be0334be-1253-4b54-929c-0117e390e396
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600343542 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 319.usbdev_tx_rx_disruption.2600343542
Directory /workspace/319.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/32.usbdev_alert_test.3642581219
Short name T594
Test name
Test status
Simulation time 57883150 ps
CPU time 0.78 seconds
Started Aug 11 07:14:10 PM PDT 24
Finished Aug 11 07:14:11 PM PDT 24
Peak memory 207592 kb
Host smart-c9de2f61-86f1-4ba1-9871-bd98a9d40541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3642581219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3642581219
Directory /workspace/32.usbdev_alert_test/latest


Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2812400849
Short name T2274
Test name
Test status
Simulation time 6544400826 ps
CPU time 7.95 seconds
Started Aug 11 07:14:06 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 216020 kb
Host smart-3b06b610-147e-4a34-bcca-6f9fc13c127f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812400849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.2812400849
Directory /workspace/32.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.4144937057
Short name T3450
Test name
Test status
Simulation time 13933533691 ps
CPU time 18.5 seconds
Started Aug 11 07:13:59 PM PDT 24
Finished Aug 11 07:14:18 PM PDT 24
Peak memory 216024 kb
Host smart-2ea497af-b744-4230-8eed-86ef29651244
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144937057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.4144937057
Directory /workspace/32.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2525530438
Short name T2326
Test name
Test status
Simulation time 24616967773 ps
CPU time 31.52 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:14:39 PM PDT 24
Peak memory 215948 kb
Host smart-5d9d4457-1e5e-4889-812a-93be1f6c5b8d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525530438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.2525530438
Directory /workspace/32.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/32.usbdev_av_buffer.1590277401
Short name T1708
Test name
Test status
Simulation time 211821233 ps
CPU time 0.98 seconds
Started Aug 11 07:13:55 PM PDT 24
Finished Aug 11 07:13:56 PM PDT 24
Peak memory 207508 kb
Host smart-97047096-c8c6-4476-8e1a-44ccb5c8308f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15902
77401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1590277401
Directory /workspace/32.usbdev_av_buffer/latest


Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2586997143
Short name T2118
Test name
Test status
Simulation time 215995514 ps
CPU time 0.9 seconds
Started Aug 11 07:14:01 PM PDT 24
Finished Aug 11 07:14:02 PM PDT 24
Peak memory 207496 kb
Host smart-4a2a8c15-2d79-443d-8c0e-97a4df15fa4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869
97143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2586997143
Directory /workspace/32.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2958436699
Short name T2697
Test name
Test status
Simulation time 258457342 ps
CPU time 1.15 seconds
Started Aug 11 07:14:00 PM PDT 24
Finished Aug 11 07:14:01 PM PDT 24
Peak memory 207572 kb
Host smart-d15ad568-0f06-4ea4-8494-a56effd55f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29584
36699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2958436699
Directory /workspace/32.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.4169868206
Short name T2567
Test name
Test status
Simulation time 576029803 ps
CPU time 1.72 seconds
Started Aug 11 07:13:59 PM PDT 24
Finished Aug 11 07:14:01 PM PDT 24
Peak memory 207508 kb
Host smart-8fbb07cd-7758-4643-8555-4b74bdd3334a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4169868206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.4169868206
Directory /workspace/32.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/32.usbdev_device_address.3471610214
Short name T1630
Test name
Test status
Simulation time 16521715428 ps
CPU time 27.5 seconds
Started Aug 11 07:13:53 PM PDT 24
Finished Aug 11 07:14:21 PM PDT 24
Peak memory 207840 kb
Host smart-a8a050fe-58ba-42ea-beb7-fb7d48d43855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34716
10214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3471610214
Directory /workspace/32.usbdev_device_address/latest


Test location /workspace/coverage/default/32.usbdev_device_timeout.873417298
Short name T3593
Test name
Test status
Simulation time 4970242478 ps
CPU time 32.43 seconds
Started Aug 11 07:13:59 PM PDT 24
Finished Aug 11 07:14:32 PM PDT 24
Peak memory 207844 kb
Host smart-a1fcf524-4f14-42e3-bb56-2cd57d698691
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873417298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.873417298
Directory /workspace/32.usbdev_device_timeout/latest


Test location /workspace/coverage/default/32.usbdev_disable_endpoint.4049223548
Short name T3434
Test name
Test status
Simulation time 988986236 ps
CPU time 2.19 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:14:09 PM PDT 24
Peak memory 207524 kb
Host smart-0ac0eec7-c58f-4f26-88ee-48ee730228b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40492
23548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.4049223548
Directory /workspace/32.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/32.usbdev_disconnected.4148976057
Short name T1675
Test name
Test status
Simulation time 145124255 ps
CPU time 0.82 seconds
Started Aug 11 07:14:02 PM PDT 24
Finished Aug 11 07:14:03 PM PDT 24
Peak memory 207468 kb
Host smart-1bc36612-9de4-47e8-9813-d2daa91a52ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41489
76057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.4148976057
Directory /workspace/32.usbdev_disconnected/latest


Test location /workspace/coverage/default/32.usbdev_enable.404620173
Short name T1647
Test name
Test status
Simulation time 39603578 ps
CPU time 0.72 seconds
Started Aug 11 07:14:00 PM PDT 24
Finished Aug 11 07:14:01 PM PDT 24
Peak memory 207484 kb
Host smart-6c7bc11f-cf54-4296-8a53-7ca41004bf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40462
0173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.404620173
Directory /workspace/32.usbdev_enable/latest


Test location /workspace/coverage/default/32.usbdev_endpoint_access.3878758838
Short name T2633
Test name
Test status
Simulation time 760340236 ps
CPU time 2.23 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:14:00 PM PDT 24
Peak memory 207696 kb
Host smart-ed087955-5375-401a-8ce9-6a25adac47b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38787
58838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3878758838
Directory /workspace/32.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/32.usbdev_endpoint_types.1028380058
Short name T514
Test name
Test status
Simulation time 254057946 ps
CPU time 1.04 seconds
Started Aug 11 07:13:53 PM PDT 24
Finished Aug 11 07:13:54 PM PDT 24
Peak memory 207504 kb
Host smart-c432c4a6-1621-4f03-b43e-6cf2c9d37fc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1028380058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.1028380058
Directory /workspace/32.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/32.usbdev_fifo_rst.3367991284
Short name T1844
Test name
Test status
Simulation time 365370250 ps
CPU time 2.66 seconds
Started Aug 11 07:13:56 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207608 kb
Host smart-22b69d1f-e26e-4879-8cda-22079a212060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33679
91284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3367991284
Directory /workspace/32.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/32.usbdev_in_iso.2074174933
Short name T2401
Test name
Test status
Simulation time 196820540 ps
CPU time 1.08 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 216908 kb
Host smart-4d270971-1b12-4f7c-8cdf-7eb16f6f94ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2074174933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2074174933
Directory /workspace/32.usbdev_in_iso/latest


Test location /workspace/coverage/default/32.usbdev_in_stall.2427784683
Short name T1971
Test name
Test status
Simulation time 150002914 ps
CPU time 0.85 seconds
Started Aug 11 07:14:02 PM PDT 24
Finished Aug 11 07:14:03 PM PDT 24
Peak memory 207544 kb
Host smart-e4be79d4-4c25-4262-a536-9ea09dae9ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24277
84683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2427784683
Directory /workspace/32.usbdev_in_stall/latest


Test location /workspace/coverage/default/32.usbdev_in_trans.616316655
Short name T2647
Test name
Test status
Simulation time 220721847 ps
CPU time 1.02 seconds
Started Aug 11 07:13:54 PM PDT 24
Finished Aug 11 07:13:56 PM PDT 24
Peak memory 207480 kb
Host smart-912e87cd-af00-4b15-bf83-5326d9b3402f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61631
6655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.616316655
Directory /workspace/32.usbdev_in_trans/latest


Test location /workspace/coverage/default/32.usbdev_invalid_sync.1554415236
Short name T685
Test name
Test status
Simulation time 3474028352 ps
CPU time 103.56 seconds
Started Aug 11 07:14:00 PM PDT 24
Finished Aug 11 07:15:44 PM PDT 24
Peak memory 216068 kb
Host smart-68ca8ae9-a313-48b5-a138-77a736c0c2ba
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1554415236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1554415236
Directory /workspace/32.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/32.usbdev_iso_retraction.1259882039
Short name T1075
Test name
Test status
Simulation time 4537971977 ps
CPU time 30.91 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 207796 kb
Host smart-25a54b51-518d-4e6d-be94-e7f1e61bb66c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1259882039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.1259882039
Directory /workspace/32.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/32.usbdev_link_in_err.4064286054
Short name T2753
Test name
Test status
Simulation time 172961332 ps
CPU time 0.89 seconds
Started Aug 11 07:13:56 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207520 kb
Host smart-03c32c57-b5f4-4c90-bf53-f4ac6068bf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40642
86054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.4064286054
Directory /workspace/32.usbdev_link_in_err/latest


Test location /workspace/coverage/default/32.usbdev_link_resume.2125955085
Short name T1324
Test name
Test status
Simulation time 29307458438 ps
CPU time 47.95 seconds
Started Aug 11 07:14:01 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 216124 kb
Host smart-99f8e1f6-cdd4-4752-84ca-a11d66d68858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21259
55085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2125955085
Directory /workspace/32.usbdev_link_resume/latest


Test location /workspace/coverage/default/32.usbdev_link_suspend.1727587137
Short name T1345
Test name
Test status
Simulation time 11350521477 ps
CPU time 15.87 seconds
Started Aug 11 07:14:08 PM PDT 24
Finished Aug 11 07:14:24 PM PDT 24
Peak memory 207844 kb
Host smart-2f88325c-5a2f-450b-ab9a-8aa2be63cb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17275
87137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1727587137
Directory /workspace/32.usbdev_link_suspend/latest


Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2642656189
Short name T406
Test name
Test status
Simulation time 3567991809 ps
CPU time 100.31 seconds
Started Aug 11 07:14:10 PM PDT 24
Finished Aug 11 07:15:50 PM PDT 24
Peak memory 224220 kb
Host smart-116e9ff2-d8b4-4dc6-979b-dc73ed77f56e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2642656189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2642656189
Directory /workspace/32.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2260416107
Short name T801
Test name
Test status
Simulation time 2734326344 ps
CPU time 25.27 seconds
Started Aug 11 07:14:10 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 216124 kb
Host smart-56a704c5-72ef-4339-9080-545df8d09996
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2260416107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2260416107
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1363534798
Short name T3557
Test name
Test status
Simulation time 255050878 ps
CPU time 1.04 seconds
Started Aug 11 07:13:59 PM PDT 24
Finished Aug 11 07:14:00 PM PDT 24
Peak memory 207536 kb
Host smart-2c63b2ad-689e-42af-8527-27c28eab88b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1363534798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1363534798
Directory /workspace/32.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1431341307
Short name T3070
Test name
Test status
Simulation time 245051895 ps
CPU time 0.98 seconds
Started Aug 11 07:14:09 PM PDT 24
Finished Aug 11 07:14:10 PM PDT 24
Peak memory 207560 kb
Host smart-c5eb152b-6e02-4234-a3be-5a7cc611ccf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14313
41307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1431341307
Directory /workspace/32.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.2121200229
Short name T1553
Test name
Test status
Simulation time 2285525660 ps
CPU time 69.71 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:15:08 PM PDT 24
Peak memory 216048 kb
Host smart-aab8116f-efc1-4c85-9e8a-41401d7c8ef7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2121200229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.2121200229
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3208063967
Short name T3200
Test name
Test status
Simulation time 156671846 ps
CPU time 0.87 seconds
Started Aug 11 07:14:00 PM PDT 24
Finished Aug 11 07:14:01 PM PDT 24
Peak memory 207540 kb
Host smart-95cd277e-e1ab-4057-b604-fb3b76284ac6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3208063967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3208063967
Directory /workspace/32.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.888234985
Short name T1928
Test name
Test status
Simulation time 189848089 ps
CPU time 0.88 seconds
Started Aug 11 07:14:04 PM PDT 24
Finished Aug 11 07:14:05 PM PDT 24
Peak memory 207516 kb
Host smart-d2c73811-2572-408c-89d2-6a71b596d636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88823
4985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.888234985
Directory /workspace/32.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_nak_trans.1251686355
Short name T2488
Test name
Test status
Simulation time 221348856 ps
CPU time 1.01 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207752 kb
Host smart-00e44a36-98fb-4a36-a5b8-90d644070695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12516
86355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1251686355
Directory /workspace/32.usbdev_nak_trans/latest


Test location /workspace/coverage/default/32.usbdev_out_iso.3315901600
Short name T2885
Test name
Test status
Simulation time 171028163 ps
CPU time 0.94 seconds
Started Aug 11 07:13:59 PM PDT 24
Finished Aug 11 07:14:00 PM PDT 24
Peak memory 207500 kb
Host smart-c2db3021-aa67-4140-83a8-1afe62ce1938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33159
01600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3315901600
Directory /workspace/32.usbdev_out_iso/latest


Test location /workspace/coverage/default/32.usbdev_out_stall.2101387835
Short name T545
Test name
Test status
Simulation time 174604466 ps
CPU time 0.88 seconds
Started Aug 11 07:14:08 PM PDT 24
Finished Aug 11 07:14:09 PM PDT 24
Peak memory 207492 kb
Host smart-94ac4734-751e-4883-a7cc-acdd72439d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21013
87835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2101387835
Directory /workspace/32.usbdev_out_stall/latest


Test location /workspace/coverage/default/32.usbdev_out_trans_nak.672157497
Short name T540
Test name
Test status
Simulation time 169195835 ps
CPU time 0.86 seconds
Started Aug 11 07:13:57 PM PDT 24
Finished Aug 11 07:13:58 PM PDT 24
Peak memory 207488 kb
Host smart-882f31a1-5949-412f-bcd4-a6b74836d300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67215
7497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.672157497
Directory /workspace/32.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/32.usbdev_pending_in_trans.332957910
Short name T2777
Test name
Test status
Simulation time 163987656 ps
CPU time 0.86 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207520 kb
Host smart-4fbd4f5b-8976-4dbc-922e-3e4caca485ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33295
7910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.332957910
Directory /workspace/32.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2968568871
Short name T632
Test name
Test status
Simulation time 225592043 ps
CPU time 0.98 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207532 kb
Host smart-02854e45-a142-4ddb-bd20-f82b21f31ddc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2968568871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2968568871
Directory /workspace/32.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1073670150
Short name T1206
Test name
Test status
Simulation time 146920050 ps
CPU time 0.88 seconds
Started Aug 11 07:14:19 PM PDT 24
Finished Aug 11 07:14:20 PM PDT 24
Peak memory 207552 kb
Host smart-ddded9e0-d194-48b4-94d4-ca2d713ef997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10736
70150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1073670150
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.994379652
Short name T980
Test name
Test status
Simulation time 37519263 ps
CPU time 0.69 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207420 kb
Host smart-f658f1f7-f820-488f-92f6-b1ce990d124f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99437
9652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.994379652
Directory /workspace/32.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2234747847
Short name T2362
Test name
Test status
Simulation time 20456768030 ps
CPU time 54.52 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 216060 kb
Host smart-41eb94c0-02b8-450f-9c56-434e2108e9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22347
47847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2234747847
Directory /workspace/32.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/32.usbdev_pkt_received.257026163
Short name T3016
Test name
Test status
Simulation time 208125437 ps
CPU time 1.02 seconds
Started Aug 11 07:14:00 PM PDT 24
Finished Aug 11 07:14:01 PM PDT 24
Peak memory 207540 kb
Host smart-3b72250d-0dd1-4353-ae38-55db24f257d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25702
6163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.257026163
Directory /workspace/32.usbdev_pkt_received/latest


Test location /workspace/coverage/default/32.usbdev_pkt_sent.905668117
Short name T857
Test name
Test status
Simulation time 195431522 ps
CPU time 0.98 seconds
Started Aug 11 07:14:06 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 207492 kb
Host smart-f9987ec7-ce72-4b64-be7d-c06cabb638c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90566
8117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.905668117
Directory /workspace/32.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.947508243
Short name T2494
Test name
Test status
Simulation time 241687545 ps
CPU time 1.01 seconds
Started Aug 11 07:13:59 PM PDT 24
Finished Aug 11 07:14:00 PM PDT 24
Peak memory 207576 kb
Host smart-2fdee7e5-3be0-49c8-8956-91636ce5f091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94750
8243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.947508243
Directory /workspace/32.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.425843009
Short name T1485
Test name
Test status
Simulation time 210868707 ps
CPU time 1.05 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:14:08 PM PDT 24
Peak memory 207592 kb
Host smart-66ba1dce-4db2-42d8-978f-356cc45ff00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42584
3009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.425843009
Directory /workspace/32.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1904486090
Short name T2801
Test name
Test status
Simulation time 148461887 ps
CPU time 0.83 seconds
Started Aug 11 07:13:59 PM PDT 24
Finished Aug 11 07:14:00 PM PDT 24
Peak memory 207564 kb
Host smart-dcfe49eb-114e-4c30-ae93-88b43193aa44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19044
86090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1904486090
Directory /workspace/32.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/32.usbdev_rx_full.3482707654
Short name T2956
Test name
Test status
Simulation time 331734768 ps
CPU time 1.3 seconds
Started Aug 11 07:14:08 PM PDT 24
Finished Aug 11 07:14:09 PM PDT 24
Peak memory 207548 kb
Host smart-8fd7f4a8-4951-4245-9ef0-e60a569c0fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34827
07654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.3482707654
Directory /workspace/32.usbdev_rx_full/latest


Test location /workspace/coverage/default/32.usbdev_setup_stage.352573149
Short name T1311
Test name
Test status
Simulation time 185199670 ps
CPU time 0.85 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207544 kb
Host smart-09d32b55-bebc-490a-bd35-e6f24cb116f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35257
3149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.352573149
Directory /workspace/32.usbdev_setup_stage/latest


Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1015706849
Short name T1055
Test name
Test status
Simulation time 150881305 ps
CPU time 0.84 seconds
Started Aug 11 07:14:05 PM PDT 24
Finished Aug 11 07:14:06 PM PDT 24
Peak memory 207576 kb
Host smart-ceffa555-5021-4c24-bd65-f2827c44b276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157
06849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1015706849
Directory /workspace/32.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/32.usbdev_smoke.2338525494
Short name T2981
Test name
Test status
Simulation time 226125706 ps
CPU time 1.02 seconds
Started Aug 11 07:13:58 PM PDT 24
Finished Aug 11 07:13:59 PM PDT 24
Peak memory 207480 kb
Host smart-d205b06b-2d7b-4ef8-8ff3-b59465e957c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23385
25494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2338525494
Directory /workspace/32.usbdev_smoke/latest


Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.639060256
Short name T2746
Test name
Test status
Simulation time 3880659015 ps
CPU time 39.81 seconds
Started Aug 11 07:13:59 PM PDT 24
Finished Aug 11 07:14:39 PM PDT 24
Peak memory 224232 kb
Host smart-5a384d04-dbe5-4ab2-b204-a3cbc17265b4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=639060256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.639060256
Directory /workspace/32.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3360989927
Short name T1769
Test name
Test status
Simulation time 264561914 ps
CPU time 1.02 seconds
Started Aug 11 07:14:08 PM PDT 24
Finished Aug 11 07:14:09 PM PDT 24
Peak memory 207560 kb
Host smart-8bc3e7da-c869-4d99-86d1-6ccb24502e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33609
89927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3360989927
Directory /workspace/32.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/32.usbdev_stall_trans.3098483016
Short name T2551
Test name
Test status
Simulation time 170346587 ps
CPU time 0.91 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:04 PM PDT 24
Peak memory 207552 kb
Host smart-1e275e11-069e-46a8-9f07-6ed978cc7be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30984
83016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3098483016
Directory /workspace/32.usbdev_stall_trans/latest


Test location /workspace/coverage/default/32.usbdev_stream_len_max.719976612
Short name T2375
Test name
Test status
Simulation time 1146856282 ps
CPU time 2.72 seconds
Started Aug 11 07:14:24 PM PDT 24
Finished Aug 11 07:14:27 PM PDT 24
Peak memory 207740 kb
Host smart-4bd4fde0-bc37-48f6-821e-4158aba498a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71997
6612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.719976612
Directory /workspace/32.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/32.usbdev_streaming_out.931092869
Short name T723
Test name
Test status
Simulation time 2486073084 ps
CPU time 20.62 seconds
Started Aug 11 07:14:08 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 217732 kb
Host smart-b629159e-7405-44fb-ac74-114b80b8525f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93109
2869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.931092869
Directory /workspace/32.usbdev_streaming_out/latest


Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.1155104218
Short name T1695
Test name
Test status
Simulation time 830486285 ps
CPU time 5.52 seconds
Started Aug 11 07:14:05 PM PDT 24
Finished Aug 11 07:14:11 PM PDT 24
Peak memory 207792 kb
Host smart-73f3244f-0a41-4d76-b7de-95bac7867332
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155104218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.1155104218
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/32.usbdev_tx_rx_disruption.215988669
Short name T2492
Test name
Test status
Simulation time 509828615 ps
CPU time 1.62 seconds
Started Aug 11 07:14:10 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207460 kb
Host smart-396f5219-c3c2-4398-b944-0606ff5cae34
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215988669 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.usbdev_tx_rx_disruption.215988669
Directory /workspace/32.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/320.usbdev_tx_rx_disruption.2380687245
Short name T2634
Test name
Test status
Simulation time 573534540 ps
CPU time 1.55 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:40 PM PDT 24
Peak memory 207580 kb
Host smart-6c5d7d54-1ced-4e55-8733-e9dc431b5964
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380687245 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 320.usbdev_tx_rx_disruption.2380687245
Directory /workspace/320.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/321.usbdev_tx_rx_disruption.1083851915
Short name T1673
Test name
Test status
Simulation time 639224244 ps
CPU time 1.63 seconds
Started Aug 11 07:17:31 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207592 kb
Host smart-bb53e38b-0187-4c41-97bb-2ac7ed59be1c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083851915 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 321.usbdev_tx_rx_disruption.1083851915
Directory /workspace/321.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/322.usbdev_tx_rx_disruption.2433042351
Short name T3069
Test name
Test status
Simulation time 647781209 ps
CPU time 1.72 seconds
Started Aug 11 07:17:42 PM PDT 24
Finished Aug 11 07:17:44 PM PDT 24
Peak memory 207572 kb
Host smart-17ca1775-a32d-4f36-86d4-5a7873692b67
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433042351 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 322.usbdev_tx_rx_disruption.2433042351
Directory /workspace/322.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/323.usbdev_tx_rx_disruption.2262915394
Short name T2242
Test name
Test status
Simulation time 666152586 ps
CPU time 1.73 seconds
Started Aug 11 07:17:53 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207572 kb
Host smart-2135fd86-1656-4284-9aba-41a0cc9c4328
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262915394 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 323.usbdev_tx_rx_disruption.2262915394
Directory /workspace/323.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/324.usbdev_tx_rx_disruption.1628167605
Short name T2566
Test name
Test status
Simulation time 539571621 ps
CPU time 1.58 seconds
Started Aug 11 07:17:46 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207524 kb
Host smart-b92302df-31a0-4714-968f-bcc8156f6860
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628167605 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 324.usbdev_tx_rx_disruption.1628167605
Directory /workspace/324.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/325.usbdev_tx_rx_disruption.3489124974
Short name T3502
Test name
Test status
Simulation time 646301055 ps
CPU time 1.66 seconds
Started Aug 11 07:17:43 PM PDT 24
Finished Aug 11 07:17:45 PM PDT 24
Peak memory 207580 kb
Host smart-cb79bb24-487b-456f-a7c6-244784acf438
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489124974 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 325.usbdev_tx_rx_disruption.3489124974
Directory /workspace/325.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/326.usbdev_tx_rx_disruption.2943889354
Short name T1474
Test name
Test status
Simulation time 653077446 ps
CPU time 1.71 seconds
Started Aug 11 07:17:43 PM PDT 24
Finished Aug 11 07:17:45 PM PDT 24
Peak memory 207520 kb
Host smart-0d604154-bb44-40f4-b6e5-5b6550b29075
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943889354 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 326.usbdev_tx_rx_disruption.2943889354
Directory /workspace/326.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/327.usbdev_tx_rx_disruption.81234934
Short name T1596
Test name
Test status
Simulation time 561012102 ps
CPU time 1.66 seconds
Started Aug 11 07:17:52 PM PDT 24
Finished Aug 11 07:17:54 PM PDT 24
Peak memory 207572 kb
Host smart-c7b170c2-4c03-4d39-8504-23f526ec8b38
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81234934 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 327.usbdev_tx_rx_disruption.81234934
Directory /workspace/327.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/328.usbdev_tx_rx_disruption.388876747
Short name T191
Test name
Test status
Simulation time 628585587 ps
CPU time 1.71 seconds
Started Aug 11 07:17:35 PM PDT 24
Finished Aug 11 07:17:37 PM PDT 24
Peak memory 207524 kb
Host smart-525dfa8b-8878-496b-abf3-9a1a633433ea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388876747 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 328.usbdev_tx_rx_disruption.388876747
Directory /workspace/328.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/329.usbdev_tx_rx_disruption.872243704
Short name T601
Test name
Test status
Simulation time 595822044 ps
CPU time 1.53 seconds
Started Aug 11 07:17:54 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207556 kb
Host smart-bb42dba3-a35f-4773-998f-fbcad1bf036b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872243704 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 329.usbdev_tx_rx_disruption.872243704
Directory /workspace/329.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/33.usbdev_alert_test.4237507877
Short name T216
Test name
Test status
Simulation time 74660494 ps
CPU time 0.72 seconds
Started Aug 11 07:14:24 PM PDT 24
Finished Aug 11 07:14:25 PM PDT 24
Peak memory 207444 kb
Host smart-dd982270-8c22-4137-893a-b28788b256e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4237507877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.4237507877
Directory /workspace/33.usbdev_alert_test/latest


Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3150112780
Short name T3607
Test name
Test status
Simulation time 5955890011 ps
CPU time 9.52 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:14:16 PM PDT 24
Peak memory 216012 kb
Host smart-cc2a9e92-f2b9-47ca-82e8-d35ee9a1c664
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150112780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.3150112780
Directory /workspace/33.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.4141724070
Short name T2748
Test name
Test status
Simulation time 13862094916 ps
CPU time 15.77 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:19 PM PDT 24
Peak memory 216240 kb
Host smart-fac80b78-bd30-481d-a248-a9b45eb1e770
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141724070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.4141724070
Directory /workspace/33.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1236591289
Short name T1698
Test name
Test status
Simulation time 30270099474 ps
CPU time 43.85 seconds
Started Aug 11 07:14:05 PM PDT 24
Finished Aug 11 07:14:49 PM PDT 24
Peak memory 207788 kb
Host smart-9b5c990b-d659-49d9-9359-8b4170d7e0b9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236591289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.1236591289
Directory /workspace/33.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/33.usbdev_av_buffer.1083463107
Short name T619
Test name
Test status
Simulation time 160867263 ps
CPU time 0.83 seconds
Started Aug 11 07:14:05 PM PDT 24
Finished Aug 11 07:14:06 PM PDT 24
Peak memory 207464 kb
Host smart-1e43f03b-c5fb-4cdc-9dd6-03b6a7c93af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10834
63107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1083463107
Directory /workspace/33.usbdev_av_buffer/latest


Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3183134312
Short name T1164
Test name
Test status
Simulation time 185971177 ps
CPU time 0.9 seconds
Started Aug 11 07:14:06 PM PDT 24
Finished Aug 11 07:14:07 PM PDT 24
Peak memory 207552 kb
Host smart-7d21c71d-1ef7-4b8c-bf88-a09725097214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831
34312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3183134312
Directory /workspace/33.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2957912488
Short name T3574
Test name
Test status
Simulation time 319361761 ps
CPU time 1.24 seconds
Started Aug 11 07:14:09 PM PDT 24
Finished Aug 11 07:14:10 PM PDT 24
Peak memory 207492 kb
Host smart-3f821901-1b26-43ba-969f-6a4cf1d3004d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29579
12488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2957912488
Directory /workspace/33.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.4172697349
Short name T915
Test name
Test status
Simulation time 1278115402 ps
CPU time 3.34 seconds
Started Aug 11 07:14:22 PM PDT 24
Finished Aug 11 07:14:26 PM PDT 24
Peak memory 207748 kb
Host smart-105144c3-6156-4172-89ad-1b97f9f460f1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4172697349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.4172697349
Directory /workspace/33.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/33.usbdev_device_address.3919369329
Short name T2581
Test name
Test status
Simulation time 47684014689 ps
CPU time 85.98 seconds
Started Aug 11 07:14:07 PM PDT 24
Finished Aug 11 07:15:33 PM PDT 24
Peak memory 207840 kb
Host smart-cd9d50fc-434a-4762-ac52-12f251ad7cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39193
69329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3919369329
Directory /workspace/33.usbdev_device_address/latest


Test location /workspace/coverage/default/33.usbdev_device_timeout.1063039644
Short name T2999
Test name
Test status
Simulation time 3410329964 ps
CPU time 32.11 seconds
Started Aug 11 07:14:03 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207872 kb
Host smart-44632f27-1399-4471-9b7a-428e68c3397b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063039644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.1063039644
Directory /workspace/33.usbdev_device_timeout/latest


Test location /workspace/coverage/default/33.usbdev_disable_endpoint.2529064399
Short name T3424
Test name
Test status
Simulation time 744820056 ps
CPU time 1.77 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:15 PM PDT 24
Peak memory 207516 kb
Host smart-18387f6c-acfb-4a6d-9e26-419446154dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25290
64399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2529064399
Directory /workspace/33.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/33.usbdev_disconnected.904364239
Short name T1213
Test name
Test status
Simulation time 185790043 ps
CPU time 0.85 seconds
Started Aug 11 07:14:12 PM PDT 24
Finished Aug 11 07:14:13 PM PDT 24
Peak memory 207424 kb
Host smart-f33a6d4f-51b5-437b-b9dd-d3429565297e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90436
4239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.904364239
Directory /workspace/33.usbdev_disconnected/latest


Test location /workspace/coverage/default/33.usbdev_enable.1340304257
Short name T660
Test name
Test status
Simulation time 53837874 ps
CPU time 0.72 seconds
Started Aug 11 07:14:12 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207536 kb
Host smart-406e80ed-6c5b-4b0b-8ba2-f0c9231c4891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13403
04257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1340304257
Directory /workspace/33.usbdev_enable/latest


Test location /workspace/coverage/default/33.usbdev_endpoint_access.470543793
Short name T3071
Test name
Test status
Simulation time 802266794 ps
CPU time 2.28 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:28 PM PDT 24
Peak memory 207760 kb
Host smart-4755f3f3-7f9d-43ca-b89c-3b069dcd8f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47054
3793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.470543793
Directory /workspace/33.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/33.usbdev_fifo_rst.1982947876
Short name T1803
Test name
Test status
Simulation time 333401904 ps
CPU time 2.03 seconds
Started Aug 11 07:14:16 PM PDT 24
Finished Aug 11 07:14:18 PM PDT 24
Peak memory 207896 kb
Host smart-913c2394-fc1d-4516-abe8-cf8a432c1cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19829
47876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1982947876
Directory /workspace/33.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/33.usbdev_in_iso.962629869
Short name T3595
Test name
Test status
Simulation time 293564101 ps
CPU time 1.18 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 215944 kb
Host smart-b02d0bc5-5f68-4494-a947-8e8496d7ca86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=962629869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.962629869
Directory /workspace/33.usbdev_in_iso/latest


Test location /workspace/coverage/default/33.usbdev_in_stall.1465104666
Short name T1641
Test name
Test status
Simulation time 170368967 ps
CPU time 0.84 seconds
Started Aug 11 07:14:10 PM PDT 24
Finished Aug 11 07:14:11 PM PDT 24
Peak memory 207520 kb
Host smart-a91e02d2-d6f9-48db-b767-304b9153e7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14651
04666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1465104666
Directory /workspace/33.usbdev_in_stall/latest


Test location /workspace/coverage/default/33.usbdev_in_trans.1420309529
Short name T3485
Test name
Test status
Simulation time 239477647 ps
CPU time 1.01 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207572 kb
Host smart-34854268-8509-4ac8-b353-1a38aecc04cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14203
09529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1420309529
Directory /workspace/33.usbdev_in_trans/latest


Test location /workspace/coverage/default/33.usbdev_invalid_sync.1770747930
Short name T2990
Test name
Test status
Simulation time 3837737467 ps
CPU time 38.25 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 224284 kb
Host smart-d003bf75-791b-4ef6-a76f-06c1ac1a64f1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1770747930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1770747930
Directory /workspace/33.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/33.usbdev_iso_retraction.2060385798
Short name T2585
Test name
Test status
Simulation time 9639829772 ps
CPU time 66.74 seconds
Started Aug 11 07:14:30 PM PDT 24
Finished Aug 11 07:15:37 PM PDT 24
Peak memory 207832 kb
Host smart-7c6895d3-04ba-4ea8-859d-b30b9de83fc3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2060385798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2060385798
Directory /workspace/33.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/33.usbdev_link_in_err.2301909788
Short name T1730
Test name
Test status
Simulation time 253884395 ps
CPU time 1.04 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 207564 kb
Host smart-e7236876-bde8-48c5-b0c2-dbf5dff02cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23019
09788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2301909788
Directory /workspace/33.usbdev_link_in_err/latest


Test location /workspace/coverage/default/33.usbdev_link_resume.2972938593
Short name T2861
Test name
Test status
Simulation time 28541479071 ps
CPU time 43.05 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:15:10 PM PDT 24
Peak memory 207876 kb
Host smart-19f49a85-71a5-44e6-af4f-17729713c41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29729
38593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2972938593
Directory /workspace/33.usbdev_link_resume/latest


Test location /workspace/coverage/default/33.usbdev_link_suspend.759850584
Short name T1488
Test name
Test status
Simulation time 10408952310 ps
CPU time 12.3 seconds
Started Aug 11 07:14:16 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 208048 kb
Host smart-d89f81a6-d3aa-409e-aece-3dbd76e080eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75985
0584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.759850584
Directory /workspace/33.usbdev_link_suspend/latest


Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.4048932762
Short name T1232
Test name
Test status
Simulation time 3953774124 ps
CPU time 40.09 seconds
Started Aug 11 07:14:30 PM PDT 24
Finished Aug 11 07:15:10 PM PDT 24
Peak memory 219416 kb
Host smart-1e89ab93-739c-4e19-b7a4-67e1bf75a27f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4048932762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.4048932762
Directory /workspace/33.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1497915459
Short name T3014
Test name
Test status
Simulation time 2455097716 ps
CPU time 65.73 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:15:17 PM PDT 24
Peak memory 216032 kb
Host smart-304c88e9-8a32-4eda-9ea5-bd4fded84e7c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1497915459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1497915459
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1979144827
Short name T2472
Test name
Test status
Simulation time 246854126 ps
CPU time 1.11 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:28 PM PDT 24
Peak memory 207568 kb
Host smart-aab446e2-3be1-4bad-a63c-c5572c1c1858
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1979144827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1979144827
Directory /workspace/33.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2723230735
Short name T3515
Test name
Test status
Simulation time 202517376 ps
CPU time 0.94 seconds
Started Aug 11 07:14:22 PM PDT 24
Finished Aug 11 07:14:23 PM PDT 24
Peak memory 207564 kb
Host smart-8b5f6c9a-6cea-426e-9204-6a7e2c14777b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27232
30735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2723230735
Directory /workspace/33.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2768805100
Short name T2084
Test name
Test status
Simulation time 3979095479 ps
CPU time 29.42 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:58 PM PDT 24
Peak memory 216080 kb
Host smart-750e5e9b-16c6-452d-8498-48d16fe2da05
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2768805100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2768805100
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.1996661761
Short name T567
Test name
Test status
Simulation time 153709331 ps
CPU time 0.86 seconds
Started Aug 11 07:14:17 PM PDT 24
Finished Aug 11 07:14:18 PM PDT 24
Peak memory 207500 kb
Host smart-9232ede4-60b5-4e35-a9ea-2c8422d1fb04
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1996661761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.1996661761
Directory /workspace/33.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.987448326
Short name T2531
Test name
Test status
Simulation time 141709505 ps
CPU time 0.83 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207516 kb
Host smart-2be39d65-6254-4d5f-b218-0098979d5e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98744
8326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.987448326
Directory /workspace/33.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_nak_trans.3617817474
Short name T162
Test name
Test status
Simulation time 246198708 ps
CPU time 0.98 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207552 kb
Host smart-1ce156a8-4a59-447a-917a-4f679da577bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
17474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3617817474
Directory /workspace/33.usbdev_nak_trans/latest


Test location /workspace/coverage/default/33.usbdev_out_iso.391517255
Short name T3321
Test name
Test status
Simulation time 155554865 ps
CPU time 0.9 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 207496 kb
Host smart-a03a6551-b328-46f0-9ead-5f9a5cd7c7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39151
7255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.391517255
Directory /workspace/33.usbdev_out_iso/latest


Test location /workspace/coverage/default/33.usbdev_out_stall.2841739379
Short name T972
Test name
Test status
Simulation time 185400096 ps
CPU time 0.88 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207452 kb
Host smart-5e5fca4e-3f98-4e49-a03a-8c0420449050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28417
39379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2841739379
Directory /workspace/33.usbdev_out_stall/latest


Test location /workspace/coverage/default/33.usbdev_out_trans_nak.570341898
Short name T2417
Test name
Test status
Simulation time 156479912 ps
CPU time 0.88 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207584 kb
Host smart-996a83ad-09b1-43ef-801f-67b500067696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57034
1898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.570341898
Directory /workspace/33.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/33.usbdev_pending_in_trans.994170040
Short name T711
Test name
Test status
Simulation time 213336706 ps
CPU time 1 seconds
Started Aug 11 07:14:17 PM PDT 24
Finished Aug 11 07:14:18 PM PDT 24
Peak memory 207492 kb
Host smart-d511313b-d7e5-4d6e-bd56-e4d4f0fcbde3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99417
0040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.994170040
Directory /workspace/33.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3452998589
Short name T2765
Test name
Test status
Simulation time 209300863 ps
CPU time 1.02 seconds
Started Aug 11 07:14:14 PM PDT 24
Finished Aug 11 07:14:15 PM PDT 24
Peak memory 207508 kb
Host smart-31fa70da-0103-4a46-b746-8f4add1adad3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3452998589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3452998589
Directory /workspace/33.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.216066231
Short name T1079
Test name
Test status
Simulation time 155300703 ps
CPU time 0.83 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 207476 kb
Host smart-94ee0430-56a0-49b7-b150-a32f267d4d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21606
6231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.216066231
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1926089659
Short name T27
Test name
Test status
Simulation time 55419569 ps
CPU time 0.74 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207540 kb
Host smart-f8183f26-dd1f-47fd-89c0-bc73b39d12d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19260
89659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1926089659
Directory /workspace/33.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1686699318
Short name T3025
Test name
Test status
Simulation time 9329096811 ps
CPU time 23.33 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:51 PM PDT 24
Peak memory 216096 kb
Host smart-789dcc0e-ec6c-462f-a52d-3f92df66a5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16866
99318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1686699318
Directory /workspace/33.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/33.usbdev_pkt_received.3106298987
Short name T1842
Test name
Test status
Simulation time 246181088 ps
CPU time 0.98 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207540 kb
Host smart-3bd5a41f-a500-4ab0-9944-fe4b231da815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31062
98987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3106298987
Directory /workspace/33.usbdev_pkt_received/latest


Test location /workspace/coverage/default/33.usbdev_pkt_sent.2378791927
Short name T2157
Test name
Test status
Simulation time 254478722 ps
CPU time 1.01 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207480 kb
Host smart-d60919b2-13a9-4bc6-af75-958f004b2323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
91927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2378791927
Directory /workspace/33.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2591839277
Short name T2959
Test name
Test status
Simulation time 224233940 ps
CPU time 0.98 seconds
Started Aug 11 07:14:15 PM PDT 24
Finished Aug 11 07:14:16 PM PDT 24
Peak memory 207052 kb
Host smart-f33b7adb-aca3-4ba5-8d62-848eaf315b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25918
39277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2591839277
Directory /workspace/33.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2408463328
Short name T3249
Test name
Test status
Simulation time 187999707 ps
CPU time 0.9 seconds
Started Aug 11 07:14:31 PM PDT 24
Finished Aug 11 07:14:32 PM PDT 24
Peak memory 207504 kb
Host smart-765b4549-4516-4785-8faa-7827096b0fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24084
63328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2408463328
Directory /workspace/33.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1136506602
Short name T2881
Test name
Test status
Simulation time 145703924 ps
CPU time 0.88 seconds
Started Aug 11 07:14:16 PM PDT 24
Finished Aug 11 07:14:17 PM PDT 24
Peak memory 207756 kb
Host smart-24d76043-b4cb-40e5-a935-81f207c5d8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11365
06602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1136506602
Directory /workspace/33.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/33.usbdev_rx_full.802510
Short name T2042
Test name
Test status
Simulation time 389794400 ps
CPU time 1.3 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207592 kb
Host smart-0cba6ed9-9f11-4b37-80d0-8e7535a52d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80251
0 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.802510
Directory /workspace/33.usbdev_rx_full/latest


Test location /workspace/coverage/default/33.usbdev_setup_stage.3411525083
Short name T2977
Test name
Test status
Simulation time 148084087 ps
CPU time 0.84 seconds
Started Aug 11 07:14:13 PM PDT 24
Finished Aug 11 07:14:14 PM PDT 24
Peak memory 207564 kb
Host smart-29517634-41fc-4643-9b2e-3837f77693e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34115
25083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3411525083
Directory /workspace/33.usbdev_setup_stage/latest


Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3910959761
Short name T2151
Test name
Test status
Simulation time 233200331 ps
CPU time 0.98 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207540 kb
Host smart-b6b518ce-2337-471f-acf8-67839b14a62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39109
59761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3910959761
Directory /workspace/33.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/33.usbdev_smoke.865503326
Short name T2624
Test name
Test status
Simulation time 220448043 ps
CPU time 0.98 seconds
Started Aug 11 07:14:09 PM PDT 24
Finished Aug 11 07:14:10 PM PDT 24
Peak memory 207548 kb
Host smart-bd70544f-9b04-4618-8aac-4eadd1e47de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86550
3326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.865503326
Directory /workspace/33.usbdev_smoke/latest


Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.2921325160
Short name T2019
Test name
Test status
Simulation time 2769245723 ps
CPU time 78.26 seconds
Started Aug 11 07:14:23 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 224180 kb
Host smart-a4ea2892-cb0e-409a-a948-3a977c7823db
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2921325160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.2921325160
Directory /workspace/33.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2776015469
Short name T2296
Test name
Test status
Simulation time 206344817 ps
CPU time 0.91 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 207572 kb
Host smart-844a2770-c0c4-4da5-8366-70226d22ca4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27760
15469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2776015469
Directory /workspace/33.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/33.usbdev_stall_trans.725240796
Short name T695
Test name
Test status
Simulation time 161606060 ps
CPU time 0.87 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207456 kb
Host smart-30912cc7-670c-4bc0-bb7b-6f3e5b634e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72524
0796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.725240796
Directory /workspace/33.usbdev_stall_trans/latest


Test location /workspace/coverage/default/33.usbdev_stream_len_max.1450164227
Short name T2893
Test name
Test status
Simulation time 1188630166 ps
CPU time 2.62 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:14:32 PM PDT 24
Peak memory 207596 kb
Host smart-8a71a503-5181-43cb-972e-9a8b7c1c40a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14501
64227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1450164227
Directory /workspace/33.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/33.usbdev_streaming_out.1258204043
Short name T2145
Test name
Test status
Simulation time 3976152794 ps
CPU time 112.58 seconds
Started Aug 11 07:14:14 PM PDT 24
Finished Aug 11 07:16:06 PM PDT 24
Peak memory 216064 kb
Host smart-bdaabfdd-0823-497d-a7ed-cba748f48485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
04043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1258204043
Directory /workspace/33.usbdev_streaming_out/latest


Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.1745641662
Short name T2395
Test name
Test status
Simulation time 4304162486 ps
CPU time 31.75 seconds
Started Aug 11 07:14:06 PM PDT 24
Finished Aug 11 07:14:38 PM PDT 24
Peak memory 207852 kb
Host smart-7b75edde-678a-4b70-ad03-dd6da7f0b5ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745641662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.1745641662
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/33.usbdev_tx_rx_disruption.500902705
Short name T575
Test name
Test status
Simulation time 543109066 ps
CPU time 1.49 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207444 kb
Host smart-4d38a650-5f73-42a3-9034-32efb81cb46d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500902705 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.usbdev_tx_rx_disruption.500902705
Directory /workspace/33.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/330.usbdev_tx_rx_disruption.1146939397
Short name T107
Test name
Test status
Simulation time 448963500 ps
CPU time 1.48 seconds
Started Aug 11 07:17:50 PM PDT 24
Finished Aug 11 07:17:52 PM PDT 24
Peak memory 207556 kb
Host smart-85fd7d74-50f2-4eea-9562-0622571ba0cf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146939397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 330.usbdev_tx_rx_disruption.1146939397
Directory /workspace/330.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/331.usbdev_tx_rx_disruption.3185661240
Short name T228
Test name
Test status
Simulation time 607092690 ps
CPU time 1.71 seconds
Started Aug 11 07:17:37 PM PDT 24
Finished Aug 11 07:17:39 PM PDT 24
Peak memory 207548 kb
Host smart-606974a3-97eb-48a0-87a9-2351654df442
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185661240 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 331.usbdev_tx_rx_disruption.3185661240
Directory /workspace/331.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/332.usbdev_tx_rx_disruption.4141227624
Short name T806
Test name
Test status
Simulation time 555368996 ps
CPU time 1.67 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207576 kb
Host smart-b0d573cf-4341-4041-a535-23ecb32b20c2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141227624 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 332.usbdev_tx_rx_disruption.4141227624
Directory /workspace/332.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/333.usbdev_tx_rx_disruption.3096103922
Short name T180
Test name
Test status
Simulation time 496533472 ps
CPU time 1.52 seconds
Started Aug 11 07:17:32 PM PDT 24
Finished Aug 11 07:17:33 PM PDT 24
Peak memory 207572 kb
Host smart-f94195c4-9935-4036-b93d-c8d1d9ff7240
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096103922 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 333.usbdev_tx_rx_disruption.3096103922
Directory /workspace/333.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/334.usbdev_tx_rx_disruption.1329345277
Short name T287
Test name
Test status
Simulation time 490970464 ps
CPU time 1.48 seconds
Started Aug 11 07:17:53 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207572 kb
Host smart-5a0de183-f40e-4c02-a268-c1667a25d7bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329345277 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 334.usbdev_tx_rx_disruption.1329345277
Directory /workspace/334.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/335.usbdev_tx_rx_disruption.776333229
Short name T581
Test name
Test status
Simulation time 536816256 ps
CPU time 1.59 seconds
Started Aug 11 07:17:40 PM PDT 24
Finished Aug 11 07:17:42 PM PDT 24
Peak memory 207512 kb
Host smart-462be031-de38-4ee9-bf35-b580cf1a53c4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776333229 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 335.usbdev_tx_rx_disruption.776333229
Directory /workspace/335.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/336.usbdev_tx_rx_disruption.2809086280
Short name T3590
Test name
Test status
Simulation time 539511046 ps
CPU time 1.53 seconds
Started Aug 11 07:17:46 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207548 kb
Host smart-0d1df4e2-5b54-42a2-b031-f35a0302e5f3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809086280 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 336.usbdev_tx_rx_disruption.2809086280
Directory /workspace/336.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/337.usbdev_tx_rx_disruption.735087302
Short name T2076
Test name
Test status
Simulation time 614380458 ps
CPU time 1.74 seconds
Started Aug 11 07:17:52 PM PDT 24
Finished Aug 11 07:17:54 PM PDT 24
Peak memory 207552 kb
Host smart-a5920aa6-b96e-4bf7-b1bd-50051805b1f0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735087302 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 337.usbdev_tx_rx_disruption.735087302
Directory /workspace/337.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/338.usbdev_tx_rx_disruption.1435957202
Short name T656
Test name
Test status
Simulation time 537928665 ps
CPU time 1.59 seconds
Started Aug 11 07:17:42 PM PDT 24
Finished Aug 11 07:17:44 PM PDT 24
Peak memory 207508 kb
Host smart-e3d52e30-dad1-4539-90b5-d55d5a031569
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435957202 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 338.usbdev_tx_rx_disruption.1435957202
Directory /workspace/338.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/339.usbdev_tx_rx_disruption.4041082053
Short name T1446
Test name
Test status
Simulation time 618810824 ps
CPU time 1.6 seconds
Started Aug 11 07:17:36 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207512 kb
Host smart-27a5407a-5346-4ad4-bb79-7985d6c927a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041082053 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 339.usbdev_tx_rx_disruption.4041082053
Directory /workspace/339.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/34.usbdev_alert_test.2659044589
Short name T2275
Test name
Test status
Simulation time 41163592 ps
CPU time 0.67 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 207524 kb
Host smart-2e5c62d5-285e-4de8-9853-6113ff184997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2659044589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2659044589
Directory /workspace/34.usbdev_alert_test/latest


Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.4081297330
Short name T267
Test name
Test status
Simulation time 10866004491 ps
CPU time 14.71 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:43 PM PDT 24
Peak memory 207876 kb
Host smart-b7921694-4de5-4beb-bf4b-b9ff6576a25e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081297330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.4081297330
Directory /workspace/34.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.4160722529
Short name T3235
Test name
Test status
Simulation time 19119027545 ps
CPU time 21.51 seconds
Started Aug 11 07:14:14 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207868 kb
Host smart-815fe531-5cf8-403c-8721-815b961c014b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160722529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.4160722529
Directory /workspace/34.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.2451236772
Short name T767
Test name
Test status
Simulation time 30432712486 ps
CPU time 34.22 seconds
Started Aug 11 07:14:25 PM PDT 24
Finished Aug 11 07:14:59 PM PDT 24
Peak memory 208064 kb
Host smart-bb6f48cd-e071-4666-b9f7-6a9f2c8b588e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451236772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.2451236772
Directory /workspace/34.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/34.usbdev_av_buffer.3944419340
Short name T3035
Test name
Test status
Simulation time 196790190 ps
CPU time 0.94 seconds
Started Aug 11 07:14:15 PM PDT 24
Finished Aug 11 07:14:16 PM PDT 24
Peak memory 207520 kb
Host smart-17c675d3-8104-4a43-a73e-ebcb28f38830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39444
19340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3944419340
Directory /workspace/34.usbdev_av_buffer/latest


Test location /workspace/coverage/default/34.usbdev_bitstuff_err.826663056
Short name T1902
Test name
Test status
Simulation time 145666644 ps
CPU time 0.83 seconds
Started Aug 11 07:14:11 PM PDT 24
Finished Aug 11 07:14:12 PM PDT 24
Peak memory 207488 kb
Host smart-c2a0c85c-3626-4ef0-bdb5-1bbe1aa2615c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82666
3056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.826663056
Directory /workspace/34.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3587420641
Short name T1969
Test name
Test status
Simulation time 376465991 ps
CPU time 1.29 seconds
Started Aug 11 07:14:24 PM PDT 24
Finished Aug 11 07:14:26 PM PDT 24
Peak memory 207596 kb
Host smart-b8d04ca1-39d1-4258-aeea-a8428de1e72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35874
20641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3587420641
Directory /workspace/34.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3785460529
Short name T1281
Test name
Test status
Simulation time 823666491 ps
CPU time 2.35 seconds
Started Aug 11 07:14:14 PM PDT 24
Finished Aug 11 07:14:16 PM PDT 24
Peak memory 207700 kb
Host smart-1a9bb018-03bb-4072-a722-80f983a36d72
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3785460529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3785460529
Directory /workspace/34.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/34.usbdev_device_address.3873048094
Short name T1128
Test name
Test status
Simulation time 47579609084 ps
CPU time 80.33 seconds
Started Aug 11 07:14:27 PM PDT 24
Finished Aug 11 07:15:48 PM PDT 24
Peak memory 207824 kb
Host smart-acfafe24-3cb7-4cb8-a765-aebe60181ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38730
48094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3873048094
Directory /workspace/34.usbdev_device_address/latest


Test location /workspace/coverage/default/34.usbdev_device_timeout.1667418520
Short name T2371
Test name
Test status
Simulation time 5645464495 ps
CPU time 38.48 seconds
Started Aug 11 07:14:15 PM PDT 24
Finished Aug 11 07:14:54 PM PDT 24
Peak memory 207240 kb
Host smart-fb3ffd70-bd51-4689-8dd3-bca0702f6adc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667418520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.1667418520
Directory /workspace/34.usbdev_device_timeout/latest


Test location /workspace/coverage/default/34.usbdev_disable_endpoint.3793964577
Short name T2715
Test name
Test status
Simulation time 762380408 ps
CPU time 1.73 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:14:31 PM PDT 24
Peak memory 207480 kb
Host smart-768513ea-ba70-4fa0-968d-26c9b7556183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37939
64577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.3793964577
Directory /workspace/34.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/34.usbdev_disconnected.1422563036
Short name T2943
Test name
Test status
Simulation time 154726450 ps
CPU time 0.84 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207536 kb
Host smart-9443bf44-ac19-4f69-ad64-b0aa59f610d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14225
63036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1422563036
Directory /workspace/34.usbdev_disconnected/latest


Test location /workspace/coverage/default/34.usbdev_enable.2004596321
Short name T1469
Test name
Test status
Simulation time 75605085 ps
CPU time 0.74 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 207464 kb
Host smart-f44cb6c3-eed4-4391-8a8b-129faf58b65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20045
96321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2004596321
Directory /workspace/34.usbdev_enable/latest


Test location /workspace/coverage/default/34.usbdev_endpoint_access.2296276447
Short name T650
Test name
Test status
Simulation time 825940936 ps
CPU time 2.42 seconds
Started Aug 11 07:14:27 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207644 kb
Host smart-cce3d455-02e4-4043-a52b-551f289f863a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22962
76447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2296276447
Directory /workspace/34.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/34.usbdev_endpoint_types.2647059784
Short name T517
Test name
Test status
Simulation time 541973865 ps
CPU time 1.48 seconds
Started Aug 11 07:14:37 PM PDT 24
Finished Aug 11 07:14:39 PM PDT 24
Peak memory 207560 kb
Host smart-82248d4e-6b59-4337-90f7-644fa656c831
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2647059784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.2647059784
Directory /workspace/34.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/34.usbdev_fifo_rst.3938013224
Short name T2994
Test name
Test status
Simulation time 266132796 ps
CPU time 2.15 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207672 kb
Host smart-9145ee4d-6977-44f1-8bd3-f320b97464f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
13224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3938013224
Directory /workspace/34.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/34.usbdev_in_iso.1564782160
Short name T1601
Test name
Test status
Simulation time 240827068 ps
CPU time 1.15 seconds
Started Aug 11 07:14:36 PM PDT 24
Finished Aug 11 07:14:38 PM PDT 24
Peak memory 215968 kb
Host smart-9579c595-d909-442d-8788-2201f18f65cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1564782160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1564782160
Directory /workspace/34.usbdev_in_iso/latest


Test location /workspace/coverage/default/34.usbdev_in_stall.3657964772
Short name T1768
Test name
Test status
Simulation time 167147963 ps
CPU time 0.95 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:28 PM PDT 24
Peak memory 207520 kb
Host smart-8a99f1dd-1f34-4497-a346-a7cd256409da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36579
64772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3657964772
Directory /workspace/34.usbdev_in_stall/latest


Test location /workspace/coverage/default/34.usbdev_in_trans.2658528045
Short name T2459
Test name
Test status
Simulation time 228016562 ps
CPU time 0.95 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 207580 kb
Host smart-2c9fd14a-8193-4d18-8e18-95ba54f0b5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26585
28045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2658528045
Directory /workspace/34.usbdev_in_trans/latest


Test location /workspace/coverage/default/34.usbdev_invalid_sync.491694835
Short name T2381
Test name
Test status
Simulation time 4228167035 ps
CPU time 125.73 seconds
Started Aug 11 07:14:30 PM PDT 24
Finished Aug 11 07:16:36 PM PDT 24
Peak memory 224280 kb
Host smart-d3ea3167-7abf-4358-9556-5db8ee25883e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=491694835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.491694835
Directory /workspace/34.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/34.usbdev_iso_retraction.225909583
Short name T2580
Test name
Test status
Simulation time 5004525324 ps
CPU time 62.04 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:15:32 PM PDT 24
Peak memory 207772 kb
Host smart-3f4b0c1f-4445-43b5-9bd1-2bdbd3f0eb08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=225909583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.225909583
Directory /workspace/34.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/34.usbdev_link_in_err.4230265532
Short name T1921
Test name
Test status
Simulation time 157135889 ps
CPU time 0.87 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207592 kb
Host smart-81e7fa29-5579-43e2-a3a0-8e83f2ff79a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42302
65532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.4230265532
Directory /workspace/34.usbdev_link_in_err/latest


Test location /workspace/coverage/default/34.usbdev_link_resume.899007805
Short name T2883
Test name
Test status
Simulation time 24456184701 ps
CPU time 34.81 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:15:04 PM PDT 24
Peak memory 207780 kb
Host smart-aa7d6721-3ca6-46ba-bf53-eb194168b865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89900
7805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.899007805
Directory /workspace/34.usbdev_link_resume/latest


Test location /workspace/coverage/default/34.usbdev_link_suspend.3793053351
Short name T1579
Test name
Test status
Simulation time 5404185595 ps
CPU time 8.15 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207752 kb
Host smart-5ac3f49f-bc19-4513-96ab-3d729d3038ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37930
53351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3793053351
Directory /workspace/34.usbdev_link_suspend/latest


Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2381280842
Short name T416
Test name
Test status
Simulation time 3279759793 ps
CPU time 91.38 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:16:01 PM PDT 24
Peak memory 218564 kb
Host smart-77973435-4b6a-4a82-a799-58c8f391a44c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2381280842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2381280842
Directory /workspace/34.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2145688599
Short name T3177
Test name
Test status
Simulation time 3588335012 ps
CPU time 35.59 seconds
Started Aug 11 07:14:30 PM PDT 24
Finished Aug 11 07:15:06 PM PDT 24
Peak memory 216044 kb
Host smart-059a006d-db37-4bf2-955b-bce1b355fb1e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2145688599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2145688599
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1674057323
Short name T3012
Test name
Test status
Simulation time 236888360 ps
CPU time 1 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:27 PM PDT 24
Peak memory 207476 kb
Host smart-b2d612b1-b5a2-4803-b942-188c1c71c5b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1674057323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1674057323
Directory /workspace/34.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.260035260
Short name T2309
Test name
Test status
Simulation time 194952789 ps
CPU time 0.95 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:27 PM PDT 24
Peak memory 207552 kb
Host smart-39a092bf-14b4-491f-88ee-9c47f63e3ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26003
5260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.260035260
Directory /workspace/34.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.576057921
Short name T3131
Test name
Test status
Simulation time 3573800694 ps
CPU time 29.17 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207868 kb
Host smart-846f7515-2089-43c6-abc5-13eb4bb2a485
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=576057921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.576057921
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.57160795
Short name T3273
Test name
Test status
Simulation time 166365412 ps
CPU time 0.91 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 207124 kb
Host smart-0a372931-6de4-4ea3-a926-e3a79c511476
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=57160795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.57160795
Directory /workspace/34.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2409242091
Short name T1608
Test name
Test status
Simulation time 137371269 ps
CPU time 0.83 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 207496 kb
Host smart-186014a7-bd77-4347-a68a-5f3fbe7595d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24092
42091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2409242091
Directory /workspace/34.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_nak_trans.2098809340
Short name T155
Test name
Test status
Simulation time 266966928 ps
CPU time 1.12 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207516 kb
Host smart-80c812c6-741f-47cb-a959-aa4662737eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20988
09340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2098809340
Directory /workspace/34.usbdev_nak_trans/latest


Test location /workspace/coverage/default/34.usbdev_out_iso.1346857306
Short name T130
Test name
Test status
Simulation time 181902036 ps
CPU time 0.94 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 207552 kb
Host smart-d63f80e2-e725-4e93-b684-3ce17f005963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13468
57306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1346857306
Directory /workspace/34.usbdev_out_iso/latest


Test location /workspace/coverage/default/34.usbdev_out_stall.3351711427
Short name T2037
Test name
Test status
Simulation time 160480305 ps
CPU time 0.87 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 207544 kb
Host smart-cab53858-bfe6-43c7-9a4e-f062b46baf04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33517
11427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3351711427
Directory /workspace/34.usbdev_out_stall/latest


Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3040316261
Short name T3544
Test name
Test status
Simulation time 224842554 ps
CPU time 0.93 seconds
Started Aug 11 07:14:31 PM PDT 24
Finished Aug 11 07:14:32 PM PDT 24
Peak memory 207560 kb
Host smart-90447ce3-889c-4168-978d-88f639409cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30403
16261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3040316261
Directory /workspace/34.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/34.usbdev_pending_in_trans.820513857
Short name T898
Test name
Test status
Simulation time 151423476 ps
CPU time 0.86 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 207552 kb
Host smart-3344ee8e-08ab-4e61-a1ad-fd98d93ea6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82051
3857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.820513857
Directory /workspace/34.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1350689793
Short name T2794
Test name
Test status
Simulation time 238053647 ps
CPU time 1.09 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207504 kb
Host smart-30a9ec14-989f-41f6-86e7-c36e5ffaf400
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1350689793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1350689793
Directory /workspace/34.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2302545351
Short name T2539
Test name
Test status
Simulation time 160016621 ps
CPU time 0.86 seconds
Started Aug 11 07:14:30 PM PDT 24
Finished Aug 11 07:14:31 PM PDT 24
Peak memory 207520 kb
Host smart-7c21059b-48c9-42ae-aa03-7a006bcfb734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23025
45351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2302545351
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2921927867
Short name T2299
Test name
Test status
Simulation time 57025181 ps
CPU time 0.71 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207536 kb
Host smart-74e72489-78c7-41f0-a019-f2c7ff045857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29219
27867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2921927867
Directory /workspace/34.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/34.usbdev_pkt_buffer.65985013
Short name T2311
Test name
Test status
Simulation time 8085386017 ps
CPU time 22 seconds
Started Aug 11 07:14:25 PM PDT 24
Finished Aug 11 07:14:47 PM PDT 24
Peak memory 220568 kb
Host smart-4ca5bea9-11bb-4869-a40c-32fba3b7c992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65985
013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.65985013
Directory /workspace/34.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/34.usbdev_pkt_received.1646639190
Short name T1719
Test name
Test status
Simulation time 207316775 ps
CPU time 1.03 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 207092 kb
Host smart-bce6eb54-7234-465f-a548-0e93162c57d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16466
39190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1646639190
Directory /workspace/34.usbdev_pkt_received/latest


Test location /workspace/coverage/default/34.usbdev_pkt_sent.766750929
Short name T1427
Test name
Test status
Simulation time 248075092 ps
CPU time 1.05 seconds
Started Aug 11 07:14:42 PM PDT 24
Finished Aug 11 07:14:43 PM PDT 24
Peak memory 207480 kb
Host smart-f16a4112-3055-4b04-b8f7-4df6b3614620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76675
0929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.766750929
Directory /workspace/34.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2914574971
Short name T1975
Test name
Test status
Simulation time 304854142 ps
CPU time 1.12 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:28 PM PDT 24
Peak memory 207484 kb
Host smart-f1a6d0a1-a727-4876-9aba-7a70a2109be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29145
74971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2914574971
Directory /workspace/34.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1041787101
Short name T1076
Test name
Test status
Simulation time 186307009 ps
CPU time 0.93 seconds
Started Aug 11 07:14:31 PM PDT 24
Finished Aug 11 07:14:32 PM PDT 24
Peak memory 207508 kb
Host smart-511cd4c4-ea19-495b-b578-7a7179bf9ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10417
87101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1041787101
Directory /workspace/34.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3274668343
Short name T271
Test name
Test status
Simulation time 140651109 ps
CPU time 0.85 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:29 PM PDT 24
Peak memory 207520 kb
Host smart-86a7d4b2-e738-4b7f-86f8-7abffa05324a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32746
68343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3274668343
Directory /workspace/34.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/34.usbdev_rx_full.3056423864
Short name T1940
Test name
Test status
Simulation time 379796948 ps
CPU time 1.29 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 207492 kb
Host smart-b8d40348-23e5-4646-9923-8a3f7d62d070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564
23864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.3056423864
Directory /workspace/34.usbdev_rx_full/latest


Test location /workspace/coverage/default/34.usbdev_setup_stage.4012497062
Short name T2162
Test name
Test status
Simulation time 151525479 ps
CPU time 0.87 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 207500 kb
Host smart-c330a360-a306-4af0-b58c-531b92fed6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40124
97062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.4012497062
Directory /workspace/34.usbdev_setup_stage/latest


Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1245738528
Short name T2833
Test name
Test status
Simulation time 162163973 ps
CPU time 0.85 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:27 PM PDT 24
Peak memory 207552 kb
Host smart-5144d168-e4d9-4160-af08-bb148d3b0cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12457
38528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1245738528
Directory /workspace/34.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/34.usbdev_smoke.1192823772
Short name T3100
Test name
Test status
Simulation time 274256038 ps
CPU time 1 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207584 kb
Host smart-2955bf1a-6061-4fd2-930d-1bf37ab26d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
23772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1192823772
Directory /workspace/34.usbdev_smoke/latest


Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2331694322
Short name T2540
Test name
Test status
Simulation time 3362001904 ps
CPU time 34.49 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:15:02 PM PDT 24
Peak memory 224132 kb
Host smart-addc969e-ee74-4d28-935c-04cb58e406dc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2331694322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2331694322
Directory /workspace/34.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1490249919
Short name T3194
Test name
Test status
Simulation time 195827129 ps
CPU time 0.87 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207592 kb
Host smart-e9da2062-9b75-46c8-9839-e7415eac39bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14902
49919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1490249919
Directory /workspace/34.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/34.usbdev_stall_trans.1052085938
Short name T2591
Test name
Test status
Simulation time 165401916 ps
CPU time 0.87 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 207544 kb
Host smart-e5c827a7-8d7a-4c0b-a942-16d47fd57982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520
85938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1052085938
Directory /workspace/34.usbdev_stall_trans/latest


Test location /workspace/coverage/default/34.usbdev_stream_len_max.3765062071
Short name T2334
Test name
Test status
Simulation time 572546557 ps
CPU time 1.72 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207560 kb
Host smart-59903535-0577-46fd-ae34-3d2542884223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37650
62071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.3765062071
Directory /workspace/34.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/34.usbdev_streaming_out.3833546910
Short name T3072
Test name
Test status
Simulation time 4428909190 ps
CPU time 44.45 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:15:13 PM PDT 24
Peak memory 217736 kb
Host smart-e3ab104a-11e2-44b2-a82b-cf720239faf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38335
46910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3833546910
Directory /workspace/34.usbdev_streaming_out/latest


Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.666025396
Short name T1797
Test name
Test status
Simulation time 844112466 ps
CPU time 19.69 seconds
Started Aug 11 07:14:26 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207680 kb
Host smart-04877486-f104-41f1-b216-f955988391b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666025396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_host
_handshake.666025396
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/34.usbdev_tx_rx_disruption.4276604437
Short name T167
Test name
Test status
Simulation time 523373418 ps
CPU time 1.56 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207528 kb
Host smart-f4b60517-68f9-4391-84c1-27c81980de84
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276604437 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.usbdev_tx_rx_disruption.4276604437
Directory /workspace/34.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/340.usbdev_tx_rx_disruption.2234197770
Short name T3168
Test name
Test status
Simulation time 680382086 ps
CPU time 1.71 seconds
Started Aug 11 07:17:54 PM PDT 24
Finished Aug 11 07:17:56 PM PDT 24
Peak memory 206572 kb
Host smart-b03a361a-d20d-454e-a5d7-728f1ed11a6b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234197770 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 340.usbdev_tx_rx_disruption.2234197770
Directory /workspace/340.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/341.usbdev_tx_rx_disruption.339603263
Short name T2873
Test name
Test status
Simulation time 589577874 ps
CPU time 1.68 seconds
Started Aug 11 07:17:46 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207552 kb
Host smart-caef3042-4ca9-4442-a754-4a6ea48f2074
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339603263 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 341.usbdev_tx_rx_disruption.339603263
Directory /workspace/341.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/342.usbdev_tx_rx_disruption.1146136902
Short name T1411
Test name
Test status
Simulation time 427931099 ps
CPU time 1.33 seconds
Started Aug 11 07:17:40 PM PDT 24
Finished Aug 11 07:17:42 PM PDT 24
Peak memory 207456 kb
Host smart-6a3907f2-ac7e-46a2-b52a-0ab67e0b3e34
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146136902 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 342.usbdev_tx_rx_disruption.1146136902
Directory /workspace/342.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/343.usbdev_tx_rx_disruption.481358419
Short name T3416
Test name
Test status
Simulation time 613508584 ps
CPU time 1.71 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:36 PM PDT 24
Peak memory 207596 kb
Host smart-03007d83-cd40-43a8-a16e-e6c9aad05534
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481358419 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 343.usbdev_tx_rx_disruption.481358419
Directory /workspace/343.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/344.usbdev_tx_rx_disruption.2283235474
Short name T1984
Test name
Test status
Simulation time 593509461 ps
CPU time 1.55 seconds
Started Aug 11 07:17:41 PM PDT 24
Finished Aug 11 07:17:43 PM PDT 24
Peak memory 207776 kb
Host smart-eab194c1-4bc8-4f75-ae62-56a04418f7e7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283235474 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 344.usbdev_tx_rx_disruption.2283235474
Directory /workspace/344.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/345.usbdev_tx_rx_disruption.2277838182
Short name T2937
Test name
Test status
Simulation time 523768200 ps
CPU time 1.5 seconds
Started Aug 11 07:17:56 PM PDT 24
Finished Aug 11 07:18:01 PM PDT 24
Peak memory 207560 kb
Host smart-1a0be96b-15eb-49b3-a433-86a0f375a29d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277838182 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 345.usbdev_tx_rx_disruption.2277838182
Directory /workspace/345.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/346.usbdev_tx_rx_disruption.2892705857
Short name T3521
Test name
Test status
Simulation time 553069782 ps
CPU time 1.54 seconds
Started Aug 11 07:17:57 PM PDT 24
Finished Aug 11 07:17:59 PM PDT 24
Peak memory 207544 kb
Host smart-62b090c0-693a-4d3b-a54f-6b6d21457202
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892705857 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 346.usbdev_tx_rx_disruption.2892705857
Directory /workspace/346.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/347.usbdev_tx_rx_disruption.2372572800
Short name T2099
Test name
Test status
Simulation time 524154672 ps
CPU time 1.6 seconds
Started Aug 11 07:17:59 PM PDT 24
Finished Aug 11 07:18:01 PM PDT 24
Peak memory 207576 kb
Host smart-2330454d-4ad9-456a-935e-0bacd4c5b26d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372572800 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 347.usbdev_tx_rx_disruption.2372572800
Directory /workspace/347.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/348.usbdev_tx_rx_disruption.1442877943
Short name T168
Test name
Test status
Simulation time 516400065 ps
CPU time 1.6 seconds
Started Aug 11 07:18:09 PM PDT 24
Finished Aug 11 07:18:11 PM PDT 24
Peak memory 207532 kb
Host smart-08533e13-2a62-440b-8930-67131b7de70d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442877943 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 348.usbdev_tx_rx_disruption.1442877943
Directory /workspace/348.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/349.usbdev_tx_rx_disruption.1031612902
Short name T3328
Test name
Test status
Simulation time 467431079 ps
CPU time 1.46 seconds
Started Aug 11 07:17:49 PM PDT 24
Finished Aug 11 07:17:51 PM PDT 24
Peak memory 207496 kb
Host smart-8d86ec2f-0c6f-40a8-9e14-fd95c293397a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031612902 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 349.usbdev_tx_rx_disruption.1031612902
Directory /workspace/349.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/35.usbdev_alert_test.759185002
Short name T1602
Test name
Test status
Simulation time 37325287 ps
CPU time 0.75 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207580 kb
Host smart-7011d251-7af1-434b-b29a-fa191a38aa63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=759185002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.759185002
Directory /workspace/35.usbdev_alert_test/latest


Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3016292876
Short name T1888
Test name
Test status
Simulation time 9312380681 ps
CPU time 14.3 seconds
Started Aug 11 07:14:27 PM PDT 24
Finished Aug 11 07:14:42 PM PDT 24
Peak memory 207816 kb
Host smart-6662ce41-fa27-4e0b-a2b7-b5f528a25939
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016292876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.3016292876
Directory /workspace/35.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3522270500
Short name T3208
Test name
Test status
Simulation time 19282927937 ps
CPU time 20.51 seconds
Started Aug 11 07:14:31 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207748 kb
Host smart-2bae06a0-56d5-4afc-9fe6-73053ddca818
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522270500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3522270500
Directory /workspace/35.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2455149031
Short name T11
Test name
Test status
Simulation time 25587741615 ps
CPU time 35.44 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:15:11 PM PDT 24
Peak memory 216060 kb
Host smart-360a7acc-fed5-439d-a140-ed0daf589a7a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455149031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.2455149031
Directory /workspace/35.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/35.usbdev_av_buffer.804675479
Short name T816
Test name
Test status
Simulation time 181609611 ps
CPU time 0.93 seconds
Started Aug 11 07:14:39 PM PDT 24
Finished Aug 11 07:14:40 PM PDT 24
Peak memory 207552 kb
Host smart-e788fb4a-5cce-42b4-b833-8b1296de22fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80467
5479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.804675479
Directory /workspace/35.usbdev_av_buffer/latest


Test location /workspace/coverage/default/35.usbdev_bitstuff_err.4210200352
Short name T870
Test name
Test status
Simulation time 208212374 ps
CPU time 0.9 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 207720 kb
Host smart-6fc79844-733c-4b6b-9090-2b92141a99f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42102
00352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.4210200352
Directory /workspace/35.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1378281852
Short name T2306
Test name
Test status
Simulation time 413156119 ps
CPU time 1.54 seconds
Started Aug 11 07:14:38 PM PDT 24
Finished Aug 11 07:14:39 PM PDT 24
Peak memory 207480 kb
Host smart-281b938a-04dd-434f-961a-49332907fc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13782
81852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1378281852
Directory /workspace/35.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1306308432
Short name T61
Test name
Test status
Simulation time 254387818 ps
CPU time 0.96 seconds
Started Aug 11 07:14:45 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207584 kb
Host smart-f1a66f50-512b-401c-8bec-5c7772cf97a6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1306308432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1306308432
Directory /workspace/35.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/35.usbdev_device_address.4249201509
Short name T1263
Test name
Test status
Simulation time 19239953989 ps
CPU time 38.73 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:15:12 PM PDT 24
Peak memory 207856 kb
Host smart-135ef81b-35e6-4f12-87a6-be45de40d068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42492
01509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.4249201509
Directory /workspace/35.usbdev_device_address/latest


Test location /workspace/coverage/default/35.usbdev_device_timeout.2517228215
Short name T3383
Test name
Test status
Simulation time 4322252874 ps
CPU time 28.88 seconds
Started Aug 11 07:14:41 PM PDT 24
Finished Aug 11 07:15:10 PM PDT 24
Peak memory 207860 kb
Host smart-d0104748-7e79-4842-8224-6a3163f82bc3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517228215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.2517228215
Directory /workspace/35.usbdev_device_timeout/latest


Test location /workspace/coverage/default/35.usbdev_disable_endpoint.796614968
Short name T1914
Test name
Test status
Simulation time 910108470 ps
CPU time 1.86 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207516 kb
Host smart-db57d63c-e44f-45a8-88a3-5498ef9685b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79661
4968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.796614968
Directory /workspace/35.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/35.usbdev_disconnected.1380262435
Short name T3497
Test name
Test status
Simulation time 145687741 ps
CPU time 0.84 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:28 PM PDT 24
Peak memory 207536 kb
Host smart-a1b046ea-22d1-471c-a3a2-3e19d510349b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13802
62435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1380262435
Directory /workspace/35.usbdev_disconnected/latest


Test location /workspace/coverage/default/35.usbdev_enable.2612499739
Short name T2139
Test name
Test status
Simulation time 33014041 ps
CPU time 0.71 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 207708 kb
Host smart-a2422af5-4e5c-492f-91fa-359f98c4e88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26124
99739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2612499739
Directory /workspace/35.usbdev_enable/latest


Test location /workspace/coverage/default/35.usbdev_endpoint_access.410927434
Short name T803
Test name
Test status
Simulation time 962785239 ps
CPU time 2.38 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207784 kb
Host smart-d834a28c-3e80-45e3-b84e-d60235a8836e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41092
7434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.410927434
Directory /workspace/35.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/35.usbdev_fifo_rst.3880977020
Short name T1280
Test name
Test status
Simulation time 348916818 ps
CPU time 2.52 seconds
Started Aug 11 07:14:28 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207656 kb
Host smart-c813378c-2bf6-4099-9178-795896d37663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
77020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3880977020
Directory /workspace/35.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/35.usbdev_in_iso.1684281710
Short name T1496
Test name
Test status
Simulation time 177714376 ps
CPU time 1.05 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:33 PM PDT 24
Peak memory 215940 kb
Host smart-65877d77-8b61-4445-91d5-5f47011ee23d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1684281710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1684281710
Directory /workspace/35.usbdev_in_iso/latest


Test location /workspace/coverage/default/35.usbdev_in_stall.3410256708
Short name T1050
Test name
Test status
Simulation time 163673172 ps
CPU time 0.84 seconds
Started Aug 11 07:14:29 PM PDT 24
Finished Aug 11 07:14:30 PM PDT 24
Peak memory 207532 kb
Host smart-591696a7-d191-430d-a7f7-25e40165fac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34102
56708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3410256708
Directory /workspace/35.usbdev_in_stall/latest


Test location /workspace/coverage/default/35.usbdev_in_trans.2331928421
Short name T954
Test name
Test status
Simulation time 184866887 ps
CPU time 0.96 seconds
Started Aug 11 07:14:31 PM PDT 24
Finished Aug 11 07:14:32 PM PDT 24
Peak memory 207528 kb
Host smart-b68517ea-e33b-4390-ac76-13f8379476a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23319
28421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2331928421
Directory /workspace/35.usbdev_in_trans/latest


Test location /workspace/coverage/default/35.usbdev_invalid_sync.1219297186
Short name T2005
Test name
Test status
Simulation time 3686491649 ps
CPU time 36.91 seconds
Started Aug 11 07:14:31 PM PDT 24
Finished Aug 11 07:15:08 PM PDT 24
Peak memory 224212 kb
Host smart-2ee49467-2597-4f11-b9f6-21f98254b301
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1219297186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.1219297186
Directory /workspace/35.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/35.usbdev_iso_retraction.2870603919
Short name T1230
Test name
Test status
Simulation time 13283392825 ps
CPU time 90.72 seconds
Started Aug 11 07:14:38 PM PDT 24
Finished Aug 11 07:16:09 PM PDT 24
Peak memory 207828 kb
Host smart-f0f022ab-d748-40ab-9659-b8b99eee69e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2870603919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.2870603919
Directory /workspace/35.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/35.usbdev_link_in_err.3884904374
Short name T2379
Test name
Test status
Simulation time 189476962 ps
CPU time 0.95 seconds
Started Aug 11 07:14:41 PM PDT 24
Finished Aug 11 07:14:42 PM PDT 24
Peak memory 207612 kb
Host smart-eaa35149-2cb6-42b7-9026-74052a1b577e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38849
04374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3884904374
Directory /workspace/35.usbdev_link_in_err/latest


Test location /workspace/coverage/default/35.usbdev_link_resume.3786796623
Short name T1005
Test name
Test status
Simulation time 9188395147 ps
CPU time 12.95 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:47 PM PDT 24
Peak memory 207832 kb
Host smart-9eb10512-2c27-4ace-9ce2-c4e5abc0f901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37867
96623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.3786796623
Directory /workspace/35.usbdev_link_resume/latest


Test location /workspace/coverage/default/35.usbdev_link_suspend.3195841540
Short name T2337
Test name
Test status
Simulation time 10898068576 ps
CPU time 15.73 seconds
Started Aug 11 07:14:36 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207820 kb
Host smart-af7135e9-71bc-4b91-8fe7-9162cb929c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31958
41540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3195841540
Directory /workspace/35.usbdev_link_suspend/latest


Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2527509598
Short name T937
Test name
Test status
Simulation time 4502179249 ps
CPU time 44.64 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 218472 kb
Host smart-d0a59d07-bca8-42fc-ac66-cb38738b3b33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2527509598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2527509598
Directory /workspace/35.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2799291074
Short name T2174
Test name
Test status
Simulation time 2660375676 ps
CPU time 19.95 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 207932 kb
Host smart-f78fd765-a216-4c83-9538-26fdbe3e5988
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2799291074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2799291074
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.647516378
Short name T2868
Test name
Test status
Simulation time 288106484 ps
CPU time 1.08 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207520 kb
Host smart-2640d25c-0a27-4059-a1f7-5c207dd8f60a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=647516378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.647516378
Directory /workspace/35.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.4246288821
Short name T2863
Test name
Test status
Simulation time 223884758 ps
CPU time 1 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207472 kb
Host smart-f8ce452a-2bff-4096-b61a-e27262781270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
88821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.4246288821
Directory /workspace/35.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1123589638
Short name T1098
Test name
Test status
Simulation time 3992184783 ps
CPU time 39.72 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:15:13 PM PDT 24
Peak memory 216060 kb
Host smart-e144cae1-6472-41c1-b0cd-f9e7ed8c9bfb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1123589638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1123589638
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.36772149
Short name T1897
Test name
Test status
Simulation time 156955756 ps
CPU time 0.91 seconds
Started Aug 11 07:14:46 PM PDT 24
Finished Aug 11 07:14:47 PM PDT 24
Peak memory 207560 kb
Host smart-433dd627-9038-4623-9de0-eb361bf19f43
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=36772149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.36772149
Directory /workspace/35.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3905737838
Short name T3282
Test name
Test status
Simulation time 142149069 ps
CPU time 0.81 seconds
Started Aug 11 07:14:44 PM PDT 24
Finished Aug 11 07:14:45 PM PDT 24
Peak memory 207544 kb
Host smart-30717a58-cb84-4cf8-b031-f3b132331dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39057
37838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3905737838
Directory /workspace/35.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_nak_trans.497251517
Short name T156
Test name
Test status
Simulation time 178715053 ps
CPU time 0.91 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 207484 kb
Host smart-bfc8a58f-da0f-4b40-823e-1f5763dcaae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49725
1517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.497251517
Directory /workspace/35.usbdev_nak_trans/latest


Test location /workspace/coverage/default/35.usbdev_out_iso.44443101
Short name T992
Test name
Test status
Simulation time 166446343 ps
CPU time 0.86 seconds
Started Aug 11 07:14:45 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207548 kb
Host smart-c530944a-e3d5-4fff-9dfa-2f61483da64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44443
101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.44443101
Directory /workspace/35.usbdev_out_iso/latest


Test location /workspace/coverage/default/35.usbdev_out_stall.1482918333
Short name T677
Test name
Test status
Simulation time 221853276 ps
CPU time 0.92 seconds
Started Aug 11 07:14:42 PM PDT 24
Finished Aug 11 07:14:43 PM PDT 24
Peak memory 207524 kb
Host smart-5c3065ac-03e9-4407-b394-63b6c10ce7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14829
18333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1482918333
Directory /workspace/35.usbdev_out_stall/latest


Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3204557795
Short name T1566
Test name
Test status
Simulation time 191538633 ps
CPU time 0.98 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207484 kb
Host smart-6a1c0fde-d4cc-4b87-93b1-948b51f35829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32045
57795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3204557795
Directory /workspace/35.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/35.usbdev_pending_in_trans.515144283
Short name T3471
Test name
Test status
Simulation time 162768629 ps
CPU time 0.88 seconds
Started Aug 11 07:14:33 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 207520 kb
Host smart-02e893c9-f4ae-4471-8837-3e666bc820c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51514
4283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.515144283
Directory /workspace/35.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1982451145
Short name T571
Test name
Test status
Simulation time 207374470 ps
CPU time 0.96 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207572 kb
Host smart-c8621c7c-a812-4abd-beb5-b1c2d5736ae1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1982451145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1982451145
Directory /workspace/35.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3092375034
Short name T2599
Test name
Test status
Simulation time 150149101 ps
CPU time 0.8 seconds
Started Aug 11 07:14:43 PM PDT 24
Finished Aug 11 07:14:44 PM PDT 24
Peak memory 207520 kb
Host smart-bee7468c-d030-47a1-acdb-54d8ca30d57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30923
75034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3092375034
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3280824933
Short name T2783
Test name
Test status
Simulation time 52742742 ps
CPU time 0.7 seconds
Started Aug 11 07:14:31 PM PDT 24
Finished Aug 11 07:14:32 PM PDT 24
Peak memory 207512 kb
Host smart-03a6a27a-5368-4104-bbee-1f37ceb7c674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32808
24933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3280824933
Directory /workspace/35.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1722603750
Short name T297
Test name
Test status
Simulation time 14822524647 ps
CPU time 38.62 seconds
Started Aug 11 07:14:36 PM PDT 24
Finished Aug 11 07:15:15 PM PDT 24
Peak memory 216056 kb
Host smart-0efced2a-2528-4108-8d79-f9b19249b5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17226
03750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1722603750
Directory /workspace/35.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/35.usbdev_pkt_received.283944254
Short name T2354
Test name
Test status
Simulation time 201491350 ps
CPU time 0.95 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:14:37 PM PDT 24
Peak memory 207572 kb
Host smart-d67cf9f4-b2ec-44c0-a9f9-b0fae3e406bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28394
4254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.283944254
Directory /workspace/35.usbdev_pkt_received/latest


Test location /workspace/coverage/default/35.usbdev_pkt_sent.993740293
Short name T1142
Test name
Test status
Simulation time 168245160 ps
CPU time 0.87 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207576 kb
Host smart-22a3fc7b-7ce4-402e-b437-05d04c82f717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99374
0293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.993740293
Directory /workspace/35.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.3323650971
Short name T596
Test name
Test status
Simulation time 192265951 ps
CPU time 0.9 seconds
Started Aug 11 07:14:44 PM PDT 24
Finished Aug 11 07:14:45 PM PDT 24
Peak memory 207556 kb
Host smart-4bdb6097-f651-4ef6-ad18-577277603c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33236
50971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.3323650971
Directory /workspace/35.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3681131732
Short name T2224
Test name
Test status
Simulation time 174488018 ps
CPU time 0.88 seconds
Started Aug 11 07:14:41 PM PDT 24
Finished Aug 11 07:14:41 PM PDT 24
Peak memory 207552 kb
Host smart-25dfe92c-926d-4d27-aa0c-26b51a2dd730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36811
31732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3681131732
Directory /workspace/35.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2664527507
Short name T1259
Test name
Test status
Simulation time 135754637 ps
CPU time 0.85 seconds
Started Aug 11 07:14:30 PM PDT 24
Finished Aug 11 07:14:31 PM PDT 24
Peak memory 207512 kb
Host smart-720a730d-f44a-49df-90a3-7a921f280622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26645
27507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2664527507
Directory /workspace/35.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/35.usbdev_rx_full.1797548384
Short name T1949
Test name
Test status
Simulation time 245426569 ps
CPU time 1.11 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207548 kb
Host smart-98d5bc8e-1151-4ee9-9751-ca7cc06558f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17975
48384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.1797548384
Directory /workspace/35.usbdev_rx_full/latest


Test location /workspace/coverage/default/35.usbdev_setup_stage.810878585
Short name T809
Test name
Test status
Simulation time 169606544 ps
CPU time 0.86 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 207540 kb
Host smart-c9e6430e-6730-4dd7-923a-f57beeea444b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81087
8585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.810878585
Directory /workspace/35.usbdev_setup_stage/latest


Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2368493865
Short name T2231
Test name
Test status
Simulation time 178824436 ps
CPU time 0.85 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:35 PM PDT 24
Peak memory 207508 kb
Host smart-6cede32d-6a6a-4531-84d5-0c2c27e2a7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23684
93865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2368493865
Directory /workspace/35.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/35.usbdev_smoke.3929934836
Short name T1901
Test name
Test status
Simulation time 210861383 ps
CPU time 0.99 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 207568 kb
Host smart-18b32fd6-c634-4d95-96ef-290c1b84070c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39299
34836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3929934836
Directory /workspace/35.usbdev_smoke/latest


Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3882807297
Short name T3532
Test name
Test status
Simulation time 2193085563 ps
CPU time 17.27 seconds
Started Aug 11 07:14:42 PM PDT 24
Finished Aug 11 07:15:00 PM PDT 24
Peak memory 217684 kb
Host smart-de61ca0f-f766-494f-8901-2db279b664aa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3882807297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3882807297
Directory /workspace/35.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3433566518
Short name T1456
Test name
Test status
Simulation time 182346502 ps
CPU time 0.89 seconds
Started Aug 11 07:14:32 PM PDT 24
Finished Aug 11 07:14:34 PM PDT 24
Peak memory 207548 kb
Host smart-bc925f70-01f0-4632-804c-a502128c61df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34335
66518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3433566518
Directory /workspace/35.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/35.usbdev_stall_trans.1936709102
Short name T2056
Test name
Test status
Simulation time 180493256 ps
CPU time 0.9 seconds
Started Aug 11 07:14:48 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207548 kb
Host smart-92ccc412-0cc0-4baf-8011-146b4ad62b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19367
09102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1936709102
Directory /workspace/35.usbdev_stall_trans/latest


Test location /workspace/coverage/default/35.usbdev_stream_len_max.3133878412
Short name T2206
Test name
Test status
Simulation time 769939278 ps
CPU time 2.1 seconds
Started Aug 11 07:14:36 PM PDT 24
Finished Aug 11 07:14:38 PM PDT 24
Peak memory 207524 kb
Host smart-045cf937-c682-49bf-8666-476fa2684ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31338
78412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.3133878412
Directory /workspace/35.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/35.usbdev_streaming_out.178183181
Short name T1578
Test name
Test status
Simulation time 3527949367 ps
CPU time 32.85 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:15:08 PM PDT 24
Peak memory 216128 kb
Host smart-1b159e26-7666-433e-bf88-7cb23c8c86b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17818
3181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.178183181
Directory /workspace/35.usbdev_streaming_out/latest


Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.2429223682
Short name T1856
Test name
Test status
Simulation time 596328351 ps
CPU time 5.03 seconds
Started Aug 11 07:14:37 PM PDT 24
Finished Aug 11 07:14:43 PM PDT 24
Peak memory 207664 kb
Host smart-b053907e-a7a9-4ea0-8b5a-031e82ea6995
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429223682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.2429223682
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/35.usbdev_tx_rx_disruption.1790373437
Short name T3077
Test name
Test status
Simulation time 548518977 ps
CPU time 1.62 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207544 kb
Host smart-86f9f82c-e58d-45cb-9953-5babcc8c23a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790373437 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.usbdev_tx_rx_disruption.1790373437
Directory /workspace/35.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/350.usbdev_tx_rx_disruption.3511914048
Short name T97
Test name
Test status
Simulation time 616589233 ps
CPU time 1.63 seconds
Started Aug 11 07:17:53 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207540 kb
Host smart-1f5a5da3-9299-4710-b687-f9bc4a3098f0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511914048 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 350.usbdev_tx_rx_disruption.3511914048
Directory /workspace/350.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/351.usbdev_tx_rx_disruption.2107035935
Short name T1003
Test name
Test status
Simulation time 581363242 ps
CPU time 1.7 seconds
Started Aug 11 07:17:47 PM PDT 24
Finished Aug 11 07:17:49 PM PDT 24
Peak memory 207540 kb
Host smart-a3467d7e-e97a-44e4-b992-c233a182660e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107035935 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 351.usbdev_tx_rx_disruption.2107035935
Directory /workspace/351.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/352.usbdev_tx_rx_disruption.637324009
Short name T257
Test name
Test status
Simulation time 629561927 ps
CPU time 1.76 seconds
Started Aug 11 07:17:52 PM PDT 24
Finished Aug 11 07:17:54 PM PDT 24
Peak memory 207508 kb
Host smart-f55dda7c-37f2-43bc-872a-400408e323bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637324009 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 352.usbdev_tx_rx_disruption.637324009
Directory /workspace/352.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/353.usbdev_tx_rx_disruption.3595004286
Short name T1358
Test name
Test status
Simulation time 553612035 ps
CPU time 1.61 seconds
Started Aug 11 07:17:47 PM PDT 24
Finished Aug 11 07:17:49 PM PDT 24
Peak memory 207564 kb
Host smart-1aeb8107-4096-4ec7-a0e1-a0cbb5b785f2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595004286 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 353.usbdev_tx_rx_disruption.3595004286
Directory /workspace/353.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/354.usbdev_tx_rx_disruption.3578981085
Short name T834
Test name
Test status
Simulation time 628101895 ps
CPU time 1.66 seconds
Started Aug 11 07:18:03 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207552 kb
Host smart-11d2b05d-bba7-4725-a252-e6b994b72d76
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578981085 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 354.usbdev_tx_rx_disruption.3578981085
Directory /workspace/354.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/355.usbdev_tx_rx_disruption.3255485531
Short name T3431
Test name
Test status
Simulation time 541587204 ps
CPU time 1.53 seconds
Started Aug 11 07:17:45 PM PDT 24
Finished Aug 11 07:17:47 PM PDT 24
Peak memory 207568 kb
Host smart-13304268-944b-4f1a-a732-c33c2db6e743
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255485531 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 355.usbdev_tx_rx_disruption.3255485531
Directory /workspace/355.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/356.usbdev_tx_rx_disruption.3161306644
Short name T3566
Test name
Test status
Simulation time 494883184 ps
CPU time 1.62 seconds
Started Aug 11 07:17:58 PM PDT 24
Finished Aug 11 07:18:00 PM PDT 24
Peak memory 207476 kb
Host smart-cf16681b-f060-40da-8501-33f6747c34a7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161306644 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 356.usbdev_tx_rx_disruption.3161306644
Directory /workspace/356.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/357.usbdev_tx_rx_disruption.613672823
Short name T2692
Test name
Test status
Simulation time 507558148 ps
CPU time 1.63 seconds
Started Aug 11 07:17:39 PM PDT 24
Finished Aug 11 07:17:41 PM PDT 24
Peak memory 207572 kb
Host smart-4e86b4f1-d662-4332-8b0e-41f4973ebe1b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613672823 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 357.usbdev_tx_rx_disruption.613672823
Directory /workspace/357.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/358.usbdev_tx_rx_disruption.856514338
Short name T652
Test name
Test status
Simulation time 510795188 ps
CPU time 1.54 seconds
Started Aug 11 07:17:44 PM PDT 24
Finished Aug 11 07:17:46 PM PDT 24
Peak memory 207552 kb
Host smart-e726f40e-75db-494e-b532-045813c972bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856514338 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 358.usbdev_tx_rx_disruption.856514338
Directory /workspace/358.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/359.usbdev_tx_rx_disruption.1391685881
Short name T2425
Test name
Test status
Simulation time 596289425 ps
CPU time 1.64 seconds
Started Aug 11 07:17:54 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207516 kb
Host smart-8f54324b-2955-46d6-9237-9709d6779a31
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391685881 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 359.usbdev_tx_rx_disruption.1391685881
Directory /workspace/359.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/36.usbdev_alert_test.767216821
Short name T804
Test name
Test status
Simulation time 34495146 ps
CPU time 0.66 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:14:51 PM PDT 24
Peak memory 207552 kb
Host smart-9b24163a-5b6e-4497-a907-6e50147412dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=767216821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.767216821
Directory /workspace/36.usbdev_alert_test/latest


Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.472105026
Short name T2436
Test name
Test status
Simulation time 10710304802 ps
CPU time 13.09 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:15:04 PM PDT 24
Peak memory 207820 kb
Host smart-4322e067-e739-4890-aef9-a5c14419df94
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472105026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_ao
n_wake_disconnect.472105026
Directory /workspace/36.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.127557478
Short name T15
Test name
Test status
Simulation time 14957178804 ps
CPU time 17.41 seconds
Started Aug 11 07:14:38 PM PDT 24
Finished Aug 11 07:14:55 PM PDT 24
Peak memory 215976 kb
Host smart-c4360ece-6177-4601-9a6d-5b04895098e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=127557478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.127557478
Directory /workspace/36.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2402118346
Short name T688
Test name
Test status
Simulation time 25376126981 ps
CPU time 30.19 seconds
Started Aug 11 07:14:30 PM PDT 24
Finished Aug 11 07:15:00 PM PDT 24
Peak memory 216024 kb
Host smart-df05d724-bab9-4c4b-8307-ccec2bf8bd91
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402118346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.2402118346
Directory /workspace/36.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/36.usbdev_av_buffer.618358532
Short name T854
Test name
Test status
Simulation time 202356091 ps
CPU time 0.97 seconds
Started Aug 11 07:14:36 PM PDT 24
Finished Aug 11 07:14:37 PM PDT 24
Peak memory 207552 kb
Host smart-9e8cfe23-bafd-44ee-8523-c25b555dd2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61835
8532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.618358532
Directory /workspace/36.usbdev_av_buffer/latest


Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3398748778
Short name T1923
Test name
Test status
Simulation time 153686860 ps
CPU time 0.82 seconds
Started Aug 11 07:14:40 PM PDT 24
Finished Aug 11 07:14:41 PM PDT 24
Peak memory 207456 kb
Host smart-bc4e4d35-4e6f-4477-a941-0247059e950c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33987
48778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3398748778
Directory /workspace/36.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2782683937
Short name T1986
Test name
Test status
Simulation time 176112122 ps
CPU time 0.89 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207544 kb
Host smart-b626de73-979c-460d-822b-1378a4f73d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27826
83937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2782683937
Directory /workspace/36.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1013174979
Short name T1694
Test name
Test status
Simulation time 1111694518 ps
CPU time 2.8 seconds
Started Aug 11 07:14:44 PM PDT 24
Finished Aug 11 07:14:47 PM PDT 24
Peak memory 207760 kb
Host smart-a29fa789-83ce-4f53-b4a7-8b5f8e4e9854
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1013174979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1013174979
Directory /workspace/36.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/36.usbdev_device_address.4219226903
Short name T2286
Test name
Test status
Simulation time 49926952603 ps
CPU time 79.59 seconds
Started Aug 11 07:14:37 PM PDT 24
Finished Aug 11 07:15:56 PM PDT 24
Peak memory 207828 kb
Host smart-ba9010d6-9cb1-4da7-aec2-b4d1373781e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42192
26903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.4219226903
Directory /workspace/36.usbdev_device_address/latest


Test location /workspace/coverage/default/36.usbdev_device_timeout.3621574004
Short name T891
Test name
Test status
Simulation time 2474241816 ps
CPU time 21.5 seconds
Started Aug 11 07:14:44 PM PDT 24
Finished Aug 11 07:15:06 PM PDT 24
Peak memory 207812 kb
Host smart-fc04dcb0-540b-4377-900f-b5f86e3c66ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621574004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.3621574004
Directory /workspace/36.usbdev_device_timeout/latest


Test location /workspace/coverage/default/36.usbdev_disable_endpoint.3674040419
Short name T1025
Test name
Test status
Simulation time 915023033 ps
CPU time 2.15 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:37 PM PDT 24
Peak memory 207720 kb
Host smart-4a02dce6-2da7-45a8-b8b4-94852fd120f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
40419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.3674040419
Directory /workspace/36.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/36.usbdev_disconnected.1353499370
Short name T1499
Test name
Test status
Simulation time 153510093 ps
CPU time 0.82 seconds
Started Aug 11 07:14:42 PM PDT 24
Finished Aug 11 07:14:43 PM PDT 24
Peak memory 207524 kb
Host smart-bdeb7aea-d19b-43d1-b835-0d156a18877d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13534
99370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1353499370
Directory /workspace/36.usbdev_disconnected/latest


Test location /workspace/coverage/default/36.usbdev_enable.810187597
Short name T3407
Test name
Test status
Simulation time 51412772 ps
CPU time 0.75 seconds
Started Aug 11 07:14:44 PM PDT 24
Finished Aug 11 07:14:45 PM PDT 24
Peak memory 207524 kb
Host smart-70ce4117-843e-4a2f-a100-475d9f08371f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81018
7597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.810187597
Directory /workspace/36.usbdev_enable/latest


Test location /workspace/coverage/default/36.usbdev_endpoint_access.1903234727
Short name T3508
Test name
Test status
Simulation time 895074691 ps
CPU time 2.52 seconds
Started Aug 11 07:14:42 PM PDT 24
Finished Aug 11 07:14:44 PM PDT 24
Peak memory 207696 kb
Host smart-97aedb06-6aee-4cd2-aca8-3fe9aa18a9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19032
34727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.1903234727
Directory /workspace/36.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/36.usbdev_endpoint_types.3641406884
Short name T523
Test name
Test status
Simulation time 176070344 ps
CPU time 0.91 seconds
Started Aug 11 07:14:59 PM PDT 24
Finished Aug 11 07:15:00 PM PDT 24
Peak memory 207504 kb
Host smart-59f07df1-e5db-42f5-88d2-a22e476076d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3641406884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.3641406884
Directory /workspace/36.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/36.usbdev_fifo_rst.3950420690
Short name T580
Test name
Test status
Simulation time 278937992 ps
CPU time 1.59 seconds
Started Aug 11 07:14:48 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207724 kb
Host smart-ce7e974b-d65e-42f8-84e9-f3e788eaea84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39504
20690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3950420690
Directory /workspace/36.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/36.usbdev_in_iso.997540285
Short name T2562
Test name
Test status
Simulation time 180607857 ps
CPU time 0.97 seconds
Started Aug 11 07:14:41 PM PDT 24
Finished Aug 11 07:14:43 PM PDT 24
Peak memory 215956 kb
Host smart-17fdda00-838c-46af-98f2-7daf4f5d2ed7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=997540285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.997540285
Directory /workspace/36.usbdev_in_iso/latest


Test location /workspace/coverage/default/36.usbdev_in_stall.67724638
Short name T1820
Test name
Test status
Simulation time 156366921 ps
CPU time 0.85 seconds
Started Aug 11 07:14:48 PM PDT 24
Finished Aug 11 07:14:49 PM PDT 24
Peak memory 207460 kb
Host smart-5cfbc6d6-9b42-44a8-b2aa-dc6953b5b96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67724
638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.67724638
Directory /workspace/36.usbdev_in_stall/latest


Test location /workspace/coverage/default/36.usbdev_in_trans.3210971343
Short name T2588
Test name
Test status
Simulation time 213684726 ps
CPU time 0.96 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207492 kb
Host smart-6c97a739-e32e-404c-be5d-cba11571eb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
71343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3210971343
Directory /workspace/36.usbdev_in_trans/latest


Test location /workspace/coverage/default/36.usbdev_invalid_sync.1793649976
Short name T3439
Test name
Test status
Simulation time 3512679867 ps
CPU time 34.85 seconds
Started Aug 11 07:14:40 PM PDT 24
Finished Aug 11 07:15:15 PM PDT 24
Peak memory 224248 kb
Host smart-5b2a267b-8e77-4a4e-b95c-5f1f4a37ef65
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1793649976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.1793649976
Directory /workspace/36.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/36.usbdev_iso_retraction.2995078046
Short name T922
Test name
Test status
Simulation time 13009148870 ps
CPU time 91.93 seconds
Started Aug 11 07:14:38 PM PDT 24
Finished Aug 11 07:16:10 PM PDT 24
Peak memory 207832 kb
Host smart-9ca4484d-83d3-471a-8543-4cccdf1527a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2995078046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2995078046
Directory /workspace/36.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/36.usbdev_link_in_err.1025894705
Short name T1484
Test name
Test status
Simulation time 236841401 ps
CPU time 0.98 seconds
Started Aug 11 07:14:45 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207532 kb
Host smart-76bfff79-d7fe-48b9-ba33-8a2c23860b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10258
94705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1025894705
Directory /workspace/36.usbdev_link_in_err/latest


Test location /workspace/coverage/default/36.usbdev_link_resume.1203773968
Short name T2758
Test name
Test status
Simulation time 29084185789 ps
CPU time 48.86 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:15:39 PM PDT 24
Peak memory 216840 kb
Host smart-84da280a-fd92-46f2-be39-a20484d711e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12037
73968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1203773968
Directory /workspace/36.usbdev_link_resume/latest


Test location /workspace/coverage/default/36.usbdev_link_suspend.3096168892
Short name T112
Test name
Test status
Simulation time 3709347676 ps
CPU time 6.09 seconds
Started Aug 11 07:14:34 PM PDT 24
Finished Aug 11 07:14:40 PM PDT 24
Peak memory 215960 kb
Host smart-fe50d4e8-b1b3-4095-a2ef-241891ba4edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30961
68892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3096168892
Directory /workspace/36.usbdev_link_suspend/latest


Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1441735441
Short name T651
Test name
Test status
Simulation time 3710551273 ps
CPU time 37.92 seconds
Started Aug 11 07:15:05 PM PDT 24
Finished Aug 11 07:15:43 PM PDT 24
Peak memory 217764 kb
Host smart-1a5df000-f1a0-47bd-a499-321ff3a11c15
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1441735441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1441735441
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1225942664
Short name T1762
Test name
Test status
Simulation time 275728611 ps
CPU time 1.07 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207512 kb
Host smart-d93bf151-6bdb-4a69-a9fc-50da7ee6c348
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1225942664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1225942664
Directory /workspace/36.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1212374996
Short name T1268
Test name
Test status
Simulation time 190099570 ps
CPU time 0.91 seconds
Started Aug 11 07:14:37 PM PDT 24
Finished Aug 11 07:14:38 PM PDT 24
Peak memory 207588 kb
Host smart-e7da70d4-99e4-43f1-aad8-db918cf84458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12123
74996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1212374996
Directory /workspace/36.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.826626187
Short name T3530
Test name
Test status
Simulation time 2585268569 ps
CPU time 74.52 seconds
Started Aug 11 07:14:42 PM PDT 24
Finished Aug 11 07:15:57 PM PDT 24
Peak memory 216084 kb
Host smart-e6070697-1b00-42e2-91da-2c09c6f49c32
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=826626187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.826626187
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.428175582
Short name T1044
Test name
Test status
Simulation time 196187819 ps
CPU time 0.91 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207496 kb
Host smart-644b0401-739e-4437-bb61-9b78f6057564
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=428175582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.428175582
Directory /workspace/36.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3047930008
Short name T1090
Test name
Test status
Simulation time 154449279 ps
CPU time 0.87 seconds
Started Aug 11 07:14:41 PM PDT 24
Finished Aug 11 07:14:42 PM PDT 24
Peak memory 207532 kb
Host smart-63f4b451-fde3-4a22-8a13-7e015a61c96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30479
30008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3047930008
Directory /workspace/36.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_nak_trans.1453962885
Short name T1729
Test name
Test status
Simulation time 197697389 ps
CPU time 0.96 seconds
Started Aug 11 07:14:47 PM PDT 24
Finished Aug 11 07:14:48 PM PDT 24
Peak memory 207592 kb
Host smart-d45eba06-43f5-4216-800b-09df0fed0d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14539
62885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1453962885
Directory /workspace/36.usbdev_nak_trans/latest


Test location /workspace/coverage/default/36.usbdev_out_iso.939109544
Short name T680
Test name
Test status
Simulation time 202178231 ps
CPU time 0.96 seconds
Started Aug 11 07:14:40 PM PDT 24
Finished Aug 11 07:14:41 PM PDT 24
Peak memory 207580 kb
Host smart-1dd26e7c-26fc-454e-9810-4f7afe116911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93910
9544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.939109544
Directory /workspace/36.usbdev_out_iso/latest


Test location /workspace/coverage/default/36.usbdev_out_stall.3288551977
Short name T3057
Test name
Test status
Simulation time 178956246 ps
CPU time 0.9 seconds
Started Aug 11 07:14:46 PM PDT 24
Finished Aug 11 07:14:48 PM PDT 24
Peak memory 207516 kb
Host smart-3a7c71fc-2b3f-47ba-b90d-472961622a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32885
51977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3288551977
Directory /workspace/36.usbdev_out_stall/latest


Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3681090272
Short name T1215
Test name
Test status
Simulation time 172083400 ps
CPU time 0.87 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207568 kb
Host smart-e3649393-9425-4424-8842-460e3c44f79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36810
90272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3681090272
Directory /workspace/36.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/36.usbdev_pending_in_trans.681642576
Short name T202
Test name
Test status
Simulation time 158014022 ps
CPU time 0.86 seconds
Started Aug 11 07:14:42 PM PDT 24
Finished Aug 11 07:14:43 PM PDT 24
Peak memory 207564 kb
Host smart-2ba74115-251f-4ad8-8a8e-6f367b649bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68164
2576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.681642576
Directory /workspace/36.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2095479207
Short name T830
Test name
Test status
Simulation time 245816177 ps
CPU time 1.02 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207576 kb
Host smart-47cee8da-a11d-4b0d-a0fe-382aa1e57fc4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2095479207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2095479207
Directory /workspace/36.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3225916551
Short name T2180
Test name
Test status
Simulation time 195768452 ps
CPU time 0.89 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 207440 kb
Host smart-49ca7905-36dc-4ab9-ad09-feb9747707ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259
16551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3225916551
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.79436557
Short name T1689
Test name
Test status
Simulation time 38927026 ps
CPU time 0.69 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:14:51 PM PDT 24
Peak memory 207548 kb
Host smart-57a534e0-820f-4dac-b725-96a5ead87332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79436
557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.79436557
Directory /workspace/36.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1127284288
Short name T3455
Test name
Test status
Simulation time 14941505001 ps
CPU time 39.45 seconds
Started Aug 11 07:14:43 PM PDT 24
Finished Aug 11 07:15:23 PM PDT 24
Peak memory 216052 kb
Host smart-4fce9bf2-9c97-4a0b-ad00-69d10e96d0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11272
84288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1127284288
Directory /workspace/36.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/36.usbdev_pkt_received.1443878511
Short name T371
Test name
Test status
Simulation time 197662496 ps
CPU time 0.87 seconds
Started Aug 11 07:14:42 PM PDT 24
Finished Aug 11 07:14:43 PM PDT 24
Peak memory 207484 kb
Host smart-65e95a15-dc6f-431b-bafb-32787038c4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14438
78511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1443878511
Directory /workspace/36.usbdev_pkt_received/latest


Test location /workspace/coverage/default/36.usbdev_pkt_sent.3672505490
Short name T2840
Test name
Test status
Simulation time 250770710 ps
CPU time 1.08 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207536 kb
Host smart-a3b13f94-d956-443a-b2d5-fd0303d7e9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36725
05490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3672505490
Directory /workspace/36.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1298887843
Short name T3118
Test name
Test status
Simulation time 152406461 ps
CPU time 0.84 seconds
Started Aug 11 07:14:53 PM PDT 24
Finished Aug 11 07:14:55 PM PDT 24
Peak memory 207552 kb
Host smart-7d600338-874b-4a0b-911a-2f2faa80dea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12988
87843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1298887843
Directory /workspace/36.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.1270802690
Short name T2156
Test name
Test status
Simulation time 187551325 ps
CPU time 0.88 seconds
Started Aug 11 07:14:45 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207512 kb
Host smart-5271cf76-9095-492a-b6b1-9a0d2d7ff315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12708
02690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.1270802690
Directory /workspace/36.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3185199833
Short name T590
Test name
Test status
Simulation time 207474637 ps
CPU time 0.95 seconds
Started Aug 11 07:14:37 PM PDT 24
Finished Aug 11 07:14:38 PM PDT 24
Peak memory 207544 kb
Host smart-4f4f4e0f-db38-4154-bc33-39caa40dffa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31851
99833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3185199833
Directory /workspace/36.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/36.usbdev_rx_full.217147625
Short name T3201
Test name
Test status
Simulation time 399222523 ps
CPU time 1.25 seconds
Started Aug 11 07:14:48 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207552 kb
Host smart-ecd94aac-c80d-4452-85e9-d9864aa312f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21714
7625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.217147625
Directory /workspace/36.usbdev_rx_full/latest


Test location /workspace/coverage/default/36.usbdev_setup_stage.3260298502
Short name T897
Test name
Test status
Simulation time 161807848 ps
CPU time 0.85 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:14:36 PM PDT 24
Peak memory 207560 kb
Host smart-a2b644ee-8b54-496c-b42d-09c441562350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32602
98502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3260298502
Directory /workspace/36.usbdev_setup_stage/latest


Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2403378613
Short name T769
Test name
Test status
Simulation time 162026585 ps
CPU time 0.83 seconds
Started Aug 11 07:14:36 PM PDT 24
Finished Aug 11 07:14:37 PM PDT 24
Peak memory 207576 kb
Host smart-1ef28aad-f458-4b4b-b5e3-effa9ac42956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24033
78613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2403378613
Directory /workspace/36.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/36.usbdev_smoke.155673064
Short name T2049
Test name
Test status
Simulation time 246379477 ps
CPU time 1.1 seconds
Started Aug 11 07:14:45 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207572 kb
Host smart-62ded200-648f-431e-b9c3-dbf9bee759ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15567
3064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.155673064
Directory /workspace/36.usbdev_smoke/latest


Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2194069024
Short name T1100
Test name
Test status
Simulation time 2281388210 ps
CPU time 17.74 seconds
Started Aug 11 07:14:47 PM PDT 24
Finished Aug 11 07:15:05 PM PDT 24
Peak memory 224288 kb
Host smart-297f7dd3-8293-4ee6-95c8-ab8a331e182a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2194069024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2194069024
Directory /workspace/36.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.598358424
Short name T1473
Test name
Test status
Simulation time 231458261 ps
CPU time 0.94 seconds
Started Aug 11 07:14:37 PM PDT 24
Finished Aug 11 07:14:38 PM PDT 24
Peak memory 207540 kb
Host smart-81924de4-e36b-4ac6-afb0-511c396e37e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59835
8424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.598358424
Directory /workspace/36.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/36.usbdev_stall_trans.737994630
Short name T1634
Test name
Test status
Simulation time 184969826 ps
CPU time 0.89 seconds
Started Aug 11 07:14:45 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207612 kb
Host smart-71da4700-0b86-4fa7-b84c-d58700e8cbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73799
4630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.737994630
Directory /workspace/36.usbdev_stall_trans/latest


Test location /workspace/coverage/default/36.usbdev_stream_len_max.3395090716
Short name T2394
Test name
Test status
Simulation time 449305303 ps
CPU time 1.34 seconds
Started Aug 11 07:14:41 PM PDT 24
Finished Aug 11 07:14:42 PM PDT 24
Peak memory 207564 kb
Host smart-3d0b2a0d-d715-4209-a369-3b7930260be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33950
90716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3395090716
Directory /workspace/36.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/36.usbdev_streaming_out.3719591570
Short name T3266
Test name
Test status
Simulation time 2061687344 ps
CPU time 19.85 seconds
Started Aug 11 07:14:37 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 216884 kb
Host smart-3348e967-06a1-435a-b8b2-00a491715da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37195
91570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3719591570
Directory /workspace/36.usbdev_streaming_out/latest


Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.1144969551
Short name T1518
Test name
Test status
Simulation time 767535325 ps
CPU time 4.86 seconds
Started Aug 11 07:14:41 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207724 kb
Host smart-043209bd-dc75-4802-a8da-a191935106cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144969551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.1144969551
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/36.usbdev_tx_rx_disruption.803122002
Short name T179
Test name
Test status
Simulation time 652731210 ps
CPU time 1.75 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:14:37 PM PDT 24
Peak memory 207552 kb
Host smart-86bc9d95-b1bf-4026-a411-2fe7d343fce6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803122002 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.usbdev_tx_rx_disruption.803122002
Directory /workspace/36.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/360.usbdev_tx_rx_disruption.3064000563
Short name T184
Test name
Test status
Simulation time 591130219 ps
CPU time 1.58 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:36 PM PDT 24
Peak memory 207528 kb
Host smart-74c79d5e-5802-4347-bb04-c9e67ea18358
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064000563 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 360.usbdev_tx_rx_disruption.3064000563
Directory /workspace/360.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/361.usbdev_tx_rx_disruption.838325581
Short name T1260
Test name
Test status
Simulation time 646342858 ps
CPU time 1.66 seconds
Started Aug 11 07:17:32 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207512 kb
Host smart-8dde1ce7-d3a3-4319-95ca-cc59a9bf6ab1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838325581 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 361.usbdev_tx_rx_disruption.838325581
Directory /workspace/361.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/362.usbdev_tx_rx_disruption.51531705
Short name T1103
Test name
Test status
Simulation time 538216411 ps
CPU time 1.72 seconds
Started Aug 11 07:17:54 PM PDT 24
Finished Aug 11 07:17:56 PM PDT 24
Peak memory 207556 kb
Host smart-ccc3011a-8f9d-4219-aca4-acf16f5b2a47
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51531705 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 362.usbdev_tx_rx_disruption.51531705
Directory /workspace/362.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/363.usbdev_tx_rx_disruption.1107360857
Short name T1732
Test name
Test status
Simulation time 440911490 ps
CPU time 1.33 seconds
Started Aug 11 07:17:49 PM PDT 24
Finished Aug 11 07:17:50 PM PDT 24
Peak memory 207532 kb
Host smart-4558c78f-2929-4115-b2f1-37d838a7b7ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107360857 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 363.usbdev_tx_rx_disruption.1107360857
Directory /workspace/363.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/364.usbdev_tx_rx_disruption.662710209
Short name T3103
Test name
Test status
Simulation time 613102921 ps
CPU time 1.84 seconds
Started Aug 11 07:17:34 PM PDT 24
Finished Aug 11 07:17:36 PM PDT 24
Peak memory 207600 kb
Host smart-ab080873-a4c7-48a8-bd25-7303a9e76932
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662710209 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 364.usbdev_tx_rx_disruption.662710209
Directory /workspace/364.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/365.usbdev_tx_rx_disruption.1239810648
Short name T1312
Test name
Test status
Simulation time 504657637 ps
CPU time 1.56 seconds
Started Aug 11 07:17:48 PM PDT 24
Finished Aug 11 07:17:50 PM PDT 24
Peak memory 207476 kb
Host smart-3b4b75d7-8645-4e82-af35-8e0dc1ee81ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239810648 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 365.usbdev_tx_rx_disruption.1239810648
Directory /workspace/365.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/366.usbdev_tx_rx_disruption.8648596
Short name T1671
Test name
Test status
Simulation time 648502843 ps
CPU time 1.69 seconds
Started Aug 11 07:17:57 PM PDT 24
Finished Aug 11 07:17:59 PM PDT 24
Peak memory 207524 kb
Host smart-eb0c257b-47ad-454c-abaf-6c98a8c8832d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8648596 -assert nopostproc +UVM_TESTN
AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 366.usbdev_tx_rx_disruption.8648596
Directory /workspace/366.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/367.usbdev_tx_rx_disruption.1784490428
Short name T3267
Test name
Test status
Simulation time 578448851 ps
CPU time 1.56 seconds
Started Aug 11 07:18:06 PM PDT 24
Finished Aug 11 07:18:07 PM PDT 24
Peak memory 207568 kb
Host smart-7f486a83-fce3-4bfd-9d72-560356dbd92d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784490428 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 367.usbdev_tx_rx_disruption.1784490428
Directory /workspace/367.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/368.usbdev_tx_rx_disruption.2993466711
Short name T2434
Test name
Test status
Simulation time 562772728 ps
CPU time 1.57 seconds
Started Aug 11 07:17:32 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207568 kb
Host smart-6ff6de21-e614-454d-8207-4e486bc42e50
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993466711 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 368.usbdev_tx_rx_disruption.2993466711
Directory /workspace/368.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/369.usbdev_tx_rx_disruption.2601865467
Short name T2254
Test name
Test status
Simulation time 476466129 ps
CPU time 1.52 seconds
Started Aug 11 07:17:53 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207556 kb
Host smart-9703ce76-d166-44aa-a3b6-d7ed6470c0e2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601865467 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 369.usbdev_tx_rx_disruption.2601865467
Directory /workspace/369.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/37.usbdev_alert_test.2421596107
Short name T3482
Test name
Test status
Simulation time 58932872 ps
CPU time 0.71 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:55 PM PDT 24
Peak memory 207536 kb
Host smart-09cefb0f-1526-4add-b100-d1afbee40be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2421596107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2421596107
Directory /workspace/37.usbdev_alert_test/latest


Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1983667387
Short name T1560
Test name
Test status
Simulation time 12242780251 ps
CPU time 17.19 seconds
Started Aug 11 07:14:53 PM PDT 24
Finished Aug 11 07:15:10 PM PDT 24
Peak memory 207844 kb
Host smart-1c0910c8-9151-4cff-80a5-08b40f2e6038
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983667387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.1983667387
Directory /workspace/37.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1404486047
Short name T220
Test name
Test status
Simulation time 15192162082 ps
CPU time 21.47 seconds
Started Aug 11 07:14:35 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 215944 kb
Host smart-b6e0773e-00b8-4db3-8ee6-cc7ac3c5a143
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404486047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1404486047
Directory /workspace/37.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3914323713
Short name T3207
Test name
Test status
Simulation time 28604928409 ps
CPU time 37.21 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:15:26 PM PDT 24
Peak memory 207780 kb
Host smart-6ca01740-8e0e-4d84-99b1-77b5d519f8e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914323713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.3914323713
Directory /workspace/37.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/37.usbdev_av_buffer.1506376756
Short name T1422
Test name
Test status
Simulation time 150957533 ps
CPU time 0.91 seconds
Started Aug 11 07:14:56 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 207544 kb
Host smart-6cc86d0e-07c5-48a7-af60-308289ec994c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15063
76756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1506376756
Directory /workspace/37.usbdev_av_buffer/latest


Test location /workspace/coverage/default/37.usbdev_bitstuff_err.680275131
Short name T1137
Test name
Test status
Simulation time 176139210 ps
CPU time 0.85 seconds
Started Aug 11 07:14:56 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 207512 kb
Host smart-111cec3b-b075-4602-bf7b-e00de78e3844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68027
5131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.680275131
Directory /workspace/37.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3532953300
Short name T1334
Test name
Test status
Simulation time 263084204 ps
CPU time 1.19 seconds
Started Aug 11 07:14:47 PM PDT 24
Finished Aug 11 07:14:49 PM PDT 24
Peak memory 207540 kb
Host smart-84e7161c-775c-48a9-bc70-61e51a8d53d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35329
53300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3532953300
Directory /workspace/37.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3451027088
Short name T1502
Test name
Test status
Simulation time 950768407 ps
CPU time 2.65 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:14:54 PM PDT 24
Peak memory 207704 kb
Host smart-cf7c3de0-d2dd-4703-bd0e-af037a071b08
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3451027088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3451027088
Directory /workspace/37.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/37.usbdev_device_address.3034095215
Short name T1805
Test name
Test status
Simulation time 44397156421 ps
CPU time 64.48 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:15:59 PM PDT 24
Peak memory 207820 kb
Host smart-911dc7b0-a270-4c44-9e9b-edd6813321ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30340
95215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3034095215
Directory /workspace/37.usbdev_device_address/latest


Test location /workspace/coverage/default/37.usbdev_device_timeout.286060029
Short name T1379
Test name
Test status
Simulation time 2239679711 ps
CPU time 15.36 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:17 PM PDT 24
Peak memory 207816 kb
Host smart-29bf4b17-4bc6-46a4-b561-34427e433e05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286060029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.286060029
Directory /workspace/37.usbdev_device_timeout/latest


Test location /workspace/coverage/default/37.usbdev_disable_endpoint.127611972
Short name T508
Test name
Test status
Simulation time 641834610 ps
CPU time 1.65 seconds
Started Aug 11 07:14:44 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207436 kb
Host smart-7b8a2450-dd06-453c-beef-1d3eea12a06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12761
1972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.127611972
Directory /workspace/37.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/37.usbdev_disconnected.2780476323
Short name T46
Test name
Test status
Simulation time 195363084 ps
CPU time 0.88 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207508 kb
Host smart-9b038838-eeeb-46b9-800f-964be2d11daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27804
76323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2780476323
Directory /workspace/37.usbdev_disconnected/latest


Test location /workspace/coverage/default/37.usbdev_enable.2718555476
Short name T3006
Test name
Test status
Simulation time 28592214 ps
CPU time 0.68 seconds
Started Aug 11 07:14:56 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207484 kb
Host smart-20166807-235b-4058-97a2-c5e8bb62558b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27185
55476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2718555476
Directory /workspace/37.usbdev_enable/latest


Test location /workspace/coverage/default/37.usbdev_endpoint_access.1472257618
Short name T599
Test name
Test status
Simulation time 949253318 ps
CPU time 2.72 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:14:54 PM PDT 24
Peak memory 207744 kb
Host smart-cf634834-e194-4100-8f09-e55b002e1da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14722
57618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1472257618
Directory /workspace/37.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/37.usbdev_endpoint_types.3075482709
Short name T526
Test name
Test status
Simulation time 290405829 ps
CPU time 1.07 seconds
Started Aug 11 07:14:44 PM PDT 24
Finished Aug 11 07:14:45 PM PDT 24
Peak memory 206540 kb
Host smart-0d6803ba-4461-47db-bb99-7715995f4988
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3075482709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.3075482709
Directory /workspace/37.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/37.usbdev_fifo_rst.3945795043
Short name T2828
Test name
Test status
Simulation time 345379199 ps
CPU time 2.37 seconds
Started Aug 11 07:14:48 PM PDT 24
Finished Aug 11 07:14:51 PM PDT 24
Peak memory 207736 kb
Host smart-b94d3d1a-7787-4c9a-93f2-e3f05d360b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39457
95043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3945795043
Directory /workspace/37.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/37.usbdev_in_iso.1194568960
Short name T2014
Test name
Test status
Simulation time 171098314 ps
CPU time 0.85 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 207552 kb
Host smart-d7d1e480-b3d3-468c-854e-f34bd7520608
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1194568960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1194568960
Directory /workspace/37.usbdev_in_iso/latest


Test location /workspace/coverage/default/37.usbdev_in_stall.1579857926
Short name T3083
Test name
Test status
Simulation time 156320936 ps
CPU time 0.9 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207460 kb
Host smart-a6afbb3b-b526-454f-85c2-e3adfda5a833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15798
57926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1579857926
Directory /workspace/37.usbdev_in_stall/latest


Test location /workspace/coverage/default/37.usbdev_in_trans.1295397112
Short name T2090
Test name
Test status
Simulation time 219364466 ps
CPU time 0.97 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207552 kb
Host smart-47d1dbf7-0ba9-4019-816c-19750971e6d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12953
97112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1295397112
Directory /workspace/37.usbdev_in_trans/latest


Test location /workspace/coverage/default/37.usbdev_invalid_sync.275192038
Short name T2422
Test name
Test status
Simulation time 4654984516 ps
CPU time 34.37 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 224248 kb
Host smart-da5c0b24-7fc0-437a-82ae-ebf264154090
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=275192038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.275192038
Directory /workspace/37.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/37.usbdev_iso_retraction.3696721897
Short name T2656
Test name
Test status
Simulation time 12835150766 ps
CPU time 160.18 seconds
Started Aug 11 07:14:55 PM PDT 24
Finished Aug 11 07:17:35 PM PDT 24
Peak memory 207824 kb
Host smart-738de1fc-a822-426a-aa21-c37df2165fed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3696721897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.3696721897
Directory /workspace/37.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/37.usbdev_link_in_err.1400253343
Short name T3142
Test name
Test status
Simulation time 249819732 ps
CPU time 0.96 seconds
Started Aug 11 07:14:45 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207536 kb
Host smart-1615402c-a272-4daa-8d2d-f6f1714651b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14002
53343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1400253343
Directory /workspace/37.usbdev_link_in_err/latest


Test location /workspace/coverage/default/37.usbdev_link_resume.2343136626
Short name T1375
Test name
Test status
Simulation time 27749080250 ps
CPU time 32.98 seconds
Started Aug 11 07:14:46 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 215992 kb
Host smart-243df9af-68d8-4353-84a5-e233cfdee113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23431
36626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2343136626
Directory /workspace/37.usbdev_link_resume/latest


Test location /workspace/coverage/default/37.usbdev_link_suspend.3154365336
Short name T1833
Test name
Test status
Simulation time 10636559990 ps
CPU time 12.16 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:15:03 PM PDT 24
Peak memory 207784 kb
Host smart-c0763ad2-d15b-4755-a7e4-10c1ed1e85cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31543
65336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3154365336
Directory /workspace/37.usbdev_link_suspend/latest


Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1827781940
Short name T2716
Test name
Test status
Simulation time 4240458640 ps
CPU time 40.44 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:15:33 PM PDT 24
Peak memory 218368 kb
Host smart-14abbcac-e2f3-4578-9b78-e274dab58af5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1827781940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1827781940
Directory /workspace/37.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.2932633586
Short name T1701
Test name
Test status
Simulation time 3122500242 ps
CPU time 22.44 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:25 PM PDT 24
Peak memory 207876 kb
Host smart-50158db4-a86a-4d91-9c31-86e8218862bf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2932633586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.2932633586
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.531279745
Short name T2028
Test name
Test status
Simulation time 240855620 ps
CPU time 0.98 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:14:51 PM PDT 24
Peak memory 207476 kb
Host smart-a69952d0-0132-4461-ac12-42e6a76b4fdc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=531279745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.531279745
Directory /workspace/37.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2989219244
Short name T2534
Test name
Test status
Simulation time 195607759 ps
CPU time 0.98 seconds
Started Aug 11 07:14:48 PM PDT 24
Finished Aug 11 07:14:49 PM PDT 24
Peak memory 207568 kb
Host smart-f6f6eb01-f09b-41f1-b5fe-d876318c3e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892
19244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2989219244
Directory /workspace/37.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.22774993
Short name T1417
Test name
Test status
Simulation time 1933704870 ps
CPU time 19.93 seconds
Started Aug 11 07:14:48 PM PDT 24
Finished Aug 11 07:15:08 PM PDT 24
Peak memory 216864 kb
Host smart-8bf8886d-7f0e-459f-8c20-458cd313ea4a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=22774993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.22774993
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3978545121
Short name T3159
Test name
Test status
Simulation time 150496434 ps
CPU time 0.88 seconds
Started Aug 11 07:14:48 PM PDT 24
Finished Aug 11 07:14:49 PM PDT 24
Peak memory 207564 kb
Host smart-d18dc293-6443-4f7d-84c3-83a51c972939
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3978545121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3978545121
Directory /workspace/37.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.215281764
Short name T2372
Test name
Test status
Simulation time 148179067 ps
CPU time 0.85 seconds
Started Aug 11 07:14:58 PM PDT 24
Finished Aug 11 07:14:59 PM PDT 24
Peak memory 207548 kb
Host smart-395b7ff4-6477-4828-8bff-3c967561b623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21528
1764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.215281764
Directory /workspace/37.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_nak_trans.1984590471
Short name T142
Test name
Test status
Simulation time 219639981 ps
CPU time 0.97 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207520 kb
Host smart-d3d55da2-f386-4648-aa9d-75353b5a2281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845
90471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1984590471
Directory /workspace/37.usbdev_nak_trans/latest


Test location /workspace/coverage/default/37.usbdev_out_iso.1615259421
Short name T2968
Test name
Test status
Simulation time 180245586 ps
CPU time 0.96 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207504 kb
Host smart-f346f488-3121-4dd9-a9de-970a89f1e66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16152
59421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1615259421
Directory /workspace/37.usbdev_out_iso/latest


Test location /workspace/coverage/default/37.usbdev_out_stall.3308284552
Short name T2355
Test name
Test status
Simulation time 168650077 ps
CPU time 0.86 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207480 kb
Host smart-fa5325a8-678c-4f43-8c9f-1e27399f0b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33082
84552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3308284552
Directory /workspace/37.usbdev_out_stall/latest


Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2851433081
Short name T3562
Test name
Test status
Simulation time 198474753 ps
CPU time 0.87 seconds
Started Aug 11 07:14:55 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 207440 kb
Host smart-e8dc9e4a-67fc-4b9f-ac33-41dfce60beaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28514
33081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2851433081
Directory /workspace/37.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/37.usbdev_pending_in_trans.796312183
Short name T1042
Test name
Test status
Simulation time 181111471 ps
CPU time 0.83 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 207576 kb
Host smart-1f123809-76a6-4d33-9266-d4140f5185fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79631
2183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.796312183
Directory /workspace/37.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.2359436018
Short name T2621
Test name
Test status
Simulation time 224921298 ps
CPU time 0.97 seconds
Started Aug 11 07:14:45 PM PDT 24
Finished Aug 11 07:14:46 PM PDT 24
Peak memory 207524 kb
Host smart-b7895313-8b9a-4a0c-ac41-f5cde3ee278c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2359436018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2359436018
Directory /workspace/37.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3012292794
Short name T3428
Test name
Test status
Simulation time 146290658 ps
CPU time 0.82 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207408 kb
Host smart-7fce4db4-2f08-4991-b9bd-1df87e166099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30122
92794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3012292794
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.961866685
Short name T26
Test name
Test status
Simulation time 42364579 ps
CPU time 0.69 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 207520 kb
Host smart-c8b016a6-b480-4799-bda6-dc12e1e392b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96186
6685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.961866685
Directory /workspace/37.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/37.usbdev_pkt_buffer.469670104
Short name T324
Test name
Test status
Simulation time 20986075885 ps
CPU time 48.96 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:15:40 PM PDT 24
Peak memory 216036 kb
Host smart-b498d0e0-5a84-45ce-8259-08f42656663c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46967
0104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.469670104
Directory /workspace/37.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/37.usbdev_pkt_received.1312728340
Short name T3260
Test name
Test status
Simulation time 154881107 ps
CPU time 0.9 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207492 kb
Host smart-9950c743-e617-4fdc-804e-39d05aeeddb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13127
28340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1312728340
Directory /workspace/37.usbdev_pkt_received/latest


Test location /workspace/coverage/default/37.usbdev_pkt_sent.1825138476
Short name T3169
Test name
Test status
Simulation time 250581649 ps
CPU time 1.07 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207468 kb
Host smart-590feb52-3917-4709-81ec-7c06de6add98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18251
38476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1825138476
Directory /workspace/37.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2788228524
Short name T2220
Test name
Test status
Simulation time 209212329 ps
CPU time 0.95 seconds
Started Aug 11 07:15:01 PM PDT 24
Finished Aug 11 07:15:02 PM PDT 24
Peak memory 207544 kb
Host smart-7130c862-4383-4bcb-ab7a-9e4fd75107b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27882
28524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2788228524
Directory /workspace/37.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.155061356
Short name T1718
Test name
Test status
Simulation time 162549309 ps
CPU time 0.85 seconds
Started Aug 11 07:14:58 PM PDT 24
Finished Aug 11 07:14:59 PM PDT 24
Peak memory 207516 kb
Host smart-0e92e20a-5cf5-4cec-88bf-363e057208bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15506
1356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.155061356
Directory /workspace/37.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3745186454
Short name T395
Test name
Test status
Simulation time 135665557 ps
CPU time 0.81 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207492 kb
Host smart-6cb968b8-53dc-409a-aba7-e4cf0cca1200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37451
86454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3745186454
Directory /workspace/37.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/37.usbdev_rx_full.3117284508
Short name T342
Test name
Test status
Simulation time 289425412 ps
CPU time 1.07 seconds
Started Aug 11 07:14:44 PM PDT 24
Finished Aug 11 07:14:45 PM PDT 24
Peak memory 207476 kb
Host smart-5dcf1978-96a3-4656-8392-20104f57ed00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31172
84508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.3117284508
Directory /workspace/37.usbdev_rx_full/latest


Test location /workspace/coverage/default/37.usbdev_setup_stage.1416574789
Short name T971
Test name
Test status
Simulation time 146531208 ps
CPU time 0.88 seconds
Started Aug 11 07:14:53 PM PDT 24
Finished Aug 11 07:14:55 PM PDT 24
Peak memory 207536 kb
Host smart-b71f7a26-c002-4b48-99e9-192186797137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14165
74789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1416574789
Directory /workspace/37.usbdev_setup_stage/latest


Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2598171958
Short name T1919
Test name
Test status
Simulation time 145908223 ps
CPU time 0.85 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 207540 kb
Host smart-7558ecd7-aea4-4edd-ad49-072257d92fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
71958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2598171958
Directory /workspace/37.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/37.usbdev_smoke.3950137154
Short name T1383
Test name
Test status
Simulation time 247897158 ps
CPU time 1.13 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207544 kb
Host smart-1c90d0cd-a9e6-4fe3-912e-3535deb750c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39501
37154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3950137154
Directory /workspace/37.usbdev_smoke/latest


Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2713402145
Short name T1585
Test name
Test status
Simulation time 2917279780 ps
CPU time 21.63 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:15:16 PM PDT 24
Peak memory 217928 kb
Host smart-21f50454-1126-4cbd-a1c7-f184c9abc997
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2713402145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2713402145
Directory /workspace/37.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1872224739
Short name T1143
Test name
Test status
Simulation time 201880434 ps
CPU time 0.94 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:03 PM PDT 24
Peak memory 207572 kb
Host smart-3739353c-1017-4957-84a2-4ecd62a92545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18722
24739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1872224739
Directory /workspace/37.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/37.usbdev_stall_trans.728399844
Short name T2257
Test name
Test status
Simulation time 183500883 ps
CPU time 0.9 seconds
Started Aug 11 07:14:53 PM PDT 24
Finished Aug 11 07:14:54 PM PDT 24
Peak memory 207504 kb
Host smart-e9fca7a0-673e-46e2-a34b-37d44a05424a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72839
9844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.728399844
Directory /workspace/37.usbdev_stall_trans/latest


Test location /workspace/coverage/default/37.usbdev_stream_len_max.2527619630
Short name T1617
Test name
Test status
Simulation time 318968634 ps
CPU time 1.17 seconds
Started Aug 11 07:15:00 PM PDT 24
Finished Aug 11 07:15:01 PM PDT 24
Peak memory 207540 kb
Host smart-002fa122-5d9a-40ce-b9d2-8ca61e5e3c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
19630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2527619630
Directory /workspace/37.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/37.usbdev_streaming_out.4029168716
Short name T3398
Test name
Test status
Simulation time 2600939556 ps
CPU time 20.24 seconds
Started Aug 11 07:15:03 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 216112 kb
Host smart-84aa2fdf-5dcb-4600-a2b2-90e0fc40d1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40291
68716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.4029168716
Directory /workspace/37.usbdev_streaming_out/latest


Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.2457414758
Short name T3311
Test name
Test status
Simulation time 1160274083 ps
CPU time 25.99 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207700 kb
Host smart-74baa675-835c-40bd-a118-f78147024d10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457414758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.2457414758
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/37.usbdev_tx_rx_disruption.1596115268
Short name T189
Test name
Test status
Simulation time 398149960 ps
CPU time 1.34 seconds
Started Aug 11 07:14:52 PM PDT 24
Finished Aug 11 07:14:53 PM PDT 24
Peak memory 207552 kb
Host smart-ab74e42a-ef47-4bad-aaf6-79ba20a7e722
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596115268 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.usbdev_tx_rx_disruption.1596115268
Directory /workspace/37.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/370.usbdev_tx_rx_disruption.594581982
Short name T1012
Test name
Test status
Simulation time 617660406 ps
CPU time 1.61 seconds
Started Aug 11 07:17:36 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207516 kb
Host smart-026093ce-0923-4d0f-b63d-4d4985ffab55
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594581982 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 370.usbdev_tx_rx_disruption.594581982
Directory /workspace/370.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/371.usbdev_tx_rx_disruption.3836010901
Short name T684
Test name
Test status
Simulation time 548715535 ps
CPU time 1.77 seconds
Started Aug 11 07:17:56 PM PDT 24
Finished Aug 11 07:17:58 PM PDT 24
Peak memory 207484 kb
Host smart-dc162dfa-48ec-44db-a223-835baa72976d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836010901 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 371.usbdev_tx_rx_disruption.3836010901
Directory /workspace/371.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/372.usbdev_tx_rx_disruption.240163476
Short name T2443
Test name
Test status
Simulation time 615596402 ps
CPU time 1.67 seconds
Started Aug 11 07:17:58 PM PDT 24
Finished Aug 11 07:18:00 PM PDT 24
Peak memory 207484 kb
Host smart-8e2c1584-ab1e-41ff-9df7-1c90e21a55ca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240163476 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 372.usbdev_tx_rx_disruption.240163476
Directory /workspace/372.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/373.usbdev_tx_rx_disruption.3512005658
Short name T3182
Test name
Test status
Simulation time 626277433 ps
CPU time 1.75 seconds
Started Aug 11 07:17:36 PM PDT 24
Finished Aug 11 07:17:38 PM PDT 24
Peak memory 207572 kb
Host smart-4254819a-9c72-4147-895a-2e9bc3d88a4b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512005658 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 373.usbdev_tx_rx_disruption.3512005658
Directory /workspace/373.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/374.usbdev_tx_rx_disruption.1494885012
Short name T259
Test name
Test status
Simulation time 642419179 ps
CPU time 1.81 seconds
Started Aug 11 07:17:56 PM PDT 24
Finished Aug 11 07:18:01 PM PDT 24
Peak memory 207572 kb
Host smart-c8a677a8-36a2-4d0e-9623-7bd81f06e41b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494885012 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 374.usbdev_tx_rx_disruption.1494885012
Directory /workspace/374.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/375.usbdev_tx_rx_disruption.2219620274
Short name T3568
Test name
Test status
Simulation time 533111921 ps
CPU time 1.74 seconds
Started Aug 11 07:17:55 PM PDT 24
Finished Aug 11 07:17:57 PM PDT 24
Peak memory 207500 kb
Host smart-79bc1122-c38a-492f-871a-e6726e570492
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219620274 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 375.usbdev_tx_rx_disruption.2219620274
Directory /workspace/375.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/376.usbdev_tx_rx_disruption.4169344171
Short name T3389
Test name
Test status
Simulation time 496225345 ps
CPU time 1.54 seconds
Started Aug 11 07:17:49 PM PDT 24
Finished Aug 11 07:17:50 PM PDT 24
Peak memory 207532 kb
Host smart-415658e3-1696-4074-b5d8-9686f450ff29
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169344171 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 376.usbdev_tx_rx_disruption.4169344171
Directory /workspace/376.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/377.usbdev_tx_rx_disruption.4293656042
Short name T1983
Test name
Test status
Simulation time 560217996 ps
CPU time 1.57 seconds
Started Aug 11 07:17:59 PM PDT 24
Finished Aug 11 07:18:00 PM PDT 24
Peak memory 207524 kb
Host smart-b2a88e2f-6ec0-4114-967c-7254835ed944
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293656042 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 377.usbdev_tx_rx_disruption.4293656042
Directory /workspace/377.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/378.usbdev_tx_rx_disruption.2594012305
Short name T1851
Test name
Test status
Simulation time 541052317 ps
CPU time 1.64 seconds
Started Aug 11 07:18:02 PM PDT 24
Finished Aug 11 07:18:03 PM PDT 24
Peak memory 207484 kb
Host smart-5871c3da-3498-4001-8155-c7793a5c0187
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594012305 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 378.usbdev_tx_rx_disruption.2594012305
Directory /workspace/378.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/379.usbdev_tx_rx_disruption.548539250
Short name T1646
Test name
Test status
Simulation time 616453080 ps
CPU time 1.55 seconds
Started Aug 11 07:17:54 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207772 kb
Host smart-29bbce83-2084-4f71-9623-7d2dd8cd2ed2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548539250 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 379.usbdev_tx_rx_disruption.548539250
Directory /workspace/379.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/38.usbdev_alert_test.1016515656
Short name T2973
Test name
Test status
Simulation time 90120320 ps
CPU time 0.73 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207592 kb
Host smart-6becb6c9-f8d6-4ced-b6e2-90b6c4101a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1016515656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1016515656
Directory /workspace/38.usbdev_alert_test/latest


Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.963679709
Short name T1942
Test name
Test status
Simulation time 11887586404 ps
CPU time 14.75 seconds
Started Aug 11 07:14:53 PM PDT 24
Finished Aug 11 07:15:08 PM PDT 24
Peak memory 207800 kb
Host smart-ef3185a4-fe04-4095-99c9-6502e4ab15db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963679709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_disconnect.963679709
Directory /workspace/38.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.57334765
Short name T3067
Test name
Test status
Simulation time 13934133480 ps
CPU time 15.9 seconds
Started Aug 11 07:15:01 PM PDT 24
Finished Aug 11 07:15:17 PM PDT 24
Peak memory 215968 kb
Host smart-1d433068-2d05-42e6-b23d-cf2b3755e301
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=57334765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.57334765
Directory /workspace/38.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.910486228
Short name T732
Test name
Test status
Simulation time 23522994308 ps
CPU time 26.64 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:29 PM PDT 24
Peak memory 216036 kb
Host smart-8fc6a367-d332-40ee-bf73-749260372e11
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910486228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_resume.910486228
Directory /workspace/38.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/38.usbdev_av_buffer.2128627602
Short name T2120
Test name
Test status
Simulation time 161852522 ps
CPU time 0.86 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:03 PM PDT 24
Peak memory 207568 kb
Host smart-f325eccb-cf43-4f0e-8c0d-d96f2eeec133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21286
27602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2128627602
Directory /workspace/38.usbdev_av_buffer/latest


Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2253506428
Short name T2126
Test name
Test status
Simulation time 140470563 ps
CPU time 0.8 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:14:51 PM PDT 24
Peak memory 207548 kb
Host smart-3bd86ea5-0b5c-4d9b-a04b-86d4d119d81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22535
06428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2253506428
Directory /workspace/38.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1655033852
Short name T2158
Test name
Test status
Simulation time 758376480 ps
CPU time 2.3 seconds
Started Aug 11 07:15:04 PM PDT 24
Finished Aug 11 07:15:06 PM PDT 24
Peak memory 207736 kb
Host smart-f964b8cc-c866-46e8-844e-580584b25758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16550
33852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1655033852
Directory /workspace/38.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1051542663
Short name T2345
Test name
Test status
Simulation time 817869624 ps
CPU time 2.25 seconds
Started Aug 11 07:14:57 PM PDT 24
Finished Aug 11 07:14:59 PM PDT 24
Peak memory 207744 kb
Host smart-f8f0cdaf-ab27-4ff1-a48a-4742e295cc27
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1051542663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1051542663
Directory /workspace/38.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/38.usbdev_device_address.1462341920
Short name T1188
Test name
Test status
Simulation time 39501914491 ps
CPU time 66.67 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:16:09 PM PDT 24
Peak memory 207856 kb
Host smart-15f453b6-2cb6-4bb1-b8c1-7ec253726c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14623
41920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1462341920
Directory /workspace/38.usbdev_device_address/latest


Test location /workspace/coverage/default/38.usbdev_device_timeout.261696960
Short name T2420
Test name
Test status
Simulation time 5565106102 ps
CPU time 37.93 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:40 PM PDT 24
Peak memory 207868 kb
Host smart-11d49d33-17e6-4840-88db-d5d39a12dd03
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261696960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.261696960
Directory /workspace/38.usbdev_device_timeout/latest


Test location /workspace/coverage/default/38.usbdev_disable_endpoint.1495475869
Short name T2253
Test name
Test status
Simulation time 984975546 ps
CPU time 2.44 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 207496 kb
Host smart-70207b92-e51a-4af8-b794-14060def695a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14954
75869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1495475869
Directory /workspace/38.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/38.usbdev_disconnected.915546376
Short name T2238
Test name
Test status
Simulation time 141781149 ps
CPU time 0.85 seconds
Started Aug 11 07:14:59 PM PDT 24
Finished Aug 11 07:15:00 PM PDT 24
Peak memory 207520 kb
Host smart-c0ed28e0-dbcf-45c2-abd2-6f96c5d2239b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91554
6376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.915546376
Directory /workspace/38.usbdev_disconnected/latest


Test location /workspace/coverage/default/38.usbdev_enable.389271914
Short name T3233
Test name
Test status
Simulation time 34015359 ps
CPU time 0.72 seconds
Started Aug 11 07:15:01 PM PDT 24
Finished Aug 11 07:15:02 PM PDT 24
Peak memory 207536 kb
Host smart-faa6f3b3-c658-41b5-82ce-6ec0091d8e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38927
1914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.389271914
Directory /workspace/38.usbdev_enable/latest


Test location /workspace/coverage/default/38.usbdev_endpoint_access.4093712352
Short name T3313
Test name
Test status
Simulation time 812872770 ps
CPU time 2.2 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:51 PM PDT 24
Peak memory 207768 kb
Host smart-d7552ae7-dbd3-4165-8dcd-ca417d63a712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937
12352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.4093712352
Directory /workspace/38.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/38.usbdev_endpoint_types.335907227
Short name T763
Test name
Test status
Simulation time 147562897 ps
CPU time 0.86 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207548 kb
Host smart-3833912f-3c8b-4ed6-a6d4-b1cf5c891164
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=335907227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.335907227
Directory /workspace/38.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/38.usbdev_fifo_rst.2643257990
Short name T881
Test name
Test status
Simulation time 175822558 ps
CPU time 2.25 seconds
Started Aug 11 07:14:53 PM PDT 24
Finished Aug 11 07:14:55 PM PDT 24
Peak memory 207648 kb
Host smart-c45334b0-f9d7-4715-89cc-759e3ded09b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26432
57990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2643257990
Directory /workspace/38.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/38.usbdev_in_iso.383942638
Short name T2415
Test name
Test status
Simulation time 263706321 ps
CPU time 1.33 seconds
Started Aug 11 07:14:50 PM PDT 24
Finished Aug 11 07:14:52 PM PDT 24
Peak memory 215960 kb
Host smart-66a7361f-03e2-4633-baed-68a7dc2e938d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=383942638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.383942638
Directory /workspace/38.usbdev_in_iso/latest


Test location /workspace/coverage/default/38.usbdev_in_stall.1411988074
Short name T2043
Test name
Test status
Simulation time 140040020 ps
CPU time 0.82 seconds
Started Aug 11 07:14:58 PM PDT 24
Finished Aug 11 07:14:59 PM PDT 24
Peak memory 207540 kb
Host smart-dc787491-edb2-43b9-bbb8-e9bf158afabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14119
88074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1411988074
Directory /workspace/38.usbdev_in_stall/latest


Test location /workspace/coverage/default/38.usbdev_in_trans.669666515
Short name T2529
Test name
Test status
Simulation time 196891718 ps
CPU time 0.89 seconds
Started Aug 11 07:14:56 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 207564 kb
Host smart-e059150c-f188-44fe-a28a-5def2fc5dbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66966
6515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.669666515
Directory /workspace/38.usbdev_in_trans/latest


Test location /workspace/coverage/default/38.usbdev_invalid_sync.655358353
Short name T664
Test name
Test status
Simulation time 4440161385 ps
CPU time 32.86 seconds
Started Aug 11 07:14:55 PM PDT 24
Finished Aug 11 07:15:28 PM PDT 24
Peak memory 224200 kb
Host smart-bd433cb5-3eb7-46be-93c1-9e80acfb649a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=655358353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.655358353
Directory /workspace/38.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/38.usbdev_iso_retraction.1950965654
Short name T3373
Test name
Test status
Simulation time 11235921055 ps
CPU time 138.67 seconds
Started Aug 11 07:14:53 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 208020 kb
Host smart-fcc57b47-c407-4be7-a27e-d336e9636575
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1950965654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.1950965654
Directory /workspace/38.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/38.usbdev_link_in_err.325970020
Short name T1907
Test name
Test status
Simulation time 225990796 ps
CPU time 0.99 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:03 PM PDT 24
Peak memory 207600 kb
Host smart-aaa957a0-e55a-4fc5-bd28-e601ab2b0930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597
0020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.325970020
Directory /workspace/38.usbdev_link_in_err/latest


Test location /workspace/coverage/default/38.usbdev_link_resume.323886626
Short name T69
Test name
Test status
Simulation time 31861575246 ps
CPU time 51.07 seconds
Started Aug 11 07:14:56 PM PDT 24
Finished Aug 11 07:15:47 PM PDT 24
Peak memory 207872 kb
Host smart-239f0e24-5c47-45c2-8731-d43e78ea2ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32388
6626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.323886626
Directory /workspace/38.usbdev_link_resume/latest


Test location /workspace/coverage/default/38.usbdev_link_suspend.3322044627
Short name T1487
Test name
Test status
Simulation time 8398880204 ps
CPU time 11.64 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:32 PM PDT 24
Peak memory 207872 kb
Host smart-22e6f086-b460-45cc-a8e3-e3736966ddf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33220
44627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3322044627
Directory /workspace/38.usbdev_link_suspend/latest


Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1055488044
Short name T2289
Test name
Test status
Simulation time 3926856253 ps
CPU time 29.29 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 216068 kb
Host smart-f6cf831c-a92c-4a96-9c3d-4f739bf7eaa7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1055488044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1055488044
Directory /workspace/38.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2590129846
Short name T615
Test name
Test status
Simulation time 2535708763 ps
CPU time 25.04 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 217892 kb
Host smart-7a87bf47-846e-4497-881c-d70a1577a4dc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2590129846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2590129846
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2525720951
Short name T247
Test name
Test status
Simulation time 271600230 ps
CPU time 1 seconds
Started Aug 11 07:14:59 PM PDT 24
Finished Aug 11 07:15:00 PM PDT 24
Peak memory 207568 kb
Host smart-1fc9cdfd-cf5c-401e-a41a-60e99a993f2e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2525720951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2525720951
Directory /workspace/38.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3353254104
Short name T2321
Test name
Test status
Simulation time 199646791 ps
CPU time 0.9 seconds
Started Aug 11 07:14:53 PM PDT 24
Finished Aug 11 07:14:55 PM PDT 24
Peak memory 207516 kb
Host smart-3c313f6a-0ac4-4364-8314-29d9756c946c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33532
54104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3353254104
Directory /workspace/38.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1093038497
Short name T1353
Test name
Test status
Simulation time 2496578098 ps
CPU time 72.42 seconds
Started Aug 11 07:14:56 PM PDT 24
Finished Aug 11 07:16:09 PM PDT 24
Peak memory 217576 kb
Host smart-b6dbe179-415a-48e7-855f-9da485950d5c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1093038497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1093038497
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1021186032
Short name T3472
Test name
Test status
Simulation time 171667765 ps
CPU time 0.87 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:55 PM PDT 24
Peak memory 207564 kb
Host smart-0a962186-344b-4147-b70b-923d46ba2d30
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1021186032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1021186032
Directory /workspace/38.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1622836538
Short name T3614
Test name
Test status
Simulation time 152516041 ps
CPU time 0.82 seconds
Started Aug 11 07:14:56 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 207556 kb
Host smart-f60d9288-f2bf-44cc-85fb-06e62e6db384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
36538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1622836538
Directory /workspace/38.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_out_iso.1659999829
Short name T2723
Test name
Test status
Simulation time 223450285 ps
CPU time 0.97 seconds
Started Aug 11 07:14:49 PM PDT 24
Finished Aug 11 07:14:50 PM PDT 24
Peak memory 207508 kb
Host smart-25176845-d98f-4f79-9c62-6c08ec862cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16599
99829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1659999829
Directory /workspace/38.usbdev_out_iso/latest


Test location /workspace/coverage/default/38.usbdev_out_stall.615396546
Short name T544
Test name
Test status
Simulation time 210362202 ps
CPU time 0.94 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:55 PM PDT 24
Peak memory 207572 kb
Host smart-006107d9-c6b4-4860-8261-28e5b34198fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61539
6546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.615396546
Directory /workspace/38.usbdev_out_stall/latest


Test location /workspace/coverage/default/38.usbdev_out_trans_nak.734649199
Short name T2649
Test name
Test status
Simulation time 196085349 ps
CPU time 0.91 seconds
Started Aug 11 07:15:04 PM PDT 24
Finished Aug 11 07:15:05 PM PDT 24
Peak memory 207572 kb
Host smart-8a4400de-1539-42a4-a619-33c7d904efd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73464
9199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.734649199
Directory /workspace/38.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1738075431
Short name T3333
Test name
Test status
Simulation time 150020963 ps
CPU time 0.9 seconds
Started Aug 11 07:15:07 PM PDT 24
Finished Aug 11 07:15:08 PM PDT 24
Peak memory 207568 kb
Host smart-dd648ecb-1923-4a44-ae0f-6180c6035125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17380
75431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1738075431
Directory /workspace/38.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3206504268
Short name T3095
Test name
Test status
Simulation time 233001910 ps
CPU time 1.02 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 207516 kb
Host smart-73c03784-1b64-47c9-9053-53519530c935
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3206504268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3206504268
Directory /workspace/38.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2089538919
Short name T1073
Test name
Test status
Simulation time 143603334 ps
CPU time 0.93 seconds
Started Aug 11 07:15:04 PM PDT 24
Finished Aug 11 07:15:05 PM PDT 24
Peak memory 207520 kb
Host smart-54c57261-e44e-4f6b-9d19-150ac5d96e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20895
38919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2089538919
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1816952013
Short name T3230
Test name
Test status
Simulation time 36968288 ps
CPU time 0.7 seconds
Started Aug 11 07:15:14 PM PDT 24
Finished Aug 11 07:15:15 PM PDT 24
Peak memory 207536 kb
Host smart-06a0197c-82d0-4484-b2b9-a3d8b8c76b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169
52013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1816952013
Directory /workspace/38.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2294755929
Short name T1955
Test name
Test status
Simulation time 12269995399 ps
CPU time 36.39 seconds
Started Aug 11 07:15:10 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 220044 kb
Host smart-7bc73336-c0af-416c-a7b6-54ff8c083321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22947
55929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2294755929
Directory /workspace/38.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/38.usbdev_pkt_received.1918598271
Short name T3533
Test name
Test status
Simulation time 196101470 ps
CPU time 0.99 seconds
Started Aug 11 07:15:01 PM PDT 24
Finished Aug 11 07:15:02 PM PDT 24
Peak memory 207596 kb
Host smart-da17564f-3739-4449-8d3e-d204e02a8de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19185
98271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1918598271
Directory /workspace/38.usbdev_pkt_received/latest


Test location /workspace/coverage/default/38.usbdev_pkt_sent.242405876
Short name T2642
Test name
Test status
Simulation time 217409120 ps
CPU time 0.96 seconds
Started Aug 11 07:14:55 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 207508 kb
Host smart-43f81fb1-e269-4d3a-9f77-9f80b7359b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24240
5876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.242405876
Directory /workspace/38.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.59277030
Short name T3043
Test name
Test status
Simulation time 199308478 ps
CPU time 0.9 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207576 kb
Host smart-be269c92-9e95-4d41-a299-cb6e2127e2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59277
030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.59277030
Directory /workspace/38.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.4273756542
Short name T3291
Test name
Test status
Simulation time 169928476 ps
CPU time 0.9 seconds
Started Aug 11 07:15:17 PM PDT 24
Finished Aug 11 07:15:18 PM PDT 24
Peak memory 207516 kb
Host smart-9f10e02e-a708-4ed7-92fe-1d39404eff4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42737
56542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.4273756542
Directory /workspace/38.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1889880332
Short name T3631
Test name
Test status
Simulation time 143899929 ps
CPU time 0.81 seconds
Started Aug 11 07:14:56 PM PDT 24
Finished Aug 11 07:14:57 PM PDT 24
Peak memory 207492 kb
Host smart-daeaa1d2-a6d9-4d25-97bd-d6993d5d1d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18898
80332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1889880332
Directory /workspace/38.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/38.usbdev_rx_full.2824720479
Short name T338
Test name
Test status
Simulation time 259994789 ps
CPU time 1.07 seconds
Started Aug 11 07:15:09 PM PDT 24
Finished Aug 11 07:15:10 PM PDT 24
Peak memory 207548 kb
Host smart-0309e03a-09d2-4f75-93d6-bd46969cc0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28247
20479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.2824720479
Directory /workspace/38.usbdev_rx_full/latest


Test location /workspace/coverage/default/38.usbdev_setup_stage.4224062894
Short name T3184
Test name
Test status
Simulation time 154723569 ps
CPU time 0.87 seconds
Started Aug 11 07:15:01 PM PDT 24
Finished Aug 11 07:15:02 PM PDT 24
Peak memory 207488 kb
Host smart-530da4fc-113f-45f1-9be2-9a01909fa132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42240
62894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.4224062894
Directory /workspace/38.usbdev_setup_stage/latest


Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3185858252
Short name T663
Test name
Test status
Simulation time 169363777 ps
CPU time 0.9 seconds
Started Aug 11 07:14:57 PM PDT 24
Finished Aug 11 07:14:58 PM PDT 24
Peak memory 207568 kb
Host smart-a4587dbd-dd4d-43c6-a3b9-8cc4e7f6c4e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31858
58252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3185858252
Directory /workspace/38.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/38.usbdev_smoke.1435306546
Short name T1781
Test name
Test status
Simulation time 233537729 ps
CPU time 1.08 seconds
Started Aug 11 07:15:04 PM PDT 24
Finished Aug 11 07:15:05 PM PDT 24
Peak memory 207568 kb
Host smart-a22622da-ce50-4cd9-9eab-08a7b0bfce98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
06546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1435306546
Directory /workspace/38.usbdev_smoke/latest


Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.4269687917
Short name T1662
Test name
Test status
Simulation time 3245474694 ps
CPU time 98.59 seconds
Started Aug 11 07:15:04 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 217992 kb
Host smart-bd0bd8b0-e73f-4508-afbf-a1183c4a27d4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4269687917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.4269687917
Directory /workspace/38.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1454379226
Short name T2933
Test name
Test status
Simulation time 160451020 ps
CPU time 0.85 seconds
Started Aug 11 07:15:11 PM PDT 24
Finished Aug 11 07:15:12 PM PDT 24
Peak memory 207568 kb
Host smart-5b6db92a-9dc4-4f0e-b922-09edfb7c82a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14543
79226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1454379226
Directory /workspace/38.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/38.usbdev_stall_trans.736695416
Short name T2555
Test name
Test status
Simulation time 200185059 ps
CPU time 0.92 seconds
Started Aug 11 07:15:03 PM PDT 24
Finished Aug 11 07:15:04 PM PDT 24
Peak memory 207540 kb
Host smart-60e0db66-3e40-438b-8c84-f6a1ada54d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73669
5416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.736695416
Directory /workspace/38.usbdev_stall_trans/latest


Test location /workspace/coverage/default/38.usbdev_stream_len_max.3979200115
Short name T829
Test name
Test status
Simulation time 956572935 ps
CPU time 2.39 seconds
Started Aug 11 07:15:00 PM PDT 24
Finished Aug 11 07:15:03 PM PDT 24
Peak memory 207660 kb
Host smart-02b1d223-c183-49cb-a934-4095c9635eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39792
00115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3979200115
Directory /workspace/38.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/38.usbdev_streaming_out.879183132
Short name T2024
Test name
Test status
Simulation time 2193040740 ps
CPU time 24.09 seconds
Started Aug 11 07:14:56 PM PDT 24
Finished Aug 11 07:15:21 PM PDT 24
Peak memory 217488 kb
Host smart-e4d8b0f8-4845-44e4-9e11-654e80531e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87918
3132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.879183132
Directory /workspace/38.usbdev_streaming_out/latest


Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.569785650
Short name T1951
Test name
Test status
Simulation time 606944787 ps
CPU time 11.36 seconds
Started Aug 11 07:14:51 PM PDT 24
Finished Aug 11 07:15:03 PM PDT 24
Peak memory 207744 kb
Host smart-170fb2a5-6772-420b-bb88-f342fe28468f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569785650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_host
_handshake.569785650
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/38.usbdev_tx_rx_disruption.1850696575
Short name T2602
Test name
Test status
Simulation time 549064491 ps
CPU time 1.67 seconds
Started Aug 11 07:15:04 PM PDT 24
Finished Aug 11 07:15:05 PM PDT 24
Peak memory 207544 kb
Host smart-f88901e9-5629-448e-8764-a727322f643b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850696575 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.usbdev_tx_rx_disruption.1850696575
Directory /workspace/38.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/380.usbdev_tx_rx_disruption.3714470482
Short name T2398
Test name
Test status
Simulation time 513752042 ps
CPU time 1.53 seconds
Started Aug 11 07:18:01 PM PDT 24
Finished Aug 11 07:18:03 PM PDT 24
Peak memory 207588 kb
Host smart-eb6b8804-ecac-4174-a1e8-7fb7b03a009d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714470482 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 380.usbdev_tx_rx_disruption.3714470482
Directory /workspace/380.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/381.usbdev_tx_rx_disruption.3205183306
Short name T1812
Test name
Test status
Simulation time 487356160 ps
CPU time 1.51 seconds
Started Aug 11 07:18:07 PM PDT 24
Finished Aug 11 07:18:09 PM PDT 24
Peak memory 207576 kb
Host smart-54e4cbde-07d9-4f5e-8b84-da87667a0d75
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205183306 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 381.usbdev_tx_rx_disruption.3205183306
Directory /workspace/381.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/382.usbdev_tx_rx_disruption.2887135094
Short name T1838
Test name
Test status
Simulation time 511642881 ps
CPU time 1.49 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207572 kb
Host smart-37c609e1-853d-4d6c-b942-7faf7887aac1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887135094 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 382.usbdev_tx_rx_disruption.2887135094
Directory /workspace/382.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/383.usbdev_tx_rx_disruption.3880839830
Short name T2237
Test name
Test status
Simulation time 505041824 ps
CPU time 1.83 seconds
Started Aug 11 07:17:57 PM PDT 24
Finished Aug 11 07:17:59 PM PDT 24
Peak memory 207548 kb
Host smart-79991039-a61b-4bf5-8fe2-29682cbc7fd9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880839830 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 383.usbdev_tx_rx_disruption.3880839830
Directory /workspace/383.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/384.usbdev_tx_rx_disruption.1297772260
Short name T1883
Test name
Test status
Simulation time 497120540 ps
CPU time 1.48 seconds
Started Aug 11 07:18:02 PM PDT 24
Finished Aug 11 07:18:03 PM PDT 24
Peak memory 207588 kb
Host smart-fae7e487-f79f-4f14-a861-e075ab71d59c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297772260 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 384.usbdev_tx_rx_disruption.1297772260
Directory /workspace/384.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/385.usbdev_tx_rx_disruption.4042121227
Short name T2613
Test name
Test status
Simulation time 510585596 ps
CPU time 1.54 seconds
Started Aug 11 07:17:47 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207544 kb
Host smart-b1d74dcd-6d98-416f-942e-93b2c1762f66
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042121227 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 385.usbdev_tx_rx_disruption.4042121227
Directory /workspace/385.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/386.usbdev_tx_rx_disruption.1218017836
Short name T2889
Test name
Test status
Simulation time 636354236 ps
CPU time 1.67 seconds
Started Aug 11 07:18:04 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207524 kb
Host smart-b915f425-a6db-48dd-85b5-7599f8804897
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218017836 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 386.usbdev_tx_rx_disruption.1218017836
Directory /workspace/386.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/387.usbdev_tx_rx_disruption.3052463194
Short name T170
Test name
Test status
Simulation time 515498644 ps
CPU time 1.55 seconds
Started Aug 11 07:17:47 PM PDT 24
Finished Aug 11 07:17:48 PM PDT 24
Peak memory 207500 kb
Host smart-ec6d48be-9b31-4cda-8c47-0f28560b0431
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052463194 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 387.usbdev_tx_rx_disruption.3052463194
Directory /workspace/387.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/388.usbdev_tx_rx_disruption.2287982367
Short name T89
Test name
Test status
Simulation time 606770950 ps
CPU time 1.58 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207572 kb
Host smart-74586fdd-b7c0-48fd-8c07-c655c28b57c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287982367 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 388.usbdev_tx_rx_disruption.2287982367
Directory /workspace/388.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/389.usbdev_tx_rx_disruption.1535306717
Short name T1720
Test name
Test status
Simulation time 528060416 ps
CPU time 1.72 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207572 kb
Host smart-ade6fceb-36ad-4137-a933-62799e45c684
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535306717 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 389.usbdev_tx_rx_disruption.1535306717
Directory /workspace/389.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/39.usbdev_alert_test.2594727356
Short name T2101
Test name
Test status
Simulation time 116779373 ps
CPU time 0.78 seconds
Started Aug 11 07:15:17 PM PDT 24
Finished Aug 11 07:15:18 PM PDT 24
Peak memory 207564 kb
Host smart-9404b568-03a4-49d2-919d-4e981665080f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2594727356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.2594727356
Directory /workspace/39.usbdev_alert_test/latest


Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3249717272
Short name T1397
Test name
Test status
Simulation time 6655004962 ps
CPU time 9.66 seconds
Started Aug 11 07:14:59 PM PDT 24
Finished Aug 11 07:15:09 PM PDT 24
Peak memory 215956 kb
Host smart-6c936978-7893-4edb-88e0-ddc2f2039018
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249717272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.3249717272
Directory /workspace/39.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.747771755
Short name T1813
Test name
Test status
Simulation time 15766899408 ps
CPU time 20.37 seconds
Started Aug 11 07:15:16 PM PDT 24
Finished Aug 11 07:15:36 PM PDT 24
Peak memory 215932 kb
Host smart-595d06fe-0866-445a-8246-1be3d2d49f7e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=747771755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.747771755
Directory /workspace/39.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1364142751
Short name T2026
Test name
Test status
Simulation time 23442270975 ps
CPU time 28.41 seconds
Started Aug 11 07:14:59 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 216028 kb
Host smart-783fff40-a88e-4282-881e-7edc4dd09477
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364142751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.1364142751
Directory /workspace/39.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/39.usbdev_av_buffer.3508391351
Short name T1337
Test name
Test status
Simulation time 158717035 ps
CPU time 0.93 seconds
Started Aug 11 07:15:00 PM PDT 24
Finished Aug 11 07:15:01 PM PDT 24
Peak memory 207532 kb
Host smart-5683f9e8-8bcc-443c-be89-a6cf9e963d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35083
91351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3508391351
Directory /workspace/39.usbdev_av_buffer/latest


Test location /workspace/coverage/default/39.usbdev_bitstuff_err.4075605789
Short name T3381
Test name
Test status
Simulation time 155687600 ps
CPU time 0.88 seconds
Started Aug 11 07:15:03 PM PDT 24
Finished Aug 11 07:15:04 PM PDT 24
Peak memory 207580 kb
Host smart-90a81362-aabd-403d-8b65-b78c64495fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40756
05789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.4075605789
Directory /workspace/39.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.985618238
Short name T770
Test name
Test status
Simulation time 595335735 ps
CPU time 2.13 seconds
Started Aug 11 07:15:11 PM PDT 24
Finished Aug 11 07:15:13 PM PDT 24
Peak memory 207572 kb
Host smart-ed43372e-56fc-4f60-ab56-dc9854e294a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98561
8238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.985618238
Directory /workspace/39.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2822814104
Short name T355
Test name
Test status
Simulation time 1098044857 ps
CPU time 2.93 seconds
Started Aug 11 07:15:04 PM PDT 24
Finished Aug 11 07:15:07 PM PDT 24
Peak memory 207724 kb
Host smart-a886aa84-9de5-42e8-8a6a-3a0f9cb354fb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2822814104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2822814104
Directory /workspace/39.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/39.usbdev_device_address.3229286500
Short name T1909
Test name
Test status
Simulation time 35035679544 ps
CPU time 67.64 seconds
Started Aug 11 07:14:57 PM PDT 24
Finished Aug 11 07:16:05 PM PDT 24
Peak memory 208076 kb
Host smart-ee67ee79-6bc4-4e4a-a4a5-23eaab0c383c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32292
86500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3229286500
Directory /workspace/39.usbdev_device_address/latest


Test location /workspace/coverage/default/39.usbdev_device_timeout.3311002877
Short name T1876
Test name
Test status
Simulation time 321468851 ps
CPU time 4.56 seconds
Started Aug 11 07:15:03 PM PDT 24
Finished Aug 11 07:15:08 PM PDT 24
Peak memory 207776 kb
Host smart-d4921f2c-8144-4364-af6a-898ef704c38f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311002877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.3311002877
Directory /workspace/39.usbdev_device_timeout/latest


Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1540836230
Short name T1053
Test name
Test status
Simulation time 689605087 ps
CPU time 1.71 seconds
Started Aug 11 07:14:54 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207520 kb
Host smart-84701820-9138-41eb-bf05-29323bbd3ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15408
36230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1540836230
Directory /workspace/39.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/39.usbdev_disconnected.2411948705
Short name T629
Test name
Test status
Simulation time 145593396 ps
CPU time 0.86 seconds
Started Aug 11 07:14:55 PM PDT 24
Finished Aug 11 07:14:56 PM PDT 24
Peak memory 207472 kb
Host smart-2ae47241-4a5c-4aa5-96b7-b94a1dd3c433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24119
48705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2411948705
Directory /workspace/39.usbdev_disconnected/latest


Test location /workspace/coverage/default/39.usbdev_enable.3917547630
Short name T2219
Test name
Test status
Simulation time 32335318 ps
CPU time 0.7 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:02 PM PDT 24
Peak memory 207440 kb
Host smart-462abacf-946d-4740-a382-ba622bf7391c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39175
47630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3917547630
Directory /workspace/39.usbdev_enable/latest


Test location /workspace/coverage/default/39.usbdev_endpoint_access.1890352831
Short name T1618
Test name
Test status
Simulation time 850072692 ps
CPU time 2.31 seconds
Started Aug 11 07:15:03 PM PDT 24
Finished Aug 11 07:15:06 PM PDT 24
Peak memory 207748 kb
Host smart-81f9dccf-1e34-48ca-9d80-3ae834f2581b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18903
52831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1890352831
Directory /workspace/39.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/39.usbdev_fifo_rst.2067688049
Short name T1801
Test name
Test status
Simulation time 373615013 ps
CPU time 2.6 seconds
Started Aug 11 07:15:13 PM PDT 24
Finished Aug 11 07:15:15 PM PDT 24
Peak memory 207640 kb
Host smart-be3f91e2-9262-440e-9a19-34d27662083e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20676
88049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2067688049
Directory /workspace/39.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/39.usbdev_in_iso.2010415368
Short name T2640
Test name
Test status
Simulation time 224485841 ps
CPU time 1.12 seconds
Started Aug 11 07:15:03 PM PDT 24
Finished Aug 11 07:15:04 PM PDT 24
Peak memory 215940 kb
Host smart-1903da15-2ae7-4ae7-b620-c2a2eead70e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2010415368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2010415368
Directory /workspace/39.usbdev_in_iso/latest


Test location /workspace/coverage/default/39.usbdev_in_stall.591420577
Short name T598
Test name
Test status
Simulation time 146505709 ps
CPU time 0.84 seconds
Started Aug 11 07:15:03 PM PDT 24
Finished Aug 11 07:15:04 PM PDT 24
Peak memory 207512 kb
Host smart-62ab3334-1db0-4895-8b7d-9956368ab4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59142
0577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.591420577
Directory /workspace/39.usbdev_in_stall/latest


Test location /workspace/coverage/default/39.usbdev_in_trans.2443268359
Short name T2400
Test name
Test status
Simulation time 227574604 ps
CPU time 0.99 seconds
Started Aug 11 07:15:15 PM PDT 24
Finished Aug 11 07:15:16 PM PDT 24
Peak memory 207568 kb
Host smart-925c768e-368f-4abf-862f-c229fd973406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24432
68359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2443268359
Directory /workspace/39.usbdev_in_trans/latest


Test location /workspace/coverage/default/39.usbdev_invalid_sync.2768873719
Short name T2849
Test name
Test status
Simulation time 3116842427 ps
CPU time 22.36 seconds
Started Aug 11 07:15:16 PM PDT 24
Finished Aug 11 07:15:39 PM PDT 24
Peak memory 218388 kb
Host smart-d6795e9e-7181-450e-81c0-a0645d2df0f2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2768873719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.2768873719
Directory /workspace/39.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/39.usbdev_iso_retraction.3893550511
Short name T2081
Test name
Test status
Simulation time 14082790203 ps
CPU time 96.74 seconds
Started Aug 11 07:15:10 PM PDT 24
Finished Aug 11 07:16:46 PM PDT 24
Peak memory 207768 kb
Host smart-3038f1fa-dcd7-485e-ac9b-983611b89e79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3893550511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.3893550511
Directory /workspace/39.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/39.usbdev_link_in_err.1911018562
Short name T3079
Test name
Test status
Simulation time 175833448 ps
CPU time 0.89 seconds
Started Aug 11 07:15:03 PM PDT 24
Finished Aug 11 07:15:04 PM PDT 24
Peak memory 207504 kb
Host smart-fe81a773-f3ab-4c9a-86fa-cf30bf3ab9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19110
18562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1911018562
Directory /workspace/39.usbdev_link_in_err/latest


Test location /workspace/coverage/default/39.usbdev_link_resume.1956580112
Short name T3128
Test name
Test status
Simulation time 33099220111 ps
CPU time 50.28 seconds
Started Aug 11 07:15:11 PM PDT 24
Finished Aug 11 07:16:01 PM PDT 24
Peak memory 207844 kb
Host smart-89e99dd0-f4c0-412e-a32c-164fca7acab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19565
80112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1956580112
Directory /workspace/39.usbdev_link_resume/latest


Test location /workspace/coverage/default/39.usbdev_link_suspend.2191446695
Short name T360
Test name
Test status
Simulation time 9002619716 ps
CPU time 11.87 seconds
Started Aug 11 07:15:08 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207808 kb
Host smart-28d3f5e0-bc75-429f-8459-bbb0a66aca8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21914
46695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2191446695
Directory /workspace/39.usbdev_link_suspend/latest


Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2929888106
Short name T2747
Test name
Test status
Simulation time 5495678636 ps
CPU time 163.38 seconds
Started Aug 11 07:15:10 PM PDT 24
Finished Aug 11 07:17:53 PM PDT 24
Peak memory 218440 kb
Host smart-886cdecb-3371-4c6d-9c99-d083531e88b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2929888106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2929888106
Directory /workspace/39.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2102079669
Short name T2949
Test name
Test status
Simulation time 2598917635 ps
CPU time 76.62 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:16:35 PM PDT 24
Peak memory 218048 kb
Host smart-67c2cd9b-ee13-4e96-8998-f90d2deaa51b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2102079669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2102079669
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.4085609128
Short name T1776
Test name
Test status
Simulation time 244556720 ps
CPU time 1.01 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:04 PM PDT 24
Peak memory 207496 kb
Host smart-e5982a40-8f1f-43e2-90be-596e851fd1c1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4085609128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.4085609128
Directory /workspace/39.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3905951342
Short name T3076
Test name
Test status
Simulation time 204115079 ps
CPU time 0.95 seconds
Started Aug 11 07:15:05 PM PDT 24
Finished Aug 11 07:15:06 PM PDT 24
Peak memory 207552 kb
Host smart-c94057c4-2219-4db9-ad79-da2efbc1a777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39059
51342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3905951342
Directory /workspace/39.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3231256280
Short name T3204
Test name
Test status
Simulation time 2447351918 ps
CPU time 70.52 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:16:29 PM PDT 24
Peak memory 224264 kb
Host smart-17833483-11bd-401b-8e3c-e7a5849763b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3231256280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3231256280
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.330276396
Short name T2349
Test name
Test status
Simulation time 154960764 ps
CPU time 0.87 seconds
Started Aug 11 07:15:09 PM PDT 24
Finished Aug 11 07:15:10 PM PDT 24
Peak memory 207564 kb
Host smart-6b925420-8b08-46fd-a481-b5935ff067ba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=330276396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.330276396
Directory /workspace/39.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2735279137
Short name T1990
Test name
Test status
Simulation time 142865772 ps
CPU time 0.85 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:25 PM PDT 24
Peak memory 207568 kb
Host smart-f3291e8b-a65c-4a51-afba-97bf8454985e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27352
79137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2735279137
Directory /workspace/39.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_nak_trans.858645835
Short name T2332
Test name
Test status
Simulation time 221100686 ps
CPU time 0.98 seconds
Started Aug 11 07:15:25 PM PDT 24
Finished Aug 11 07:15:26 PM PDT 24
Peak memory 207580 kb
Host smart-61302cf3-cf10-453d-97dd-abcedc000ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85864
5835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.858645835
Directory /workspace/39.usbdev_nak_trans/latest


Test location /workspace/coverage/default/39.usbdev_out_iso.2177780741
Short name T1597
Test name
Test status
Simulation time 181828144 ps
CPU time 0.88 seconds
Started Aug 11 07:15:13 PM PDT 24
Finished Aug 11 07:15:14 PM PDT 24
Peak memory 207760 kb
Host smart-b70ace63-ad42-463e-a205-6818007fb2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21777
80741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2177780741
Directory /workspace/39.usbdev_out_iso/latest


Test location /workspace/coverage/default/39.usbdev_out_stall.1146579783
Short name T2512
Test name
Test status
Simulation time 183103148 ps
CPU time 0.93 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207480 kb
Host smart-2c272e66-6f6a-465c-96f9-8ec2e63c9200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11465
79783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1146579783
Directory /workspace/39.usbdev_out_stall/latest


Test location /workspace/coverage/default/39.usbdev_out_trans_nak.941273688
Short name T1288
Test name
Test status
Simulation time 205370036 ps
CPU time 0.88 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 207576 kb
Host smart-45d2ae10-defa-4d30-9e08-10076477e92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94127
3688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.941273688
Directory /workspace/39.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3684712216
Short name T3460
Test name
Test status
Simulation time 162836358 ps
CPU time 0.85 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207404 kb
Host smart-fb18be1c-86c9-48e7-8e49-8ce830a01956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36847
12216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3684712216
Directory /workspace/39.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.4283936611
Short name T2560
Test name
Test status
Simulation time 193556417 ps
CPU time 0.94 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207544 kb
Host smart-33fb2d2c-b3f5-4185-9750-88c150d80207
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4283936611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.4283936611
Directory /workspace/39.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.434710701
Short name T2792
Test name
Test status
Simulation time 146947509 ps
CPU time 0.81 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 207544 kb
Host smart-62d0848b-c134-4107-bab0-b23b48aaebd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43471
0701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.434710701
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1999302132
Short name T28
Test name
Test status
Simulation time 36594336 ps
CPU time 0.71 seconds
Started Aug 11 07:15:17 PM PDT 24
Finished Aug 11 07:15:18 PM PDT 24
Peak memory 207728 kb
Host smart-570c8ef2-a702-47cc-b7ea-687959c1200c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19993
02132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1999302132
Directory /workspace/39.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/39.usbdev_pkt_buffer.590383348
Short name T1669
Test name
Test status
Simulation time 9365268146 ps
CPU time 23.36 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:44 PM PDT 24
Peak memory 216088 kb
Host smart-f8f75718-9884-48fc-aed3-8cac9764c1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59038
3348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.590383348
Directory /workspace/39.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/39.usbdev_pkt_received.972104283
Short name T823
Test name
Test status
Simulation time 161250792 ps
CPU time 0.88 seconds
Started Aug 11 07:15:16 PM PDT 24
Finished Aug 11 07:15:17 PM PDT 24
Peak memory 207520 kb
Host smart-0a03506a-2623-48b5-9146-44a7c6d4efe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97210
4283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.972104283
Directory /workspace/39.usbdev_pkt_received/latest


Test location /workspace/coverage/default/39.usbdev_pkt_sent.121665937
Short name T978
Test name
Test status
Simulation time 245608998 ps
CPU time 1.01 seconds
Started Aug 11 07:15:08 PM PDT 24
Finished Aug 11 07:15:09 PM PDT 24
Peak memory 207496 kb
Host smart-8ea51ac1-638b-40d6-9cff-c3bdba3e01b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12166
5937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.121665937
Directory /workspace/39.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.617424063
Short name T913
Test name
Test status
Simulation time 179273809 ps
CPU time 0.88 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207440 kb
Host smart-7c8e6fa9-553c-4138-9fea-7b5239ca7fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61742
4063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.617424063
Directory /workspace/39.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2226740895
Short name T2163
Test name
Test status
Simulation time 192835842 ps
CPU time 0.89 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 207496 kb
Host smart-b7b5a804-1618-4c61-8734-91f53dbf526c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22267
40895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2226740895
Directory /workspace/39.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_rx_crc_err.1019543741
Short name T2018
Test name
Test status
Simulation time 224433110 ps
CPU time 0.93 seconds
Started Aug 11 07:15:17 PM PDT 24
Finished Aug 11 07:15:18 PM PDT 24
Peak memory 207492 kb
Host smart-232a1972-c10c-4746-adbc-47675b4b21e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10195
43741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.1019543741
Directory /workspace/39.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/39.usbdev_rx_full.3472436426
Short name T2672
Test name
Test status
Simulation time 241696802 ps
CPU time 1.09 seconds
Started Aug 11 07:15:17 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207760 kb
Host smart-41752889-1f38-49da-885c-88d3d20d1968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34724
36426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.3472436426
Directory /workspace/39.usbdev_rx_full/latest


Test location /workspace/coverage/default/39.usbdev_setup_stage.2674859413
Short name T2734
Test name
Test status
Simulation time 149275894 ps
CPU time 0.82 seconds
Started Aug 11 07:15:27 PM PDT 24
Finished Aug 11 07:15:28 PM PDT 24
Peak memory 207380 kb
Host smart-ab9e5836-0723-4b36-8930-3ac86323894b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26748
59413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2674859413
Directory /workspace/39.usbdev_setup_stage/latest


Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3154823398
Short name T1504
Test name
Test status
Simulation time 160969720 ps
CPU time 0.89 seconds
Started Aug 11 07:15:33 PM PDT 24
Finished Aug 11 07:15:34 PM PDT 24
Peak memory 207412 kb
Host smart-1b5fd91e-cb96-4e0f-b47f-c49e364ed2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31548
23398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3154823398
Directory /workspace/39.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/39.usbdev_smoke.2225322767
Short name T1724
Test name
Test status
Simulation time 220803904 ps
CPU time 1.08 seconds
Started Aug 11 07:15:16 PM PDT 24
Finished Aug 11 07:15:17 PM PDT 24
Peak memory 207556 kb
Host smart-6f3a5b75-35d3-464c-a5e4-314a6987cd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22253
22767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2225322767
Directory /workspace/39.usbdev_smoke/latest


Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.90063174
Short name T2811
Test name
Test status
Simulation time 2901748122 ps
CPU time 79.6 seconds
Started Aug 11 07:15:11 PM PDT 24
Finished Aug 11 07:16:31 PM PDT 24
Peak memory 224272 kb
Host smart-59be5497-64c2-47b4-8399-1b32d79b6775
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=90063174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.90063174
Directory /workspace/39.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1124122881
Short name T1551
Test name
Test status
Simulation time 182687502 ps
CPU time 0.89 seconds
Started Aug 11 07:15:17 PM PDT 24
Finished Aug 11 07:15:18 PM PDT 24
Peak memory 207548 kb
Host smart-5bc13eeb-09d6-415a-bb70-c74aec5390dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11241
22881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1124122881
Directory /workspace/39.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/39.usbdev_stall_trans.1447145433
Short name T2115
Test name
Test status
Simulation time 243650185 ps
CPU time 0.93 seconds
Started Aug 11 07:15:32 PM PDT 24
Finished Aug 11 07:15:33 PM PDT 24
Peak memory 207412 kb
Host smart-cb50af3f-5a63-4a6f-a689-1f027487f716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14471
45433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1447145433
Directory /workspace/39.usbdev_stall_trans/latest


Test location /workspace/coverage/default/39.usbdev_stream_len_max.130507975
Short name T2572
Test name
Test status
Simulation time 784511536 ps
CPU time 2.11 seconds
Started Aug 11 07:15:06 PM PDT 24
Finished Aug 11 07:15:08 PM PDT 24
Peak memory 207684 kb
Host smart-9b0d284c-0e9e-48f5-8724-2f8ffe94ba74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13050
7975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.130507975
Directory /workspace/39.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/39.usbdev_streaming_out.3882002445
Short name T1672
Test name
Test status
Simulation time 2686697333 ps
CPU time 25.34 seconds
Started Aug 11 07:15:31 PM PDT 24
Finished Aug 11 07:15:56 PM PDT 24
Peak memory 217024 kb
Host smart-d5137549-dd3b-423c-87ad-b4b61fcb29ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
02445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3882002445
Directory /workspace/39.usbdev_streaming_out/latest


Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.148875469
Short name T675
Test name
Test status
Simulation time 1587601761 ps
CPU time 37.13 seconds
Started Aug 11 07:15:02 PM PDT 24
Finished Aug 11 07:15:39 PM PDT 24
Peak memory 207748 kb
Host smart-50746543-67ae-4824-82a0-0ddd44afff98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148875469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_host
_handshake.148875469
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/39.usbdev_tx_rx_disruption.2090175798
Short name T2736
Test name
Test status
Simulation time 566540496 ps
CPU time 1.57 seconds
Started Aug 11 07:15:27 PM PDT 24
Finished Aug 11 07:15:29 PM PDT 24
Peak memory 207600 kb
Host smart-d89412a7-0c80-4591-8a43-99a6d255361b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090175798 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.usbdev_tx_rx_disruption.2090175798
Directory /workspace/39.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/390.usbdev_tx_rx_disruption.2327216696
Short name T3456
Test name
Test status
Simulation time 589596187 ps
CPU time 1.63 seconds
Started Aug 11 07:17:57 PM PDT 24
Finished Aug 11 07:17:59 PM PDT 24
Peak memory 207540 kb
Host smart-1c3dad59-64ad-402b-a7b8-409c6920384c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327216696 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 390.usbdev_tx_rx_disruption.2327216696
Directory /workspace/390.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/391.usbdev_tx_rx_disruption.1908699888
Short name T2421
Test name
Test status
Simulation time 621670305 ps
CPU time 1.74 seconds
Started Aug 11 07:18:02 PM PDT 24
Finished Aug 11 07:18:04 PM PDT 24
Peak memory 207600 kb
Host smart-9114b9f8-6394-40cb-b864-2966b130509c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908699888 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 391.usbdev_tx_rx_disruption.1908699888
Directory /workspace/391.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/392.usbdev_tx_rx_disruption.1263334123
Short name T1169
Test name
Test status
Simulation time 566565309 ps
CPU time 1.7 seconds
Started Aug 11 07:17:55 PM PDT 24
Finished Aug 11 07:17:57 PM PDT 24
Peak memory 207556 kb
Host smart-7a53e983-7ad8-4316-99e3-e1458d3a312a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263334123 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 392.usbdev_tx_rx_disruption.1263334123
Directory /workspace/392.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/393.usbdev_tx_rx_disruption.1317000396
Short name T3394
Test name
Test status
Simulation time 566797661 ps
CPU time 1.67 seconds
Started Aug 11 07:18:13 PM PDT 24
Finished Aug 11 07:18:15 PM PDT 24
Peak memory 207568 kb
Host smart-e3ccaada-238e-4b49-8b7a-235fb44b6a6e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317000396 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 393.usbdev_tx_rx_disruption.1317000396
Directory /workspace/393.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/394.usbdev_tx_rx_disruption.3984559633
Short name T188
Test name
Test status
Simulation time 626282171 ps
CPU time 1.88 seconds
Started Aug 11 07:18:04 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207512 kb
Host smart-ef9cec25-9afd-48fa-a587-3f289db1e641
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984559633 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 394.usbdev_tx_rx_disruption.3984559633
Directory /workspace/394.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/395.usbdev_tx_rx_disruption.398423032
Short name T3480
Test name
Test status
Simulation time 626962699 ps
CPU time 1.71 seconds
Started Aug 11 07:17:53 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207548 kb
Host smart-0530c261-4321-45d7-8890-96fcc3ddad01
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398423032 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 395.usbdev_tx_rx_disruption.398423032
Directory /workspace/395.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/396.usbdev_tx_rx_disruption.3542378690
Short name T603
Test name
Test status
Simulation time 638858109 ps
CPU time 1.81 seconds
Started Aug 11 07:18:02 PM PDT 24
Finished Aug 11 07:18:04 PM PDT 24
Peak memory 207568 kb
Host smart-dae4c3de-90e3-4117-a1a3-02dd9d7b9d05
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542378690 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 396.usbdev_tx_rx_disruption.3542378690
Directory /workspace/396.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/397.usbdev_tx_rx_disruption.2415696552
Short name T2879
Test name
Test status
Simulation time 425329487 ps
CPU time 1.34 seconds
Started Aug 11 07:17:58 PM PDT 24
Finished Aug 11 07:18:00 PM PDT 24
Peak memory 207548 kb
Host smart-8bed8a18-e963-4bcf-a7b9-51f50fa30304
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415696552 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 397.usbdev_tx_rx_disruption.2415696552
Directory /workspace/397.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/398.usbdev_tx_rx_disruption.4081894325
Short name T3346
Test name
Test status
Simulation time 559198235 ps
CPU time 1.62 seconds
Started Aug 11 07:18:01 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207528 kb
Host smart-17270fb1-afae-4a1f-b10b-316fd9249e89
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081894325 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 398.usbdev_tx_rx_disruption.4081894325
Directory /workspace/398.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/399.usbdev_tx_rx_disruption.1926981331
Short name T1139
Test name
Test status
Simulation time 685171196 ps
CPU time 1.76 seconds
Started Aug 11 07:17:59 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207568 kb
Host smart-63dd12cf-e195-4b3b-960b-fc3d21a5fdd3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926981331 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 399.usbdev_tx_rx_disruption.1926981331
Directory /workspace/399.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/4.usbdev_alert_test.1760408709
Short name T3193
Test name
Test status
Simulation time 45030721 ps
CPU time 0.67 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:09:29 PM PDT 24
Peak memory 207592 kb
Host smart-1371fa7f-62b8-4247-9462-3c52099cef8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1760408709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1760408709
Directory /workspace/4.usbdev_alert_test/latest


Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.117805866
Short name T757
Test name
Test status
Simulation time 6300745838 ps
CPU time 8.81 seconds
Started Aug 11 07:09:10 PM PDT 24
Finished Aug 11 07:09:19 PM PDT 24
Peak memory 216016 kb
Host smart-1b3af43c-86a0-475d-ab6f-ffc3745937b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117805866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon
_wake_disconnect.117805866
Directory /workspace/4.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2356041878
Short name T2105
Test name
Test status
Simulation time 19653225737 ps
CPU time 26.69 seconds
Started Aug 11 07:09:15 PM PDT 24
Finished Aug 11 07:09:42 PM PDT 24
Peak memory 207812 kb
Host smart-6bc65d13-03fc-4049-9115-feccf7a31053
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356041878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2356041878
Directory /workspace/4.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2317136126
Short name T2646
Test name
Test status
Simulation time 25363957250 ps
CPU time 29.63 seconds
Started Aug 11 07:09:12 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 216020 kb
Host smart-417f7333-346b-4759-aa53-5fb05ebc308a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317136126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.2317136126
Directory /workspace/4.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/4.usbdev_av_buffer.3954854482
Short name T1889
Test name
Test status
Simulation time 154797762 ps
CPU time 0.82 seconds
Started Aug 11 07:09:14 PM PDT 24
Finished Aug 11 07:09:15 PM PDT 24
Peak memory 207532 kb
Host smart-446cc18f-3dba-47f2-9175-c74f3b373bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39548
54482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3954854482
Directory /workspace/4.usbdev_av_buffer/latest


Test location /workspace/coverage/default/4.usbdev_av_empty.996063134
Short name T48
Test name
Test status
Simulation time 213583234 ps
CPU time 0.92 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:09:17 PM PDT 24
Peak memory 207544 kb
Host smart-4dee9c70-3aa8-48e9-9fcd-96f010896b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99606
3134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.996063134
Directory /workspace/4.usbdev_av_empty/latest


Test location /workspace/coverage/default/4.usbdev_av_overflow.2218661953
Short name T63
Test name
Test status
Simulation time 144508198 ps
CPU time 0.85 seconds
Started Aug 11 07:09:12 PM PDT 24
Finished Aug 11 07:09:13 PM PDT 24
Peak memory 207452 kb
Host smart-381589c6-bda0-4baa-ad59-491d2c951541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22186
61953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2218661953
Directory /workspace/4.usbdev_av_overflow/latest


Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3547138481
Short name T3350
Test name
Test status
Simulation time 171044696 ps
CPU time 0.91 seconds
Started Aug 11 07:09:10 PM PDT 24
Finished Aug 11 07:09:11 PM PDT 24
Peak memory 207540 kb
Host smart-6828e5eb-9158-4781-8bec-e85932ce2a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35471
38481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3547138481
Directory /workspace/4.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1382534014
Short name T694
Test name
Test status
Simulation time 299938344 ps
CPU time 1.13 seconds
Started Aug 11 07:09:15 PM PDT 24
Finished Aug 11 07:09:16 PM PDT 24
Peak memory 207556 kb
Host smart-dacd7ad9-1840-442b-b749-42dec59310aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13825
34014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1382534014
Directory /workspace/4.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3087554514
Short name T348
Test name
Test status
Simulation time 1022869017 ps
CPU time 2.73 seconds
Started Aug 11 07:09:17 PM PDT 24
Finished Aug 11 07:09:20 PM PDT 24
Peak memory 207736 kb
Host smart-fad2fb18-59c9-42aa-aa4b-4e4321982384
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3087554514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3087554514
Directory /workspace/4.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/4.usbdev_device_timeout.69758636
Short name T3156
Test name
Test status
Simulation time 442806298 ps
CPU time 8.89 seconds
Started Aug 11 07:09:17 PM PDT 24
Finished Aug 11 07:09:26 PM PDT 24
Peak memory 207772 kb
Host smart-069b5fd6-1340-4f48-8252-75a81b0018d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69758636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.69758636
Directory /workspace/4.usbdev_device_timeout/latest


Test location /workspace/coverage/default/4.usbdev_disable_endpoint.2264145824
Short name T2637
Test name
Test status
Simulation time 730475563 ps
CPU time 2.01 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:09:18 PM PDT 24
Peak memory 207520 kb
Host smart-07f4c14c-82fc-4d6f-be54-6638f339e6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22641
45824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.2264145824
Directory /workspace/4.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/4.usbdev_disconnected.3077506821
Short name T950
Test name
Test status
Simulation time 138657274 ps
CPU time 0.83 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:09:17 PM PDT 24
Peak memory 207520 kb
Host smart-12ef8372-1b4c-45ac-9be9-7a5c131cd2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
06821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3077506821
Directory /workspace/4.usbdev_disconnected/latest


Test location /workspace/coverage/default/4.usbdev_enable.4254611630
Short name T3478
Test name
Test status
Simulation time 46966073 ps
CPU time 0.7 seconds
Started Aug 11 07:09:17 PM PDT 24
Finished Aug 11 07:09:18 PM PDT 24
Peak memory 207712 kb
Host smart-f9f35ceb-5996-463f-a028-9b969932264a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42546
11630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.4254611630
Directory /workspace/4.usbdev_enable/latest


Test location /workspace/coverage/default/4.usbdev_endpoint_access.2520757422
Short name T1654
Test name
Test status
Simulation time 871966842 ps
CPU time 2.53 seconds
Started Aug 11 07:09:17 PM PDT 24
Finished Aug 11 07:09:19 PM PDT 24
Peak memory 207768 kb
Host smart-361e9ce7-2292-4b09-9b92-8cf9e00b3e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25207
57422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2520757422
Directory /workspace/4.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/4.usbdev_endpoint_types.2095301126
Short name T2823
Test name
Test status
Simulation time 345337705 ps
CPU time 1.23 seconds
Started Aug 11 07:09:18 PM PDT 24
Finished Aug 11 07:09:19 PM PDT 24
Peak memory 207500 kb
Host smart-5db0b8a2-a6b6-4385-bbca-3fe03f460f41
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2095301126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.2095301126
Directory /workspace/4.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/4.usbdev_fifo_rst.4075586976
Short name T569
Test name
Test status
Simulation time 288785008 ps
CPU time 2.5 seconds
Started Aug 11 07:09:17 PM PDT 24
Finished Aug 11 07:09:19 PM PDT 24
Peak memory 207628 kb
Host smart-229463ae-92c1-4d8c-bd05-c5fdd58469fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40755
86976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.4075586976
Directory /workspace/4.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/4.usbdev_freq_hiclk.3668503913
Short name T2218
Test name
Test status
Simulation time 112204784414 ps
CPU time 192.93 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 207784 kb
Host smart-f265a808-31ce-40c4-bfbc-56dea7924e56
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3668503913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.3668503913
Directory /workspace/4.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.994874646
Short name T2888
Test name
Test status
Simulation time 99040531776 ps
CPU time 158.26 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:11:54 PM PDT 24
Peak memory 207876 kb
Host smart-5bd31850-bb43-42f0-a37f-1aa65d55b716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994874646 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.994874646
Directory /workspace/4.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/4.usbdev_freq_loclk.1398689035
Short name T1287
Test name
Test status
Simulation time 114095628429 ps
CPU time 184.01 seconds
Started Aug 11 07:09:15 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 207844 kb
Host smart-e2d424e9-4a71-453e-8f3d-ccc6d2da5312
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1398689035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1398689035
Directory /workspace/4.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.2014242
Short name T1635
Test name
Test status
Simulation time 99022462010 ps
CPU time 165.17 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 207756 kb
Host smart-2324ed52-b266-487f-a16b-f2dadf0fed59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014242 -assert nopo
stproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.2014242
Directory /workspace/4.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/4.usbdev_freq_phase.3480974259
Short name T1024
Test name
Test status
Simulation time 109202496491 ps
CPU time 167.57 seconds
Started Aug 11 07:09:16 PM PDT 24
Finished Aug 11 07:12:03 PM PDT 24
Peak memory 207864 kb
Host smart-fdad4769-7aed-427f-9ea0-c963ad55209b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34809
74259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3480974259
Directory /workspace/4.usbdev_freq_phase/latest


Test location /workspace/coverage/default/4.usbdev_in_iso.3787218017
Short name T2268
Test name
Test status
Simulation time 246578854 ps
CPU time 1.09 seconds
Started Aug 11 07:09:17 PM PDT 24
Finished Aug 11 07:09:19 PM PDT 24
Peak memory 215844 kb
Host smart-8cdd0b7b-7483-48a7-b981-9756fdfe12c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3787218017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3787218017
Directory /workspace/4.usbdev_in_iso/latest


Test location /workspace/coverage/default/4.usbdev_in_stall.2082989471
Short name T3599
Test name
Test status
Simulation time 157963677 ps
CPU time 0.86 seconds
Started Aug 11 07:09:18 PM PDT 24
Finished Aug 11 07:09:19 PM PDT 24
Peak memory 207448 kb
Host smart-8993195e-76e2-48c0-807a-ddd24fec05bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20829
89471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2082989471
Directory /workspace/4.usbdev_in_stall/latest


Test location /workspace/coverage/default/4.usbdev_in_trans.2458960328
Short name T1458
Test name
Test status
Simulation time 266919499 ps
CPU time 1.05 seconds
Started Aug 11 07:09:17 PM PDT 24
Finished Aug 11 07:09:18 PM PDT 24
Peak memory 207480 kb
Host smart-14273fd4-fd23-44d1-8cc7-9c225b850399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24589
60328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2458960328
Directory /workspace/4.usbdev_in_trans/latest


Test location /workspace/coverage/default/4.usbdev_invalid_sync.2784094188
Short name T385
Test name
Test status
Simulation time 3450939256 ps
CPU time 25.4 seconds
Started Aug 11 07:09:18 PM PDT 24
Finished Aug 11 07:09:43 PM PDT 24
Peak memory 218104 kb
Host smart-ec713bd7-a866-4726-9d3f-c3b2fcdd8fbb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2784094188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.2784094188
Directory /workspace/4.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/4.usbdev_iso_retraction.1889945060
Short name T1713
Test name
Test status
Simulation time 9188633153 ps
CPU time 57.91 seconds
Started Aug 11 07:09:24 PM PDT 24
Finished Aug 11 07:10:22 PM PDT 24
Peak memory 207756 kb
Host smart-0a1bbf5f-807b-4f1b-bd9b-218f929d7a1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1889945060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.1889945060
Directory /workspace/4.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/4.usbdev_link_in_err.3626126355
Short name T2278
Test name
Test status
Simulation time 179045661 ps
CPU time 0.94 seconds
Started Aug 11 07:09:23 PM PDT 24
Finished Aug 11 07:09:24 PM PDT 24
Peak memory 207748 kb
Host smart-208f9f6a-0660-4f64-88e9-7f6864e591bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36261
26355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3626126355
Directory /workspace/4.usbdev_link_in_err/latest


Test location /workspace/coverage/default/4.usbdev_link_resume.3374342866
Short name T3543
Test name
Test status
Simulation time 14686193308 ps
CPU time 23.45 seconds
Started Aug 11 07:09:23 PM PDT 24
Finished Aug 11 07:09:46 PM PDT 24
Peak memory 207816 kb
Host smart-2fe662b2-37e4-4cdd-8f98-b967abec65be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33743
42866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3374342866
Directory /workspace/4.usbdev_link_resume/latest


Test location /workspace/coverage/default/4.usbdev_link_suspend.2172991759
Short name T1593
Test name
Test status
Simulation time 6010219060 ps
CPU time 7.78 seconds
Started Aug 11 07:09:21 PM PDT 24
Finished Aug 11 07:09:29 PM PDT 24
Peak memory 216804 kb
Host smart-3231e726-78d3-4659-8aa2-155cbf99f3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21729
91759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2172991759
Directory /workspace/4.usbdev_link_suspend/latest


Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.245111813
Short name T2635
Test name
Test status
Simulation time 4739062803 ps
CPU time 38.58 seconds
Started Aug 11 07:09:22 PM PDT 24
Finished Aug 11 07:10:01 PM PDT 24
Peak memory 219860 kb
Host smart-8ab3a9a1-d976-40dd-a65c-6aa05debbe71
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=245111813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.245111813
Directory /workspace/4.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1420571398
Short name T2487
Test name
Test status
Simulation time 2986480166 ps
CPU time 30.54 seconds
Started Aug 11 07:09:23 PM PDT 24
Finished Aug 11 07:09:54 PM PDT 24
Peak memory 217720 kb
Host smart-7526fae9-4d40-494a-907d-a08c4e4de3d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1420571398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1420571398
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3421089148
Short name T2976
Test name
Test status
Simulation time 250151040 ps
CPU time 1.05 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:09:29 PM PDT 24
Peak memory 207552 kb
Host smart-413ce4ef-6192-433e-bd1b-df01d4e6fc62
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3421089148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3421089148
Directory /workspace/4.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3163289906
Short name T1349
Test name
Test status
Simulation time 190547246 ps
CPU time 0.94 seconds
Started Aug 11 07:09:22 PM PDT 24
Finished Aug 11 07:09:23 PM PDT 24
Peak memory 207580 kb
Host smart-9e3d420f-46c6-45b5-9de2-d83cf2c5d2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31632
89906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3163289906
Directory /workspace/4.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.887358252
Short name T1739
Test name
Test status
Simulation time 1709344131 ps
CPU time 17.13 seconds
Started Aug 11 07:09:25 PM PDT 24
Finished Aug 11 07:09:42 PM PDT 24
Peak memory 224072 kb
Host smart-f41d78d9-0213-49d3-bcea-0be08c5257b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88735
8252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.887358252
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3216106589
Short name T2406
Test name
Test status
Simulation time 2949675428 ps
CPU time 81.33 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 218016 kb
Host smart-210d75f7-0f28-46d8-a222-5594c1f4c066
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3216106589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3216106589
Directory /workspace/4.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3131342909
Short name T3081
Test name
Test status
Simulation time 2209356980 ps
CPU time 63.95 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 216036 kb
Host smart-944e9d29-2062-4501-acb9-5a8c454cfd4f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3131342909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3131342909
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1913278512
Short name T623
Test name
Test status
Simulation time 159454192 ps
CPU time 0.89 seconds
Started Aug 11 07:09:23 PM PDT 24
Finished Aug 11 07:09:24 PM PDT 24
Peak memory 207560 kb
Host smart-da6f421d-4efa-41a7-98ea-a53d42b53807
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1913278512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1913278512
Directory /workspace/4.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3409039464
Short name T2559
Test name
Test status
Simulation time 148437158 ps
CPU time 0.88 seconds
Started Aug 11 07:09:22 PM PDT 24
Finished Aug 11 07:09:23 PM PDT 24
Peak memory 207568 kb
Host smart-de8370b0-5b0b-4ae0-95e5-6cf5baf6ff63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34090
39464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3409039464
Directory /workspace/4.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_nak_trans.1149100759
Short name T150
Test name
Test status
Simulation time 227415841 ps
CPU time 0.99 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:09:29 PM PDT 24
Peak memory 207556 kb
Host smart-e6355e70-8681-49c1-9303-63b1ecf7f69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11491
00759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1149100759
Directory /workspace/4.usbdev_nak_trans/latest


Test location /workspace/coverage/default/4.usbdev_out_iso.2220848052
Short name T961
Test name
Test status
Simulation time 200118741 ps
CPU time 0.86 seconds
Started Aug 11 07:09:22 PM PDT 24
Finished Aug 11 07:09:23 PM PDT 24
Peak memory 207524 kb
Host smart-d5e19640-601a-4d15-8bc7-0364f4033344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22208
48052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2220848052
Directory /workspace/4.usbdev_out_iso/latest


Test location /workspace/coverage/default/4.usbdev_out_stall.1180995477
Short name T3527
Test name
Test status
Simulation time 215900878 ps
CPU time 0.98 seconds
Started Aug 11 07:09:21 PM PDT 24
Finished Aug 11 07:09:22 PM PDT 24
Peak memory 207504 kb
Host smart-3c0cf36b-ff09-43c0-b395-c1c390f47e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
95477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1180995477
Directory /workspace/4.usbdev_out_stall/latest


Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1656925301
Short name T1541
Test name
Test status
Simulation time 149739214 ps
CPU time 0.87 seconds
Started Aug 11 07:09:21 PM PDT 24
Finished Aug 11 07:09:22 PM PDT 24
Peak memory 207564 kb
Host smart-24a0f9c7-1aee-4a95-bf9e-18f2e8e030fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16569
25301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1656925301
Directory /workspace/4.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3910381768
Short name T2489
Test name
Test status
Simulation time 161099207 ps
CPU time 0.84 seconds
Started Aug 11 07:09:22 PM PDT 24
Finished Aug 11 07:09:23 PM PDT 24
Peak memory 207572 kb
Host smart-108ff256-6b31-4d69-9875-00d869ca6854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39103
81768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3910381768
Directory /workspace/4.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.229302851
Short name T2136
Test name
Test status
Simulation time 223714558 ps
CPU time 1.05 seconds
Started Aug 11 07:09:27 PM PDT 24
Finished Aug 11 07:09:28 PM PDT 24
Peak memory 207560 kb
Host smart-7e0ac07a-69f0-4240-a392-379b49a788ca
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=229302851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.229302851
Directory /workspace/4.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2010329620
Short name T673
Test name
Test status
Simulation time 255313735 ps
CPU time 1.06 seconds
Started Aug 11 07:09:22 PM PDT 24
Finished Aug 11 07:09:23 PM PDT 24
Peak memory 207596 kb
Host smart-f98c64c5-6190-4c43-9569-0fe9b1715615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20103
29620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2010329620
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2876706800
Short name T1514
Test name
Test status
Simulation time 144789181 ps
CPU time 0.83 seconds
Started Aug 11 07:09:21 PM PDT 24
Finished Aug 11 07:09:22 PM PDT 24
Peak memory 207536 kb
Host smart-4bd91ca9-340b-49c0-bf96-692d2cd257ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28767
06800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2876706800
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3004658876
Short name T3262
Test name
Test status
Simulation time 40527163 ps
CPU time 0.72 seconds
Started Aug 11 07:09:27 PM PDT 24
Finished Aug 11 07:09:28 PM PDT 24
Peak memory 207516 kb
Host smart-267e836f-5793-47db-ac14-957dcf72531b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30046
58876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3004658876
Directory /workspace/4.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3739462865
Short name T2245
Test name
Test status
Simulation time 5869608333 ps
CPU time 15.68 seconds
Started Aug 11 07:09:24 PM PDT 24
Finished Aug 11 07:09:40 PM PDT 24
Peak memory 220552 kb
Host smart-b551e86d-6e24-4852-8315-e8d04b6495f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37394
62865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3739462865
Directory /workspace/4.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/4.usbdev_pkt_received.3846840295
Short name T611
Test name
Test status
Simulation time 200388784 ps
CPU time 0.96 seconds
Started Aug 11 07:09:21 PM PDT 24
Finished Aug 11 07:09:22 PM PDT 24
Peak memory 207516 kb
Host smart-a6c03c46-f6e7-4b4e-a4e8-393e356260de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38468
40295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3846840295
Directory /workspace/4.usbdev_pkt_received/latest


Test location /workspace/coverage/default/4.usbdev_pkt_sent.1970768667
Short name T2463
Test name
Test status
Simulation time 192047852 ps
CPU time 0.88 seconds
Started Aug 11 07:09:22 PM PDT 24
Finished Aug 11 07:09:23 PM PDT 24
Peak memory 207568 kb
Host smart-cea84a8e-bf42-4c08-96fa-48ddffc050fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
68667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1970768667
Directory /workspace/4.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.763856627
Short name T2295
Test name
Test status
Simulation time 7141612773 ps
CPU time 67.69 seconds
Started Aug 11 07:09:22 PM PDT 24
Finished Aug 11 07:10:30 PM PDT 24
Peak memory 218660 kb
Host smart-7be88a06-4010-403c-9941-e6ea54318a69
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=763856627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.763856627
Directory /workspace/4.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3348811098
Short name T3612
Test name
Test status
Simulation time 3700907463 ps
CPU time 98.14 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:11:07 PM PDT 24
Peak memory 218848 kb
Host smart-88e6c22e-8816-43f3-a9e5-751d42fdf796
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3348811098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3348811098
Directory /workspace/4.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/4.usbdev_rand_suspends.2106091370
Short name T2796
Test name
Test status
Simulation time 6548068801 ps
CPU time 31.97 seconds
Started Aug 11 07:09:31 PM PDT 24
Finished Aug 11 07:10:03 PM PDT 24
Peak memory 224292 kb
Host smart-0bca4e1a-b651-4090-91a3-f0b80b611b0c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106091370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2106091370
Directory /workspace/4.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.4138825540
Short name T2407
Test name
Test status
Simulation time 176796350 ps
CPU time 0.92 seconds
Started Aug 11 07:09:23 PM PDT 24
Finished Aug 11 07:09:24 PM PDT 24
Peak memory 207468 kb
Host smart-15cd5cac-b9b4-4767-8b03-ba97a4cac9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41388
25540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.4138825540
Directory /workspace/4.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.2900826904
Short name T911
Test name
Test status
Simulation time 177545027 ps
CPU time 0.92 seconds
Started Aug 11 07:09:22 PM PDT 24
Finished Aug 11 07:09:23 PM PDT 24
Peak memory 207544 kb
Host smart-41a2c527-6871-497d-a44b-a58d5c52197d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29008
26904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.2900826904
Directory /workspace/4.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_resume_link_active.2177747424
Short name T1176
Test name
Test status
Simulation time 20172890556 ps
CPU time 30.09 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207596 kb
Host smart-88107656-7509-4c2c-918d-a68f5703d77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21777
47424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.2177747424
Directory /workspace/4.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2186891973
Short name T2966
Test name
Test status
Simulation time 158768370 ps
CPU time 0.89 seconds
Started Aug 11 07:09:29 PM PDT 24
Finished Aug 11 07:09:30 PM PDT 24
Peak memory 207576 kb
Host smart-e16b7f0e-9bd0-4dac-8b58-e7726d919f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21868
91973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2186891973
Directory /workspace/4.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/4.usbdev_rx_full.889635194
Short name T340
Test name
Test status
Simulation time 313374426 ps
CPU time 1.12 seconds
Started Aug 11 07:09:31 PM PDT 24
Finished Aug 11 07:09:32 PM PDT 24
Peak memory 207508 kb
Host smart-3cc32891-9da3-4d9f-9df0-6ce1a2601dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88963
5194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.889635194
Directory /workspace/4.usbdev_rx_full/latest


Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2350025291
Short name T81
Test name
Test status
Simulation time 170741797 ps
CPU time 0.96 seconds
Started Aug 11 07:09:30 PM PDT 24
Finished Aug 11 07:09:32 PM PDT 24
Peak memory 207508 kb
Host smart-6cf5e765-6fdc-4efc-afdb-d8961238b47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23500
25291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2350025291
Directory /workspace/4.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/4.usbdev_sec_cm.1845975027
Short name T237
Test name
Test status
Simulation time 1804227315 ps
CPU time 2.48 seconds
Started Aug 11 07:09:31 PM PDT 24
Finished Aug 11 07:09:33 PM PDT 24
Peak memory 224536 kb
Host smart-04d5ba1f-ff0f-45e1-ad77-ca5f89904b46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1845975027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1845975027
Directory /workspace/4.usbdev_sec_cm/latest


Test location /workspace/coverage/default/4.usbdev_setup_priority.2601268571
Short name T55
Test name
Test status
Simulation time 423479926 ps
CPU time 1.45 seconds
Started Aug 11 07:09:29 PM PDT 24
Finished Aug 11 07:09:30 PM PDT 24
Peak memory 207492 kb
Host smart-d74f35a3-56bc-49fc-973d-21a7541e423d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26012
68571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2601268571
Directory /workspace/4.usbdev_setup_priority/latest


Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.369987133
Short name T1586
Test name
Test status
Simulation time 208184916 ps
CPU time 1.02 seconds
Started Aug 11 07:09:26 PM PDT 24
Finished Aug 11 07:09:27 PM PDT 24
Peak memory 207528 kb
Host smart-8304c379-7af8-4571-a24c-87a55fb1db3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36998
7133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.369987133
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/4.usbdev_setup_stage.3223678556
Short name T1948
Test name
Test status
Simulation time 148091817 ps
CPU time 0.81 seconds
Started Aug 11 07:09:30 PM PDT 24
Finished Aug 11 07:09:31 PM PDT 24
Peak memory 207716 kb
Host smart-1ec64c84-10a5-4c64-bbc9-63f85b81f75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32236
78556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3223678556
Directory /workspace/4.usbdev_setup_stage/latest


Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3035430453
Short name T1960
Test name
Test status
Simulation time 146092416 ps
CPU time 0.88 seconds
Started Aug 11 07:09:30 PM PDT 24
Finished Aug 11 07:09:31 PM PDT 24
Peak memory 207596 kb
Host smart-ae99c8a6-6d60-4375-a5e9-3e4d9bbf88d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30354
30453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3035430453
Directory /workspace/4.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/4.usbdev_smoke.3781926324
Short name T1778
Test name
Test status
Simulation time 197360968 ps
CPU time 0.92 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:09:29 PM PDT 24
Peak memory 207440 kb
Host smart-da076a67-b134-4879-baaf-00c9d13b0083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37819
26324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3781926324
Directory /workspace/4.usbdev_smoke/latest


Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.2941188649
Short name T2095
Test name
Test status
Simulation time 2229675793 ps
CPU time 65.12 seconds
Started Aug 11 07:09:30 PM PDT 24
Finished Aug 11 07:10:35 PM PDT 24
Peak memory 217764 kb
Host smart-d7434881-123f-4086-a86e-fe5ba1d97c82
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2941188649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.2941188649
Directory /workspace/4.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1190853293
Short name T2116
Test name
Test status
Simulation time 163870498 ps
CPU time 0.85 seconds
Started Aug 11 07:09:26 PM PDT 24
Finished Aug 11 07:09:27 PM PDT 24
Peak memory 207492 kb
Host smart-d8a36f58-e7d5-4a92-aafc-785fbed14c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11908
53293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1190853293
Directory /workspace/4.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/4.usbdev_stall_trans.1987918815
Short name T1356
Test name
Test status
Simulation time 172313730 ps
CPU time 0.87 seconds
Started Aug 11 07:09:29 PM PDT 24
Finished Aug 11 07:09:30 PM PDT 24
Peak memory 207536 kb
Host smart-e00562d9-4341-47b9-8566-54fd70a71240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19879
18815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1987918815
Directory /workspace/4.usbdev_stall_trans/latest


Test location /workspace/coverage/default/4.usbdev_stream_len_max.4280954025
Short name T274
Test name
Test status
Simulation time 651203484 ps
CPU time 1.73 seconds
Started Aug 11 07:09:27 PM PDT 24
Finished Aug 11 07:09:29 PM PDT 24
Peak memory 207408 kb
Host smart-604f92b4-586d-4a74-bfca-9131907ade96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42809
54025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.4280954025
Directory /workspace/4.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/4.usbdev_streaming_out.2855560226
Short name T3516
Test name
Test status
Simulation time 1676254240 ps
CPU time 17.14 seconds
Started Aug 11 07:09:26 PM PDT 24
Finished Aug 11 07:09:44 PM PDT 24
Peak memory 224228 kb
Host smart-d1229b14-8d9d-44f1-b791-f905212c43c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28555
60226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2855560226
Directory /workspace/4.usbdev_streaming_out/latest


Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1808181083
Short name T87
Test name
Test status
Simulation time 7804964517 ps
CPU time 130.65 seconds
Started Aug 11 07:09:30 PM PDT 24
Finished Aug 11 07:11:41 PM PDT 24
Peak memory 216108 kb
Host smart-57c5de6d-6812-4142-90bf-72e2599dd0c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808181083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1808181083
Directory /workspace/4.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.3681443823
Short name T3345
Test name
Test status
Simulation time 3887612921 ps
CPU time 33.41 seconds
Started Aug 11 07:09:14 PM PDT 24
Finished Aug 11 07:09:48 PM PDT 24
Peak memory 207788 kb
Host smart-96597e3d-a222-43af-b3b0-aaca4d5f4396
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681443823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.3681443823
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/4.usbdev_tx_rx_disruption.3496799053
Short name T3174
Test name
Test status
Simulation time 497992474 ps
CPU time 1.55 seconds
Started Aug 11 07:09:30 PM PDT 24
Finished Aug 11 07:09:31 PM PDT 24
Peak memory 207776 kb
Host smart-8b7b3751-010f-48a7-86dd-e727bbaeb99d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496799053 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.usbdev_tx_rx_disruption.3496799053
Directory /workspace/4.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/40.usbdev_alert_test.618746893
Short name T669
Test name
Test status
Simulation time 32418701 ps
CPU time 0.66 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207560 kb
Host smart-0f15f2b8-4826-48d9-aec1-11a364cd35e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=618746893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.618746893
Directory /workspace/40.usbdev_alert_test/latest


Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.734181923
Short name T3102
Test name
Test status
Simulation time 10924392801 ps
CPU time 12.93 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:31 PM PDT 24
Peak memory 207748 kb
Host smart-ed48b99d-8c19-44ec-9c64-55c11dbf6d35
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734181923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ao
n_wake_disconnect.734181923
Directory /workspace/40.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2946554230
Short name T1481
Test name
Test status
Simulation time 20418188181 ps
CPU time 26.88 seconds
Started Aug 11 07:15:25 PM PDT 24
Finished Aug 11 07:15:52 PM PDT 24
Peak memory 207844 kb
Host smart-ed9ffb7c-defd-4ed1-97d4-0330c2db0074
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946554230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2946554230
Directory /workspace/40.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.4054937345
Short name T1750
Test name
Test status
Simulation time 30797086900 ps
CPU time 35.91 seconds
Started Aug 11 07:15:32 PM PDT 24
Finished Aug 11 07:16:08 PM PDT 24
Peak memory 207708 kb
Host smart-5aa3e0c9-36bc-41ec-b25d-b5e9191042c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054937345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.4054937345
Directory /workspace/40.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/40.usbdev_av_buffer.948997498
Short name T1276
Test name
Test status
Simulation time 159945768 ps
CPU time 0.87 seconds
Started Aug 11 07:15:31 PM PDT 24
Finished Aug 11 07:15:32 PM PDT 24
Peak memory 207580 kb
Host smart-56e69e65-4a77-4cf5-9c7b-389cbe4dbfc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94899
7498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.948997498
Directory /workspace/40.usbdev_av_buffer/latest


Test location /workspace/coverage/default/40.usbdev_bitstuff_err.1777656655
Short name T2098
Test name
Test status
Simulation time 170289267 ps
CPU time 0.87 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207576 kb
Host smart-eb873d1e-c351-48c2-8ef9-d00647ae4214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17776
56655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.1777656655
Directory /workspace/40.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1631711741
Short name T3620
Test name
Test status
Simulation time 403644474 ps
CPU time 1.44 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207392 kb
Host smart-9d0a6303-4df6-4edc-81e3-67160b0c0aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317
11741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1631711741
Directory /workspace/40.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.504030229
Short name T349
Test name
Test status
Simulation time 708494255 ps
CPU time 1.88 seconds
Started Aug 11 07:15:30 PM PDT 24
Finished Aug 11 07:15:32 PM PDT 24
Peak memory 207608 kb
Host smart-f89aadb5-c727-4346-8c4d-c5f1fd2ad96c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=504030229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.504030229
Directory /workspace/40.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/40.usbdev_device_address.3356844042
Short name T2082
Test name
Test status
Simulation time 35493814770 ps
CPU time 59.03 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:16:25 PM PDT 24
Peak memory 207880 kb
Host smart-936aaa2c-6a6f-48c7-ab17-f68c69cc52d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33568
44042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3356844042
Directory /workspace/40.usbdev_device_address/latest


Test location /workspace/coverage/default/40.usbdev_device_timeout.1179529142
Short name T760
Test name
Test status
Simulation time 5666699741 ps
CPU time 36.6 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:57 PM PDT 24
Peak memory 207712 kb
Host smart-e042336d-d8ec-40ae-89b2-fa665d1e81f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179529142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.1179529142
Directory /workspace/40.usbdev_device_timeout/latest


Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1084116641
Short name T1530
Test name
Test status
Simulation time 721365760 ps
CPU time 1.81 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 207532 kb
Host smart-45444d3e-09fe-4294-a8bf-380b039426f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10841
16641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1084116641
Directory /workspace/40.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/40.usbdev_disconnected.2864292412
Short name T640
Test name
Test status
Simulation time 180149092 ps
CPU time 0.88 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207536 kb
Host smart-8f2fa377-6f6b-428f-a85c-d3e8abceb9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28642
92412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2864292412
Directory /workspace/40.usbdev_disconnected/latest


Test location /workspace/coverage/default/40.usbdev_enable.2874916652
Short name T702
Test name
Test status
Simulation time 71730858 ps
CPU time 0.78 seconds
Started Aug 11 07:15:27 PM PDT 24
Finished Aug 11 07:15:28 PM PDT 24
Peak memory 207536 kb
Host smart-6c12f612-e743-4b55-828a-117fff28e7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28749
16652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2874916652
Directory /workspace/40.usbdev_enable/latest


Test location /workspace/coverage/default/40.usbdev_endpoint_access.236323528
Short name T2706
Test name
Test status
Simulation time 857168301 ps
CPU time 2.26 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 207796 kb
Host smart-dd995581-57d8-4da4-86e9-223f44276916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23632
3528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.236323528
Directory /workspace/40.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/40.usbdev_endpoint_types.3202353091
Short name T445
Test name
Test status
Simulation time 469361721 ps
CPU time 1.23 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:21 PM PDT 24
Peak memory 207484 kb
Host smart-c01b4e74-29a0-4ae7-8867-2ae70db47c1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3202353091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.3202353091
Directory /workspace/40.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/40.usbdev_fifo_rst.25899296
Short name T1199
Test name
Test status
Simulation time 175737194 ps
CPU time 1.51 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207648 kb
Host smart-6eb30798-4331-4f39-955c-97aea618720e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25899
296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.25899296
Directory /workspace/40.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/40.usbdev_in_stall.3417034704
Short name T2346
Test name
Test status
Simulation time 148117943 ps
CPU time 0.86 seconds
Started Aug 11 07:15:25 PM PDT 24
Finished Aug 11 07:15:26 PM PDT 24
Peak memory 207520 kb
Host smart-7c8ab1a7-7f87-4679-9b57-76cd2d0f0a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34170
34704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3417034704
Directory /workspace/40.usbdev_in_stall/latest


Test location /workspace/coverage/default/40.usbdev_in_trans.133226399
Short name T3094
Test name
Test status
Simulation time 238295264 ps
CPU time 0.99 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:21 PM PDT 24
Peak memory 207560 kb
Host smart-1815457b-6150-498a-a5b2-58c5990e5c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13322
6399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.133226399
Directory /workspace/40.usbdev_in_trans/latest


Test location /workspace/coverage/default/40.usbdev_invalid_sync.974067923
Short name T3457
Test name
Test status
Simulation time 4412426002 ps
CPU time 32.83 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:55 PM PDT 24
Peak memory 224244 kb
Host smart-afeb9a8d-6a7b-47de-80be-96254a60e725
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=974067923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.974067923
Directory /workspace/40.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/40.usbdev_iso_retraction.429970846
Short name T95
Test name
Test status
Simulation time 8866530330 ps
CPU time 65.57 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:16:24 PM PDT 24
Peak memory 207804 kb
Host smart-faf9e38b-b53d-4de3-a93d-e63b4894bc9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=429970846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.429970846
Directory /workspace/40.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/40.usbdev_link_in_err.769075480
Short name T661
Test name
Test status
Simulation time 186141147 ps
CPU time 0.89 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:21 PM PDT 24
Peak memory 207588 kb
Host smart-ece17e85-876c-4d82-a7c3-ea3f1f0d8d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76907
5480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.769075480
Directory /workspace/40.usbdev_link_in_err/latest


Test location /workspace/coverage/default/40.usbdev_link_resume.2308507100
Short name T3413
Test name
Test status
Simulation time 32741291620 ps
CPU time 51.68 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:16:12 PM PDT 24
Peak memory 207860 kb
Host smart-e581883f-3f0c-4632-9181-efc1cdffbf7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23085
07100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.2308507100
Directory /workspace/40.usbdev_link_resume/latest


Test location /workspace/coverage/default/40.usbdev_link_suspend.852261694
Short name T1506
Test name
Test status
Simulation time 10689335085 ps
CPU time 12.17 seconds
Started Aug 11 07:15:24 PM PDT 24
Finished Aug 11 07:15:36 PM PDT 24
Peak memory 207812 kb
Host smart-49c2be45-d249-42d8-96a9-23f3f1f1afcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85226
1694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.852261694
Directory /workspace/40.usbdev_link_suspend/latest


Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.4037017274
Short name T1306
Test name
Test status
Simulation time 2934621447 ps
CPU time 21.86 seconds
Started Aug 11 07:15:27 PM PDT 24
Finished Aug 11 07:15:49 PM PDT 24
Peak memory 219108 kb
Host smart-8fcd1525-bc0e-4d85-84d0-6d594edbb8b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4037017274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.4037017274
Directory /workspace/40.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2340581959
Short name T2936
Test name
Test status
Simulation time 2289048031 ps
CPU time 22.09 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 217552 kb
Host smart-76fefe47-3a1b-43e6-868c-3f79eed6cbbc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2340581959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2340581959
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.107437879
Short name T692
Test name
Test status
Simulation time 238943925 ps
CPU time 1.02 seconds
Started Aug 11 07:15:29 PM PDT 24
Finished Aug 11 07:15:30 PM PDT 24
Peak memory 207500 kb
Host smart-642a3a51-b689-4b39-b03f-56a2f19d1959
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=107437879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.107437879
Directory /workspace/40.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.172042217
Short name T2437
Test name
Test status
Simulation time 226280562 ps
CPU time 1.02 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:21 PM PDT 24
Peak memory 207492 kb
Host smart-0a4ccf1e-e594-4fb8-a6c0-e1f370988ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17204
2217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.172042217
Directory /workspace/40.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1479096830
Short name T1185
Test name
Test status
Simulation time 3057291734 ps
CPU time 87.08 seconds
Started Aug 11 07:15:28 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 216072 kb
Host smart-f04aa499-e3f2-433e-b068-339ee0642bd7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1479096830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1479096830
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.1002736587
Short name T679
Test name
Test status
Simulation time 223750686 ps
CPU time 1 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207552 kb
Host smart-6138bb06-2cad-4d1d-9a36-cffad555a038
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1002736587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.1002736587
Directory /workspace/40.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2917690160
Short name T2705
Test name
Test status
Simulation time 187461182 ps
CPU time 0.88 seconds
Started Aug 11 07:15:27 PM PDT 24
Finished Aug 11 07:15:28 PM PDT 24
Peak memory 207508 kb
Host smart-c93e74f7-4a2e-49fd-8322-3343502b20f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29176
90160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2917690160
Directory /workspace/40.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_nak_trans.1979474231
Short name T3290
Test name
Test status
Simulation time 233093670 ps
CPU time 1.03 seconds
Started Aug 11 07:15:16 PM PDT 24
Finished Aug 11 07:15:17 PM PDT 24
Peak memory 207548 kb
Host smart-cd7413c9-f337-43c0-8079-2b8666778eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
74231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1979474231
Directory /workspace/40.usbdev_nak_trans/latest


Test location /workspace/coverage/default/40.usbdev_out_iso.4115390996
Short name T560
Test name
Test status
Simulation time 162879088 ps
CPU time 0.88 seconds
Started Aug 11 07:15:23 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 207584 kb
Host smart-d1d2bd56-bfdf-401e-90f5-8cca33bfe58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41153
90996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.4115390996
Directory /workspace/40.usbdev_out_iso/latest


Test location /workspace/coverage/default/40.usbdev_out_stall.1496462219
Short name T2483
Test name
Test status
Simulation time 185763309 ps
CPU time 0.9 seconds
Started Aug 11 07:15:23 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 207516 kb
Host smart-e2bc23ac-799f-448f-84d7-658dadb32f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14964
62219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1496462219
Directory /workspace/40.usbdev_out_stall/latest


Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2176688303
Short name T622
Test name
Test status
Simulation time 192711677 ps
CPU time 0.94 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207548 kb
Host smart-28eba443-74a8-4ff8-9c89-d9b3909a7ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21766
88303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2176688303
Directory /workspace/40.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1703321365
Short name T3277
Test name
Test status
Simulation time 190476338 ps
CPU time 0.93 seconds
Started Aug 11 07:15:16 PM PDT 24
Finished Aug 11 07:15:17 PM PDT 24
Peak memory 207544 kb
Host smart-81e9fbd9-09ff-4133-a3ac-2b498a259568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
21365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1703321365
Directory /workspace/40.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3540465802
Short name T585
Test name
Test status
Simulation time 226022809 ps
CPU time 1.01 seconds
Started Aug 11 07:15:27 PM PDT 24
Finished Aug 11 07:15:28 PM PDT 24
Peak memory 207532 kb
Host smart-e3028c9f-056d-48ee-8984-9bd38684844a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3540465802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3540465802
Directory /workspace/40.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1103171591
Short name T2316
Test name
Test status
Simulation time 140745431 ps
CPU time 0.83 seconds
Started Aug 11 07:15:23 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 207424 kb
Host smart-ce4ed023-8134-41e8-b202-a614423a9272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11031
71591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1103171591
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3395851190
Short name T397
Test name
Test status
Simulation time 12141857454 ps
CPU time 27.12 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:47 PM PDT 24
Peak memory 216052 kb
Host smart-33e3eb93-2ecd-4b54-866f-7b75f791222b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33958
51190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3395851190
Directory /workspace/40.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/40.usbdev_pkt_received.3883636217
Short name T2592
Test name
Test status
Simulation time 186403922 ps
CPU time 0.95 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207556 kb
Host smart-39193c6a-f8a7-4674-9866-abe3b038f4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38836
36217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3883636217
Directory /workspace/40.usbdev_pkt_received/latest


Test location /workspace/coverage/default/40.usbdev_pkt_sent.3539987054
Short name T3325
Test name
Test status
Simulation time 226507404 ps
CPU time 0.94 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207544 kb
Host smart-7f11b51f-24d9-40ed-99b7-41da5163b7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35399
87054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3539987054
Directory /workspace/40.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.888256598
Short name T2123
Test name
Test status
Simulation time 184143482 ps
CPU time 0.93 seconds
Started Aug 11 07:15:35 PM PDT 24
Finished Aug 11 07:15:36 PM PDT 24
Peak memory 207756 kb
Host smart-5ba4bfda-41ea-45bd-8aad-d60686ebd104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88825
6598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.888256598
Directory /workspace/40.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.316374903
Short name T3427
Test name
Test status
Simulation time 173533041 ps
CPU time 0.88 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:15:48 PM PDT 24
Peak memory 207556 kb
Host smart-c292e76d-5a4d-4c2b-841e-2536a7b6fbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31637
4903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.316374903
Directory /workspace/40.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_rx_crc_err.812034591
Short name T1981
Test name
Test status
Simulation time 185932351 ps
CPU time 0.88 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:23 PM PDT 24
Peak memory 207504 kb
Host smart-ecec8c4c-3f01-459e-b3a2-60bd01790ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81203
4591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.812034591
Directory /workspace/40.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/40.usbdev_rx_full.2817206213
Short name T1222
Test name
Test status
Simulation time 365125828 ps
CPU time 1.23 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 207576 kb
Host smart-63ec7035-6beb-420d-97f2-757f0b71f872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28172
06213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.2817206213
Directory /workspace/40.usbdev_rx_full/latest


Test location /workspace/coverage/default/40.usbdev_setup_stage.152484901
Short name T1013
Test name
Test status
Simulation time 147644620 ps
CPU time 0.84 seconds
Started Aug 11 07:15:33 PM PDT 24
Finished Aug 11 07:15:34 PM PDT 24
Peak memory 207484 kb
Host smart-f69baf48-0492-4c8e-a4f7-ac177e5ab28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15248
4901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.152484901
Directory /workspace/40.usbdev_setup_stage/latest


Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.137525722
Short name T3632
Test name
Test status
Simulation time 147001701 ps
CPU time 0.94 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:23 PM PDT 24
Peak memory 207572 kb
Host smart-3c952a4c-eb79-4b15-8f82-7cbcf58a7440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13752
5722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.137525722
Directory /workspace/40.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/40.usbdev_smoke.866853012
Short name T3212
Test name
Test status
Simulation time 205571880 ps
CPU time 0.97 seconds
Started Aug 11 07:15:17 PM PDT 24
Finished Aug 11 07:15:18 PM PDT 24
Peak memory 207516 kb
Host smart-82b82c59-e315-4215-990f-eb1f4e4620d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86685
3012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.866853012
Directory /workspace/40.usbdev_smoke/latest


Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1848425971
Short name T1929
Test name
Test status
Simulation time 2390639047 ps
CPU time 18.88 seconds
Started Aug 11 07:15:42 PM PDT 24
Finished Aug 11 07:16:01 PM PDT 24
Peak memory 216260 kb
Host smart-590e0ec0-36f6-4d1f-b2d1-d1242a8df4de
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1848425971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1848425971
Directory /workspace/40.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3768236287
Short name T2846
Test name
Test status
Simulation time 176823371 ps
CPU time 0.92 seconds
Started Aug 11 07:15:23 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 207572 kb
Host smart-3f008398-5bbd-4b6a-b744-524be161b1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37682
36287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3768236287
Directory /workspace/40.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/40.usbdev_stall_trans.51299321
Short name T2688
Test name
Test status
Simulation time 186563459 ps
CPU time 0.94 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207568 kb
Host smart-26284d79-58c2-4ef4-9f92-2acfb7bc3df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51299
321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.51299321
Directory /workspace/40.usbdev_stall_trans/latest


Test location /workspace/coverage/default/40.usbdev_stream_len_max.3397427377
Short name T613
Test name
Test status
Simulation time 398468874 ps
CPU time 1.3 seconds
Started Aug 11 07:15:25 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 207516 kb
Host smart-a6929d37-7d89-4031-a84c-087961c8f596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33974
27377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3397427377
Directory /workspace/40.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/40.usbdev_streaming_out.913508596
Short name T2210
Test name
Test status
Simulation time 2747939568 ps
CPU time 20.33 seconds
Started Aug 11 07:15:34 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 217564 kb
Host smart-db207349-7d6d-4982-a8d1-f9d6ff244680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91350
8596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.913508596
Directory /workspace/40.usbdev_streaming_out/latest


Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.2474734730
Short name T1680
Test name
Test status
Simulation time 5256522907 ps
CPU time 44.43 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:16:10 PM PDT 24
Peak memory 207844 kb
Host smart-ee0a5c89-b52b-4c3f-8a53-d47887f1e8e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474734730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.2474734730
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/40.usbdev_tx_rx_disruption.3769959309
Short name T198
Test name
Test status
Simulation time 529324314 ps
CPU time 1.58 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 207560 kb
Host smart-75d3d19a-c7c6-412d-a0f2-933c3ea87b3d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769959309 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.usbdev_tx_rx_disruption.3769959309
Directory /workspace/40.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/400.usbdev_tx_rx_disruption.3437171680
Short name T255
Test name
Test status
Simulation time 586086781 ps
CPU time 1.76 seconds
Started Aug 11 07:18:03 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207504 kb
Host smart-6798a6f0-5358-48de-92df-259350577796
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437171680 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 400.usbdev_tx_rx_disruption.3437171680
Directory /workspace/400.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/401.usbdev_tx_rx_disruption.846322703
Short name T3604
Test name
Test status
Simulation time 527268689 ps
CPU time 1.59 seconds
Started Aug 11 07:17:48 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207480 kb
Host smart-12dc101e-84b9-45ad-9f25-96bbec147313
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846322703 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 401.usbdev_tx_rx_disruption.846322703
Directory /workspace/401.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/402.usbdev_tx_rx_disruption.3731296008
Short name T3503
Test name
Test status
Simulation time 580102911 ps
CPU time 1.8 seconds
Started Aug 11 07:17:51 PM PDT 24
Finished Aug 11 07:17:53 PM PDT 24
Peak memory 207564 kb
Host smart-77426e36-950e-4c01-abc3-f4f6ed8d65f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731296008 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 402.usbdev_tx_rx_disruption.3731296008
Directory /workspace/402.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/403.usbdev_tx_rx_disruption.1263302453
Short name T3065
Test name
Test status
Simulation time 512084387 ps
CPU time 1.54 seconds
Started Aug 11 07:17:56 PM PDT 24
Finished Aug 11 07:18:01 PM PDT 24
Peak memory 207564 kb
Host smart-d270ba50-8041-4e71-8047-6be7a47d850c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263302453 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 403.usbdev_tx_rx_disruption.1263302453
Directory /workspace/403.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/404.usbdev_tx_rx_disruption.722825604
Short name T1434
Test name
Test status
Simulation time 512724644 ps
CPU time 1.61 seconds
Started Aug 11 07:17:58 PM PDT 24
Finished Aug 11 07:18:00 PM PDT 24
Peak memory 207548 kb
Host smart-1314ab46-6eb4-40a9-b9a3-9dfd929b6867
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722825604 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 404.usbdev_tx_rx_disruption.722825604
Directory /workspace/404.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/405.usbdev_tx_rx_disruption.699680478
Short name T93
Test name
Test status
Simulation time 566872651 ps
CPU time 1.54 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207564 kb
Host smart-e1e7433e-4559-44a1-bb58-f88ac2606fc5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699680478 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 405.usbdev_tx_rx_disruption.699680478
Directory /workspace/405.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/406.usbdev_tx_rx_disruption.3903079931
Short name T3129
Test name
Test status
Simulation time 545943799 ps
CPU time 1.47 seconds
Started Aug 11 07:17:58 PM PDT 24
Finished Aug 11 07:18:00 PM PDT 24
Peak memory 207548 kb
Host smart-2a677ff1-c1a5-4eca-a751-c7841f91d15b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903079931 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 406.usbdev_tx_rx_disruption.3903079931
Directory /workspace/406.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/407.usbdev_tx_rx_disruption.2741316203
Short name T1300
Test name
Test status
Simulation time 576931265 ps
CPU time 1.61 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207568 kb
Host smart-3b66d633-385c-4d1c-84fd-e9140bab0a28
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741316203 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 407.usbdev_tx_rx_disruption.2741316203
Directory /workspace/407.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/408.usbdev_tx_rx_disruption.885982218
Short name T840
Test name
Test status
Simulation time 409612305 ps
CPU time 1.34 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207544 kb
Host smart-87e6abad-6519-4ac6-8923-6a639c713d9c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885982218 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 408.usbdev_tx_rx_disruption.885982218
Directory /workspace/408.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/409.usbdev_tx_rx_disruption.2535605933
Short name T612
Test name
Test status
Simulation time 636761100 ps
CPU time 1.62 seconds
Started Aug 11 07:18:01 PM PDT 24
Finished Aug 11 07:18:03 PM PDT 24
Peak memory 207576 kb
Host smart-f1ac19ab-c864-4680-9a82-9287f59d2d70
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535605933 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 409.usbdev_tx_rx_disruption.2535605933
Directory /workspace/409.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/41.usbdev_alert_test.4016696301
Short name T3563
Test name
Test status
Simulation time 57808921 ps
CPU time 0.66 seconds
Started Aug 11 07:15:41 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 207628 kb
Host smart-bc9d8895-7faf-4580-ae2f-c8338aa04045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4016696301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.4016696301
Directory /workspace/41.usbdev_alert_test/latest


Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3686026139
Short name T1346
Test name
Test status
Simulation time 9160624803 ps
CPU time 11.58 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:32 PM PDT 24
Peak memory 207836 kb
Host smart-d5de2310-1a32-4a03-94a5-dbf275a06c87
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686026139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.3686026139
Directory /workspace/41.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3290304112
Short name T3417
Test name
Test status
Simulation time 19940392573 ps
CPU time 28.15 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:50 PM PDT 24
Peak memory 207828 kb
Host smart-c32c55a9-4c1d-41d9-bacb-bfbd5604a27f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290304112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3290304112
Directory /workspace/41.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2896639367
Short name T3301
Test name
Test status
Simulation time 30108301706 ps
CPU time 37.91 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:59 PM PDT 24
Peak memory 207856 kb
Host smart-a803660f-95bb-4994-a20a-e6f4ecc056db
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896639367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.2896639367
Directory /workspace/41.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/41.usbdev_av_buffer.3385692095
Short name T824
Test name
Test status
Simulation time 164852892 ps
CPU time 0.82 seconds
Started Aug 11 07:15:30 PM PDT 24
Finished Aug 11 07:15:31 PM PDT 24
Peak memory 207396 kb
Host smart-afca5606-862b-48e1-bb53-57b9bed3ed7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33856
92095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3385692095
Directory /workspace/41.usbdev_av_buffer/latest


Test location /workspace/coverage/default/41.usbdev_bitstuff_err.4198420556
Short name T3602
Test name
Test status
Simulation time 144058875 ps
CPU time 0.83 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 207580 kb
Host smart-72df34e1-743d-4b52-b9c2-01697b2a92bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41984
20556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.4198420556
Directory /workspace/41.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.4044717205
Short name T3085
Test name
Test status
Simulation time 477519181 ps
CPU time 1.58 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 207504 kb
Host smart-844590b0-abbd-4cc2-a120-51650ccca5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40447
17205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.4044717205
Directory /workspace/41.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.634876640
Short name T352
Test name
Test status
Simulation time 710952944 ps
CPU time 2.01 seconds
Started Aug 11 07:15:25 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 207672 kb
Host smart-71efb08f-cb32-423b-99f3-9cdfc27049d8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=634876640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.634876640
Directory /workspace/41.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/41.usbdev_device_address.3212816152
Short name T2708
Test name
Test status
Simulation time 44861907227 ps
CPU time 72.79 seconds
Started Aug 11 07:15:17 PM PDT 24
Finished Aug 11 07:16:30 PM PDT 24
Peak memory 207808 kb
Host smart-a1070bdb-1aff-491c-ac3e-6b2e392927b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32128
16152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.3212816152
Directory /workspace/41.usbdev_device_address/latest


Test location /workspace/coverage/default/41.usbdev_device_timeout.2346630270
Short name T821
Test name
Test status
Simulation time 882338804 ps
CPU time 18.51 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:40 PM PDT 24
Peak memory 207680 kb
Host smart-4342d7db-94cc-418e-a174-9ac08e20e945
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346630270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.2346630270
Directory /workspace/41.usbdev_device_timeout/latest


Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2176898986
Short name T1998
Test name
Test status
Simulation time 778210008 ps
CPU time 1.93 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:15:28 PM PDT 24
Peak memory 207460 kb
Host smart-0f03c62e-e8f4-44a4-9a3f-8a088f4f3fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21768
98986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2176898986
Directory /workspace/41.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/41.usbdev_disconnected.828255923
Short name T2522
Test name
Test status
Simulation time 146848183 ps
CPU time 0.82 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207536 kb
Host smart-2eeb825a-7ba9-474f-b4d7-fd1d0bff5055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82825
5923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.828255923
Directory /workspace/41.usbdev_disconnected/latest


Test location /workspace/coverage/default/41.usbdev_enable.4112398689
Short name T1409
Test name
Test status
Simulation time 45787298 ps
CPU time 0.78 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:21 PM PDT 24
Peak memory 207456 kb
Host smart-31b0879c-eed3-41e9-830b-c345a9b30004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41123
98689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.4112398689
Directory /workspace/41.usbdev_enable/latest


Test location /workspace/coverage/default/41.usbdev_endpoint_access.2826424458
Short name T856
Test name
Test status
Simulation time 723996161 ps
CPU time 2.11 seconds
Started Aug 11 07:15:29 PM PDT 24
Finished Aug 11 07:15:32 PM PDT 24
Peak memory 207752 kb
Host smart-234ea2b3-4575-4464-a738-a43ebb323bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28264
24458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2826424458
Directory /workspace/41.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/41.usbdev_endpoint_types.4255239054
Short name T3476
Test name
Test status
Simulation time 307464583 ps
CPU time 1.16 seconds
Started Aug 11 07:15:28 PM PDT 24
Finished Aug 11 07:15:29 PM PDT 24
Peak memory 207568 kb
Host smart-4247239c-591a-47c8-9beb-7f848738b1c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4255239054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.4255239054
Directory /workspace/41.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/41.usbdev_fifo_rst.1976671622
Short name T886
Test name
Test status
Simulation time 330196586 ps
CPU time 2.46 seconds
Started Aug 11 07:15:23 PM PDT 24
Finished Aug 11 07:15:26 PM PDT 24
Peak memory 207644 kb
Host smart-78bf2744-a92f-4a2e-9bd1-8505b06ee110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19766
71622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1976671622
Directory /workspace/41.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/41.usbdev_in_iso.1715258749
Short name T3294
Test name
Test status
Simulation time 243324113 ps
CPU time 1.23 seconds
Started Aug 11 07:15:35 PM PDT 24
Finished Aug 11 07:15:36 PM PDT 24
Peak memory 215952 kb
Host smart-45fc86c4-a716-4427-9d5d-583795f7106f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1715258749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1715258749
Directory /workspace/41.usbdev_in_iso/latest


Test location /workspace/coverage/default/41.usbdev_in_stall.596573643
Short name T2378
Test name
Test status
Simulation time 168177048 ps
CPU time 0.83 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 207452 kb
Host smart-f9d96d59-7ad4-4161-803a-83b3788e7bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59657
3643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.596573643
Directory /workspace/41.usbdev_in_stall/latest


Test location /workspace/coverage/default/41.usbdev_in_trans.3539976631
Short name T3600
Test name
Test status
Simulation time 206293869 ps
CPU time 0.96 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 207744 kb
Host smart-b43320d8-22ad-471a-8062-fb554f0aec31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35399
76631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3539976631
Directory /workspace/41.usbdev_in_trans/latest


Test location /workspace/coverage/default/41.usbdev_invalid_sync.2652273988
Short name T1583
Test name
Test status
Simulation time 4544404347 ps
CPU time 45.9 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:16:07 PM PDT 24
Peak memory 218492 kb
Host smart-4b1bcf62-5210-4ad5-85c3-98e76d84da1d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2652273988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2652273988
Directory /workspace/41.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/41.usbdev_iso_retraction.258858914
Short name T2467
Test name
Test status
Simulation time 10176798721 ps
CPU time 132.2 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 207828 kb
Host smart-86600e2c-f799-439d-9699-060abcef30d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=258858914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.258858914
Directory /workspace/41.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/41.usbdev_link_in_err.3562898989
Short name T2598
Test name
Test status
Simulation time 238470384 ps
CPU time 0.97 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207572 kb
Host smart-c5afb603-3b02-47c2-b02f-d48b9a8998a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35628
98989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3562898989
Directory /workspace/41.usbdev_link_in_err/latest


Test location /workspace/coverage/default/41.usbdev_link_resume.654666982
Short name T2167
Test name
Test status
Simulation time 13842471005 ps
CPU time 19 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 207876 kb
Host smart-aa8054cb-faef-4300-a870-a0d5c266ee82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65466
6982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.654666982
Directory /workspace/41.usbdev_link_resume/latest


Test location /workspace/coverage/default/41.usbdev_link_suspend.3992759914
Short name T116
Test name
Test status
Simulation time 10688914699 ps
CPU time 14.24 seconds
Started Aug 11 07:15:24 PM PDT 24
Finished Aug 11 07:15:38 PM PDT 24
Peak memory 207844 kb
Host smart-37917f12-d153-4a97-8756-a9ecfd3939d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39927
59914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3992759914
Directory /workspace/41.usbdev_link_suspend/latest


Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.3537820239
Short name T2554
Test name
Test status
Simulation time 2375622081 ps
CPU time 17.72 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:38 PM PDT 24
Peak memory 216048 kb
Host smart-bdc19c87-8a9f-4499-a137-31617222b5d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3537820239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3537820239
Directory /workspace/41.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1688618860
Short name T1595
Test name
Test status
Simulation time 3768778774 ps
CPU time 38.82 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:57 PM PDT 24
Peak memory 217788 kb
Host smart-f2bece3c-1ebf-408e-a8f0-a2fe28dd0330
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1688618860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1688618860
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.4182405474
Short name T3601
Test name
Test status
Simulation time 269318454 ps
CPU time 1.09 seconds
Started Aug 11 07:15:30 PM PDT 24
Finished Aug 11 07:15:31 PM PDT 24
Peak memory 207528 kb
Host smart-2b2d9126-fec5-4453-8f43-181c745acc17
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4182405474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.4182405474
Directory /workspace/41.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.890533769
Short name T2526
Test name
Test status
Simulation time 188663804 ps
CPU time 0.92 seconds
Started Aug 11 07:15:24 PM PDT 24
Finished Aug 11 07:15:25 PM PDT 24
Peak memory 207572 kb
Host smart-c6ebc9da-661d-40d0-a860-34ac5715a6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89053
3769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.890533769
Directory /workspace/41.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.3507840704
Short name T2276
Test name
Test status
Simulation time 4049306342 ps
CPU time 32.7 seconds
Started Aug 11 07:15:25 PM PDT 24
Finished Aug 11 07:15:57 PM PDT 24
Peak memory 217856 kb
Host smart-96658ddf-774c-497f-b24b-9828e69e60a2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3507840704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.3507840704
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2174589037
Short name T1965
Test name
Test status
Simulation time 156473120 ps
CPU time 0.87 seconds
Started Aug 11 07:15:35 PM PDT 24
Finished Aug 11 07:15:36 PM PDT 24
Peak memory 207564 kb
Host smart-20025d21-f73f-49a8-8341-a40d7fa9d083
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2174589037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2174589037
Directory /workspace/41.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.799353178
Short name T1605
Test name
Test status
Simulation time 152734184 ps
CPU time 0.83 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:23 PM PDT 24
Peak memory 207516 kb
Host smart-cee4a823-3d56-4e78-8ed3-52896777689d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79935
3178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.799353178
Directory /workspace/41.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_nak_trans.2556482770
Short name T3257
Test name
Test status
Simulation time 209857330 ps
CPU time 0.91 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207548 kb
Host smart-14bb2d8c-b079-4f75-9830-5c138f2436fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25564
82770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2556482770
Directory /workspace/41.usbdev_nak_trans/latest


Test location /workspace/coverage/default/41.usbdev_out_iso.1238504311
Short name T1144
Test name
Test status
Simulation time 157107124 ps
CPU time 0.84 seconds
Started Aug 11 07:15:21 PM PDT 24
Finished Aug 11 07:15:22 PM PDT 24
Peak memory 207592 kb
Host smart-266c5eb5-bc10-4b29-8c84-b01458e822f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385
04311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1238504311
Directory /workspace/41.usbdev_out_iso/latest


Test location /workspace/coverage/default/41.usbdev_out_stall.801320912
Short name T2262
Test name
Test status
Simulation time 199023307 ps
CPU time 0.93 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:23 PM PDT 24
Peak memory 207492 kb
Host smart-28a74665-36a3-4366-851b-546f8f099d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80132
0912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.801320912
Directory /workspace/41.usbdev_out_stall/latest


Test location /workspace/coverage/default/41.usbdev_out_trans_nak.529120132
Short name T1270
Test name
Test status
Simulation time 166574748 ps
CPU time 0.85 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 207584 kb
Host smart-e3461a95-584c-44e6-861e-fb6128b49d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52912
0132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.529120132
Directory /workspace/41.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2712678951
Short name T3073
Test name
Test status
Simulation time 162553357 ps
CPU time 0.86 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 207492 kb
Host smart-b4d55229-564d-455a-8054-50b90b4547d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27126
78951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2712678951
Directory /workspace/41.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.920032362
Short name T1939
Test name
Test status
Simulation time 278832349 ps
CPU time 1.16 seconds
Started Aug 11 07:15:18 PM PDT 24
Finished Aug 11 07:15:19 PM PDT 24
Peak memory 207536 kb
Host smart-d98ef778-7334-4f1d-826d-d50f9f03d339
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=920032362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.920032362
Directory /workspace/41.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2617830940
Short name T578
Test name
Test status
Simulation time 196560586 ps
CPU time 0.87 seconds
Started Aug 11 07:15:24 PM PDT 24
Finished Aug 11 07:15:25 PM PDT 24
Peak memory 207548 kb
Host smart-9346b577-2fa7-4313-8280-6e5bcdfa2d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26178
30940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2617830940
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.299566166
Short name T2068
Test name
Test status
Simulation time 62937993 ps
CPU time 0.71 seconds
Started Aug 11 07:15:35 PM PDT 24
Finished Aug 11 07:15:35 PM PDT 24
Peak memory 207468 kb
Host smart-fa6b8ac6-2bec-4377-acc9-60566c33556e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29956
6166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.299566166
Directory /workspace/41.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/41.usbdev_pkt_buffer.421592925
Short name T1464
Test name
Test status
Simulation time 12043816479 ps
CPU time 33.63 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:55 PM PDT 24
Peak memory 216004 kb
Host smart-c20c371d-e44b-47a9-af53-4ad4cc1bc2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42159
2925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.421592925
Directory /workspace/41.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/41.usbdev_pkt_received.1735246407
Short name T3196
Test name
Test status
Simulation time 170113867 ps
CPU time 0.89 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:15:27 PM PDT 24
Peak memory 207504 kb
Host smart-5a8bbe9c-bb38-42d6-9a0b-4717eafacbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17352
46407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1735246407
Directory /workspace/41.usbdev_pkt_received/latest


Test location /workspace/coverage/default/41.usbdev_pkt_sent.264748456
Short name T977
Test name
Test status
Simulation time 203594231 ps
CPU time 0.95 seconds
Started Aug 11 07:15:19 PM PDT 24
Finished Aug 11 07:15:20 PM PDT 24
Peak memory 207480 kb
Host smart-b82edb92-a14b-48d9-a63a-6278063bce52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26474
8456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.264748456
Directory /workspace/41.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3814424530
Short name T722
Test name
Test status
Simulation time 283524839 ps
CPU time 1.01 seconds
Started Aug 11 07:15:23 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 207552 kb
Host smart-9bf93d46-fbd8-4b73-9b3a-aec7b387926b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
24530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3814424530
Directory /workspace/41.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.382430995
Short name T1668
Test name
Test status
Simulation time 174810119 ps
CPU time 0.87 seconds
Started Aug 11 07:15:25 PM PDT 24
Finished Aug 11 07:15:26 PM PDT 24
Peak memory 207544 kb
Host smart-6661038b-ee47-4aab-bd3b-5243cab593fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38243
0995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.382430995
Directory /workspace/41.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1624798105
Short name T998
Test name
Test status
Simulation time 176498016 ps
CPU time 0.9 seconds
Started Aug 11 07:15:34 PM PDT 24
Finished Aug 11 07:15:35 PM PDT 24
Peak memory 207536 kb
Host smart-f3747dc5-70bb-4a85-8bd7-768dfc32708f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16247
98105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1624798105
Directory /workspace/41.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/41.usbdev_rx_full.4002439896
Short name T2476
Test name
Test status
Simulation time 357695395 ps
CPU time 1.24 seconds
Started Aug 11 07:15:34 PM PDT 24
Finished Aug 11 07:15:35 PM PDT 24
Peak memory 207460 kb
Host smart-5d80817b-47bf-4284-88fb-40c965613b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40024
39896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.4002439896
Directory /workspace/41.usbdev_rx_full/latest


Test location /workspace/coverage/default/41.usbdev_setup_stage.2063597047
Short name T3570
Test name
Test status
Simulation time 151119058 ps
CPU time 0.83 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:23 PM PDT 24
Peak memory 207444 kb
Host smart-120fa029-b57e-4188-a1cf-d75242c32ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20635
97047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2063597047
Directory /workspace/41.usbdev_setup_stage/latest


Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.18601963
Short name T3166
Test name
Test status
Simulation time 158398891 ps
CPU time 0.85 seconds
Started Aug 11 07:15:25 PM PDT 24
Finished Aug 11 07:15:26 PM PDT 24
Peak memory 207532 kb
Host smart-c4f82802-418f-4051-a8d2-2f1a6b1f95e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18601
963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.18601963
Directory /workspace/41.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/41.usbdev_smoke.2911872342
Short name T1289
Test name
Test status
Simulation time 237083384 ps
CPU time 1.03 seconds
Started Aug 11 07:15:43 PM PDT 24
Finished Aug 11 07:15:44 PM PDT 24
Peak memory 207596 kb
Host smart-8d8301e7-a544-4f49-a71c-590bf75f8654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29118
72342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2911872342
Directory /workspace/41.usbdev_smoke/latest


Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.1734407546
Short name T2015
Test name
Test status
Simulation time 2313162876 ps
CPU time 67.59 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:16:47 PM PDT 24
Peak memory 217988 kb
Host smart-4903c452-8a9b-4f5e-8a6f-a6877eef41fe
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1734407546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.1734407546
Directory /workspace/41.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.778367895
Short name T1066
Test name
Test status
Simulation time 210038320 ps
CPU time 0.94 seconds
Started Aug 11 07:15:37 PM PDT 24
Finished Aug 11 07:15:38 PM PDT 24
Peak memory 207552 kb
Host smart-e573adc1-865d-4858-9601-1ed469523d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77836
7895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.778367895
Directory /workspace/41.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/41.usbdev_stall_trans.1689275907
Short name T2359
Test name
Test status
Simulation time 186759229 ps
CPU time 0.9 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:40 PM PDT 24
Peak memory 207540 kb
Host smart-6f72e9a8-573c-498a-8603-3149d4a692a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16892
75907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1689275907
Directory /workspace/41.usbdev_stall_trans/latest


Test location /workspace/coverage/default/41.usbdev_stream_len_max.805915130
Short name T1421
Test name
Test status
Simulation time 1087324118 ps
CPU time 2.57 seconds
Started Aug 11 07:15:38 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 207724 kb
Host smart-80bc07c2-fc70-4057-966a-945347bce8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80591
5130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.805915130
Directory /workspace/41.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/41.usbdev_streaming_out.2916205449
Short name T3106
Test name
Test status
Simulation time 3360737143 ps
CPU time 98.96 seconds
Started Aug 11 07:15:27 PM PDT 24
Finished Aug 11 07:17:11 PM PDT 24
Peak memory 217440 kb
Host smart-fe68406e-6dbe-47c3-8f5c-f8a5bf864c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29162
05449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2916205449
Directory /workspace/41.usbdev_streaming_out/latest


Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.71057516
Short name T2239
Test name
Test status
Simulation time 178792509 ps
CPU time 0.89 seconds
Started Aug 11 07:15:20 PM PDT 24
Finished Aug 11 07:15:21 PM PDT 24
Peak memory 207468 kb
Host smart-7e05b627-1b29-4e36-b160-34d763fc0587
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71057516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_host_
handshake.71057516
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/41.usbdev_tx_rx_disruption.1572892923
Short name T2514
Test name
Test status
Simulation time 587096227 ps
CPU time 1.53 seconds
Started Aug 11 07:15:28 PM PDT 24
Finished Aug 11 07:15:30 PM PDT 24
Peak memory 207564 kb
Host smart-aa9459a1-21ff-41da-8272-68159fe068d0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572892923 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.usbdev_tx_rx_disruption.1572892923
Directory /workspace/41.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/410.usbdev_tx_rx_disruption.2152603700
Short name T3329
Test name
Test status
Simulation time 460468214 ps
CPU time 1.59 seconds
Started Aug 11 07:17:53 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 207548 kb
Host smart-4ba07b0d-29de-4ef1-9338-484c6fe4e266
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152603700 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 410.usbdev_tx_rx_disruption.2152603700
Directory /workspace/410.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/411.usbdev_tx_rx_disruption.1959189709
Short name T678
Test name
Test status
Simulation time 516887441 ps
CPU time 1.54 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:07 PM PDT 24
Peak memory 207576 kb
Host smart-6b55532e-bd53-42d8-8ee1-fd1d276cec10
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959189709 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 411.usbdev_tx_rx_disruption.1959189709
Directory /workspace/411.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/412.usbdev_tx_rx_disruption.769058034
Short name T1811
Test name
Test status
Simulation time 442884484 ps
CPU time 1.48 seconds
Started Aug 11 07:18:01 PM PDT 24
Finished Aug 11 07:18:03 PM PDT 24
Peak memory 207516 kb
Host smart-16f06f1f-14a4-44ae-8d5f-86012b70ca6b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769058034 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 412.usbdev_tx_rx_disruption.769058034
Directory /workspace/412.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/413.usbdev_tx_rx_disruption.2029369024
Short name T964
Test name
Test status
Simulation time 517463156 ps
CPU time 1.55 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207516 kb
Host smart-6ca45f75-6952-4dfa-8667-40008d53ca1f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029369024 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 413.usbdev_tx_rx_disruption.2029369024
Directory /workspace/413.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/414.usbdev_tx_rx_disruption.332711783
Short name T1330
Test name
Test status
Simulation time 533001771 ps
CPU time 1.53 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207516 kb
Host smart-4a3f7d5d-8b6c-4e60-b9d0-e42dfdee1550
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332711783 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 414.usbdev_tx_rx_disruption.332711783
Directory /workspace/414.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/415.usbdev_tx_rx_disruption.3954345115
Short name T1500
Test name
Test status
Simulation time 554126150 ps
CPU time 1.68 seconds
Started Aug 11 07:17:48 PM PDT 24
Finished Aug 11 07:17:50 PM PDT 24
Peak memory 207492 kb
Host smart-ae2037d9-3ecc-4029-9077-3a24bd8a303b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954345115 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 415.usbdev_tx_rx_disruption.3954345115
Directory /workspace/415.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/416.usbdev_tx_rx_disruption.3895917625
Short name T2611
Test name
Test status
Simulation time 573308440 ps
CPU time 1.6 seconds
Started Aug 11 07:17:57 PM PDT 24
Finished Aug 11 07:17:58 PM PDT 24
Peak memory 207536 kb
Host smart-2d1a4d8e-6799-4b8d-bb40-6b959d36c5fa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895917625 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 416.usbdev_tx_rx_disruption.3895917625
Directory /workspace/416.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/417.usbdev_tx_rx_disruption.748006097
Short name T1344
Test name
Test status
Simulation time 580508795 ps
CPU time 1.61 seconds
Started Aug 11 07:18:08 PM PDT 24
Finished Aug 11 07:18:10 PM PDT 24
Peak memory 207572 kb
Host smart-8c13450d-04a0-4816-a836-6d9869126ef7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748006097 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 417.usbdev_tx_rx_disruption.748006097
Directory /workspace/417.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/418.usbdev_tx_rx_disruption.909444973
Short name T2165
Test name
Test status
Simulation time 613462429 ps
CPU time 1.62 seconds
Started Aug 11 07:17:57 PM PDT 24
Finished Aug 11 07:18:01 PM PDT 24
Peak memory 207572 kb
Host smart-b0eb3413-2db0-4004-bf4e-316969a94947
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909444973 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 418.usbdev_tx_rx_disruption.909444973
Directory /workspace/418.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/419.usbdev_tx_rx_disruption.494914252
Short name T3209
Test name
Test status
Simulation time 544099019 ps
CPU time 1.71 seconds
Started Aug 11 07:18:09 PM PDT 24
Finished Aug 11 07:18:10 PM PDT 24
Peak memory 207540 kb
Host smart-602075c1-f767-4d59-91b6-17331f3c122d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494914252 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 419.usbdev_tx_rx_disruption.494914252
Directory /workspace/419.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/42.usbdev_alert_test.1436174968
Short name T1063
Test name
Test status
Simulation time 78001862 ps
CPU time 0.68 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:40 PM PDT 24
Peak memory 207588 kb
Host smart-0a6d918f-6bd2-4172-8a36-d901adcc39f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1436174968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1436174968
Directory /workspace/42.usbdev_alert_test/latest


Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1879076199
Short name T118
Test name
Test status
Simulation time 21321042739 ps
CPU time 29.32 seconds
Started Aug 11 07:15:27 PM PDT 24
Finished Aug 11 07:15:56 PM PDT 24
Peak memory 207748 kb
Host smart-0c45e550-5447-4726-83d5-7ed3ddf8cbaa
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879076199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1879076199
Directory /workspace/42.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3713416434
Short name T3432
Test name
Test status
Simulation time 30396316380 ps
CPU time 43 seconds
Started Aug 11 07:15:28 PM PDT 24
Finished Aug 11 07:16:11 PM PDT 24
Peak memory 207796 kb
Host smart-7bc60f8f-ac8d-410d-ad55-a304b62d173f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713416434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.3713416434
Directory /workspace/42.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/42.usbdev_av_buffer.3019347681
Short name T698
Test name
Test status
Simulation time 159219496 ps
CPU time 0.89 seconds
Started Aug 11 07:15:24 PM PDT 24
Finished Aug 11 07:15:25 PM PDT 24
Peak memory 207476 kb
Host smart-24049bec-56ea-4029-9df3-ad94f8f29c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30193
47681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3019347681
Directory /workspace/42.usbdev_av_buffer/latest


Test location /workspace/coverage/default/42.usbdev_bitstuff_err.425616714
Short name T1313
Test name
Test status
Simulation time 157078151 ps
CPU time 0.88 seconds
Started Aug 11 07:15:37 PM PDT 24
Finished Aug 11 07:15:38 PM PDT 24
Peak memory 207484 kb
Host smart-8b21a521-6df1-433d-abe0-36b8cb4e99b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42561
6714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.425616714
Directory /workspace/42.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.1504028020
Short name T1973
Test name
Test status
Simulation time 448551303 ps
CPU time 1.52 seconds
Started Aug 11 07:15:30 PM PDT 24
Finished Aug 11 07:15:31 PM PDT 24
Peak memory 207556 kb
Host smart-c5cd173b-ed63-45f4-b8ca-b4099b3eb648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15040
28020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1504028020
Directory /workspace/42.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1855821439
Short name T358
Test name
Test status
Simulation time 628814558 ps
CPU time 1.84 seconds
Started Aug 11 07:15:32 PM PDT 24
Finished Aug 11 07:15:39 PM PDT 24
Peak memory 207544 kb
Host smart-af1a9554-476d-41da-8798-3af54dc52dab
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1855821439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1855821439
Directory /workspace/42.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/42.usbdev_device_address.1958923666
Short name T2721
Test name
Test status
Simulation time 13717106030 ps
CPU time 22.51 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:16:01 PM PDT 24
Peak memory 207820 kb
Host smart-7b4d244b-8533-4b68-bb2c-fd0e7ddb7bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19589
23666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1958923666
Directory /workspace/42.usbdev_device_address/latest


Test location /workspace/coverage/default/42.usbdev_device_timeout.2099527860
Short name T645
Test name
Test status
Simulation time 569505549 ps
CPU time 12.08 seconds
Started Aug 11 07:15:26 PM PDT 24
Finished Aug 11 07:15:38 PM PDT 24
Peak memory 207728 kb
Host smart-a74a905e-1174-4e4d-8fbe-bca4e7aa4be5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099527860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.2099527860
Directory /workspace/42.usbdev_device_timeout/latest


Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3863450006
Short name T2260
Test name
Test status
Simulation time 875380928 ps
CPU time 2.03 seconds
Started Aug 11 07:15:24 PM PDT 24
Finished Aug 11 07:15:26 PM PDT 24
Peak memory 207512 kb
Host smart-d712730c-510c-4157-b754-adf84d0f2769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634
50006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3863450006
Directory /workspace/42.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/42.usbdev_disconnected.2613707470
Short name T1989
Test name
Test status
Simulation time 131372898 ps
CPU time 0.81 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207516 kb
Host smart-0b8c9603-7ce5-4ff5-8595-214ad5d9fa55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26137
07470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2613707470
Directory /workspace/42.usbdev_disconnected/latest


Test location /workspace/coverage/default/42.usbdev_enable.2991229067
Short name T3444
Test name
Test status
Simulation time 65200446 ps
CPU time 0.76 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207480 kb
Host smart-120233ab-8a81-468f-8cd7-1df6e09f6279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29912
29067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2991229067
Directory /workspace/42.usbdev_enable/latest


Test location /workspace/coverage/default/42.usbdev_endpoint_access.2928696308
Short name T779
Test name
Test status
Simulation time 851632258 ps
CPU time 2.23 seconds
Started Aug 11 07:15:28 PM PDT 24
Finished Aug 11 07:15:31 PM PDT 24
Peak memory 207792 kb
Host smart-216c3776-37b6-45ec-bb42-7efcc759d5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29286
96308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2928696308
Directory /workspace/42.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/42.usbdev_endpoint_types.3229858499
Short name T442
Test name
Test status
Simulation time 340162571 ps
CPU time 1.23 seconds
Started Aug 11 07:15:30 PM PDT 24
Finished Aug 11 07:15:31 PM PDT 24
Peak memory 207508 kb
Host smart-8bcfd956-8dac-4372-9992-bb684638af23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3229858499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.3229858499
Directory /workspace/42.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/42.usbdev_fifo_rst.3823742260
Short name T985
Test name
Test status
Simulation time 215854884 ps
CPU time 2.57 seconds
Started Aug 11 07:15:31 PM PDT 24
Finished Aug 11 07:15:34 PM PDT 24
Peak memory 207656 kb
Host smart-117186cf-de7a-4fa7-9036-a3a35c8bd373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38237
42260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3823742260
Directory /workspace/42.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/42.usbdev_in_iso.3569782329
Short name T3633
Test name
Test status
Simulation time 247030822 ps
CPU time 1.15 seconds
Started Aug 11 07:15:22 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 215944 kb
Host smart-97446610-b0f9-45a6-8dd7-edaa612c5302
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3569782329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3569782329
Directory /workspace/42.usbdev_in_iso/latest


Test location /workspace/coverage/default/42.usbdev_in_stall.2787704179
Short name T1545
Test name
Test status
Simulation time 155923336 ps
CPU time 0.82 seconds
Started Aug 11 07:15:24 PM PDT 24
Finished Aug 11 07:15:25 PM PDT 24
Peak memory 207472 kb
Host smart-3ba2ea38-6e80-49d2-8017-2c1ac15affa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
04179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2787704179
Directory /workspace/42.usbdev_in_stall/latest


Test location /workspace/coverage/default/42.usbdev_in_trans.1183273561
Short name T727
Test name
Test status
Simulation time 252627766 ps
CPU time 1.02 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:40 PM PDT 24
Peak memory 207456 kb
Host smart-f52d6638-fe93-4fd6-9ffc-09d736d3b5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11832
73561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1183273561
Directory /workspace/42.usbdev_in_trans/latest


Test location /workspace/coverage/default/42.usbdev_invalid_sync.885135278
Short name T1028
Test name
Test status
Simulation time 4090694953 ps
CPU time 41.03 seconds
Started Aug 11 07:15:25 PM PDT 24
Finished Aug 11 07:16:06 PM PDT 24
Peak memory 218404 kb
Host smart-fd35d0c2-0636-424a-a1d8-7edd4449e605
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=885135278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.885135278
Directory /workspace/42.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/42.usbdev_iso_retraction.179350164
Short name T1455
Test name
Test status
Simulation time 7571874981 ps
CPU time 84.71 seconds
Started Aug 11 07:15:51 PM PDT 24
Finished Aug 11 07:17:16 PM PDT 24
Peak memory 207708 kb
Host smart-761f1878-dfdb-4ffb-9791-f7f0e692e44c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=179350164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.179350164
Directory /workspace/42.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/42.usbdev_link_in_err.1969976418
Short name T2725
Test name
Test status
Simulation time 248235353 ps
CPU time 0.97 seconds
Started Aug 11 07:15:23 PM PDT 24
Finished Aug 11 07:15:24 PM PDT 24
Peak memory 207552 kb
Host smart-0d2becaf-6434-4e5b-9888-eb8b5966e231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19699
76418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1969976418
Directory /workspace/42.usbdev_link_in_err/latest


Test location /workspace/coverage/default/42.usbdev_link_suspend.1988986807
Short name T1845
Test name
Test status
Simulation time 6092993544 ps
CPU time 7.67 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:53 PM PDT 24
Peak memory 207748 kb
Host smart-38bd27a2-daaa-4a3e-b0d8-c2bad9000548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19889
86807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1988986807
Directory /workspace/42.usbdev_link_suspend/latest


Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.510554021
Short name T2333
Test name
Test status
Simulation time 2521331092 ps
CPU time 70.46 seconds
Started Aug 11 07:15:42 PM PDT 24
Finished Aug 11 07:16:53 PM PDT 24
Peak memory 218888 kb
Host smart-9d37c792-8ec7-4a04-ab20-f3b5d6813f16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=510554021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.510554021
Directory /workspace/42.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.491108306
Short name T3323
Test name
Test status
Simulation time 1844170367 ps
CPU time 13.31 seconds
Started Aug 11 07:15:41 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 217688 kb
Host smart-7e4ce902-a1fd-4cf7-a412-ec1c5ea99cdf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=491108306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.491108306
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.637435704
Short name T924
Test name
Test status
Simulation time 245548391 ps
CPU time 1.01 seconds
Started Aug 11 07:15:40 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 207552 kb
Host smart-e14570c2-a538-4abb-b7bc-f5c5bd7439f2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=637435704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.637435704
Directory /workspace/42.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1187549154
Short name T1418
Test name
Test status
Simulation time 200474588 ps
CPU time 0.98 seconds
Started Aug 11 07:15:36 PM PDT 24
Finished Aug 11 07:15:38 PM PDT 24
Peak memory 207580 kb
Host smart-11f46562-dc6e-451c-a5f7-1004f26a3963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11875
49154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1187549154
Directory /workspace/42.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.2948317140
Short name T2025
Test name
Test status
Simulation time 2565975460 ps
CPU time 25.02 seconds
Started Aug 11 07:15:35 PM PDT 24
Finished Aug 11 07:16:00 PM PDT 24
Peak memory 215996 kb
Host smart-d35498bb-1290-42dc-aedf-bdc0459fd356
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2948317140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.2948317140
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.1111494568
Short name T3518
Test name
Test status
Simulation time 155421443 ps
CPU time 0.89 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:15:45 PM PDT 24
Peak memory 207568 kb
Host smart-335ac9c7-de3c-4137-b4c0-a78b45f77539
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1111494568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.1111494568
Directory /workspace/42.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1989281046
Short name T2284
Test name
Test status
Simulation time 163212494 ps
CPU time 0.85 seconds
Started Aug 11 07:15:40 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 207472 kb
Host smart-61b07420-7f33-414a-aa56-e7d29a81ba20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
81046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1989281046
Directory /workspace/42.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_out_iso.2956855886
Short name T1657
Test name
Test status
Simulation time 153750218 ps
CPU time 0.86 seconds
Started Aug 11 07:15:50 PM PDT 24
Finished Aug 11 07:15:51 PM PDT 24
Peak memory 207572 kb
Host smart-47688388-6c6b-480d-b5a6-a014211431df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29568
55886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2956855886
Directory /workspace/42.usbdev_out_iso/latest


Test location /workspace/coverage/default/42.usbdev_out_stall.499913535
Short name T3045
Test name
Test status
Simulation time 210203373 ps
CPU time 0.96 seconds
Started Aug 11 07:15:53 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 207568 kb
Host smart-631cf604-471b-48e7-9ac1-511346c5e8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49991
3535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.499913535
Directory /workspace/42.usbdev_out_stall/latest


Test location /workspace/coverage/default/42.usbdev_out_trans_nak.270203325
Short name T879
Test name
Test status
Simulation time 170904157 ps
CPU time 0.86 seconds
Started Aug 11 07:15:50 PM PDT 24
Finished Aug 11 07:15:52 PM PDT 24
Peak memory 207524 kb
Host smart-66657c84-7d6f-4590-84b8-05e14ad59605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020
3325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.270203325
Directory /workspace/42.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3990062672
Short name T1711
Test name
Test status
Simulation time 157617132 ps
CPU time 0.88 seconds
Started Aug 11 07:15:42 PM PDT 24
Finished Aug 11 07:15:43 PM PDT 24
Peak memory 207572 kb
Host smart-8bdde3c3-c216-4db6-bab1-eacc3ce88367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900
62672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3990062672
Directory /workspace/42.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.1282526434
Short name T1448
Test name
Test status
Simulation time 214045683 ps
CPU time 1.07 seconds
Started Aug 11 07:15:46 PM PDT 24
Finished Aug 11 07:15:48 PM PDT 24
Peak memory 207520 kb
Host smart-59e85805-636c-4d9e-adb7-0dbc2dcbafc7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1282526434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.1282526434
Directory /workspace/42.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.535079213
Short name T3454
Test name
Test status
Simulation time 151150034 ps
CPU time 0.87 seconds
Started Aug 11 07:15:35 PM PDT 24
Finished Aug 11 07:15:36 PM PDT 24
Peak memory 207468 kb
Host smart-2072cae5-d2bc-49b6-a909-50917891d575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53507
9213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.535079213
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2577305304
Short name T979
Test name
Test status
Simulation time 27688447 ps
CPU time 0.69 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:15:45 PM PDT 24
Peak memory 207480 kb
Host smart-94e8535c-fefa-4750-95e6-5f6940071e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25773
05304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2577305304
Directory /workspace/42.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3107153175
Short name T294
Test name
Test status
Simulation time 20070853509 ps
CPU time 52.75 seconds
Started Aug 11 07:15:34 PM PDT 24
Finished Aug 11 07:16:27 PM PDT 24
Peak memory 215936 kb
Host smart-e1dfe7cb-be8c-40ea-8564-4d3004b18965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31071
53175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3107153175
Directory /workspace/42.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/42.usbdev_pkt_received.1269379044
Short name T2842
Test name
Test status
Simulation time 172894844 ps
CPU time 0.87 seconds
Started Aug 11 07:15:46 PM PDT 24
Finished Aug 11 07:15:47 PM PDT 24
Peak memory 207568 kb
Host smart-f2782956-c66e-4de6-84ec-0cc0d02f2ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12693
79044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1269379044
Directory /workspace/42.usbdev_pkt_received/latest


Test location /workspace/coverage/default/42.usbdev_pkt_sent.4234427143
Short name T1062
Test name
Test status
Simulation time 222203550 ps
CPU time 0.99 seconds
Started Aug 11 07:15:29 PM PDT 24
Finished Aug 11 07:15:30 PM PDT 24
Peak memory 207548 kb
Host smart-583db502-2ce7-47b1-9334-f3c5ed0b88bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42344
27143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.4234427143
Directory /workspace/42.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2940558570
Short name T818
Test name
Test status
Simulation time 226811062 ps
CPU time 0.97 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:40 PM PDT 24
Peak memory 207556 kb
Host smart-1bea9b3c-dc3a-4fbb-ac84-28ea24ed9606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29405
58570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2940558570
Directory /workspace/42.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.527280926
Short name T658
Test name
Test status
Simulation time 246080721 ps
CPU time 1.11 seconds
Started Aug 11 07:15:43 PM PDT 24
Finished Aug 11 07:15:45 PM PDT 24
Peak memory 207512 kb
Host smart-8155f438-8cd2-4880-9112-24eb6168fcd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52728
0926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.527280926
Directory /workspace/42.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3018790264
Short name T866
Test name
Test status
Simulation time 176361859 ps
CPU time 0.84 seconds
Started Aug 11 07:15:40 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 207424 kb
Host smart-a43ab606-ae07-4333-87ce-8e33888874ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
90264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3018790264
Directory /workspace/42.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/42.usbdev_setup_stage.1650470967
Short name T1193
Test name
Test status
Simulation time 167249818 ps
CPU time 0.86 seconds
Started Aug 11 07:15:36 PM PDT 24
Finished Aug 11 07:15:37 PM PDT 24
Peak memory 207456 kb
Host smart-d2ef14ce-3820-4bbe-9786-bece47653932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16504
70967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1650470967
Directory /workspace/42.usbdev_setup_stage/latest


Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.635349251
Short name T521
Test name
Test status
Simulation time 159110785 ps
CPU time 0.87 seconds
Started Aug 11 07:15:38 PM PDT 24
Finished Aug 11 07:15:39 PM PDT 24
Peak memory 207540 kb
Host smart-8661385a-9269-492b-bbdf-4a6237f57c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63534
9251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.635349251
Directory /workspace/42.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/42.usbdev_smoke.185893722
Short name T2330
Test name
Test status
Simulation time 192617064 ps
CPU time 0.92 seconds
Started Aug 11 07:15:38 PM PDT 24
Finished Aug 11 07:15:39 PM PDT 24
Peak memory 207568 kb
Host smart-01decb96-b402-42b4-ae80-132ad28ecff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18589
3722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.185893722
Directory /workspace/42.usbdev_smoke/latest


Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.3452398363
Short name T2704
Test name
Test status
Simulation time 2260417572 ps
CPU time 16.66 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:56 PM PDT 24
Peak memory 224256 kb
Host smart-40e0cf4a-083a-449f-9991-a25cc387977e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3452398363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.3452398363
Directory /workspace/42.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3045231272
Short name T2541
Test name
Test status
Simulation time 194411667 ps
CPU time 0.94 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207452 kb
Host smart-710dd2ab-025d-4b05-8b0c-71751658b017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30452
31272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3045231272
Directory /workspace/42.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/42.usbdev_stall_trans.1335654549
Short name T3322
Test name
Test status
Simulation time 168917835 ps
CPU time 0.84 seconds
Started Aug 11 07:15:34 PM PDT 24
Finished Aug 11 07:15:34 PM PDT 24
Peak memory 207572 kb
Host smart-fe83e9b6-dbac-40df-abe6-b0a1a2d396c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13356
54549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1335654549
Directory /workspace/42.usbdev_stall_trans/latest


Test location /workspace/coverage/default/42.usbdev_stream_len_max.1480501267
Short name T1088
Test name
Test status
Simulation time 1197283142 ps
CPU time 2.81 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:42 PM PDT 24
Peak memory 207664 kb
Host smart-945b9f41-f544-4ee9-b3b3-52637f751513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14805
01267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.1480501267
Directory /workspace/42.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/42.usbdev_streaming_out.3526205010
Short name T2978
Test name
Test status
Simulation time 2438071252 ps
CPU time 69.39 seconds
Started Aug 11 07:15:37 PM PDT 24
Finished Aug 11 07:16:47 PM PDT 24
Peak memory 217756 kb
Host smart-7204991d-4cf1-4cef-a247-9bcb74f7f737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35262
05010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3526205010
Directory /workspace/42.usbdev_streaming_out/latest


Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.3001060476
Short name T2897
Test name
Test status
Simulation time 988490513 ps
CPU time 23.52 seconds
Started Aug 11 07:15:33 PM PDT 24
Finished Aug 11 07:15:56 PM PDT 24
Peak memory 207744 kb
Host smart-f8387cd5-e30b-4e2e-b9c3-70f720da5543
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001060476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.3001060476
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/42.usbdev_tx_rx_disruption.3077678678
Short name T2027
Test name
Test status
Simulation time 625759582 ps
CPU time 1.69 seconds
Started Aug 11 07:15:36 PM PDT 24
Finished Aug 11 07:15:38 PM PDT 24
Peak memory 207540 kb
Host smart-70fea13d-1381-42fb-9b3b-5ad8465a96fa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077678678 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.usbdev_tx_rx_disruption.3077678678
Directory /workspace/42.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/421.usbdev_tx_rx_disruption.2927629343
Short name T923
Test name
Test status
Simulation time 503799311 ps
CPU time 1.49 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207544 kb
Host smart-d9adc3f2-3b55-4f32-b8b0-1a939d67d9e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927629343 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 421.usbdev_tx_rx_disruption.2927629343
Directory /workspace/421.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/422.usbdev_tx_rx_disruption.2283343073
Short name T2336
Test name
Test status
Simulation time 454831919 ps
CPU time 1.47 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:07 PM PDT 24
Peak memory 207536 kb
Host smart-513350b2-b0cc-4f70-9e81-9af2da1dfdf4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283343073 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 422.usbdev_tx_rx_disruption.2283343073
Directory /workspace/422.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/423.usbdev_tx_rx_disruption.3587469259
Short name T3172
Test name
Test status
Simulation time 525404890 ps
CPU time 1.64 seconds
Started Aug 11 07:18:02 PM PDT 24
Finished Aug 11 07:18:04 PM PDT 24
Peak memory 207596 kb
Host smart-122bf846-57a7-45f9-958e-7886fa8bb6fe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587469259 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 423.usbdev_tx_rx_disruption.3587469259
Directory /workspace/423.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/424.usbdev_tx_rx_disruption.2875123967
Short name T2314
Test name
Test status
Simulation time 431058133 ps
CPU time 1.33 seconds
Started Aug 11 07:17:56 PM PDT 24
Finished Aug 11 07:17:58 PM PDT 24
Peak memory 207548 kb
Host smart-4516230e-442d-47dd-a6c9-04fcdbd1fd5d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875123967 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 424.usbdev_tx_rx_disruption.2875123967
Directory /workspace/424.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/425.usbdev_tx_rx_disruption.3454654315
Short name T92
Test name
Test status
Simulation time 524203373 ps
CPU time 1.55 seconds
Started Aug 11 07:17:58 PM PDT 24
Finished Aug 11 07:18:00 PM PDT 24
Peak memory 207568 kb
Host smart-dad47058-bef1-403a-bbb5-86e4a221b1dc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454654315 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 425.usbdev_tx_rx_disruption.3454654315
Directory /workspace/425.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/426.usbdev_tx_rx_disruption.685339838
Short name T1884
Test name
Test status
Simulation time 584750679 ps
CPU time 1.72 seconds
Started Aug 11 07:18:08 PM PDT 24
Finished Aug 11 07:18:10 PM PDT 24
Peak memory 207776 kb
Host smart-c46e6d00-df32-4bbc-a1b1-3f04badabc59
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685339838 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 426.usbdev_tx_rx_disruption.685339838
Directory /workspace/426.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/427.usbdev_tx_rx_disruption.1220328712
Short name T3436
Test name
Test status
Simulation time 568112170 ps
CPU time 1.56 seconds
Started Aug 11 07:18:07 PM PDT 24
Finished Aug 11 07:18:08 PM PDT 24
Peak memory 207568 kb
Host smart-795a5a9f-bbe0-4d9f-a2e1-665d05853397
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220328712 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 427.usbdev_tx_rx_disruption.1220328712
Directory /workspace/427.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/428.usbdev_tx_rx_disruption.1924635369
Short name T3010
Test name
Test status
Simulation time 416318668 ps
CPU time 1.39 seconds
Started Aug 11 07:17:58 PM PDT 24
Finished Aug 11 07:17:59 PM PDT 24
Peak memory 207556 kb
Host smart-d8e13c39-9be0-4d19-bf7d-0f3437983f8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924635369 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 428.usbdev_tx_rx_disruption.1924635369
Directory /workspace/428.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/429.usbdev_tx_rx_disruption.3575759364
Short name T2201
Test name
Test status
Simulation time 489312621 ps
CPU time 1.42 seconds
Started Aug 11 07:18:13 PM PDT 24
Finished Aug 11 07:18:15 PM PDT 24
Peak memory 207504 kb
Host smart-ce106c7a-6b53-4c9f-9be8-e5f1502c95f5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575759364 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 429.usbdev_tx_rx_disruption.3575759364
Directory /workspace/429.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/43.usbdev_alert_test.2526467004
Short name T1350
Test name
Test status
Simulation time 47561803 ps
CPU time 0.64 seconds
Started Aug 11 07:15:51 PM PDT 24
Finished Aug 11 07:15:51 PM PDT 24
Peak memory 207576 kb
Host smart-0fdd7d12-2039-4914-8f49-bc245bd4bb2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2526467004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.2526467004
Directory /workspace/43.usbdev_alert_test/latest


Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.103800365
Short name T2429
Test name
Test status
Simulation time 9332527581 ps
CPU time 12.35 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:57 PM PDT 24
Peak memory 207756 kb
Host smart-17ff5a4c-d965-44d4-8a9f-9fbb225902f1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103800365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_ao
n_wake_disconnect.103800365
Directory /workspace/43.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.4275491787
Short name T2676
Test name
Test status
Simulation time 18883172729 ps
CPU time 21.65 seconds
Started Aug 11 07:15:43 PM PDT 24
Finished Aug 11 07:16:05 PM PDT 24
Peak memory 207828 kb
Host smart-7186951a-43ad-4f26-9cfa-5e13bceab73a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275491787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.4275491787
Directory /workspace/43.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1617984925
Short name T1766
Test name
Test status
Simulation time 25291517945 ps
CPU time 32.49 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:16:19 PM PDT 24
Peak memory 215920 kb
Host smart-25237a56-dcf5-4a56-a8a7-ef0f87099aa9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617984925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.1617984925
Directory /workspace/43.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/43.usbdev_av_buffer.2738658614
Short name T1177
Test name
Test status
Simulation time 193606264 ps
CPU time 0.89 seconds
Started Aug 11 07:15:29 PM PDT 24
Finished Aug 11 07:15:30 PM PDT 24
Peak memory 207524 kb
Host smart-6ccf01cf-e617-461f-b561-dacf2d02802b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27386
58614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2738658614
Directory /workspace/43.usbdev_av_buffer/latest


Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1777887572
Short name T1590
Test name
Test status
Simulation time 199155736 ps
CPU time 0.95 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:40 PM PDT 24
Peak memory 207536 kb
Host smart-a2c4a850-1dce-48d6-ac15-4e6630ba4d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17778
87572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1777887572
Directory /workspace/43.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.1570499369
Short name T1666
Test name
Test status
Simulation time 374235917 ps
CPU time 1.34 seconds
Started Aug 11 07:15:35 PM PDT 24
Finished Aug 11 07:15:36 PM PDT 24
Peak memory 207564 kb
Host smart-acaced49-c55c-4d78-a91b-5e8bab9879ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15704
99369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.1570499369
Directory /workspace/43.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2255351584
Short name T347
Test name
Test status
Simulation time 1147318336 ps
CPU time 3.19 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:42 PM PDT 24
Peak memory 207728 kb
Host smart-6a68a6bc-e999-4bf0-8d31-4cd1433f8660
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2255351584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2255351584
Directory /workspace/43.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/43.usbdev_device_address.2699743697
Short name T211
Test name
Test status
Simulation time 47408201904 ps
CPU time 76.14 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:17:00 PM PDT 24
Peak memory 207772 kb
Host smart-4733dad3-1956-43ba-98c7-fc02755ad024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26997
43697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2699743697
Directory /workspace/43.usbdev_device_address/latest


Test location /workspace/coverage/default/43.usbdev_device_timeout.3241123706
Short name T1109
Test name
Test status
Simulation time 2029814906 ps
CPU time 18.1 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:57 PM PDT 24
Peak memory 207720 kb
Host smart-b1bd8926-1512-430e-84bd-23c9752d1dea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241123706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.3241123706
Directory /workspace/43.usbdev_device_timeout/latest


Test location /workspace/coverage/default/43.usbdev_disable_endpoint.2822608532
Short name T999
Test name
Test status
Simulation time 836969974 ps
CPU time 1.88 seconds
Started Aug 11 07:15:39 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 207528 kb
Host smart-de3ec8c0-b7cd-4ea7-849d-01670b4d9151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28226
08532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.2822608532
Directory /workspace/43.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/43.usbdev_disconnected.2233441145
Short name T3151
Test name
Test status
Simulation time 140517275 ps
CPU time 0.81 seconds
Started Aug 11 07:15:36 PM PDT 24
Finished Aug 11 07:15:37 PM PDT 24
Peak memory 207472 kb
Host smart-df5e0991-c880-481f-bfa5-811cb6373634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22334
41145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2233441145
Directory /workspace/43.usbdev_disconnected/latest


Test location /workspace/coverage/default/43.usbdev_enable.1215239070
Short name T19
Test name
Test status
Simulation time 31568736 ps
CPU time 0.74 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:15:45 PM PDT 24
Peak memory 207512 kb
Host smart-e90485fc-3ed9-4c40-b3b9-60c0e6418263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12152
39070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1215239070
Directory /workspace/43.usbdev_enable/latest


Test location /workspace/coverage/default/43.usbdev_endpoint_access.2154079048
Short name T3121
Test name
Test status
Simulation time 812458153 ps
CPU time 2.26 seconds
Started Aug 11 07:15:33 PM PDT 24
Finished Aug 11 07:15:35 PM PDT 24
Peak memory 207976 kb
Host smart-730c82fc-db3f-4231-8f8d-bb62b05e447f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21540
79048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2154079048
Directory /workspace/43.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/43.usbdev_endpoint_types.3676391013
Short name T2608
Test name
Test status
Simulation time 185773603 ps
CPU time 0.9 seconds
Started Aug 11 07:15:36 PM PDT 24
Finished Aug 11 07:15:37 PM PDT 24
Peak memory 207496 kb
Host smart-5678e8ba-9f69-4729-8a78-607503222cc9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3676391013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.3676391013
Directory /workspace/43.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/43.usbdev_fifo_rst.3364644690
Short name T1620
Test name
Test status
Simulation time 394481283 ps
CPU time 2.49 seconds
Started Aug 11 07:15:50 PM PDT 24
Finished Aug 11 07:15:53 PM PDT 24
Peak memory 207756 kb
Host smart-d7d0180d-2681-4eff-8983-ec288186c7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33646
44690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3364644690
Directory /workspace/43.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/43.usbdev_in_iso.3763492650
Short name T2214
Test name
Test status
Simulation time 212749483 ps
CPU time 1.06 seconds
Started Aug 11 07:15:41 PM PDT 24
Finished Aug 11 07:15:42 PM PDT 24
Peak memory 215864 kb
Host smart-1b14232e-b01a-4572-8d61-42291c835513
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3763492650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3763492650
Directory /workspace/43.usbdev_in_iso/latest


Test location /workspace/coverage/default/43.usbdev_in_stall.4011197495
Short name T2569
Test name
Test status
Simulation time 161473611 ps
CPU time 0.83 seconds
Started Aug 11 07:15:42 PM PDT 24
Finished Aug 11 07:15:43 PM PDT 24
Peak memory 207420 kb
Host smart-900e4e39-6d6b-4fab-9095-41a36227e8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40111
97495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.4011197495
Directory /workspace/43.usbdev_in_stall/latest


Test location /workspace/coverage/default/43.usbdev_in_trans.2903035816
Short name T1366
Test name
Test status
Simulation time 202942363 ps
CPU time 1 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207456 kb
Host smart-d2a22213-6ae5-465f-a1d9-06ee90a8ed80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29030
35816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2903035816
Directory /workspace/43.usbdev_in_trans/latest


Test location /workspace/coverage/default/43.usbdev_invalid_sync.4115807256
Short name T1872
Test name
Test status
Simulation time 3535808466 ps
CPU time 99.55 seconds
Started Aug 11 07:15:28 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 218436 kb
Host smart-ebd5fcb5-79dd-467a-8bb7-acb45a238f33
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4115807256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.4115807256
Directory /workspace/43.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/43.usbdev_iso_retraction.1966678183
Short name T1819
Test name
Test status
Simulation time 12728336040 ps
CPU time 153.57 seconds
Started Aug 11 07:15:42 PM PDT 24
Finished Aug 11 07:18:16 PM PDT 24
Peak memory 207768 kb
Host smart-74217b02-5cd8-4508-b87e-0ee01e4dd1ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1966678183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.1966678183
Directory /workspace/43.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/43.usbdev_link_in_err.2377650066
Short name T3198
Test name
Test status
Simulation time 187398477 ps
CPU time 0.92 seconds
Started Aug 11 07:15:49 PM PDT 24
Finished Aug 11 07:15:50 PM PDT 24
Peak memory 207548 kb
Host smart-5645a419-d5e0-4031-a290-86c87d518965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
50066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2377650066
Directory /workspace/43.usbdev_link_in_err/latest


Test location /workspace/coverage/default/43.usbdev_link_resume.3419103877
Short name T1992
Test name
Test status
Simulation time 8026897994 ps
CPU time 11.71 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:15:59 PM PDT 24
Peak memory 216036 kb
Host smart-41609828-16b2-4281-9cd1-a0cac4008d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34191
03877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.3419103877
Directory /workspace/43.usbdev_link_resume/latest


Test location /workspace/coverage/default/43.usbdev_link_suspend.1123331404
Short name T2675
Test name
Test status
Simulation time 4145979151 ps
CPU time 5.96 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:15:53 PM PDT 24
Peak memory 207828 kb
Host smart-add98eea-d9c2-48cf-8c61-15ea54f1d43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11233
31404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1123331404
Directory /workspace/43.usbdev_link_suspend/latest


Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3946488774
Short name T2001
Test name
Test status
Simulation time 2888957747 ps
CPU time 84.78 seconds
Started Aug 11 07:15:42 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 216148 kb
Host smart-5c83f4d4-7c06-4004-9553-0b76efaf2e9c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3946488774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3946488774
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2814362096
Short name T3348
Test name
Test status
Simulation time 261051571 ps
CPU time 0.98 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207508 kb
Host smart-c3f77d23-0f45-4842-b50b-a6dc390d9b40
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2814362096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2814362096
Directory /workspace/43.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1300259252
Short name T1323
Test name
Test status
Simulation time 243398088 ps
CPU time 0.95 seconds
Started Aug 11 07:15:42 PM PDT 24
Finished Aug 11 07:15:43 PM PDT 24
Peak memory 207512 kb
Host smart-e343ca6a-639f-4bfe-b959-3bd0365655be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13002
59252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1300259252
Directory /workspace/43.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.1124269373
Short name T2960
Test name
Test status
Simulation time 3769087682 ps
CPU time 37.21 seconds
Started Aug 11 07:15:42 PM PDT 24
Finished Aug 11 07:16:19 PM PDT 24
Peak memory 217704 kb
Host smart-e4515ee2-5629-4a28-a4ce-a584f2f1c7c4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1124269373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.1124269373
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2761777687
Short name T3049
Test name
Test status
Simulation time 151159487 ps
CPU time 0.87 seconds
Started Aug 11 07:15:46 PM PDT 24
Finished Aug 11 07:15:47 PM PDT 24
Peak memory 207532 kb
Host smart-f0d36318-d33d-4dc1-a338-391b04a828a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2761777687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2761777687
Directory /workspace/43.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1062903588
Short name T1129
Test name
Test status
Simulation time 151546886 ps
CPU time 0.82 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:15:45 PM PDT 24
Peak memory 207576 kb
Host smart-ec3a05b9-da63-4996-b366-79315799277e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10629
03588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1062903588
Directory /workspace/43.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_nak_trans.2246608940
Short name T1650
Test name
Test status
Simulation time 256954919 ps
CPU time 1.06 seconds
Started Aug 11 07:15:38 PM PDT 24
Finished Aug 11 07:15:39 PM PDT 24
Peak memory 207552 kb
Host smart-c8971178-b04b-4b38-9505-95d3214b7b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22466
08940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2246608940
Directory /workspace/43.usbdev_nak_trans/latest


Test location /workspace/coverage/default/43.usbdev_out_iso.2493844317
Short name T3344
Test name
Test status
Simulation time 156677053 ps
CPU time 0.9 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207524 kb
Host smart-c3df1213-03a8-42bb-af41-5e8feca4cc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24938
44317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2493844317
Directory /workspace/43.usbdev_out_iso/latest


Test location /workspace/coverage/default/43.usbdev_out_stall.3961255119
Short name T2455
Test name
Test status
Simulation time 210754054 ps
CPU time 1 seconds
Started Aug 11 07:15:50 PM PDT 24
Finished Aug 11 07:15:51 PM PDT 24
Peak memory 207468 kb
Host smart-d6d0e2f3-be47-4026-a45d-2be9c46ed5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39612
55119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3961255119
Directory /workspace/43.usbdev_out_stall/latest


Test location /workspace/coverage/default/43.usbdev_out_trans_nak.387844177
Short name T2700
Test name
Test status
Simulation time 187261185 ps
CPU time 0.94 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:15:48 PM PDT 24
Peak memory 207540 kb
Host smart-5a6833e0-c3f1-4ced-9adc-4663cf4601e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38784
4177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.387844177
Directory /workspace/43.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/43.usbdev_pending_in_trans.4115612685
Short name T1575
Test name
Test status
Simulation time 152543505 ps
CPU time 0.85 seconds
Started Aug 11 07:15:43 PM PDT 24
Finished Aug 11 07:15:44 PM PDT 24
Peak memory 207580 kb
Host smart-487024c9-92cc-4e6b-b4cd-264b7a27e7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156
12685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.4115612685
Directory /workspace/43.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3192984269
Short name T3032
Test name
Test status
Simulation time 220381225 ps
CPU time 0.96 seconds
Started Aug 11 07:15:40 PM PDT 24
Finished Aug 11 07:15:41 PM PDT 24
Peak memory 207568 kb
Host smart-c05791a5-346b-405c-8895-aa1734e9fafe
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3192984269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3192984269
Directory /workspace/43.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.27944257
Short name T2568
Test name
Test status
Simulation time 156013383 ps
CPU time 0.88 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207484 kb
Host smart-9b66a26e-e8ac-4f6f-8475-ab7b62e30c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27944
257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.27944257
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2797366481
Short name T899
Test name
Test status
Simulation time 27868791 ps
CPU time 0.67 seconds
Started Aug 11 07:15:32 PM PDT 24
Finished Aug 11 07:15:33 PM PDT 24
Peak memory 207528 kb
Host smart-20948d0f-5ec7-4376-9c87-6f81b983a865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27973
66481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2797366481
Directory /workspace/43.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/43.usbdev_pkt_received.1820761859
Short name T2934
Test name
Test status
Simulation time 203522984 ps
CPU time 1 seconds
Started Aug 11 07:15:53 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 207568 kb
Host smart-4e660824-4b19-4a4d-a7ff-e4125021ceb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18207
61859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1820761859
Directory /workspace/43.usbdev_pkt_received/latest


Test location /workspace/coverage/default/43.usbdev_pkt_sent.919121125
Short name T2499
Test name
Test status
Simulation time 179987762 ps
CPU time 0.89 seconds
Started Aug 11 07:15:36 PM PDT 24
Finished Aug 11 07:15:37 PM PDT 24
Peak memory 207544 kb
Host smart-7053cce7-ab70-42e3-8e92-fcc0a882821b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91912
1125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.919121125
Directory /workspace/43.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.4265248687
Short name T1576
Test name
Test status
Simulation time 191832832 ps
CPU time 0.91 seconds
Started Aug 11 07:15:53 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 207568 kb
Host smart-b8196d55-93f5-400c-b79a-04a633ee387d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42652
48687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.4265248687
Directory /workspace/43.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2213219979
Short name T1505
Test name
Test status
Simulation time 181662365 ps
CPU time 0.93 seconds
Started Aug 11 07:15:37 PM PDT 24
Finished Aug 11 07:15:38 PM PDT 24
Peak memory 207528 kb
Host smart-26e542da-e1a4-41f8-8f6c-ceb2d0e3689c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22132
19979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2213219979
Directory /workspace/43.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1395935101
Short name T3192
Test name
Test status
Simulation time 152473075 ps
CPU time 0.83 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:15:45 PM PDT 24
Peak memory 207456 kb
Host smart-82eaf3b4-45ed-4656-9f04-9478067763cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13959
35101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1395935101
Directory /workspace/43.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/43.usbdev_rx_full.2057783299
Short name T3358
Test name
Test status
Simulation time 328779995 ps
CPU time 1.19 seconds
Started Aug 11 07:15:43 PM PDT 24
Finished Aug 11 07:15:45 PM PDT 24
Peak memory 207572 kb
Host smart-3bb77b8f-ba9f-4022-a1f5-1b55923f8626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20577
83299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.2057783299
Directory /workspace/43.usbdev_rx_full/latest


Test location /workspace/coverage/default/43.usbdev_setup_stage.2737395314
Short name T2454
Test name
Test status
Simulation time 152707119 ps
CPU time 0.9 seconds
Started Aug 11 07:15:38 PM PDT 24
Finished Aug 11 07:15:39 PM PDT 24
Peak memory 207500 kb
Host smart-e1175d8f-31f2-42be-a5a4-a783a2119240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27373
95314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2737395314
Directory /workspace/43.usbdev_setup_stage/latest


Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2151054319
Short name T2083
Test name
Test status
Simulation time 164814748 ps
CPU time 0.88 seconds
Started Aug 11 07:15:36 PM PDT 24
Finished Aug 11 07:15:37 PM PDT 24
Peak memory 207520 kb
Host smart-ab72eecf-f966-4bd3-b145-9d49cfdd0a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21510
54319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2151054319
Directory /workspace/43.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/43.usbdev_smoke.2765048987
Short name T1479
Test name
Test status
Simulation time 261753071 ps
CPU time 1.09 seconds
Started Aug 11 07:15:37 PM PDT 24
Finished Aug 11 07:15:38 PM PDT 24
Peak memory 207564 kb
Host smart-f7b1e98e-e997-4e74-b0f1-3eaacb993c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27650
48987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2765048987
Directory /workspace/43.usbdev_smoke/latest


Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2193459393
Short name T2511
Test name
Test status
Simulation time 3323343775 ps
CPU time 32.75 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:16:17 PM PDT 24
Peak memory 218088 kb
Host smart-87185bba-fdcb-47eb-9a3b-b8cc71e71d03
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2193459393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2193459393
Directory /workspace/43.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1020583322
Short name T1202
Test name
Test status
Simulation time 156971798 ps
CPU time 0.83 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:15:44 PM PDT 24
Peak memory 207600 kb
Host smart-abdab299-9fd6-4553-82f1-77078dfe1ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10205
83322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1020583322
Directory /workspace/43.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/43.usbdev_stall_trans.795189645
Short name T696
Test name
Test status
Simulation time 196181623 ps
CPU time 0.97 seconds
Started Aug 11 07:15:53 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 207568 kb
Host smart-72879698-d361-44d5-b36e-567efc2d2249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79518
9645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.795189645
Directory /workspace/43.usbdev_stall_trans/latest


Test location /workspace/coverage/default/43.usbdev_stream_len_max.605525015
Short name T2537
Test name
Test status
Simulation time 1310609556 ps
CPU time 3.18 seconds
Started Aug 11 07:15:43 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207668 kb
Host smart-377cff12-320c-4656-b7ca-44752e93a4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60552
5015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.605525015
Directory /workspace/43.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/43.usbdev_streaming_out.1428266755
Short name T2810
Test name
Test status
Simulation time 3312234437 ps
CPU time 96.92 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:17:24 PM PDT 24
Peak memory 216008 kb
Host smart-d44515f6-2bca-48c2-a3b8-d9f1943ab443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14282
66755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1428266755
Directory /workspace/43.usbdev_streaming_out/latest


Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.2473403069
Short name T3561
Test name
Test status
Simulation time 3619709606 ps
CPU time 23.92 seconds
Started Aug 11 07:15:41 PM PDT 24
Finished Aug 11 07:16:05 PM PDT 24
Peak memory 207796 kb
Host smart-cee95b02-cead-4024-9081-a566a793a62e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473403069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.2473403069
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/43.usbdev_tx_rx_disruption.4080483216
Short name T2557
Test name
Test status
Simulation time 524792383 ps
CPU time 1.56 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:15:49 PM PDT 24
Peak memory 207544 kb
Host smart-a8661288-2cea-4c80-a016-ab55e709e8f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080483216 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.usbdev_tx_rx_disruption.4080483216
Directory /workspace/43.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/430.usbdev_tx_rx_disruption.1084280560
Short name T1556
Test name
Test status
Simulation time 633960284 ps
CPU time 1.64 seconds
Started Aug 11 07:17:52 PM PDT 24
Finished Aug 11 07:17:54 PM PDT 24
Peak memory 207484 kb
Host smart-9a68123a-d952-466f-91c6-61f7e2062bd3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084280560 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 430.usbdev_tx_rx_disruption.1084280560
Directory /workspace/430.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/431.usbdev_tx_rx_disruption.1206536687
Short name T2808
Test name
Test status
Simulation time 539416309 ps
CPU time 1.69 seconds
Started Aug 11 07:17:57 PM PDT 24
Finished Aug 11 07:17:59 PM PDT 24
Peak memory 207544 kb
Host smart-6af93e22-8dd3-4646-a205-ea8bdf894b06
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206536687 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 431.usbdev_tx_rx_disruption.1206536687
Directory /workspace/431.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/432.usbdev_tx_rx_disruption.810430339
Short name T2140
Test name
Test status
Simulation time 615439437 ps
CPU time 1.67 seconds
Started Aug 11 07:17:56 PM PDT 24
Finished Aug 11 07:17:58 PM PDT 24
Peak memory 207440 kb
Host smart-34e297b9-a852-44a6-93f3-ed8d6af02fa4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810430339 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 432.usbdev_tx_rx_disruption.810430339
Directory /workspace/432.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/433.usbdev_tx_rx_disruption.814086426
Short name T2453
Test name
Test status
Simulation time 491748886 ps
CPU time 1.62 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207544 kb
Host smart-e7c652b0-e842-483d-913e-4f1bd315bcff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814086426 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 433.usbdev_tx_rx_disruption.814086426
Directory /workspace/433.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/434.usbdev_tx_rx_disruption.2662378172
Short name T3629
Test name
Test status
Simulation time 557321473 ps
CPU time 1.51 seconds
Started Aug 11 07:18:06 PM PDT 24
Finished Aug 11 07:18:08 PM PDT 24
Peak memory 207560 kb
Host smart-e267558a-adc4-47c1-9eeb-dd746e34c7dd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662378172 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 434.usbdev_tx_rx_disruption.2662378172
Directory /workspace/434.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/435.usbdev_tx_rx_disruption.1267768908
Short name T917
Test name
Test status
Simulation time 541012343 ps
CPU time 1.58 seconds
Started Aug 11 07:17:59 PM PDT 24
Finished Aug 11 07:18:00 PM PDT 24
Peak memory 207528 kb
Host smart-de5b6212-0914-45d0-8c02-399597174343
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267768908 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 435.usbdev_tx_rx_disruption.1267768908
Directory /workspace/435.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/436.usbdev_tx_rx_disruption.3914944240
Short name T1786
Test name
Test status
Simulation time 499684834 ps
CPU time 1.47 seconds
Started Aug 11 07:18:09 PM PDT 24
Finished Aug 11 07:18:10 PM PDT 24
Peak memory 207568 kb
Host smart-2b0d49b7-7db6-40fe-9db4-bc752bdfd5b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914944240 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 436.usbdev_tx_rx_disruption.3914944240
Directory /workspace/436.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/437.usbdev_tx_rx_disruption.981918614
Short name T1980
Test name
Test status
Simulation time 623132082 ps
CPU time 1.63 seconds
Started Aug 11 07:18:04 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207572 kb
Host smart-822ce960-5fa2-435f-af97-2e58b336a964
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981918614 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 437.usbdev_tx_rx_disruption.981918614
Directory /workspace/437.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/438.usbdev_tx_rx_disruption.3132729892
Short name T2619
Test name
Test status
Simulation time 570634745 ps
CPU time 1.71 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207572 kb
Host smart-8f41f018-e58c-42e7-8058-17bb34774688
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132729892 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 438.usbdev_tx_rx_disruption.3132729892
Directory /workspace/438.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/439.usbdev_tx_rx_disruption.1469826004
Short name T3556
Test name
Test status
Simulation time 686301416 ps
CPU time 1.71 seconds
Started Aug 11 07:18:03 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207564 kb
Host smart-091638ce-b470-453b-bbbc-7441ab19791c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469826004 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 439.usbdev_tx_rx_disruption.1469826004
Directory /workspace/439.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/44.usbdev_alert_test.3759995642
Short name T3037
Test name
Test status
Simulation time 38123233 ps
CPU time 0.77 seconds
Started Aug 11 07:15:51 PM PDT 24
Finished Aug 11 07:15:52 PM PDT 24
Peak memory 207524 kb
Host smart-13cd4961-2139-43ac-a766-f97878904877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3759995642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3759995642
Directory /workspace/44.usbdev_alert_test/latest


Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3465040428
Short name T3247
Test name
Test status
Simulation time 5034709807 ps
CPU time 6.99 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 216044 kb
Host smart-36004839-df61-4ddd-8f37-70b01cd4e599
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465040428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.3465040428
Directory /workspace/44.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.423907692
Short name T3218
Test name
Test status
Simulation time 13319472808 ps
CPU time 16.21 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:16:02 PM PDT 24
Peak memory 215956 kb
Host smart-ff349729-fde2-4989-8cde-b6c79c17dc76
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=423907692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.423907692
Directory /workspace/44.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.630295928
Short name T2744
Test name
Test status
Simulation time 30235503175 ps
CPU time 37.32 seconds
Started Aug 11 07:15:52 PM PDT 24
Finished Aug 11 07:16:30 PM PDT 24
Peak memory 207840 kb
Host smart-d7050a3f-fc01-4e85-b79d-063640b4ec82
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630295928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_resume.630295928
Directory /workspace/44.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/44.usbdev_av_buffer.1275047262
Short name T1905
Test name
Test status
Simulation time 202226549 ps
CPU time 0.88 seconds
Started Aug 11 07:15:46 PM PDT 24
Finished Aug 11 07:15:47 PM PDT 24
Peak memory 207552 kb
Host smart-0dcbb446-a546-43b1-9eee-7c71022b7e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12750
47262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1275047262
Directory /workspace/44.usbdev_av_buffer/latest


Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1350321282
Short name T2517
Test name
Test status
Simulation time 177022156 ps
CPU time 0.92 seconds
Started Aug 11 07:15:48 PM PDT 24
Finished Aug 11 07:15:49 PM PDT 24
Peak memory 207544 kb
Host smart-f7ec5f6d-b363-4aed-94dd-3ae7ba91a5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13503
21282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1350321282
Directory /workspace/44.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.652296881
Short name T714
Test name
Test status
Simulation time 244041529 ps
CPU time 1.13 seconds
Started Aug 11 07:15:53 PM PDT 24
Finished Aug 11 07:15:59 PM PDT 24
Peak memory 207484 kb
Host smart-0ead3c63-1d18-4c2f-92f2-5e150e34679b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65229
6881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.652296881
Directory /workspace/44.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1151726746
Short name T3437
Test name
Test status
Simulation time 1014339794 ps
CPU time 2.56 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:15:47 PM PDT 24
Peak memory 207740 kb
Host smart-6077d4c1-8fb3-4832-ad81-d5ffbe367b15
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1151726746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1151726746
Directory /workspace/44.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/44.usbdev_device_address.1783763936
Short name T2872
Test name
Test status
Simulation time 40603703504 ps
CPU time 60.85 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:16:46 PM PDT 24
Peak memory 207820 kb
Host smart-15024dfc-6c8b-4ad0-bdac-5ae79aafae58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17837
63936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1783763936
Directory /workspace/44.usbdev_device_address/latest


Test location /workspace/coverage/default/44.usbdev_device_timeout.1230523673
Short name T1777
Test name
Test status
Simulation time 1309305019 ps
CPU time 29.2 seconds
Started Aug 11 07:15:49 PM PDT 24
Finished Aug 11 07:16:19 PM PDT 24
Peak memory 207752 kb
Host smart-89cfc9cd-aa1d-4dfe-b3ad-8b3f34dad6b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230523673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.1230523673
Directory /workspace/44.usbdev_device_timeout/latest


Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2031099689
Short name T1734
Test name
Test status
Simulation time 1057542454 ps
CPU time 2.08 seconds
Started Aug 11 07:15:51 PM PDT 24
Finished Aug 11 07:15:53 PM PDT 24
Peak memory 207496 kb
Host smart-4e20591d-0c78-4c87-b09b-c0bccc94b2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20310
99689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2031099689
Directory /workspace/44.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/44.usbdev_disconnected.2709956332
Short name T2745
Test name
Test status
Simulation time 191992000 ps
CPU time 0.88 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207468 kb
Host smart-ff95b93b-c752-456e-aabc-0f6e8584e252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27099
56332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2709956332
Directory /workspace/44.usbdev_disconnected/latest


Test location /workspace/coverage/default/44.usbdev_enable.1296526185
Short name T1741
Test name
Test status
Simulation time 69813534 ps
CPU time 0.71 seconds
Started Aug 11 07:15:51 PM PDT 24
Finished Aug 11 07:15:52 PM PDT 24
Peak memory 207524 kb
Host smart-89db1444-d557-4433-b5d2-727742f6fad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12965
26185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1296526185
Directory /workspace/44.usbdev_enable/latest


Test location /workspace/coverage/default/44.usbdev_endpoint_access.1049332330
Short name T3548
Test name
Test status
Simulation time 802313699 ps
CPU time 2.34 seconds
Started Aug 11 07:15:48 PM PDT 24
Finished Aug 11 07:15:51 PM PDT 24
Peak memory 207720 kb
Host smart-114a3286-230b-4e28-8da8-199275eabf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10493
32330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1049332330
Directory /workspace/44.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/44.usbdev_endpoint_types.1055301229
Short name T103
Test name
Test status
Simulation time 585179239 ps
CPU time 1.62 seconds
Started Aug 11 07:15:49 PM PDT 24
Finished Aug 11 07:15:51 PM PDT 24
Peak memory 207504 kb
Host smart-96c650de-052a-491f-a90c-72696e9ec9a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1055301229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.1055301229
Directory /workspace/44.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/44.usbdev_fifo_rst.3861473387
Short name T2785
Test name
Test status
Simulation time 259569904 ps
CPU time 1.46 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:47 PM PDT 24
Peak memory 207668 kb
Host smart-9ce94e76-5267-40e9-9c47-fb330c189013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38614
73387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3861473387
Directory /workspace/44.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/44.usbdev_in_iso.3309285985
Short name T1186
Test name
Test status
Simulation time 209893402 ps
CPU time 0.95 seconds
Started Aug 11 07:15:53 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 207496 kb
Host smart-e3dfe5e6-0847-44bd-846c-38833f05fe4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3309285985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3309285985
Directory /workspace/44.usbdev_in_iso/latest


Test location /workspace/coverage/default/44.usbdev_in_stall.2815222844
Short name T1449
Test name
Test status
Simulation time 142642280 ps
CPU time 0.83 seconds
Started Aug 11 07:15:54 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 207464 kb
Host smart-6d415e77-6fe2-4d64-b7e7-5f2e1540ed7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28152
22844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2815222844
Directory /workspace/44.usbdev_in_stall/latest


Test location /workspace/coverage/default/44.usbdev_in_trans.2026165317
Short name T1943
Test name
Test status
Simulation time 205319025 ps
CPU time 0.96 seconds
Started Aug 11 07:15:38 PM PDT 24
Finished Aug 11 07:15:39 PM PDT 24
Peak memory 207548 kb
Host smart-9e7ded09-2bb4-464f-8a21-a57f966236f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20261
65317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2026165317
Directory /workspace/44.usbdev_in_trans/latest


Test location /workspace/coverage/default/44.usbdev_invalid_sync.217688777
Short name T918
Test name
Test status
Simulation time 3889366150 ps
CPU time 39.28 seconds
Started Aug 11 07:16:03 PM PDT 24
Finished Aug 11 07:16:43 PM PDT 24
Peak memory 217308 kb
Host smart-3f8ea8ff-5722-47b3-b0bd-50ecb1898a99
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=217688777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.217688777
Directory /workspace/44.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/44.usbdev_iso_retraction.1082597206
Short name T666
Test name
Test status
Simulation time 4701131403 ps
CPU time 51.7 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207828 kb
Host smart-56d9b19f-e939-4fa5-a6c9-5b63423f9b00
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1082597206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.1082597206
Directory /workspace/44.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/44.usbdev_link_in_err.587725193
Short name T3384
Test name
Test status
Simulation time 276260267 ps
CPU time 1.03 seconds
Started Aug 11 07:15:46 PM PDT 24
Finished Aug 11 07:15:47 PM PDT 24
Peak memory 207548 kb
Host smart-8594592d-44b3-492e-af08-71b2571dfe9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58772
5193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.587725193
Directory /workspace/44.usbdev_link_in_err/latest


Test location /workspace/coverage/default/44.usbdev_link_resume.2770383911
Short name T1097
Test name
Test status
Simulation time 24761382451 ps
CPU time 35.6 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:16:23 PM PDT 24
Peak memory 207804 kb
Host smart-050e7b3e-1048-4bfc-baa1-519de3ec5d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27703
83911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2770383911
Directory /workspace/44.usbdev_link_resume/latest


Test location /workspace/coverage/default/44.usbdev_link_suspend.4193220697
Short name T123
Test name
Test status
Simulation time 5664820849 ps
CPU time 7.66 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:58 PM PDT 24
Peak memory 207740 kb
Host smart-e6891faa-611e-4170-9982-00fb2aeb2c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
20697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.4193220697
Directory /workspace/44.usbdev_link_suspend/latest


Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.4237567049
Short name T2411
Test name
Test status
Simulation time 3944778671 ps
CPU time 30.94 seconds
Started Aug 11 07:15:44 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 224312 kb
Host smart-17a41e3f-7416-4678-ab9e-4372ba8e09da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4237567049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.4237567049
Directory /workspace/44.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3977153484
Short name T2391
Test name
Test status
Simulation time 2729421033 ps
CPU time 26.11 seconds
Started Aug 11 07:15:53 PM PDT 24
Finished Aug 11 07:16:19 PM PDT 24
Peak memory 216076 kb
Host smart-de970a5e-8284-459b-b420-15d38398fccb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3977153484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3977153484
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.711998619
Short name T1392
Test name
Test status
Simulation time 291449681 ps
CPU time 1.13 seconds
Started Aug 11 07:15:57 PM PDT 24
Finished Aug 11 07:15:58 PM PDT 24
Peak memory 207476 kb
Host smart-05ac193f-6af8-4a85-a9e4-e49e4b44d6a2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=711998619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.711998619
Directory /workspace/44.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2555887762
Short name T633
Test name
Test status
Simulation time 229474175 ps
CPU time 1.02 seconds
Started Aug 11 07:15:55 PM PDT 24
Finished Aug 11 07:15:56 PM PDT 24
Peak memory 207544 kb
Host smart-18c7c86e-722d-4045-be72-528307f300b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25558
87762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2555887762
Directory /workspace/44.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.566473274
Short name T2031
Test name
Test status
Simulation time 3607769893 ps
CPU time 37.19 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:16:22 PM PDT 24
Peak memory 216108 kb
Host smart-d5d95b0a-63a3-4920-831c-0146f124e291
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=566473274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.566473274
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.100373503
Short name T1317
Test name
Test status
Simulation time 165190597 ps
CPU time 0.94 seconds
Started Aug 11 07:15:55 PM PDT 24
Finished Aug 11 07:15:57 PM PDT 24
Peak memory 207516 kb
Host smart-d9f49ccd-38d7-4ec4-a95e-567cbda67d9f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=100373503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.100373503
Directory /workspace/44.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.701181045
Short name T1065
Test name
Test status
Simulation time 180298982 ps
CPU time 0.87 seconds
Started Aug 11 07:15:47 PM PDT 24
Finished Aug 11 07:15:48 PM PDT 24
Peak memory 207548 kb
Host smart-e726dcd3-140c-46cb-95d5-a751e9d12cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70118
1045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.701181045
Directory /workspace/44.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_nak_trans.4118185213
Short name T141
Test name
Test status
Simulation time 180226732 ps
CPU time 0.93 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207524 kb
Host smart-0d432747-e432-46db-80d1-4ff3e712fc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41181
85213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.4118185213
Directory /workspace/44.usbdev_nak_trans/latest


Test location /workspace/coverage/default/44.usbdev_out_iso.2693364116
Short name T3520
Test name
Test status
Simulation time 150622647 ps
CPU time 0.86 seconds
Started Aug 11 07:15:51 PM PDT 24
Finished Aug 11 07:15:52 PM PDT 24
Peak memory 207552 kb
Host smart-f5e8bca3-a86f-42c3-9ac8-336e6e42dd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26933
64116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2693364116
Directory /workspace/44.usbdev_out_iso/latest


Test location /workspace/coverage/default/44.usbdev_out_stall.2709137514
Short name T2153
Test name
Test status
Simulation time 182527957 ps
CPU time 0.9 seconds
Started Aug 11 07:15:50 PM PDT 24
Finished Aug 11 07:15:51 PM PDT 24
Peak memory 207568 kb
Host smart-17a58ed6-6d82-43ef-a80e-c2ddeed9fa05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27091
37514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2709137514
Directory /workspace/44.usbdev_out_stall/latest


Test location /workspace/coverage/default/44.usbdev_out_trans_nak.274074608
Short name T1494
Test name
Test status
Simulation time 142977709 ps
CPU time 0.79 seconds
Started Aug 11 07:15:51 PM PDT 24
Finished Aug 11 07:15:52 PM PDT 24
Peak memory 207436 kb
Host smart-170e0c28-f90d-453e-bcd3-e2d50b85a5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27407
4608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.274074608
Directory /workspace/44.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2667557727
Short name T876
Test name
Test status
Simulation time 148216615 ps
CPU time 0.84 seconds
Started Aug 11 07:15:50 PM PDT 24
Finished Aug 11 07:15:50 PM PDT 24
Peak memory 207540 kb
Host smart-62ea03fd-a732-4f81-baac-bc5004b5cb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26675
57727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2667557727
Directory /workspace/44.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1600272423
Short name T1868
Test name
Test status
Simulation time 284886926 ps
CPU time 1.06 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207612 kb
Host smart-53bec378-906a-4b38-97f7-f7e5ecda3669
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1600272423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1600272423
Directory /workspace/44.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3339847769
Short name T1403
Test name
Test status
Simulation time 154936843 ps
CPU time 0.87 seconds
Started Aug 11 07:15:58 PM PDT 24
Finished Aug 11 07:15:59 PM PDT 24
Peak memory 207516 kb
Host smart-a968f5d3-0b0a-4df7-b2fc-cb31c5c7f186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33398
47769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3339847769
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1026461908
Short name T1296
Test name
Test status
Simulation time 37691225 ps
CPU time 0.71 seconds
Started Aug 11 07:16:01 PM PDT 24
Finished Aug 11 07:16:02 PM PDT 24
Peak memory 207480 kb
Host smart-244bbaa4-3d10-4718-9620-c991c12b2c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10264
61908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1026461908
Directory /workspace/44.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2456587544
Short name T325
Test name
Test status
Simulation time 21901481104 ps
CPU time 56.36 seconds
Started Aug 11 07:15:46 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 216024 kb
Host smart-db570d04-000c-4934-a6db-27b4b26e67ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24565
87544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2456587544
Directory /workspace/44.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/44.usbdev_pkt_received.1351347553
Short name T22
Test name
Test status
Simulation time 189012143 ps
CPU time 0.95 seconds
Started Aug 11 07:15:55 PM PDT 24
Finished Aug 11 07:15:56 PM PDT 24
Peak memory 207548 kb
Host smart-d6e45509-b1f5-4ea8-a005-8e9ee3176865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13513
47553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1351347553
Directory /workspace/44.usbdev_pkt_received/latest


Test location /workspace/coverage/default/44.usbdev_pkt_sent.1341650924
Short name T1068
Test name
Test status
Simulation time 206933245 ps
CPU time 0.96 seconds
Started Aug 11 07:16:01 PM PDT 24
Finished Aug 11 07:16:02 PM PDT 24
Peak memory 207508 kb
Host smart-1e5dbe0b-c521-4634-b03a-aeae9840b3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13416
50924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1341650924
Directory /workspace/44.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2043459310
Short name T3512
Test name
Test status
Simulation time 194226008 ps
CPU time 0.89 seconds
Started Aug 11 07:15:54 PM PDT 24
Finished Aug 11 07:15:55 PM PDT 24
Peak memory 207576 kb
Host smart-0af129d4-1f3c-4818-901f-2db22e009743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20434
59310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2043459310
Directory /workspace/44.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3890803672
Short name T1963
Test name
Test status
Simulation time 183474204 ps
CPU time 0.96 seconds
Started Aug 11 07:15:54 PM PDT 24
Finished Aug 11 07:15:55 PM PDT 24
Peak memory 207480 kb
Host smart-f4a7734b-8d1f-4ea2-b4c3-1daf48f6fc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38908
03672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3890803672
Directory /workspace/44.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_rx_crc_err.330414565
Short name T832
Test name
Test status
Simulation time 177768450 ps
CPU time 0.88 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:13 PM PDT 24
Peak memory 207556 kb
Host smart-b5a52738-97cf-482d-9241-016fe484d636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33041
4565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.330414565
Directory /workspace/44.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/44.usbdev_rx_full.2407704979
Short name T3228
Test name
Test status
Simulation time 394565205 ps
CPU time 1.31 seconds
Started Aug 11 07:15:48 PM PDT 24
Finished Aug 11 07:15:49 PM PDT 24
Peak memory 207576 kb
Host smart-ab7c2f8e-1171-49ff-a223-0dd10ee3eb8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24077
04979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.2407704979
Directory /workspace/44.usbdev_rx_full/latest


Test location /workspace/coverage/default/44.usbdev_setup_stage.2700513921
Short name T3572
Test name
Test status
Simulation time 158271422 ps
CPU time 0.8 seconds
Started Aug 11 07:15:48 PM PDT 24
Finished Aug 11 07:15:49 PM PDT 24
Peak memory 207544 kb
Host smart-167be222-45f7-421e-9e48-cff641b02e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27005
13921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2700513921
Directory /workspace/44.usbdev_setup_stage/latest


Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.476941540
Short name T3429
Test name
Test status
Simulation time 166156003 ps
CPU time 0.87 seconds
Started Aug 11 07:16:03 PM PDT 24
Finished Aug 11 07:16:04 PM PDT 24
Peak memory 207568 kb
Host smart-ae42d4df-b38f-41f6-aa57-223257505cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47694
1540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.476941540
Directory /workspace/44.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/44.usbdev_smoke.1832289339
Short name T591
Test name
Test status
Simulation time 259530436 ps
CPU time 1.06 seconds
Started Aug 11 07:16:00 PM PDT 24
Finished Aug 11 07:16:01 PM PDT 24
Peak memory 207592 kb
Host smart-97e540d3-f10b-421a-9476-b0561863532b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18322
89339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1832289339
Directory /workspace/44.usbdev_smoke/latest


Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2206051860
Short name T1760
Test name
Test status
Simulation time 2579619393 ps
CPU time 18.47 seconds
Started Aug 11 07:15:52 PM PDT 24
Finished Aug 11 07:16:10 PM PDT 24
Peak memory 207900 kb
Host smart-9df644bc-3999-4b5e-a032-d492b372b6d0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2206051860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2206051860
Directory /workspace/44.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1017810690
Short name T2468
Test name
Test status
Simulation time 171924250 ps
CPU time 0.98 seconds
Started Aug 11 07:16:07 PM PDT 24
Finished Aug 11 07:16:08 PM PDT 24
Peak memory 207548 kb
Host smart-9d2adfe4-02ac-4741-99a9-85acc988f3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10178
10690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1017810690
Directory /workspace/44.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/44.usbdev_stall_trans.1528627568
Short name T2300
Test name
Test status
Simulation time 155761388 ps
CPU time 0.87 seconds
Started Aug 11 07:16:02 PM PDT 24
Finished Aug 11 07:16:03 PM PDT 24
Peak memory 207544 kb
Host smart-7383dcad-695b-4671-ba44-d36219dfbe3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15286
27568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1528627568
Directory /workspace/44.usbdev_stall_trans/latest


Test location /workspace/coverage/default/44.usbdev_stream_len_max.1354791097
Short name T3449
Test name
Test status
Simulation time 391666499 ps
CPU time 1.39 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:47 PM PDT 24
Peak memory 207716 kb
Host smart-6f0c2c6b-3466-45ea-b260-a627b10c8d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13547
91097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1354791097
Directory /workspace/44.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/44.usbdev_streaming_out.793974033
Short name T1697
Test name
Test status
Simulation time 1658105674 ps
CPU time 44.95 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:17:00 PM PDT 24
Peak memory 216012 kb
Host smart-318128d6-3c52-4136-af18-e4cd2f18df20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79397
4033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.793974033
Directory /workspace/44.usbdev_streaming_out/latest


Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.1668636706
Short name T3507
Test name
Test status
Simulation time 4289670606 ps
CPU time 28.49 seconds
Started Aug 11 07:15:54 PM PDT 24
Finished Aug 11 07:16:22 PM PDT 24
Peak memory 207788 kb
Host smart-b0d981a1-e778-42af-af78-7014ffbcfbda
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668636706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.1668636706
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/44.usbdev_tx_rx_disruption.622962457
Short name T1247
Test name
Test status
Simulation time 603937939 ps
CPU time 1.62 seconds
Started Aug 11 07:15:55 PM PDT 24
Finished Aug 11 07:15:57 PM PDT 24
Peak memory 207776 kb
Host smart-a2992802-ae47-4b42-9ebd-3d73af2074ed
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622962457 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.usbdev_tx_rx_disruption.622962457
Directory /workspace/44.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/440.usbdev_tx_rx_disruption.1526077856
Short name T775
Test name
Test status
Simulation time 508683341 ps
CPU time 1.51 seconds
Started Aug 11 07:18:09 PM PDT 24
Finished Aug 11 07:18:10 PM PDT 24
Peak memory 207528 kb
Host smart-e1f6e872-1a11-4a44-9333-c3a79f77c552
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526077856 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 440.usbdev_tx_rx_disruption.1526077856
Directory /workspace/440.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/441.usbdev_tx_rx_disruption.3873862242
Short name T949
Test name
Test status
Simulation time 523063613 ps
CPU time 1.55 seconds
Started Aug 11 07:18:08 PM PDT 24
Finished Aug 11 07:18:10 PM PDT 24
Peak memory 207536 kb
Host smart-96cf618f-875a-4dde-a1cf-6ba0fc601a63
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873862242 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 441.usbdev_tx_rx_disruption.3873862242
Directory /workspace/441.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/442.usbdev_tx_rx_disruption.3164185215
Short name T185
Test name
Test status
Simulation time 645622538 ps
CPU time 1.72 seconds
Started Aug 11 07:18:04 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207572 kb
Host smart-dca3501d-9a63-4352-bf4f-a693189feba1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164185215 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 442.usbdev_tx_rx_disruption.3164185215
Directory /workspace/442.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/443.usbdev_tx_rx_disruption.1819157946
Short name T2914
Test name
Test status
Simulation time 414881269 ps
CPU time 1.33 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:01 PM PDT 24
Peak memory 207568 kb
Host smart-e14d87e9-5c6c-4d5b-b4c5-d93f57a3aca0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819157946 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 443.usbdev_tx_rx_disruption.1819157946
Directory /workspace/443.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/444.usbdev_tx_rx_disruption.4227250661
Short name T3395
Test name
Test status
Simulation time 567050517 ps
CPU time 1.56 seconds
Started Aug 11 07:18:12 PM PDT 24
Finished Aug 11 07:18:14 PM PDT 24
Peak memory 207608 kb
Host smart-ab61581c-7276-4439-a342-f99a656dea74
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227250661 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 444.usbdev_tx_rx_disruption.4227250661
Directory /workspace/444.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/445.usbdev_tx_rx_disruption.182506118
Short name T2066
Test name
Test status
Simulation time 633419778 ps
CPU time 1.72 seconds
Started Aug 11 07:18:17 PM PDT 24
Finished Aug 11 07:18:18 PM PDT 24
Peak memory 207520 kb
Host smart-f7f20811-9c0d-42b2-bc9a-466e12317fc3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182506118 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 445.usbdev_tx_rx_disruption.182506118
Directory /workspace/445.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/446.usbdev_tx_rx_disruption.107193512
Short name T2614
Test name
Test status
Simulation time 510273228 ps
CPU time 1.54 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:07 PM PDT 24
Peak memory 207592 kb
Host smart-12af46e2-ca32-4388-a785-e75bb2df3408
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107193512 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 446.usbdev_tx_rx_disruption.107193512
Directory /workspace/446.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/447.usbdev_tx_rx_disruption.4013294756
Short name T3315
Test name
Test status
Simulation time 512579875 ps
CPU time 1.51 seconds
Started Aug 11 07:18:04 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207552 kb
Host smart-9ce36812-9d02-4e71-b7d6-3efd2a165e07
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013294756 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 447.usbdev_tx_rx_disruption.4013294756
Directory /workspace/447.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/448.usbdev_tx_rx_disruption.221432083
Short name T2293
Test name
Test status
Simulation time 661183006 ps
CPU time 1.75 seconds
Started Aug 11 07:18:09 PM PDT 24
Finished Aug 11 07:18:11 PM PDT 24
Peak memory 207580 kb
Host smart-2a1ebbab-868a-4858-97fe-a4b466b507f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221432083 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 448.usbdev_tx_rx_disruption.221432083
Directory /workspace/448.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/449.usbdev_tx_rx_disruption.2997449283
Short name T3101
Test name
Test status
Simulation time 482402503 ps
CPU time 1.47 seconds
Started Aug 11 07:18:09 PM PDT 24
Finished Aug 11 07:18:11 PM PDT 24
Peak memory 207480 kb
Host smart-ed325425-271d-4856-b330-ef0d2202cf2b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997449283 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 449.usbdev_tx_rx_disruption.2997449283
Directory /workspace/449.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/45.usbdev_alert_test.1163536782
Short name T2603
Test name
Test status
Simulation time 46241752 ps
CPU time 0.66 seconds
Started Aug 11 07:16:01 PM PDT 24
Finished Aug 11 07:16:02 PM PDT 24
Peak memory 207544 kb
Host smart-312d47b4-53bc-4014-aceb-202a9dbd41af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1163536782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.1163536782
Directory /workspace/45.usbdev_alert_test/latest


Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2665838370
Short name T2664
Test name
Test status
Simulation time 11282112566 ps
CPU time 14.41 seconds
Started Aug 11 07:15:54 PM PDT 24
Finished Aug 11 07:16:08 PM PDT 24
Peak memory 207808 kb
Host smart-62d82934-663d-4536-8af5-09d1a5150e40
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665838370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.2665838370
Directory /workspace/45.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1227518447
Short name T1915
Test name
Test status
Simulation time 16361411817 ps
CPU time 17.7 seconds
Started Aug 11 07:15:57 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 217032 kb
Host smart-005ebe50-2e3c-4036-bc77-8cf1eb330bd2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227518447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1227518447
Directory /workspace/45.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.155656978
Short name T2890
Test name
Test status
Simulation time 31424247365 ps
CPU time 34.2 seconds
Started Aug 11 07:15:51 PM PDT 24
Finished Aug 11 07:16:25 PM PDT 24
Peak memory 207800 kb
Host smart-e1ed15a5-be67-46fb-a7d4-495eaf670ce8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155656978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_ao
n_wake_resume.155656978
Directory /workspace/45.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/45.usbdev_av_buffer.1667622922
Short name T33
Test name
Test status
Simulation time 187429142 ps
CPU time 0.96 seconds
Started Aug 11 07:16:03 PM PDT 24
Finished Aug 11 07:16:04 PM PDT 24
Peak memory 207544 kb
Host smart-8ea2fb39-3587-4790-9822-3057527dd575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16676
22922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1667622922
Directory /workspace/45.usbdev_av_buffer/latest


Test location /workspace/coverage/default/45.usbdev_bitstuff_err.502190029
Short name T3149
Test name
Test status
Simulation time 153898641 ps
CPU time 0.86 seconds
Started Aug 11 07:15:50 PM PDT 24
Finished Aug 11 07:15:51 PM PDT 24
Peak memory 207564 kb
Host smart-ab7b8a9f-2bab-4352-ac9d-5e2be789946d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50219
0029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.502190029
Directory /workspace/45.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.57297852
Short name T989
Test name
Test status
Simulation time 207271846 ps
CPU time 0.96 seconds
Started Aug 11 07:15:45 PM PDT 24
Finished Aug 11 07:15:46 PM PDT 24
Peak memory 207556 kb
Host smart-20cc8934-b63e-4064-95b3-d17f8f2fcd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57297
852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.57297852
Directory /workspace/45.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1689732093
Short name T3271
Test name
Test status
Simulation time 743444302 ps
CPU time 2.13 seconds
Started Aug 11 07:15:43 PM PDT 24
Finished Aug 11 07:15:45 PM PDT 24
Peak memory 207664 kb
Host smart-438044ad-9744-470f-86b5-d5327a7e97e6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1689732093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1689732093
Directory /workspace/45.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/45.usbdev_device_address.2964463020
Short name T212
Test name
Test status
Simulation time 47572354037 ps
CPU time 73.14 seconds
Started Aug 11 07:16:03 PM PDT 24
Finished Aug 11 07:17:16 PM PDT 24
Peak memory 207804 kb
Host smart-0b4319e0-45eb-4bfa-865d-0ce1b671b9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29644
63020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2964463020
Directory /workspace/45.usbdev_device_address/latest


Test location /workspace/coverage/default/45.usbdev_device_timeout.497998555
Short name T643
Test name
Test status
Simulation time 3417888596 ps
CPU time 30.44 seconds
Started Aug 11 07:16:01 PM PDT 24
Finished Aug 11 07:16:32 PM PDT 24
Peak memory 207808 kb
Host smart-76020815-6f11-4c88-8d53-80c14faf52a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497998555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.497998555
Directory /workspace/45.usbdev_device_timeout/latest


Test location /workspace/coverage/default/45.usbdev_disable_endpoint.4037767540
Short name T1707
Test name
Test status
Simulation time 684781747 ps
CPU time 1.65 seconds
Started Aug 11 07:16:00 PM PDT 24
Finished Aug 11 07:16:01 PM PDT 24
Peak memory 207496 kb
Host smart-6d0b863a-5afc-487f-9acc-2373b76f8698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40377
67540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.4037767540
Directory /workspace/45.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/45.usbdev_disconnected.69910648
Short name T3363
Test name
Test status
Simulation time 137112230 ps
CPU time 0.83 seconds
Started Aug 11 07:16:06 PM PDT 24
Finished Aug 11 07:16:07 PM PDT 24
Peak memory 207544 kb
Host smart-9e42ab60-02fe-42e0-9225-723816a1a870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69910
648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.69910648
Directory /workspace/45.usbdev_disconnected/latest


Test location /workspace/coverage/default/45.usbdev_enable.764825455
Short name T2119
Test name
Test status
Simulation time 40488158 ps
CPU time 0.69 seconds
Started Aug 11 07:15:53 PM PDT 24
Finished Aug 11 07:15:53 PM PDT 24
Peak memory 207552 kb
Host smart-0b98dc9c-c3ba-4ecd-8347-cb504610b9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76482
5455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.764825455
Directory /workspace/45.usbdev_enable/latest


Test location /workspace/coverage/default/45.usbdev_endpoint_access.531066456
Short name T17
Test name
Test status
Simulation time 931260004 ps
CPU time 2.47 seconds
Started Aug 11 07:16:00 PM PDT 24
Finished Aug 11 07:16:02 PM PDT 24
Peak memory 207936 kb
Host smart-c41e73b0-6148-4127-a4c0-2802f51f7a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53106
6456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.531066456
Directory /workspace/45.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/45.usbdev_endpoint_types.1106732094
Short name T555
Test name
Test status
Simulation time 183698236 ps
CPU time 0.87 seconds
Started Aug 11 07:16:01 PM PDT 24
Finished Aug 11 07:16:02 PM PDT 24
Peak memory 207568 kb
Host smart-db5f061e-881f-4512-81bb-888e2f70c1e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1106732094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.1106732094
Directory /workspace/45.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/45.usbdev_fifo_rst.171285166
Short name T2693
Test name
Test status
Simulation time 307192793 ps
CPU time 2.23 seconds
Started Aug 11 07:15:56 PM PDT 24
Finished Aug 11 07:15:58 PM PDT 24
Peak memory 207692 kb
Host smart-c97cca46-a365-46cc-8029-76ef1e7134b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17128
5166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.171285166
Directory /workspace/45.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/45.usbdev_in_iso.574506593
Short name T777
Test name
Test status
Simulation time 171604836 ps
CPU time 0.97 seconds
Started Aug 11 07:16:01 PM PDT 24
Finished Aug 11 07:16:02 PM PDT 24
Peak memory 215948 kb
Host smart-1517ad3d-cb93-4a06-ad90-99663b7255ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=574506593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.574506593
Directory /workspace/45.usbdev_in_iso/latest


Test location /workspace/coverage/default/45.usbdev_in_stall.1931842291
Short name T1226
Test name
Test status
Simulation time 144296773 ps
CPU time 0.88 seconds
Started Aug 11 07:15:57 PM PDT 24
Finished Aug 11 07:15:58 PM PDT 24
Peak memory 207472 kb
Host smart-d36a1dba-6885-477f-92f3-554510623f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19318
42291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1931842291
Directory /workspace/45.usbdev_in_stall/latest


Test location /workspace/coverage/default/45.usbdev_in_trans.2022134764
Short name T1132
Test name
Test status
Simulation time 259482666 ps
CPU time 1.06 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:11 PM PDT 24
Peak memory 207568 kb
Host smart-e63a62a5-58a3-4383-be25-945817a4cb93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20221
34764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2022134764
Directory /workspace/45.usbdev_in_trans/latest


Test location /workspace/coverage/default/45.usbdev_invalid_sync.10879726
Short name T2077
Test name
Test status
Simulation time 4026248135 ps
CPU time 113.14 seconds
Started Aug 11 07:16:01 PM PDT 24
Finished Aug 11 07:17:54 PM PDT 24
Peak memory 216132 kb
Host smart-c7100ba8-c07d-4b7e-9145-f2ddd28491d8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=10879726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.10879726
Directory /workspace/45.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/45.usbdev_iso_retraction.880891089
Short name T858
Test name
Test status
Simulation time 11863934843 ps
CPU time 141.91 seconds
Started Aug 11 07:16:05 PM PDT 24
Finished Aug 11 07:18:27 PM PDT 24
Peak memory 207828 kb
Host smart-23d760a0-4d42-46c4-b73a-20aabe641d1d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=880891089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.880891089
Directory /workspace/45.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/45.usbdev_link_in_err.3426875325
Short name T1594
Test name
Test status
Simulation time 164507410 ps
CPU time 0.87 seconds
Started Aug 11 07:16:00 PM PDT 24
Finished Aug 11 07:16:01 PM PDT 24
Peak memory 207604 kb
Host smart-c0270126-8591-4085-be95-a29038469f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34268
75325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3426875325
Directory /workspace/45.usbdev_link_in_err/latest


Test location /workspace/coverage/default/45.usbdev_link_resume.3995421088
Short name T1688
Test name
Test status
Simulation time 31867340909 ps
CPU time 46.9 seconds
Started Aug 11 07:15:52 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207868 kb
Host smart-f0023dae-b95f-4736-83f4-9a2c50b0cc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39954
21088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.3995421088
Directory /workspace/45.usbdev_link_resume/latest


Test location /workspace/coverage/default/45.usbdev_link_suspend.2073576261
Short name T3571
Test name
Test status
Simulation time 10872779569 ps
CPU time 13.19 seconds
Started Aug 11 07:16:01 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207784 kb
Host smart-bd6ced56-ff99-4185-a032-a709984a5aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735
76261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2073576261
Directory /workspace/45.usbdev_link_suspend/latest


Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1065532513
Short name T2142
Test name
Test status
Simulation time 2150496799 ps
CPU time 15.96 seconds
Started Aug 11 07:16:05 PM PDT 24
Finished Aug 11 07:16:21 PM PDT 24
Peak memory 216096 kb
Host smart-0571e245-40db-4b47-804e-927952a117aa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1065532513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1065532513
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.222258723
Short name T3411
Test name
Test status
Simulation time 253376962 ps
CPU time 1.07 seconds
Started Aug 11 07:16:20 PM PDT 24
Finished Aug 11 07:16:21 PM PDT 24
Peak memory 207512 kb
Host smart-deb719b6-165b-41d1-ac20-51b4ff2f83c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=222258723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.222258723
Directory /workspace/45.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.687261762
Short name T2546
Test name
Test status
Simulation time 202331243 ps
CPU time 0.94 seconds
Started Aug 11 07:15:53 PM PDT 24
Finished Aug 11 07:15:54 PM PDT 24
Peak memory 207572 kb
Host smart-dc3914a4-2889-4e53-9891-eaa0d35a1858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68726
1762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.687261762
Directory /workspace/45.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1709465623
Short name T1338
Test name
Test status
Simulation time 2309288678 ps
CPU time 23.01 seconds
Started Aug 11 07:16:06 PM PDT 24
Finished Aug 11 07:16:30 PM PDT 24
Peak memory 216072 kb
Host smart-841d36eb-8808-4a4e-9939-9456d1cf52a4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1709465623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1709465623
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.4261604893
Short name T1574
Test name
Test status
Simulation time 148467891 ps
CPU time 0.91 seconds
Started Aug 11 07:16:25 PM PDT 24
Finished Aug 11 07:16:26 PM PDT 24
Peak memory 207544 kb
Host smart-972d607c-4fa7-48b4-9fce-287d2e21cc82
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4261604893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.4261604893
Directory /workspace/45.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.4155694616
Short name T3020
Test name
Test status
Simulation time 158752923 ps
CPU time 0.93 seconds
Started Aug 11 07:15:59 PM PDT 24
Finished Aug 11 07:16:00 PM PDT 24
Peak memory 207504 kb
Host smart-1a226217-badc-4bba-9472-1ef8bf6fcb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41556
94616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.4155694616
Directory /workspace/45.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_nak_trans.3040078699
Short name T2361
Test name
Test status
Simulation time 207904639 ps
CPU time 0.98 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207572 kb
Host smart-6b79364f-b4ed-425e-a080-3ca01cd49711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30400
78699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3040078699
Directory /workspace/45.usbdev_nak_trans/latest


Test location /workspace/coverage/default/45.usbdev_out_iso.4285538138
Short name T2628
Test name
Test status
Simulation time 174353172 ps
CPU time 0.92 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207492 kb
Host smart-6d2abfa6-ad41-4327-b2f6-4c3e27e67886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42855
38138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.4285538138
Directory /workspace/45.usbdev_out_iso/latest


Test location /workspace/coverage/default/45.usbdev_out_stall.3007505827
Short name T1861
Test name
Test status
Simulation time 163959717 ps
CPU time 0.86 seconds
Started Aug 11 07:16:06 PM PDT 24
Finished Aug 11 07:16:08 PM PDT 24
Peak memory 207584 kb
Host smart-3fe7c446-57fd-4e2f-8552-37b58432e0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30075
05827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3007505827
Directory /workspace/45.usbdev_out_stall/latest


Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1619787249
Short name T2793
Test name
Test status
Simulation time 193398288 ps
CPU time 0.96 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207544 kb
Host smart-7d96684a-e232-44d4-a54c-476950902db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16197
87249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1619787249
Directory /workspace/45.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/45.usbdev_pending_in_trans.4228855232
Short name T3495
Test name
Test status
Simulation time 192530334 ps
CPU time 0.86 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207512 kb
Host smart-e156beb5-7119-48a8-b155-ec5f5ba673bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42288
55232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.4228855232
Directory /workspace/45.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.2817269551
Short name T3483
Test name
Test status
Simulation time 199774007 ps
CPU time 0.95 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:11 PM PDT 24
Peak memory 207508 kb
Host smart-768e7043-f864-46e3-9be8-ac04823416df
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2817269551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2817269551
Directory /workspace/45.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3851681465
Short name T2124
Test name
Test status
Simulation time 142812554 ps
CPU time 0.79 seconds
Started Aug 11 07:16:11 PM PDT 24
Finished Aug 11 07:16:12 PM PDT 24
Peak memory 207520 kb
Host smart-e66ca4f6-1c46-4afb-8627-53604fc125c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38516
81465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3851681465
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3831989894
Short name T2466
Test name
Test status
Simulation time 41609262 ps
CPU time 0.72 seconds
Started Aug 11 07:16:16 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207540 kb
Host smart-7767492d-64ed-4915-beae-ab343ac0f8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38319
89894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3831989894
Directory /workspace/45.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1713290484
Short name T3336
Test name
Test status
Simulation time 15698063378 ps
CPU time 42.43 seconds
Started Aug 11 07:15:56 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 224220 kb
Host smart-7ebcbfc4-ba63-48cf-afa3-2d5e6d845621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17132
90484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1713290484
Directory /workspace/45.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/45.usbdev_pkt_received.3303227375
Short name T1684
Test name
Test status
Simulation time 175981845 ps
CPU time 0.92 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207524 kb
Host smart-972b035c-5353-43c0-ab20-2896d06b29e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33032
27375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3303227375
Directory /workspace/45.usbdev_pkt_received/latest


Test location /workspace/coverage/default/45.usbdev_pkt_sent.524788790
Short name T932
Test name
Test status
Simulation time 247249604 ps
CPU time 1 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207532 kb
Host smart-eca7ffe1-8d94-4a48-9847-4b3948ee27f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52478
8790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.524788790
Directory /workspace/45.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3629656960
Short name T1227
Test name
Test status
Simulation time 154014618 ps
CPU time 0.86 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207512 kb
Host smart-22dacebe-e280-495c-824b-c5aa09e34204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36296
56960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3629656960
Directory /workspace/45.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3877006
Short name T3296
Test name
Test status
Simulation time 178952521 ps
CPU time 0.93 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207556 kb
Host smart-1224e929-4a92-4cc8-9042-734fb374dd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38770
06 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3877006
Directory /workspace/45.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_rx_crc_err.511788875
Short name T1217
Test name
Test status
Simulation time 182196031 ps
CPU time 0.87 seconds
Started Aug 11 07:16:06 PM PDT 24
Finished Aug 11 07:16:07 PM PDT 24
Peak memory 207468 kb
Host smart-ecdf9ac7-1e8e-46c2-8919-fbfb54c8c961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51178
8875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.511788875
Directory /workspace/45.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/45.usbdev_rx_full.1840124088
Short name T1492
Test name
Test status
Simulation time 243603562 ps
CPU time 1 seconds
Started Aug 11 07:15:58 PM PDT 24
Finished Aug 11 07:15:59 PM PDT 24
Peak memory 207568 kb
Host smart-28d1e4ce-6b1c-4798-bf34-5b5bef6a4289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18401
24088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.1840124088
Directory /workspace/45.usbdev_rx_full/latest


Test location /workspace/coverage/default/45.usbdev_setup_stage.3830930365
Short name T2435
Test name
Test status
Simulation time 148482733 ps
CPU time 0.85 seconds
Started Aug 11 07:16:07 PM PDT 24
Finished Aug 11 07:16:08 PM PDT 24
Peak memory 207540 kb
Host smart-1ef63969-cb7d-40fe-92ac-655afb89188a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38309
30365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3830930365
Directory /workspace/45.usbdev_setup_stage/latest


Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.631897217
Short name T3124
Test name
Test status
Simulation time 161130819 ps
CPU time 0.87 seconds
Started Aug 11 07:16:07 PM PDT 24
Finished Aug 11 07:16:08 PM PDT 24
Peak memory 207548 kb
Host smart-755acda7-0873-48c2-820e-10812a202406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63189
7217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.631897217
Directory /workspace/45.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/45.usbdev_smoke.1353508541
Short name T2110
Test name
Test status
Simulation time 233930551 ps
CPU time 1.01 seconds
Started Aug 11 07:16:07 PM PDT 24
Finished Aug 11 07:16:09 PM PDT 24
Peak memory 207536 kb
Host smart-bbbe321a-8ddd-4b7f-b249-50938f1075e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13535
08541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1353508541
Directory /workspace/45.usbdev_smoke/latest


Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.374175920
Short name T1779
Test name
Test status
Simulation time 3269439423 ps
CPU time 27.64 seconds
Started Aug 11 07:16:19 PM PDT 24
Finished Aug 11 07:16:47 PM PDT 24
Peak memory 218092 kb
Host smart-d2e5d62c-adc4-4231-a809-594db9ad899d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=374175920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.374175920
Directory /workspace/45.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.4239008363
Short name T1995
Test name
Test status
Simulation time 176621815 ps
CPU time 0.88 seconds
Started Aug 11 07:16:08 PM PDT 24
Finished Aug 11 07:16:09 PM PDT 24
Peak memory 207552 kb
Host smart-0e293d4a-c823-42e3-a097-909fc701165e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42390
08363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.4239008363
Directory /workspace/45.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/45.usbdev_stall_trans.1374694701
Short name T2388
Test name
Test status
Simulation time 188711768 ps
CPU time 0.92 seconds
Started Aug 11 07:16:08 PM PDT 24
Finished Aug 11 07:16:09 PM PDT 24
Peak memory 207596 kb
Host smart-a1f1ed1c-3d9f-4a95-835c-28e14f03fabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13746
94701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1374694701
Directory /workspace/45.usbdev_stall_trans/latest


Test location /workspace/coverage/default/45.usbdev_stream_len_max.242503439
Short name T2766
Test name
Test status
Simulation time 1238167547 ps
CPU time 3.02 seconds
Started Aug 11 07:16:06 PM PDT 24
Finished Aug 11 07:16:10 PM PDT 24
Peak memory 207660 kb
Host smart-eb10fb1f-8850-456a-bdb5-7b55b9041dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24250
3439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.242503439
Directory /workspace/45.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/45.usbdev_streaming_out.1888658682
Short name T1133
Test name
Test status
Simulation time 3513974130 ps
CPU time 33.36 seconds
Started Aug 11 07:16:11 PM PDT 24
Finished Aug 11 07:16:45 PM PDT 24
Peak memory 216040 kb
Host smart-d92238bd-99c7-4881-8c12-365e847bffb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18886
58682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1888658682
Directory /workspace/45.usbdev_streaming_out/latest


Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.835885556
Short name T1233
Test name
Test status
Simulation time 2972126030 ps
CPU time 26.33 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207808 kb
Host smart-a47d3f76-01e6-4849-80f2-4a1f8dff7842
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835885556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_host
_handshake.835885556
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/45.usbdev_tx_rx_disruption.301752359
Short name T3387
Test name
Test status
Simulation time 445770769 ps
CPU time 1.38 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207552 kb
Host smart-7f6b27f3-cf28-44e3-bf15-1f62352d646e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301752359 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.usbdev_tx_rx_disruption.301752359
Directory /workspace/45.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/450.usbdev_tx_rx_disruption.1826049356
Short name T1020
Test name
Test status
Simulation time 512778983 ps
CPU time 1.59 seconds
Started Aug 11 07:18:11 PM PDT 24
Finished Aug 11 07:18:12 PM PDT 24
Peak memory 207500 kb
Host smart-2bc928dd-dd6c-45b2-af02-563cc8691910
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826049356 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 450.usbdev_tx_rx_disruption.1826049356
Directory /workspace/450.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/451.usbdev_tx_rx_disruption.3086763014
Short name T1451
Test name
Test status
Simulation time 492384558 ps
CPU time 1.5 seconds
Started Aug 11 07:18:08 PM PDT 24
Finished Aug 11 07:18:09 PM PDT 24
Peak memory 207524 kb
Host smart-c85d865e-067e-4880-bcb3-4433d038838a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086763014 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 451.usbdev_tx_rx_disruption.3086763014
Directory /workspace/451.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/452.usbdev_tx_rx_disruption.2952540303
Short name T1069
Test name
Test status
Simulation time 532494278 ps
CPU time 1.61 seconds
Started Aug 11 07:18:12 PM PDT 24
Finished Aug 11 07:18:13 PM PDT 24
Peak memory 207596 kb
Host smart-0645a2cf-783c-4713-b4d4-24ac5b2028d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952540303 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 452.usbdev_tx_rx_disruption.2952540303
Directory /workspace/452.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/453.usbdev_tx_rx_disruption.3094891403
Short name T2380
Test name
Test status
Simulation time 493230280 ps
CPU time 1.42 seconds
Started Aug 11 07:18:12 PM PDT 24
Finished Aug 11 07:18:14 PM PDT 24
Peak memory 207600 kb
Host smart-1120f51e-2eed-4663-a548-d33a80e36dba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094891403 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 453.usbdev_tx_rx_disruption.3094891403
Directory /workspace/453.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/454.usbdev_tx_rx_disruption.2007380803
Short name T3580
Test name
Test status
Simulation time 596735639 ps
CPU time 1.56 seconds
Started Aug 11 07:18:22 PM PDT 24
Finished Aug 11 07:18:24 PM PDT 24
Peak memory 207600 kb
Host smart-c50f1c87-acb2-422b-8f97-8832db63692f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007380803 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 454.usbdev_tx_rx_disruption.2007380803
Directory /workspace/454.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/455.usbdev_tx_rx_disruption.973126269
Short name T3586
Test name
Test status
Simulation time 458677769 ps
CPU time 1.45 seconds
Started Aug 11 07:18:24 PM PDT 24
Finished Aug 11 07:18:26 PM PDT 24
Peak memory 207608 kb
Host smart-c02c326b-4d8c-4508-9650-91af4af16343
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973126269 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 455.usbdev_tx_rx_disruption.973126269
Directory /workspace/455.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/456.usbdev_tx_rx_disruption.4100064069
Short name T566
Test name
Test status
Simulation time 450803919 ps
CPU time 1.4 seconds
Started Aug 11 07:18:25 PM PDT 24
Finished Aug 11 07:18:26 PM PDT 24
Peak memory 207516 kb
Host smart-93d7423b-8481-4c43-a302-4ebc3b6003a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100064069 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 456.usbdev_tx_rx_disruption.4100064069
Directory /workspace/456.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/457.usbdev_tx_rx_disruption.4103086040
Short name T2283
Test name
Test status
Simulation time 548430135 ps
CPU time 1.68 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207504 kb
Host smart-20154d34-4858-488b-b5eb-c81b85e2834d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103086040 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 457.usbdev_tx_rx_disruption.4103086040
Directory /workspace/457.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/458.usbdev_tx_rx_disruption.1649940991
Short name T799
Test name
Test status
Simulation time 470110751 ps
CPU time 1.47 seconds
Started Aug 11 07:18:10 PM PDT 24
Finished Aug 11 07:18:11 PM PDT 24
Peak memory 207572 kb
Host smart-8468e7c2-7317-4887-8c12-d643d3faed9c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649940991 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 458.usbdev_tx_rx_disruption.1649940991
Directory /workspace/458.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/459.usbdev_tx_rx_disruption.3996566882
Short name T3287
Test name
Test status
Simulation time 593818842 ps
CPU time 1.68 seconds
Started Aug 11 07:18:20 PM PDT 24
Finished Aug 11 07:18:22 PM PDT 24
Peak memory 207584 kb
Host smart-2efb202f-a1a5-4420-8270-c7fdae2add3b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996566882 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 459.usbdev_tx_rx_disruption.3996566882
Directory /workspace/459.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/46.usbdev_alert_test.2429733956
Short name T2852
Test name
Test status
Simulation time 73535928 ps
CPU time 0.71 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207448 kb
Host smart-5d8e1fd9-5dd2-4ac3-81fc-859f3f59e8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2429733956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2429733956
Directory /workspace/46.usbdev_alert_test/latest


Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.4029297758
Short name T1283
Test name
Test status
Simulation time 4767931668 ps
CPU time 6.5 seconds
Started Aug 11 07:16:07 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 215948 kb
Host smart-ed09d5de-214f-424c-a2a5-ce0eaaa7e22b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029297758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.4029297758
Directory /workspace/46.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3288074295
Short name T1404
Test name
Test status
Simulation time 29392503678 ps
CPU time 37.59 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:51 PM PDT 24
Peak memory 207868 kb
Host smart-98e3e9f4-5446-441a-874a-334288b7b78b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288074295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.3288074295
Directory /workspace/46.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/46.usbdev_av_buffer.184905349
Short name T1703
Test name
Test status
Simulation time 195660274 ps
CPU time 0.95 seconds
Started Aug 11 07:16:09 PM PDT 24
Finished Aug 11 07:16:10 PM PDT 24
Peak memory 207544 kb
Host smart-d664d16d-181c-4344-8347-4b6e513bb444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18490
5349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.184905349
Directory /workspace/46.usbdev_av_buffer/latest


Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2616414804
Short name T79
Test name
Test status
Simulation time 149053273 ps
CPU time 0.83 seconds
Started Aug 11 07:16:07 PM PDT 24
Finished Aug 11 07:16:08 PM PDT 24
Peak memory 207524 kb
Host smart-29d50dd0-c4da-4408-9d85-d5cdaa7386fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26164
14804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2616414804
Directory /workspace/46.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.199995540
Short name T2216
Test name
Test status
Simulation time 372395156 ps
CPU time 1.25 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207572 kb
Host smart-5aea0e9b-cd20-43c2-a29e-0dabfdba664f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19999
5540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.199995540
Directory /workspace/46.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3630368801
Short name T2590
Test name
Test status
Simulation time 315576051 ps
CPU time 1.06 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207544 kb
Host smart-efb1e338-d799-4276-a695-e265854e39c7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3630368801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3630368801
Directory /workspace/46.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/46.usbdev_device_address.1779760947
Short name T2859
Test name
Test status
Simulation time 16819405708 ps
CPU time 28.96 seconds
Started Aug 11 07:16:02 PM PDT 24
Finished Aug 11 07:16:31 PM PDT 24
Peak memory 207832 kb
Host smart-aee549e0-3ea2-497b-94f1-828969d70285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17797
60947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.1779760947
Directory /workspace/46.usbdev_device_address/latest


Test location /workspace/coverage/default/46.usbdev_device_timeout.1482333274
Short name T1858
Test name
Test status
Simulation time 418568024 ps
CPU time 7.66 seconds
Started Aug 11 07:16:20 PM PDT 24
Finished Aug 11 07:16:28 PM PDT 24
Peak memory 207684 kb
Host smart-c6c8dc26-09f6-4398-992a-ccf034c9f939
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482333274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.1482333274
Directory /workspace/46.usbdev_device_timeout/latest


Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3084597818
Short name T2835
Test name
Test status
Simulation time 989712227 ps
CPU time 2.05 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207520 kb
Host smart-9016327a-3b1d-4ec3-a57f-19745f9dbdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30845
97818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3084597818
Directory /workspace/46.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/46.usbdev_disconnected.593689058
Short name T938
Test name
Test status
Simulation time 146471992 ps
CPU time 0.81 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:11 PM PDT 24
Peak memory 207524 kb
Host smart-e06b1d3b-7687-4322-847b-2870918bb7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59368
9058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.593689058
Directory /workspace/46.usbdev_disconnected/latest


Test location /workspace/coverage/default/46.usbdev_enable.1047740905
Short name T2426
Test name
Test status
Simulation time 88758834 ps
CPU time 0.8 seconds
Started Aug 11 07:16:17 PM PDT 24
Finished Aug 11 07:16:17 PM PDT 24
Peak memory 207516 kb
Host smart-5d2e0e10-ac43-4dd2-8c46-4197e28d2c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10477
40905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1047740905
Directory /workspace/46.usbdev_enable/latest


Test location /workspace/coverage/default/46.usbdev_endpoint_access.1209272762
Short name T1946
Test name
Test status
Simulation time 991732502 ps
CPU time 2.67 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207724 kb
Host smart-02204e17-03f6-43dc-8c70-4e343a109b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
72762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1209272762
Directory /workspace/46.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/46.usbdev_endpoint_types.1464140765
Short name T3080
Test name
Test status
Simulation time 257180424 ps
CPU time 1.05 seconds
Started Aug 11 07:16:07 PM PDT 24
Finished Aug 11 07:16:09 PM PDT 24
Peak memory 207516 kb
Host smart-acc8f8a7-27bc-4a59-b9f5-cf16c426b4c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1464140765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.1464140765
Directory /workspace/46.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/46.usbdev_fifo_rst.3814326494
Short name T2618
Test name
Test status
Simulation time 233816516 ps
CPU time 2.19 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207716 kb
Host smart-25d43e48-a900-43a7-8154-524ddf22b73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38143
26494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3814326494
Directory /workspace/46.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/46.usbdev_in_iso.783854556
Short name T1782
Test name
Test status
Simulation time 230411433 ps
CPU time 1.18 seconds
Started Aug 11 07:16:19 PM PDT 24
Finished Aug 11 07:16:21 PM PDT 24
Peak memory 215936 kb
Host smart-ca3486f9-81b8-4e26-a954-a49e53719eef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=783854556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.783854556
Directory /workspace/46.usbdev_in_iso/latest


Test location /workspace/coverage/default/46.usbdev_in_stall.3184922859
Short name T2319
Test name
Test status
Simulation time 150925974 ps
CPU time 0.83 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207536 kb
Host smart-c6a6c25e-85c0-4887-91f1-3646a83848be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31849
22859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3184922859
Directory /workspace/46.usbdev_in_stall/latest


Test location /workspace/coverage/default/46.usbdev_in_trans.1768096939
Short name T1875
Test name
Test status
Simulation time 223082051 ps
CPU time 0.99 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:17 PM PDT 24
Peak memory 207548 kb
Host smart-3aebce94-ab1b-4747-b0f5-699d69f81c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17680
96939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1768096939
Directory /workspace/46.usbdev_in_trans/latest


Test location /workspace/coverage/default/46.usbdev_invalid_sync.4160534146
Short name T2486
Test name
Test status
Simulation time 3820139686 ps
CPU time 30.35 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 216112 kb
Host smart-3c85baf4-09ee-4731-bb3f-85c855c75ca8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4160534146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.4160534146
Directory /workspace/46.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/46.usbdev_iso_retraction.2434031547
Short name T973
Test name
Test status
Simulation time 11033258636 ps
CPU time 133.64 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:18:29 PM PDT 24
Peak memory 207824 kb
Host smart-f914c873-865d-4f9b-b5e6-a989379fb2e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2434031547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.2434031547
Directory /workspace/46.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/46.usbdev_link_in_err.3933194620
Short name T1468
Test name
Test status
Simulation time 201453211 ps
CPU time 0.96 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:11 PM PDT 24
Peak memory 207572 kb
Host smart-0bd64b00-cf5e-4f3c-bd2c-784bed0d4fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39331
94620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3933194620
Directory /workspace/46.usbdev_link_in_err/latest


Test location /workspace/coverage/default/46.usbdev_link_resume.77003329
Short name T2961
Test name
Test status
Simulation time 10954418446 ps
CPU time 18.31 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:32 PM PDT 24
Peak memory 216092 kb
Host smart-da6aa7f1-2c2e-4706-b54d-7f491922faed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77003
329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.77003329
Directory /workspace/46.usbdev_link_resume/latest


Test location /workspace/coverage/default/46.usbdev_link_suspend.1991128447
Short name T1476
Test name
Test status
Simulation time 9618259294 ps
CPU time 13.64 seconds
Started Aug 11 07:16:16 PM PDT 24
Finished Aug 11 07:16:30 PM PDT 24
Peak memory 207848 kb
Host smart-2e8f2b7a-c1b8-497d-9620-55a068750ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19911
28447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1991128447
Directory /workspace/46.usbdev_link_suspend/latest


Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.4031215850
Short name T1408
Test name
Test status
Simulation time 4422504731 ps
CPU time 36.59 seconds
Started Aug 11 07:16:05 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 220144 kb
Host smart-de7d98f1-2f6b-4d5e-945c-0ca78bc707a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4031215850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.4031215850
Directory /workspace/46.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3382226835
Short name T2882
Test name
Test status
Simulation time 3354429066 ps
CPU time 24.58 seconds
Started Aug 11 07:16:32 PM PDT 24
Finished Aug 11 07:16:57 PM PDT 24
Peak memory 216136 kb
Host smart-23446bb9-9f78-4354-8a7c-bd5077b94f3b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3382226835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3382226835
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.792175328
Short name T2993
Test name
Test status
Simulation time 255845885 ps
CPU time 0.98 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207588 kb
Host smart-0520eeb4-d719-4b9b-bda7-fc80a5036f66
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=792175328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.792175328
Directory /workspace/46.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3796067214
Short name T1102
Test name
Test status
Simulation time 186325681 ps
CPU time 0.94 seconds
Started Aug 11 07:16:24 PM PDT 24
Finished Aug 11 07:16:25 PM PDT 24
Peak memory 207548 kb
Host smart-652b36c7-6e1b-4b37-b211-dc3aec2a37de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37960
67214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3796067214
Directory /workspace/46.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.570598359
Short name T2674
Test name
Test status
Simulation time 2752232309 ps
CPU time 20.21 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:35 PM PDT 24
Peak memory 215992 kb
Host smart-97dfec18-2eec-45e0-b3c0-42faa6f94f9e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=570598359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.570598359
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.34312624
Short name T2953
Test name
Test status
Simulation time 151249752 ps
CPU time 0.91 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207568 kb
Host smart-7c018339-a556-421b-aba0-1f133f490059
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=34312624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.34312624
Directory /workspace/46.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.603180555
Short name T1501
Test name
Test status
Simulation time 178079195 ps
CPU time 0.9 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207496 kb
Host smart-9e817f2c-06ef-411e-a97c-7a350fce7639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60318
0555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.603180555
Directory /workspace/46.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_nak_trans.366909530
Short name T146
Test name
Test status
Simulation time 228877047 ps
CPU time 0.98 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207708 kb
Host smart-0f68b08d-710e-43b1-905b-1699a9b96097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36690
9530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.366909530
Directory /workspace/46.usbdev_nak_trans/latest


Test location /workspace/coverage/default/46.usbdev_out_iso.2157639951
Short name T1173
Test name
Test status
Simulation time 226867328 ps
CPU time 0.97 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:11 PM PDT 24
Peak memory 207492 kb
Host smart-f2bbb05e-9e97-4307-880e-be5ca952bb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21576
39951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2157639951
Directory /workspace/46.usbdev_out_iso/latest


Test location /workspace/coverage/default/46.usbdev_out_stall.3490197581
Short name T2204
Test name
Test status
Simulation time 230471544 ps
CPU time 0.99 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:11 PM PDT 24
Peak memory 207524 kb
Host smart-c19284b8-43b9-45dc-b2e5-b0e43fee69ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34901
97581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3490197581
Directory /workspace/46.usbdev_out_stall/latest


Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3870933949
Short name T916
Test name
Test status
Simulation time 174248063 ps
CPU time 0.88 seconds
Started Aug 11 07:16:11 PM PDT 24
Finished Aug 11 07:16:12 PM PDT 24
Peak memory 207572 kb
Host smart-bdbc2de1-5e58-4774-a46d-929cac502d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
33949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3870933949
Directory /workspace/46.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2187135935
Short name T169
Test name
Test status
Simulation time 189672808 ps
CPU time 0.88 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207572 kb
Host smart-c7ce67b9-e8e4-41d4-af23-070da13773ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21871
35935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2187135935
Directory /workspace/46.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.406706546
Short name T2660
Test name
Test status
Simulation time 247671302 ps
CPU time 1.05 seconds
Started Aug 11 07:16:17 PM PDT 24
Finished Aug 11 07:16:23 PM PDT 24
Peak memory 207564 kb
Host smart-cc7e3aab-d9f7-418f-bc74-4cce32cc0d7d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=406706546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.406706546
Directory /workspace/46.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3199624884
Short name T3316
Test name
Test status
Simulation time 156317413 ps
CPU time 0.91 seconds
Started Aug 11 07:16:24 PM PDT 24
Finished Aug 11 07:16:25 PM PDT 24
Peak memory 207516 kb
Host smart-bec78d86-6d83-487b-95c3-a4d744594d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31996
24884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3199624884
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.753963238
Short name T1155
Test name
Test status
Simulation time 61208181 ps
CPU time 0.74 seconds
Started Aug 11 07:16:19 PM PDT 24
Finished Aug 11 07:16:20 PM PDT 24
Peak memory 207476 kb
Host smart-e3e8a9df-098c-4a41-9024-8f7e06175b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75396
3238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.753963238
Directory /workspace/46.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/46.usbdev_pkt_buffer.858334676
Short name T2548
Test name
Test status
Simulation time 7941306414 ps
CPU time 19.26 seconds
Started Aug 11 07:16:23 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 224276 kb
Host smart-65d07c5b-4215-4c0a-a673-76792e99d767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85833
4676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.858334676
Directory /workspace/46.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/46.usbdev_pkt_received.2759282068
Short name T1201
Test name
Test status
Simulation time 217147568 ps
CPU time 1.02 seconds
Started Aug 11 07:16:16 PM PDT 24
Finished Aug 11 07:16:17 PM PDT 24
Peak memory 207552 kb
Host smart-7a83959d-6ec5-4fbe-9607-eec7c26e4dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27592
82068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2759282068
Directory /workspace/46.usbdev_pkt_received/latest


Test location /workspace/coverage/default/46.usbdev_pkt_sent.242143975
Short name T558
Test name
Test status
Simulation time 215829257 ps
CPU time 0.94 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:11 PM PDT 24
Peak memory 207544 kb
Host smart-f95b9f37-9c12-4cc6-99c2-164767f6c2e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24214
3975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.242143975
Directory /workspace/46.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.1305852826
Short name T2507
Test name
Test status
Simulation time 165454340 ps
CPU time 0.83 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:10 PM PDT 24
Peak memory 207396 kb
Host smart-bb293910-e862-4fa6-83ce-99b57a1fc98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13058
52826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.1305852826
Directory /workspace/46.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1755136383
Short name T842
Test name
Test status
Simulation time 202528358 ps
CPU time 0.89 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:13 PM PDT 24
Peak memory 207580 kb
Host smart-76e51098-a25d-4474-80e5-4b5115f8255f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551
36383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1755136383
Directory /workspace/46.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3005662466
Short name T2641
Test name
Test status
Simulation time 231068171 ps
CPU time 1.02 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:13 PM PDT 24
Peak memory 207508 kb
Host smart-a2c6c35f-a7ae-43f8-8d36-0ae3d3497662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30056
62466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3005662466
Directory /workspace/46.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/46.usbdev_rx_full.2642829754
Short name T1938
Test name
Test status
Simulation time 280995507 ps
CPU time 1.22 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207572 kb
Host smart-9c81a76e-8f06-4020-b538-e85805a5dc35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26428
29754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.2642829754
Directory /workspace/46.usbdev_rx_full/latest


Test location /workspace/coverage/default/46.usbdev_setup_stage.2173812952
Short name T2827
Test name
Test status
Simulation time 216826644 ps
CPU time 0.91 seconds
Started Aug 11 07:16:20 PM PDT 24
Finished Aug 11 07:16:21 PM PDT 24
Peak memory 207384 kb
Host smart-75751d66-1b74-4d16-868c-21f744926702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21738
12952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2173812952
Directory /workspace/46.usbdev_setup_stage/latest


Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.882504433
Short name T2217
Test name
Test status
Simulation time 163596568 ps
CPU time 0.83 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207540 kb
Host smart-3fc0b119-517c-4d3c-9ef0-219a752ac7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88250
4433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.882504433
Directory /workspace/46.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/46.usbdev_smoke.2279924365
Short name T2032
Test name
Test status
Simulation time 298120726 ps
CPU time 1.05 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207588 kb
Host smart-1c0e7cfb-eb6f-4d07-bb84-b0280879fee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22799
24365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2279924365
Directory /workspace/46.usbdev_smoke/latest


Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.899404000
Short name T1686
Test name
Test status
Simulation time 3485696218 ps
CPU time 36.27 seconds
Started Aug 11 07:16:24 PM PDT 24
Finished Aug 11 07:17:01 PM PDT 24
Peak memory 218028 kb
Host smart-33fe2aa4-2aee-4f8b-a788-4fc3032730a8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=899404000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.899404000
Directory /workspace/46.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3189383426
Short name T2144
Test name
Test status
Simulation time 209714430 ps
CPU time 0.93 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207456 kb
Host smart-6a2b62a6-c2c7-4466-83ec-50948f6ff6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31893
83426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3189383426
Directory /workspace/46.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/46.usbdev_stall_trans.4222621668
Short name T1784
Test name
Test status
Simulation time 192347221 ps
CPU time 0.9 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207552 kb
Host smart-c83d00c4-65e8-4061-abeb-79226cbf901c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42226
21668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.4222621668
Directory /workspace/46.usbdev_stall_trans/latest


Test location /workspace/coverage/default/46.usbdev_stream_len_max.1291916313
Short name T1089
Test name
Test status
Simulation time 1391509316 ps
CPU time 3.26 seconds
Started Aug 11 07:16:03 PM PDT 24
Finished Aug 11 07:16:06 PM PDT 24
Peak memory 207696 kb
Host smart-21e401be-3697-4a60-b3e4-d9e8f1669a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12919
16313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.1291916313
Directory /workspace/46.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/46.usbdev_streaming_out.3171863717
Short name T1343
Test name
Test status
Simulation time 3980621830 ps
CPU time 30.62 seconds
Started Aug 11 07:16:06 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 217744 kb
Host smart-2fc70eba-d90f-4024-b6e6-99561806c38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31718
63717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3171863717
Directory /workspace/46.usbdev_streaming_out/latest


Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.722061240
Short name T725
Test name
Test status
Simulation time 183570934 ps
CPU time 1.07 seconds
Started Aug 11 07:16:08 PM PDT 24
Finished Aug 11 07:16:09 PM PDT 24
Peak memory 207504 kb
Host smart-e4268267-b6cc-4599-80c4-b6819d139fe2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722061240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_host
_handshake.722061240
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/46.usbdev_tx_rx_disruption.2834539940
Short name T3415
Test name
Test status
Simulation time 708679992 ps
CPU time 1.77 seconds
Started Aug 11 07:16:17 PM PDT 24
Finished Aug 11 07:16:19 PM PDT 24
Peak memory 207476 kb
Host smart-f46a7c16-e8a3-478e-92fd-0ba67ae3f130
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834539940 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.usbdev_tx_rx_disruption.2834539940
Directory /workspace/46.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/460.usbdev_tx_rx_disruption.196512526
Short name T2058
Test name
Test status
Simulation time 558623339 ps
CPU time 1.75 seconds
Started Aug 11 07:18:31 PM PDT 24
Finished Aug 11 07:18:32 PM PDT 24
Peak memory 207544 kb
Host smart-c9f62552-c738-43a7-85a0-afa117637be9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196512526 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 460.usbdev_tx_rx_disruption.196512526
Directory /workspace/460.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/461.usbdev_tx_rx_disruption.2906103729
Short name T2798
Test name
Test status
Simulation time 599792786 ps
CPU time 1.64 seconds
Started Aug 11 07:18:08 PM PDT 24
Finished Aug 11 07:18:10 PM PDT 24
Peak memory 207600 kb
Host smart-4358a9e2-5e56-4473-b4ea-eb22a67f2116
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906103729 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 461.usbdev_tx_rx_disruption.2906103729
Directory /workspace/461.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/462.usbdev_tx_rx_disruption.3039381094
Short name T2532
Test name
Test status
Simulation time 506811789 ps
CPU time 1.53 seconds
Started Aug 11 07:18:11 PM PDT 24
Finished Aug 11 07:18:13 PM PDT 24
Peak memory 207600 kb
Host smart-d9795624-2557-4d31-a3d2-a1d5506e0af5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039381094 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 462.usbdev_tx_rx_disruption.3039381094
Directory /workspace/462.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/463.usbdev_tx_rx_disruption.1652621080
Short name T2221
Test name
Test status
Simulation time 589045123 ps
CPU time 1.58 seconds
Started Aug 11 07:18:03 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207520 kb
Host smart-735f4f74-5d2c-46e8-86b0-d97bc890e48e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652621080 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 463.usbdev_tx_rx_disruption.1652621080
Directory /workspace/463.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/464.usbdev_tx_rx_disruption.4049565857
Short name T1457
Test name
Test status
Simulation time 530764999 ps
CPU time 1.53 seconds
Started Aug 11 07:17:57 PM PDT 24
Finished Aug 11 07:17:59 PM PDT 24
Peak memory 207572 kb
Host smart-044e2f89-3f0b-426c-9f2f-4a83a532e272
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049565857 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 464.usbdev_tx_rx_disruption.4049565857
Directory /workspace/464.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/465.usbdev_tx_rx_disruption.1148873199
Short name T2279
Test name
Test status
Simulation time 445253445 ps
CPU time 1.46 seconds
Started Aug 11 07:17:58 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207544 kb
Host smart-be2985ff-0d39-48bb-ad42-8a45aa5b531e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148873199 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 465.usbdev_tx_rx_disruption.1148873199
Directory /workspace/465.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/466.usbdev_tx_rx_disruption.92414732
Short name T171
Test name
Test status
Simulation time 537477284 ps
CPU time 1.72 seconds
Started Aug 11 07:18:23 PM PDT 24
Finished Aug 11 07:18:24 PM PDT 24
Peak memory 207592 kb
Host smart-a26f3122-ba6c-4c2e-9a46-36e74c5cc7e7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92414732 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 466.usbdev_tx_rx_disruption.92414732
Directory /workspace/466.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/467.usbdev_tx_rx_disruption.450603736
Short name T1572
Test name
Test status
Simulation time 440229777 ps
CPU time 1.42 seconds
Started Aug 11 07:18:19 PM PDT 24
Finished Aug 11 07:18:21 PM PDT 24
Peak memory 207552 kb
Host smart-86dc0abd-18a0-43b7-939a-6175b775a5c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450603736 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 467.usbdev_tx_rx_disruption.450603736
Directory /workspace/467.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/468.usbdev_tx_rx_disruption.3934034131
Short name T1253
Test name
Test status
Simulation time 496667243 ps
CPU time 1.6 seconds
Started Aug 11 07:18:09 PM PDT 24
Finished Aug 11 07:18:11 PM PDT 24
Peak memory 207764 kb
Host smart-20ddd3dd-4957-4801-9988-f5c330dfcdaa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934034131 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 468.usbdev_tx_rx_disruption.3934034131
Directory /workspace/468.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/469.usbdev_tx_rx_disruption.3626182308
Short name T609
Test name
Test status
Simulation time 425534755 ps
CPU time 1.43 seconds
Started Aug 11 07:18:03 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207536 kb
Host smart-15cf863a-d93c-4469-a258-d12c28b84a3f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626182308 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 469.usbdev_tx_rx_disruption.3626182308
Directory /workspace/469.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/47.usbdev_alert_test.215889579
Short name T3446
Test name
Test status
Simulation time 40820865 ps
CPU time 0.65 seconds
Started Aug 11 07:16:22 PM PDT 24
Finished Aug 11 07:16:23 PM PDT 24
Peak memory 207612 kb
Host smart-85ee06de-7376-40e0-8276-bc40f733d229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=215889579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.215889579
Directory /workspace/47.usbdev_alert_test/latest


Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.4008846618
Short name T1526
Test name
Test status
Simulation time 4694154639 ps
CPU time 7.9 seconds
Started Aug 11 07:16:23 PM PDT 24
Finished Aug 11 07:16:31 PM PDT 24
Peak memory 216252 kb
Host smart-b3e13d66-b1e5-4d3f-aa1d-e24475eb36d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008846618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.4008846618
Directory /workspace/47.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2532164546
Short name T1250
Test name
Test status
Simulation time 18489070519 ps
CPU time 20.14 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:35 PM PDT 24
Peak memory 207836 kb
Host smart-a5c26de8-05dd-4d51-b3a4-fcd8db013749
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532164546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2532164546
Directory /workspace/47.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2077504662
Short name T1470
Test name
Test status
Simulation time 25032956825 ps
CPU time 31.9 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:44 PM PDT 24
Peak memory 216028 kb
Host smart-2364483a-a042-4edf-b51a-6a28fffb22f6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077504662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.2077504662
Directory /workspace/47.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/47.usbdev_av_buffer.1467090692
Short name T3359
Test name
Test status
Simulation time 172408924 ps
CPU time 0.86 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207576 kb
Host smart-0626f296-a409-4acb-83e3-baace244fc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14670
90692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1467090692
Directory /workspace/47.usbdev_av_buffer/latest


Test location /workspace/coverage/default/47.usbdev_bitstuff_err.265380621
Short name T3122
Test name
Test status
Simulation time 192747323 ps
CPU time 0.86 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207560 kb
Host smart-70413268-5854-43e1-a15a-5105c882de43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26538
0621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.265380621
Directory /workspace/47.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.4203214863
Short name T1077
Test name
Test status
Simulation time 321080224 ps
CPU time 1.23 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207560 kb
Host smart-c09a8220-cca1-40b3-8e27-5b62cf851e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42032
14863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.4203214863
Directory /workspace/47.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1705039429
Short name T351
Test name
Test status
Simulation time 825945415 ps
CPU time 2.32 seconds
Started Aug 11 07:16:16 PM PDT 24
Finished Aug 11 07:16:18 PM PDT 24
Peak memory 207764 kb
Host smart-a6ca8e27-0b4e-49b4-bea8-f9bcbbea8d5f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1705039429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1705039429
Directory /workspace/47.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/47.usbdev_device_address.539673344
Short name T1443
Test name
Test status
Simulation time 40372079624 ps
CPU time 67.35 seconds
Started Aug 11 07:16:11 PM PDT 24
Finished Aug 11 07:17:18 PM PDT 24
Peak memory 207796 kb
Host smart-9a2a5f56-5734-4e94-a79b-3192deff14c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53967
3344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.539673344
Directory /workspace/47.usbdev_device_address/latest


Test location /workspace/coverage/default/47.usbdev_device_timeout.392321461
Short name T2703
Test name
Test status
Simulation time 2040606036 ps
CPU time 13.62 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:27 PM PDT 24
Peak memory 207696 kb
Host smart-f778c701-f150-402b-9008-4d38113fc50a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392321461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.392321461
Directory /workspace/47.usbdev_device_timeout/latest


Test location /workspace/coverage/default/47.usbdev_disable_endpoint.3972293232
Short name T1370
Test name
Test status
Simulation time 697472337 ps
CPU time 1.75 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207548 kb
Host smart-0ecda976-5a2d-4595-b7c9-608978273fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39722
93232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3972293232
Directory /workspace/47.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/47.usbdev_disconnected.2767586770
Short name T2570
Test name
Test status
Simulation time 142838566 ps
CPU time 0.82 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:11 PM PDT 24
Peak memory 207516 kb
Host smart-b6f818a8-10f5-43bc-b308-c2f1f289e05d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
86770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2767586770
Directory /workspace/47.usbdev_disconnected/latest


Test location /workspace/coverage/default/47.usbdev_enable.677717837
Short name T921
Test name
Test status
Simulation time 40767646 ps
CPU time 0.71 seconds
Started Aug 11 07:16:21 PM PDT 24
Finished Aug 11 07:16:21 PM PDT 24
Peak memory 207540 kb
Host smart-409e6d37-6fed-4023-9328-1ac8d267e79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67771
7837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.677717837
Directory /workspace/47.usbdev_enable/latest


Test location /workspace/coverage/default/47.usbdev_endpoint_access.1775441392
Short name T1162
Test name
Test status
Simulation time 936974585 ps
CPU time 2.54 seconds
Started Aug 11 07:16:06 PM PDT 24
Finished Aug 11 07:16:09 PM PDT 24
Peak memory 207752 kb
Host smart-4ef9501d-5cf4-43d8-ac7d-d378c300a73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17754
41392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1775441392
Directory /workspace/47.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/47.usbdev_endpoint_types.2339770063
Short name T525
Test name
Test status
Simulation time 278420736 ps
CPU time 1.08 seconds
Started Aug 11 07:16:23 PM PDT 24
Finished Aug 11 07:16:25 PM PDT 24
Peak memory 207536 kb
Host smart-e32071cf-80cd-4780-9d57-5c45008ead36
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2339770063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.2339770063
Directory /workspace/47.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/47.usbdev_fifo_rst.470810876
Short name T784
Test name
Test status
Simulation time 353167704 ps
CPU time 2.52 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207492 kb
Host smart-63fd7dc2-dde8-4dc2-ae19-7d66c651814b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47081
0876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.470810876
Directory /workspace/47.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/47.usbdev_in_iso.31564730
Short name T2121
Test name
Test status
Simulation time 217395957 ps
CPU time 1.13 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:16:12 PM PDT 24
Peak memory 215888 kb
Host smart-4d9c75f2-e30b-4942-8c76-4c2e628d5377
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=31564730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.31564730
Directory /workspace/47.usbdev_in_iso/latest


Test location /workspace/coverage/default/47.usbdev_in_stall.2483379196
Short name T2347
Test name
Test status
Simulation time 180610575 ps
CPU time 0.94 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:13 PM PDT 24
Peak memory 207476 kb
Host smart-893938d1-6438-4bc9-bec2-05cc44b70c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24833
79196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2483379196
Directory /workspace/47.usbdev_in_stall/latest


Test location /workspace/coverage/default/47.usbdev_in_trans.3866080608
Short name T1791
Test name
Test status
Simulation time 151311017 ps
CPU time 0.87 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207552 kb
Host smart-e8af671a-5e4e-4a57-9450-53576f9b6cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38660
80608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3866080608
Directory /workspace/47.usbdev_in_trans/latest


Test location /workspace/coverage/default/47.usbdev_invalid_sync.243859565
Short name T2197
Test name
Test status
Simulation time 4135032181 ps
CPU time 123.07 seconds
Started Aug 11 07:16:10 PM PDT 24
Finished Aug 11 07:18:13 PM PDT 24
Peak memory 217672 kb
Host smart-7143453a-eb5c-4882-af35-e410cde0afa2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=243859565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.243859565
Directory /workspace/47.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/47.usbdev_iso_retraction.588807250
Short name T825
Test name
Test status
Simulation time 12494036285 ps
CPU time 90.46 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:17:44 PM PDT 24
Peak memory 207780 kb
Host smart-e6738eca-42b4-4821-a517-91a309a395c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=588807250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.588807250
Directory /workspace/47.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/47.usbdev_link_in_err.1174589415
Short name T2226
Test name
Test status
Simulation time 209039484 ps
CPU time 0.92 seconds
Started Aug 11 07:16:09 PM PDT 24
Finished Aug 11 07:16:10 PM PDT 24
Peak memory 207548 kb
Host smart-61375eee-a814-466b-b66d-c208148f7e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11745
89415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1174589415
Directory /workspace/47.usbdev_link_in_err/latest


Test location /workspace/coverage/default/47.usbdev_link_resume.485304621
Short name T2579
Test name
Test status
Simulation time 12139166004 ps
CPU time 16.94 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:31 PM PDT 24
Peak memory 207864 kb
Host smart-a76c2536-2c3d-4bba-922f-6eb2e02f2350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48530
4621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.485304621
Directory /workspace/47.usbdev_link_resume/latest


Test location /workspace/coverage/default/47.usbdev_link_suspend.2425763638
Short name T2815
Test name
Test status
Simulation time 8366081522 ps
CPU time 10.93 seconds
Started Aug 11 07:16:26 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207864 kb
Host smart-e1276993-aba1-4dad-aac0-58dc33e203e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24257
63638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2425763638
Directory /workspace/47.usbdev_link_suspend/latest


Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.33807761
Short name T2563
Test name
Test status
Simulation time 3878469962 ps
CPU time 31.28 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:45 PM PDT 24
Peak memory 219312 kb
Host smart-bd089085-e8f2-4fb6-862c-158cd7871366
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=33807761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.33807761
Directory /workspace/47.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2489800629
Short name T668
Test name
Test status
Simulation time 2475682355 ps
CPU time 18.86 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 217844 kb
Host smart-1969586f-fa9e-43fc-9eee-2291374810f2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2489800629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2489800629
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3423867942
Short name T1533
Test name
Test status
Simulation time 242850802 ps
CPU time 1.02 seconds
Started Aug 11 07:16:23 PM PDT 24
Finished Aug 11 07:16:25 PM PDT 24
Peak memory 207520 kb
Host smart-70b0a929-8da7-4804-b392-6857358598b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3423867942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3423867942
Directory /workspace/47.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.843962613
Short name T1716
Test name
Test status
Simulation time 203291874 ps
CPU time 1 seconds
Started Aug 11 07:16:24 PM PDT 24
Finished Aug 11 07:16:25 PM PDT 24
Peak memory 207556 kb
Host smart-615ea33d-ed2e-498e-bd3f-544654d0a703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84396
2613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.843962613
Directory /workspace/47.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2232490281
Short name T1774
Test name
Test status
Simulation time 2583468544 ps
CPU time 72.89 seconds
Started Aug 11 07:16:18 PM PDT 24
Finished Aug 11 07:17:31 PM PDT 24
Peak memory 224264 kb
Host smart-4eca9edd-d87d-490b-af7e-40493f1ff10d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2232490281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2232490281
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.4270189515
Short name T2797
Test name
Test status
Simulation time 173949979 ps
CPU time 0.86 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207560 kb
Host smart-0784e9e5-8bca-4c8f-8416-c3117cfb86a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4270189515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.4270189515
Directory /workspace/47.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.4045835439
Short name T2209
Test name
Test status
Simulation time 155888035 ps
CPU time 0.94 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207580 kb
Host smart-5d04c7b6-11f2-4fc3-96e2-2c04917d1e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40458
35439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.4045835439
Directory /workspace/47.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_out_iso.4116851710
Short name T2386
Test name
Test status
Simulation time 172815061 ps
CPU time 0.92 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207580 kb
Host smart-6e611a68-66fa-4c87-82a8-414fb709aefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41168
51710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.4116851710
Directory /workspace/47.usbdev_out_iso/latest


Test location /workspace/coverage/default/47.usbdev_out_stall.3186299637
Short name T2397
Test name
Test status
Simulation time 173584835 ps
CPU time 0.87 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207496 kb
Host smart-e72b22df-afb2-49b0-b94a-614a067dfa99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31862
99637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3186299637
Directory /workspace/47.usbdev_out_stall/latest


Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2949732706
Short name T1510
Test name
Test status
Simulation time 211174459 ps
CPU time 1 seconds
Started Aug 11 07:16:20 PM PDT 24
Finished Aug 11 07:16:21 PM PDT 24
Peak memory 207516 kb
Host smart-2d689255-8140-47b2-973b-efe3a9c1069b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29497
32706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2949732706
Directory /workspace/47.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/47.usbdev_pending_in_trans.4236476971
Short name T1922
Test name
Test status
Simulation time 157816221 ps
CPU time 0.88 seconds
Started Aug 11 07:16:12 PM PDT 24
Finished Aug 11 07:16:13 PM PDT 24
Peak memory 207572 kb
Host smart-269951c7-2bd6-4d38-88d4-f60ed015e3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42364
76971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.4236476971
Directory /workspace/47.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3910965612
Short name T874
Test name
Test status
Simulation time 140299679 ps
CPU time 0.83 seconds
Started Aug 11 07:16:17 PM PDT 24
Finished Aug 11 07:16:18 PM PDT 24
Peak memory 207516 kb
Host smart-21ef0d8e-c066-402e-971a-a022dbae3730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39109
65612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3910965612
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2532715552
Short name T2606
Test name
Test status
Simulation time 69722689 ps
CPU time 0.72 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:32 PM PDT 24
Peak memory 207540 kb
Host smart-076e9528-8007-496b-aba7-334f053682e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25327
15552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2532715552
Directory /workspace/47.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1754719672
Short name T1783
Test name
Test status
Simulation time 9185381661 ps
CPU time 23.55 seconds
Started Aug 11 07:16:23 PM PDT 24
Finished Aug 11 07:16:47 PM PDT 24
Peak memory 216072 kb
Host smart-a9b1ef5f-5001-4076-acf8-32dded2ee598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17547
19672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1754719672
Directory /workspace/47.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/47.usbdev_pkt_received.1123424222
Short name T1333
Test name
Test status
Simulation time 169665746 ps
CPU time 0.89 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207548 kb
Host smart-819a76d4-ce2e-41f0-986f-d0feb2c17f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11234
24222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1123424222
Directory /workspace/47.usbdev_pkt_received/latest


Test location /workspace/coverage/default/47.usbdev_pkt_sent.3133094102
Short name T786
Test name
Test status
Simulation time 230085711 ps
CPU time 0.99 seconds
Started Aug 11 07:16:34 PM PDT 24
Finished Aug 11 07:16:35 PM PDT 24
Peak memory 207528 kb
Host smart-50032fd8-8edc-4fdb-ad9f-4dce13077183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31330
94102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3133094102
Directory /workspace/47.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1009044938
Short name T1740
Test name
Test status
Simulation time 234418014 ps
CPU time 0.95 seconds
Started Aug 11 07:16:18 PM PDT 24
Finished Aug 11 07:16:20 PM PDT 24
Peak memory 207492 kb
Host smart-679d04e1-2400-4cb5-bfae-4471c2ef1b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10090
44938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1009044938
Directory /workspace/47.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.315114259
Short name T2482
Test name
Test status
Simulation time 143769636 ps
CPU time 0.84 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207568 kb
Host smart-0d1f8aa8-b917-4227-8c85-0fe2e590e57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31511
4259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.315114259
Directory /workspace/47.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_rx_crc_err.352593102
Short name T2869
Test name
Test status
Simulation time 174280237 ps
CPU time 0.86 seconds
Started Aug 11 07:16:14 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207524 kb
Host smart-3412e119-cd50-41f4-8bc2-130cd0267d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35259
3102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.352593102
Directory /workspace/47.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/47.usbdev_rx_full.3032142233
Short name T1588
Test name
Test status
Simulation time 381157753 ps
CPU time 1.3 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207304 kb
Host smart-4bad2c28-7210-4307-9e86-2483cc939b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30321
42233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.3032142233
Directory /workspace/47.usbdev_rx_full/latest


Test location /workspace/coverage/default/47.usbdev_setup_stage.1206293419
Short name T2967
Test name
Test status
Simulation time 165544277 ps
CPU time 0.84 seconds
Started Aug 11 07:16:17 PM PDT 24
Finished Aug 11 07:16:18 PM PDT 24
Peak memory 207472 kb
Host smart-90c9a9d8-5e6e-4355-93db-ce80a6a1dce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12062
93419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1206293419
Directory /workspace/47.usbdev_setup_stage/latest


Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1126537244
Short name T3619
Test name
Test status
Simulation time 161707072 ps
CPU time 0.89 seconds
Started Aug 11 07:16:24 PM PDT 24
Finished Aug 11 07:16:25 PM PDT 24
Peak memory 207756 kb
Host smart-ed4bf4d3-1227-4203-9328-29d92ff43069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11265
37244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1126537244
Directory /workspace/47.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/47.usbdev_smoke.2863565077
Short name T741
Test name
Test status
Simulation time 262786209 ps
CPU time 1.07 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:14 PM PDT 24
Peak memory 207528 kb
Host smart-b3c1e9bc-8386-408f-9393-07ca0e24acf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28635
65077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2863565077
Directory /workspace/47.usbdev_smoke/latest


Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3907334821
Short name T387
Test name
Test status
Simulation time 3185529255 ps
CPU time 25.4 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:38 PM PDT 24
Peak memory 218048 kb
Host smart-e0fd44d5-7827-4631-8968-308bdf763d0a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3907334821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3907334821
Directory /workspace/47.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3151299456
Short name T839
Test name
Test status
Simulation time 197856726 ps
CPU time 0.96 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207500 kb
Host smart-aa912c2d-c78a-45de-9366-90c1ff30ac76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31512
99456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3151299456
Directory /workspace/47.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/47.usbdev_stall_trans.2773703529
Short name T2272
Test name
Test status
Simulation time 171875361 ps
CPU time 0.87 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207608 kb
Host smart-f4d084ff-40d3-4721-a8f5-075b8ec5cc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27737
03529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2773703529
Directory /workspace/47.usbdev_stall_trans/latest


Test location /workspace/coverage/default/47.usbdev_stream_len_max.1070582216
Short name T1656
Test name
Test status
Simulation time 208047866 ps
CPU time 1.03 seconds
Started Aug 11 07:16:15 PM PDT 24
Finished Aug 11 07:16:16 PM PDT 24
Peak memory 207516 kb
Host smart-057b58d4-4ffa-40b6-8675-c48879904e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
82216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1070582216
Directory /workspace/47.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/47.usbdev_streaming_out.1147207923
Short name T959
Test name
Test status
Simulation time 2795815829 ps
CPU time 21.44 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:35 PM PDT 24
Peak memory 216000 kb
Host smart-5a268a7d-6a09-4c0f-84ba-e4d445a275f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11472
07923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1147207923
Directory /workspace/47.usbdev_streaming_out/latest


Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.95393343
Short name T802
Test name
Test status
Simulation time 2439169988 ps
CPU time 21.26 seconds
Started Aug 11 07:16:25 PM PDT 24
Finished Aug 11 07:16:47 PM PDT 24
Peak memory 207768 kb
Host smart-a51f1816-7359-4b5d-ad06-97e0dc4d9895
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95393343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_host_
handshake.95393343
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/47.usbdev_tx_rx_disruption.2957383744
Short name T2806
Test name
Test status
Simulation time 598509247 ps
CPU time 1.65 seconds
Started Aug 11 07:16:20 PM PDT 24
Finished Aug 11 07:16:22 PM PDT 24
Peak memory 207540 kb
Host smart-e63483cd-671d-48f2-ae58-db0f2f248e59
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957383744 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.usbdev_tx_rx_disruption.2957383744
Directory /workspace/47.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/470.usbdev_tx_rx_disruption.2867912063
Short name T2169
Test name
Test status
Simulation time 491217607 ps
CPU time 1.51 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:02 PM PDT 24
Peak memory 207548 kb
Host smart-1d8b8cb9-8b76-4d6c-bcd3-49c42f7d7777
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867912063 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 470.usbdev_tx_rx_disruption.2867912063
Directory /workspace/470.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/471.usbdev_tx_rx_disruption.3272782618
Short name T206
Test name
Test status
Simulation time 585655095 ps
CPU time 1.64 seconds
Started Aug 11 07:18:38 PM PDT 24
Finished Aug 11 07:18:39 PM PDT 24
Peak memory 207528 kb
Host smart-20f434d9-f0b6-45be-be04-c20e0fad567c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272782618 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 471.usbdev_tx_rx_disruption.3272782618
Directory /workspace/471.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/472.usbdev_tx_rx_disruption.1550022754
Short name T934
Test name
Test status
Simulation time 597608614 ps
CPU time 1.57 seconds
Started Aug 11 07:18:03 PM PDT 24
Finished Aug 11 07:18:04 PM PDT 24
Peak memory 207572 kb
Host smart-fc1117c7-31bd-47b0-8062-1c03c50a4beb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550022754 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 472.usbdev_tx_rx_disruption.1550022754
Directory /workspace/472.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/473.usbdev_tx_rx_disruption.2858912091
Short name T3097
Test name
Test status
Simulation time 496047289 ps
CPU time 1.58 seconds
Started Aug 11 07:18:02 PM PDT 24
Finished Aug 11 07:18:04 PM PDT 24
Peak memory 207776 kb
Host smart-0353f408-e896-4bda-b2c6-f70faa82f018
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858912091 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 473.usbdev_tx_rx_disruption.2858912091
Directory /workspace/473.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/474.usbdev_tx_rx_disruption.2608557677
Short name T2470
Test name
Test status
Simulation time 542604394 ps
CPU time 1.66 seconds
Started Aug 11 07:18:03 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207504 kb
Host smart-dcb61492-295f-4a75-8918-e273da51acde
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608557677 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 474.usbdev_tx_rx_disruption.2608557677
Directory /workspace/474.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/475.usbdev_tx_rx_disruption.566036256
Short name T589
Test name
Test status
Simulation time 499943735 ps
CPU time 1.54 seconds
Started Aug 11 07:18:01 PM PDT 24
Finished Aug 11 07:18:03 PM PDT 24
Peak memory 207564 kb
Host smart-e4712d26-3f9b-4839-ba6d-b2ba33b5307f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566036256 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 475.usbdev_tx_rx_disruption.566036256
Directory /workspace/475.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/476.usbdev_tx_rx_disruption.3334197761
Short name T3581
Test name
Test status
Simulation time 633706335 ps
CPU time 1.68 seconds
Started Aug 11 07:18:12 PM PDT 24
Finished Aug 11 07:18:14 PM PDT 24
Peak memory 207548 kb
Host smart-6680d828-c55b-4774-acde-ded019b7c406
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334197761 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 476.usbdev_tx_rx_disruption.3334197761
Directory /workspace/476.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/477.usbdev_tx_rx_disruption.1943376408
Short name T3246
Test name
Test status
Simulation time 535778334 ps
CPU time 1.54 seconds
Started Aug 11 07:18:03 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207592 kb
Host smart-a6e9e1cb-7db6-4537-bf84-47e3b04d2e51
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943376408 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 477.usbdev_tx_rx_disruption.1943376408
Directory /workspace/477.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/478.usbdev_tx_rx_disruption.1120970808
Short name T2315
Test name
Test status
Simulation time 539090862 ps
CPU time 1.6 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:07 PM PDT 24
Peak memory 207520 kb
Host smart-80222e0d-cae7-489d-8105-95ad140ab05c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120970808 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 478.usbdev_tx_rx_disruption.1120970808
Directory /workspace/478.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/479.usbdev_tx_rx_disruption.3586922732
Short name T1913
Test name
Test status
Simulation time 541141950 ps
CPU time 1.72 seconds
Started Aug 11 07:18:05 PM PDT 24
Finished Aug 11 07:18:07 PM PDT 24
Peak memory 207480 kb
Host smart-5eb949c8-c7b5-4adc-a61c-a8c9387180ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586922732 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 479.usbdev_tx_rx_disruption.3586922732
Directory /workspace/479.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/48.usbdev_alert_test.3975946789
Short name T2040
Test name
Test status
Simulation time 47483609 ps
CPU time 0.67 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207620 kb
Host smart-59cda459-481b-438b-98ba-8c107b62e39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3975946789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3975946789
Directory /workspace/48.usbdev_alert_test/latest


Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3819293821
Short name T2490
Test name
Test status
Simulation time 10336607883 ps
CPU time 13.58 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:45 PM PDT 24
Peak memory 207780 kb
Host smart-8b33db67-77df-4db1-bb44-119b0e86a214
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819293821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.3819293821
Directory /workspace/48.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2124829390
Short name T2358
Test name
Test status
Simulation time 14531035281 ps
CPU time 17.59 seconds
Started Aug 11 07:16:28 PM PDT 24
Finished Aug 11 07:16:45 PM PDT 24
Peak memory 215956 kb
Host smart-516d9f0f-1321-449f-83f2-cb293b56cafe
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124829390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2124829390
Directory /workspace/48.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.2015679854
Short name T2493
Test name
Test status
Simulation time 30894884253 ps
CPU time 39.2 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:17:15 PM PDT 24
Peak memory 207856 kb
Host smart-923d9486-0a2a-4f8e-aab2-82ac13b37667
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015679854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.2015679854
Directory /workspace/48.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/48.usbdev_av_buffer.2945397466
Short name T2819
Test name
Test status
Simulation time 165716078 ps
CPU time 0.91 seconds
Started Aug 11 07:16:21 PM PDT 24
Finished Aug 11 07:16:22 PM PDT 24
Peak memory 207480 kb
Host smart-9b3833f5-4c52-43b5-b09b-db71ae77c0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29453
97466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2945397466
Directory /workspace/48.usbdev_av_buffer/latest


Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4118816802
Short name T84
Test name
Test status
Simulation time 159565500 ps
CPU time 0.85 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:16:38 PM PDT 24
Peak memory 207504 kb
Host smart-04e22a93-ef84-4681-ba5e-003656dca235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41188
16802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4118816802
Directory /workspace/48.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.760593770
Short name T1045
Test name
Test status
Simulation time 242694306 ps
CPU time 1.04 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:32 PM PDT 24
Peak memory 207544 kb
Host smart-4aa6a949-80e9-403d-921d-d26e07ac9e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76059
3770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.760593770
Directory /workspace/48.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1690923838
Short name T1764
Test name
Test status
Simulation time 1372540266 ps
CPU time 3.64 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:35 PM PDT 24
Peak memory 207668 kb
Host smart-6411a546-7fc1-4151-9cd7-7771cc2faa65
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1690923838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1690923838
Directory /workspace/48.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/48.usbdev_device_timeout.2355641866
Short name T3553
Test name
Test status
Simulation time 1067923671 ps
CPU time 8.87 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:49 PM PDT 24
Peak memory 207700 kb
Host smart-a9067966-6c81-457e-bcea-5b8ddb3be4bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355641866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.2355641866
Directory /workspace/48.usbdev_device_timeout/latest


Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2721281097
Short name T2751
Test name
Test status
Simulation time 783808452 ps
CPU time 1.8 seconds
Started Aug 11 07:16:42 PM PDT 24
Finished Aug 11 07:16:44 PM PDT 24
Peak memory 207468 kb
Host smart-44cb64b0-7821-47f1-b442-fbec1cc24166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27212
81097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2721281097
Directory /workspace/48.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/48.usbdev_disconnected.1341612870
Short name T1221
Test name
Test status
Simulation time 173564711 ps
CPU time 0.87 seconds
Started Aug 11 07:16:30 PM PDT 24
Finished Aug 11 07:16:31 PM PDT 24
Peak memory 207488 kb
Host smart-ee6de16b-b682-447a-b049-c15dc293731c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13416
12870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1341612870
Directory /workspace/48.usbdev_disconnected/latest


Test location /workspace/coverage/default/48.usbdev_enable.2810341938
Short name T877
Test name
Test status
Simulation time 42657522 ps
CPU time 0.71 seconds
Started Aug 11 07:16:27 PM PDT 24
Finished Aug 11 07:16:28 PM PDT 24
Peak memory 207476 kb
Host smart-c56d12ab-f9e7-4768-b07a-01aaabab9394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28103
41938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2810341938
Directory /workspace/48.usbdev_enable/latest


Test location /workspace/coverage/default/48.usbdev_endpoint_access.579982608
Short name T1223
Test name
Test status
Simulation time 690873202 ps
CPU time 2.08 seconds
Started Aug 11 07:16:13 PM PDT 24
Finished Aug 11 07:16:15 PM PDT 24
Peak memory 207744 kb
Host smart-f7b1bdfd-0830-41c0-9e7e-333489e92ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57998
2608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.579982608
Directory /workspace/48.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/48.usbdev_endpoint_types.1922277387
Short name T460
Test name
Test status
Simulation time 424903884 ps
CPU time 1.34 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:38 PM PDT 24
Peak memory 207520 kb
Host smart-8794994c-d587-48a1-b9f8-9c5c9bfe1a51
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1922277387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.1922277387
Directory /workspace/48.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/48.usbdev_fifo_rst.1088340264
Short name T2203
Test name
Test status
Simulation time 211373518 ps
CPU time 2.34 seconds
Started Aug 11 07:16:20 PM PDT 24
Finished Aug 11 07:16:22 PM PDT 24
Peak memory 207692 kb
Host smart-323a66c0-2fff-4588-81c0-997ffa3d8d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
40264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1088340264
Directory /workspace/48.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/48.usbdev_in_iso.736867285
Short name T2228
Test name
Test status
Simulation time 178704396 ps
CPU time 1.01 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:33 PM PDT 24
Peak memory 215796 kb
Host smart-7d613a5c-bd5b-4135-87e9-7fff7f7a01c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=736867285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.736867285
Directory /workspace/48.usbdev_in_iso/latest


Test location /workspace/coverage/default/48.usbdev_in_stall.4174791675
Short name T691
Test name
Test status
Simulation time 146347853 ps
CPU time 0.82 seconds
Started Aug 11 07:16:30 PM PDT 24
Finished Aug 11 07:16:31 PM PDT 24
Peak memory 207488 kb
Host smart-b748bb66-4625-47a0-a6ad-ec83545581a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41747
91675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.4174791675
Directory /workspace/48.usbdev_in_stall/latest


Test location /workspace/coverage/default/48.usbdev_in_trans.2213221067
Short name T1040
Test name
Test status
Simulation time 217607002 ps
CPU time 0.98 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:16:38 PM PDT 24
Peak memory 207496 kb
Host smart-53b0c6d6-4e86-4f43-af90-dc76708cb8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22132
21067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2213221067
Directory /workspace/48.usbdev_in_trans/latest


Test location /workspace/coverage/default/48.usbdev_invalid_sync.720691109
Short name T126
Test name
Test status
Simulation time 5247239746 ps
CPU time 40.95 seconds
Started Aug 11 07:16:19 PM PDT 24
Finished Aug 11 07:17:00 PM PDT 24
Peak memory 216152 kb
Host smart-f6b5be12-1e7c-4ead-8f2b-6e4fb2bc17c2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=720691109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.720691109
Directory /workspace/48.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/48.usbdev_iso_retraction.281792782
Short name T3183
Test name
Test status
Simulation time 8749252803 ps
CPU time 61.87 seconds
Started Aug 11 07:16:32 PM PDT 24
Finished Aug 11 07:17:34 PM PDT 24
Peak memory 207804 kb
Host smart-4ea3578e-b62c-4198-bb33-bbe6c85f1e15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=281792782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.281792782
Directory /workspace/48.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/48.usbdev_link_in_err.2909698488
Short name T1293
Test name
Test status
Simulation time 222439299 ps
CPU time 0.94 seconds
Started Aug 11 07:16:24 PM PDT 24
Finished Aug 11 07:16:26 PM PDT 24
Peak memory 207576 kb
Host smart-0be5aa90-5393-45ea-aad0-174ef443cd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096
98488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2909698488
Directory /workspace/48.usbdev_link_in_err/latest


Test location /workspace/coverage/default/48.usbdev_link_resume.4174587275
Short name T1009
Test name
Test status
Simulation time 25691832551 ps
CPU time 46.82 seconds
Started Aug 11 07:16:20 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 207808 kb
Host smart-cc2c744c-9253-43fa-9e01-362a3d300885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41745
87275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.4174587275
Directory /workspace/48.usbdev_link_resume/latest


Test location /workspace/coverage/default/48.usbdev_link_suspend.4276842800
Short name T2301
Test name
Test status
Simulation time 10471482423 ps
CPU time 15.92 seconds
Started Aug 11 07:16:28 PM PDT 24
Finished Aug 11 07:16:44 PM PDT 24
Peak memory 207808 kb
Host smart-8229f625-0edd-45ca-a602-cfab2fd0400d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42768
42800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.4276842800
Directory /workspace/48.usbdev_link_suspend/latest


Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2292034728
Short name T2054
Test name
Test status
Simulation time 3343466177 ps
CPU time 94.94 seconds
Started Aug 11 07:16:23 PM PDT 24
Finished Aug 11 07:17:59 PM PDT 24
Peak memory 215992 kb
Host smart-3490ad5f-c2f7-4eef-8ad6-7e27eb4d74e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2292034728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2292034728
Directory /workspace/48.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.1878279034
Short name T2368
Test name
Test status
Simulation time 3296905464 ps
CPU time 31.06 seconds
Started Aug 11 07:16:26 PM PDT 24
Finished Aug 11 07:16:57 PM PDT 24
Peak memory 217912 kb
Host smart-d88dfad1-076e-4fa4-a5e5-55dc6766b9ff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1878279034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.1878279034
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1579888950
Short name T2912
Test name
Test status
Simulation time 241062306 ps
CPU time 1.01 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:03 PM PDT 24
Peak memory 207516 kb
Host smart-eed0950a-8601-4596-82c8-46f4e8bdae9e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1579888950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1579888950
Directory /workspace/48.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3978427360
Short name T1952
Test name
Test status
Simulation time 253843868 ps
CPU time 1.06 seconds
Started Aug 11 07:16:30 PM PDT 24
Finished Aug 11 07:16:31 PM PDT 24
Peak memory 207572 kb
Host smart-6de98e94-cc26-430d-aad8-f7ae3065f0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39784
27360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3978427360
Directory /workspace/48.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.3024825416
Short name T1472
Test name
Test status
Simulation time 2281776770 ps
CPU time 66.39 seconds
Started Aug 11 07:16:30 PM PDT 24
Finished Aug 11 07:17:37 PM PDT 24
Peak memory 217216 kb
Host smart-e6163d1f-3a39-45bb-bcf4-243e20089925
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3024825416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3024825416
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1612262543
Short name T1705
Test name
Test status
Simulation time 149829247 ps
CPU time 0.87 seconds
Started Aug 11 07:16:29 PM PDT 24
Finished Aug 11 07:16:30 PM PDT 24
Peak memory 207744 kb
Host smart-09a4039e-68ca-40bc-b522-1139438f55b3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1612262543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1612262543
Directory /workspace/48.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2086866585
Short name T719
Test name
Test status
Simulation time 152547774 ps
CPU time 0.85 seconds
Started Aug 11 07:16:30 PM PDT 24
Finished Aug 11 07:16:31 PM PDT 24
Peak memory 207572 kb
Host smart-1e10c157-c34e-4a21-af34-6635192fc57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20868
66585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2086866585
Directory /workspace/48.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_out_iso.3677505074
Short name T3173
Test name
Test status
Simulation time 144367720 ps
CPU time 0.81 seconds
Started Aug 11 07:16:17 PM PDT 24
Finished Aug 11 07:16:18 PM PDT 24
Peak memory 207596 kb
Host smart-ffccb5e8-f2fb-434d-a200-67a2851f1542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36775
05074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3677505074
Directory /workspace/48.usbdev_out_iso/latest


Test location /workspace/coverage/default/48.usbdev_out_stall.983970712
Short name T2786
Test name
Test status
Simulation time 184018934 ps
CPU time 0.88 seconds
Started Aug 11 07:16:22 PM PDT 24
Finished Aug 11 07:16:23 PM PDT 24
Peak memory 207464 kb
Host smart-1e90ed59-a23a-4923-94a2-02854e1dfb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98397
0712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.983970712
Directory /workspace/48.usbdev_out_stall/latest


Test location /workspace/coverage/default/48.usbdev_out_trans_nak.4293377180
Short name T939
Test name
Test status
Simulation time 279796341 ps
CPU time 1.07 seconds
Started Aug 11 07:16:32 PM PDT 24
Finished Aug 11 07:16:33 PM PDT 24
Peak memory 207568 kb
Host smart-3adbf9d4-6184-4d13-9499-869b0cf561a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42933
77180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.4293377180
Directory /workspace/48.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3000502078
Short name T3509
Test name
Test status
Simulation time 172528327 ps
CPU time 0.88 seconds
Started Aug 11 07:16:20 PM PDT 24
Finished Aug 11 07:16:21 PM PDT 24
Peak memory 207504 kb
Host smart-e52f59d9-b2fa-442c-a60c-08cd4efffcff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30005
02078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3000502078
Directory /workspace/48.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1973479324
Short name T29
Test name
Test status
Simulation time 263584335 ps
CPU time 1.01 seconds
Started Aug 11 07:16:20 PM PDT 24
Finished Aug 11 07:16:26 PM PDT 24
Peak memory 207516 kb
Host smart-f31024fa-bc42-43ea-880c-a679eaf0b8bb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1973479324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1973479324
Directory /workspace/48.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2044776405
Short name T2248
Test name
Test status
Simulation time 171083271 ps
CPU time 0.88 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207552 kb
Host smart-9349a53e-1bec-4da2-a039-4324df43812e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20447
76405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2044776405
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2798340611
Short name T2699
Test name
Test status
Simulation time 49760386 ps
CPU time 0.74 seconds
Started Aug 11 07:16:28 PM PDT 24
Finished Aug 11 07:16:29 PM PDT 24
Peak memory 207492 kb
Host smart-65503b2f-a45f-417e-906b-60948e549372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27983
40611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2798340611
Directory /workspace/48.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/48.usbdev_pkt_buffer.905504607
Short name T2836
Test name
Test status
Simulation time 18170346782 ps
CPU time 44.89 seconds
Started Aug 11 07:16:27 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 216004 kb
Host smart-981f7e8f-e639-43b3-babd-0503d41016ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90550
4607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.905504607
Directory /workspace/48.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/48.usbdev_pkt_received.1302233163
Short name T2202
Test name
Test status
Simulation time 181878262 ps
CPU time 0.91 seconds
Started Aug 11 07:16:32 PM PDT 24
Finished Aug 11 07:16:33 PM PDT 24
Peak memory 207552 kb
Host smart-8330489d-3d8e-41d0-8b44-07fbf83b7da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13022
33163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1302233163
Directory /workspace/48.usbdev_pkt_received/latest


Test location /workspace/coverage/default/48.usbdev_pkt_sent.2605001851
Short name T1667
Test name
Test status
Simulation time 239570409 ps
CPU time 1 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:16:36 PM PDT 24
Peak memory 207488 kb
Host smart-21f1114a-9138-493c-8f90-f198ee25765e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26050
01851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2605001851
Directory /workspace/48.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1925723926
Short name T2586
Test name
Test status
Simulation time 169604786 ps
CPU time 0.84 seconds
Started Aug 11 07:16:44 PM PDT 24
Finished Aug 11 07:16:45 PM PDT 24
Peak memory 207572 kb
Host smart-e653e292-f429-479c-99fd-e459acfdd84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19257
23926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1925723926
Directory /workspace/48.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1041316585
Short name T1964
Test name
Test status
Simulation time 195461213 ps
CPU time 0.94 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207752 kb
Host smart-c4010eb4-9015-4669-85ed-b1874a3d4906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10413
16585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1041316585
Directory /workspace/48.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1157959028
Short name T1744
Test name
Test status
Simulation time 184058912 ps
CPU time 0.91 seconds
Started Aug 11 07:16:23 PM PDT 24
Finished Aug 11 07:16:25 PM PDT 24
Peak memory 207548 kb
Host smart-6e05f039-73eb-41f4-bc34-65c8082c9286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11579
59028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1157959028
Directory /workspace/48.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/48.usbdev_rx_full.2687377520
Short name T341
Test name
Test status
Simulation time 254635610 ps
CPU time 1.17 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 207544 kb
Host smart-0b79ffa9-d42c-4d3c-b9d1-d57448ebc25d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26873
77520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.2687377520
Directory /workspace/48.usbdev_rx_full/latest


Test location /workspace/coverage/default/48.usbdev_setup_stage.85016022
Short name T1957
Test name
Test status
Simulation time 198529712 ps
CPU time 0.87 seconds
Started Aug 11 07:16:21 PM PDT 24
Finished Aug 11 07:16:22 PM PDT 24
Peak memory 207524 kb
Host smart-8a05ea77-2a9f-44d5-91e6-95f23ae6abc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85016
022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.85016022
Directory /workspace/48.usbdev_setup_stage/latest


Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2798286901
Short name T3117
Test name
Test status
Simulation time 149383757 ps
CPU time 0.79 seconds
Started Aug 11 07:16:41 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 207568 kb
Host smart-99d82221-8140-4aaa-bdf4-7da0af8ca7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27982
86901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2798286901
Directory /workspace/48.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/48.usbdev_smoke.3358591266
Short name T1826
Test name
Test status
Simulation time 212016184 ps
CPU time 0.99 seconds
Started Aug 11 07:16:45 PM PDT 24
Finished Aug 11 07:16:46 PM PDT 24
Peak memory 207452 kb
Host smart-9e7bdf7a-580c-4993-8d3a-6ef9cb9342e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33585
91266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3358591266
Directory /workspace/48.usbdev_smoke/latest


Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.4114359589
Short name T2841
Test name
Test status
Simulation time 3312237265 ps
CPU time 89.72 seconds
Started Aug 11 07:16:42 PM PDT 24
Finished Aug 11 07:18:12 PM PDT 24
Peak memory 224268 kb
Host smart-959866a5-e545-4eb8-a6e3-126dc80e3c0d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4114359589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.4114359589
Directory /workspace/48.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3263578135
Short name T548
Test name
Test status
Simulation time 171636135 ps
CPU time 0.86 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207524 kb
Host smart-b065a802-8cdb-4c22-a04e-56b266e44b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32635
78135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3263578135
Directory /workspace/48.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/48.usbdev_stall_trans.3520993758
Short name T807
Test name
Test status
Simulation time 164734409 ps
CPU time 0.89 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207512 kb
Host smart-9a176aaf-e3fa-4cf4-9818-2067fc861957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35209
93758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3520993758
Directory /workspace/48.usbdev_stall_trans/latest


Test location /workspace/coverage/default/48.usbdev_stream_len_max.292894435
Short name T1308
Test name
Test status
Simulation time 200517947 ps
CPU time 0.94 seconds
Started Aug 11 07:16:28 PM PDT 24
Finished Aug 11 07:16:29 PM PDT 24
Peak memory 207480 kb
Host smart-531307e6-2b2f-4f89-a766-49a3645eaa68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29289
4435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.292894435
Directory /workspace/48.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/48.usbdev_streaming_out.306859462
Short name T1372
Test name
Test status
Simulation time 2326190241 ps
CPU time 65.37 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:17:36 PM PDT 24
Peak memory 216120 kb
Host smart-6cbff388-61a1-440c-a6a7-36907d17f455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30685
9462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.306859462
Directory /workspace/48.usbdev_streaming_out/latest


Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.2581177177
Short name T1329
Test name
Test status
Simulation time 1089005278 ps
CPU time 22.57 seconds
Started Aug 11 07:16:18 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207708 kb
Host smart-0ec1caf4-4ae0-43ce-b321-909568a0c244
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581177177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.2581177177
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/48.usbdev_tx_rx_disruption.3080542940
Short name T2035
Test name
Test status
Simulation time 485998552 ps
CPU time 1.53 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207532 kb
Host smart-2e7940a9-be2d-4aee-93ca-7d6d00c7b77f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080542940 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.usbdev_tx_rx_disruption.3080542940
Directory /workspace/48.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/480.usbdev_tx_rx_disruption.4095815964
Short name T2377
Test name
Test status
Simulation time 577812465 ps
CPU time 1.52 seconds
Started Aug 11 07:18:10 PM PDT 24
Finished Aug 11 07:18:12 PM PDT 24
Peak memory 207540 kb
Host smart-4ea64b9d-f15f-4d06-86f1-be6f7341b5f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095815964 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 480.usbdev_tx_rx_disruption.4095815964
Directory /workspace/480.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/481.usbdev_tx_rx_disruption.1405418074
Short name T1619
Test name
Test status
Simulation time 571668481 ps
CPU time 1.74 seconds
Started Aug 11 07:18:20 PM PDT 24
Finished Aug 11 07:18:22 PM PDT 24
Peak memory 207600 kb
Host smart-47a853a6-6cc4-46fc-9fcc-192406343a1e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405418074 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 481.usbdev_tx_rx_disruption.1405418074
Directory /workspace/481.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/483.usbdev_tx_rx_disruption.326954735
Short name T1866
Test name
Test status
Simulation time 487394726 ps
CPU time 1.54 seconds
Started Aug 11 07:18:14 PM PDT 24
Finished Aug 11 07:18:16 PM PDT 24
Peak memory 207584 kb
Host smart-125cb999-5f49-4321-b73d-97cfbf4a4bf6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326954735 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 483.usbdev_tx_rx_disruption.326954735
Directory /workspace/483.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/484.usbdev_tx_rx_disruption.2597858464
Short name T2654
Test name
Test status
Simulation time 518067689 ps
CPU time 1.48 seconds
Started Aug 11 07:17:59 PM PDT 24
Finished Aug 11 07:18:01 PM PDT 24
Peak memory 207528 kb
Host smart-c0b353fe-ce75-4e1c-b4ed-fb28e4f56054
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597858464 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 484.usbdev_tx_rx_disruption.2597858464
Directory /workspace/484.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/485.usbdev_tx_rx_disruption.186888016
Short name T1816
Test name
Test status
Simulation time 463806569 ps
CPU time 1.35 seconds
Started Aug 11 07:17:59 PM PDT 24
Finished Aug 11 07:18:01 PM PDT 24
Peak memory 207524 kb
Host smart-0438c146-8c00-444e-a613-1e5addec1dea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186888016 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 485.usbdev_tx_rx_disruption.186888016
Directory /workspace/485.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/486.usbdev_tx_rx_disruption.363146689
Short name T2544
Test name
Test status
Simulation time 525888459 ps
CPU time 1.71 seconds
Started Aug 11 07:18:15 PM PDT 24
Finished Aug 11 07:18:17 PM PDT 24
Peak memory 207536 kb
Host smart-9be59fbd-16f5-4273-aea4-18b7b14ba44e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363146689 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 486.usbdev_tx_rx_disruption.363146689
Directory /workspace/486.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/487.usbdev_tx_rx_disruption.2070252021
Short name T1477
Test name
Test status
Simulation time 512221049 ps
CPU time 1.51 seconds
Started Aug 11 07:18:07 PM PDT 24
Finished Aug 11 07:18:09 PM PDT 24
Peak memory 207596 kb
Host smart-10709276-570a-42f3-83b9-430ced14fa86
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070252021 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 487.usbdev_tx_rx_disruption.2070252021
Directory /workspace/487.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/488.usbdev_tx_rx_disruption.1156953178
Short name T76
Test name
Test status
Simulation time 599396574 ps
CPU time 1.67 seconds
Started Aug 11 07:18:14 PM PDT 24
Finished Aug 11 07:18:15 PM PDT 24
Peak memory 207536 kb
Host smart-2534f254-c3c2-47f1-9fb3-5b9b6a6fc130
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156953178 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 488.usbdev_tx_rx_disruption.1156953178
Directory /workspace/488.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/489.usbdev_tx_rx_disruption.1810676885
Short name T2093
Test name
Test status
Simulation time 606197481 ps
CPU time 1.67 seconds
Started Aug 11 07:18:02 PM PDT 24
Finished Aug 11 07:18:03 PM PDT 24
Peak memory 207568 kb
Host smart-c680a325-01b1-46d9-90a2-98ff7ac506e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810676885 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 489.usbdev_tx_rx_disruption.1810676885
Directory /workspace/489.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/49.usbdev_alert_test.1793482459
Short name T991
Test name
Test status
Simulation time 40188943 ps
CPU time 0.71 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207592 kb
Host smart-e7e4f1ae-af08-4d43-99cd-459e8853f6cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1793482459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1793482459
Directory /workspace/49.usbdev_alert_test/latest


Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.352326046
Short name T3490
Test name
Test status
Simulation time 4808295649 ps
CPU time 6.3 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 216012 kb
Host smart-815e4829-827a-4dcd-9f97-3056b465abd8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352326046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ao
n_wake_disconnect.352326046
Directory /workspace/49.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2343450568
Short name T266
Test name
Test status
Simulation time 14732109567 ps
CPU time 16.49 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:47 PM PDT 24
Peak memory 216032 kb
Host smart-be225b85-5d1c-4df9-b91a-2303ebf3b2fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343450568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2343450568
Directory /workspace/49.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3404038234
Short name T13
Test name
Test status
Simulation time 23930302643 ps
CPU time 29.82 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 215992 kb
Host smart-9cd0f919-d013-4922-91f2-4c1afb36058f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404038234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.3404038234
Directory /workspace/49.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/49.usbdev_av_buffer.866436611
Short name T2913
Test name
Test status
Simulation time 161791333 ps
CPU time 0.83 seconds
Started Aug 11 07:16:47 PM PDT 24
Finished Aug 11 07:16:48 PM PDT 24
Peak memory 207540 kb
Host smart-9f6d9a53-bb91-4db7-87c8-73d3fc19110b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86643
6611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.866436611
Directory /workspace/49.usbdev_av_buffer/latest


Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1884421834
Short name T1490
Test name
Test status
Simulation time 165832856 ps
CPU time 0.87 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:16:36 PM PDT 24
Peak memory 207448 kb
Host smart-1a973936-565c-4843-aed4-519b19697c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18844
21834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1884421834
Directory /workspace/49.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.748968393
Short name T3310
Test name
Test status
Simulation time 440856719 ps
CPU time 1.48 seconds
Started Aug 11 07:16:21 PM PDT 24
Finished Aug 11 07:16:23 PM PDT 24
Peak memory 207484 kb
Host smart-d7735f71-c50d-4921-af29-6bd791a4b89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74896
8393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.748968393
Directory /workspace/49.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3734669281
Short name T102
Test name
Test status
Simulation time 1131854361 ps
CPU time 3.17 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207752 kb
Host smart-f0f711b3-ff13-46fc-a13c-c7d15197fecb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3734669281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3734669281
Directory /workspace/49.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/49.usbdev_device_address.1193078181
Short name T3546
Test name
Test status
Simulation time 29023817993 ps
CPU time 49.46 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:17:26 PM PDT 24
Peak memory 207876 kb
Host smart-b58c430a-6747-44e3-9b7d-c869c318e314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11930
78181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1193078181
Directory /workspace/49.usbdev_device_address/latest


Test location /workspace/coverage/default/49.usbdev_device_timeout.4273517544
Short name T2294
Test name
Test status
Simulation time 753348518 ps
CPU time 15.27 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:16:53 PM PDT 24
Peak memory 207704 kb
Host smart-d5a0a2bf-90b9-42b3-b2ea-9fdce314f43c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273517544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.4273517544
Directory /workspace/49.usbdev_device_timeout/latest


Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1392705618
Short name T2240
Test name
Test status
Simulation time 832856955 ps
CPU time 2.01 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:34 PM PDT 24
Peak memory 207420 kb
Host smart-bed9b8b7-ef70-41f5-b88f-275eda8b1c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13927
05618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1392705618
Directory /workspace/49.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/49.usbdev_disconnected.2133218394
Short name T1183
Test name
Test status
Simulation time 147268453 ps
CPU time 0.85 seconds
Started Aug 11 07:16:42 PM PDT 24
Finished Aug 11 07:16:43 PM PDT 24
Peak memory 207528 kb
Host smart-4b84ec11-6073-4480-8f23-84f5dfec5ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21332
18394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2133218394
Directory /workspace/49.usbdev_disconnected/latest


Test location /workspace/coverage/default/49.usbdev_enable.3214614183
Short name T3535
Test name
Test status
Simulation time 55944448 ps
CPU time 0.74 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207540 kb
Host smart-3cb1518b-6313-4e90-b7cd-f6d757938c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146
14183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3214614183
Directory /workspace/49.usbdev_enable/latest


Test location /workspace/coverage/default/49.usbdev_endpoint_access.3508124077
Short name T3161
Test name
Test status
Simulation time 1103148887 ps
CPU time 2.73 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207768 kb
Host smart-d39784e9-7cd1-4f87-ae06-5bb23450af2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35081
24077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3508124077
Directory /workspace/49.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/49.usbdev_endpoint_types.868116025
Short name T419
Test name
Test status
Simulation time 297581343 ps
CPU time 1.16 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 207548 kb
Host smart-ead331d8-8a8f-4743-bca3-4984979b7395
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=868116025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.868116025
Directory /workspace/49.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/49.usbdev_fifo_rst.3862801386
Short name T783
Test name
Test status
Simulation time 391821953 ps
CPU time 2.76 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207644 kb
Host smart-4efaafbf-0563-4cd7-9c4b-d24199e8d769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38628
01386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3862801386
Directory /workspace/49.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/49.usbdev_in_iso.568586343
Short name T2010
Test name
Test status
Simulation time 251841659 ps
CPU time 1.18 seconds
Started Aug 11 07:16:33 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 215928 kb
Host smart-6acace48-2f8e-4945-a0b5-2752ac3e8e81
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=568586343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.568586343
Directory /workspace/49.usbdev_in_iso/latest


Test location /workspace/coverage/default/49.usbdev_in_stall.711713373
Short name T835
Test name
Test status
Simulation time 148321992 ps
CPU time 0.84 seconds
Started Aug 11 07:16:22 PM PDT 24
Finished Aug 11 07:16:23 PM PDT 24
Peak memory 207520 kb
Host smart-dffc2cb3-c6f0-4471-8ad0-5e77a99bec2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71171
3373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.711713373
Directory /workspace/49.usbdev_in_stall/latest


Test location /workspace/coverage/default/49.usbdev_in_trans.80730304
Short name T3360
Test name
Test status
Simulation time 223009832 ps
CPU time 0.93 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207568 kb
Host smart-62558e03-090f-4a72-8bcc-b76c0166c0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80730
304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.80730304
Directory /workspace/49.usbdev_in_trans/latest


Test location /workspace/coverage/default/49.usbdev_invalid_sync.4070801588
Short name T1873
Test name
Test status
Simulation time 2927717919 ps
CPU time 28.64 seconds
Started Aug 11 07:16:33 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 224260 kb
Host smart-7f939091-a2bf-4361-8120-f928a57f2c07
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4070801588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.4070801588
Directory /workspace/49.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/49.usbdev_iso_retraction.257823363
Short name T1569
Test name
Test status
Simulation time 6324965762 ps
CPU time 46.06 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:17:21 PM PDT 24
Peak memory 207804 kb
Host smart-df8913cc-9b3d-4ec7-834d-52ae55c0cb69
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=257823363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.257823363
Directory /workspace/49.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/49.usbdev_link_in_err.1809057242
Short name T810
Test name
Test status
Simulation time 255477287 ps
CPU time 1 seconds
Started Aug 11 07:16:42 PM PDT 24
Finished Aug 11 07:16:43 PM PDT 24
Peak memory 207540 kb
Host smart-d8cd070c-5f64-42dc-87a5-54e528597f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18090
57242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1809057242
Directory /workspace/49.usbdev_link_in_err/latest


Test location /workspace/coverage/default/49.usbdev_link_resume.1716530789
Short name T3265
Test name
Test status
Simulation time 30723317415 ps
CPU time 53.78 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:17:32 PM PDT 24
Peak memory 207892 kb
Host smart-4fece709-3e59-483c-a138-418d965ad83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17165
30789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1716530789
Directory /workspace/49.usbdev_link_resume/latest


Test location /workspace/coverage/default/49.usbdev_link_suspend.1812109814
Short name T820
Test name
Test status
Simulation time 3637750423 ps
CPU time 5.45 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:16:43 PM PDT 24
Peak memory 216792 kb
Host smart-a664ffb7-1e65-4a2a-a61e-9392ec8011b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18121
09814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1812109814
Directory /workspace/49.usbdev_link_suspend/latest


Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.3135238553
Short name T2854
Test name
Test status
Simulation time 4105704239 ps
CPU time 34.68 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 216124 kb
Host smart-8cb5730d-d829-4972-a555-205c2f9283c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3135238553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3135238553
Directory /workspace/49.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.2890645088
Short name T3526
Test name
Test status
Simulation time 2919224815 ps
CPU time 86.95 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:17:58 PM PDT 24
Peak memory 217344 kb
Host smart-392fc622-6b53-4d8e-abb3-6e2b2d85f821
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2890645088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.2890645088
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.935378197
Short name T2339
Test name
Test status
Simulation time 249912140 ps
CPU time 0.99 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207596 kb
Host smart-689e718b-a218-4d2c-9763-6129a4dd6cf9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=935378197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.935378197
Directory /workspace/49.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.28832733
Short name T983
Test name
Test status
Simulation time 199503254 ps
CPU time 1.02 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207596 kb
Host smart-6fd71c60-f7fa-4934-b01a-d04316fdb32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28832
733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.28832733
Directory /workspace/49.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.1713823246
Short name T1382
Test name
Test status
Simulation time 2979473125 ps
CPU time 85.12 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:18:04 PM PDT 24
Peak memory 216064 kb
Host smart-f32a2284-8589-4f83-accd-4a3aa0cc6016
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1713823246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1713823246
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.843041236
Short name T984
Test name
Test status
Simulation time 201449979 ps
CPU time 0.92 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:16:36 PM PDT 24
Peak memory 207524 kb
Host smart-00076820-3513-47f0-b893-d19159607c3c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=843041236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.843041236
Directory /workspace/49.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1262367079
Short name T2186
Test name
Test status
Simulation time 172882986 ps
CPU time 0.87 seconds
Started Aug 11 07:16:21 PM PDT 24
Finished Aug 11 07:16:22 PM PDT 24
Peak memory 207572 kb
Host smart-27f00542-3151-4daf-9e2e-22aeb4e8feec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
67079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1262367079
Directory /workspace/49.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_nak_trans.32357891
Short name T140
Test name
Test status
Simulation time 227347873 ps
CPU time 0.98 seconds
Started Aug 11 07:16:44 PM PDT 24
Finished Aug 11 07:16:45 PM PDT 24
Peak memory 207576 kb
Host smart-f28f6814-4a0f-40b7-b09f-fb75cbbf6bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32357
891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.32357891
Directory /workspace/49.usbdev_nak_trans/latest


Test location /workspace/coverage/default/49.usbdev_out_iso.322365207
Short name T2057
Test name
Test status
Simulation time 188363848 ps
CPU time 0.91 seconds
Started Aug 11 07:16:32 PM PDT 24
Finished Aug 11 07:16:33 PM PDT 24
Peak memory 207508 kb
Host smart-bbbfb67c-00db-4cfe-80cc-65e2d7cf1ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32236
5207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.322365207
Directory /workspace/49.usbdev_out_iso/latest


Test location /workspace/coverage/default/49.usbdev_out_stall.2125001052
Short name T2329
Test name
Test status
Simulation time 162722090 ps
CPU time 0.88 seconds
Started Aug 11 07:16:33 PM PDT 24
Finished Aug 11 07:16:34 PM PDT 24
Peak memory 207552 kb
Host smart-4f8b389c-a18f-4b27-aae8-d16e3226a4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21250
01052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2125001052
Directory /workspace/49.usbdev_out_stall/latest


Test location /workspace/coverage/default/49.usbdev_out_trans_nak.4196511994
Short name T2838
Test name
Test status
Simulation time 225739753 ps
CPU time 0.91 seconds
Started Aug 11 07:16:28 PM PDT 24
Finished Aug 11 07:16:29 PM PDT 24
Peak memory 207484 kb
Host smart-aba2f09c-312f-4d1b-8ab4-48ec20e9a888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41965
11994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.4196511994
Directory /workspace/49.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2741388448
Short name T1018
Test name
Test status
Simulation time 153217640 ps
CPU time 0.9 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:37 PM PDT 24
Peak memory 207488 kb
Host smart-d4d36047-4cf8-4080-8f12-6c9c05e64e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27413
88448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2741388448
Directory /workspace/49.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1509210336
Short name T3137
Test name
Test status
Simulation time 223336871 ps
CPU time 1.03 seconds
Started Aug 11 07:16:27 PM PDT 24
Finished Aug 11 07:16:28 PM PDT 24
Peak memory 207452 kb
Host smart-f3aece14-7e18-44e5-86a0-e1fa7808e542
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1509210336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1509210336
Directory /workspace/49.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2283217337
Short name T1522
Test name
Test status
Simulation time 170659891 ps
CPU time 0.91 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207464 kb
Host smart-d5b04201-3a2e-4d74-a4f3-c5f1f1dbb686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22832
17337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2283217337
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2390035323
Short name T3300
Test name
Test status
Simulation time 57922289 ps
CPU time 0.73 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207552 kb
Host smart-86e55b23-a4f8-4f3a-886a-9961783c387c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23900
35323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2390035323
Directory /workspace/49.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2650034966
Short name T326
Test name
Test status
Simulation time 10915571491 ps
CPU time 27.43 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 216004 kb
Host smart-7f82889a-eff9-404e-9473-5f7d6d461b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26500
34966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2650034966
Directory /workspace/49.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/49.usbdev_pkt_received.906748861
Short name T3068
Test name
Test status
Simulation time 173911480 ps
CPU time 0.91 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:16:38 PM PDT 24
Peak memory 207508 kb
Host smart-a764655d-fd9e-4617-acde-d8b3008fb81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90674
8861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.906748861
Directory /workspace/49.usbdev_pkt_received/latest


Test location /workspace/coverage/default/49.usbdev_pkt_sent.281586877
Short name T1717
Test name
Test status
Simulation time 149500073 ps
CPU time 0.89 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207544 kb
Host smart-7d1cf165-7ac4-4361-82f3-c0a447eecc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28158
6877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.281586877
Directory /workspace/49.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3606030563
Short name T1361
Test name
Test status
Simulation time 237831875 ps
CPU time 1.01 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:33 PM PDT 24
Peak memory 207576 kb
Host smart-5417bed6-5b05-48c1-a898-a839058cbcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36060
30563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3606030563
Directory /workspace/49.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.720304541
Short name T3250
Test name
Test status
Simulation time 150976446 ps
CPU time 0.81 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:36 PM PDT 24
Peak memory 207572 kb
Host smart-271bce8c-6868-4f72-a655-1f5801acdf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72030
4541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.720304541
Directory /workspace/49.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3363661957
Short name T1148
Test name
Test status
Simulation time 160117326 ps
CPU time 0.87 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207548 kb
Host smart-3964af0b-a8c5-4275-9b82-ff322dfbcdf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33636
61957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3363661957
Directory /workspace/49.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/49.usbdev_rx_full.979391728
Short name T346
Test name
Test status
Simulation time 326888448 ps
CPU time 1.16 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 207576 kb
Host smart-a3086470-71d6-4e68-8e49-17cb96117d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97939
1728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.979391728
Directory /workspace/49.usbdev_rx_full/latest


Test location /workspace/coverage/default/49.usbdev_setup_stage.3768178593
Short name T3372
Test name
Test status
Simulation time 219180795 ps
CPU time 0.91 seconds
Started Aug 11 07:16:29 PM PDT 24
Finished Aug 11 07:16:30 PM PDT 24
Peak memory 207528 kb
Host smart-c1384a5f-37d7-4f72-9059-e3c63410f814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37681
78593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3768178593
Directory /workspace/49.usbdev_setup_stage/latest


Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1699304386
Short name T2547
Test name
Test status
Simulation time 157977174 ps
CPU time 0.85 seconds
Started Aug 11 07:16:47 PM PDT 24
Finished Aug 11 07:16:48 PM PDT 24
Peak memory 207556 kb
Host smart-2a4422cd-1760-4999-8e52-6cfd33671ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16993
04386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1699304386
Directory /workspace/49.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/49.usbdev_smoke.3271851759
Short name T2085
Test name
Test status
Simulation time 235106592 ps
CPU time 1.06 seconds
Started Aug 11 07:16:52 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207548 kb
Host smart-6b6bb03b-c239-490b-b783-2ea5c0682806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32718
51759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3271851759
Directory /workspace/49.usbdev_smoke/latest


Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3167109592
Short name T3623
Test name
Test status
Simulation time 1868347055 ps
CPU time 52.57 seconds
Started Aug 11 07:16:35 PM PDT 24
Finished Aug 11 07:17:28 PM PDT 24
Peak memory 217548 kb
Host smart-bc37ecc7-48bb-4d97-a2c7-1b89fb4a098a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3167109592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3167109592
Directory /workspace/49.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.613764505
Short name T1035
Test name
Test status
Simulation time 156340041 ps
CPU time 0.88 seconds
Started Aug 11 07:16:26 PM PDT 24
Finished Aug 11 07:16:28 PM PDT 24
Peak memory 207544 kb
Host smart-294d47dd-d578-4960-bb4d-7b8a8b43fc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61376
4505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.613764505
Directory /workspace/49.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/49.usbdev_stall_trans.857325568
Short name T2181
Test name
Test status
Simulation time 182159144 ps
CPU time 0.89 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207612 kb
Host smart-d26c0d21-5985-43ac-a1f7-b46c471abdc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85732
5568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.857325568
Directory /workspace/49.usbdev_stall_trans/latest


Test location /workspace/coverage/default/49.usbdev_stream_len_max.2365517082
Short name T3319
Test name
Test status
Simulation time 641086822 ps
CPU time 1.76 seconds
Started Aug 11 07:16:32 PM PDT 24
Finished Aug 11 07:16:34 PM PDT 24
Peak memory 207472 kb
Host smart-b92305f5-b218-4d5f-a806-bfd0d98d86b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23655
17082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2365517082
Directory /workspace/49.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/49.usbdev_streaming_out.2675788123
Short name T1078
Test name
Test status
Simulation time 2164262065 ps
CPU time 16.36 seconds
Started Aug 11 07:16:34 PM PDT 24
Finished Aug 11 07:16:51 PM PDT 24
Peak memory 207900 kb
Host smart-dd9dd795-88f9-4f8d-b089-cdb12064488c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26757
88123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2675788123
Directory /workspace/49.usbdev_streaming_out/latest


Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.174372523
Short name T1126
Test name
Test status
Simulation time 998431830 ps
CPU time 22.55 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207732 kb
Host smart-9db5fc76-e22d-430f-abfc-0343736d050e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174372523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_host
_handshake.174372523
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/49.usbdev_tx_rx_disruption.321571665
Short name T3003
Test name
Test status
Simulation time 452392051 ps
CPU time 1.41 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207524 kb
Host smart-f9b0eba4-97ea-441d-9a82-9c081142981e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321571665 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.usbdev_tx_rx_disruption.321571665
Directory /workspace/49.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/490.usbdev_tx_rx_disruption.2616825347
Short name T1444
Test name
Test status
Simulation time 483552056 ps
CPU time 1.54 seconds
Started Aug 11 07:18:04 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207556 kb
Host smart-719a48ec-a7e4-4bfe-886e-b9aaaf69989b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616825347 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 490.usbdev_tx_rx_disruption.2616825347
Directory /workspace/490.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/491.usbdev_tx_rx_disruption.3221136836
Short name T3180
Test name
Test status
Simulation time 524038966 ps
CPU time 1.56 seconds
Started Aug 11 07:18:13 PM PDT 24
Finished Aug 11 07:18:15 PM PDT 24
Peak memory 207540 kb
Host smart-b81a9157-b806-475d-91e8-d3f581b4ad8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221136836 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 491.usbdev_tx_rx_disruption.3221136836
Directory /workspace/491.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/492.usbdev_tx_rx_disruption.3437511020
Short name T3575
Test name
Test status
Simulation time 571691251 ps
CPU time 1.76 seconds
Started Aug 11 07:18:13 PM PDT 24
Finished Aug 11 07:18:15 PM PDT 24
Peak memory 207580 kb
Host smart-378d62d9-235e-4e59-b46d-ac48809d95bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437511020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 492.usbdev_tx_rx_disruption.3437511020
Directory /workspace/492.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/493.usbdev_tx_rx_disruption.3742800992
Short name T3304
Test name
Test status
Simulation time 490671651 ps
CPU time 1.54 seconds
Started Aug 11 07:18:00 PM PDT 24
Finished Aug 11 07:18:01 PM PDT 24
Peak memory 207600 kb
Host smart-42a5b384-15ff-435f-9977-9a63736b0c5b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742800992 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 493.usbdev_tx_rx_disruption.3742800992
Directory /workspace/493.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/494.usbdev_tx_rx_disruption.3206582456
Short name T1517
Test name
Test status
Simulation time 562752362 ps
CPU time 1.6 seconds
Started Aug 11 07:18:04 PM PDT 24
Finished Aug 11 07:18:05 PM PDT 24
Peak memory 207544 kb
Host smart-d7503311-1bb5-4aa6-afca-37d8c2a1147d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206582456 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 494.usbdev_tx_rx_disruption.3206582456
Directory /workspace/494.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/495.usbdev_tx_rx_disruption.3960926337
Short name T3489
Test name
Test status
Simulation time 521403958 ps
CPU time 1.52 seconds
Started Aug 11 07:18:04 PM PDT 24
Finished Aug 11 07:18:06 PM PDT 24
Peak memory 207580 kb
Host smart-686b8d8e-97b7-49ea-a221-e2a07d2739a4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960926337 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 495.usbdev_tx_rx_disruption.3960926337
Directory /workspace/495.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/496.usbdev_tx_rx_disruption.988084325
Short name T665
Test name
Test status
Simulation time 510785434 ps
CPU time 1.53 seconds
Started Aug 11 07:18:15 PM PDT 24
Finished Aug 11 07:18:17 PM PDT 24
Peak memory 207608 kb
Host smart-8cfaa0f0-8577-45eb-9494-f5b91b9b6570
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988084325 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 496.usbdev_tx_rx_disruption.988084325
Directory /workspace/496.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/497.usbdev_tx_rx_disruption.4176746726
Short name T811
Test name
Test status
Simulation time 539871459 ps
CPU time 1.69 seconds
Started Aug 11 07:18:13 PM PDT 24
Finished Aug 11 07:18:15 PM PDT 24
Peak memory 207516 kb
Host smart-2a094b62-5ee1-45d7-9501-7ec0341642ce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176746726 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 497.usbdev_tx_rx_disruption.4176746726
Directory /workspace/497.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/498.usbdev_tx_rx_disruption.3408138573
Short name T2410
Test name
Test status
Simulation time 642017690 ps
CPU time 1.83 seconds
Started Aug 11 07:18:12 PM PDT 24
Finished Aug 11 07:18:14 PM PDT 24
Peak memory 207604 kb
Host smart-6f035ab1-ff45-4d87-a84e-a23a05afb3b2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408138573 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 498.usbdev_tx_rx_disruption.3408138573
Directory /workspace/498.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/499.usbdev_tx_rx_disruption.3873606811
Short name T1352
Test name
Test status
Simulation time 588245177 ps
CPU time 1.71 seconds
Started Aug 11 07:18:13 PM PDT 24
Finished Aug 11 07:18:15 PM PDT 24
Peak memory 207572 kb
Host smart-ceca1c75-c6f0-4a8e-bf28-4835156ccf57
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873606811 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 499.usbdev_tx_rx_disruption.3873606811
Directory /workspace/499.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/5.usbdev_alert_test.2678451861
Short name T1728
Test name
Test status
Simulation time 28957105 ps
CPU time 0.65 seconds
Started Aug 11 07:09:42 PM PDT 24
Finished Aug 11 07:09:43 PM PDT 24
Peak memory 207540 kb
Host smart-7b16ab14-390d-477d-a77c-3961e4e75028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2678451861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2678451861
Directory /workspace/5.usbdev_alert_test/latest


Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2990402278
Short name T1034
Test name
Test status
Simulation time 9689903318 ps
CPU time 12.23 seconds
Started Aug 11 07:09:31 PM PDT 24
Finished Aug 11 07:09:43 PM PDT 24
Peak memory 207776 kb
Host smart-63d890cf-eb0f-47db-b2c0-c77154276d34
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990402278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.2990402278
Directory /workspace/5.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.234426670
Short name T12
Test name
Test status
Simulation time 15575700036 ps
CPU time 18.62 seconds
Started Aug 11 07:09:27 PM PDT 24
Finished Aug 11 07:09:45 PM PDT 24
Peak memory 216020 kb
Host smart-5ac1faab-5a35-4033-9d6e-8267b4762e9f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=234426670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.234426670
Directory /workspace/5.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3031058075
Short name T3369
Test name
Test status
Simulation time 29085731038 ps
CPU time 32.66 seconds
Started Aug 11 07:09:27 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 207828 kb
Host smart-35d41295-b033-4673-82c0-406b574870ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031058075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.3031058075
Directory /workspace/5.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/5.usbdev_av_buffer.3493463424
Short name T2998
Test name
Test status
Simulation time 176770672 ps
CPU time 0.87 seconds
Started Aug 11 07:09:31 PM PDT 24
Finished Aug 11 07:09:32 PM PDT 24
Peak memory 207512 kb
Host smart-6e4b6e47-3811-47a1-a8e2-50435d71943d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34934
63424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3493463424
Directory /workspace/5.usbdev_av_buffer/latest


Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3418279850
Short name T1453
Test name
Test status
Simulation time 160540777 ps
CPU time 0.91 seconds
Started Aug 11 07:09:29 PM PDT 24
Finished Aug 11 07:09:30 PM PDT 24
Peak memory 207448 kb
Host smart-f3ca7c92-e924-4ea6-bc90-79854467fad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34182
79850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3418279850
Directory /workspace/5.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.2322718845
Short name T1621
Test name
Test status
Simulation time 392905203 ps
CPU time 1.42 seconds
Started Aug 11 07:09:30 PM PDT 24
Finished Aug 11 07:09:31 PM PDT 24
Peak memory 207516 kb
Host smart-cf1d656c-9d22-4ec5-8c01-391ac4163ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23227
18845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.2322718845
Directory /workspace/5.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.761392691
Short name T836
Test name
Test status
Simulation time 580795615 ps
CPU time 1.73 seconds
Started Aug 11 07:09:31 PM PDT 24
Finished Aug 11 07:09:33 PM PDT 24
Peak memory 207560 kb
Host smart-7b451db0-4b78-431b-bd48-a41bf1ae9c90
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=761392691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.761392691
Directory /workspace/5.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/5.usbdev_device_address.1702533695
Short name T428
Test name
Test status
Simulation time 24688053080 ps
CPU time 44.66 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:10:13 PM PDT 24
Peak memory 207752 kb
Host smart-c0785dd7-ea00-4c34-9a26-2377562f38b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17025
33695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1702533695
Directory /workspace/5.usbdev_device_address/latest


Test location /workspace/coverage/default/5.usbdev_device_timeout.2673545124
Short name T1203
Test name
Test status
Simulation time 7072771733 ps
CPU time 48.17 seconds
Started Aug 11 07:09:28 PM PDT 24
Finished Aug 11 07:10:17 PM PDT 24
Peak memory 207824 kb
Host smart-75ff9ae8-b613-4784-afc4-f7f6246f5bed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673545124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.2673545124
Directory /workspace/5.usbdev_device_timeout/latest


Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3739848264
Short name T1229
Test name
Test status
Simulation time 937487979 ps
CPU time 2.53 seconds
Started Aug 11 07:09:37 PM PDT 24
Finished Aug 11 07:09:39 PM PDT 24
Peak memory 207540 kb
Host smart-197bd861-78ef-4bf7-ab20-a9255ff50b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37398
48264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3739848264
Directory /workspace/5.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/5.usbdev_disconnected.625649443
Short name T2478
Test name
Test status
Simulation time 146933080 ps
CPU time 0.82 seconds
Started Aug 11 07:09:36 PM PDT 24
Finished Aug 11 07:09:37 PM PDT 24
Peak memory 207568 kb
Host smart-d9317e83-d764-47ee-a5cc-455515cc57ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62564
9443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.625649443
Directory /workspace/5.usbdev_disconnected/latest


Test location /workspace/coverage/default/5.usbdev_enable.246679747
Short name T749
Test name
Test status
Simulation time 48534111 ps
CPU time 0.69 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:09:35 PM PDT 24
Peak memory 207512 kb
Host smart-cc2eed4b-f07d-43a5-a2b1-973624bb9722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24667
9747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.246679747
Directory /workspace/5.usbdev_enable/latest


Test location /workspace/coverage/default/5.usbdev_endpoint_access.716862489
Short name T1831
Test name
Test status
Simulation time 1022338417 ps
CPU time 2.64 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:09:37 PM PDT 24
Peak memory 207712 kb
Host smart-42fa1ba8-7a0b-4bd7-8d79-fa028407c2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71686
2489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.716862489
Directory /workspace/5.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/5.usbdev_endpoint_types.2801020649
Short name T554
Test name
Test status
Simulation time 320727814 ps
CPU time 1.18 seconds
Started Aug 11 07:09:39 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 207520 kb
Host smart-20691cf5-a0e8-471b-b454-b2dc7d709d65
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2801020649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.2801020649
Directory /workspace/5.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/5.usbdev_fifo_rst.4230467835
Short name T752
Test name
Test status
Simulation time 246431549 ps
CPU time 2.56 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:42 PM PDT 24
Peak memory 207736 kb
Host smart-21cf58c8-b351-4105-8f2d-6cd21e40fb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42304
67835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4230467835
Directory /workspace/5.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/5.usbdev_in_iso.3037772492
Short name T936
Test name
Test status
Simulation time 207923456 ps
CPU time 1.15 seconds
Started Aug 11 07:09:35 PM PDT 24
Finished Aug 11 07:09:36 PM PDT 24
Peak memory 215932 kb
Host smart-6b89c3b8-3ba8-4aea-9134-dbaee7593de8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3037772492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3037772492
Directory /workspace/5.usbdev_in_iso/latest


Test location /workspace/coverage/default/5.usbdev_in_stall.2998431698
Short name T716
Test name
Test status
Simulation time 152490040 ps
CPU time 0.87 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:09:35 PM PDT 24
Peak memory 207508 kb
Host smart-24dae3b1-13e7-43e9-bd43-ef9e33491e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29984
31698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2998431698
Directory /workspace/5.usbdev_in_stall/latest


Test location /workspace/coverage/default/5.usbdev_in_trans.3836585387
Short name T3051
Test name
Test status
Simulation time 194601272 ps
CPU time 0.98 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:09:35 PM PDT 24
Peak memory 207492 kb
Host smart-d7b097a2-fffa-43a8-bc01-4704c848c74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38365
85387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3836585387
Directory /workspace/5.usbdev_in_trans/latest


Test location /workspace/coverage/default/5.usbdev_invalid_sync.1556889451
Short name T3487
Test name
Test status
Simulation time 3737706152 ps
CPU time 32.67 seconds
Started Aug 11 07:09:36 PM PDT 24
Finished Aug 11 07:10:09 PM PDT 24
Peak memory 218504 kb
Host smart-b3e83f9a-6e61-4028-acc1-57600e2d5695
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1556889451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.1556889451
Directory /workspace/5.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/5.usbdev_iso_retraction.3005743028
Short name T2583
Test name
Test status
Simulation time 11571430952 ps
CPU time 147.57 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:12:02 PM PDT 24
Peak memory 207832 kb
Host smart-c281ccb1-0989-4786-b278-3a9e0fd57f3a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3005743028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3005743028
Directory /workspace/5.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/5.usbdev_link_in_err.1000039129
Short name T1242
Test name
Test status
Simulation time 159394289 ps
CPU time 0.93 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 207576 kb
Host smart-c910fd69-f983-4620-9e3d-7fd5cc39034d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10000
39129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1000039129
Directory /workspace/5.usbdev_link_in_err/latest


Test location /workspace/coverage/default/5.usbdev_link_resume.3259827734
Short name T2013
Test name
Test status
Simulation time 27055187101 ps
CPU time 41.43 seconds
Started Aug 11 07:09:37 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207736 kb
Host smart-a9da3c55-9c2c-49b9-bb6e-899750d4b32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32598
27734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.3259827734
Directory /workspace/5.usbdev_link_resume/latest


Test location /workspace/coverage/default/5.usbdev_link_suspend.2291493701
Short name T1690
Test name
Test status
Simulation time 5970899364 ps
CPU time 7.63 seconds
Started Aug 11 07:09:38 PM PDT 24
Finished Aug 11 07:09:46 PM PDT 24
Peak memory 207832 kb
Host smart-c4c8d9e4-ce48-492b-9825-f530b3b327de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22914
93701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2291493701
Directory /workspace/5.usbdev_link_suspend/latest


Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3211832067
Short name T1612
Test name
Test status
Simulation time 3421847025 ps
CPU time 25.54 seconds
Started Aug 11 07:09:32 PM PDT 24
Finished Aug 11 07:09:57 PM PDT 24
Peak memory 224244 kb
Host smart-c13853ce-7e27-411c-91d8-2f91d6bc7200
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3211832067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3211832067
Directory /workspace/5.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.568300459
Short name T3393
Test name
Test status
Simulation time 2527380318 ps
CPU time 20.16 seconds
Started Aug 11 07:09:33 PM PDT 24
Finished Aug 11 07:09:53 PM PDT 24
Peak memory 217712 kb
Host smart-a169168a-0443-4ea0-a151-76b4cc5ccabb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=568300459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.568300459
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3716384294
Short name T926
Test name
Test status
Simulation time 316489983 ps
CPU time 1.17 seconds
Started Aug 11 07:09:35 PM PDT 24
Finished Aug 11 07:09:37 PM PDT 24
Peak memory 207480 kb
Host smart-dee8510f-8699-4e23-a1f4-acfca13a76af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3716384294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3716384294
Directory /workspace/5.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.85945886
Short name T2149
Test name
Test status
Simulation time 186519954 ps
CPU time 0.92 seconds
Started Aug 11 07:09:35 PM PDT 24
Finished Aug 11 07:09:36 PM PDT 24
Peak memory 207520 kb
Host smart-bcfaf0bf-64e1-425b-87e3-8e965a8eb7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85945
886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.85945886
Directory /workspace/5.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.3577091631
Short name T1787
Test name
Test status
Simulation time 2502670557 ps
CPU time 20.16 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:09:55 PM PDT 24
Peak memory 216108 kb
Host smart-f6eb5e4f-45dd-480a-b395-e11e09a2ecf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35770
91631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.3577091631
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.2105668794
Short name T847
Test name
Test status
Simulation time 2623751513 ps
CPU time 23.78 seconds
Started Aug 11 07:09:35 PM PDT 24
Finished Aug 11 07:09:59 PM PDT 24
Peak memory 207896 kb
Host smart-b0971871-2465-4741-90f9-209eb4c5d5b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2105668794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.2105668794
Directory /workspace/5.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1778530063
Short name T761
Test name
Test status
Simulation time 3843527540 ps
CPU time 110.05 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 216076 kb
Host smart-807f7408-4697-47bc-8f17-1b27af458670
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1778530063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1778530063
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.790222251
Short name T1538
Test name
Test status
Simulation time 160037059 ps
CPU time 0.86 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:09:35 PM PDT 24
Peak memory 207520 kb
Host smart-6aa4af40-5641-456a-8734-873dbcbf5609
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=790222251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.790222251
Directory /workspace/5.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.297481856
Short name T1636
Test name
Test status
Simulation time 149905353 ps
CPU time 0.86 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:09:35 PM PDT 24
Peak memory 207512 kb
Host smart-d102a7cd-a6a3-43ed-a753-bff8e714f959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29748
1856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.297481856
Directory /workspace/5.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_nak_trans.706768442
Short name T159
Test name
Test status
Simulation time 192458659 ps
CPU time 0.92 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 207552 kb
Host smart-827ac2a8-02ae-4879-9888-533a4bafc4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70676
8442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.706768442
Directory /workspace/5.usbdev_nak_trans/latest


Test location /workspace/coverage/default/5.usbdev_out_iso.2204256885
Short name T577
Test name
Test status
Simulation time 185890752 ps
CPU time 0.9 seconds
Started Aug 11 07:09:34 PM PDT 24
Finished Aug 11 07:09:35 PM PDT 24
Peak memory 207576 kb
Host smart-1f6ecde0-63a8-423b-aeaf-18667386c89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22042
56885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2204256885
Directory /workspace/5.usbdev_out_iso/latest


Test location /workspace/coverage/default/5.usbdev_out_stall.3295226418
Short name T3374
Test name
Test status
Simulation time 188019509 ps
CPU time 0.88 seconds
Started Aug 11 07:09:37 PM PDT 24
Finished Aug 11 07:09:38 PM PDT 24
Peak memory 207480 kb
Host smart-3196aead-f533-4c08-906e-e3a95dd8992c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32952
26418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3295226418
Directory /workspace/5.usbdev_out_stall/latest


Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1834036397
Short name T1258
Test name
Test status
Simulation time 151083545 ps
CPU time 0.85 seconds
Started Aug 11 07:09:42 PM PDT 24
Finished Aug 11 07:09:43 PM PDT 24
Peak memory 207596 kb
Host smart-d6ad5345-7b16-4690-99c8-d733aaceaeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340
36397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1834036397
Directory /workspace/5.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1901053910
Short name T2759
Test name
Test status
Simulation time 189010504 ps
CPU time 0.88 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 207588 kb
Host smart-ca935ec5-072a-4818-bc8c-a7b7865cdf2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19010
53910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1901053910
Directory /workspace/5.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2397900202
Short name T3126
Test name
Test status
Simulation time 232274117 ps
CPU time 1.08 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 207540 kb
Host smart-527e1e5c-7460-429d-945b-29ae0422cba4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2397900202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2397900202
Directory /workspace/5.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2074201388
Short name T221
Test name
Test status
Simulation time 146468481 ps
CPU time 0.83 seconds
Started Aug 11 07:09:43 PM PDT 24
Finished Aug 11 07:09:44 PM PDT 24
Peak memory 207528 kb
Host smart-2a07f7c3-e003-41d9-b69d-7de3a70a9749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20742
01388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2074201388
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.488157547
Short name T1187
Test name
Test status
Simulation time 38036276 ps
CPU time 0.67 seconds
Started Aug 11 07:09:43 PM PDT 24
Finished Aug 11 07:09:44 PM PDT 24
Peak memory 207540 kb
Host smart-13514235-701b-47a1-abcc-cd211f0f847c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48815
7547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.488157547
Directory /workspace/5.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3589929662
Short name T94
Test name
Test status
Simulation time 10702099020 ps
CPU time 28.8 seconds
Started Aug 11 07:09:45 PM PDT 24
Finished Aug 11 07:10:14 PM PDT 24
Peak memory 220840 kb
Host smart-14538cce-e5fb-4069-b091-f9b615dbdbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35899
29662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3589929662
Directory /workspace/5.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/5.usbdev_pkt_received.3630342947
Short name T1209
Test name
Test status
Simulation time 177442372 ps
CPU time 0.91 seconds
Started Aug 11 07:09:41 PM PDT 24
Finished Aug 11 07:09:42 PM PDT 24
Peak memory 207568 kb
Host smart-a12b427d-0568-4de2-904d-ed54b3717780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303
42947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3630342947
Directory /workspace/5.usbdev_pkt_received/latest


Test location /workspace/coverage/default/5.usbdev_pkt_sent.329804487
Short name T1220
Test name
Test status
Simulation time 259950476 ps
CPU time 0.96 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 207568 kb
Host smart-ed36a179-e12d-48a3-b5ca-b019be0b762e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32980
4487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.329804487
Directory /workspace/5.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1099803263
Short name T2523
Test name
Test status
Simulation time 3290098562 ps
CPU time 27.2 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:10:07 PM PDT 24
Peak memory 224188 kb
Host smart-1027bbad-7cd9-47fe-ad3c-6cd45ec8f7ef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1099803263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1099803263
Directory /workspace/5.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/5.usbdev_rand_suspends.3506956929
Short name T2974
Test name
Test status
Simulation time 6266309907 ps
CPU time 24.46 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:10:05 PM PDT 24
Peak memory 220056 kb
Host smart-e9a9b417-276d-44a8-9786-0a9a90f32025
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506956929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3506956929
Directory /workspace/5.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1307288751
Short name T893
Test name
Test status
Simulation time 217068643 ps
CPU time 1.02 seconds
Started Aug 11 07:09:43 PM PDT 24
Finished Aug 11 07:09:44 PM PDT 24
Peak memory 207552 kb
Host smart-62ba3fde-9834-4554-9097-f2126ec5d021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13072
88751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1307288751
Directory /workspace/5.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.4245626769
Short name T642
Test name
Test status
Simulation time 228581856 ps
CPU time 0.92 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 207568 kb
Host smart-a89b6649-27d4-4f4d-a27a-ec241593f7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456
26769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.4245626769
Directory /workspace/5.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_resume_link_active.166843286
Short name T2196
Test name
Test status
Simulation time 20213598121 ps
CPU time 22.51 seconds
Started Aug 11 07:09:41 PM PDT 24
Finished Aug 11 07:10:03 PM PDT 24
Peak memory 207828 kb
Host smart-a61b6133-8bf8-44d8-b3c3-1326b5ab9112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16684
3286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.166843286
Directory /workspace/5.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2978425494
Short name T3324
Test name
Test status
Simulation time 188837712 ps
CPU time 0.9 seconds
Started Aug 11 07:09:41 PM PDT 24
Finished Aug 11 07:09:42 PM PDT 24
Peak memory 207548 kb
Host smart-e1db3d60-5d45-4ba3-b1ca-da7910d8b7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29784
25494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2978425494
Directory /workspace/5.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/5.usbdev_rx_full.1898298737
Short name T56
Test name
Test status
Simulation time 298365580 ps
CPU time 1.13 seconds
Started Aug 11 07:09:41 PM PDT 24
Finished Aug 11 07:09:42 PM PDT 24
Peak memory 207544 kb
Host smart-3f7352b9-6365-4af7-a6dc-aa378b0bd9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18982
98737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.1898298737
Directory /workspace/5.usbdev_rx_full/latest


Test location /workspace/coverage/default/5.usbdev_setup_stage.643234282
Short name T2615
Test name
Test status
Simulation time 156407116 ps
CPU time 0.87 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 207516 kb
Host smart-c8cb8dba-79b5-4097-afc2-ae6c8551db1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64323
4282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.643234282
Directory /workspace/5.usbdev_setup_stage/latest


Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.42794960
Short name T3195
Test name
Test status
Simulation time 215764194 ps
CPU time 0.93 seconds
Started Aug 11 07:09:42 PM PDT 24
Finished Aug 11 07:09:43 PM PDT 24
Peak memory 207500 kb
Host smart-aa58778e-3e56-4c88-855f-a4b2d34d8c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42794
960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.42794960
Directory /workspace/5.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/5.usbdev_smoke.23155242
Short name T3240
Test name
Test status
Simulation time 243477017 ps
CPU time 1.08 seconds
Started Aug 11 07:09:43 PM PDT 24
Finished Aug 11 07:09:45 PM PDT 24
Peak memory 207576 kb
Host smart-72710fb4-50fd-4e0f-a14c-ca5a77a2101a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23155
242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.23155242
Directory /workspace/5.usbdev_smoke/latest


Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1791872918
Short name T3176
Test name
Test status
Simulation time 2796984304 ps
CPU time 22.19 seconds
Started Aug 11 07:09:44 PM PDT 24
Finished Aug 11 07:10:06 PM PDT 24
Peak memory 224276 kb
Host smart-b0975f9b-0cb4-4b88-b944-38a67a14e0fa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1791872918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1791872918
Directory /workspace/5.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1212680881
Short name T546
Test name
Test status
Simulation time 226086858 ps
CPU time 0.92 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:41 PM PDT 24
Peak memory 207528 kb
Host smart-2e1f6acb-0e47-43fd-b1db-2463696bec9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12126
80881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1212680881
Directory /workspace/5.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/5.usbdev_stall_trans.1130954854
Short name T2781
Test name
Test status
Simulation time 154424188 ps
CPU time 0.83 seconds
Started Aug 11 07:09:42 PM PDT 24
Finished Aug 11 07:09:43 PM PDT 24
Peak memory 207572 kb
Host smart-2de50089-94a8-45de-b0ca-1b0d1653b4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11309
54854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1130954854
Directory /workspace/5.usbdev_stall_trans/latest


Test location /workspace/coverage/default/5.usbdev_stream_len_max.910118922
Short name T2249
Test name
Test status
Simulation time 1011255082 ps
CPU time 2.67 seconds
Started Aug 11 07:09:42 PM PDT 24
Finished Aug 11 07:09:45 PM PDT 24
Peak memory 207696 kb
Host smart-4c23a3e8-675a-445c-8842-6fa744bf9824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91011
8922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.910118922
Directory /workspace/5.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/5.usbdev_streaming_out.3939266568
Short name T3334
Test name
Test status
Simulation time 2423864734 ps
CPU time 18.32 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 217612 kb
Host smart-bc2632b6-3602-4958-b405-87cae0fbc4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39392
66568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3939266568
Directory /workspace/5.usbdev_streaming_out/latest


Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.2845971300
Short name T3259
Test name
Test status
Simulation time 3599699764 ps
CPU time 23.92 seconds
Started Aug 11 07:09:29 PM PDT 24
Finished Aug 11 07:09:53 PM PDT 24
Peak memory 207780 kb
Host smart-22a84960-3957-49a3-b3b2-1fc1ccb3948e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845971300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.2845971300
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/5.usbdev_tx_rx_disruption.1104389055
Short name T186
Test name
Test status
Simulation time 542441982 ps
CPU time 1.52 seconds
Started Aug 11 07:09:41 PM PDT 24
Finished Aug 11 07:09:43 PM PDT 24
Peak memory 207560 kb
Host smart-4ea429f2-f85d-441e-8be8-330261556f60
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104389055 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.usbdev_tx_rx_disruption.1104389055
Directory /workspace/5.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/50.usbdev_endpoint_types.1440648546
Short name T480
Test name
Test status
Simulation time 573068834 ps
CPU time 1.7 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207516 kb
Host smart-74d68e5f-2506-4d1f-81cd-9a1d205ed79b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1440648546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.1440648546
Directory /workspace/50.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/50.usbdev_tx_rx_disruption.635932329
Short name T1599
Test name
Test status
Simulation time 615761746 ps
CPU time 1.66 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 207576 kb
Host smart-e1fc4a10-d43f-40fb-ade3-3eea4bf02684
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635932329 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 50.usbdev_tx_rx_disruption.635932329
Directory /workspace/50.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/51.usbdev_endpoint_types.4020984878
Short name T3380
Test name
Test status
Simulation time 624604995 ps
CPU time 1.5 seconds
Started Aug 11 07:16:33 PM PDT 24
Finished Aug 11 07:16:35 PM PDT 24
Peak memory 207716 kb
Host smart-c98dc5f0-3277-4300-8fc2-747f2bf04795
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4020984878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.4020984878
Directory /workspace/51.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/51.usbdev_tx_rx_disruption.824198243
Short name T3588
Test name
Test status
Simulation time 474908951 ps
CPU time 1.59 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:16:38 PM PDT 24
Peak memory 207572 kb
Host smart-1baa87a5-bc23-45fe-8ae0-5d68ac31ecb5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824198243 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 51.usbdev_tx_rx_disruption.824198243
Directory /workspace/51.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/52.usbdev_endpoint_types.188317841
Short name T2727
Test name
Test status
Simulation time 718940493 ps
CPU time 1.66 seconds
Started Aug 11 07:16:41 PM PDT 24
Finished Aug 11 07:16:43 PM PDT 24
Peak memory 207532 kb
Host smart-dd3f4611-de35-48d7-87fc-04cca8ab3289
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=188317841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.188317841
Directory /workspace/52.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/52.usbdev_tx_rx_disruption.1647152108
Short name T1752
Test name
Test status
Simulation time 498981972 ps
CPU time 1.47 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 207560 kb
Host smart-1f6bca33-9f71-49ea-92e3-05ab8193dbd6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647152108 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.usbdev_tx_rx_disruption.1647152108
Directory /workspace/52.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/53.usbdev_endpoint_types.4223381119
Short name T542
Test name
Test status
Simulation time 201970241 ps
CPU time 1.01 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 206540 kb
Host smart-c9f003b8-8217-433e-abd0-8f751fafc444
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4223381119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.4223381119
Directory /workspace/53.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/53.usbdev_tx_rx_disruption.2470911276
Short name T205
Test name
Test status
Simulation time 660139608 ps
CPU time 1.83 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207540 kb
Host smart-cab9e3df-d11e-4b87-81b9-b58f2c8ab0b4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470911276 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.usbdev_tx_rx_disruption.2470911276
Directory /workspace/53.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/54.usbdev_endpoint_types.2501043887
Short name T3475
Test name
Test status
Simulation time 307548540 ps
CPU time 1.12 seconds
Started Aug 11 07:16:44 PM PDT 24
Finished Aug 11 07:16:45 PM PDT 24
Peak memory 207516 kb
Host smart-e82501c7-5211-4303-95a8-3ecebd983683
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2501043887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.2501043887
Directory /workspace/54.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/54.usbdev_tx_rx_disruption.372578960
Short name T2558
Test name
Test status
Simulation time 650111561 ps
CPU time 1.73 seconds
Started Aug 11 07:16:52 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207580 kb
Host smart-121ed777-9475-4592-b4f7-0e8fae9ce402
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372578960 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 54.usbdev_tx_rx_disruption.372578960
Directory /workspace/54.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/55.usbdev_tx_rx_disruption.563965820
Short name T3154
Test name
Test status
Simulation time 515624729 ps
CPU time 1.61 seconds
Started Aug 11 07:16:31 PM PDT 24
Finished Aug 11 07:16:33 PM PDT 24
Peak memory 207576 kb
Host smart-6b6d260f-df7a-4e6a-a86b-f702c3ab29b4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563965820 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 55.usbdev_tx_rx_disruption.563965820
Directory /workspace/55.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/56.usbdev_endpoint_types.787185869
Short name T511
Test name
Test status
Simulation time 379130228 ps
CPU time 1.25 seconds
Started Aug 11 07:16:44 PM PDT 24
Finished Aug 11 07:16:46 PM PDT 24
Peak memory 207544 kb
Host smart-dcd58b82-ad17-4bad-88f0-9c128db5dd78
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=787185869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.787185869
Directory /workspace/56.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/56.usbdev_tx_rx_disruption.2922467904
Short name T2788
Test name
Test status
Simulation time 514853028 ps
CPU time 1.54 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207540 kb
Host smart-9dd2614b-4ceb-478b-8fc1-fa081888ac79
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922467904 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.usbdev_tx_rx_disruption.2922467904
Directory /workspace/56.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/57.usbdev_endpoint_types.3846661626
Short name T430
Test name
Test status
Simulation time 364566489 ps
CPU time 1.22 seconds
Started Aug 11 07:16:41 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 207508 kb
Host smart-2e992322-9934-43f1-9d8b-c911804c09d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3846661626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.3846661626
Directory /workspace/57.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/57.usbdev_tx_rx_disruption.2990460430
Short name T2741
Test name
Test status
Simulation time 500947990 ps
CPU time 1.61 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207532 kb
Host smart-a0f49c72-dd07-4f6b-bb3b-e77bbbd8ee12
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990460430 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.usbdev_tx_rx_disruption.2990460430
Directory /workspace/57.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/58.usbdev_endpoint_types.3934871223
Short name T497
Test name
Test status
Simulation time 312335570 ps
CPU time 1.13 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207576 kb
Host smart-c57437e2-50dc-431d-bc0d-71a86b2ad540
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3934871223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.3934871223
Directory /workspace/58.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/58.usbdev_tx_rx_disruption.2297125018
Short name T2281
Test name
Test status
Simulation time 625590541 ps
CPU time 1.83 seconds
Started Aug 11 07:16:43 PM PDT 24
Finished Aug 11 07:16:50 PM PDT 24
Peak memory 207720 kb
Host smart-ab862df9-57bb-4b1a-a3f1-ba1ea51ca245
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297125018 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.usbdev_tx_rx_disruption.2297125018
Directory /workspace/58.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/59.usbdev_endpoint_types.4022219228
Short name T538
Test name
Test status
Simulation time 278442378 ps
CPU time 1.04 seconds
Started Aug 11 07:16:43 PM PDT 24
Finished Aug 11 07:16:44 PM PDT 24
Peak memory 207480 kb
Host smart-dbb56550-9918-4f43-83b1-b02be6c12ffb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4022219228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.4022219228
Directory /workspace/59.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/59.usbdev_tx_rx_disruption.2835531527
Short name T2857
Test name
Test status
Simulation time 475828642 ps
CPU time 1.47 seconds
Started Aug 11 07:16:36 PM PDT 24
Finished Aug 11 07:16:38 PM PDT 24
Peak memory 207552 kb
Host smart-84875285-12f6-4025-a4d8-4631c2282ea4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835531527 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.usbdev_tx_rx_disruption.2835531527
Directory /workspace/59.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/6.usbdev_alert_test.521577438
Short name T2728
Test name
Test status
Simulation time 59015338 ps
CPU time 0.78 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:09:52 PM PDT 24
Peak memory 207460 kb
Host smart-3efca404-75e4-4618-bc76-d463af368322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=521577438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.521577438
Directory /workspace/6.usbdev_alert_test/latest


Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2389560499
Short name T976
Test name
Test status
Simulation time 3862809670 ps
CPU time 6.01 seconds
Started Aug 11 07:09:40 PM PDT 24
Finished Aug 11 07:09:46 PM PDT 24
Peak memory 216044 kb
Host smart-69da1467-99e6-408b-94d6-c9bfce6acf03
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389560499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.2389560499
Directory /workspace/6.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3084452910
Short name T218
Test name
Test status
Simulation time 13664078533 ps
CPU time 18.43 seconds
Started Aug 11 07:09:42 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 216008 kb
Host smart-199e07b0-794c-4f77-ba17-92eaa7bd394d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084452910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3084452910
Directory /workspace/6.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3243421248
Short name T3462
Test name
Test status
Simulation time 30525133377 ps
CPU time 34.99 seconds
Started Aug 11 07:09:39 PM PDT 24
Finished Aug 11 07:10:14 PM PDT 24
Peak memory 207856 kb
Host smart-268c6e4f-182a-494d-b639-2bfff1bdbe96
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243421248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.3243421248
Directory /workspace/6.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/6.usbdev_av_buffer.841815033
Short name T728
Test name
Test status
Simulation time 166270790 ps
CPU time 0.88 seconds
Started Aug 11 07:09:44 PM PDT 24
Finished Aug 11 07:09:45 PM PDT 24
Peak memory 207484 kb
Host smart-b5271fee-0cec-4a19-b69c-c1571aa3c347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84181
5033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.841815033
Directory /workspace/6.usbdev_av_buffer/latest


Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3447043815
Short name T2148
Test name
Test status
Simulation time 153484017 ps
CPU time 0.85 seconds
Started Aug 11 07:09:41 PM PDT 24
Finished Aug 11 07:09:42 PM PDT 24
Peak memory 207544 kb
Host smart-281634ab-0377-49a9-b4a1-d79a78033129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34470
43815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3447043815
Directory /workspace/6.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.826033404
Short name T3477
Test name
Test status
Simulation time 335892857 ps
CPU time 1.31 seconds
Started Aug 11 07:09:50 PM PDT 24
Finished Aug 11 07:09:51 PM PDT 24
Peak memory 207516 kb
Host smart-483d7218-5547-4fa9-a08c-4438d41c6b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82603
3404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.826033404
Directory /workspace/6.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1595646150
Short name T2114
Test name
Test status
Simulation time 466646730 ps
CPU time 1.48 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207508 kb
Host smart-0c7d97c6-9592-407b-9bff-d835def3a0c7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1595646150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1595646150
Directory /workspace/6.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/6.usbdev_device_address.1826276123
Short name T194
Test name
Test status
Simulation time 43891427077 ps
CPU time 81.64 seconds
Started Aug 11 07:09:47 PM PDT 24
Finished Aug 11 07:11:09 PM PDT 24
Peak memory 207760 kb
Host smart-0b678781-7551-46d5-9a10-649603893fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18262
76123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.1826276123
Directory /workspace/6.usbdev_device_address/latest


Test location /workspace/coverage/default/6.usbdev_device_timeout.1403566534
Short name T2928
Test name
Test status
Simulation time 5044871761 ps
CPU time 31.99 seconds
Started Aug 11 07:09:46 PM PDT 24
Finished Aug 11 07:10:18 PM PDT 24
Peak memory 207828 kb
Host smart-2973b4a9-796b-4d84-93d4-b517d7b5ec9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403566534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.1403566534
Directory /workspace/6.usbdev_device_timeout/latest


Test location /workspace/coverage/default/6.usbdev_disable_endpoint.896051622
Short name T721
Test name
Test status
Simulation time 685189285 ps
CPU time 1.85 seconds
Started Aug 11 07:09:46 PM PDT 24
Finished Aug 11 07:09:48 PM PDT 24
Peak memory 207528 kb
Host smart-5ef5efa6-c3da-4d40-92a1-94b566ec1fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89605
1622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.896051622
Directory /workspace/6.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/6.usbdev_disconnected.2842952756
Short name T3403
Test name
Test status
Simulation time 150149343 ps
CPU time 0.84 seconds
Started Aug 11 07:09:48 PM PDT 24
Finished Aug 11 07:09:49 PM PDT 24
Peak memory 207532 kb
Host smart-3848f8b6-6389-417d-b2ac-52d4a021baa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28429
52756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2842952756
Directory /workspace/6.usbdev_disconnected/latest


Test location /workspace/coverage/default/6.usbdev_enable.226230807
Short name T2711
Test name
Test status
Simulation time 85229796 ps
CPU time 0.74 seconds
Started Aug 11 07:09:47 PM PDT 24
Finished Aug 11 07:09:48 PM PDT 24
Peak memory 207536 kb
Host smart-c9e1ac49-1746-4109-a688-e299d1248c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22623
0807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.226230807
Directory /workspace/6.usbdev_enable/latest


Test location /workspace/coverage/default/6.usbdev_endpoint_access.2478420699
Short name T2970
Test name
Test status
Simulation time 863886650 ps
CPU time 2.26 seconds
Started Aug 11 07:09:49 PM PDT 24
Finished Aug 11 07:09:51 PM PDT 24
Peak memory 207696 kb
Host smart-cb116923-726b-48a4-9b5e-1eda4c0f25b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24784
20699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2478420699
Directory /workspace/6.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/6.usbdev_endpoint_types.4285444961
Short name T1264
Test name
Test status
Simulation time 170267933 ps
CPU time 0.88 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207480 kb
Host smart-f272d3a4-2c7e-4b18-9551-6495d7b89b51
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4285444961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.4285444961
Directory /workspace/6.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/6.usbdev_fifo_rst.2419809911
Short name T2235
Test name
Test status
Simulation time 275145203 ps
CPU time 1.99 seconds
Started Aug 11 07:09:48 PM PDT 24
Finished Aug 11 07:09:50 PM PDT 24
Peak memory 207680 kb
Host smart-d2af2d4a-8974-4a5e-937d-3d11b3ab639a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24198
09911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2419809911
Directory /workspace/6.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/6.usbdev_in_iso.2272996323
Short name T2452
Test name
Test status
Simulation time 177367686 ps
CPU time 1 seconds
Started Aug 11 07:09:46 PM PDT 24
Finished Aug 11 07:09:47 PM PDT 24
Peak memory 215872 kb
Host smart-34b52857-034d-4d13-8f11-9b23a45c51b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2272996323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2272996323
Directory /workspace/6.usbdev_in_iso/latest


Test location /workspace/coverage/default/6.usbdev_in_stall.3657768164
Short name T2225
Test name
Test status
Simulation time 148326761 ps
CPU time 0.83 seconds
Started Aug 11 07:09:48 PM PDT 24
Finished Aug 11 07:09:49 PM PDT 24
Peak memory 207512 kb
Host smart-dd6b7b89-505f-4e15-a790-0e191b7975af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36577
68164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3657768164
Directory /workspace/6.usbdev_in_stall/latest


Test location /workspace/coverage/default/6.usbdev_in_trans.1594636667
Short name T2251
Test name
Test status
Simulation time 228919118 ps
CPU time 1.02 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:09:52 PM PDT 24
Peak memory 207492 kb
Host smart-92f46fa2-6237-41f8-a17f-b32e0ace633c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15946
36667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1594636667
Directory /workspace/6.usbdev_in_trans/latest


Test location /workspace/coverage/default/6.usbdev_invalid_sync.3326803862
Short name T3529
Test name
Test status
Simulation time 4932363635 ps
CPU time 38.19 seconds
Started Aug 11 07:09:47 PM PDT 24
Finished Aug 11 07:10:26 PM PDT 24
Peak memory 218424 kb
Host smart-fc161145-6350-4a74-912a-c8fe34a5a788
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3326803862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3326803862
Directory /workspace/6.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/6.usbdev_iso_retraction.192605829
Short name T844
Test name
Test status
Simulation time 9988640094 ps
CPU time 65.47 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:11:02 PM PDT 24
Peak memory 207772 kb
Host smart-931ff910-c170-4bda-8a3e-df5c8769f6a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=192605829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.192605829
Directory /workspace/6.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/6.usbdev_link_in_err.1597938400
Short name T1531
Test name
Test status
Simulation time 228845300 ps
CPU time 0.94 seconds
Started Aug 11 07:09:46 PM PDT 24
Finished Aug 11 07:09:47 PM PDT 24
Peak memory 207604 kb
Host smart-c4d63da8-7769-4eca-9b85-87c3b7cfbf6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15979
38400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1597938400
Directory /workspace/6.usbdev_link_in_err/latest


Test location /workspace/coverage/default/6.usbdev_link_resume.166511620
Short name T1305
Test name
Test status
Simulation time 9587132947 ps
CPU time 15.74 seconds
Started Aug 11 07:09:46 PM PDT 24
Finished Aug 11 07:10:02 PM PDT 24
Peak memory 207808 kb
Host smart-af91fae1-732b-4b3c-acf3-345802a7d1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16651
1620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.166511620
Directory /workspace/6.usbdev_link_resume/latest


Test location /workspace/coverage/default/6.usbdev_link_suspend.1540258228
Short name T1539
Test name
Test status
Simulation time 9822162756 ps
CPU time 13.47 seconds
Started Aug 11 07:09:50 PM PDT 24
Finished Aug 11 07:10:04 PM PDT 24
Peak memory 207792 kb
Host smart-5e4dec14-5200-4443-8ceb-146466977447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15402
58228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1540258228
Directory /workspace/6.usbdev_link_suspend/latest


Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.545638865
Short name T1864
Test name
Test status
Simulation time 2017588498 ps
CPU time 56.58 seconds
Started Aug 11 07:09:48 PM PDT 24
Finished Aug 11 07:10:45 PM PDT 24
Peak memory 224148 kb
Host smart-821547bf-e997-4d8d-a19c-6b3852b8e949
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=545638865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.545638865
Directory /workspace/6.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.2102978574
Short name T106
Test name
Test status
Simulation time 2458777338 ps
CPU time 19.63 seconds
Started Aug 11 07:09:46 PM PDT 24
Finished Aug 11 07:10:06 PM PDT 24
Peak memory 216036 kb
Host smart-3f8d3458-5b8b-42b6-9918-3a42f7f7dfe8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2102978574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2102978574
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.4261121052
Short name T1146
Test name
Test status
Simulation time 284770692 ps
CPU time 1.11 seconds
Started Aug 11 07:09:48 PM PDT 24
Finished Aug 11 07:09:49 PM PDT 24
Peak memory 207540 kb
Host smart-cc2ff491-5cb3-4426-9d74-00067fa83a3e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4261121052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.4261121052
Directory /workspace/6.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.711919894
Short name T593
Test name
Test status
Simulation time 209728658 ps
CPU time 0.97 seconds
Started Aug 11 07:09:48 PM PDT 24
Finished Aug 11 07:09:49 PM PDT 24
Peak memory 207484 kb
Host smart-e25245a1-ec5c-4ef7-9b5c-14e4d5fc3be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71191
9894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.711919894
Directory /workspace/6.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.4170130973
Short name T1885
Test name
Test status
Simulation time 3693224857 ps
CPU time 29.15 seconds
Started Aug 11 07:09:48 PM PDT 24
Finished Aug 11 07:10:17 PM PDT 24
Peak memory 216136 kb
Host smart-d8a5bb17-599f-4a78-ad84-6e5ffadbd984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701
30973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.4170130973
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2043784605
Short name T3534
Test name
Test status
Simulation time 2499296445 ps
CPU time 21.54 seconds
Started Aug 11 07:09:45 PM PDT 24
Finished Aug 11 07:10:07 PM PDT 24
Peak memory 216068 kb
Host smart-43009c1a-bfb5-4546-b42f-60637ca1ea89
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2043784605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2043784605
Directory /workspace/6.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.2359234197
Short name T717
Test name
Test status
Simulation time 3501767771 ps
CPU time 99.92 seconds
Started Aug 11 07:09:47 PM PDT 24
Finished Aug 11 07:11:28 PM PDT 24
Peak memory 216056 kb
Host smart-67a79cc1-a60e-4321-9974-25fcbb5f9cbe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2359234197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.2359234197
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.4069285583
Short name T3219
Test name
Test status
Simulation time 162797999 ps
CPU time 0.84 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207512 kb
Host smart-451e23ca-8d12-44e2-858c-f1447e132247
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4069285583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.4069285583
Directory /workspace/6.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.800924788
Short name T3086
Test name
Test status
Simulation time 175096800 ps
CPU time 0.89 seconds
Started Aug 11 07:09:47 PM PDT 24
Finished Aug 11 07:09:48 PM PDT 24
Peak memory 207508 kb
Host smart-d465c219-8f4b-41f2-bee8-f6a462699fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80092
4788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.800924788
Directory /workspace/6.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_nak_trans.230094197
Short name T153
Test name
Test status
Simulation time 251202015 ps
CPU time 1 seconds
Started Aug 11 07:09:48 PM PDT 24
Finished Aug 11 07:09:49 PM PDT 24
Peak memory 207476 kb
Host smart-8ab32584-84f0-43fb-9316-0228e7817f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23009
4197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.230094197
Directory /workspace/6.usbdev_nak_trans/latest


Test location /workspace/coverage/default/6.usbdev_out_iso.3507851714
Short name T2327
Test name
Test status
Simulation time 151762073 ps
CPU time 0.84 seconds
Started Aug 11 07:09:49 PM PDT 24
Finished Aug 11 07:09:50 PM PDT 24
Peak memory 207512 kb
Host smart-e573318b-a8ea-4756-b1e3-f66bf610ee41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35078
51714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3507851714
Directory /workspace/6.usbdev_out_iso/latest


Test location /workspace/coverage/default/6.usbdev_out_stall.2030345935
Short name T2091
Test name
Test status
Simulation time 181828637 ps
CPU time 0.91 seconds
Started Aug 11 07:09:50 PM PDT 24
Finished Aug 11 07:09:52 PM PDT 24
Peak memory 207472 kb
Host smart-46f2ecfc-d67d-40b9-93e1-b698849470a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20303
45935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2030345935
Directory /workspace/6.usbdev_out_stall/latest


Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3333904595
Short name T1400
Test name
Test status
Simulation time 189685480 ps
CPU time 0.89 seconds
Started Aug 11 07:09:47 PM PDT 24
Finished Aug 11 07:09:48 PM PDT 24
Peak memory 207568 kb
Host smart-1f835535-85e4-4166-8a75-5da4429dcf83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33339
04595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3333904595
Directory /workspace/6.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2761739130
Short name T1145
Test name
Test status
Simulation time 146862598 ps
CPU time 0.86 seconds
Started Aug 11 07:09:47 PM PDT 24
Finished Aug 11 07:09:48 PM PDT 24
Peak memory 207508 kb
Host smart-49453139-c6b9-4351-bf84-452cd2cb66ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27617
39130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2761739130
Directory /workspace/6.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1614014152
Short name T215
Test name
Test status
Simulation time 238257028 ps
CPU time 1.07 seconds
Started Aug 11 07:09:50 PM PDT 24
Finished Aug 11 07:09:51 PM PDT 24
Peak memory 207472 kb
Host smart-2c8bcf69-0542-4b2f-af06-78c0645617ed
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1614014152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1614014152
Directory /workspace/6.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3045106670
Short name T1804
Test name
Test status
Simulation time 143219843 ps
CPU time 0.81 seconds
Started Aug 11 07:09:47 PM PDT 24
Finished Aug 11 07:09:48 PM PDT 24
Peak memory 207512 kb
Host smart-d7b12aad-fabd-4272-8149-dd46bd5d4300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30451
06670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3045106670
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.826935619
Short name T1802
Test name
Test status
Simulation time 55259793 ps
CPU time 0.7 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:09:57 PM PDT 24
Peak memory 207480 kb
Host smart-0b4e0096-37cd-4be3-bd79-b0ea9f284636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82693
5619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.826935619
Directory /workspace/6.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2416752695
Short name T300
Test name
Test status
Simulation time 15169486879 ps
CPU time 39.81 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:10:31 PM PDT 24
Peak memory 215960 kb
Host smart-050e4307-56a7-4a02-8fab-f26d08fc17df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24167
52695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2416752695
Directory /workspace/6.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/6.usbdev_pkt_received.4055529677
Short name T1755
Test name
Test status
Simulation time 182422099 ps
CPU time 0.85 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207520 kb
Host smart-8a61183d-ea84-4968-bf8b-cb098e4f6cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40555
29677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.4055529677
Directory /workspace/6.usbdev_pkt_received/latest


Test location /workspace/coverage/default/6.usbdev_pkt_sent.1284129102
Short name T674
Test name
Test status
Simulation time 171634043 ps
CPU time 0.88 seconds
Started Aug 11 07:09:50 PM PDT 24
Finished Aug 11 07:09:51 PM PDT 24
Peak memory 207476 kb
Host smart-742e8a15-a1c6-461a-970b-863fd0c07fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12841
29102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1284129102
Directory /workspace/6.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2201501198
Short name T1441
Test name
Test status
Simulation time 7486181933 ps
CPU time 220.04 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:13:34 PM PDT 24
Peak memory 218488 kb
Host smart-31b64496-2fc4-414c-9392-3263f2b91dd3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201501198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2201501198
Directory /workspace/6.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2552791524
Short name T2205
Test name
Test status
Simulation time 6984259679 ps
CPU time 38.95 seconds
Started Aug 11 07:09:54 PM PDT 24
Finished Aug 11 07:10:33 PM PDT 24
Peak memory 224212 kb
Host smart-4fd99bb2-d594-4446-aad3-f0ab2558cdb4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2552791524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2552791524
Directory /workspace/6.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/6.usbdev_rand_suspends.1347648900
Short name T3302
Test name
Test status
Simulation time 10600050880 ps
CPU time 206.27 seconds
Started Aug 11 07:09:54 PM PDT 24
Finished Aug 11 07:13:20 PM PDT 24
Peak memory 218568 kb
Host smart-9a128ea9-7523-4b30-85f9-cb51f3999230
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347648900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1347648900
Directory /workspace/6.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.82433288
Short name T244
Test name
Test status
Simulation time 169277545 ps
CPU time 0.89 seconds
Started Aug 11 07:09:47 PM PDT 24
Finished Aug 11 07:09:48 PM PDT 24
Peak memory 207596 kb
Host smart-482981b6-5627-4bd1-b9d8-016d6708b6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82433
288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.82433288
Directory /workspace/6.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1197661335
Short name T2431
Test name
Test status
Simulation time 159262314 ps
CPU time 0.89 seconds
Started Aug 11 07:09:50 PM PDT 24
Finished Aug 11 07:09:51 PM PDT 24
Peak memory 207552 kb
Host smart-b7618459-2664-48e2-a84f-9f1f1486eaa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11976
61335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1197661335
Directory /workspace/6.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_resume_link_active.1954953372
Short name T2622
Test name
Test status
Simulation time 20185077191 ps
CPU time 29.44 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:10:20 PM PDT 24
Peak memory 207652 kb
Host smart-857eeaeb-8b5c-4536-bab5-82c79cc7787b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19549
53372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.1954953372
Directory /workspace/6.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/6.usbdev_rx_crc_err.27102978
Short name T394
Test name
Test status
Simulation time 143292929 ps
CPU time 0.82 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:09:55 PM PDT 24
Peak memory 207512 kb
Host smart-894aaafe-300f-489b-8f8d-3c841f20fbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27102
978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.27102978
Directory /workspace/6.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/6.usbdev_rx_full.1319708047
Short name T1709
Test name
Test status
Simulation time 373673109 ps
CPU time 1.27 seconds
Started Aug 11 07:09:50 PM PDT 24
Finished Aug 11 07:09:51 PM PDT 24
Peak memory 207532 kb
Host smart-0654335c-437a-4235-a557-2957c54a41ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13197
08047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.1319708047
Directory /workspace/6.usbdev_rx_full/latest


Test location /workspace/coverage/default/6.usbdev_setup_stage.963884426
Short name T3140
Test name
Test status
Simulation time 173914478 ps
CPU time 0.83 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:09:52 PM PDT 24
Peak memory 207532 kb
Host smart-16d3d9b0-47be-4661-9f74-2ba29ce68aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96388
4426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.963884426
Directory /workspace/6.usbdev_setup_stage/latest


Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3362418926
Short name T853
Test name
Test status
Simulation time 153754547 ps
CPU time 0.92 seconds
Started Aug 11 07:09:54 PM PDT 24
Finished Aug 11 07:09:55 PM PDT 24
Peak memory 207480 kb
Host smart-5f083268-035a-4b4a-b2db-f7a011056feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624
18926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3362418926
Directory /workspace/6.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/6.usbdev_smoke.2213143941
Short name T1031
Test name
Test status
Simulation time 214221185 ps
CPU time 1 seconds
Started Aug 11 07:09:52 PM PDT 24
Finished Aug 11 07:09:53 PM PDT 24
Peak memory 207572 kb
Host smart-83729689-db01-4cb0-b46a-8c5543aa4761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22131
43941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2213143941
Directory /workspace/6.usbdev_smoke/latest


Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3938422503
Short name T2918
Test name
Test status
Simulation time 2869591725 ps
CPU time 87.47 seconds
Started Aug 11 07:09:52 PM PDT 24
Finished Aug 11 07:11:19 PM PDT 24
Peak memory 217828 kb
Host smart-d2c0a7f5-5072-4a6c-8a53-add6b30f3e01
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3938422503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3938422503
Directory /workspace/6.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2572155073
Short name T3552
Test name
Test status
Simulation time 167406686 ps
CPU time 0.91 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:09:52 PM PDT 24
Peak memory 207504 kb
Host smart-a01f8a6e-13e3-413a-a0fc-a47e38b535c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25721
55073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2572155073
Directory /workspace/6.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/6.usbdev_stall_trans.2038596447
Short name T543
Test name
Test status
Simulation time 159418294 ps
CPU time 0.86 seconds
Started Aug 11 07:09:55 PM PDT 24
Finished Aug 11 07:09:56 PM PDT 24
Peak memory 207484 kb
Host smart-1795daeb-c9e0-4082-95d0-9abb83a20c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20385
96447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2038596447
Directory /workspace/6.usbdev_stall_trans/latest


Test location /workspace/coverage/default/6.usbdev_stream_len_max.1252521277
Short name T1212
Test name
Test status
Simulation time 501291690 ps
CPU time 1.52 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:09:55 PM PDT 24
Peak memory 207420 kb
Host smart-e3aee46b-2142-479b-9cee-2ade3a129aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12525
21277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1252521277
Directory /workspace/6.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/6.usbdev_streaming_out.3504955432
Short name T2458
Test name
Test status
Simulation time 1889217380 ps
CPU time 15.11 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:10:08 PM PDT 24
Peak memory 217376 kb
Host smart-869685c8-1be7-4fb8-978f-0e0c575e7505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35049
55432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3504955432
Directory /workspace/6.usbdev_streaming_out/latest


Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.3416480590
Short name T845
Test name
Test status
Simulation time 2028850763 ps
CPU time 18.48 seconds
Started Aug 11 07:09:46 PM PDT 24
Finished Aug 11 07:10:04 PM PDT 24
Peak memory 207648 kb
Host smart-d5adbdf8-884c-4b15-89e9-9cfb2d2713a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416480590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.3416480590
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/6.usbdev_tx_rx_disruption.238229461
Short name T848
Test name
Test status
Simulation time 406510038 ps
CPU time 1.3 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:09:52 PM PDT 24
Peak memory 207564 kb
Host smart-21173f46-8bf8-4e4b-bd4b-1caa846b2c9c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238229461 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.usbdev_tx_rx_disruption.238229461
Directory /workspace/6.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/60.usbdev_endpoint_types.3032089742
Short name T2740
Test name
Test status
Simulation time 262254516 ps
CPU time 1.16 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207488 kb
Host smart-e73d6b1e-9147-4fe2-887e-62a991a7d859
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3032089742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.3032089742
Directory /workspace/60.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/60.usbdev_tx_rx_disruption.1707135122
Short name T1628
Test name
Test status
Simulation time 662586681 ps
CPU time 1.86 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207568 kb
Host smart-acc16c9e-a135-4617-91ad-74555e70780a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707135122 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.usbdev_tx_rx_disruption.1707135122
Directory /workspace/60.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/61.usbdev_endpoint_types.3595687287
Short name T463
Test name
Test status
Simulation time 738037462 ps
CPU time 1.88 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207568 kb
Host smart-e3405514-c586-4008-9c45-21f1c864f484
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3595687287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.3595687287
Directory /workspace/61.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/61.usbdev_tx_rx_disruption.3799109531
Short name T1655
Test name
Test status
Simulation time 500599897 ps
CPU time 1.5 seconds
Started Aug 11 07:16:45 PM PDT 24
Finished Aug 11 07:16:47 PM PDT 24
Peak memory 207516 kb
Host smart-45e093f8-d157-4043-bb5e-a2267351b070
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799109531 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.usbdev_tx_rx_disruption.3799109531
Directory /workspace/61.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/62.usbdev_endpoint_types.3970048536
Short name T1933
Test name
Test status
Simulation time 276130663 ps
CPU time 1.17 seconds
Started Aug 11 07:16:43 PM PDT 24
Finished Aug 11 07:16:45 PM PDT 24
Peak memory 207400 kb
Host smart-2e44cc43-68f2-4a52-95e0-53301950f8ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3970048536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.3970048536
Directory /workspace/62.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/62.usbdev_tx_rx_disruption.2175884253
Short name T564
Test name
Test status
Simulation time 511473390 ps
CPU time 1.5 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 207540 kb
Host smart-826c1887-a1cf-44ed-8991-a3d76beb1a00
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175884253 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.usbdev_tx_rx_disruption.2175884253
Directory /workspace/62.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/63.usbdev_endpoint_types.717725708
Short name T408
Test name
Test status
Simulation time 332735996 ps
CPU time 1.22 seconds
Started Aug 11 07:16:47 PM PDT 24
Finished Aug 11 07:16:48 PM PDT 24
Peak memory 207416 kb
Host smart-2b31774e-0a35-49c1-8593-4940d65fe164
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=717725708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.717725708
Directory /workspace/63.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/63.usbdev_tx_rx_disruption.4238785864
Short name T1677
Test name
Test status
Simulation time 476373668 ps
CPU time 1.53 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207540 kb
Host smart-949104e2-a6bf-40fe-bae8-26ad85a59eae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238785864 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.usbdev_tx_rx_disruption.4238785864
Directory /workspace/63.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/64.usbdev_endpoint_types.3411066185
Short name T440
Test name
Test status
Simulation time 299137348 ps
CPU time 1.02 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207516 kb
Host smart-1ebaa72e-43f6-4d6a-b7c8-0096ef399958
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3411066185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.3411066185
Directory /workspace/64.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/64.usbdev_tx_rx_disruption.757942961
Short name T646
Test name
Test status
Simulation time 530113663 ps
CPU time 1.71 seconds
Started Aug 11 07:16:39 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207772 kb
Host smart-64b3950f-e23f-4fe2-9a7c-58df99be9319
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757942961 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 64.usbdev_tx_rx_disruption.757942961
Directory /workspace/64.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/65.usbdev_endpoint_types.2289992295
Short name T1640
Test name
Test status
Simulation time 407980575 ps
CPU time 1.26 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207560 kb
Host smart-d8d60678-0d2c-4f59-a160-c9ca3079af5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2289992295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.2289992295
Directory /workspace/65.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/65.usbdev_tx_rx_disruption.2588266700
Short name T2726
Test name
Test status
Simulation time 570147527 ps
CPU time 1.48 seconds
Started Aug 11 07:16:44 PM PDT 24
Finished Aug 11 07:16:46 PM PDT 24
Peak memory 207484 kb
Host smart-a7cd99b0-6570-401e-a5ce-8cbe1d035f43
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588266700 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.usbdev_tx_rx_disruption.2588266700
Directory /workspace/65.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/66.usbdev_tx_rx_disruption.4036376384
Short name T1237
Test name
Test status
Simulation time 482626448 ps
CPU time 1.48 seconds
Started Aug 11 07:16:42 PM PDT 24
Finished Aug 11 07:16:43 PM PDT 24
Peak memory 207548 kb
Host smart-dfffbc54-bec0-40dd-a127-6e2dbaf57666
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036376384 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.usbdev_tx_rx_disruption.4036376384
Directory /workspace/66.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/67.usbdev_tx_rx_disruption.2979732262
Short name T3584
Test name
Test status
Simulation time 474953983 ps
CPU time 1.47 seconds
Started Aug 11 07:16:42 PM PDT 24
Finished Aug 11 07:16:44 PM PDT 24
Peak memory 207532 kb
Host smart-80b6ff00-dd14-40da-8ce1-d6c5017a67df
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979732262 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.usbdev_tx_rx_disruption.2979732262
Directory /workspace/67.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/68.usbdev_endpoint_types.1810825176
Short name T2760
Test name
Test status
Simulation time 176596790 ps
CPU time 0.87 seconds
Started Aug 11 07:16:57 PM PDT 24
Finished Aug 11 07:16:58 PM PDT 24
Peak memory 207536 kb
Host smart-4e7ac14c-e066-408a-872f-9f8c97d112c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1810825176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.1810825176
Directory /workspace/68.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/68.usbdev_tx_rx_disruption.3554416135
Short name T3356
Test name
Test status
Simulation time 561176171 ps
CPU time 1.72 seconds
Started Aug 11 07:16:48 PM PDT 24
Finished Aug 11 07:16:50 PM PDT 24
Peak memory 207496 kb
Host smart-04d579b2-f198-46bd-83f1-37e5692aa841
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554416135 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.usbdev_tx_rx_disruption.3554416135
Directory /workspace/68.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/69.usbdev_endpoint_types.2427581493
Short name T494
Test name
Test status
Simulation time 301654033 ps
CPU time 1.13 seconds
Started Aug 11 07:16:51 PM PDT 24
Finished Aug 11 07:16:52 PM PDT 24
Peak memory 207536 kb
Host smart-3a1a82e2-950c-4a46-82cd-fb5fcd3121f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2427581493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.2427581493
Directory /workspace/69.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/69.usbdev_tx_rx_disruption.1107484336
Short name T1010
Test name
Test status
Simulation time 646750737 ps
CPU time 1.75 seconds
Started Aug 11 07:16:41 PM PDT 24
Finished Aug 11 07:16:43 PM PDT 24
Peak memory 207496 kb
Host smart-8f94aa2a-6485-46a8-8547-978b183b63bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107484336 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.usbdev_tx_rx_disruption.1107484336
Directory /workspace/69.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/7.usbdev_alert_test.81442999
Short name T986
Test name
Test status
Simulation time 63517732 ps
CPU time 0.67 seconds
Started Aug 11 07:10:13 PM PDT 24
Finished Aug 11 07:10:14 PM PDT 24
Peak memory 207576 kb
Host smart-fa5ff19c-657b-40df-a5c5-804f1d7807fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=81442999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.81442999
Directory /workspace/7.usbdev_alert_test/latest


Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1925881702
Short name T1852
Test name
Test status
Simulation time 12091442129 ps
CPU time 15.12 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:10:06 PM PDT 24
Peak memory 207772 kb
Host smart-c3abe669-8dc0-4e63-8345-9d26cb22dfd5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925881702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.1925881702
Directory /workspace/7.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3960897508
Short name T1156
Test name
Test status
Simulation time 14380427066 ps
CPU time 18.12 seconds
Started Aug 11 07:09:52 PM PDT 24
Finished Aug 11 07:10:10 PM PDT 24
Peak memory 215940 kb
Host smart-1abb408b-d190-4622-8861-d7b56c240e85
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960897508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3960897508
Directory /workspace/7.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3829362118
Short name T1056
Test name
Test status
Simulation time 25442954599 ps
CPU time 30.89 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:10:22 PM PDT 24
Peak memory 216028 kb
Host smart-e20e0d55-1885-41c5-a7ef-d5f1c2f430da
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829362118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.3829362118
Directory /workspace/7.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/7.usbdev_av_buffer.4155202020
Short name T2461
Test name
Test status
Simulation time 150342006 ps
CPU time 0.92 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:09:54 PM PDT 24
Peak memory 207572 kb
Host smart-dbb742a3-e0b3-4751-b52f-f048eb28dd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41552
02020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.4155202020
Directory /workspace/7.usbdev_av_buffer/latest


Test location /workspace/coverage/default/7.usbdev_bitstuff_err.843745180
Short name T772
Test name
Test status
Simulation time 182354607 ps
CPU time 0.84 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:09:55 PM PDT 24
Peak memory 207412 kb
Host smart-946a70c5-0d23-49b0-b971-0cf5151b48a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84374
5180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.843745180
Directory /workspace/7.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2240735469
Short name T2720
Test name
Test status
Simulation time 351688799 ps
CPU time 1.39 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:09:53 PM PDT 24
Peak memory 207572 kb
Host smart-cef88a55-d10b-42f7-93bf-31da363cbe54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407
35469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2240735469
Directory /workspace/7.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/7.usbdev_device_address.2409802771
Short name T3447
Test name
Test status
Simulation time 35341975525 ps
CPU time 57.12 seconds
Started Aug 11 07:09:51 PM PDT 24
Finished Aug 11 07:10:49 PM PDT 24
Peak memory 207764 kb
Host smart-8ad61206-f954-4ca3-bcea-8d56ec9a09f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24098
02771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2409802771
Directory /workspace/7.usbdev_device_address/latest


Test location /workspace/coverage/default/7.usbdev_device_timeout.2854787728
Short name T2128
Test name
Test status
Simulation time 311421578 ps
CPU time 4.42 seconds
Started Aug 11 07:09:54 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207720 kb
Host smart-6eba57d9-34e7-45b3-8f83-2521803b5be5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854787728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2854787728
Directory /workspace/7.usbdev_device_timeout/latest


Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2744393689
Short name T1267
Test name
Test status
Simulation time 677228806 ps
CPU time 1.79 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:09:56 PM PDT 24
Peak memory 207524 kb
Host smart-aff7389c-fdb3-4255-b8dd-7a96c4959e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27443
93689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2744393689
Directory /workspace/7.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/7.usbdev_disconnected.1237627961
Short name T1886
Test name
Test status
Simulation time 145973849 ps
CPU time 0.86 seconds
Started Aug 11 07:09:50 PM PDT 24
Finished Aug 11 07:09:52 PM PDT 24
Peak memory 207472 kb
Host smart-7def2a48-d273-4694-aaee-e026833ad8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12376
27961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1237627961
Directory /workspace/7.usbdev_disconnected/latest


Test location /workspace/coverage/default/7.usbdev_enable.124831298
Short name T276
Test name
Test status
Simulation time 42328319 ps
CPU time 0.71 seconds
Started Aug 11 07:09:54 PM PDT 24
Finished Aug 11 07:09:55 PM PDT 24
Peak memory 207496 kb
Host smart-37fc9b7f-f382-41c0-9a8b-bfa0a96539e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12483
1298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.124831298
Directory /workspace/7.usbdev_enable/latest


Test location /workspace/coverage/default/7.usbdev_endpoint_access.1273415413
Short name T3592
Test name
Test status
Simulation time 921696883 ps
CPU time 2.4 seconds
Started Aug 11 07:09:55 PM PDT 24
Finished Aug 11 07:09:57 PM PDT 24
Peak memory 207740 kb
Host smart-a8539301-3895-4675-a9c7-f8dd37102d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12734
15413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1273415413
Directory /workspace/7.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/7.usbdev_endpoint_types.1593834425
Short name T537
Test name
Test status
Simulation time 259479680 ps
CPU time 1.07 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:09:54 PM PDT 24
Peak memory 207412 kb
Host smart-f5806642-6213-4dd6-ad13-d02d5b239502
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1593834425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.1593834425
Directory /workspace/7.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/7.usbdev_fifo_rst.3104350891
Short name T3244
Test name
Test status
Simulation time 171824982 ps
CPU time 1.98 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:09:55 PM PDT 24
Peak memory 207680 kb
Host smart-36597709-5cf2-4b2c-94a6-dd246b96efea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31043
50891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3104350891
Directory /workspace/7.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/7.usbdev_in_iso.897599955
Short name T1638
Test name
Test status
Simulation time 172429530 ps
CPU time 0.95 seconds
Started Aug 11 07:09:55 PM PDT 24
Finished Aug 11 07:09:56 PM PDT 24
Peak memory 207520 kb
Host smart-dbda0b83-36f1-4058-97e4-504eceac60bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=897599955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.897599955
Directory /workspace/7.usbdev_in_iso/latest


Test location /workspace/coverage/default/7.usbdev_in_stall.3209993093
Short name T3018
Test name
Test status
Simulation time 196551601 ps
CPU time 0.88 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:09:54 PM PDT 24
Peak memory 207464 kb
Host smart-beb60883-dac5-430c-8138-e9dcd06cbf2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32099
93093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3209993093
Directory /workspace/7.usbdev_in_stall/latest


Test location /workspace/coverage/default/7.usbdev_in_trans.2721367945
Short name T3609
Test name
Test status
Simulation time 258614510 ps
CPU time 1.05 seconds
Started Aug 11 07:09:54 PM PDT 24
Finished Aug 11 07:09:55 PM PDT 24
Peak memory 207552 kb
Host smart-9223549d-bdac-49c9-96d4-d8d1857d4c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27213
67945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2721367945
Directory /workspace/7.usbdev_in_trans/latest


Test location /workspace/coverage/default/7.usbdev_invalid_sync.466027213
Short name T3440
Test name
Test status
Simulation time 3679238776 ps
CPU time 110.79 seconds
Started Aug 11 07:09:54 PM PDT 24
Finished Aug 11 07:11:45 PM PDT 24
Peak memory 216028 kb
Host smart-f27138e2-0fcc-4b23-b987-b8641569a533
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=466027213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.466027213
Directory /workspace/7.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/7.usbdev_iso_retraction.1166169738
Short name T2735
Test name
Test status
Simulation time 5866684610 ps
CPU time 38.78 seconds
Started Aug 11 07:09:52 PM PDT 24
Finished Aug 11 07:10:31 PM PDT 24
Peak memory 207808 kb
Host smart-01fb7e60-ab56-4b23-9d14-a0166f821b4e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1166169738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.1166169738
Directory /workspace/7.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/7.usbdev_link_in_err.2261514444
Short name T2491
Test name
Test status
Simulation time 195481174 ps
CPU time 0.88 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 207548 kb
Host smart-9216c2d8-b660-427c-9365-1e7e4c22cd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22615
14444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2261514444
Directory /workspace/7.usbdev_link_in_err/latest


Test location /workspace/coverage/default/7.usbdev_link_resume.826456414
Short name T1135
Test name
Test status
Simulation time 12503742224 ps
CPU time 16.09 seconds
Started Aug 11 07:10:03 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207772 kb
Host smart-0f116d12-bad6-47ec-9e89-e6bcfd7796ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82645
6414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.826456414
Directory /workspace/7.usbdev_link_resume/latest


Test location /workspace/coverage/default/7.usbdev_link_suspend.2164774657
Short name T1299
Test name
Test status
Simulation time 8336444863 ps
CPU time 11.16 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:11 PM PDT 24
Peak memory 207864 kb
Host smart-4dc6084b-ab80-4a3e-b8c7-a98a61a4365b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21647
74657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2164774657
Directory /workspace/7.usbdev_link_suspend/latest


Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1789865427
Short name T2046
Test name
Test status
Simulation time 4660374727 ps
CPU time 50.29 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:50 PM PDT 24
Peak memory 219172 kb
Host smart-24f58c4b-0e8a-4dfd-b4f3-651280335437
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1789865427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1789865427
Directory /workspace/7.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.1904655917
Short name T712
Test name
Test status
Simulation time 3450365444 ps
CPU time 25.75 seconds
Started Aug 11 07:09:58 PM PDT 24
Finished Aug 11 07:10:23 PM PDT 24
Peak memory 217716 kb
Host smart-76bd7153-08fc-4be3-a642-054181af41e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1904655917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.1904655917
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2503690843
Short name T793
Test name
Test status
Simulation time 248804565 ps
CPU time 1.03 seconds
Started Aug 11 07:09:58 PM PDT 24
Finished Aug 11 07:09:59 PM PDT 24
Peak memory 207536 kb
Host smart-1dbf045b-5122-4697-8772-45932bdec0f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2503690843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2503690843
Directory /workspace/7.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.28573690
Short name T1402
Test name
Test status
Simulation time 229643546 ps
CPU time 0.95 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207464 kb
Host smart-5dbc52d6-d590-4326-bc21-6515e8ffa463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28573
690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.28573690
Directory /workspace/7.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.3414891745
Short name T1252
Test name
Test status
Simulation time 2517526112 ps
CPU time 18.47 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:10:16 PM PDT 24
Peak memory 224280 kb
Host smart-e29f2f8b-5941-4729-a560-d6d3971ac1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34148
91745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.3414891745
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.759114939
Short name T1731
Test name
Test status
Simulation time 2448869015 ps
CPU time 69.73 seconds
Started Aug 11 07:10:00 PM PDT 24
Finished Aug 11 07:11:10 PM PDT 24
Peak memory 224184 kb
Host smart-57472671-7926-421f-99d9-4492f94c5b8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=759114939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.759114939
Directory /workspace/7.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3796970132
Short name T2047
Test name
Test status
Simulation time 1491591652 ps
CPU time 40.19 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:40 PM PDT 24
Peak memory 215964 kb
Host smart-71611c32-09ff-444f-87f4-540b329175d1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3796970132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3796970132
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.409153273
Short name T748
Test name
Test status
Simulation time 156654377 ps
CPU time 0.84 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 207544 kb
Host smart-791b63ee-5322-4643-bd59-27918c3d3d06
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=409153273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.409153273
Directory /workspace/7.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4205752997
Short name T1548
Test name
Test status
Simulation time 181056923 ps
CPU time 0.85 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 207560 kb
Host smart-f8e301bc-cfb5-4fb4-9fc2-4dc3b5466ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42057
52997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4205752997
Directory /workspace/7.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_nak_trans.3057687029
Short name T1629
Test name
Test status
Simulation time 202929944 ps
CPU time 0.99 seconds
Started Aug 11 07:09:58 PM PDT 24
Finished Aug 11 07:09:59 PM PDT 24
Peak memory 207544 kb
Host smart-a2471e95-af5d-4753-870e-c4cc3c271b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30576
87029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3057687029
Directory /workspace/7.usbdev_nak_trans/latest


Test location /workspace/coverage/default/7.usbdev_out_iso.4169714111
Short name T2465
Test name
Test status
Simulation time 187770064 ps
CPU time 0.91 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 207548 kb
Host smart-ce151280-7b76-4856-a0b9-828a213128d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41697
14111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.4169714111
Directory /workspace/7.usbdev_out_iso/latest


Test location /workspace/coverage/default/7.usbdev_out_stall.3966141821
Short name T2273
Test name
Test status
Simulation time 255210030 ps
CPU time 0.99 seconds
Started Aug 11 07:09:58 PM PDT 24
Finished Aug 11 07:09:59 PM PDT 24
Peak memory 207484 kb
Host smart-f406aab6-d965-43ad-89b1-e11155680ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39661
41821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3966141821
Directory /workspace/7.usbdev_out_stall/latest


Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2978263856
Short name T1862
Test name
Test status
Simulation time 156961253 ps
CPU time 0.88 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 207572 kb
Host smart-3bf44809-e540-4220-8daf-5cba4e2677e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29782
63856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2978263856
Directory /workspace/7.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1879181198
Short name T2063
Test name
Test status
Simulation time 149221691 ps
CPU time 0.81 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207580 kb
Host smart-47c1f17c-d667-4146-a2e3-d7e16239367f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18791
81198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1879181198
Directory /workspace/7.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2577117941
Short name T822
Test name
Test status
Simulation time 219512562 ps
CPU time 1.07 seconds
Started Aug 11 07:09:58 PM PDT 24
Finished Aug 11 07:10:00 PM PDT 24
Peak memory 207536 kb
Host smart-9d8b30a5-edae-4bf1-9471-68f49cce747b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2577117941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2577117941
Directory /workspace/7.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1223860956
Short name T2029
Test name
Test status
Simulation time 144563295 ps
CPU time 0.83 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207556 kb
Host smart-e3af095d-f693-40c8-9076-81a237962d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12238
60956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1223860956
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.382316237
Short name T43
Test name
Test status
Simulation time 74197155 ps
CPU time 0.74 seconds
Started Aug 11 07:10:00 PM PDT 24
Finished Aug 11 07:10:01 PM PDT 24
Peak memory 207444 kb
Host smart-5765b3e9-379a-4326-bde6-a91041c46b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38231
6237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.382316237
Directory /workspace/7.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1012175702
Short name T872
Test name
Test status
Simulation time 12210614878 ps
CPU time 31.06 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:30 PM PDT 24
Peak memory 216000 kb
Host smart-a3eb7320-2497-4a35-8bb7-c8577598c834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10121
75702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1012175702
Directory /workspace/7.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/7.usbdev_pkt_received.3925852806
Short name T2900
Test name
Test status
Simulation time 188189223 ps
CPU time 0.99 seconds
Started Aug 11 07:10:02 PM PDT 24
Finished Aug 11 07:10:03 PM PDT 24
Peak memory 207480 kb
Host smart-d9ebea5a-dd06-4b18-b00c-0b53275c55a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39258
52806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3925852806
Directory /workspace/7.usbdev_pkt_received/latest


Test location /workspace/coverage/default/7.usbdev_pkt_sent.4073544865
Short name T398
Test name
Test status
Simulation time 257645044 ps
CPU time 0.99 seconds
Started Aug 11 07:09:57 PM PDT 24
Finished Aug 11 07:09:58 PM PDT 24
Peak memory 207568 kb
Host smart-3d729fd4-02fd-4005-b281-5222e3aa25b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40735
44865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4073544865
Directory /workspace/7.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3946456000
Short name T3573
Test name
Test status
Simulation time 7438038786 ps
CPU time 102.87 seconds
Started Aug 11 07:09:58 PM PDT 24
Finished Aug 11 07:11:41 PM PDT 24
Peak memory 216076 kb
Host smart-3ad33547-206c-45c1-86c0-5dcc0486bc96
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946456000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3946456000
Directory /workspace/7.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.4112811600
Short name T2227
Test name
Test status
Simulation time 3731173921 ps
CPU time 34.71 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:34 PM PDT 24
Peak memory 218568 kb
Host smart-fccdcb1c-98c4-4794-a08b-b3e55f6c35db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4112811600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.4112811600
Directory /workspace/7.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/7.usbdev_rand_suspends.1556406019
Short name T59
Test name
Test status
Simulation time 6525477426 ps
CPU time 30.14 seconds
Started Aug 11 07:10:03 PM PDT 24
Finished Aug 11 07:10:33 PM PDT 24
Peak memory 216176 kb
Host smart-f16fd3b0-85c1-48cb-908b-5550d9c51d2e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556406019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1556406019
Directory /workspace/7.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.675299168
Short name T242
Test name
Test status
Simulation time 173631436 ps
CPU time 0.96 seconds
Started Aug 11 07:10:02 PM PDT 24
Finished Aug 11 07:10:03 PM PDT 24
Peak memory 207480 kb
Host smart-b5c99eb9-1b5c-49d0-8653-bd4f3cc630c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67529
9168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.675299168
Directory /workspace/7.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2861561506
Short name T2804
Test name
Test status
Simulation time 253950712 ps
CPU time 0.97 seconds
Started Aug 11 07:09:59 PM PDT 24
Finished Aug 11 07:10:01 PM PDT 24
Peak memory 207576 kb
Host smart-5d105589-f1f0-488d-8550-adcaa91ac758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28615
61506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2861561506
Directory /workspace/7.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_resume_link_active.2943090015
Short name T120
Test name
Test status
Simulation time 20216721600 ps
CPU time 25.12 seconds
Started Aug 11 07:10:02 PM PDT 24
Finished Aug 11 07:10:27 PM PDT 24
Peak memory 207652 kb
Host smart-5381e4fe-206d-4ddc-ada2-26fbd2f0f417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29430
90015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.2943090015
Directory /workspace/7.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/7.usbdev_rx_crc_err.843533100
Short name T78
Test name
Test status
Simulation time 133618825 ps
CPU time 0.85 seconds
Started Aug 11 07:10:02 PM PDT 24
Finished Aug 11 07:10:03 PM PDT 24
Peak memory 207520 kb
Host smart-2fa9f5a9-b719-4d44-8e3b-8987b26bea84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84353
3100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.843533100
Directory /workspace/7.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/7.usbdev_rx_full.1117678114
Short name T880
Test name
Test status
Simulation time 267958247 ps
CPU time 1.09 seconds
Started Aug 11 07:10:03 PM PDT 24
Finished Aug 11 07:10:04 PM PDT 24
Peak memory 207528 kb
Host smart-c808e620-ab24-4e5e-8677-d6bb91771ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
78114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.1117678114
Directory /workspace/7.usbdev_rx_full/latest


Test location /workspace/coverage/default/7.usbdev_setup_stage.418865334
Short name T3306
Test name
Test status
Simulation time 153193709 ps
CPU time 0.84 seconds
Started Aug 11 07:10:05 PM PDT 24
Finished Aug 11 07:10:05 PM PDT 24
Peak memory 207552 kb
Host smart-e553348e-ae43-4178-8bae-79bba8e7fcbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886
5334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.418865334
Directory /workspace/7.usbdev_setup_stage/latest


Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3209108576
Short name T697
Test name
Test status
Simulation time 154161672 ps
CPU time 0.82 seconds
Started Aug 11 07:10:04 PM PDT 24
Finished Aug 11 07:10:04 PM PDT 24
Peak memory 207520 kb
Host smart-3688daf0-be7c-4ca3-9173-dbdaa2962b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32091
08576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3209108576
Directory /workspace/7.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/7.usbdev_smoke.2835729559
Short name T3517
Test name
Test status
Simulation time 210987795 ps
CPU time 1.02 seconds
Started Aug 11 07:10:05 PM PDT 24
Finished Aug 11 07:10:06 PM PDT 24
Peak memory 207540 kb
Host smart-3c836201-8e18-4230-9347-8c2e44bf4829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28357
29559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2835729559
Directory /workspace/7.usbdev_smoke/latest


Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1445373395
Short name T2948
Test name
Test status
Simulation time 2389038535 ps
CPU time 18.63 seconds
Started Aug 11 07:10:13 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 224268 kb
Host smart-594685fb-5176-43a1-b283-e096d7614203
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1445373395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1445373395
Directory /workspace/7.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.387465983
Short name T3099
Test name
Test status
Simulation time 189381952 ps
CPU time 0.91 seconds
Started Aug 11 07:10:03 PM PDT 24
Finished Aug 11 07:10:04 PM PDT 24
Peak memory 207564 kb
Host smart-ff976ffa-9242-4623-93dd-ceb3f5a44311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38746
5983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.387465983
Directory /workspace/7.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/7.usbdev_stall_trans.4280980890
Short name T1516
Test name
Test status
Simulation time 179655738 ps
CPU time 0.91 seconds
Started Aug 11 07:10:02 PM PDT 24
Finished Aug 11 07:10:03 PM PDT 24
Peak memory 207568 kb
Host smart-25979403-2ceb-4489-b001-b7e5dc75245a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42809
80890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4280980890
Directory /workspace/7.usbdev_stall_trans/latest


Test location /workspace/coverage/default/7.usbdev_stream_len_max.1783925006
Short name T1830
Test name
Test status
Simulation time 1152294374 ps
CPU time 2.73 seconds
Started Aug 11 07:10:04 PM PDT 24
Finished Aug 11 07:10:07 PM PDT 24
Peak memory 207624 kb
Host smart-30cb1cc6-920f-491a-84eb-80a2f9115ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17839
25006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.1783925006
Directory /workspace/7.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/7.usbdev_streaming_out.1107934228
Short name T2627
Test name
Test status
Simulation time 3998367837 ps
CPU time 116.98 seconds
Started Aug 11 07:10:04 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 216108 kb
Host smart-54d90e82-29da-4d36-97b3-9792404e7b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11079
34228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1107934228
Directory /workspace/7.usbdev_streaming_out/latest


Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.2772991530
Short name T1303
Test name
Test status
Simulation time 5714282683 ps
CPU time 35.79 seconds
Started Aug 11 07:09:53 PM PDT 24
Finished Aug 11 07:10:30 PM PDT 24
Peak memory 207768 kb
Host smart-0e18fd6d-236a-489f-b3d8-7c86785556f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772991530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.2772991530
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/7.usbdev_tx_rx_disruption.1906892986
Short name T1046
Test name
Test status
Simulation time 533911626 ps
CPU time 1.59 seconds
Started Aug 11 07:10:04 PM PDT 24
Finished Aug 11 07:10:06 PM PDT 24
Peak memory 207468 kb
Host smart-e4ea63bb-2d98-4331-99ca-0d5439863b85
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906892986 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.usbdev_tx_rx_disruption.1906892986
Directory /workspace/7.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/70.usbdev_endpoint_types.813024143
Short name T152
Test name
Test status
Simulation time 249668393 ps
CPU time 1.02 seconds
Started Aug 11 07:16:45 PM PDT 24
Finished Aug 11 07:16:46 PM PDT 24
Peak memory 207484 kb
Host smart-f8e5fb9f-2033-44f8-9aba-9bac9a2ce8a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=813024143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.813024143
Directory /workspace/70.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/70.usbdev_tx_rx_disruption.1734383728
Short name T1881
Test name
Test status
Simulation time 571478114 ps
CPU time 1.69 seconds
Started Aug 11 07:17:02 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207568 kb
Host smart-c3d8b1c0-93e1-45bc-9714-a94629e253e2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734383728 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.usbdev_tx_rx_disruption.1734383728
Directory /workspace/70.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/71.usbdev_endpoint_types.912672458
Short name T2538
Test name
Test status
Simulation time 458612042 ps
CPU time 1.51 seconds
Started Aug 11 07:16:41 PM PDT 24
Finished Aug 11 07:16:43 PM PDT 24
Peak memory 207512 kb
Host smart-ad21de05-5a8e-4ca2-90ad-7b417417d0a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=912672458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.912672458
Directory /workspace/71.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/71.usbdev_tx_rx_disruption.737033175
Short name T2469
Test name
Test status
Simulation time 592213325 ps
CPU time 1.59 seconds
Started Aug 11 07:16:47 PM PDT 24
Finished Aug 11 07:16:49 PM PDT 24
Peak memory 207572 kb
Host smart-8353b85f-37ef-4505-89de-ef8b68570925
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737033175 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 71.usbdev_tx_rx_disruption.737033175
Directory /workspace/71.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/72.usbdev_endpoint_types.2717418011
Short name T433
Test name
Test status
Simulation time 387657010 ps
CPU time 1.3 seconds
Started Aug 11 07:16:47 PM PDT 24
Finished Aug 11 07:16:49 PM PDT 24
Peak memory 207516 kb
Host smart-6d1ea57e-166c-4120-b294-1a757b060b50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2717418011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.2717418011
Directory /workspace/72.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/72.usbdev_tx_rx_disruption.3426232827
Short name T2596
Test name
Test status
Simulation time 554877098 ps
CPU time 1.86 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 207592 kb
Host smart-b44068a9-35ec-4c87-88b9-060cf201e7f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426232827 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.usbdev_tx_rx_disruption.3426232827
Directory /workspace/72.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/73.usbdev_endpoint_types.1759745871
Short name T518
Test name
Test status
Simulation time 270161372 ps
CPU time 1.16 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207504 kb
Host smart-dae58062-050b-47ea-85f7-95959f5eaafe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1759745871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.1759745871
Directory /workspace/73.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/73.usbdev_tx_rx_disruption.834872564
Short name T1432
Test name
Test status
Simulation time 479344391 ps
CPU time 1.48 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:46 PM PDT 24
Peak memory 207516 kb
Host smart-56672d86-1d49-49ab-abbb-87df5c621a6d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834872564 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 73.usbdev_tx_rx_disruption.834872564
Directory /workspace/73.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/74.usbdev_tx_rx_disruption.896023596
Short name T1870
Test name
Test status
Simulation time 641708843 ps
CPU time 1.68 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:42 PM PDT 24
Peak memory 207592 kb
Host smart-fa1a4d39-50fc-4799-80e0-5be5f66d9a91
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896023596 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 74.usbdev_tx_rx_disruption.896023596
Directory /workspace/74.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/75.usbdev_endpoint_types.3013592230
Short name T510
Test name
Test status
Simulation time 306270121 ps
CPU time 1.16 seconds
Started Aug 11 07:16:57 PM PDT 24
Finished Aug 11 07:16:58 PM PDT 24
Peak memory 207512 kb
Host smart-756e2d7e-54cb-40a8-85e0-844781ef6411
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3013592230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.3013592230
Directory /workspace/75.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/75.usbdev_tx_rx_disruption.1490428792
Short name T2919
Test name
Test status
Simulation time 544981285 ps
CPU time 1.59 seconds
Started Aug 11 07:16:37 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207536 kb
Host smart-4f47911b-2fdb-41ab-88ef-778118524f55
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490428792 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.usbdev_tx_rx_disruption.1490428792
Directory /workspace/75.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/76.usbdev_tx_rx_disruption.2560175532
Short name T2874
Test name
Test status
Simulation time 507163711 ps
CPU time 1.59 seconds
Started Aug 11 07:16:46 PM PDT 24
Finished Aug 11 07:16:48 PM PDT 24
Peak memory 207560 kb
Host smart-e3c018d7-3f5b-424c-8ad7-63612884f334
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560175532 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.usbdev_tx_rx_disruption.2560175532
Directory /workspace/76.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/77.usbdev_endpoint_types.84155726
Short name T410
Test name
Test status
Simulation time 342498752 ps
CPU time 1.15 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207548 kb
Host smart-ce20ac68-9969-4184-966f-f7210d8e1ea5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=84155726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.84155726
Directory /workspace/77.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/77.usbdev_tx_rx_disruption.3890714041
Short name T906
Test name
Test status
Simulation time 439325267 ps
CPU time 1.41 seconds
Started Aug 11 07:16:50 PM PDT 24
Finished Aug 11 07:16:52 PM PDT 24
Peak memory 207536 kb
Host smart-b7515159-2652-4519-81cf-de9933db86b4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890714041 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.usbdev_tx_rx_disruption.3890714041
Directory /workspace/77.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/78.usbdev_endpoint_types.4130273915
Short name T527
Test name
Test status
Simulation time 441409229 ps
CPU time 1.34 seconds
Started Aug 11 07:16:40 PM PDT 24
Finished Aug 11 07:16:41 PM PDT 24
Peak memory 207484 kb
Host smart-7bfaa233-9887-410f-ab1d-b5b169fa0d76
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4130273915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.4130273915
Directory /workspace/78.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/78.usbdev_tx_rx_disruption.2719245617
Short name T2147
Test name
Test status
Simulation time 539560365 ps
CPU time 1.66 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207600 kb
Host smart-b2d0e0af-e8ba-4208-9579-b43d77a731ca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719245617 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.usbdev_tx_rx_disruption.2719245617
Directory /workspace/78.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/79.usbdev_endpoint_types.3754619074
Short name T465
Test name
Test status
Simulation time 693966943 ps
CPU time 1.76 seconds
Started Aug 11 07:17:10 PM PDT 24
Finished Aug 11 07:17:12 PM PDT 24
Peak memory 207400 kb
Host smart-f2d58a23-2c03-4d96-bbef-65103628bd07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3754619074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.3754619074
Directory /workspace/79.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/79.usbdev_tx_rx_disruption.2643393347
Short name T3320
Test name
Test status
Simulation time 469410159 ps
CPU time 1.46 seconds
Started Aug 11 07:16:50 PM PDT 24
Finished Aug 11 07:16:51 PM PDT 24
Peak memory 207576 kb
Host smart-dd7e088a-4b9b-45c2-812b-eece8c334215
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643393347 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.usbdev_tx_rx_disruption.2643393347
Directory /workspace/79.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/8.usbdev_alert_test.2790930045
Short name T1910
Test name
Test status
Simulation time 53929835 ps
CPU time 0.65 seconds
Started Aug 11 07:10:16 PM PDT 24
Finished Aug 11 07:10:17 PM PDT 24
Peak memory 207532 kb
Host smart-3994bb20-64e6-4107-962d-d02058b0a4c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2790930045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2790930045
Directory /workspace/8.usbdev_alert_test/latest


Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3610558064
Short name T10
Test name
Test status
Simulation time 6051790401 ps
CPU time 8.84 seconds
Started Aug 11 07:10:13 PM PDT 24
Finished Aug 11 07:10:22 PM PDT 24
Peak memory 216024 kb
Host smart-ba9179a3-12de-42b1-83dd-e1dc8ad504d9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610558064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.3610558064
Directory /workspace/8.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.4093091043
Short name T1134
Test name
Test status
Simulation time 16453530223 ps
CPU time 19.09 seconds
Started Aug 11 07:10:13 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 216016 kb
Host smart-453bed51-2fee-4e87-a24b-2a7b7b117952
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093091043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.4093091043
Directory /workspace/8.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3223295922
Short name T2088
Test name
Test status
Simulation time 30324472151 ps
CPU time 36.08 seconds
Started Aug 11 07:10:06 PM PDT 24
Finished Aug 11 07:10:42 PM PDT 24
Peak memory 207836 kb
Host smart-83cf1c2f-c503-4783-b5c2-60fd6ff7b8df
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223295922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.3223295922
Directory /workspace/8.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/8.usbdev_av_buffer.4097467993
Short name T1147
Test name
Test status
Simulation time 150540540 ps
CPU time 0.86 seconds
Started Aug 11 07:10:04 PM PDT 24
Finished Aug 11 07:10:05 PM PDT 24
Peak memory 207580 kb
Host smart-9d41a902-64de-41f4-84aa-1bb93ff6f6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40974
67993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.4097467993
Directory /workspace/8.usbdev_av_buffer/latest


Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3377980223
Short name T1623
Test name
Test status
Simulation time 175182790 ps
CPU time 0.9 seconds
Started Aug 11 07:10:05 PM PDT 24
Finished Aug 11 07:10:06 PM PDT 24
Peak memory 207492 kb
Host smart-6ab6f30e-d04b-40fa-bb13-91898fa7856f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33779
80223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3377980223
Directory /workspace/8.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3056222826
Short name T771
Test name
Test status
Simulation time 288642392 ps
CPU time 1.19 seconds
Started Aug 11 07:10:04 PM PDT 24
Finished Aug 11 07:10:06 PM PDT 24
Peak memory 207748 kb
Host smart-79911628-8f14-4e26-9f3b-653c8afdfd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30562
22826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3056222826
Directory /workspace/8.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.4187897228
Short name T2669
Test name
Test status
Simulation time 369083955 ps
CPU time 1.35 seconds
Started Aug 11 07:10:03 PM PDT 24
Finished Aug 11 07:10:05 PM PDT 24
Peak memory 207588 kb
Host smart-4f6466c1-dbea-4024-86fe-d51e6bcd548d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4187897228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.4187897228
Directory /workspace/8.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/8.usbdev_device_address.3668366366
Short name T2510
Test name
Test status
Simulation time 32703641276 ps
CPU time 58.3 seconds
Started Aug 11 07:10:03 PM PDT 24
Finished Aug 11 07:11:02 PM PDT 24
Peak memory 207840 kb
Host smart-7dd7cebd-9168-4770-bfc1-525286cb55e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36683
66366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3668366366
Directory /workspace/8.usbdev_device_address/latest


Test location /workspace/coverage/default/8.usbdev_device_timeout.1273528808
Short name T3505
Test name
Test status
Simulation time 3593499289 ps
CPU time 22.61 seconds
Started Aug 11 07:10:13 PM PDT 24
Finished Aug 11 07:10:35 PM PDT 24
Peak memory 207696 kb
Host smart-3081f851-5357-4d91-9552-e5e0a630e72c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273528808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.1273528808
Directory /workspace/8.usbdev_device_timeout/latest


Test location /workspace/coverage/default/8.usbdev_disable_endpoint.3494395998
Short name T2172
Test name
Test status
Simulation time 1009297335 ps
CPU time 2.24 seconds
Started Aug 11 07:10:12 PM PDT 24
Finished Aug 11 07:10:15 PM PDT 24
Peak memory 207524 kb
Host smart-4c54e429-5a50-4425-b2f0-09d544f19394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34943
95998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.3494395998
Directory /workspace/8.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/8.usbdev_disconnected.751105196
Short name T1189
Test name
Test status
Simulation time 184094363 ps
CPU time 0.88 seconds
Started Aug 11 07:10:21 PM PDT 24
Finished Aug 11 07:10:22 PM PDT 24
Peak memory 207540 kb
Host smart-02b102b0-ed91-4d6c-b083-35fe78be1bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75110
5196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.751105196
Directory /workspace/8.usbdev_disconnected/latest


Test location /workspace/coverage/default/8.usbdev_enable.4035471735
Short name T808
Test name
Test status
Simulation time 89660463 ps
CPU time 0.75 seconds
Started Aug 11 07:10:09 PM PDT 24
Finished Aug 11 07:10:10 PM PDT 24
Peak memory 207448 kb
Host smart-f1f1c16f-83ca-44c0-8ac5-623ca9046551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40354
71735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.4035471735
Directory /workspace/8.usbdev_enable/latest


Test location /workspace/coverage/default/8.usbdev_endpoint_access.379081609
Short name T796
Test name
Test status
Simulation time 1004031458 ps
CPU time 2.61 seconds
Started Aug 11 07:10:22 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207792 kb
Host smart-2ecb2c34-e96d-4dac-93a2-50270949b1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37908
1609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.379081609
Directory /workspace/8.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/8.usbdev_endpoint_types.747754327
Short name T457
Test name
Test status
Simulation time 478553312 ps
CPU time 1.34 seconds
Started Aug 11 07:10:10 PM PDT 24
Finished Aug 11 07:10:11 PM PDT 24
Peak memory 207512 kb
Host smart-00c50edf-625c-4878-ac94-09073a275dba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=747754327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.747754327
Directory /workspace/8.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/8.usbdev_fifo_rst.3950868827
Short name T2188
Test name
Test status
Simulation time 170988437 ps
CPU time 1.76 seconds
Started Aug 11 07:10:11 PM PDT 24
Finished Aug 11 07:10:13 PM PDT 24
Peak memory 207716 kb
Host smart-a549442a-eb75-46df-8ef6-e0d2357369b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39508
68827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3950868827
Directory /workspace/8.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/8.usbdev_in_iso.3789692894
Short name T1540
Test name
Test status
Simulation time 219519766 ps
CPU time 1.14 seconds
Started Aug 11 07:10:11 PM PDT 24
Finished Aug 11 07:10:12 PM PDT 24
Peak memory 224104 kb
Host smart-63c3673e-9e50-4352-ba95-d206f79a907a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3789692894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3789692894
Directory /workspace/8.usbdev_in_iso/latest


Test location /workspace/coverage/default/8.usbdev_in_stall.2007585738
Short name T788
Test name
Test status
Simulation time 139445368 ps
CPU time 0.84 seconds
Started Aug 11 07:10:22 PM PDT 24
Finished Aug 11 07:10:23 PM PDT 24
Peak memory 207540 kb
Host smart-6e3248cf-6f36-481c-a65b-3033fb278daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20075
85738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2007585738
Directory /workspace/8.usbdev_in_stall/latest


Test location /workspace/coverage/default/8.usbdev_in_trans.3163552604
Short name T1765
Test name
Test status
Simulation time 188243847 ps
CPU time 0.98 seconds
Started Aug 11 07:10:12 PM PDT 24
Finished Aug 11 07:10:13 PM PDT 24
Peak memory 207556 kb
Host smart-cd7d55ef-215f-404a-b146-e56e26ab95ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31635
52604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3163552604
Directory /workspace/8.usbdev_in_trans/latest


Test location /workspace/coverage/default/8.usbdev_invalid_sync.103590357
Short name T125
Test name
Test status
Simulation time 3730768440 ps
CPU time 107.9 seconds
Started Aug 11 07:10:13 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 224172 kb
Host smart-96d307ef-3347-45b8-9409-5686660e6654
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=103590357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.103590357
Directory /workspace/8.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/8.usbdev_iso_retraction.3542691380
Short name T3522
Test name
Test status
Simulation time 15368527830 ps
CPU time 98.41 seconds
Started Aug 11 07:10:09 PM PDT 24
Finished Aug 11 07:11:48 PM PDT 24
Peak memory 207748 kb
Host smart-d0ad0986-ceec-4984-aa29-7d02b66f9e60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3542691380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.3542691380
Directory /workspace/8.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/8.usbdev_link_in_err.819519327
Short name T100
Test name
Test status
Simulation time 205025470 ps
CPU time 0.99 seconds
Started Aug 11 07:10:09 PM PDT 24
Finished Aug 11 07:10:10 PM PDT 24
Peak memory 207572 kb
Host smart-7a30cbf6-78d7-4731-9df9-783607648186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81951
9327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.819519327
Directory /workspace/8.usbdev_link_in_err/latest


Test location /workspace/coverage/default/8.usbdev_link_resume.3670871734
Short name T2191
Test name
Test status
Simulation time 13973816917 ps
CPU time 19.38 seconds
Started Aug 11 07:10:10 PM PDT 24
Finished Aug 11 07:10:30 PM PDT 24
Peak memory 207848 kb
Host smart-d1451616-4b59-489f-85eb-f8f5bf0cfa00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36708
71734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3670871734
Directory /workspace/8.usbdev_link_resume/latest


Test location /workspace/coverage/default/8.usbdev_link_suspend.4135046322
Short name T119
Test name
Test status
Simulation time 8732747688 ps
CPU time 12.07 seconds
Started Aug 11 07:10:10 PM PDT 24
Finished Aug 11 07:10:22 PM PDT 24
Peak memory 207832 kb
Host smart-6cab54fc-e075-4a58-9c87-ca14e2f9f310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41350
46322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.4135046322
Directory /workspace/8.usbdev_link_suspend/latest


Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2276659477
Short name T1125
Test name
Test status
Simulation time 3347605360 ps
CPU time 27.81 seconds
Started Aug 11 07:10:10 PM PDT 24
Finished Aug 11 07:10:38 PM PDT 24
Peak memory 216040 kb
Host smart-c7a4abf1-35d1-48b2-9be1-9c2d07d28ee0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2276659477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2276659477
Directory /workspace/8.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.4145384579
Short name T2447
Test name
Test status
Simulation time 2926950351 ps
CPU time 26.76 seconds
Started Aug 11 07:10:21 PM PDT 24
Finished Aug 11 07:10:48 PM PDT 24
Peak memory 216092 kb
Host smart-f94bae0e-b9dd-4d74-a0d3-8f1ead96f2e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4145384579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.4145384579
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.27339525
Short name T3338
Test name
Test status
Simulation time 240051744 ps
CPU time 1.04 seconds
Started Aug 11 07:10:11 PM PDT 24
Finished Aug 11 07:10:12 PM PDT 24
Peak memory 207468 kb
Host smart-fe914cda-2d42-4de9-9458-11be9dadd5f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=27339525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.27339525
Directory /workspace/8.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3362482446
Short name T1225
Test name
Test status
Simulation time 232644190 ps
CPU time 1.04 seconds
Started Aug 11 07:10:10 PM PDT 24
Finished Aug 11 07:10:12 PM PDT 24
Peak memory 207572 kb
Host smart-22393a59-ebbd-4502-9e95-190169cb7905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624
82446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3362482446
Directory /workspace/8.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.1868713395
Short name T1559
Test name
Test status
Simulation time 1950313416 ps
CPU time 17.92 seconds
Started Aug 11 07:10:09 PM PDT 24
Finished Aug 11 07:10:27 PM PDT 24
Peak memory 217248 kb
Host smart-05eaa406-69ed-42fc-8403-6e901869e9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18687
13395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.1868713395
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.818692405
Short name T1507
Test name
Test status
Simulation time 1888238366 ps
CPU time 54.88 seconds
Started Aug 11 07:10:09 PM PDT 24
Finished Aug 11 07:11:04 PM PDT 24
Peak memory 217700 kb
Host smart-eab8d564-5a24-424f-ab64-541b6c970640
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=818692405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.818692405
Directory /workspace/8.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1672644808
Short name T1160
Test name
Test status
Simulation time 2629167007 ps
CPU time 24.09 seconds
Started Aug 11 07:10:13 PM PDT 24
Finished Aug 11 07:10:37 PM PDT 24
Peak memory 216116 kb
Host smart-c75d005e-14f7-4460-9533-0a93e4cf0c6e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1672644808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1672644808
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2547297969
Short name T2389
Test name
Test status
Simulation time 214099377 ps
CPU time 1 seconds
Started Aug 11 07:10:13 PM PDT 24
Finished Aug 11 07:10:14 PM PDT 24
Peak memory 207436 kb
Host smart-76788387-93e6-469e-b1ff-677060da5b8a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2547297969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2547297969
Directory /workspace/8.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3856240958
Short name T1626
Test name
Test status
Simulation time 146351676 ps
CPU time 0.8 seconds
Started Aug 11 07:10:08 PM PDT 24
Finished Aug 11 07:10:09 PM PDT 24
Peak memory 207568 kb
Host smart-21a67477-1465-45c7-9ec0-c3b97a2086e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38562
40958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3856240958
Directory /workspace/8.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_nak_trans.3852226306
Short name T158
Test name
Test status
Simulation time 191721129 ps
CPU time 0.92 seconds
Started Aug 11 07:10:11 PM PDT 24
Finished Aug 11 07:10:12 PM PDT 24
Peak memory 207480 kb
Host smart-5b8f9852-4919-4716-b113-2056e4f457e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38522
26306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3852226306
Directory /workspace/8.usbdev_nak_trans/latest


Test location /workspace/coverage/default/8.usbdev_out_iso.2525980763
Short name T88
Test name
Test status
Simulation time 220951707 ps
CPU time 0.99 seconds
Started Aug 11 07:10:10 PM PDT 24
Finished Aug 11 07:10:11 PM PDT 24
Peak memory 207460 kb
Host smart-3a77b937-eb06-44b1-8259-c888af251437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25259
80763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2525980763
Directory /workspace/8.usbdev_out_iso/latest


Test location /workspace/coverage/default/8.usbdev_out_stall.1582756021
Short name T2862
Test name
Test status
Simulation time 164443489 ps
CPU time 0.86 seconds
Started Aug 11 07:10:16 PM PDT 24
Finished Aug 11 07:10:17 PM PDT 24
Peak memory 207568 kb
Host smart-c0e1577e-3465-406c-83ca-d9bec5c5ba5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15827
56021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1582756021
Directory /workspace/8.usbdev_out_stall/latest


Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2170840050
Short name T3397
Test name
Test status
Simulation time 158456512 ps
CPU time 0.87 seconds
Started Aug 11 07:10:20 PM PDT 24
Finished Aug 11 07:10:21 PM PDT 24
Peak memory 207524 kb
Host smart-4a7a821c-5741-479c-a6cf-843453066a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21708
40050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2170840050
Directory /workspace/8.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3198013498
Short name T3028
Test name
Test status
Simulation time 183041980 ps
CPU time 0.91 seconds
Started Aug 11 07:10:17 PM PDT 24
Finished Aug 11 07:10:18 PM PDT 24
Peak memory 207588 kb
Host smart-e3144b4c-a2d1-4a64-85c5-3540c784f664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31980
13498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3198013498
Directory /workspace/8.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.997917413
Short name T2824
Test name
Test status
Simulation time 226047880 ps
CPU time 1.1 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207556 kb
Host smart-e063d8b9-914e-4b45-99a1-aee3322015ab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=997917413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.997917413
Directory /workspace/8.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.426728220
Short name T967
Test name
Test status
Simulation time 142566337 ps
CPU time 0.88 seconds
Started Aug 11 07:10:17 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207524 kb
Host smart-9e9f6447-a2dc-4920-ade6-d6917b674f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42672
8220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.426728220
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.165446241
Short name T44
Test name
Test status
Simulation time 37192856 ps
CPU time 0.72 seconds
Started Aug 11 07:10:17 PM PDT 24
Finished Aug 11 07:10:18 PM PDT 24
Peak memory 207536 kb
Host smart-6671b565-8e9c-46cf-8aa1-e8cab4cf4b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16544
6241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.165446241
Directory /workspace/8.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2435148659
Short name T243
Test name
Test status
Simulation time 18250891024 ps
CPU time 46.17 seconds
Started Aug 11 07:10:16 PM PDT 24
Finished Aug 11 07:11:02 PM PDT 24
Peak memory 224256 kb
Host smart-360c86f2-bf06-40c3-96c9-8c618ae9b31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24351
48659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2435148659
Directory /workspace/8.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/8.usbdev_pkt_received.3257439623
Short name T1152
Test name
Test status
Simulation time 151780323 ps
CPU time 0.87 seconds
Started Aug 11 07:10:16 PM PDT 24
Finished Aug 11 07:10:17 PM PDT 24
Peak memory 207480 kb
Host smart-bd28d206-0f85-4458-9e28-85f6481752d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32574
39623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3257439623
Directory /workspace/8.usbdev_pkt_received/latest


Test location /workspace/coverage/default/8.usbdev_pkt_sent.56460999
Short name T1663
Test name
Test status
Simulation time 230486093 ps
CPU time 1.07 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207720 kb
Host smart-43f0a95a-ef3c-4141-bddb-c58de5ab9a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56460
999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.56460999
Directory /workspace/8.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.4179980465
Short name T1924
Test name
Test status
Simulation time 7436085706 ps
CPU time 210.01 seconds
Started Aug 11 07:10:16 PM PDT 24
Finished Aug 11 07:13:46 PM PDT 24
Peak memory 216104 kb
Host smart-9e8751e9-cf5d-4076-a804-64e05bed0d9a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179980465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.4179980465
Directory /workspace/8.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1416513641
Short name T2750
Test name
Test status
Simulation time 7581414086 ps
CPU time 37.63 seconds
Started Aug 11 07:10:17 PM PDT 24
Finished Aug 11 07:10:55 PM PDT 24
Peak memory 224252 kb
Host smart-b255f9df-8929-4cae-91ca-8297a0513929
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1416513641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1416513641
Directory /workspace/8.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/8.usbdev_rand_suspends.2128783483
Short name T2887
Test name
Test status
Simulation time 10278959679 ps
CPU time 66.82 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:11:25 PM PDT 24
Peak memory 224304 kb
Host smart-258fc79b-b5ea-4719-8ced-b9ae8603ac92
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128783483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2128783483
Directory /workspace/8.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1286393415
Short name T1658
Test name
Test status
Simulation time 223701862 ps
CPU time 1.07 seconds
Started Aug 11 07:10:19 PM PDT 24
Finished Aug 11 07:10:20 PM PDT 24
Peak memory 207524 kb
Host smart-cc7dd7d4-b70a-40bb-ab26-ec388300e9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12863
93415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1286393415
Directory /workspace/8.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.570220847
Short name T2138
Test name
Test status
Simulation time 189352402 ps
CPU time 0.94 seconds
Started Aug 11 07:10:17 PM PDT 24
Finished Aug 11 07:10:18 PM PDT 24
Peak memory 207576 kb
Host smart-19fd6105-8281-4c1c-b1e9-6518c7d8c6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57022
0847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.570220847
Directory /workspace/8.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_resume_link_active.3724851376
Short name T2520
Test name
Test status
Simulation time 20167524545 ps
CPU time 25.66 seconds
Started Aug 11 07:10:15 PM PDT 24
Finished Aug 11 07:10:41 PM PDT 24
Peak memory 207624 kb
Host smart-75ada015-bf0b-4c61-bbd5-0498932bf01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37248
51376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.3724851376
Directory /workspace/8.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1433493506
Short name T1552
Test name
Test status
Simulation time 168445689 ps
CPU time 0.88 seconds
Started Aug 11 07:10:17 PM PDT 24
Finished Aug 11 07:10:18 PM PDT 24
Peak memory 207572 kb
Host smart-9a45d4a5-bec2-48d5-ab44-4e936fc804c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14334
93506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1433493506
Directory /workspace/8.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/8.usbdev_rx_full.3911101621
Short name T2556
Test name
Test status
Simulation time 325305228 ps
CPU time 1.17 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207548 kb
Host smart-dd79d176-6ab4-4313-8697-50c3beb47a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39111
01621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.3911101621
Directory /workspace/8.usbdev_rx_full/latest


Test location /workspace/coverage/default/8.usbdev_setup_stage.2848891517
Short name T925
Test name
Test status
Simulation time 158105472 ps
CPU time 0.85 seconds
Started Aug 11 07:10:16 PM PDT 24
Finished Aug 11 07:10:17 PM PDT 24
Peak memory 207500 kb
Host smart-d2dc5bd1-e218-47bc-85c0-e73932bd14a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28488
91517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2848891517
Directory /workspace/8.usbdev_setup_stage/latest


Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3910981575
Short name T1094
Test name
Test status
Simulation time 153384187 ps
CPU time 0.91 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207572 kb
Host smart-a98a7b9e-38d3-44af-a598-fe23d3048e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39109
81575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3910981575
Directory /workspace/8.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/8.usbdev_smoke.4262971711
Short name T2473
Test name
Test status
Simulation time 202164738 ps
CPU time 0.96 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207480 kb
Host smart-53f60081-40a9-48ff-a868-7d017ecf22c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42629
71711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.4262971711
Directory /workspace/8.usbdev_smoke/latest


Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3103433957
Short name T1571
Test name
Test status
Simulation time 1975054727 ps
CPU time 15.53 seconds
Started Aug 11 07:10:17 PM PDT 24
Finished Aug 11 07:10:33 PM PDT 24
Peak memory 224100 kb
Host smart-337a8d1c-343c-4c99-9cc0-3b2a3d95d502
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3103433957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3103433957
Directory /workspace/8.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.368537737
Short name T3127
Test name
Test status
Simulation time 176556356 ps
CPU time 0.9 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207588 kb
Host smart-bc182688-6888-4a13-8812-c16db7155bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36853
7737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.368537737
Directory /workspace/8.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/8.usbdev_stall_trans.460990089
Short name T1985
Test name
Test status
Simulation time 175442849 ps
CPU time 1.02 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:10:19 PM PDT 24
Peak memory 207548 kb
Host smart-d1f1eb3d-8177-4bbe-8fbc-e1d92f949e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46099
0089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.460990089
Directory /workspace/8.usbdev_stall_trans/latest


Test location /workspace/coverage/default/8.usbdev_stream_len_max.1665578440
Short name T1450
Test name
Test status
Simulation time 1087065786 ps
CPU time 2.91 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:10:21 PM PDT 24
Peak memory 207628 kb
Host smart-11ebf2fa-c19b-45b1-ad46-39580b2f814d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16655
78440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.1665578440
Directory /workspace/8.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/8.usbdev_streaming_out.3735705891
Short name T3528
Test name
Test status
Simulation time 2329884047 ps
CPU time 66.79 seconds
Started Aug 11 07:10:17 PM PDT 24
Finished Aug 11 07:11:24 PM PDT 24
Peak memory 216108 kb
Host smart-8fc5497f-e78f-4ab4-b99e-9db3dc03b55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37357
05891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3735705891
Directory /workspace/8.usbdev_streaming_out/latest


Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.4154786509
Short name T1592
Test name
Test status
Simulation time 538744502 ps
CPU time 11.59 seconds
Started Aug 11 07:10:13 PM PDT 24
Finished Aug 11 07:10:24 PM PDT 24
Peak memory 207716 kb
Host smart-a03e8365-4bbe-499b-854d-f1687da1166c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154786509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.4154786509
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/8.usbdev_tx_rx_disruption.2838053190
Short name T3046
Test name
Test status
Simulation time 491033806 ps
CPU time 1.52 seconds
Started Aug 11 07:10:20 PM PDT 24
Finished Aug 11 07:10:22 PM PDT 24
Peak memory 207524 kb
Host smart-81364247-15c4-43ed-9733-bf4d11377fd9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838053190 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.usbdev_tx_rx_disruption.2838053190
Directory /workspace/8.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/80.usbdev_endpoint_types.3462506176
Short name T3305
Test name
Test status
Simulation time 214830434 ps
CPU time 1.04 seconds
Started Aug 11 07:16:49 PM PDT 24
Finished Aug 11 07:16:50 PM PDT 24
Peak memory 207480 kb
Host smart-c1147572-7d47-4511-bb2b-13d1d0812581
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3462506176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.3462506176
Directory /workspace/80.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/80.usbdev_tx_rx_disruption.264541046
Short name T1746
Test name
Test status
Simulation time 585906946 ps
CPU time 1.61 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207456 kb
Host smart-25412240-30b9-477a-8e10-db6e188da4a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264541046 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 80.usbdev_tx_rx_disruption.264541046
Directory /workspace/80.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/81.usbdev_tx_rx_disruption.2747300578
Short name T1978
Test name
Test status
Simulation time 483073286 ps
CPU time 1.45 seconds
Started Aug 11 07:16:59 PM PDT 24
Finished Aug 11 07:17:00 PM PDT 24
Peak memory 207564 kb
Host smart-e28a0de9-a52d-4f3f-bedd-2f1b44c159cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747300578 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.usbdev_tx_rx_disruption.2747300578
Directory /workspace/81.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/82.usbdev_endpoint_types.1866055483
Short name T2020
Test name
Test status
Simulation time 192959463 ps
CPU time 0.85 seconds
Started Aug 11 07:16:54 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 207528 kb
Host smart-e98d4d0a-2df5-4c8d-9876-336b37b338d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1866055483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.1866055483
Directory /workspace/82.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/82.usbdev_tx_rx_disruption.3616985128
Short name T1751
Test name
Test status
Simulation time 474878464 ps
CPU time 1.5 seconds
Started Aug 11 07:16:48 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 207540 kb
Host smart-df5a4b9f-68a7-40ed-9b4c-11673cea8e31
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616985128 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.usbdev_tx_rx_disruption.3616985128
Directory /workspace/82.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/83.usbdev_endpoint_types.2784320199
Short name T489
Test name
Test status
Simulation time 550684605 ps
CPU time 1.37 seconds
Started Aug 11 07:16:48 PM PDT 24
Finished Aug 11 07:16:49 PM PDT 24
Peak memory 207484 kb
Host smart-c08a91d7-783f-4f9a-950f-76ff8f436374
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2784320199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.2784320199
Directory /workspace/83.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/83.usbdev_tx_rx_disruption.1178643504
Short name T2234
Test name
Test status
Simulation time 599722755 ps
CPU time 1.6 seconds
Started Aug 11 07:16:54 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 207552 kb
Host smart-e09df6ac-b88a-4981-a3fe-d89ffba653a7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178643504 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.usbdev_tx_rx_disruption.1178643504
Directory /workspace/83.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/84.usbdev_endpoint_types.2332328836
Short name T1512
Test name
Test status
Simulation time 179936191 ps
CPU time 0.91 seconds
Started Aug 11 07:16:50 PM PDT 24
Finished Aug 11 07:16:51 PM PDT 24
Peak memory 207532 kb
Host smart-51d1cab5-51e1-4288-8bb2-19bda2506830
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2332328836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.2332328836
Directory /workspace/84.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/84.usbdev_tx_rx_disruption.882851154
Short name T2800
Test name
Test status
Simulation time 521420233 ps
CPU time 1.52 seconds
Started Aug 11 07:16:55 PM PDT 24
Finished Aug 11 07:16:57 PM PDT 24
Peak memory 207576 kb
Host smart-0582a295-c251-4c2b-bad4-9cca46009810
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882851154 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 84.usbdev_tx_rx_disruption.882851154
Directory /workspace/84.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/85.usbdev_tx_rx_disruption.2651546362
Short name T3157
Test name
Test status
Simulation time 706457194 ps
CPU time 1.7 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207540 kb
Host smart-3103105e-a024-4f03-ad28-ffc69660a7e3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651546362 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.usbdev_tx_rx_disruption.2651546362
Directory /workspace/85.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/86.usbdev_tx_rx_disruption.809125662
Short name T1614
Test name
Test status
Simulation time 590572265 ps
CPU time 1.75 seconds
Started Aug 11 07:16:52 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207740 kb
Host smart-62d60b19-3d2b-49c0-8787-7a5aa5e51306
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809125662 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 86.usbdev_tx_rx_disruption.809125662
Directory /workspace/86.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/87.usbdev_endpoint_types.10268291
Short name T429
Test name
Test status
Simulation time 449212840 ps
CPU time 1.39 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:40 PM PDT 24
Peak memory 207476 kb
Host smart-f0bdd6aa-5e2f-4025-8386-a9688aadc20a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=10268291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.10268291
Directory /workspace/87.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/87.usbdev_tx_rx_disruption.924261200
Short name T173
Test name
Test status
Simulation time 512046157 ps
CPU time 1.55 seconds
Started Aug 11 07:17:01 PM PDT 24
Finished Aug 11 07:17:03 PM PDT 24
Peak memory 207552 kb
Host smart-6e3b53bc-9de3-40cf-888c-503f131fd289
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924261200 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 87.usbdev_tx_rx_disruption.924261200
Directory /workspace/87.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/88.usbdev_endpoint_types.181833537
Short name T506
Test name
Test status
Simulation time 242950940 ps
CPU time 0.99 seconds
Started Aug 11 07:16:55 PM PDT 24
Finished Aug 11 07:16:56 PM PDT 24
Peak memory 207460 kb
Host smart-43d28415-748a-4af1-a5b4-7cbe31ae5001
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=181833537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.181833537
Directory /workspace/88.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/88.usbdev_tx_rx_disruption.2834152006
Short name T1426
Test name
Test status
Simulation time 418290425 ps
CPU time 1.31 seconds
Started Aug 11 07:16:54 PM PDT 24
Finished Aug 11 07:16:55 PM PDT 24
Peak memory 207492 kb
Host smart-2a57ddb6-1b19-4178-8f0c-e435d93b6901
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834152006 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.usbdev_tx_rx_disruption.2834152006
Directory /workspace/88.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/89.usbdev_endpoint_types.1612443375
Short name T479
Test name
Test status
Simulation time 762237654 ps
CPU time 1.82 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 207524 kb
Host smart-7d7208b7-ee5f-487d-91b5-f5a0dec775b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1612443375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.1612443375
Directory /workspace/89.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/89.usbdev_tx_rx_disruption.3488267422
Short name T2287
Test name
Test status
Simulation time 482228248 ps
CPU time 1.62 seconds
Started Aug 11 07:16:38 PM PDT 24
Finished Aug 11 07:16:39 PM PDT 24
Peak memory 207524 kb
Host smart-b8d3f00e-03d2-4da6-9a10-eac7c242faac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488267422 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.usbdev_tx_rx_disruption.3488267422
Directory /workspace/89.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/9.usbdev_alert_test.2161206787
Short name T780
Test name
Test status
Simulation time 35497823 ps
CPU time 0.72 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:10:31 PM PDT 24
Peak memory 207548 kb
Host smart-eb39b265-3fc5-433a-ad27-8bcc1050e630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2161206787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.2161206787
Directory /workspace/9.usbdev_alert_test/latest


Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2930737301
Short name T2784
Test name
Test status
Simulation time 10953045616 ps
CPU time 14.25 seconds
Started Aug 11 07:10:15 PM PDT 24
Finished Aug 11 07:10:29 PM PDT 24
Peak memory 207752 kb
Host smart-96c4e32a-af2f-4ad8-878c-641ebf4cfbf0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930737301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.2930737301
Directory /workspace/9.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1890161268
Short name T1210
Test name
Test status
Simulation time 15157111554 ps
CPU time 19.06 seconds
Started Aug 11 07:10:17 PM PDT 24
Finished Aug 11 07:10:36 PM PDT 24
Peak memory 215992 kb
Host smart-e887c127-a15b-451d-b64f-2d2ac4b4a1ed
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890161268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1890161268
Directory /workspace/9.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.2613757551
Short name T2303
Test name
Test status
Simulation time 29970642815 ps
CPU time 38.99 seconds
Started Aug 11 07:10:18 PM PDT 24
Finished Aug 11 07:10:57 PM PDT 24
Peak memory 208072 kb
Host smart-e709b7dd-7675-4024-88d4-9c296264d18c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613757551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.2613757551
Directory /workspace/9.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/9.usbdev_av_buffer.3987793395
Short name T841
Test name
Test status
Simulation time 158198145 ps
CPU time 0.87 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207572 kb
Host smart-456bef66-a5d0-4f08-8c9b-77f41bbbd931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39877
93395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3987793395
Directory /workspace/9.usbdev_av_buffer/latest


Test location /workspace/coverage/default/9.usbdev_bitstuff_err.677010189
Short name T2448
Test name
Test status
Simulation time 152581104 ps
CPU time 0.87 seconds
Started Aug 11 07:10:22 PM PDT 24
Finished Aug 11 07:10:23 PM PDT 24
Peak memory 207512 kb
Host smart-d72de41b-dd73-46ba-a6aa-94331224eabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67701
0189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.677010189
Directory /workspace/9.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.870710664
Short name T1848
Test name
Test status
Simulation time 207464609 ps
CPU time 0.97 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:10:24 PM PDT 24
Peak memory 207480 kb
Host smart-3fa56182-0d83-47e7-b9a4-23f596be974d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87071
0664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.870710664
Directory /workspace/9.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3120806126
Short name T2589
Test name
Test status
Simulation time 1163574517 ps
CPU time 3.11 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:27 PM PDT 24
Peak memory 207792 kb
Host smart-d3b8b612-d15e-46bd-98d7-55d249637cd5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3120806126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3120806126
Directory /workspace/9.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/9.usbdev_device_address.2384333913
Short name T1261
Test name
Test status
Simulation time 39472006638 ps
CPU time 76.32 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:11:39 PM PDT 24
Peak memory 207836 kb
Host smart-27e7a6c1-3f0f-4a43-a6a1-081e93481f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23843
33913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2384333913
Directory /workspace/9.usbdev_device_address/latest


Test location /workspace/coverage/default/9.usbdev_device_timeout.3425572076
Short name T1110
Test name
Test status
Simulation time 3170275347 ps
CPU time 22 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:10:45 PM PDT 24
Peak memory 207816 kb
Host smart-29473a95-f1f0-4e3d-96ef-6f09dac516a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425572076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.3425572076
Directory /workspace/9.usbdev_device_timeout/latest


Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1823396974
Short name T3400
Test name
Test status
Simulation time 1173294525 ps
CPU time 2.49 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:27 PM PDT 24
Peak memory 207492 kb
Host smart-c53342f6-3ccb-4804-8e0e-4f93b874d656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18233
96974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1823396974
Directory /workspace/9.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/9.usbdev_disconnected.659957983
Short name T2605
Test name
Test status
Simulation time 144040997 ps
CPU time 0.79 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:10:24 PM PDT 24
Peak memory 207536 kb
Host smart-fc059d84-1d08-459f-967a-83a085fb6c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65995
7983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.659957983
Directory /workspace/9.usbdev_disconnected/latest


Test location /workspace/coverage/default/9.usbdev_enable.15489775
Short name T561
Test name
Test status
Simulation time 32645694 ps
CPU time 0.7 seconds
Started Aug 11 07:10:22 PM PDT 24
Finished Aug 11 07:10:23 PM PDT 24
Peak memory 207440 kb
Host smart-cd93f16c-622a-4d31-b87a-d7c46ae757f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15489
775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.15489775
Directory /workspace/9.usbdev_enable/latest


Test location /workspace/coverage/default/9.usbdev_endpoint_access.1136919194
Short name T1322
Test name
Test status
Simulation time 929707456 ps
CPU time 2.66 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:10:26 PM PDT 24
Peak memory 207696 kb
Host smart-416f1f74-95f8-4c9a-9235-91ddfae19880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
19194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1136919194
Directory /workspace/9.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/9.usbdev_endpoint_types.1135357735
Short name T2390
Test name
Test status
Simulation time 219353325 ps
CPU time 1 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207520 kb
Host smart-554a9001-16ea-460e-b9c7-ecda8bb5a3d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1135357735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.1135357735
Directory /workspace/9.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/9.usbdev_fifo_rst.2688505953
Short name T2860
Test name
Test status
Simulation time 208699248 ps
CPU time 1.57 seconds
Started Aug 11 07:10:22 PM PDT 24
Finished Aug 11 07:10:24 PM PDT 24
Peak memory 207740 kb
Host smart-4a7eb216-c842-4624-b5f8-0c048a33fcef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26885
05953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2688505953
Directory /workspace/9.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/9.usbdev_in_iso.303360773
Short name T2875
Test name
Test status
Simulation time 210610785 ps
CPU time 1.07 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 215928 kb
Host smart-dd9a17c8-b6c5-4093-952f-478f90ebee6f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=303360773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.303360773
Directory /workspace/9.usbdev_in_iso/latest


Test location /workspace/coverage/default/9.usbdev_in_stall.1024486638
Short name T1286
Test name
Test status
Simulation time 148978735 ps
CPU time 0.84 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207544 kb
Host smart-c8a0e619-05dd-4230-943d-2e3d1b92171f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10244
86638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1024486638
Directory /workspace/9.usbdev_in_stall/latest


Test location /workspace/coverage/default/9.usbdev_in_trans.3024356344
Short name T1733
Test name
Test status
Simulation time 207638167 ps
CPU time 0.96 seconds
Started Aug 11 07:10:22 PM PDT 24
Finished Aug 11 07:10:23 PM PDT 24
Peak memory 207484 kb
Host smart-fb3b4301-6f50-4a5b-a7b2-2b3dcef82920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30243
56344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3024356344
Directory /workspace/9.usbdev_in_trans/latest


Test location /workspace/coverage/default/9.usbdev_invalid_sync.2502864453
Short name T1916
Test name
Test status
Simulation time 4401916088 ps
CPU time 142.24 seconds
Started Aug 11 07:10:21 PM PDT 24
Finished Aug 11 07:12:43 PM PDT 24
Peak memory 218016 kb
Host smart-18120952-8a82-44cd-ae9e-40cfcb15af09
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2502864453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.2502864453
Directory /workspace/9.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/9.usbdev_iso_retraction.3639185870
Short name T3341
Test name
Test status
Simulation time 14942511360 ps
CPU time 97.55 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:12:01 PM PDT 24
Peak memory 207808 kb
Host smart-4d39e396-fc03-4268-aacd-2ecb1ec1553f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3639185870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.3639185870
Directory /workspace/9.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/9.usbdev_link_in_err.3962482975
Short name T2733
Test name
Test status
Simulation time 253723986 ps
CPU time 1.03 seconds
Started Aug 11 07:10:22 PM PDT 24
Finished Aug 11 07:10:23 PM PDT 24
Peak memory 207488 kb
Host smart-2d2dc520-a059-4b88-be93-4125e3cfad70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39624
82975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3962482975
Directory /workspace/9.usbdev_link_in_err/latest


Test location /workspace/coverage/default/9.usbdev_link_resume.254284528
Short name T1489
Test name
Test status
Simulation time 13939700638 ps
CPU time 19.72 seconds
Started Aug 11 07:10:26 PM PDT 24
Finished Aug 11 07:10:46 PM PDT 24
Peak memory 207872 kb
Host smart-4fb3419c-9ae0-4e2b-b348-1a695b40f932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25428
4528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.254284528
Directory /workspace/9.usbdev_link_resume/latest


Test location /workspace/coverage/default/9.usbdev_link_suspend.3865329950
Short name T2950
Test name
Test status
Simulation time 4198205088 ps
CPU time 5.81 seconds
Started Aug 11 07:10:26 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 216036 kb
Host smart-b965d38a-eb2d-4c67-b7fe-e12ffc275e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38653
29950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3865329950
Directory /workspace/9.usbdev_link_suspend/latest


Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3429344515
Short name T3458
Test name
Test status
Simulation time 3079133121 ps
CPU time 25.86 seconds
Started Aug 11 07:10:25 PM PDT 24
Finished Aug 11 07:10:51 PM PDT 24
Peak memory 224304 kb
Host smart-0e4a3960-650b-4ba7-aa66-467b8bd83446
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3429344515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3429344515
Directory /workspace/9.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.39241540
Short name T909
Test name
Test status
Simulation time 3919923949 ps
CPU time 114.21 seconds
Started Aug 11 07:10:25 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 216100 kb
Host smart-cda1193f-5e28-4a13-a777-eae170e3f212
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=39241540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.39241540
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3346429830
Short name T3090
Test name
Test status
Simulation time 236600412 ps
CPU time 1.03 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207564 kb
Host smart-ddcf989b-51b1-408a-9250-4d4fe1d1bc6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3346429830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3346429830
Directory /workspace/9.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3591279897
Short name T1123
Test name
Test status
Simulation time 196378689 ps
CPU time 0.96 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207516 kb
Host smart-9e4a2e29-71f0-4f14-82ca-953ca27f22c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912
79897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3591279897
Directory /workspace/9.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.932390416
Short name T963
Test name
Test status
Simulation time 3238944933 ps
CPU time 95.69 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:11:59 PM PDT 24
Peak memory 217976 kb
Host smart-4f629038-64a1-46de-8b13-a583960b97f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93239
0416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.932390416
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.1316498518
Short name T3279
Test name
Test status
Simulation time 1774988763 ps
CPU time 51.29 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:11:15 PM PDT 24
Peak memory 217608 kb
Host smart-3c5706d4-c2e8-4fc2-bb5c-35ab26c287cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1316498518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.1316498518
Directory /workspace/9.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.488973012
Short name T1064
Test name
Test status
Simulation time 3880483509 ps
CPU time 115.07 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:12:18 PM PDT 24
Peak memory 217468 kb
Host smart-2e5c63c9-e695-4140-b76d-b642583f608e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=488973012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.488973012
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3435885614
Short name T32
Test name
Test status
Simulation time 160168447 ps
CPU time 0.88 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:10:24 PM PDT 24
Peak memory 207564 kb
Host smart-8cb0c5ee-189c-439a-941e-1c9dbd764387
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3435885614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3435885614
Directory /workspace/9.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.739429797
Short name T2414
Test name
Test status
Simulation time 159933851 ps
CPU time 0.86 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207520 kb
Host smart-813d4be0-91ce-47b3-9eba-99a2e2f6adc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73942
9797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.739429797
Directory /workspace/9.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_nak_trans.1877434966
Short name T136
Test name
Test status
Simulation time 177224919 ps
CPU time 0.89 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207548 kb
Host smart-0c6f7d38-c221-43d1-a170-9f690f3456d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18774
34966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1877434966
Directory /workspace/9.usbdev_nak_trans/latest


Test location /workspace/coverage/default/9.usbdev_out_iso.3960207360
Short name T2787
Test name
Test status
Simulation time 174388162 ps
CPU time 0.91 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:26 PM PDT 24
Peak memory 207540 kb
Host smart-684ce205-dce6-4208-ac2a-4b7b3da3af47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39602
07360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3960207360
Directory /workspace/9.usbdev_out_iso/latest


Test location /workspace/coverage/default/9.usbdev_out_stall.1886211574
Short name T1653
Test name
Test status
Simulation time 222252877 ps
CPU time 1.03 seconds
Started Aug 11 07:10:22 PM PDT 24
Finished Aug 11 07:10:23 PM PDT 24
Peak memory 207580 kb
Host smart-6a58e972-1744-4bd5-9176-0881d175da3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18862
11574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1886211574
Directory /workspace/9.usbdev_out_stall/latest


Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3472961586
Short name T639
Test name
Test status
Simulation time 230932558 ps
CPU time 0.94 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207512 kb
Host smart-e44c1c7e-e89e-4e18-8200-9bee61fe9822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34729
61586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3472961586
Directory /workspace/9.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/9.usbdev_pending_in_trans.4245782487
Short name T975
Test name
Test status
Simulation time 206695165 ps
CPU time 0.88 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:10:24 PM PDT 24
Peak memory 207548 kb
Host smart-6c16256d-36f8-4dbc-8cb9-d197bbe8db28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42457
82487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.4245782487
Directory /workspace/9.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2649830777
Short name T2003
Test name
Test status
Simulation time 225140551 ps
CPU time 1.02 seconds
Started Aug 11 07:10:22 PM PDT 24
Finished Aug 11 07:10:23 PM PDT 24
Peak memory 207572 kb
Host smart-68f1f31f-a809-49b6-93ef-a326de75c6c0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2649830777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2649830777
Directory /workspace/9.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.253974271
Short name T2117
Test name
Test status
Simulation time 144505123 ps
CPU time 0.85 seconds
Started Aug 11 07:10:24 PM PDT 24
Finished Aug 11 07:10:25 PM PDT 24
Peak memory 207488 kb
Host smart-d39edb40-4d50-42e2-9329-4449d9c17a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25397
4271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.253974271
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1876255308
Short name T3510
Test name
Test status
Simulation time 41868056 ps
CPU time 0.73 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:10:24 PM PDT 24
Peak memory 207472 kb
Host smart-94a0c506-a0d7-4455-acef-5caf135333d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18762
55308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1876255308
Directory /workspace/9.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3230296403
Short name T2100
Test name
Test status
Simulation time 21578993252 ps
CPU time 50.4 seconds
Started Aug 11 07:10:28 PM PDT 24
Finished Aug 11 07:11:18 PM PDT 24
Peak memory 216072 kb
Host smart-5aee64a8-c01a-48ef-a939-fbf4b32b9579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32302
96403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3230296403
Directory /workspace/9.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/9.usbdev_pkt_received.465662504
Short name T970
Test name
Test status
Simulation time 209219769 ps
CPU time 0.99 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:10:31 PM PDT 24
Peak memory 207564 kb
Host smart-7669b519-cc96-49d8-ad8f-977fd52c3c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46566
2504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.465662504
Directory /workspace/9.usbdev_pkt_received/latest


Test location /workspace/coverage/default/9.usbdev_pkt_sent.3598588845
Short name T1780
Test name
Test status
Simulation time 181730661 ps
CPU time 0.93 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:10:31 PM PDT 24
Peak memory 207524 kb
Host smart-7d3ec13e-62a5-4f33-8f6f-c64e6b25bff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35985
88845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3598588845
Directory /workspace/9.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1448747050
Short name T2870
Test name
Test status
Simulation time 3932769474 ps
CPU time 34.42 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:11:06 PM PDT 24
Peak memory 217632 kb
Host smart-73ff6be9-666e-423d-9d69-4e6ccd5be3e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448747050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1448747050
Directory /workspace/9.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2051504844
Short name T1809
Test name
Test status
Simulation time 6325892455 ps
CPU time 28.16 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:10:58 PM PDT 24
Peak memory 224216 kb
Host smart-05d845d3-a3b1-4102-8db4-f1e6591ecf51
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2051504844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2051504844
Directory /workspace/9.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/9.usbdev_rand_suspends.1668395575
Short name T2816
Test name
Test status
Simulation time 14673751054 ps
CPU time 81.67 seconds
Started Aug 11 07:10:28 PM PDT 24
Finished Aug 11 07:11:50 PM PDT 24
Peak memory 224180 kb
Host smart-76781588-a0f7-427a-9f26-7703994149f6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668395575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1668395575
Directory /workspace/9.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.671639869
Short name T1850
Test name
Test status
Simulation time 178353047 ps
CPU time 0.91 seconds
Started Aug 11 07:10:29 PM PDT 24
Finished Aug 11 07:10:31 PM PDT 24
Peak memory 207480 kb
Host smart-122816f5-4fd4-44a4-a995-1552fda7d692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67163
9869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.671639869
Directory /workspace/9.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3153957177
Short name T1052
Test name
Test status
Simulation time 185512059 ps
CPU time 0.93 seconds
Started Aug 11 07:10:29 PM PDT 24
Finished Aug 11 07:10:30 PM PDT 24
Peak memory 207584 kb
Host smart-3db9e533-d46e-468e-b7b5-adfc104282d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31539
57177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3153957177
Directory /workspace/9.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_resume_link_active.3409610952
Short name T1896
Test name
Test status
Simulation time 20184119460 ps
CPU time 22.25 seconds
Started Aug 11 07:10:29 PM PDT 24
Finished Aug 11 07:10:52 PM PDT 24
Peak memory 207580 kb
Host smart-9130ae45-9680-48e9-ade3-74a35fcfefab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34096
10952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.3409610952
Directory /workspace/9.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/9.usbdev_rx_crc_err.4020216809
Short name T77
Test name
Test status
Simulation time 179051303 ps
CPU time 0.85 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:10:33 PM PDT 24
Peak memory 207504 kb
Host smart-0b92c75e-2db9-460a-9094-d9479c124556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40202
16809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.4020216809
Directory /workspace/9.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/9.usbdev_rx_full.3096372559
Short name T344
Test name
Test status
Simulation time 414990195 ps
CPU time 1.52 seconds
Started Aug 11 07:10:28 PM PDT 24
Finished Aug 11 07:10:30 PM PDT 24
Peak memory 207480 kb
Host smart-9d6b8ad6-d63e-43e5-9263-b8ae62a49796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30963
72559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.3096372559
Directory /workspace/9.usbdev_rx_full/latest


Test location /workspace/coverage/default/9.usbdev_setup_stage.1599846460
Short name T908
Test name
Test status
Simulation time 194745211 ps
CPU time 0.93 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 207500 kb
Host smart-d8c82c31-511c-4591-91b2-aa16a2597934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15998
46460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1599846460
Directory /workspace/9.usbdev_setup_stage/latest


Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1889107003
Short name T2643
Test name
Test status
Simulation time 157759845 ps
CPU time 0.81 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:10:31 PM PDT 24
Peak memory 207552 kb
Host smart-ca646e4a-ea16-474e-a385-19750a52d382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18891
07003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1889107003
Directory /workspace/9.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/9.usbdev_smoke.1196611443
Short name T2892
Test name
Test status
Simulation time 208949836 ps
CPU time 1 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:10:32 PM PDT 24
Peak memory 207508 kb
Host smart-44b21e6f-de96-42d1-8be2-2ae1bf5c4a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11966
11443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1196611443
Directory /workspace/9.usbdev_smoke/latest


Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.4073307979
Short name T1327
Test name
Test status
Simulation time 1965163874 ps
CPU time 14.61 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:10:45 PM PDT 24
Peak memory 217528 kb
Host smart-d88eff22-58f6-4023-85ab-002d4141cb78
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4073307979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.4073307979
Directory /workspace/9.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2741585797
Short name T2485
Test name
Test status
Simulation time 200274547 ps
CPU time 0.95 seconds
Started Aug 11 07:10:29 PM PDT 24
Finished Aug 11 07:10:31 PM PDT 24
Peak memory 207572 kb
Host smart-3b349fd2-1a21-486d-a823-63f085d7a0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27415
85797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2741585797
Directory /workspace/9.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/9.usbdev_stall_trans.769446396
Short name T2044
Test name
Test status
Simulation time 187141511 ps
CPU time 0.94 seconds
Started Aug 11 07:10:32 PM PDT 24
Finished Aug 11 07:10:33 PM PDT 24
Peak memory 207480 kb
Host smart-90d7d18f-07b1-4ade-a82d-aeac6e45dacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76944
6396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.769446396
Directory /workspace/9.usbdev_stall_trans/latest


Test location /workspace/coverage/default/9.usbdev_stream_len_max.2749302301
Short name T3284
Test name
Test status
Simulation time 1148343019 ps
CPU time 2.93 seconds
Started Aug 11 07:10:31 PM PDT 24
Finished Aug 11 07:10:34 PM PDT 24
Peak memory 207664 kb
Host smart-a9396cb0-1b27-4d3b-aae9-e1061d94457a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27493
02301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.2749302301
Directory /workspace/9.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/9.usbdev_streaming_out.2502116024
Short name T750
Test name
Test status
Simulation time 3379229827 ps
CPU time 24.64 seconds
Started Aug 11 07:10:27 PM PDT 24
Finished Aug 11 07:10:52 PM PDT 24
Peak memory 216084 kb
Host smart-ae4e02cc-630c-41f7-b42c-a6cc75f63e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25021
16024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2502116024
Directory /workspace/9.usbdev_streaming_out/latest


Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.2171761365
Short name T1754
Test name
Test status
Simulation time 2484897005 ps
CPU time 21.41 seconds
Started Aug 11 07:10:23 PM PDT 24
Finished Aug 11 07:10:44 PM PDT 24
Peak memory 207884 kb
Host smart-76db43ed-52a2-4eeb-95eb-5606bab4c410
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171761365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.2171761365
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/9.usbdev_tx_rx_disruption.2140954661
Short name T2576
Test name
Test status
Simulation time 490260807 ps
CPU time 1.65 seconds
Started Aug 11 07:10:30 PM PDT 24
Finished Aug 11 07:10:31 PM PDT 24
Peak memory 207432 kb
Host smart-79a34f49-5c1e-4857-bf78-b35b0ada478e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140954661 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.usbdev_tx_rx_disruption.2140954661
Directory /workspace/9.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/90.usbdev_endpoint_types.2307053359
Short name T502
Test name
Test status
Simulation time 302328669 ps
CPU time 1.24 seconds
Started Aug 11 07:16:45 PM PDT 24
Finished Aug 11 07:16:46 PM PDT 24
Peak memory 207508 kb
Host smart-9d554602-9c5f-4661-b15f-ad20d7d60f1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2307053359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.2307053359
Directory /workspace/90.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/90.usbdev_tx_rx_disruption.624756266
Short name T2481
Test name
Test status
Simulation time 502179633 ps
CPU time 1.61 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:04 PM PDT 24
Peak memory 207552 kb
Host smart-1083dbed-0a47-486c-9c6e-8b502b3885d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624756266 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 90.usbdev_tx_rx_disruption.624756266
Directory /workspace/90.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/91.usbdev_endpoint_types.142409739
Short name T490
Test name
Test status
Simulation time 270155384 ps
CPU time 1.04 seconds
Started Aug 11 07:16:52 PM PDT 24
Finished Aug 11 07:16:53 PM PDT 24
Peak memory 207556 kb
Host smart-c378af6a-9598-4d5d-b6e5-bcbd6430cc9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=142409739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.142409739
Directory /workspace/91.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/91.usbdev_tx_rx_disruption.1776315419
Short name T2232
Test name
Test status
Simulation time 555258666 ps
CPU time 1.52 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207480 kb
Host smart-9dea27b0-7e39-4d09-afce-9b3ef3487a76
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776315419 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.usbdev_tx_rx_disruption.1776315419
Directory /workspace/91.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/92.usbdev_endpoint_types.141502508
Short name T426
Test name
Test status
Simulation time 659662717 ps
CPU time 1.71 seconds
Started Aug 11 07:17:06 PM PDT 24
Finished Aug 11 07:17:08 PM PDT 24
Peak memory 207504 kb
Host smart-cbbd9d4c-09bb-4822-8080-b27164eb198e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=141502508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.141502508
Directory /workspace/92.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/92.usbdev_tx_rx_disruption.2399038164
Short name T1659
Test name
Test status
Simulation time 500084667 ps
CPU time 1.51 seconds
Started Aug 11 07:17:03 PM PDT 24
Finished Aug 11 07:17:05 PM PDT 24
Peak memory 207476 kb
Host smart-1a7bc318-b290-4941-b581-2cf93c14b5a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399038164 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.usbdev_tx_rx_disruption.2399038164
Directory /workspace/92.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/93.usbdev_endpoint_types.2573900551
Short name T1839
Test name
Test status
Simulation time 261964380 ps
CPU time 1.15 seconds
Started Aug 11 07:17:09 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207528 kb
Host smart-0fadef89-e393-4594-b93f-2930fbd28012
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2573900551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.2573900551
Directory /workspace/93.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/93.usbdev_tx_rx_disruption.2836439513
Short name T1509
Test name
Test status
Simulation time 504002369 ps
CPU time 1.47 seconds
Started Aug 11 07:16:51 PM PDT 24
Finished Aug 11 07:16:52 PM PDT 24
Peak memory 207600 kb
Host smart-1d6694c2-f8a4-484a-84d3-5545a67cb5b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836439513 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.usbdev_tx_rx_disruption.2836439513
Directory /workspace/93.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/94.usbdev_endpoint_types.2464670552
Short name T515
Test name
Test status
Simulation time 240172997 ps
CPU time 1.06 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207508 kb
Host smart-31462205-1492-4079-a62f-74ce3a16d02f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2464670552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.2464670552
Directory /workspace/94.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/94.usbdev_tx_rx_disruption.3017961771
Short name T3423
Test name
Test status
Simulation time 447500447 ps
CPU time 1.35 seconds
Started Aug 11 07:16:53 PM PDT 24
Finished Aug 11 07:16:54 PM PDT 24
Peak memory 207600 kb
Host smart-98d649e3-ad4f-4d36-b799-374d435b8187
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017961771 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.usbdev_tx_rx_disruption.3017961771
Directory /workspace/94.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/95.usbdev_endpoint_types.3276587485
Short name T449
Test name
Test status
Simulation time 716371957 ps
CPU time 1.8 seconds
Started Aug 11 07:17:07 PM PDT 24
Finished Aug 11 07:17:09 PM PDT 24
Peak memory 207568 kb
Host smart-9313c6c9-5588-400e-a1a3-cfcbe66268b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3276587485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.3276587485
Directory /workspace/95.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/95.usbdev_tx_rx_disruption.3301452077
Short name T200
Test name
Test status
Simulation time 582135846 ps
CPU time 1.64 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 207548 kb
Host smart-7151c346-3cff-4302-bc2f-abbbf0a1ae85
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301452077 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.usbdev_tx_rx_disruption.3301452077
Directory /workspace/95.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/96.usbdev_tx_rx_disruption.2844285041
Short name T2432
Test name
Test status
Simulation time 541872768 ps
CPU time 1.52 seconds
Started Aug 11 07:16:56 PM PDT 24
Finished Aug 11 07:16:58 PM PDT 24
Peak memory 207500 kb
Host smart-17e27f13-cce2-4f77-9cc3-64bfc01e5ae5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844285041 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.usbdev_tx_rx_disruption.2844285041
Directory /workspace/96.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/97.usbdev_endpoint_types.3617504266
Short name T246
Test name
Test status
Simulation time 276930852 ps
CPU time 1.12 seconds
Started Aug 11 07:16:59 PM PDT 24
Finished Aug 11 07:17:00 PM PDT 24
Peak memory 207560 kb
Host smart-718b3331-37ee-4600-867f-71270636c97c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3617504266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.3617504266
Directory /workspace/97.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/97.usbdev_tx_rx_disruption.1615301187
Short name T1001
Test name
Test status
Simulation time 505806596 ps
CPU time 1.51 seconds
Started Aug 11 07:17:05 PM PDT 24
Finished Aug 11 07:17:07 PM PDT 24
Peak memory 207536 kb
Host smart-a46f1fb6-6e39-4d74-82f5-885aac97a8ec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615301187 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.usbdev_tx_rx_disruption.1615301187
Directory /workspace/97.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/98.usbdev_endpoint_types.3250550218
Short name T439
Test name
Test status
Simulation time 637904368 ps
CPU time 1.57 seconds
Started Aug 11 07:17:00 PM PDT 24
Finished Aug 11 07:17:02 PM PDT 24
Peak memory 207508 kb
Host smart-56c44f79-4ab0-43b8-9384-438cef304712
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3250550218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.3250550218
Directory /workspace/98.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/98.usbdev_tx_rx_disruption.1897533724
Short name T2817
Test name
Test status
Simulation time 568814104 ps
CPU time 1.61 seconds
Started Aug 11 07:17:08 PM PDT 24
Finished Aug 11 07:17:10 PM PDT 24
Peak memory 207536 kb
Host smart-f1a6b367-c98f-491e-9b38-295307f076cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897533724 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.usbdev_tx_rx_disruption.1897533724
Directory /workspace/98.usbdev_tx_rx_disruption/latest


Test location /workspace/coverage/default/99.usbdev_endpoint_types.186777363
Short name T3202
Test name
Test status
Simulation time 282024193 ps
CPU time 1.2 seconds
Started Aug 11 07:16:58 PM PDT 24
Finished Aug 11 07:16:59 PM PDT 24
Peak memory 207504 kb
Host smart-b8dbec3d-a79d-4f3b-9638-7ffdca72f233
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=186777363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.186777363
Directory /workspace/99.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/99.usbdev_tx_rx_disruption.3731378315
Short name T3352
Test name
Test status
Simulation time 509140213 ps
CPU time 1.65 seconds
Started Aug 11 07:16:56 PM PDT 24
Finished Aug 11 07:16:58 PM PDT 24
Peak memory 207572 kb
Host smart-01b18bd9-b8fb-4196-a308-325af48e6b2f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731378315 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.usbdev_tx_rx_disruption.3731378315
Directory /workspace/99.usbdev_tx_rx_disruption/latest
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