Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	170048	1			T1	2		T2	2		T3	3
all_values[1]	170048	1			T1	2		T2	2		T3	3
all_values[2]	170048	1			T1	2		T2	2		T3	3
all_values[3]	170048	1			T1	2		T2	2		T3	3
all_values[4]	170048	1			T1	2		T2	2		T3	3
all_values[5]	170048	1			T1	2		T2	2		T3	3
all_values[6]	170048	1			T1	2		T2	2		T3	3
all_values[7]	170048	1			T1	2		T2	2		T3	3
all_values[8]	170048	1			T1	2		T2	2		T3	3
all_values[9]	170048	1			T1	2		T2	2		T3	3
all_values[10]	170048	1			T1	2		T2	2		T3	3
all_values[11]	170048	1			T1	2		T2	2		T3	3
all_values[12]	170048	1			T1	2		T2	2		T3	3
all_values[13]	170048	1			T1	2		T2	2		T3	3
all_values[14]	170048	1			T1	2		T2	2		T3	3
all_values[15]	170048	1			T1	2		T2	2		T3	3
all_values[16]	170048	1			T1	2		T2	2		T3	3
all_values[17]	170048	1			T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5431952

1

T1

64

T2

64

T3

93

auto[1]

9584

1

T3

3

T26

3

T34

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4666319

1

T1

60

T2

53

T3

83

auto[1]

775217

1

T1

4

T2

11

T3

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142211	1			T1	2		T2	2		T3	3
all_values[0]	auto[0]	auto[1]	24507	1			T33	19		T87	3		T88	1
all_values[0]	auto[1]	auto[0]	3228	1			T34	3		T29	5		T30	3
all_values[0]	auto[1]	auto[1]	102	1			T345	1		T346	1		T347	1
all_values[1]	auto[0]	auto[0]	165561	1			T1	2		T26	3		T34	3
all_values[1]	auto[0]	auto[1]	3050	1			T2	2		T27	2		T28	2
all_values[1]	auto[1]	auto[0]	551	1			T3	2		T26	1		T6	1
all_values[1]	auto[1]	auto[1]	886	1			T3	1		T26	1		T6	1
all_values[2]	auto[0]	auto[0]	4225	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	165580	1			T1	1		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	129	1			T42	1		T58	1		T59	1
all_values[2]	auto[1]	auto[1]	114	1			T42	1		T58	1		T59	1
all_values[3]	auto[0]	auto[0]	168194	1			T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	294	1			T27	1		T60	1		T61	1
all_values[3]	auto[1]	auto[0]	1499	1			T62	1393		T222	4		T225	1
all_values[3]	auto[1]	auto[1]	61	1			T62	1		T222	1		T225	3
all_values[4]	auto[0]	auto[0]	4198	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	165689	1			T1	1		T2	1		T3	2
all_values[4]	auto[1]	auto[0]	102	1			T63	1		T222	5		T223	1
all_values[4]	auto[1]	auto[1]	59	1			T63	1		T223	5		T224	1
all_values[5]	auto[0]	auto[0]	169553	1			T1	2		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	340	1			T26	1		T6	1		T7	1
all_values[5]	auto[1]	auto[0]	109	1			T222	5		T225	1		T223	1
all_values[5]	auto[1]	auto[1]	46	1			T222	1		T226	1		T310	1
all_values[6]	auto[0]	auto[0]	169653	1			T1	2		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	209	1			T7	1		T64	1		T100	1
all_values[6]	auto[1]	auto[0]	76	1			T222	2		T224	1		T227	3
all_values[6]	auto[1]	auto[1]	110	1			T26	1		T41	1		T65	1
all_values[7]	auto[0]	auto[0]	114995	1			T1	2		T26	2		T27	2
all_values[7]	auto[0]	auto[1]	54876	1			T2	2		T3	3		T26	3
all_values[7]	auto[1]	auto[0]	112	1			T44	1		T45	1		T46	1
all_values[7]	auto[1]	auto[1]	65	1			T44	1		T45	1		T46	1
all_values[8]	auto[0]	auto[0]	169321	1			T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	56	1			T222	1		T225	1		T223	2
all_values[8]	auto[1]	auto[0]	598	1			T50	10		T47	10		T48	10
all_values[8]	auto[1]	auto[1]	73	1			T47	1		T48	1		T49	1
all_values[9]	auto[0]	auto[0]	169804	1			T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	66	1			T222	2		T225	1		T226	1
all_values[9]	auto[1]	auto[0]	99	1			T55	3		T56	3		T57	3
all_values[9]	auto[1]	auto[1]	79	1			T55	2		T56	2		T57	2
all_values[10]	auto[0]	auto[0]	169535	1			T1	2		T2	1		T3	3
all_values[10]	auto[0]	auto[1]	339	1			T2	1		T28	1		T31	1
all_values[10]	auto[1]	auto[0]	103	1			T222	5		T225	3		T223	1
all_values[10]	auto[1]	auto[1]	71	1			T223	1		T227	3		T226	2
all_values[11]	auto[0]	auto[0]	168987	1			T1	2		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	787	1			T70	3		T71	3		T74	3
all_values[11]	auto[1]	auto[0]	150	1			T69	1		T72	1		T73	1
all_values[11]	auto[1]	auto[1]	124	1			T69	1		T72	1		T73	1
all_values[12]	auto[0]	auto[0]	169675	1			T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	204	1			T75	3		T76	3		T77	3
all_values[12]	auto[1]	auto[0]	97	1			T78	2		T79	2		T80	2
all_values[12]	auto[1]	auto[1]	72	1			T78	1		T79	1		T80	1
all_values[13]	auto[0]	auto[0]	169710	1			T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	61	1			T84	1		T85	1		T86	1
all_values[13]	auto[1]	auto[0]	151	1			T81	1		T82	1		T83	1
all_values[13]	auto[1]	auto[1]	126	1			T81	1		T82	1		T83	1
all_values[14]	auto[0]	auto[0]	35412	1			T1	1		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	134488	1			T1	1		T26	3		T27	1
all_values[14]	auto[1]	auto[0]	85	1			T222	2		T223	2		T224	1
all_values[14]	auto[1]	auto[1]	63	1			T222	4		T225	1		T223	5
all_values[15]	auto[0]	auto[0]	4259	1			T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	165646	1			T1	1		T2	1		T3	2
all_values[15]	auto[1]	auto[0]	79	1			T222	4		T225	2		T223	1
all_values[15]	auto[1]	auto[1]	64	1			T222	2		T223	2		T224	2
all_values[16]	auto[0]	auto[0]	169108	1			T1	2		T2	1		T3	3
all_values[16]	auto[0]	auto[1]	772	1			T2	1		T27	1		T28	1
all_values[16]	auto[1]	auto[0]	104	1			T66	4		T67	4		T68	4
all_values[16]	auto[1]	auto[1]	64	1			T66	4		T67	4		T68	4
all_values[17]	auto[0]	auto[0]	113894	1			T1	2		T26	2		T27	2
all_values[17]	auto[0]	auto[1]	56021	1			T2	2		T3	3		T26	3
all_values[17]	auto[1]	auto[0]	80	1			T54	1		T222	1		T223	1
all_values[17]	auto[1]	auto[1]	53	1			T54	1		T222	3		T225	1