Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1209	1			T27	6		T110	5		T111	6
range_16_to_126	150073	1			T1	87		T2	10		T3	2
fifteen	1571	1			T27	7		T110	4		T519	1
range_2_to_14	18263	1			T27	85		T29	10		T4	2
seven	699	1			T27	9		T111	7		T380	1
one	1499	1			T27	6		T18	1		T118	2
zero	1977	1			T27	9		T5	63		T110	7

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

13405

1

T1

18

T2

1

T27

129

three

14954

1

T34

1

T27

125

T106

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	18	1			T174	1		T426	1		T520	1
range_127	three	31	1			T27	1		T110	1		T333	1
range_16_to_126	seven	12014	1			T1	18		T2	1		T27	124
range_16_to_126	three	12458	1			T34	1		T27	116		T106	2
fifteen	seven	99	1			T333	1		T192	17		T521	35
fifteen	three	79	1			T110	1		T111	1		T176	1
range_2_to_14	seven	1032	1			T27	5		T29	7		T61	1
range_2_to_14	three	2109	1			T27	7		T17	2		T109	1
seven	seven	11	1			T111	1		T522	1		T523	1
seven	three	42	1			T27	4		T111	1		T524	1
one	seven	125	1			T162	3		T525	1		T526	12
one	three	120	1			T333	1		T192	1		T492	1
zero	seven	117	1			T5	9		T192	1		T527	1
zero	three	157	1			T27	1		T5	9		T110	1