Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 11 0 11 100.00
Crosses 18 0 18 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dir 2 0 2 100.00 100 1 1 2
cp_pkt_len 9 0 9 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pktlen_X_dir 18 0 18 100.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 108051 1 T1 42 T2 5 T3 1
auto[1] 45665 1 T1 42 T2 5 T3 1



Summary for Variable cp_pkt_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 9 0 9 100.00


User Defined Bins for cp_pkt_len

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
max_len 29151 1 T1 2 T33 19 T87 2
max_len_m1 801 1 T1 6 T4 4 T5 2
max_len_m2 843 1 T1 4 T4 2 T60 3
max_len_m3 845 1 T1 2 T2 2 T4 2
five 1082 1 T4 2 T16 4 T60 11
four 1128 1 T1 2 T4 2 T16 2
three 817 1 T71 1 T60 12 T154 2
one 902 1 T60 15 T154 1 T61 1
zero 11618 1 T1 2 T2 3 T28 6



Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 0 18 100.00


Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins
cp_pkt_lencp_dirCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
max_len auto[0] 23496 1 T1 1 T33 19 T87 1
max_len auto[1] 5655 1 T1 1 T87 1 T16 1
max_len_m1 auto[0] 549 1 T1 3 T4 2 T5 1
max_len_m1 auto[1] 252 1 T1 3 T4 2 T5 1
max_len_m2 auto[0] 559 1 T1 2 T4 1 T60 3
max_len_m2 auto[1] 284 1 T1 2 T4 1 T274 1
max_len_m3 auto[0] 569 1 T1 1 T2 1 T4 1
max_len_m3 auto[1] 276 1 T1 1 T2 1 T4 1
five auto[0] 579 1 T4 1 T16 2 T60 4
five auto[1] 503 1 T4 1 T16 2 T60 7
four auto[0] 564 1 T1 1 T4 1 T16 1
four auto[1] 564 1 T1 1 T4 1 T16 1
three auto[0] 410 1 T60 4 T154 2 T107 1
three auto[1] 407 1 T71 1 T60 8 T528 1
one auto[0] 403 1 T60 7 T154 1 T61 1
one auto[1] 499 1 T60 8 T251 1 T529 1
zero auto[0] 582 1 T28 1 T4 1 T153 1
zero auto[1] 11036 1 T1 2 T2 3 T28 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%