Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69182

1

T1

42

T2

5

T3

1

auto[1]

77316

1

T1

48

T2

9

T3

2

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	12264	1			T1	24		T27	56		T28	5
endpoints[0x1]	11898	1			T2	2		T27	26		T28	3
endpoints[0x2]	10659	1			T1	24		T28	4		T31	6
endpoints[0x3]	14099	1			T34	1		T27	33		T71	4
endpoints[0x4]	11219	1			T28	2		T71	8		T5	12
endpoints[0x5]	11455	1			T2	6		T28	2		T30	4
endpoints[0x6]	14775	1			T1	9		T2	1		T26	3
endpoints[0x7]	12455	1			T1	9		T2	2		T27	56
endpoints[0x8]	12123	1			T2	3		T28	4		T248	1
endpoints[0x9]	10713	1			T28	1		T4	15		T5	12
endpoints[0xa]	12800	1			T1	24		T3	3		T27	55
endpoints[0xb]	12038	1			T27	28		T28	4		T69	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	161	1			T2	2		T28	3		T107	2
ack	38099	1			T1	24		T2	2		T3	1
data1	50461	1			T1	20		T2	5		T27	72
data0	57718	1			T1	46		T2	5		T3	2

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	13	1			T28	1		T183	1		T319	1
nak	auto[1]	endpoints[0x1]	14	1			T183	1		T320	1		T321	1
nak	auto[1]	endpoints[0x2]	13	1			T107	1		T320	1		T322	2
nak	auto[1]	endpoints[0x3]	10	1			T321	1		T323	1		T324	1
nak	auto[1]	endpoints[0x4]	11	1			T321	2		T319	1		T325	1
nak	auto[1]	endpoints[0x5]	6	1			T28	1		T322	1		T326	1
nak	auto[1]	endpoints[0x6]	13	1			T319	1		T327	1		T328	1
nak	auto[1]	endpoints[0x7]	21	1			T2	1		T107	1		T329	1
nak	auto[1]	endpoints[0x8]	17	1			T2	1		T28	1		T183	1
nak	auto[1]	endpoints[0x9]	19	1			T319	1		T330	1		T331	2
nak	auto[1]	endpoints[0xa]	10	1			T183	1		T321	1		T327	1
nak	auto[1]	endpoints[0xb]	14	1			T332	1		T319	1		T326	2
ack	auto[1]	endpoints[0x0]	3258	1			T1	8		T27	15		T28	1
ack	auto[1]	endpoints[0x1]	3325	1			T28	1		T43	2		T70	1
ack	auto[1]	endpoints[0x2]	2945	1			T1	8		T28	1		T31	2
ack	auto[1]	endpoints[0x3]	3115	1			T71	1		T5	4		T60	30
ack	auto[1]	endpoints[0x4]	3200	1			T71	2		T5	4		T22	36
ack	auto[1]	endpoints[0x5]	3305	1			T2	2		T30	1		T60	27
ack	auto[1]	endpoints[0x6]	3497	1			T26	1		T27	18		T29	1
ack	auto[1]	endpoints[0x7]	2911	1			T27	16		T29	2		T4	5
ack	auto[1]	endpoints[0x8]	3207	1			T5	4		T60	29		T161	1
ack	auto[1]	endpoints[0x9]	2997	1			T4	5		T5	4		T60	24
ack	auto[1]	endpoints[0xa]	3187	1			T1	8		T3	1		T27	12
ack	auto[1]	endpoints[0xb]	3152	1			T27	14		T28	1		T4	5
data1	auto[0]	endpoints[0x0]	2424	1			T1	4		T43	1		T60	21
data1	auto[0]	endpoints[0x1]	2126	1			T2	1		T43	2		T70	1
data1	auto[0]	endpoints[0x2]	1960	1			T28	1		T70	2		T60	16
data1	auto[0]	endpoints[0x3]	3454	1			T27	11		T71	1		T5	2
data1	auto[0]	endpoints[0x4]	1969	1			T71	2		T5	2		T22	18
data1	auto[0]	endpoints[0x5]	1987	1			T2	2		T30	1		T60	14
data1	auto[0]	endpoints[0x6]	3386	1			T29	1		T33	9		T134	1
data1	auto[0]	endpoints[0x7]	2814	1			T28	2		T29	2		T4	1
data1	auto[0]	endpoints[0x8]	2357	1			T2	1		T28	1		T4	2
data1	auto[0]	endpoints[0x9]	1921	1			T4	2		T5	2		T60	14
data1	auto[0]	endpoints[0xa]	2725	1			T1	2		T27	11		T28	1
data1	auto[0]	endpoints[0xb]	2411	1			T94	495		T4	2		T5	1
data1	auto[1]	endpoints[0x0]	1763	1			T1	4		T27	9		T43	1
data1	auto[1]	endpoints[0x1]	1778	1			T43	2		T70	1		T5	2
data1	auto[1]	endpoints[0x2]	1605	1			T1	4		T28	1		T31	1
data1	auto[1]	endpoints[0x3]	1719	1			T71	1		T5	2		T60	15
data1	auto[1]	endpoints[0x4]	1774	1			T28	1		T71	2		T5	2
data1	auto[1]	endpoints[0x5]	1788	1			T2	1		T30	1		T60	13
data1	auto[1]	endpoints[0x6]	1933	1			T27	13		T29	1		T16	22
data1	auto[1]	endpoints[0x7]	1597	1			T27	10		T29	2		T4	4
data1	auto[1]	endpoints[0x8]	1795	1			T28	1		T5	2		T60	14
data1	auto[1]	endpoints[0x9]	1673	1			T28	1		T4	3		T5	2
data1	auto[1]	endpoints[0xa]	1761	1			T1	6		T27	8		T4	2
data1	auto[1]	endpoints[0xb]	1741	1			T27	10		T28	1		T4	2
data0	auto[0]	endpoints[0x0]	3244	1			T1	4		T27	26		T28	1
data0	auto[0]	endpoints[0x1]	3041	1			T27	26		T43	2		T70	1
data0	auto[0]	endpoints[0x2]	2708	1			T1	8		T32	1		T70	3
data0	auto[0]	endpoints[0x3]	4335	1			T34	1		T27	22		T71	1
data0	auto[0]	endpoints[0x4]	2734	1			T28	1		T71	2		T5	2
data0	auto[0]	endpoints[0x5]	2769	1			T30	1		T88	1		T60	15
data0	auto[0]	endpoints[0x6]	4319	1			T1	9		T2	1		T26	1
data0	auto[0]	endpoints[0x7]	3701	1			T1	9		T27	24		T28	3
data0	auto[0]	endpoints[0x8]	3257	1			T248	1		T4	3		T5	2
data0	auto[0]	endpoints[0x9]	2686	1			T4	3		T5	2		T60	15
data0	auto[0]	endpoints[0xa]	3612	1			T1	6		T3	1		T27	20
data0	auto[0]	endpoints[0xb]	3233	1			T28	2		T69	1		T94	495
data0	auto[1]	endpoints[0x0]	1557	1			T1	4		T27	6		T28	2
data0	auto[1]	endpoints[0x1]	1609	1			T2	1		T28	2		T43	1
data0	auto[1]	endpoints[0x2]	1424	1			T1	4		T28	1		T31	3
data0	auto[1]	endpoints[0x3]	1464	1			T5	2		T60	15		T107	1
data0	auto[1]	endpoints[0x4]	1526	1			T5	2		T22	18		T60	18
data0	auto[1]	endpoints[0x5]	1597	1			T2	1		T28	1		T60	14
data0	auto[1]	endpoints[0x6]	1616	1			T26	1		T27	5		T16	23
data0	auto[1]	endpoints[0x7]	1405	1			T2	1		T27	6		T4	1
data0	auto[1]	endpoints[0x8]	1488	1			T2	1		T28	1		T5	2
data0	auto[1]	endpoints[0x9]	1413	1			T4	2		T5	2		T60	12
data0	auto[1]	endpoints[0xa]	1499	1			T1	2		T3	1		T27	4
data0	auto[1]	endpoints[0xb]	1481	1			T27	4		T4	3		T5	1