Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7886 1 T27 168 T106 3 T4 4
auto[1] 53371 1 T1 45 T2 5 T3 1


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 53317 1 T1 27 T2 5 T3 1
auto[1] 7940 1 T1 18 T106 2 T4 8


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55648 1 T1 45 T2 5 T3 1
auto[1] 5609 1 T27 163 T106 1 T17 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4184 1 T27 126 T106 2 T4 7
pkt_types[PidTypeInToken] 57073 1 T1 45 T2 5 T3 1


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1267 1 T27 33 T106 1 T4 2
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 671 1 T27 8 T110 29 T111 8
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 85 1 T4 2 T61 3 T176 3
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 20 1 T17 1 T393 1 T439 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1436 1 T27 51 T4 3 T110 16
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 607 1 T27 34 T111 27 T392 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 88 1 T106 1 T61 2 T392 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 10 1 T109 1 T465 1 T360 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3539 1 T27 90 T106 1 T17 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2202 1 T27 37 T110 96 T111 20
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 54 1 T17 1 T519 1 T407 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 48 1 T106 1 T362 2 T407 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 41605 1 T1 27 T2 5 T3 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 1990 1 T27 84 T117 1 T111 89
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7574 1 T1 18 T4 6 T61 40
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 61 1 T109 1 T519 1 T380 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%