Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	170048	1			T1	2		T2	2		T3	3
all_pins[1]	170048	1			T1	2		T2	2		T3	3
all_pins[2]	170048	1			T1	2		T2	2		T3	3
all_pins[3]	170048	1			T1	2		T2	2		T3	3
all_pins[4]	170048	1			T1	2		T2	2		T3	3
all_pins[5]	170048	1			T1	2		T2	2		T3	3
all_pins[6]	170048	1			T1	2		T2	2		T3	3
all_pins[7]	170048	1			T1	2		T2	2		T3	3
all_pins[8]	170048	1			T1	2		T2	2		T3	3
all_pins[9]	170048	1			T1	2		T2	2		T3	3
all_pins[10]	170048	1			T1	2		T2	2		T3	3
all_pins[11]	170048	1			T1	2		T2	2		T3	3
all_pins[12]	170048	1			T1	2		T2	2		T3	3
all_pins[13]	170048	1			T1	2		T2	2		T3	3
all_pins[14]	170048	1			T1	2		T2	2		T3	3
all_pins[15]	170048	1			T1	2		T2	2		T3	3
all_pins[16]	170048	1			T1	2		T2	2		T3	3
all_pins[17]	170048	1			T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5439304	1			T1	64		T2	64		T3	95
values[0x1]	2232	1			T3	1		T26	2		T69	1
transitions[0x0=>0x1]	1968	1			T3	1		T26	2		T69	1
transitions[0x1=>0x0]	1968	1			T3	1		T26	2		T69	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	169946	1			T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	102	1			T345	1		T346	1		T347	1
all_pins[0]	transitions[0x0=>0x1]	93	1			T345	1		T346	1		T347	1
all_pins[0]	transitions[0x1=>0x0]	877	1			T3	1		T26	1		T6	1
all_pins[1]	values[0x0]	169162	1			T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	886	1			T3	1		T26	1		T6	1
all_pins[1]	transitions[0x0=>0x1]	876	1			T3	1		T26	1		T6	1
all_pins[1]	transitions[0x1=>0x0]	104	1			T42	1		T58	1		T59	1
all_pins[2]	values[0x0]	169934	1			T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	114	1			T42	1		T58	1		T59	1
all_pins[2]	transitions[0x0=>0x1]	99	1			T42	1		T58	1		T59	1
all_pins[2]	transitions[0x1=>0x0]	46	1			T62	1		T222	1		T225	3
all_pins[3]	values[0x0]	169987	1			T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	61	1			T62	1		T222	1		T225	3
all_pins[3]	transitions[0x0=>0x1]	48	1			T62	1		T222	1		T225	3
all_pins[3]	transitions[0x1=>0x0]	46	1			T63	1		T223	3		T310	1
all_pins[4]	values[0x0]	169989	1			T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	59	1			T63	1		T223	5		T224	1
all_pins[4]	transitions[0x0=>0x1]	48	1			T63	1		T223	5		T224	1
all_pins[4]	transitions[0x1=>0x0]	35	1			T222	1		T226	1		T310	1
all_pins[5]	values[0x0]	170002	1			T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	46	1			T222	1		T226	1		T310	1
all_pins[5]	transitions[0x0=>0x1]	34	1			T222	1		T226	1		T310	1
all_pins[5]	transitions[0x1=>0x0]	98	1			T26	1		T41	1		T65	1
all_pins[6]	values[0x0]	169938	1			T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	110	1			T26	1		T41	1		T65	1
all_pins[6]	transitions[0x0=>0x1]	99	1			T26	1		T41	1		T65	1
all_pins[6]	transitions[0x1=>0x0]	54	1			T44	1		T45	1		T46	1
all_pins[7]	values[0x0]	169983	1			T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	65	1			T44	1		T45	1		T46	1
all_pins[7]	transitions[0x0=>0x1]	50	1			T44	1		T45	1		T46	1
all_pins[7]	transitions[0x1=>0x0]	58	1			T47	1		T48	1		T49	1
all_pins[8]	values[0x0]	169975	1			T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	73	1			T47	1		T48	1		T49	1
all_pins[8]	transitions[0x0=>0x1]	57	1			T47	1		T48	1		T49	1
all_pins[8]	transitions[0x1=>0x0]	63	1			T55	2		T56	2		T57	2
all_pins[9]	values[0x0]	169969	1			T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	79	1			T55	2		T56	2		T57	2
all_pins[9]	transitions[0x0=>0x1]	57	1			T55	2		T56	2		T57	2
all_pins[9]	transitions[0x1=>0x0]	49	1			T227	3		T226	1		T310	2
all_pins[10]	values[0x0]	169977	1			T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	71	1			T223	1		T227	3		T226	2
all_pins[10]	transitions[0x0=>0x1]	47	1			T227	2		T226	1		T310	3
all_pins[10]	transitions[0x1=>0x0]	100	1			T69	1		T72	1		T73	1
all_pins[11]	values[0x0]	169924	1			T1	2		T2	2		T3	3
all_pins[11]	values[0x1]	124	1			T69	1		T72	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	107	1			T69	1		T72	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	55	1			T78	1		T79	1		T80	1
all_pins[12]	values[0x0]	169976	1			T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	72	1			T78	1		T79	1		T80	1
all_pins[12]	transitions[0x0=>0x1]	51	1			T78	1		T79	1		T80	1
all_pins[12]	transitions[0x1=>0x0]	105	1			T81	1		T82	1		T83	1
all_pins[13]	values[0x0]	169922	1			T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	126	1			T81	1		T82	1		T83	1
all_pins[13]	transitions[0x0=>0x1]	106	1			T81	1		T82	1		T83	1
all_pins[13]	transitions[0x1=>0x0]	43	1			T222	1		T225	1		T223	2
all_pins[14]	values[0x0]	169985	1			T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	63	1			T222	4		T225	1		T223	5
all_pins[14]	transitions[0x0=>0x1]	45	1			T222	2		T225	1		T223	4
all_pins[14]	transitions[0x1=>0x0]	46	1			T223	1		T227	2		T310	2
all_pins[15]	values[0x0]	169984	1			T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	64	1			T222	2		T223	2		T224	2
all_pins[15]	transitions[0x0=>0x1]	48	1			T222	2		T223	1		T224	1
all_pins[15]	transitions[0x1=>0x0]	48	1			T66	4		T67	4		T68	4
all_pins[16]	values[0x0]	169984	1			T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	64	1			T66	4		T67	4		T68	4
all_pins[16]	transitions[0x0=>0x1]	50	1			T66	4		T67	4		T68	4
all_pins[16]	transitions[0x1=>0x0]	39	1			T54	1		T222	2		T225	1
all_pins[17]	values[0x0]	169995	1			T1	2		T2	2		T3	3
all_pins[17]	values[0x1]	53	1			T54	1		T222	3		T225	1
all_pins[17]	transitions[0x0=>0x1]	53	1			T54	1		T222	3		T225	1