Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4319	1			T27	141		T17	1		T18	2
invalid_ep[0xd]	4435	1			T27	134		T17	1		T154	16
invalid_ep[0xe]	4378	1			T27	112		T106	1		T17	1
invalid_ep[0xf]	4390	1			T27	130		T17	1		T362	1
endpoints[0x0]	13350	1			T1	17		T27	115		T28	3
endpoints[0x1]	12825	1			T2	2		T27	116		T28	2
endpoints[0x2]	11794	1			T1	17		T27	117		T28	3
endpoints[0x3]	14954	1			T34	1		T27	125		T106	2
endpoints[0x4]	12230	1			T27	113		T28	2		T106	1
endpoints[0x5]	12212	1			T2	4		T27	124		T28	1
endpoints[0x6]	14944	1			T1	18		T2	1		T26	2
endpoints[0x7]	13405	1			T1	18		T2	1		T27	129
endpoints[0x8]	13140	1			T2	2		T27	117		T28	3
endpoints[0x9]	11864	1			T27	114		T28	1		T4	11
endpoints[0xa]	13654	1			T1	17		T3	2		T27	119
endpoints[0xb]	12698	1			T27	120		T28	3		T69	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	21887	1			T1	4		T34	1		T27	528
pkt_types[PidTypeOutToken]	75192	1			T1	38		T2	5		T3	1
pkt_types[PidTypeInToken]	60914	1			T1	45		T2	5		T3	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	956	1			T27	32		T18	1		T109	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	981	1			T27	38		T17	1		T110	20
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	968	1			T27	34		T362	1		T110	24
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	948	1			T27	40		T17	1		T110	30
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1489	1			T27	29		T43	1		T21	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1454	1			T27	27		T43	2		T70	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1375	1			T27	27		T70	3		T110	31
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1555	1			T34	1		T27	41		T71	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1572	1			T27	33		T71	2		T110	24
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1472	1			T27	35		T30	1		T61	2
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1607	1			T27	36		T29	1		T160	20
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1443	1			T27	36		T29	3		T4	4
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1637	1			T27	25		T161	1		T110	26
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1493	1			T27	33		T4	2		T163	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1478	1			T1	4		T27	31		T153	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1459	1			T27	31		T5	2		T17	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1480	1			T27	43		T109	1		T154	6
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1521	1			T27	28		T154	16		T150	13
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1523	1			T27	28		T17	1		T362	1
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1503	1			T27	23		T362	1		T154	14
pkt_types[PidTypeOutToken]	endpoints[0x0]	5770	1			T1	8		T27	24		T28	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	5312	1			T2	1		T27	26		T43	2
pkt_types[PidTypeOutToken]	endpoints[0x2]	4770	1			T1	8		T27	29		T28	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	7630	1			T27	25		T71	1		T5	4
pkt_types[PidTypeOutToken]	endpoints[0x4]	4695	1			T27	26		T28	1		T71	2
pkt_types[PidTypeOutToken]	endpoints[0x5]	4934	1			T2	2		T27	28		T30	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	7603	1			T1	9		T2	1		T26	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	6435	1			T1	9		T27	27		T28	5
pkt_types[PidTypeOutToken]	endpoints[0x8]	5509	1			T2	1		T27	29		T28	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	4600	1			T27	31		T4	3		T5	4
pkt_types[PidTypeOutToken]	endpoints[0xa]	6242	1			T1	4		T3	1		T27	31
pkt_types[PidTypeOutToken]	endpoints[0xb]	5665	1			T27	36		T28	2		T69	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	940	1			T27	31		T18	1		T109	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	984	1			T27	31		T110	24		T111	20
pkt_types[PidTypeInToken]	invalid_ep[0xe]	937	1			T27	24		T106	1		T110	21
pkt_types[PidTypeInToken]	invalid_ep[0xf]	980	1			T27	34		T110	28		T111	17
pkt_types[PidTypeInToken]	endpoints[0x0]	5050	1			T1	9		T27	35		T28	2
pkt_types[PidTypeInToken]	endpoints[0x1]	4979	1			T2	1		T27	27		T28	2
pkt_types[PidTypeInToken]	endpoints[0x2]	4580	1			T1	9		T27	37		T28	2
pkt_types[PidTypeInToken]	endpoints[0x3]	4727	1			T27	30		T106	1		T71	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4861	1			T27	22		T28	1		T106	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4704	1			T2	2		T27	35		T28	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4681	1			T1	9		T26	1		T27	38
pkt_types[PidTypeInToken]	endpoints[0x7]	4455	1			T1	9		T2	1		T27	30
pkt_types[PidTypeInToken]	endpoints[0x8]	4899	1			T2	1		T27	33		T28	2
pkt_types[PidTypeInToken]	endpoints[0x9]	4754	1			T27	27		T28	1		T4	6
pkt_types[PidTypeInToken]	endpoints[0xa]	4846	1			T1	9		T3	1		T27	29
pkt_types[PidTypeInToken]	endpoints[0xb]	4537	1			T27	28		T28	1		T4	6