Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	257	1			T222	7		T225	4		T223	7
all_values[1]	257	1			T222	7		T225	4		T223	7
all_values[2]	257	1			T222	7		T225	4		T223	7
all_values[3]	257	1			T222	7		T225	4		T223	7
all_values[4]	257	1			T222	7		T225	4		T223	7
all_values[5]	257	1			T222	7		T225	4		T223	7
all_values[6]	257	1			T222	7		T225	4		T223	7
all_values[7]	257	1			T222	7		T225	4		T223	7
all_values[8]	257	1			T222	7		T225	4		T223	7
all_values[9]	257	1			T222	7		T225	4		T223	7
all_values[10]	257	1			T222	7		T225	4		T223	7
all_values[11]	257	1			T222	7		T225	4		T223	7
all_values[12]	257	1			T222	7		T225	4		T223	7
all_values[13]	257	1			T222	7		T225	4		T223	7
all_values[14]	257	1			T222	7		T225	4		T223	7
all_values[15]	257	1			T222	7		T225	4		T223	7
all_values[16]	257	1			T222	7		T225	4		T223	7
all_values[17]	257	1			T222	7		T225	4		T223	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6131

1

T222

166

T225

97

T223

163

auto[1]

2093

1

T222

58

T225

31

T223

61

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5637

1

T222

157

T225

95

T223

137

auto[1]

2587

1

T222

67

T225

33

T223

87

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4830

1

T222

133

T225

78

T223

116

auto[1]

3394

1

T222

91

T225

50

T223

108

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	84	1			T222	5		T225	2		T224	5
all_values[0]	auto[0]	auto[1]	auto[0]	70	1			T225	2		T223	3		T224	2
all_values[0]	auto[1]	auto[0]	auto[1]	59	1			T222	2		T223	1		T227	2
all_values[0]	auto[1]	auto[1]	auto[1]	44	1			T223	3		T336	1		T337	1
all_values[1]	auto[0]	auto[0]	auto[0]	82	1			T222	2		T225	1		T223	3
all_values[1]	auto[0]	auto[1]	auto[0]	82	1			T222	3		T225	1		T223	3
all_values[1]	auto[1]	auto[0]	auto[1]	52	1			T222	1		T225	1		T227	3
all_values[1]	auto[1]	auto[1]	auto[1]	41	1			T222	1		T225	1		T223	1
all_values[2]	auto[0]	auto[0]	auto[0]	36	1			T222	2		T225	1		T226	1
all_values[2]	auto[0]	auto[0]	auto[1]	52	1			T222	3		T225	2		T223	4
all_values[2]	auto[0]	auto[1]	auto[0]	32	1			T227	3		T226	1		T310	2
all_values[2]	auto[0]	auto[1]	auto[1]	30	1			T223	1		T224	2		T338	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1			T222	2		T225	1		T223	1
all_values[2]	auto[1]	auto[1]	auto[1]	41	1			T223	1		T224	1		T227	3
all_values[3]	auto[0]	auto[0]	auto[0]	60	1			T222	2		T223	2		T227	1
all_values[3]	auto[0]	auto[0]	auto[1]	20	1			T225	1		T337	2		T338	1
all_values[3]	auto[0]	auto[1]	auto[0]	53	1			T222	2		T223	1		T227	1
all_values[3]	auto[0]	auto[1]	auto[1]	24	1			T225	2		T223	1		T224	3
all_values[3]	auto[1]	auto[0]	auto[1]	51	1			T222	3		T223	1		T224	3
all_values[3]	auto[1]	auto[1]	auto[1]	49	1			T225	1		T223	2		T224	1
all_values[4]	auto[0]	auto[0]	auto[0]	57	1			T222	3		T225	2		T223	1
all_values[4]	auto[0]	auto[0]	auto[1]	26	1			T224	1		T227	1		T336	1
all_values[4]	auto[0]	auto[1]	auto[0]	42	1			T222	3		T224	1		T226	1
all_values[4]	auto[0]	auto[1]	auto[1]	25	1			T223	3		T339	1		T338	2
all_values[4]	auto[1]	auto[0]	auto[1]	62	1			T222	1		T225	2		T223	1
all_values[4]	auto[1]	auto[1]	auto[1]	45	1			T223	2		T224	2		T227	2
all_values[5]	auto[0]	auto[0]	auto[0]	54	1			T225	3		T224	4		T227	2
all_values[5]	auto[0]	auto[0]	auto[1]	25	1			T223	1		T340	1		T338	1
all_values[5]	auto[0]	auto[1]	auto[0]	58	1			T222	3		T225	1		T223	1
all_values[5]	auto[0]	auto[1]	auto[1]	21	1			T310	1		T341	1		T342	1
all_values[5]	auto[1]	auto[0]	auto[1]	58	1			T222	2		T223	4		T224	2
all_values[5]	auto[1]	auto[1]	auto[1]	41	1			T222	2		T223	1		T226	1
all_values[6]	auto[0]	auto[0]	auto[0]	57	1			T225	2		T223	3		T226	1
all_values[6]	auto[0]	auto[0]	auto[1]	26	1			T222	1		T225	1		T224	2
all_values[6]	auto[0]	auto[1]	auto[0]	38	1			T224	1		T227	2		T226	2
all_values[6]	auto[0]	auto[1]	auto[1]	29	1			T222	1		T223	1		T224	2
all_values[6]	auto[1]	auto[0]	auto[1]	61	1			T222	3		T225	1		T223	1
all_values[6]	auto[1]	auto[1]	auto[1]	46	1			T222	2		T223	2		T227	3
all_values[7]	auto[0]	auto[0]	auto[0]	62	1			T222	2		T225	1		T223	2
all_values[7]	auto[0]	auto[1]	auto[0]	76	1			T222	2		T225	2		T223	2
all_values[7]	auto[1]	auto[0]	auto[1]	66	1			T222	2		T224	3		T227	3
all_values[7]	auto[1]	auto[1]	auto[1]	53	1			T222	1		T225	1		T223	3
all_values[8]	auto[0]	auto[0]	auto[0]	80	1			T222	3		T223	3		T224	3
all_values[8]	auto[0]	auto[1]	auto[0]	73	1			T222	2		T225	2		T223	1
all_values[8]	auto[1]	auto[0]	auto[1]	67	1			T222	2		T225	1		T223	3
all_values[8]	auto[1]	auto[1]	auto[1]	37	1			T225	1		T224	1		T227	2
all_values[9]	auto[0]	auto[0]	auto[0]	56	1			T222	1		T223	4		T227	1
all_values[9]	auto[0]	auto[0]	auto[1]	25	1			T224	1		T310	2		T336	1
all_values[9]	auto[0]	auto[1]	auto[0]	34	1			T222	2		T225	1		T223	1
all_values[9]	auto[0]	auto[1]	auto[1]	33	1			T222	1		T225	2		T223	1
all_values[9]	auto[1]	auto[0]	auto[1]	59	1			T222	2		T225	1		T224	1
all_values[9]	auto[1]	auto[1]	auto[1]	50	1			T222	1		T223	1		T224	1
all_values[10]	auto[0]	auto[0]	auto[0]	67	1			T225	1		T223	1		T224	4
all_values[10]	auto[0]	auto[0]	auto[1]	14	1			T222	1		T223	2		T224	1
all_values[10]	auto[0]	auto[1]	auto[0]	48	1			T222	3		T225	2		T223	1
all_values[10]	auto[0]	auto[1]	auto[1]	31	1			T227	2		T310	1		T340	1
all_values[10]	auto[1]	auto[0]	auto[1]	48	1			T222	2		T225	1		T223	1
all_values[10]	auto[1]	auto[1]	auto[1]	49	1			T222	1		T223	2		T227	1
all_values[11]	auto[0]	auto[0]	auto[0]	54	1			T222	1		T225	2		T223	1
all_values[11]	auto[0]	auto[0]	auto[1]	22	1			T222	1		T224	2		T226	1
all_values[11]	auto[0]	auto[1]	auto[0]	43	1			T224	1		T227	1		T310	3
all_values[11]	auto[0]	auto[1]	auto[1]	29	1			T222	1		T223	1		T340	1
all_values[11]	auto[1]	auto[0]	auto[1]	57	1			T222	2		T225	1		T223	2
all_values[11]	auto[1]	auto[1]	auto[1]	52	1			T222	2		T225	1		T223	3
all_values[12]	auto[0]	auto[0]	auto[0]	60	1			T225	3		T223	1		T224	3
all_values[12]	auto[0]	auto[0]	auto[1]	23	1			T224	1		T227	1		T226	2
all_values[12]	auto[0]	auto[1]	auto[0]	38	1			T222	3		T223	1		T224	1
all_values[12]	auto[0]	auto[1]	auto[1]	28	1			T223	1		T310	2		T337	2
all_values[12]	auto[1]	auto[0]	auto[1]	52	1			T222	1		T223	2		T224	2
all_values[12]	auto[1]	auto[1]	auto[1]	56	1			T222	3		T225	1		T223	2
all_values[13]	auto[0]	auto[0]	auto[0]	51	1			T222	2		T224	2		T227	4
all_values[13]	auto[0]	auto[0]	auto[1]	27	1			T340	1		T336	3		T343	2
all_values[13]	auto[0]	auto[1]	auto[0]	47	1			T224	4		T227	1		T310	2
all_values[13]	auto[0]	auto[1]	auto[1]	31	1			T222	2		T225	2		T223	1
all_values[13]	auto[1]	auto[0]	auto[1]	54	1			T225	2		T223	4		T227	2
all_values[13]	auto[1]	auto[1]	auto[1]	47	1			T222	3		T223	2		T224	1
all_values[14]	auto[0]	auto[0]	auto[0]	62	1			T222	1		T225	1		T227	1
all_values[14]	auto[0]	auto[0]	auto[1]	21	1			T222	1		T225	1		T224	1
all_values[14]	auto[0]	auto[1]	auto[0]	36	1			T310	2		T339	2		T344	2
all_values[14]	auto[0]	auto[1]	auto[1]	32	1			T222	1		T223	2		T227	2
all_values[14]	auto[1]	auto[0]	auto[1]	56	1			T222	1		T225	1		T223	1
all_values[14]	auto[1]	auto[1]	auto[1]	50	1			T222	3		T225	1		T223	4
all_values[15]	auto[0]	auto[0]	auto[0]	54	1			T222	4		T225	2		T224	2
all_values[15]	auto[0]	auto[0]	auto[1]	33	1			T223	4		T224	1		T227	3
all_values[15]	auto[0]	auto[1]	auto[0]	34	1			T222	1		T225	2		T224	1
all_values[15]	auto[0]	auto[1]	auto[1]	25	1			T222	1		T340	1		T337	1
all_values[15]	auto[1]	auto[0]	auto[1]	60	1			T223	1		T224	1		T227	2
all_values[15]	auto[1]	auto[1]	auto[1]	51	1			T222	1		T223	2		T224	2
all_values[16]	auto[0]	auto[0]	auto[0]	68	1			T222	3		T224	2		T227	4
all_values[16]	auto[0]	auto[0]	auto[1]	24	1			T223	3		T226	1		T310	1
all_values[16]	auto[0]	auto[1]	auto[0]	43	1			T222	1		T225	4		T224	2
all_values[16]	auto[0]	auto[1]	auto[1]	22	1			T310	1		T339	1		T343	1
all_values[16]	auto[1]	auto[0]	auto[1]	65	1			T222	1		T223	2		T224	1
all_values[16]	auto[1]	auto[1]	auto[1]	35	1			T222	2		T223	2		T224	2
all_values[17]	auto[0]	auto[0]	auto[0]	89	1			T222	1		T225	1		T223	4
all_values[17]	auto[0]	auto[1]	auto[0]	59	1			T222	2		T224	2		T227	3
all_values[17]	auto[1]	auto[0]	auto[1]	69	1			T222	2		T225	2		T223	1
all_values[17]	auto[1]	auto[1]	auto[1]	40	1			T222	2		T225	1		T223	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal