Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	81986	1			T1	2		T2	2		T3	3
all_values[1]	81986	1			T1	2		T2	2		T3	3
all_values[2]	81986	1			T1	2		T2	2		T3	3
all_values[3]	81986	1			T1	2		T2	2		T3	3
all_values[4]	81986	1			T1	2		T2	2		T3	3
all_values[5]	81986	1			T1	2		T2	2		T3	3
all_values[6]	81986	1			T1	2		T2	2		T3	3
all_values[7]	81986	1			T1	2		T2	2		T3	3
all_values[8]	81986	1			T1	2		T2	2		T3	3
all_values[9]	81986	1			T1	2		T2	2		T3	3
all_values[10]	81986	1			T1	2		T2	2		T3	3
all_values[11]	81986	1			T1	2		T2	2		T3	3
all_values[12]	81986	1			T1	2		T2	2		T3	3
all_values[13]	81986	1			T1	2		T2	2		T3	3
all_values[14]	81986	1			T1	2		T2	2		T3	3
all_values[15]	81986	1			T1	2		T2	2		T3	3
all_values[16]	81986	1			T1	2		T2	2		T3	3
all_values[17]	81986	1			T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2613898

1

T1

64

T2

64

T3

96

auto[1]

9654

1

T15

11

T16

2

T18

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2176113

1

T1

60

T2

61

T3

84

auto[1]

447439

1

T1

4

T2

3

T3

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	53148	1			T1	2		T2	2		T3	3
all_values[0]	auto[0]	auto[1]	25509	1			T15	8		T19	3		T21	1
all_values[0]	auto[1]	auto[0]	3226	1			T18	5		T23	3		T28	5
all_values[0]	auto[1]	auto[1]	103	1			T356	1		T357	1		T358	1
all_values[1]	auto[0]	auto[0]	77534	1			T1	2		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	3054	1			T17	2		T18	3		T19	1
all_values[1]	auto[1]	auto[0]	526	1			T33	2		T37	1		T38	2
all_values[1]	auto[1]	auto[1]	872	1			T33	1		T37	1		T38	1
all_values[2]	auto[0]	auto[0]	4221	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	77480	1			T1	1		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	147	1			T16	1		T35	1		T55	1
all_values[2]	auto[1]	auto[1]	138	1			T16	1		T35	1		T55	1
all_values[3]	auto[0]	auto[0]	80105	1			T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	300	1			T17	1		T56	1		T57	1
all_values[3]	auto[1]	auto[0]	1511	1			T58	1429		T245	3		T242	1
all_values[3]	auto[1]	auto[1]	70	1			T58	1		T245	4		T242	1
all_values[4]	auto[0]	auto[0]	4208	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	77628	1			T1	1		T2	1		T3	2
all_values[4]	auto[1]	auto[0]	102	1			T59	1		T245	1		T242	3
all_values[4]	auto[1]	auto[1]	48	1			T59	1		T245	3		T242	2
all_values[5]	auto[0]	auto[0]	81484	1			T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	337	1			T3	1		T37	1		T6	1
all_values[5]	auto[1]	auto[0]	90	1			T245	1		T242	2		T244	3
all_values[5]	auto[1]	auto[1]	75	1			T245	4		T242	2		T243	3
all_values[6]	auto[0]	auto[0]	81540	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	222	1			T3	1		T37	1		T7	1
all_values[6]	auto[1]	auto[0]	114	1			T245	4		T242	2		T244	1
all_values[6]	auto[1]	auto[1]	110	1			T34	1		T60	1		T61	1
all_values[7]	auto[0]	auto[0]	24930	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	56914	1			T3	1		T15	13		T17	2
all_values[7]	auto[1]	auto[0]	96	1			T39	1		T40	1		T41	1
all_values[7]	auto[1]	auto[1]	46	1			T39	1		T40	1		T41	1
all_values[8]	auto[0]	auto[0]	81239	1			T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	49	1			T245	1		T242	1		T243	1
all_values[8]	auto[1]	auto[0]	625	1			T15	10		T44	10		T45	10
all_values[8]	auto[1]	auto[1]	73	1			T15	1		T42	1		T43	1
all_values[9]	auto[0]	auto[0]	81758	1			T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	49	1			T242	2		T243	2		T244	1
all_values[9]	auto[1]	auto[0]	117	1			T52	3		T53	3		T54	3
all_values[9]	auto[1]	auto[1]	62	1			T52	2		T53	2		T54	2
all_values[10]	auto[0]	auto[0]	81433	1			T1	2		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	391	1			T49	1		T50	2		T51	1
all_values[10]	auto[1]	auto[0]	94	1			T245	7		T244	3		T323	4
all_values[10]	auto[1]	auto[1]	68	1			T242	1		T243	2		T244	1
all_values[11]	auto[0]	auto[0]	81015	1			T1	2		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	719	1			T18	3		T28	3		T66	1
all_values[11]	auto[1]	auto[0]	132	1			T67	1		T68	1		T69	1
all_values[11]	auto[1]	auto[1]	120	1			T67	1		T68	1		T69	1
all_values[12]	auto[0]	auto[0]	81618	1			T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	204	1			T70	3		T72	3		T75	3
all_values[12]	auto[1]	auto[0]	94	1			T71	2		T73	2		T74	2
all_values[12]	auto[1]	auto[1]	70	1			T71	1		T73	1		T74	1
all_values[13]	auto[0]	auto[0]	81656	1			T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	74	1			T78	1		T79	1		T80	1
all_values[13]	auto[1]	auto[0]	130	1			T66	1		T76	1		T77	1
all_values[13]	auto[1]	auto[1]	126	1			T66	1		T76	1		T77	1
all_values[14]	auto[0]	auto[0]	15950	1			T1	1		T2	2		T3	1
all_values[14]	auto[0]	auto[1]	65855	1			T1	1		T3	2		T16	1
all_values[14]	auto[1]	auto[0]	107	1			T245	2		T242	1		T243	1
all_values[14]	auto[1]	auto[1]	74	1			T245	4		T243	1		T244	3
all_values[15]	auto[0]	auto[0]	4255	1			T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	77570	1			T1	1		T2	1		T3	2
all_values[15]	auto[1]	auto[0]	97	1			T245	5		T242	1		T243	2
all_values[15]	auto[1]	auto[1]	64	1			T242	4		T243	4		T323	4
all_values[16]	auto[0]	auto[0]	81005	1			T1	2		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	803	1			T18	3		T62	1		T51	1
all_values[16]	auto[1]	auto[0]	99	1			T63	4		T64	4		T65	4
all_values[16]	auto[1]	auto[1]	79	1			T63	4		T64	4		T65	4
all_values[17]	auto[0]	auto[0]	23797	1			T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	58040	1			T3	1		T15	2		T16	2
all_values[17]	auto[1]	auto[0]	106	1			T245	1		T242	1		T244	3
all_values[17]	auto[1]	auto[1]	43	1			T245	1		T243	1		T244	3