Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1408	1			T56	9		T111	4		T163	1
range_16_to_126	156842	1			T1	108		T2	15		T15	8
fifteen	1936	1			T331	1		T124	2		T56	5
range_2_to_14	20768	1			T1	6		T2	2		T18	10
seven	1876	1			T1	1		T18	10		T56	7
one	1407	1			T56	4		T210	1		T111	3
zero	940	1			T2	1		T331	1		T66	1

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

12855

1

T1

15

T2

1

T17

45

three

12994

1

T1

15

T2

2

T17

43

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	59	1			T56	1		T112	1		T515	3
range_127	three	64	1			T56	1		T516	3		T517	1
range_16_to_126	seven	10785	1			T1	15		T2	1		T17	45
range_16_to_126	three	11248	1			T1	15		T2	2		T17	43
fifteen	seven	250	1			T111	1		T115	7		T518	6
fifteen	three	119	1			T519	1		T134	2		T208	2
range_2_to_14	seven	1552	1			T56	3		T111	32		T91	69
range_2_to_14	three	1396	1			T56	8		T82	2		T111	33
seven	seven	147	1			T163	1		T208	1		T520	1
seven	three	117	1			T111	1		T521	1		T180	2
one	seven	168	1			T112	1		T180	1		T321	66
one	three	117	1			T414	1		T321	62		T522	15
zero	seven	41	1			T181	1		T467	1		T297	30
zero	three	50	1			T56	1		T523	1		T297	38