Summary for Variable cp_crc5
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_crc5
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_ones |
6992 |
1 |
|
|
T1 |
13 |
|
T28 |
3 |
|
T50 |
2 |
leading_zero |
7893 |
1 |
|
|
T20 |
1 |
|
T33 |
2 |
|
T36 |
3 |
trailing_zero |
4565 |
1 |
|
|
T1 |
1 |
|
T17 |
45 |
|
T18 |
3 |
Summary for Variable cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_dir
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
114102 |
1 |
|
|
T1 |
56 |
|
T2 |
9 |
|
T15 |
8 |
auto[1] |
69199 |
1 |
|
|
T1 |
58 |
|
T2 |
9 |
|
T17 |
268 |
Summary for Cross cr_crc5_X_dir
Samples crossed: cp_crc5 cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for cr_crc5_X_dir
Bins
cp_crc5 | cp_dir | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_ones |
auto[0] |
4862 |
1 |
|
|
T1 |
6 |
|
T28 |
2 |
|
T50 |
1 |
all_ones |
auto[1] |
2130 |
1 |
|
|
T1 |
7 |
|
T28 |
1 |
|
T50 |
1 |
leading_zero |
auto[0] |
5748 |
1 |
|
|
T20 |
1 |
|
T33 |
1 |
|
T36 |
2 |
leading_zero |
auto[1] |
2145 |
1 |
|
|
T33 |
1 |
|
T36 |
1 |
|
T56 |
24 |
trailing_zero |
auto[0] |
2658 |
1 |
|
|
T17 |
16 |
|
T18 |
2 |
|
T20 |
1 |
trailing_zero |
auto[1] |
1907 |
1 |
|
|
T1 |
1 |
|
T17 |
29 |
|
T18 |
1 |