Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_crc5 3 0 3 100.00 100 1 1 0
cp_dir 2 0 2 100.00 100 1 1 2


Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_crc5_X_dir 6 0 6 100.00 100 1 1 0


Summary for Variable cp_crc5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_crc5

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_ones 6992 1 T1 13 T28 3 T50 2
leading_zero 7893 1 T20 1 T33 2 T36 3
trailing_zero 4565 1 T1 1 T17 45 T18 3



Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 114102 1 T1 56 T2 9 T15 8
auto[1] 69199 1 T1 58 T2 9 T17 268



Summary for Cross cr_crc5_X_dir

Samples crossed: cp_crc5 cp_dir
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for cr_crc5_X_dir

Bins
cp_crc5cp_dirCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_ones auto[0] 4862 1 T1 6 T28 2 T50 1
all_ones auto[1] 2130 1 T1 7 T28 1 T50 1
leading_zero auto[0] 5748 1 T20 1 T33 1 T36 2
leading_zero auto[1] 2145 1 T33 1 T36 1 T56 24
trailing_zero auto[0] 2658 1 T17 16 T18 2 T20 1
trailing_zero auto[1] 1907 1 T1 1 T17 29 T18 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%