Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113960

1

T1

56

T2

9

T15

8

auto[1]

45411

1

T1

43

T17

268

T18

3

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	30196	1			T1	2		T17	2		T22	2
max_len_m1	814	1			T1	2		T17	4		T5	2
max_len_m2	819	1			T17	7		T4	2		T5	2
max_len_m3	787	1			T1	2		T17	4		T5	2
five	1154	1			T17	13		T4	2		T530	2
four	1121	1			T1	1		T17	13		T4	2
three	778	1			T17	9		T166	2		T57	4
one	868	1			T17	15		T37	2		T82	1
zero	11633	1			T1	1		T17	133		T49	8

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24448	1			T1	1		T17	2		T22	1
max_len	auto[1]	5748	1			T1	1		T22	1		T4	1
max_len_m1	auto[0]	558	1			T1	1		T17	4		T5	1
max_len_m1	auto[1]	256	1			T1	1		T5	1		T85	3
max_len_m2	auto[0]	554	1			T17	7		T4	1		T5	1
max_len_m2	auto[1]	265	1			T4	1		T5	1		T82	1
max_len_m3	auto[0]	537	1			T1	1		T17	2		T5	1
max_len_m3	auto[1]	250	1			T1	1		T17	2		T5	1
five	auto[0]	592	1			T17	5		T4	1		T530	1
five	auto[1]	562	1			T17	8		T4	1		T530	1
four	auto[0]	585	1			T1	1		T17	4		T4	1
four	auto[1]	536	1			T17	9		T4	1		T85	1
three	auto[0]	358	1			T17	2		T166	1		T57	2
three	auto[1]	420	1			T17	7		T166	1		T57	2
one	auto[0]	366	1			T17	4		T37	1		T82	1
one	auto[1]	502	1			T17	11		T37	1		T57	11
zero	auto[0]	523	1			T17	5		T51	1		T66	1
zero	auto[1]	11110	1			T1	1		T17	128		T49	8