Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69934

1

T1

44

T15

8

T17

281

auto[1]

76537

1

T1

72

T17

536

T18

6

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	11659	1			T17	66		T5	159		T158	3
endpoints[0x1]	12229	1			T1	18		T17	72		T38	3
endpoints[0x2]	10782	1			T1	18		T17	79		T28	4
endpoints[0x3]	11738	1			T1	7		T17	63		T4	183
endpoints[0x4]	13003	1			T15	8		T17	78		T37	3
endpoints[0x5]	14024	1			T1	18		T17	62		T82	6
endpoints[0x6]	12061	1			T17	77		T21	1		T27	3
endpoints[0x7]	11241	1			T1	18		T17	74		T19	1
endpoints[0x8]	12240	1			T17	62		T51	1		T87	780
endpoints[0x9]	10946	1			T1	18		T17	65		T18	4
endpoints[0xa]	13207	1			T17	64		T18	9		T85	27
endpoints[0xb]	13341	1			T1	19		T17	55		T51	4

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	204	1			T51	3		T108	7		T109	3
ack	37631	1			T1	36		T17	268		T18	3
data1	50441	1			T1	29		T17	269		T18	6
data0	58134	1			T1	51		T15	8		T17	280

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	17	1			T336	1		T337	1		T338	1
nak	auto[1]	endpoints[0x1]	17	1			T109	1		T339	1		T340	1
nak	auto[1]	endpoints[0x2]	14	1			T108	1		T341	1		T339	1
nak	auto[1]	endpoints[0x3]	14	1			T342	2		T343	1		T344	1
nak	auto[1]	endpoints[0x4]	16	1			T108	2		T343	1		T340	1
nak	auto[1]	endpoints[0x5]	13	1			T109	1		T340	1		T336	1
nak	auto[1]	endpoints[0x6]	18	1			T108	2		T345	1		T342	1
nak	auto[1]	endpoints[0x7]	17	1			T51	1		T345	1		T346	1
nak	auto[1]	endpoints[0x8]	20	1			T109	1		T345	1		T346	1
nak	auto[1]	endpoints[0x9]	11	1			T51	1		T342	2		T339	1
nak	auto[1]	endpoints[0xa]	21	1			T346	1		T340	1		T347	2
nak	auto[1]	endpoints[0xb]	26	1			T51	1		T108	2		T345	2
ack	auto[1]	endpoints[0x0]	3359	1			T17	20		T5	53		T158	1
ack	auto[1]	endpoints[0x1]	3124	1			T1	6		T17	22		T38	1
ack	auto[1]	endpoints[0x2]	3057	1			T1	6		T17	26		T28	1
ack	auto[1]	endpoints[0x3]	3192	1			T17	20		T4	61		T28	2
ack	auto[1]	endpoints[0x4]	3280	1			T17	26		T37	1		T82	6
ack	auto[1]	endpoints[0x5]	3207	1			T1	6		T17	23		T57	20
ack	auto[1]	endpoints[0x6]	2972	1			T17	25		T27	1		T85	9
ack	auto[1]	endpoints[0x7]	3207	1			T1	6		T17	29		T281	1
ack	auto[1]	endpoints[0x8]	2911	1			T17	21		T36	1		T164	32
ack	auto[1]	endpoints[0x9]	3060	1			T1	6		T17	21		T18	1
ack	auto[1]	endpoints[0xa]	3152	1			T17	19		T18	2		T85	9
ack	auto[1]	endpoints[0xb]	3110	1			T1	6		T17	16		T56	12
data1	auto[0]	endpoints[0x0]	1906	1			T17	13		T5	20		T85	2
data1	auto[0]	endpoints[0x1]	2484	1			T17	14		T51	1		T56	3
data1	auto[0]	endpoints[0x2]	1815	1			T1	1		T17	13		T28	1
data1	auto[0]	endpoints[0x3]	2193	1			T17	11		T4	19		T28	2
data1	auto[0]	endpoints[0x4]	2685	1			T17	13		T82	2		T57	13
data1	auto[0]	endpoints[0x5]	3330	1			T1	2		T17	8		T82	3
data1	auto[0]	endpoints[0x6]	2567	1			T17	13		T84	530		T85	4
data1	auto[0]	endpoints[0x7]	1902	1			T1	2		T17	8		T57	11
data1	auto[0]	endpoints[0x8]	2674	1			T17	10		T51	1		T87	390
data1	auto[0]	endpoints[0x9]	1971	1			T1	2		T17	11		T18	1
data1	auto[0]	endpoints[0xa]	3019	1			T17	13		T18	2		T85	4
data1	auto[0]	endpoints[0xb]	3123	1			T17	11		T51	1		T57	9
data1	auto[1]	endpoints[0x0]	1830	1			T17	10		T5	33		T49	4
data1	auto[1]	endpoints[0x1]	1695	1			T1	3		T17	11		T56	6
data1	auto[1]	endpoints[0x2]	1697	1			T1	4		T17	13		T28	1
data1	auto[1]	endpoints[0x3]	1768	1			T17	10		T4	42		T28	2
data1	auto[1]	endpoints[0x4]	1841	1			T17	13		T82	3		T57	7
data1	auto[1]	endpoints[0x5]	1795	1			T1	4		T17	11		T57	10
data1	auto[1]	endpoints[0x6]	1630	1			T17	12		T85	4		T57	12
data1	auto[1]	endpoints[0x7]	1789	1			T1	4		T17	14		T51	2
data1	auto[1]	endpoints[0x8]	1642	1			T17	10		T36	1		T164	24
data1	auto[1]	endpoints[0x9]	1641	1			T1	4		T17	10		T18	1
data1	auto[1]	endpoints[0xa]	1749	1			T17	9		T18	2		T85	4
data1	auto[1]	endpoints[0xb]	1695	1			T1	3		T17	8		T56	8
data0	auto[0]	endpoints[0x0]	2924	1			T17	13		T5	33		T158	1
data0	auto[0]	endpoints[0x1]	3392	1			T1	6		T17	14		T38	1
data0	auto[0]	endpoints[0x2]	2753	1			T1	5		T17	14		T28	1
data0	auto[0]	endpoints[0x3]	3019	1			T1	7		T17	12		T4	42
data0	auto[0]	endpoints[0x4]	3664	1			T15	8		T17	13		T37	1
data0	auto[0]	endpoints[0x5]	4162	1			T1	4		T17	8		T82	3
data0	auto[0]	endpoints[0x6]	3442	1			T17	14		T21	1		T27	1
data0	auto[0]	endpoints[0x7]	2847	1			T1	4		T17	8		T19	1
data0	auto[0]	endpoints[0x8]	3584	1			T17	10		T87	390		T36	1
data0	auto[0]	endpoints[0x9]	2789	1			T1	4		T17	12		T18	1
data0	auto[0]	endpoints[0xa]	3764	1			T17	13		T18	3		T85	5
data0	auto[0]	endpoints[0xb]	3914	1			T1	7		T17	12		T56	29
data0	auto[1]	endpoints[0x0]	1616	1			T17	10		T5	20		T158	1
data0	auto[1]	endpoints[0x1]	1513	1			T1	3		T17	11		T38	1
data0	auto[1]	endpoints[0x2]	1442	1			T1	2		T17	13		T82	3
data0	auto[1]	endpoints[0x3]	1547	1			T17	10		T4	19		T85	4
data0	auto[1]	endpoints[0x4]	1510	1			T17	13		T37	1		T82	3
data0	auto[1]	endpoints[0x5]	1512	1			T1	2		T17	12		T57	10
data0	auto[1]	endpoints[0x6]	1425	1			T17	13		T27	1		T85	5
data0	auto[1]	endpoints[0x7]	1473	1			T1	2		T17	15		T281	1
data0	auto[1]	endpoints[0x8]	1405	1			T17	11		T164	8		T57	10
data0	auto[1]	endpoints[0x9]	1471	1			T1	2		T17	11		T22	1
data0	auto[1]	endpoints[0xa]	1497	1			T17	10		T85	5		T166	1
data0	auto[1]	endpoints[0xb]	1469	1			T1	3		T17	8		T51	2