Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	0	16	100.00	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9438

1

T1

2

T2

4

T20

4

auto[1]

53910

1

T1

56

T2

3

T17

268

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55321

1

T1

34

T2

6

T17

268

auto[1]

8027

1

T1

24

T2

1

T19

1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57020

1

T1

58

T2

5

T17

268

auto[1]

6328

1

T2

2

T20

2

T83

2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

4749

1

T1

9

T2

1

T20

2

pkt_types[PidTypeInToken]

58599

1

T1

49

T2

6

T17

268

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

1555

1

T1

1

T56

56

T82

3

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

762

1

T20

1

T56

6

T111

25

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

121

1

T1

1

T2

1

T83

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

16

1

T404

1

T466

1

T416

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

1410

1

T1

5

T20

1

T56

42

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

766

1

T56

6

T359

2

T112

6

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

99

1

T1

2

T82

3

T163

3

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

20

1

T83

1

T401

1

T466

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

4631

1

T2

1

T331

1

T56

145

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2263

1

T2

2

T83

1

T56

18

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

45

1

T20

3

T211

1

T212

3

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

45

1

T374

1

T401

1

T364

2

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

41533

1

T1

28

T2

3

T17

268

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2401

1

T20

1

T121

1

T56

24

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

7626

1

T1

21

T19

1

T82

35

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

55

1

T374

1

T456

1

T384

1