Summary for Variable cp_avout
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_avout
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full |
19380 |
1 |
|
|
T1 |
44 |
|
T4 |
61 |
|
T5 |
53 |
solo |
77898 |
1 |
|
|
T2 |
8 |
|
T17 |
281 |
|
T18 |
3 |
empty |
4191 |
1 |
|
|
T15 |
8 |
|
T18 |
4 |
|
T23 |
1 |
Summary for Variable cp_avsetup
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_avsetup
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full |
19403 |
1 |
|
|
T1 |
44 |
|
T15 |
2 |
|
T4 |
61 |
solo |
35699 |
1 |
|
|
T2 |
6 |
|
T15 |
1 |
|
T18 |
3 |
empty |
46412 |
1 |
|
|
T2 |
2 |
|
T17 |
281 |
|
T18 |
4 |
Summary for Variable cp_pid
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_pid
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
out |
77244 |
1 |
|
|
T1 |
34 |
|
T2 |
5 |
|
T17 |
281 |
setup |
24419 |
1 |
|
|
T1 |
10 |
|
T2 |
3 |
|
T15 |
8 |
Summary for Variable cp_rx
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for cp_rx
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
full |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
solo |
40 |
1 |
|
|
T15 |
1 |
|
T42 |
1 |
|
T43 |
1 |
empty |
84522 |
1 |
|
|
T1 |
44 |
|
T2 |
8 |
|
T15 |
1 |
Summary for Cross cr_fifo_X_pid
Samples crossed: cp_avsetup cp_avout cp_rx cp_pid
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
54 |
39 |
15 |
27.78 |
39 |
Automatically Generated Cross Bins for cr_fifo_X_pid
Element holes
cp_avsetup | cp_avout | cp_rx | cp_pid | COUNT | AT LEAST | NUMBER | STATUS |
[full] |
[full] |
[full , solo] |
* |
-- |
-- |
4 |
|
[full] |
[solo] |
* |
* |
-- |
-- |
6 |
|
[full] |
[empty] |
[full] |
* |
-- |
-- |
2 |
|
[solo] |
[full] |
[full , solo] |
* |
-- |
-- |
4 |
|
[solo] |
[solo] |
[full] |
* |
-- |
-- |
2 |
|
[solo] |
[empty] |
[full] |
* |
-- |
-- |
2 |
|
[empty] |
[full , solo] |
[full , solo] |
* |
-- |
-- |
8 |
|
[empty] |
[empty] |
[full , solo] |
* |
-- |
-- |
4 |
|
Uncovered bins
cp_avsetup | cp_avout | cp_rx | cp_pid | COUNT | AT LEAST | NUMBER | STATUS |
[full] |
[empty] |
[solo , empty] |
[out] |
-- |
-- |
2 |
|
[solo] |
[full] |
[empty] |
[setup] |
0 |
1 |
1 |
|
[solo] |
[empty] |
[solo , empty] |
[out] |
-- |
-- |
2 |
|
[empty] |
[full , solo] |
[empty] |
[setup] |
-- |
-- |
2 |
|
Covered bins
cp_avsetup | cp_avout | cp_rx | cp_pid | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full |
full |
empty |
out |
14958 |
1 |
|
|
T1 |
34 |
|
T4 |
30 |
|
T5 |
32 |
full |
full |
empty |
setup |
4394 |
1 |
|
|
T1 |
10 |
|
T4 |
31 |
|
T5 |
21 |
full |
empty |
solo |
setup |
5 |
1 |
|
|
T325 |
1 |
|
T326 |
1 |
|
T327 |
1 |
full |
empty |
empty |
setup |
6 |
1 |
|
|
T328 |
1 |
|
T329 |
1 |
|
T330 |
1 |
solo |
full |
empty |
out |
5 |
1 |
|
|
T46 |
1 |
|
T47 |
1 |
|
T48 |
1 |
solo |
solo |
solo |
out |
5 |
1 |
|
|
T46 |
1 |
|
T47 |
1 |
|
T48 |
1 |
solo |
solo |
solo |
setup |
5 |
1 |
|
|
T46 |
1 |
|
T47 |
1 |
|
T48 |
1 |
solo |
solo |
empty |
out |
9318 |
1 |
|
|
T2 |
3 |
|
T20 |
1 |
|
T331 |
4 |
solo |
solo |
empty |
setup |
9129 |
1 |
|
|
T2 |
3 |
|
T20 |
2 |
|
T83 |
1 |
solo |
empty |
solo |
setup |
1 |
1 |
|
|
T332 |
1 |
|
- |
- |
|
- |
- |
solo |
empty |
empty |
setup |
2033 |
1 |
|
|
T15 |
1 |
|
T18 |
3 |
|
T28 |
3 |
empty |
full |
empty |
out |
1 |
1 |
|
|
T333 |
1 |
|
- |
- |
|
- |
- |
empty |
solo |
empty |
out |
44217 |
1 |
|
|
T2 |
2 |
|
T17 |
281 |
|
T18 |
3 |
empty |
empty |
empty |
out |
260 |
1 |
|
|
T18 |
1 |
|
T28 |
1 |
|
T162 |
1 |
empty |
empty |
empty |
setup |
159 |
1 |
|
|
T23 |
1 |
|
T334 |
1 |
|
T335 |
1 |