Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	81986	1			T1	2		T2	2		T3	3
all_pins[1]	81986	1			T1	2		T2	2		T3	3
all_pins[2]	81986	1			T1	2		T2	2		T3	3
all_pins[3]	81986	1			T1	2		T2	2		T3	3
all_pins[4]	81986	1			T1	2		T2	2		T3	3
all_pins[5]	81986	1			T1	2		T2	2		T3	3
all_pins[6]	81986	1			T1	2		T2	2		T3	3
all_pins[7]	81986	1			T1	2		T2	2		T3	3
all_pins[8]	81986	1			T1	2		T2	2		T3	3
all_pins[9]	81986	1			T1	2		T2	2		T3	3
all_pins[10]	81986	1			T1	2		T2	2		T3	3
all_pins[11]	81986	1			T1	2		T2	2		T3	3
all_pins[12]	81986	1			T1	2		T2	2		T3	3
all_pins[13]	81986	1			T1	2		T2	2		T3	3
all_pins[14]	81986	1			T1	2		T2	2		T3	3
all_pins[15]	81986	1			T1	2		T2	2		T3	3
all_pins[16]	81986	1			T1	2		T2	2		T3	3
all_pins[17]	81986	1			T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2621311	1			T1	64		T2	64		T3	96
values[0x1]	2241	1			T15	1		T16	1		T33	1
transitions[0x0=>0x1]	1973	1			T15	1		T16	1		T33	1
transitions[0x1=>0x0]	1973	1			T15	1		T16	1		T33	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	81883	1			T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	103	1			T356	1		T357	1		T358	1
all_pins[0]	transitions[0x0=>0x1]	93	1			T356	1		T357	1		T358	1
all_pins[0]	transitions[0x1=>0x0]	862	1			T33	1		T37	1		T38	1
all_pins[1]	values[0x0]	81114	1			T1	2		T2	2		T3	3
all_pins[1]	values[0x1]	872	1			T33	1		T37	1		T38	1
all_pins[1]	transitions[0x0=>0x1]	856	1			T33	1		T37	1		T38	1
all_pins[1]	transitions[0x1=>0x0]	122	1			T16	1		T35	1		T55	1
all_pins[2]	values[0x0]	81848	1			T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	138	1			T16	1		T35	1		T55	1
all_pins[2]	transitions[0x0=>0x1]	112	1			T16	1		T35	1		T55	1
all_pins[2]	transitions[0x1=>0x0]	44	1			T58	1		T245	4		T244	1
all_pins[3]	values[0x0]	81916	1			T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	70	1			T58	1		T245	4		T242	1
all_pins[3]	transitions[0x0=>0x1]	57	1			T58	1		T245	2		T243	1
all_pins[3]	transitions[0x1=>0x0]	35	1			T59	1		T245	1		T242	1
all_pins[4]	values[0x0]	81938	1			T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	48	1			T59	1		T245	3		T242	2
all_pins[4]	transitions[0x0=>0x1]	30	1			T59	1		T242	2		T323	1
all_pins[4]	transitions[0x1=>0x0]	57	1			T245	1		T242	2		T243	3
all_pins[5]	values[0x0]	81911	1			T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	75	1			T245	4		T242	2		T243	3
all_pins[5]	transitions[0x0=>0x1]	57	1			T245	3		T242	2		T243	1
all_pins[5]	transitions[0x1=>0x0]	92	1			T34	1		T60	1		T61	1
all_pins[6]	values[0x0]	81876	1			T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	110	1			T34	1		T60	1		T61	1
all_pins[6]	transitions[0x0=>0x1]	101	1			T34	1		T60	1		T61	1
all_pins[6]	transitions[0x1=>0x0]	37	1			T39	1		T40	1		T41	1
all_pins[7]	values[0x0]	81940	1			T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	46	1			T39	1		T40	1		T41	1
all_pins[7]	transitions[0x0=>0x1]	37	1			T39	1		T40	1		T41	1
all_pins[7]	transitions[0x1=>0x0]	64	1			T15	1		T42	1		T43	1
all_pins[8]	values[0x0]	81913	1			T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	73	1			T15	1		T42	1		T43	1
all_pins[8]	transitions[0x0=>0x1]	59	1			T15	1		T42	1		T43	1
all_pins[8]	transitions[0x1=>0x0]	48	1			T52	2		T53	2		T54	2
all_pins[9]	values[0x0]	81924	1			T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	62	1			T52	2		T53	2		T54	2
all_pins[9]	transitions[0x0=>0x1]	52	1			T52	2		T53	2		T54	2
all_pins[9]	transitions[0x1=>0x0]	58	1			T243	2		T244	1		T323	3
all_pins[10]	values[0x0]	81918	1			T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	68	1			T242	1		T243	2		T244	1
all_pins[10]	transitions[0x0=>0x1]	52	1			T243	2		T244	1		T323	3
all_pins[10]	transitions[0x1=>0x0]	104	1			T67	1		T68	1		T69	1
all_pins[11]	values[0x0]	81866	1			T1	2		T2	2		T3	3
all_pins[11]	values[0x1]	120	1			T67	1		T68	1		T69	1
all_pins[11]	transitions[0x0=>0x1]	102	1			T67	1		T68	1		T69	1
all_pins[11]	transitions[0x1=>0x0]	52	1			T71	1		T73	1		T74	1
all_pins[12]	values[0x0]	81916	1			T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	70	1			T71	1		T73	1		T74	1
all_pins[12]	transitions[0x0=>0x1]	47	1			T71	1		T73	1		T74	1
all_pins[12]	transitions[0x1=>0x0]	103	1			T66	1		T76	1		T77	1
all_pins[13]	values[0x0]	81860	1			T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	126	1			T66	1		T76	1		T77	1
all_pins[13]	transitions[0x0=>0x1]	104	1			T66	1		T76	1		T77	1
all_pins[13]	transitions[0x1=>0x0]	52	1			T245	4		T243	1		T244	3
all_pins[14]	values[0x0]	81912	1			T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	74	1			T245	4		T243	1		T244	3
all_pins[14]	transitions[0x0=>0x1]	55	1			T245	4		T244	3		T323	2
all_pins[14]	transitions[0x1=>0x0]	45	1			T242	4		T243	3		T323	2
all_pins[15]	values[0x0]	81922	1			T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	64	1			T242	4		T243	4		T323	4
all_pins[15]	transitions[0x0=>0x1]	47	1			T242	1		T243	3		T323	3
all_pins[15]	transitions[0x1=>0x0]	62	1			T63	4		T64	4		T65	4
all_pins[16]	values[0x0]	81907	1			T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	79	1			T63	4		T64	4		T65	4
all_pins[16]	transitions[0x0=>0x1]	69	1			T63	4		T64	4		T65	4
all_pins[16]	transitions[0x1=>0x0]	33	1			T245	1		T244	2		T349	3
all_pins[17]	values[0x0]	81943	1			T1	2		T2	2		T3	3
all_pins[17]	values[0x1]	43	1			T245	1		T243	1		T244	3
all_pins[17]	transitions[0x0=>0x1]	43	1			T245	1		T243	1		T244	3