Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4960	1			T2	2		T20	2		T83	2
invalid_ep[0xd]	4950	1			T2	1		T83	1		T56	112
invalid_ep[0xe]	4902	1			T2	1		T20	3		T56	87
invalid_ep[0xf]	4804	1			T83	1		T56	99		T210	1
endpoints[0x0]	12863	1			T2	1		T17	46		T5	107
endpoints[0x1]	13547	1			T1	15		T2	2		T17	50
endpoints[0x2]	12119	1			T1	16		T2	1		T17	53
endpoints[0x3]	12994	1			T1	15		T2	2		T17	43
endpoints[0x4]	14144	1			T1	4		T15	8		T17	52
endpoints[0x5]	15687	1			T1	14		T2	1		T17	39
endpoints[0x6]	13823	1			T1	2		T2	2		T17	52
endpoints[0x7]	12855	1			T1	15		T2	1		T17	45
endpoints[0x8]	13655	1			T2	1		T17	41		T20	4
endpoints[0x9]	12714	1			T1	15		T17	44		T18	3
endpoints[0xa]	14443	1			T1	1		T2	1		T17	45
endpoints[0xb]	14841	1			T1	17		T2	2		T17	39

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	24419	1			T1	10		T2	3		T15	8
pkt_types[PidTypeOutToken]	77244	1			T1	34		T2	5		T17	281
pkt_types[PidTypeInToken]	63000	1			T1	49		T2	8		T17	268

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1064	1			T56	25		T111	12		T212	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1079	1			T2	1		T56	39		T111	8
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1085	1			T20	1		T56	28		T110	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1119	1			T56	36		T210	1		T111	12
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1681	1			T5	21		T85	7		T56	25
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1565	1			T56	15		T111	23		T334	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1725	1			T1	4		T28	1		T56	26
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1656	1			T4	31		T28	2		T85	4
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1755	1			T15	8		T56	29		T82	2
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1716	1			T1	2		T83	1		T56	28
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1655	1			T56	29		T110	1		T111	19
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1716	1			T1	2		T56	33		T111	13
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1704	1			T2	1		T36	1		T56	32
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1628	1			T1	2		T18	1		T20	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1639	1			T2	1		T18	2		T331	4
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1632	1			T56	29		T111	14		T211	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1651	1			T2	1		T56	26		T111	22
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1648	1			T56	16		T110	1		T111	21
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1652	1			T20	1		T56	17		T111	9
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1549	1			T83	1		T56	21		T111	10
pkt_types[PidTypeOutToken]	endpoints[0x0]	4867	1			T17	26		T5	32		T158	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	5919	1			T1	6		T2	2		T17	28
pkt_types[PidTypeOutToken]	endpoints[0x2]	4549	1			T1	2		T17	27		T20	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5134	1			T1	7		T17	23		T4	30
pkt_types[PidTypeOutToken]	endpoints[0x4]	6318	1			T17	26		T37	1		T56	29
pkt_types[PidTypeOutToken]	endpoints[0x5]	7564	1			T1	4		T17	16		T56	22
pkt_types[PidTypeOutToken]	endpoints[0x6]	6076	1			T2	1		T17	27		T21	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	4710	1			T1	4		T17	16		T19	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	6275	1			T17	20		T20	1		T51	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	4874	1			T1	4		T17	23		T18	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	7031	1			T17	26		T18	3		T85	9
pkt_types[PidTypeOutToken]	endpoints[0xb]	7427	1			T1	7		T2	1		T17	23
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1130	1			T2	1		T20	1		T83	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1131	1			T83	1		T56	31		T111	7
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1073	1			T2	1		T56	21		T111	12
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1067	1			T56	25		T111	17		T415	1
pkt_types[PidTypeInToken]	endpoints[0x0]	5156	1			T2	1		T17	20		T5	54
pkt_types[PidTypeInToken]	endpoints[0x1]	4897	1			T1	7		T17	22		T20	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4643	1			T1	7		T2	1		T17	26
pkt_types[PidTypeInToken]	endpoints[0x3]	5004	1			T1	7		T2	1		T17	20
pkt_types[PidTypeInToken]	endpoints[0x4]	4882	1			T17	26		T37	1		T56	18
pkt_types[PidTypeInToken]	endpoints[0x5]	5247	1			T1	7		T2	1		T17	23
pkt_types[PidTypeInToken]	endpoints[0x6]	4871	1			T2	1		T17	25		T27	1
pkt_types[PidTypeInToken]	endpoints[0x7]	5232	1			T1	7		T2	1		T17	29
pkt_types[PidTypeInToken]	endpoints[0x8]	4500	1			T17	21		T36	1		T56	15
pkt_types[PidTypeInToken]	endpoints[0x9]	5046	1			T1	7		T17	21		T18	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4533	1			T17	19		T18	2		T20	3
pkt_types[PidTypeInToken]	endpoints[0xb]	4588	1			T1	7		T17	16		T83	1