Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T245	7		T242	4		T243	7
all_values[1]	263	1			T245	7		T242	4		T243	7
all_values[2]	263	1			T245	7		T242	4		T243	7
all_values[3]	263	1			T245	7		T242	4		T243	7
all_values[4]	263	1			T245	7		T242	4		T243	7
all_values[5]	263	1			T245	7		T242	4		T243	7
all_values[6]	263	1			T245	7		T242	4		T243	7
all_values[7]	263	1			T245	7		T242	4		T243	7
all_values[8]	263	1			T245	7		T242	4		T243	7
all_values[9]	263	1			T245	7		T242	4		T243	7
all_values[10]	263	1			T245	7		T242	4		T243	7
all_values[11]	263	1			T245	7		T242	4		T243	7
all_values[12]	263	1			T245	7		T242	4		T243	7
all_values[13]	263	1			T245	7		T242	4		T243	7
all_values[14]	263	1			T245	7		T242	4		T243	7
all_values[15]	263	1			T245	7		T242	4		T243	7
all_values[16]	263	1			T245	7		T242	4		T243	7
all_values[17]	263	1			T245	7		T242	4		T243	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6228

1

T245

168

T242

80

T243

182

auto[1]

2188

1

T245

56

T242

48

T243

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5753

1

T245

143

T242

84

T243

150

auto[1]

2663

1

T245

81

T242

44

T243

74

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5002

1

T245

122

T242

84

T243

132

auto[1]

3414

1

T245

102

T242

44

T243

92

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	88	1			T245	5		T242	1		T243	5
all_values[0]	auto[0]	auto[1]	auto[0]	77	1			T242	3		T243	1		T244	4
all_values[0]	auto[1]	auto[0]	auto[1]	52	1			T245	2		T243	1		T244	2
all_values[0]	auto[1]	auto[1]	auto[1]	46	1			T323	1		T348	1		T349	1
all_values[1]	auto[0]	auto[0]	auto[0]	95	1			T242	1		T243	3		T244	3
all_values[1]	auto[0]	auto[1]	auto[0]	68	1			T245	1		T242	1		T243	2
all_values[1]	auto[1]	auto[0]	auto[1]	47	1			T245	1		T243	2		T244	1
all_values[1]	auto[1]	auto[1]	auto[1]	53	1			T245	5		T242	2		T244	1
all_values[2]	auto[0]	auto[0]	auto[0]	34	1			T350	1		T351	2		T352	1
all_values[2]	auto[0]	auto[0]	auto[1]	43	1			T245	3		T243	3		T244	2
all_values[2]	auto[0]	auto[1]	auto[0]	44	1			T244	2		T349	2		T353	1
all_values[2]	auto[0]	auto[1]	auto[1]	32	1			T242	2		T244	1		T323	1
all_values[2]	auto[1]	auto[0]	auto[1]	61	1			T245	4		T242	1		T243	4
all_values[2]	auto[1]	auto[1]	auto[1]	49	1			T242	1		T244	2		T323	1
all_values[3]	auto[0]	auto[0]	auto[0]	61	1			T245	1		T242	1		T243	2
all_values[3]	auto[0]	auto[0]	auto[1]	32	1			T243	2		T244	1		T323	1
all_values[3]	auto[0]	auto[1]	auto[0]	35	1			T245	1		T242	1		T243	1
all_values[3]	auto[0]	auto[1]	auto[1]	37	1			T245	2		T244	2		T349	1
all_values[3]	auto[1]	auto[0]	auto[1]	55	1			T245	1		T242	1		T243	2
all_values[3]	auto[1]	auto[1]	auto[1]	43	1			T245	2		T242	1		T244	1
all_values[4]	auto[0]	auto[0]	auto[0]	54	1			T243	1		T244	2		T323	3
all_values[4]	auto[0]	auto[0]	auto[1]	33	1			T245	1		T243	1		T349	1
all_values[4]	auto[0]	auto[1]	auto[0]	48	1			T242	1		T243	1		T244	1
all_values[4]	auto[0]	auto[1]	auto[1]	23	1			T245	1		T242	1		T323	1
all_values[4]	auto[1]	auto[0]	auto[1]	65	1			T245	4		T243	3		T244	4
all_values[4]	auto[1]	auto[1]	auto[1]	40	1			T245	1		T242	2		T243	1
all_values[5]	auto[0]	auto[0]	auto[0]	54	1			T245	1		T243	4		T244	1
all_values[5]	auto[0]	auto[0]	auto[1]	24	1			T245	1		T323	2		T324	1
all_values[5]	auto[0]	auto[1]	auto[0]	44	1			T242	1		T244	2		T323	2
all_values[5]	auto[0]	auto[1]	auto[1]	29	1			T245	1		T242	2		T243	1
all_values[5]	auto[1]	auto[0]	auto[1]	54	1			T245	2		T242	1		T244	1
all_values[5]	auto[1]	auto[1]	auto[1]	58	1			T245	2		T243	2		T244	2
all_values[6]	auto[0]	auto[0]	auto[0]	48	1			T242	2		T244	3		T323	2
all_values[6]	auto[0]	auto[0]	auto[1]	27	1			T245	1		T243	2		T323	1
all_values[6]	auto[0]	auto[1]	auto[0]	55	1			T245	2		T242	2		T323	2
all_values[6]	auto[0]	auto[1]	auto[1]	30	1			T243	2		T353	1		T324	1
all_values[6]	auto[1]	auto[0]	auto[1]	56	1			T245	3		T243	2		T244	3
all_values[6]	auto[1]	auto[1]	auto[1]	47	1			T245	1		T243	1		T244	1
all_values[7]	auto[0]	auto[0]	auto[0]	92	1			T245	1		T243	2		T244	1
all_values[7]	auto[0]	auto[1]	auto[0]	67	1			T245	1		T242	3		T243	1
all_values[7]	auto[1]	auto[0]	auto[1]	61	1			T245	4		T243	3		T323	1
all_values[7]	auto[1]	auto[1]	auto[1]	43	1			T245	1		T242	1		T243	1
all_values[8]	auto[0]	auto[0]	auto[0]	87	1			T245	1		T242	1		T243	4
all_values[8]	auto[0]	auto[1]	auto[0]	81	1			T245	3		T242	2		T243	2
all_values[8]	auto[1]	auto[0]	auto[1]	49	1			T245	2		T242	1		T243	1
all_values[8]	auto[1]	auto[1]	auto[1]	46	1			T245	1		T323	1		T348	1
all_values[9]	auto[0]	auto[0]	auto[0]	74	1			T245	4		T323	3		T349	2
all_values[9]	auto[0]	auto[0]	auto[1]	24	1			T242	2		T243	1		T323	2
all_values[9]	auto[0]	auto[1]	auto[0]	52	1			T245	1		T243	3		T244	1
all_values[9]	auto[0]	auto[1]	auto[1]	21	1			T244	1		T349	1		T354	2
all_values[9]	auto[1]	auto[0]	auto[1]	51	1			T245	2		T243	1		T244	1
all_values[9]	auto[1]	auto[1]	auto[1]	41	1			T242	2		T243	2		T244	4
all_values[10]	auto[0]	auto[0]	auto[0]	54	1			T245	1		T243	2		T244	1
all_values[10]	auto[0]	auto[0]	auto[1]	23	1			T242	2		T243	1		T348	2
all_values[10]	auto[0]	auto[1]	auto[0]	45	1			T245	5		T244	1		T323	3
all_values[10]	auto[0]	auto[1]	auto[1]	28	1			T242	1		T324	2		T351	1
all_values[10]	auto[1]	auto[0]	auto[1]	68	1			T245	1		T242	1		T243	3
all_values[10]	auto[1]	auto[1]	auto[1]	45	1			T243	1		T244	2		T323	3
all_values[11]	auto[0]	auto[0]	auto[0]	52	1			T243	2		T323	1		T348	1
all_values[11]	auto[0]	auto[0]	auto[1]	25	1			T244	1		T323	1		T349	1
all_values[11]	auto[0]	auto[1]	auto[0]	40	1			T245	2		T243	3		T324	3
all_values[11]	auto[0]	auto[1]	auto[1]	28	1			T245	1		T242	2		T244	1
all_values[11]	auto[1]	auto[0]	auto[1]	63	1			T245	3		T244	5		T323	2
all_values[11]	auto[1]	auto[1]	auto[1]	55	1			T245	1		T242	2		T243	2
all_values[12]	auto[0]	auto[0]	auto[0]	43	1			T243	1		T244	1		T323	3
all_values[12]	auto[0]	auto[0]	auto[1]	28	1			T348	1		T349	3		T355	1
all_values[12]	auto[0]	auto[1]	auto[0]	44	1			T242	1		T243	1		T244	1
all_values[12]	auto[0]	auto[1]	auto[1]	25	1			T245	3		T243	1		T349	1
all_values[12]	auto[1]	auto[0]	auto[1]	70	1			T245	3		T242	1		T243	3
all_values[12]	auto[1]	auto[1]	auto[1]	53	1			T245	1		T242	2		T243	1
all_values[13]	auto[0]	auto[0]	auto[0]	48	1			T245	2		T243	1		T244	1
all_values[13]	auto[0]	auto[0]	auto[1]	24	1			T348	1		T353	2		T351	1
all_values[13]	auto[0]	auto[1]	auto[0]	34	1			T242	2		T244	4		T323	1
all_values[13]	auto[0]	auto[1]	auto[1]	37	1			T245	2		T242	1		T243	2
all_values[13]	auto[1]	auto[0]	auto[1]	67	1			T245	1		T242	1		T243	1
all_values[13]	auto[1]	auto[1]	auto[1]	53	1			T245	2		T243	3		T323	2
all_values[14]	auto[0]	auto[0]	auto[0]	49	1			T245	1		T242	1		T243	2
all_values[14]	auto[0]	auto[0]	auto[1]	20	1			T242	1		T243	1		T244	1
all_values[14]	auto[0]	auto[1]	auto[0]	53	1			T245	1		T242	1		T243	1
all_values[14]	auto[0]	auto[1]	auto[1]	36	1			T245	2		T244	2		T323	1
all_values[14]	auto[1]	auto[0]	auto[1]	57	1			T245	2		T242	1		T243	3
all_values[14]	auto[1]	auto[1]	auto[1]	48	1			T245	1		T244	1		T323	4
all_values[15]	auto[0]	auto[0]	auto[0]	50	1			T245	1		T243	1		T244	1
all_values[15]	auto[0]	auto[0]	auto[1]	25	1			T244	1		T349	1		T350	1
all_values[15]	auto[0]	auto[1]	auto[0]	48	1			T245	5		T243	1		T244	3
all_values[15]	auto[0]	auto[1]	auto[1]	33	1			T242	2		T243	2		T323	2
all_values[15]	auto[1]	auto[0]	auto[1]	63	1			T245	1		T243	2		T244	2
all_values[15]	auto[1]	auto[1]	auto[1]	44	1			T242	2		T243	1		T323	3
all_values[16]	auto[0]	auto[0]	auto[0]	56	1			T245	1		T242	1		T243	1
all_values[16]	auto[0]	auto[0]	auto[1]	32	1			T245	1		T243	3		T348	1
all_values[16]	auto[0]	auto[1]	auto[0]	36	1			T244	1		T323	1		T349	3
all_values[16]	auto[0]	auto[1]	auto[1]	32	1			T245	2		T242	1		T244	2
all_values[16]	auto[1]	auto[0]	auto[1]	60	1			T245	3		T243	2		T323	1
all_values[16]	auto[1]	auto[1]	auto[1]	47	1			T242	2		T243	1		T244	3
all_values[17]	auto[0]	auto[0]	auto[0]	85	1			T245	3		T242	1		T243	4
all_values[17]	auto[0]	auto[1]	auto[0]	76	1			T245	1		T242	1		T244	2
all_values[17]	auto[1]	auto[0]	auto[1]	63	1			T245	2		T242	2		T243	2
all_values[17]	auto[1]	auto[1]	auto[1]	39	1			T245	1		T243	1		T244	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal