Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.56 98.14 95.89 97.44 94.92 98.34 98.17 93.03


Total test records in report: 3740
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html | tests63.html | tests64.html | tests65.html | tests66.html | tests67.html | tests68.html | tests69.html | tests70.html | tests71.html | tests72.html | tests73.html | tests74.html | tests75.html | tests76.html | tests77.html | tests78.html | tests79.html
T3571 /workspace/coverage/default/21.usbdev_in_iso.4023051112 Aug 13 06:36:39 PM PDT 24 Aug 13 06:36:40 PM PDT 24 229674678 ps
T3572 /workspace/coverage/default/20.usbdev_min_length_out_transaction.4115129927 Aug 13 06:36:37 PM PDT 24 Aug 13 06:36:38 PM PDT 24 193821643 ps
T3573 /workspace/coverage/default/5.usbdev_random_length_in_transaction.3368290780 Aug 13 06:34:09 PM PDT 24 Aug 13 06:34:10 PM PDT 24 230725262 ps
T3574 /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2837269089 Aug 13 06:37:00 PM PDT 24 Aug 13 06:38:38 PM PDT 24 3420269053 ps
T3575 /workspace/coverage/default/72.usbdev_tx_rx_disruption.67515520 Aug 13 06:41:02 PM PDT 24 Aug 13 06:41:03 PM PDT 24 478942063 ps
T3576 /workspace/coverage/default/1.usbdev_link_suspend.3295819828 Aug 13 06:33:14 PM PDT 24 Aug 13 06:33:31 PM PDT 24 10287518425 ps
T3577 /workspace/coverage/default/312.usbdev_tx_rx_disruption.480118116 Aug 13 06:41:53 PM PDT 24 Aug 13 06:41:55 PM PDT 24 435120486 ps
T3578 /workspace/coverage/default/8.usbdev_max_length_in_transaction.3904378371 Aug 13 06:34:38 PM PDT 24 Aug 13 06:34:39 PM PDT 24 236887723 ps
T3579 /workspace/coverage/default/109.usbdev_endpoint_types.422551413 Aug 13 06:41:28 PM PDT 24 Aug 13 06:41:32 PM PDT 24 580701788 ps
T3580 /workspace/coverage/default/204.usbdev_tx_rx_disruption.753442249 Aug 13 06:42:04 PM PDT 24 Aug 13 06:42:06 PM PDT 24 564486155 ps
T3581 /workspace/coverage/default/12.usbdev_out_iso.1333873342 Aug 13 06:35:20 PM PDT 24 Aug 13 06:35:21 PM PDT 24 167758930 ps
T3582 /workspace/coverage/default/17.usbdev_endpoint_access.562290660 Aug 13 06:36:09 PM PDT 24 Aug 13 06:36:11 PM PDT 24 934905559 ps
T3583 /workspace/coverage/default/32.usbdev_bitstuff_err.3575400899 Aug 13 06:38:20 PM PDT 24 Aug 13 06:38:21 PM PDT 24 149986212 ps
T3584 /workspace/coverage/default/16.usbdev_in_trans.4217502802 Aug 13 06:35:58 PM PDT 24 Aug 13 06:35:59 PM PDT 24 169581057 ps
T3585 /workspace/coverage/default/3.usbdev_disconnected.1310764434 Aug 13 06:33:43 PM PDT 24 Aug 13 06:33:44 PM PDT 24 138777204 ps
T3586 /workspace/coverage/default/43.usbdev_rx_crc_err.2876424903 Aug 13 06:40:11 PM PDT 24 Aug 13 06:40:17 PM PDT 24 144286283 ps
T3587 /workspace/coverage/default/18.usbdev_min_length_out_transaction.1464093497 Aug 13 06:36:18 PM PDT 24 Aug 13 06:36:19 PM PDT 24 175149338 ps
T3588 /workspace/coverage/default/143.usbdev_endpoint_types.3763873201 Aug 13 06:41:13 PM PDT 24 Aug 13 06:41:14 PM PDT 24 301793361 ps
T3589 /workspace/coverage/default/30.usbdev_nak_trans.3743454883 Aug 13 06:38:03 PM PDT 24 Aug 13 06:38:04 PM PDT 24 222508627 ps
T3590 /workspace/coverage/default/40.usbdev_invalid_sync.2724494315 Aug 13 06:39:45 PM PDT 24 Aug 13 06:40:04 PM PDT 24 2407142648 ps
T3591 /workspace/coverage/default/28.usbdev_bitstuff_err.4287362454 Aug 13 06:38:03 PM PDT 24 Aug 13 06:38:04 PM PDT 24 166570520 ps
T3592 /workspace/coverage/default/1.usbdev_disable_endpoint.388119346 Aug 13 06:33:05 PM PDT 24 Aug 13 06:33:06 PM PDT 24 513836340 ps
T3593 /workspace/coverage/default/198.usbdev_tx_rx_disruption.4165504202 Aug 13 06:41:45 PM PDT 24 Aug 13 06:41:46 PM PDT 24 481829582 ps
T3594 /workspace/coverage/default/17.usbdev_av_buffer.3481961146 Aug 13 06:36:14 PM PDT 24 Aug 13 06:36:15 PM PDT 24 182537820 ps
T3595 /workspace/coverage/default/107.usbdev_tx_rx_disruption.449179596 Aug 13 06:41:07 PM PDT 24 Aug 13 06:41:09 PM PDT 24 468865160 ps
T3596 /workspace/coverage/default/24.usbdev_data_toggle_restore.1470405822 Aug 13 06:37:08 PM PDT 24 Aug 13 06:37:10 PM PDT 24 501686060 ps
T3597 /workspace/coverage/default/11.usbdev_device_address.2535175369 Aug 13 06:35:16 PM PDT 24 Aug 13 06:36:36 PM PDT 24 47884622291 ps
T3598 /workspace/coverage/default/43.usbdev_in_iso.3277277183 Aug 13 06:40:04 PM PDT 24 Aug 13 06:40:06 PM PDT 24 228452851 ps
T3599 /workspace/coverage/default/8.usbdev_av_buffer.728577551 Aug 13 06:34:41 PM PDT 24 Aug 13 06:34:42 PM PDT 24 149228724 ps
T3600 /workspace/coverage/default/287.usbdev_tx_rx_disruption.2617147208 Aug 13 06:41:55 PM PDT 24 Aug 13 06:41:56 PM PDT 24 495407221 ps
T3601 /workspace/coverage/default/24.usbdev_max_length_out_transaction.605989471 Aug 13 06:37:27 PM PDT 24 Aug 13 06:37:28 PM PDT 24 273715095 ps
T3602 /workspace/coverage/default/24.usbdev_max_length_in_transaction.2331020934 Aug 13 06:37:29 PM PDT 24 Aug 13 06:37:35 PM PDT 24 231891124 ps
T3603 /workspace/coverage/default/19.usbdev_random_length_out_transaction.1913716343 Aug 13 06:36:34 PM PDT 24 Aug 13 06:36:35 PM PDT 24 167721520 ps
T3604 /workspace/coverage/default/12.usbdev_av_buffer.2154413112 Aug 13 06:35:21 PM PDT 24 Aug 13 06:35:22 PM PDT 24 155791537 ps
T3605 /workspace/coverage/default/125.usbdev_tx_rx_disruption.4223539032 Aug 13 06:41:37 PM PDT 24 Aug 13 06:41:39 PM PDT 24 508077836 ps
T3606 /workspace/coverage/default/75.usbdev_tx_rx_disruption.929202094 Aug 13 06:40:58 PM PDT 24 Aug 13 06:41:00 PM PDT 24 463583226 ps
T3607 /workspace/coverage/default/44.usbdev_device_address.1097831774 Aug 13 06:40:05 PM PDT 24 Aug 13 06:40:53 PM PDT 24 26680946514 ps
T264 /workspace/coverage/default/496.usbdev_tx_rx_disruption.3741643890 Aug 13 06:42:26 PM PDT 24 Aug 13 06:42:28 PM PDT 24 502649122 ps
T3608 /workspace/coverage/default/6.usbdev_tx_rx_disruption.1694004455 Aug 13 06:34:25 PM PDT 24 Aug 13 06:34:27 PM PDT 24 515022847 ps
T3609 /workspace/coverage/default/74.usbdev_tx_rx_disruption.2145078967 Aug 13 06:41:09 PM PDT 24 Aug 13 06:41:11 PM PDT 24 486148503 ps
T3610 /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3484852574 Aug 13 06:39:01 PM PDT 24 Aug 13 06:39:24 PM PDT 24 2936923994 ps
T3611 /workspace/coverage/default/20.usbdev_rx_crc_err.1140572978 Aug 13 06:36:39 PM PDT 24 Aug 13 06:36:40 PM PDT 24 189186717 ps
T3612 /workspace/coverage/default/160.usbdev_endpoint_types.3377377023 Aug 13 06:41:29 PM PDT 24 Aug 13 06:41:30 PM PDT 24 200544405 ps
T3613 /workspace/coverage/default/22.usbdev_in_iso.1814389825 Aug 13 06:36:50 PM PDT 24 Aug 13 06:36:51 PM PDT 24 217470806 ps
T3614 /workspace/coverage/default/41.usbdev_aon_wake_reset.902809304 Aug 13 06:39:44 PM PDT 24 Aug 13 06:40:02 PM PDT 24 14600342981 ps
T3615 /workspace/coverage/default/71.usbdev_endpoint_types.2914048027 Aug 13 06:41:24 PM PDT 24 Aug 13 06:41:25 PM PDT 24 243301546 ps
T3616 /workspace/coverage/default/133.usbdev_endpoint_types.1938780423 Aug 13 06:41:29 PM PDT 24 Aug 13 06:41:30 PM PDT 24 274977865 ps
T3617 /workspace/coverage/default/142.usbdev_tx_rx_disruption.2816091783 Aug 13 06:41:35 PM PDT 24 Aug 13 06:41:37 PM PDT 24 577448323 ps
T3618 /workspace/coverage/default/49.usbdev_phy_config_pinflip.4090466969 Aug 13 06:41:01 PM PDT 24 Aug 13 06:41:02 PM PDT 24 237085669 ps
T3619 /workspace/coverage/default/25.usbdev_pkt_sent.1410488966 Aug 13 06:37:34 PM PDT 24 Aug 13 06:37:35 PM PDT 24 203237112 ps
T3620 /workspace/coverage/default/49.usbdev_rx_full.3947449275 Aug 13 06:40:58 PM PDT 24 Aug 13 06:41:00 PM PDT 24 409466083 ps
T3621 /workspace/coverage/default/4.usbdev_rx_pid_err.1487724113 Aug 13 06:34:00 PM PDT 24 Aug 13 06:34:01 PM PDT 24 155366594 ps
T3622 /workspace/coverage/default/250.usbdev_tx_rx_disruption.4114776888 Aug 13 06:42:21 PM PDT 24 Aug 13 06:42:23 PM PDT 24 494709891 ps
T3623 /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.71915120 Aug 13 06:37:05 PM PDT 24 Aug 13 06:37:20 PM PDT 24 699150205 ps
T3624 /workspace/coverage/default/35.usbdev_in_iso.1019294905 Aug 13 06:38:51 PM PDT 24 Aug 13 06:38:53 PM PDT 24 173329646 ps
T3625 /workspace/coverage/default/52.usbdev_tx_rx_disruption.583172602 Aug 13 06:41:01 PM PDT 24 Aug 13 06:41:03 PM PDT 24 457117510 ps
T3626 /workspace/coverage/default/192.usbdev_tx_rx_disruption.159296394 Aug 13 06:41:56 PM PDT 24 Aug 13 06:41:58 PM PDT 24 655016684 ps
T3627 /workspace/coverage/default/44.usbdev_phy_pins_sense.814453658 Aug 13 06:40:10 PM PDT 24 Aug 13 06:40:11 PM PDT 24 83958377 ps
T3628 /workspace/coverage/default/82.usbdev_endpoint_types.2637296591 Aug 13 06:41:27 PM PDT 24 Aug 13 06:41:28 PM PDT 24 264020207 ps
T3629 /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2478689559 Aug 13 06:35:56 PM PDT 24 Aug 13 06:37:05 PM PDT 24 2355647172 ps
T3630 /workspace/coverage/default/0.usbdev_streaming_out.521120935 Aug 13 06:33:08 PM PDT 24 Aug 13 06:34:24 PM PDT 24 2593686134 ps
T3631 /workspace/coverage/default/41.usbdev_device_address.428007906 Aug 13 06:39:41 PM PDT 24 Aug 13 06:40:24 PM PDT 24 26294981320 ps
T3632 /workspace/coverage/default/7.usbdev_device_address.1440624093 Aug 13 06:34:29 PM PDT 24 Aug 13 06:34:53 PM PDT 24 15448965123 ps
T3633 /workspace/coverage/default/403.usbdev_tx_rx_disruption.2577123621 Aug 13 06:41:54 PM PDT 24 Aug 13 06:41:56 PM PDT 24 546239490 ps
T3634 /workspace/coverage/default/26.usbdev_smoke.2783848248 Aug 13 06:37:31 PM PDT 24 Aug 13 06:37:37 PM PDT 24 251745531 ps
T245 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1966267989 Aug 13 05:13:32 PM PDT 24 Aug 13 05:13:33 PM PDT 24 78959297 ps
T234 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2460791847 Aug 13 05:13:25 PM PDT 24 Aug 13 05:13:27 PM PDT 24 186804941 ps
T242 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2563720776 Aug 13 05:13:33 PM PDT 24 Aug 13 05:13:34 PM PDT 24 41584121 ps
T290 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3070936477 Aug 13 05:13:20 PM PDT 24 Aug 13 05:13:21 PM PDT 24 66603479 ps
T269 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1673541573 Aug 13 05:13:00 PM PDT 24 Aug 13 05:13:01 PM PDT 24 107953817 ps
T270 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.739296304 Aug 13 05:13:11 PM PDT 24 Aug 13 05:13:13 PM PDT 24 257444953 ps
T271 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2843562488 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:11 PM PDT 24 55624709 ps
T243 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2248626585 Aug 13 05:13:09 PM PDT 24 Aug 13 05:13:10 PM PDT 24 46772919 ps
T315 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1402866517 Aug 13 05:13:27 PM PDT 24 Aug 13 05:13:28 PM PDT 24 118071942 ps
T235 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.313269186 Aug 13 05:13:19 PM PDT 24 Aug 13 05:13:25 PM PDT 24 901104961 ps
T244 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4237390192 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:10 PM PDT 24 73697857 ps
T316 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.134072086 Aug 13 05:13:08 PM PDT 24 Aug 13 05:13:09 PM PDT 24 62712293 ps
T317 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3149595930 Aug 13 05:13:04 PM PDT 24 Aug 13 05:13:06 PM PDT 24 169537113 ps
T318 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3912684805 Aug 13 05:13:26 PM PDT 24 Aug 13 05:13:28 PM PDT 24 252861887 ps
T323 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1692302080 Aug 13 05:13:32 PM PDT 24 Aug 13 05:13:33 PM PDT 24 50935500 ps
T236 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1853440606 Aug 13 05:13:16 PM PDT 24 Aug 13 05:13:18 PM PDT 24 181674802 ps
T348 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3208979994 Aug 13 05:13:25 PM PDT 24 Aug 13 05:13:26 PM PDT 24 84227127 ps
T349 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2389702858 Aug 13 05:13:27 PM PDT 24 Aug 13 05:13:28 PM PDT 24 61258916 ps
T319 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1512223297 Aug 13 05:13:08 PM PDT 24 Aug 13 05:13:10 PM PDT 24 81594561 ps
T353 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1406699806 Aug 13 05:13:33 PM PDT 24 Aug 13 05:13:34 PM PDT 24 76579876 ps
T320 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4168941134 Aug 13 05:12:58 PM PDT 24 Aug 13 05:13:00 PM PDT 24 75929349 ps
T3635 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1542018058 Aug 13 05:13:13 PM PDT 24 Aug 13 05:13:15 PM PDT 24 235586530 ps
T3636 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1224132079 Aug 13 05:13:26 PM PDT 24 Aug 13 05:13:27 PM PDT 24 75272949 ps
T324 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3040544578 Aug 13 05:13:34 PM PDT 24 Aug 13 05:13:35 PM PDT 24 48637900 ps
T350 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.864747617 Aug 13 05:13:24 PM PDT 24 Aug 13 05:13:25 PM PDT 24 78458806 ps
T302 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4268443399 Aug 13 05:13:26 PM PDT 24 Aug 13 05:13:28 PM PDT 24 72139178 ps
T303 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4169357657 Aug 13 05:13:06 PM PDT 24 Aug 13 05:13:07 PM PDT 24 104996901 ps
T267 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.198057961 Aug 13 05:13:02 PM PDT 24 Aug 13 05:13:05 PM PDT 24 115524997 ps
T354 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.414561564 Aug 13 05:13:02 PM PDT 24 Aug 13 05:13:03 PM PDT 24 51440014 ps
T268 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2654543748 Aug 13 05:13:11 PM PDT 24 Aug 13 05:13:13 PM PDT 24 401079823 ps
T3637 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1698797708 Aug 13 05:13:14 PM PDT 24 Aug 13 05:13:15 PM PDT 24 38371526 ps
T3638 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.551434362 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:20 PM PDT 24 119859494 ps
T304 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.942026356 Aug 13 05:13:11 PM PDT 24 Aug 13 05:13:12 PM PDT 24 82817164 ps
T275 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2363595747 Aug 13 05:13:31 PM PDT 24 Aug 13 05:13:36 PM PDT 24 1445374166 ps
T305 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2944954647 Aug 13 05:13:03 PM PDT 24 Aug 13 05:13:04 PM PDT 24 66133820 ps
T291 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.976457519 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:19 PM PDT 24 113930745 ps
T292 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3868455367 Aug 13 05:13:07 PM PDT 24 Aug 13 05:13:08 PM PDT 24 116700568 ps
T351 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1843335375 Aug 13 05:13:19 PM PDT 24 Aug 13 05:13:19 PM PDT 24 53158068 ps
T293 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1490472510 Aug 13 05:13:03 PM PDT 24 Aug 13 05:13:05 PM PDT 24 170984932 ps
T283 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3165662055 Aug 13 05:13:02 PM PDT 24 Aug 13 05:13:04 PM PDT 24 134224490 ps
T278 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3214195914 Aug 13 05:13:26 PM PDT 24 Aug 13 05:13:29 PM PDT 24 100544001 ps
T294 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1021841671 Aug 13 05:13:02 PM PDT 24 Aug 13 05:13:08 PM PDT 24 1637280194 ps
T355 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2715785367 Aug 13 05:13:32 PM PDT 24 Aug 13 05:13:33 PM PDT 24 39224941 ps
T279 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.237523935 Aug 13 05:13:26 PM PDT 24 Aug 13 05:13:28 PM PDT 24 192910871 ps
T503 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1449475928 Aug 13 05:12:56 PM PDT 24 Aug 13 05:13:02 PM PDT 24 1436768559 ps
T306 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2604402114 Aug 13 05:12:57 PM PDT 24 Aug 13 05:12:59 PM PDT 24 177621509 ps
T285 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1294300703 Aug 13 05:13:04 PM PDT 24 Aug 13 05:13:06 PM PDT 24 140090147 ps
T307 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3782401595 Aug 13 05:13:05 PM PDT 24 Aug 13 05:13:06 PM PDT 24 123961324 ps
T3639 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.84276544 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:20 PM PDT 24 198046399 ps
T284 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2006309745 Aug 13 05:13:12 PM PDT 24 Aug 13 05:13:14 PM PDT 24 110936164 ps
T3640 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1433472700 Aug 13 05:13:33 PM PDT 24 Aug 13 05:13:34 PM PDT 24 94544810 ps
T308 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.323845704 Aug 13 05:13:03 PM PDT 24 Aug 13 05:13:13 PM PDT 24 1673979372 ps
T3641 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1279703135 Aug 13 05:13:35 PM PDT 24 Aug 13 05:13:36 PM PDT 24 42335810 ps
T3642 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.942449909 Aug 13 05:13:32 PM PDT 24 Aug 13 05:13:33 PM PDT 24 32447274 ps
T309 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3808252713 Aug 13 05:13:02 PM PDT 24 Aug 13 05:13:05 PM PDT 24 212043753 ps
T352 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3394571897 Aug 13 05:13:21 PM PDT 24 Aug 13 05:13:21 PM PDT 24 35653707 ps
T310 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3522703345 Aug 13 05:12:58 PM PDT 24 Aug 13 05:13:02 PM PDT 24 388413389 ps
T3643 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3084965143 Aug 13 05:13:36 PM PDT 24 Aug 13 05:13:37 PM PDT 24 57584066 ps
T282 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.930692211 Aug 13 05:13:19 PM PDT 24 Aug 13 05:13:21 PM PDT 24 128362056 ps
T3644 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4129002554 Aug 13 05:13:19 PM PDT 24 Aug 13 05:13:21 PM PDT 24 323938696 ps
T286 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1158225480 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:12 PM PDT 24 85089549 ps
T287 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2040861980 Aug 13 05:13:05 PM PDT 24 Aug 13 05:13:07 PM PDT 24 153115581 ps
T3645 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2403679198 Aug 13 05:13:35 PM PDT 24 Aug 13 05:13:36 PM PDT 24 34040920 ps
T289 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1000714278 Aug 13 05:13:26 PM PDT 24 Aug 13 05:13:28 PM PDT 24 273866864 ps
T3646 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1622736025 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:12 PM PDT 24 140398666 ps
T311 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3330234886 Aug 13 05:13:14 PM PDT 24 Aug 13 05:13:15 PM PDT 24 95603498 ps
T3647 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1607794484 Aug 13 05:13:16 PM PDT 24 Aug 13 05:13:17 PM PDT 24 109334679 ps
T3648 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1581385984 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:11 PM PDT 24 154176932 ps
T3649 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3884766845 Aug 13 05:13:03 PM PDT 24 Aug 13 05:13:04 PM PDT 24 72952213 ps
T3650 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2541328112 Aug 13 05:13:26 PM PDT 24 Aug 13 05:13:28 PM PDT 24 86280678 ps
T3651 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2049167755 Aug 13 05:13:20 PM PDT 24 Aug 13 05:13:22 PM PDT 24 431119730 ps
T3652 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.877026389 Aug 13 05:13:17 PM PDT 24 Aug 13 05:13:18 PM PDT 24 46530696 ps
T3653 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1545135665 Aug 13 05:13:03 PM PDT 24 Aug 13 05:13:05 PM PDT 24 84674159 ps
T3654 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1547911769 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:11 PM PDT 24 42376077 ps
T3655 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3849803890 Aug 13 05:13:29 PM PDT 24 Aug 13 05:13:31 PM PDT 24 159049304 ps
T312 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1891247854 Aug 13 05:12:56 PM PDT 24 Aug 13 05:12:57 PM PDT 24 91496788 ps
T3656 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2174324843 Aug 13 05:13:11 PM PDT 24 Aug 13 05:13:14 PM PDT 24 288867827 ps
T512 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2091226797 Aug 13 05:13:03 PM PDT 24 Aug 13 05:13:06 PM PDT 24 463991382 ps
T3657 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3491853189 Aug 13 05:13:01 PM PDT 24 Aug 13 05:13:02 PM PDT 24 126173202 ps
T3658 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.147647639 Aug 13 05:13:36 PM PDT 24 Aug 13 05:13:36 PM PDT 24 35091039 ps
T3659 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1499563935 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:12 PM PDT 24 173572143 ps
T3660 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1191575204 Aug 13 05:12:56 PM PDT 24 Aug 13 05:12:57 PM PDT 24 83158290 ps
T507 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3570906399 Aug 13 05:13:02 PM PDT 24 Aug 13 05:13:07 PM PDT 24 907294352 ps
T3661 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1963015553 Aug 13 05:13:37 PM PDT 24 Aug 13 05:13:38 PM PDT 24 51937844 ps
T3662 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.482968478 Aug 13 05:13:07 PM PDT 24 Aug 13 05:13:11 PM PDT 24 749332919 ps
T288 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4189148777 Aug 13 05:13:13 PM PDT 24 Aug 13 05:13:16 PM PDT 24 224188511 ps
T3663 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2606319542 Aug 13 05:13:33 PM PDT 24 Aug 13 05:13:34 PM PDT 24 36545244 ps
T508 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2936763645 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:22 PM PDT 24 1160362753 ps
T3664 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1544335715 Aug 13 05:12:59 PM PDT 24 Aug 13 05:13:01 PM PDT 24 290591870 ps
T3665 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1101212015 Aug 13 05:13:19 PM PDT 24 Aug 13 05:13:20 PM PDT 24 98281433 ps
T3666 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3106988084 Aug 13 05:13:26 PM PDT 24 Aug 13 05:13:27 PM PDT 24 42215312 ps
T3667 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1443774371 Aug 13 05:13:33 PM PDT 24 Aug 13 05:13:34 PM PDT 24 40770546 ps
T3668 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3706122729 Aug 13 05:13:36 PM PDT 24 Aug 13 05:13:37 PM PDT 24 53064679 ps
T3669 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4163810600 Aug 13 05:12:58 PM PDT 24 Aug 13 05:13:00 PM PDT 24 373838408 ps
T3670 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3680841777 Aug 13 05:12:57 PM PDT 24 Aug 13 05:12:59 PM PDT 24 193415994 ps
T3671 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2996666873 Aug 13 05:13:33 PM PDT 24 Aug 13 05:13:34 PM PDT 24 79819510 ps
T3672 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2006561857 Aug 13 05:13:02 PM PDT 24 Aug 13 05:13:03 PM PDT 24 38821433 ps
T313 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2491336213 Aug 13 05:13:11 PM PDT 24 Aug 13 05:13:11 PM PDT 24 68752303 ps
T3673 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1634675895 Aug 13 05:13:09 PM PDT 24 Aug 13 05:13:12 PM PDT 24 99179583 ps
T3674 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3665336993 Aug 13 05:13:05 PM PDT 24 Aug 13 05:13:07 PM PDT 24 251598774 ps
T3675 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4010320946 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:19 PM PDT 24 52994860 ps
T3676 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3136835438 Aug 13 05:12:58 PM PDT 24 Aug 13 05:13:00 PM PDT 24 72814503 ps
T3677 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3039181164 Aug 13 05:13:33 PM PDT 24 Aug 13 05:13:34 PM PDT 24 45052577 ps
T3678 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3120688092 Aug 13 05:13:36 PM PDT 24 Aug 13 05:13:37 PM PDT 24 42281639 ps
T3679 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.279323346 Aug 13 05:13:27 PM PDT 24 Aug 13 05:13:28 PM PDT 24 71305970 ps
T504 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.464843594 Aug 13 05:13:08 PM PDT 24 Aug 13 05:13:14 PM PDT 24 938162197 ps
T3680 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3380085219 Aug 13 05:13:34 PM PDT 24 Aug 13 05:13:34 PM PDT 24 73590539 ps
T510 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2841626829 Aug 13 05:12:56 PM PDT 24 Aug 13 05:13:01 PM PDT 24 1151266329 ps
T3681 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.285786308 Aug 13 05:13:00 PM PDT 24 Aug 13 05:13:01 PM PDT 24 54065348 ps
T314 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.112933651 Aug 13 05:12:58 PM PDT 24 Aug 13 05:13:01 PM PDT 24 208511121 ps
T3682 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.568457511 Aug 13 05:13:00 PM PDT 24 Aug 13 05:13:01 PM PDT 24 76703864 ps
T3683 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.11557555 Aug 13 05:13:17 PM PDT 24 Aug 13 05:13:18 PM PDT 24 46170847 ps
T3684 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4203812879 Aug 13 05:12:59 PM PDT 24 Aug 13 05:13:00 PM PDT 24 128961427 ps
T3685 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3367976014 Aug 13 05:13:05 PM PDT 24 Aug 13 05:13:06 PM PDT 24 128529253 ps
T3686 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.111581788 Aug 13 05:13:02 PM PDT 24 Aug 13 05:13:06 PM PDT 24 337426121 ps
T3687 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4259087981 Aug 13 05:13:23 PM PDT 24 Aug 13 05:13:24 PM PDT 24 66506886 ps
T509 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2501097750 Aug 13 05:13:13 PM PDT 24 Aug 13 05:13:16 PM PDT 24 717462761 ps
T514 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3134553195 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:21 PM PDT 24 454870636 ps
T3688 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1191493726 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:12 PM PDT 24 87662649 ps
T3689 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.360141587 Aug 13 05:13:14 PM PDT 24 Aug 13 05:13:19 PM PDT 24 465201017 ps
T3690 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2302959411 Aug 13 05:13:23 PM PDT 24 Aug 13 05:13:26 PM PDT 24 96506567 ps
T3691 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.5078233 Aug 13 05:12:58 PM PDT 24 Aug 13 05:13:00 PM PDT 24 131309499 ps
T3692 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1312664249 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:11 PM PDT 24 97582845 ps
T3693 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1876005466 Aug 13 05:13:19 PM PDT 24 Aug 13 05:13:20 PM PDT 24 161742033 ps
T3694 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2401440047 Aug 13 05:13:04 PM PDT 24 Aug 13 05:13:05 PM PDT 24 120640367 ps
T513 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3739156591 Aug 13 05:13:27 PM PDT 24 Aug 13 05:13:31 PM PDT 24 531872372 ps
T3695 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2779838793 Aug 13 05:13:14 PM PDT 24 Aug 13 05:13:15 PM PDT 24 69580078 ps
T3696 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3163472391 Aug 13 05:13:33 PM PDT 24 Aug 13 05:13:34 PM PDT 24 70164965 ps
T3697 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1506112893 Aug 13 05:13:32 PM PDT 24 Aug 13 05:13:33 PM PDT 24 59773514 ps
T3698 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.371038987 Aug 13 05:13:04 PM PDT 24 Aug 13 05:13:08 PM PDT 24 628046804 ps
T3699 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1353420936 Aug 13 05:13:10 PM PDT 24 Aug 13 05:13:12 PM PDT 24 102250430 ps
T505 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.809135063 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:21 PM PDT 24 372347649 ps
T3700 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3911940117 Aug 13 05:13:09 PM PDT 24 Aug 13 05:13:11 PM PDT 24 83560562 ps
T3701 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3190344157 Aug 13 05:13:03 PM PDT 24 Aug 13 05:13:05 PM PDT 24 226260379 ps
T3702 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2663991610 Aug 13 05:13:06 PM PDT 24 Aug 13 05:13:10 PM PDT 24 909431358 ps
T511 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.748914872 Aug 13 05:13:00 PM PDT 24 Aug 13 05:13:05 PM PDT 24 755528534 ps
T3703 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.21023204 Aug 13 05:13:02 PM PDT 24 Aug 13 05:13:04 PM PDT 24 153589942 ps
T3704 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1303563600 Aug 13 05:13:11 PM PDT 24 Aug 13 05:13:11 PM PDT 24 42173180 ps
T3705 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2499437131 Aug 13 05:12:59 PM PDT 24 Aug 13 05:13:00 PM PDT 24 36081816 ps
T3706 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2367150849 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:22 PM PDT 24 493641318 ps
T3707 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2435673873 Aug 13 05:13:05 PM PDT 24 Aug 13 05:13:09 PM PDT 24 162111657 ps
T3708 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1057578954 Aug 13 05:13:19 PM PDT 24 Aug 13 05:13:20 PM PDT 24 59482263 ps
T3709 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2646620347 Aug 13 05:13:37 PM PDT 24 Aug 13 05:13:38 PM PDT 24 35769782 ps
T3710 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2657862961 Aug 13 05:13:24 PM PDT 24 Aug 13 05:13:25 PM PDT 24 100494855 ps
T3711 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.190568304 Aug 13 05:13:14 PM PDT 24 Aug 13 05:13:17 PM PDT 24 138797611 ps
T3712 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2819849046 Aug 13 05:12:58 PM PDT 24 Aug 13 05:12:59 PM PDT 24 73374701 ps
T3713 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4026041660 Aug 13 05:13:28 PM PDT 24 Aug 13 05:13:30 PM PDT 24 127070401 ps
T3714 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.411812947 Aug 13 05:13:17 PM PDT 24 Aug 13 05:13:18 PM PDT 24 36427307 ps
T3715 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2118766960 Aug 13 05:13:12 PM PDT 24 Aug 13 05:13:15 PM PDT 24 563628046 ps
T3716 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3858943796 Aug 13 05:13:21 PM PDT 24 Aug 13 05:13:23 PM PDT 24 94615959 ps
T3717 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3453173149 Aug 13 05:13:20 PM PDT 24 Aug 13 05:13:21 PM PDT 24 59471272 ps
T506 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.964954936 Aug 13 05:13:25 PM PDT 24 Aug 13 05:13:29 PM PDT 24 727988453 ps
T3718 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1231058573 Aug 13 05:13:12 PM PDT 24 Aug 13 05:13:14 PM PDT 24 270041886 ps
T3719 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2979675484 Aug 13 05:13:33 PM PDT 24 Aug 13 05:13:33 PM PDT 24 36706180 ps
T3720 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.396187182 Aug 13 05:13:14 PM PDT 24 Aug 13 05:13:15 PM PDT 24 96563836 ps
T3721 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1650499901 Aug 13 05:12:59 PM PDT 24 Aug 13 05:13:03 PM PDT 24 607558166 ps
T3722 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.588642927 Aug 13 05:13:14 PM PDT 24 Aug 13 05:13:15 PM PDT 24 50193682 ps
T3723 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3192354850 Aug 13 05:12:58 PM PDT 24 Aug 13 05:13:05 PM PDT 24 618839717 ps
T3724 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3315453490 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:19 PM PDT 24 65364443 ps
T3725 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2975832411 Aug 13 05:13:03 PM PDT 24 Aug 13 05:13:05 PM PDT 24 90763952 ps
T3726 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.528280706 Aug 13 05:13:17 PM PDT 24 Aug 13 05:13:19 PM PDT 24 61125788 ps
T3727 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4167109169 Aug 13 05:13:04 PM PDT 24 Aug 13 05:13:10 PM PDT 24 1668021779 ps
T3728 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3297594062 Aug 13 05:13:20 PM PDT 24 Aug 13 05:13:22 PM PDT 24 157588141 ps
T3729 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3170941198 Aug 13 05:13:36 PM PDT 24 Aug 13 05:13:37 PM PDT 24 51753078 ps
T3730 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1975329096 Aug 13 05:13:27 PM PDT 24 Aug 13 05:13:28 PM PDT 24 69008316 ps
T3731 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.207138755 Aug 13 05:13:16 PM PDT 24 Aug 13 05:13:18 PM PDT 24 76417076 ps
T3732 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.708040661 Aug 13 05:13:17 PM PDT 24 Aug 13 05:13:20 PM PDT 24 171796979 ps
T3733 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.471057339 Aug 13 05:13:25 PM PDT 24 Aug 13 05:13:26 PM PDT 24 88567354 ps
T3734 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2604286578 Aug 13 05:13:01 PM PDT 24 Aug 13 05:13:02 PM PDT 24 44675456 ps
T3735 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2116032433 Aug 13 05:13:35 PM PDT 24 Aug 13 05:13:36 PM PDT 24 49381492 ps
T3736 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3948945386 Aug 13 05:13:20 PM PDT 24 Aug 13 05:13:23 PM PDT 24 474993065 ps
T3737 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.345512320 Aug 13 05:13:05 PM PDT 24 Aug 13 05:13:05 PM PDT 24 29876636 ps
T3738 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.29751254 Aug 13 05:13:24 PM PDT 24 Aug 13 05:13:25 PM PDT 24 87918784 ps
T3739 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4245233929 Aug 13 05:13:18 PM PDT 24 Aug 13 05:13:19 PM PDT 24 104278694 ps
T3740 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1409869559 Aug 13 05:13:00 PM PDT 24 Aug 13 05:13:04 PM PDT 24 121629758 ps

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1886256971
Short name T1
Test name
Test status
Simulation time 3991832650 ps
CPU time 116.98 seconds
Started Aug 13 06:34:35 PM PDT 24
Finished Aug 13 06:36:32 PM PDT 24
Peak memory 218540 kb
Host smart-c8aaf65d-87d3-4e44-a915-e5fcadf1279e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1886256971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1886256971
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/62.usbdev_tx_rx_disruption.2768619594
Short name T18
Test name
Test status
Simulation time 620478560 ps
CPU time 1.71 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207540 kb
Host smart-ec39b8cb-ed51-448b-a9ad-349bdb784cb8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768619594 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.usbdev_tx_rx_disruption.2768619594
Directory /workspace/62.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.446491045
Short name T10
Test name
Test status
Simulation time 28400686798 ps
CPU time 39.67 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:36:24 PM PDT 24
Peak memory 207816 kb
Host smart-85118a71-bcef-44df-8df7-62edf450d188
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446491045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_ao
n_wake_resume.446491045
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_device_address.1790287977
Short name T56
Test name
Test status
Simulation time 39856631324 ps
CPU time 61.86 seconds
Started Aug 13 06:38:51 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 207724 kb
Host smart-a5c3808e-bd10-4cd0-9854-566120f29ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17902
87977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.1790287977
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4237390192
Short name T244
Test name
Test status
Simulation time 73697857 ps
CPU time 0.77 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:10 PM PDT 24
Peak memory 206828 kb
Host smart-5c111bf8-4cab-44cc-829e-f53f3c4d06a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4237390192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4237390192
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.313269186
Short name T235
Test name
Test status
Simulation time 901104961 ps
CPU time 5.19 seconds
Started Aug 13 05:13:19 PM PDT 24
Finished Aug 13 05:13:25 PM PDT 24
Peak memory 207292 kb
Host smart-d0ddf336-6a5c-4bd7-86ed-1fb111484c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=313269186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.313269186
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1621091739
Short name T12
Test name
Test status
Simulation time 10941373391 ps
CPU time 15.66 seconds
Started Aug 13 06:32:48 PM PDT 24
Finished Aug 13 06:33:04 PM PDT 24
Peak memory 207836 kb
Host smart-0d4a2c76-3aba-49e1-96da-bca16257fafe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621091739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.1621091739
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2837500080
Short name T90
Test name
Test status
Simulation time 14252967910 ps
CPU time 35.7 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:38:04 PM PDT 24
Peak memory 215988 kb
Host smart-985ec043-79ba-4663-bdea-c68eadf2f2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28375
00080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2837500080
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1718059391
Short name T101
Test name
Test status
Simulation time 6884974790 ps
CPU time 9.59 seconds
Started Aug 13 06:40:32 PM PDT 24
Finished Aug 13 06:40:41 PM PDT 24
Peak memory 216012 kb
Host smart-a143cb96-40a0-4ae4-8107-42af1614fd0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17180
59391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1718059391
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/124.usbdev_tx_rx_disruption.715134777
Short name T118
Test name
Test status
Simulation time 556891156 ps
CPU time 1.56 seconds
Started Aug 13 06:41:08 PM PDT 24
Finished Aug 13 06:41:10 PM PDT 24
Peak memory 207608 kb
Host smart-82156c0b-ab93-4468-9972-ca1526504db3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715134777 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 124.usbdev_tx_rx_disruption.715134777
Directory /workspace/124.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1473272691
Short name T259
Test name
Test status
Simulation time 308221756 ps
CPU time 1.14 seconds
Started Aug 13 06:33:00 PM PDT 24
Finished Aug 13 06:33:01 PM PDT 24
Peak memory 207512 kb
Host smart-242b0aba-82a4-44db-9d0a-095ca4eed633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14732
72691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1473272691
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.198057961
Short name T267
Test name
Test status
Simulation time 115524997 ps
CPU time 2.93 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 215536 kb
Host smart-14e0bd62-7e29-4e55-abb7-09eeb80f72fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=198057961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.198057961
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1626816243
Short name T246
Test name
Test status
Simulation time 446878443 ps
CPU time 1.32 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:11 PM PDT 24
Peak memory 223184 kb
Host smart-97e40e2a-42e1-4c91-aaaf-0b536644aa12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1626816243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1626816243
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2500712116
Short name T24
Test name
Test status
Simulation time 97548113 ps
CPU time 0.8 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 207544 kb
Host smart-56c1a82d-b7f3-423b-8907-abbecd5a90a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25007
12116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2500712116
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2389702858
Short name T349
Test name
Test status
Simulation time 61258916 ps
CPU time 0.76 seconds
Started Aug 13 05:13:27 PM PDT 24
Finished Aug 13 05:13:28 PM PDT 24
Peak memory 206852 kb
Host smart-14e4f25f-ad1e-4da7-a278-4d32870c0f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2389702858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2389702858
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.2747487282
Short name T51
Test name
Test status
Simulation time 534512745 ps
CPU time 1.61 seconds
Started Aug 13 06:36:02 PM PDT 24
Finished Aug 13 06:36:03 PM PDT 24
Peak memory 207416 kb
Host smart-0db230a8-ad94-4ab8-8246-590a33adbfff
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2747487282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.2747487282
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/206.usbdev_tx_rx_disruption.1484362254
Short name T186
Test name
Test status
Simulation time 508405751 ps
CPU time 1.5 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207608 kb
Host smart-862bfd43-03a8-48aa-9d63-46e900e31d75
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484362254 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.usbdev_tx_rx_disruption.1484362254
Directory /workspace/206.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3829182436
Short name T98
Test name
Test status
Simulation time 9853754966 ps
CPU time 12.69 seconds
Started Aug 13 06:39:00 PM PDT 24
Finished Aug 13 06:39:12 PM PDT 24
Peak memory 207848 kb
Host smart-8324744c-ca0a-4515-b6ac-e3834e6b753c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829182436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.3829182436
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/484.usbdev_tx_rx_disruption.1119707055
Short name T260
Test name
Test status
Simulation time 484219485 ps
CPU time 1.54 seconds
Started Aug 13 06:42:31 PM PDT 24
Finished Aug 13 06:42:33 PM PDT 24
Peak memory 207608 kb
Host smart-0a520772-cafc-4ce4-beea-dac401ae8543
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119707055 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 484.usbdev_tx_rx_disruption.1119707055
Directory /workspace/484.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.994323084
Short name T3214
Test name
Test status
Simulation time 4720048909 ps
CPU time 6.59 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:16 PM PDT 24
Peak memory 215924 kb
Host smart-09bc1012-38a1-4089-b4ff-163fa1110a6c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994323084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_ao
n_wake_disconnect.994323084
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/268.usbdev_tx_rx_disruption.494669220
Short name T263
Test name
Test status
Simulation time 508416389 ps
CPU time 1.58 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207592 kb
Host smart-94d2d5b9-ff7f-47f8-87e6-6832ee8b400e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494669220 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 268.usbdev_tx_rx_disruption.494669220
Directory /workspace/268.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2666855816
Short name T181
Test name
Test status
Simulation time 22473769180 ps
CPU time 40.8 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:37:17 PM PDT 24
Peak memory 207772 kb
Host smart-9b9aad17-771e-4dbf-8549-49976dba1960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26668
55816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2666855816
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_rx_full.2728313614
Short name T15
Test name
Test status
Simulation time 253705623 ps
CPU time 1.22 seconds
Started Aug 13 06:38:49 PM PDT 24
Finished Aug 13 06:38:51 PM PDT 24
Peak memory 207420 kb
Host smart-d23b7d2a-73f6-483f-a8d5-94f3dd3d38be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27283
13614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.2728313614
Directory /workspace/34.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2604402114
Short name T306
Test name
Test status
Simulation time 177621509 ps
CPU time 2.26 seconds
Started Aug 13 05:12:57 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 215428 kb
Host smart-e58b7082-284c-4aee-8622-46ad90f7e108
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2604402114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2604402114
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.4002713571
Short name T66
Test name
Test status
Simulation time 145195283 ps
CPU time 0.86 seconds
Started Aug 13 06:36:07 PM PDT 24
Finished Aug 13 06:36:08 PM PDT 24
Peak memory 207612 kb
Host smart-c09874f3-430d-4b82-838f-73073399ad35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40027
13571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.4002713571
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1843335375
Short name T351
Test name
Test status
Simulation time 53158068 ps
CPU time 0.81 seconds
Started Aug 13 05:13:19 PM PDT 24
Finished Aug 13 05:13:19 PM PDT 24
Peak memory 206900 kb
Host smart-4aac579b-de01-4355-9981-d60117e5cf71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1843335375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1843335375
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/100.usbdev_endpoint_types.379354064
Short name T421
Test name
Test status
Simulation time 902158430 ps
CPU time 2.04 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207572 kb
Host smart-d47a35fb-24d7-4359-9003-32e29ec8162b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=379354064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.379354064
Directory /workspace/100.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3113498181
Short name T227
Test name
Test status
Simulation time 19013446546 ps
CPU time 23.6 seconds
Started Aug 13 06:38:54 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207864 kb
Host smart-99e984a3-7531-41d4-92a9-e85a31bc1d49
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113498181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3113498181
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_types.4098116994
Short name T404
Test name
Test status
Simulation time 540466701 ps
CPU time 1.49 seconds
Started Aug 13 06:38:57 PM PDT 24
Finished Aug 13 06:38:59 PM PDT 24
Peak memory 207552 kb
Host smart-30aeeb37-ea8e-4278-9470-b0f4dc0f5708
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4098116994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.4098116994
Directory /workspace/35.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_types.1635055160
Short name T366
Test name
Test status
Simulation time 805445769 ps
CPU time 1.81 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207560 kb
Host smart-4b0e8ba8-135c-403f-924f-fcde9cc53e04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1635055160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.1635055160
Directory /workspace/25.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.4165587331
Short name T68
Test name
Test status
Simulation time 132927817 ps
CPU time 0.87 seconds
Started Aug 13 06:35:43 PM PDT 24
Finished Aug 13 06:35:44 PM PDT 24
Peak memory 207496 kb
Host smart-6042f658-b1dc-42c0-a56c-193f3f1e117f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41655
87331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.4165587331
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/119.usbdev_endpoint_types.1217827888
Short name T414
Test name
Test status
Simulation time 611062923 ps
CPU time 1.5 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207572 kb
Host smart-c9f4e062-6378-4190-a19d-b1984a4b7ff8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1217827888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.1217827888
Directory /workspace/119.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/145.usbdev_endpoint_types.2539487582
Short name T382
Test name
Test status
Simulation time 808800602 ps
CPU time 1.82 seconds
Started Aug 13 06:41:28 PM PDT 24
Finished Aug 13 06:41:30 PM PDT 24
Peak memory 207560 kb
Host smart-fe67b70e-0c31-4a9b-a1c7-95f3f7afe8de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2539487582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.2539487582
Directory /workspace/145.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1426266891
Short name T1046
Test name
Test status
Simulation time 139908037 ps
CPU time 0.88 seconds
Started Aug 13 06:36:00 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 207532 kb
Host smart-c22eea0a-fe47-42cd-aeb4-da6d03179b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14262
66891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1426266891
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/113.usbdev_endpoint_types.3498219788
Short name T2976
Test name
Test status
Simulation time 768706690 ps
CPU time 1.65 seconds
Started Aug 13 06:41:08 PM PDT 24
Finished Aug 13 06:41:10 PM PDT 24
Peak memory 207568 kb
Host smart-1feb21b0-9c52-492e-8c92-8147840e2902
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3498219788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.3498219788
Directory /workspace/113.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/62.usbdev_endpoint_types.2132665031
Short name T377
Test name
Test status
Simulation time 373846191 ps
CPU time 1.37 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207432 kb
Host smart-bffcc57d-545e-42d3-9233-b504cca43f3e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2132665031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.2132665031
Directory /workspace/62.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2310867286
Short name T927
Test name
Test status
Simulation time 29183571215 ps
CPU time 46.8 seconds
Started Aug 13 06:33:14 PM PDT 24
Finished Aug 13 06:34:01 PM PDT 24
Peak memory 216032 kb
Host smart-3a81a508-f785-4f4a-9b1e-a8d631c4454b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23108
67286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2310867286
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/104.usbdev_endpoint_types.2241062281
Short name T419
Test name
Test status
Simulation time 486998928 ps
CPU time 1.34 seconds
Started Aug 13 06:41:09 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207580 kb
Host smart-a4ad8305-fe42-45f8-b929-12b2ae1435e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2241062281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.2241062281
Directory /workspace/104.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1611412042
Short name T340
Test name
Test status
Simulation time 1176529831 ps
CPU time 2.98 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:37:14 PM PDT 24
Peak memory 207588 kb
Host smart-dd533904-75a7-4f54-9611-9430d99e1891
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1611412042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1611412042
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/66.usbdev_endpoint_types.1490745992
Short name T400
Test name
Test status
Simulation time 556134317 ps
CPU time 1.57 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 206880 kb
Host smart-0fccb705-bf6c-4cba-9ca9-6dcdceb7ee26
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1490745992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.1490745992
Directory /workspace/66.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/20.usbdev_device_address.4197165020
Short name T111
Test name
Test status
Simulation time 22383306233 ps
CPU time 40.18 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:37:18 PM PDT 24
Peak memory 207852 kb
Host smart-f185afaf-8cfc-48f1-81df-6eaa3a31dc7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41971
65020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.4197165020
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/75.usbdev_endpoint_types.1984981390
Short name T384
Test name
Test status
Simulation time 635858179 ps
CPU time 1.58 seconds
Started Aug 13 06:41:23 PM PDT 24
Finished Aug 13 06:41:25 PM PDT 24
Peak memory 207564 kb
Host smart-8a11ebc5-17b8-41be-807a-9d82c3a415e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1984981390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.1984981390
Directory /workspace/75.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/186.usbdev_tx_rx_disruption.4143125594
Short name T72
Test name
Test status
Simulation time 599458963 ps
CPU time 1.63 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207580 kb
Host smart-9f9f917c-2e1f-4382-8e0d-9dd9806d600f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143125594 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 186.usbdev_tx_rx_disruption.4143125594
Directory /workspace/186.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.809135063
Short name T505
Test name
Test status
Simulation time 372347649 ps
CPU time 2.41 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:21 PM PDT 24
Peak memory 207280 kb
Host smart-11970295-9dc3-481b-90a7-5271e3fa2ab8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=809135063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.809135063
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_types.3484748063
Short name T442
Test name
Test status
Simulation time 447701085 ps
CPU time 1.38 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207560 kb
Host smart-45fcedc9-43f1-4141-a8c0-ad5915ba0fb7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3484748063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.3484748063
Directory /workspace/31.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/91.usbdev_endpoint_types.2719631272
Short name T432
Test name
Test status
Simulation time 655590226 ps
CPU time 1.65 seconds
Started Aug 13 06:41:06 PM PDT 24
Finished Aug 13 06:41:08 PM PDT 24
Peak memory 207480 kb
Host smart-fe483fdd-589a-4dbc-97c3-05682a974ef7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2719631272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.2719631272
Directory /workspace/91.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/164.usbdev_endpoint_types.2234585198
Short name T2
Test name
Test status
Simulation time 441177845 ps
CPU time 1.37 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:48 PM PDT 24
Peak memory 207500 kb
Host smart-afb91386-5b6e-44b5-851c-6f477d4a7cc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2234585198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.2234585198
Directory /workspace/164.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1367603562
Short name T3195
Test name
Test status
Simulation time 351577376 ps
CPU time 1.42 seconds
Started Aug 13 06:32:59 PM PDT 24
Finished Aug 13 06:33:01 PM PDT 24
Peak memory 207572 kb
Host smart-115ed5c2-9719-49c5-b266-453539878743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13676
03562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1367603562
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_types.3546452915
Short name T425
Test name
Test status
Simulation time 470195652 ps
CPU time 1.46 seconds
Started Aug 13 06:35:03 PM PDT 24
Finished Aug 13 06:35:05 PM PDT 24
Peak memory 207560 kb
Host smart-3dc426ca-9887-4d58-9459-836ad64d9a4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3546452915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.3546452915
Directory /workspace/10.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/102.usbdev_endpoint_types.732819385
Short name T3506
Test name
Test status
Simulation time 625363266 ps
CPU time 1.6 seconds
Started Aug 13 06:41:10 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207576 kb
Host smart-73d7b783-932e-4655-8642-3bde0334f5b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=732819385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.732819385
Directory /workspace/102.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_types.1774539817
Short name T383
Test name
Test status
Simulation time 658994341 ps
CPU time 1.67 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207568 kb
Host smart-756c2b6a-356b-40db-9bb7-4c3ca78d8118
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1774539817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.1774539817
Directory /workspace/20.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/26.usbdev_device_address.4093609989
Short name T112
Test name
Test status
Simulation time 22600056273 ps
CPU time 38.6 seconds
Started Aug 13 06:37:44 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207724 kb
Host smart-dbf5fc47-90df-483e-a452-ab126a681975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40936
09989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.4093609989
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3486725708
Short name T224
Test name
Test status
Simulation time 44488158 ps
CPU time 0.71 seconds
Started Aug 13 06:33:21 PM PDT 24
Finished Aug 13 06:33:22 PM PDT 24
Peak memory 207476 kb
Host smart-bf0ef304-4740-4b1e-b24f-55f3637bcdf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3486725708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3486725708
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.4276701018
Short name T173
Test name
Test status
Simulation time 3100347950 ps
CPU time 27.88 seconds
Started Aug 13 06:34:26 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 224160 kb
Host smart-f9595aaf-9166-4779-83a6-e52a065e8ccd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4276701018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.4276701018
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3667545855
Short name T623
Test name
Test status
Simulation time 177242012 ps
CPU time 0.99 seconds
Started Aug 13 06:32:57 PM PDT 24
Finished Aug 13 06:32:58 PM PDT 24
Peak memory 207500 kb
Host smart-166f9792-531f-4674-b649-b6a872825a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36675
45855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3667545855
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/106.usbdev_endpoint_types.203684403
Short name T378
Test name
Test status
Simulation time 706574708 ps
CPU time 1.69 seconds
Started Aug 13 06:41:06 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207528 kb
Host smart-f1b56358-f233-4166-b7b7-1444c9835cde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=203684403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.203684403
Directory /workspace/106.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/107.usbdev_endpoint_types.3260055844
Short name T370
Test name
Test status
Simulation time 816895291 ps
CPU time 1.88 seconds
Started Aug 13 06:41:09 PM PDT 24
Finished Aug 13 06:41:10 PM PDT 24
Peak memory 207520 kb
Host smart-66e6426b-6c04-4db1-8ac2-f8f615c6a2a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3260055844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.3260055844
Directory /workspace/107.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/112.usbdev_endpoint_types.1501842582
Short name T460
Test name
Test status
Simulation time 447472895 ps
CPU time 1.45 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207528 kb
Host smart-3e9401f8-c79b-4711-a079-70d3b1d57abf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1501842582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.1501842582
Directory /workspace/112.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.1902720886
Short name T526
Test name
Test status
Simulation time 3544535599 ps
CPU time 108.69 seconds
Started Aug 13 06:35:56 PM PDT 24
Finished Aug 13 06:37:45 PM PDT 24
Peak memory 215960 kb
Host smart-5a894ed1-ee39-45f5-ac28-48418429727e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1902720886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1902720886
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1623588784
Short name T2010
Test name
Test status
Simulation time 1218126605 ps
CPU time 3.15 seconds
Started Aug 13 06:38:19 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207588 kb
Host smart-5d3135ff-849f-4e5a-86e8-0c7bf9a49ade
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1623588784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1623588784
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_types.1024215527
Short name T429
Test name
Test status
Simulation time 481908157 ps
CPU time 1.33 seconds
Started Aug 13 06:40:22 PM PDT 24
Finished Aug 13 06:40:23 PM PDT 24
Peak memory 207548 kb
Host smart-89101f40-7c00-4970-bc0a-b19329266f80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1024215527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.1024215527
Directory /workspace/46.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/59.usbdev_endpoint_types.601267221
Short name T410
Test name
Test status
Simulation time 561836878 ps
CPU time 1.4 seconds
Started Aug 13 06:41:34 PM PDT 24
Finished Aug 13 06:41:36 PM PDT 24
Peak memory 207580 kb
Host smart-c3a63f30-ae62-48f9-9659-4eb84286607b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=601267221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.601267221
Directory /workspace/59.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2561710056
Short name T134
Test name
Test status
Simulation time 214288907 ps
CPU time 0.95 seconds
Started Aug 13 06:35:09 PM PDT 24
Finished Aug 13 06:35:10 PM PDT 24
Peak memory 207460 kb
Host smart-f7b05079-2911-41fb-a812-86a2a498e765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25617
10056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2561710056
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2670070375
Short name T163
Test name
Test status
Simulation time 5592582324 ps
CPU time 165.61 seconds
Started Aug 13 06:38:33 PM PDT 24
Finished Aug 13 06:41:19 PM PDT 24
Peak memory 216056 kb
Host smart-8ac48edd-6c17-4128-936b-b985f1c7048a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2670070375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2670070375
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4168941134
Short name T320
Test name
Test status
Simulation time 75929349 ps
CPU time 0.98 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:00 PM PDT 24
Peak memory 206956 kb
Host smart-e66d2677-bf66-4945-a5a3-be13dbf9b082
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4168941134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.4168941134
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.2457929022
Short name T54
Test name
Test status
Simulation time 149733025 ps
CPU time 0.85 seconds
Started Aug 13 06:32:52 PM PDT 24
Finished Aug 13 06:32:53 PM PDT 24
Peak memory 207492 kb
Host smart-253b8ecf-a411-437b-9b3a-18e28c4a3805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24579
29022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.2457929022
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.748914872
Short name T511
Test name
Test status
Simulation time 755528534 ps
CPU time 4.5 seconds
Started Aug 13 05:13:00 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 207176 kb
Host smart-fcd0b773-068a-456c-9fa8-dddb828abad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=748914872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.748914872
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3394571897
Short name T352
Test name
Test status
Simulation time 35653707 ps
CPU time 0.75 seconds
Started Aug 13 05:13:21 PM PDT 24
Finished Aug 13 05:13:21 PM PDT 24
Peak memory 206944 kb
Host smart-c960b103-32b4-4619-b258-7c3f73732370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3394571897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3394571897
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3300253284
Short name T531
Test name
Test status
Simulation time 115155332490 ps
CPU time 180.15 seconds
Started Aug 13 06:32:59 PM PDT 24
Finished Aug 13 06:36:00 PM PDT 24
Peak memory 207736 kb
Host smart-d9791d50-ee24-4cf8-ba8e-c10728ecad74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33002
53284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3300253284
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_types.3019841075
Short name T363
Test name
Test status
Simulation time 588052552 ps
CPU time 1.39 seconds
Started Aug 13 06:33:06 PM PDT 24
Finished Aug 13 06:33:07 PM PDT 24
Peak memory 207456 kb
Host smart-4750bfef-6c6b-46bf-a605-d278ad33e233
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3019841075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.3019841075
Directory /workspace/1.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_types.4109993714
Short name T490
Test name
Test status
Simulation time 436373740 ps
CPU time 1.25 seconds
Started Aug 13 06:35:32 PM PDT 24
Finished Aug 13 06:35:34 PM PDT 24
Peak memory 207496 kb
Host smart-83d498b1-e98c-4eba-9eca-ad959e9766ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4109993714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.4109993714
Directory /workspace/13.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/136.usbdev_endpoint_types.410102847
Short name T424
Test name
Test status
Simulation time 667588226 ps
CPU time 1.58 seconds
Started Aug 13 06:41:36 PM PDT 24
Finished Aug 13 06:41:37 PM PDT 24
Peak memory 207456 kb
Host smart-3e9394be-7996-4ab1-aa62-bb18d4211a43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=410102847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.410102847
Directory /workspace/136.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_types.2257074056
Short name T462
Test name
Test status
Simulation time 328428251 ps
CPU time 1.17 seconds
Started Aug 13 06:36:01 PM PDT 24
Finished Aug 13 06:36:02 PM PDT 24
Peak memory 207580 kb
Host smart-663899ea-58c5-47a1-be14-c28addfe432d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2257074056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.2257074056
Directory /workspace/16.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/174.usbdev_endpoint_types.89644870
Short name T412
Test name
Test status
Simulation time 848456679 ps
CPU time 1.88 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207560 kb
Host smart-c159ff46-65d8-4a5d-a7a7-85ee5e77ecc1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=89644870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.89644870
Directory /workspace/174.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/25.usbdev_rx_full.3539002817
Short name T326
Test name
Test status
Simulation time 270692155 ps
CPU time 1.11 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207508 kb
Host smart-5323b5d6-60fa-488e-9b03-411b1c43ebfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35390
02817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.3539002817
Directory /workspace/25.usbdev_rx_full/latest

Test location /workspace/coverage/default/58.usbdev_endpoint_types.4250957632
Short name T454
Test name
Test status
Simulation time 282139424 ps
CPU time 1.07 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207564 kb
Host smart-1523ab27-34eb-41ab-868d-c9785569460e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4250957632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.4250957632
Directory /workspace/58.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/155.usbdev_tx_rx_disruption.1449673274
Short name T172
Test name
Test status
Simulation time 674200866 ps
CPU time 1.83 seconds
Started Aug 13 06:41:59 PM PDT 24
Finished Aug 13 06:42:01 PM PDT 24
Peak memory 207624 kb
Host smart-234f7d90-89f1-4eed-a19c-036495b9e170
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449673274 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.usbdev_tx_rx_disruption.1449673274
Directory /workspace/155.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3214195914
Short name T278
Test name
Test status
Simulation time 100544001 ps
CPU time 2.97 seconds
Started Aug 13 05:13:26 PM PDT 24
Finished Aug 13 05:13:29 PM PDT 24
Peak memory 223532 kb
Host smart-699d4127-c8df-4aab-8b2b-2bd2192593a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3214195914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3214195914
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1944039734
Short name T184
Test name
Test status
Simulation time 10986367823 ps
CPU time 216.98 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:37:23 PM PDT 24
Peak memory 218368 kb
Host smart-738a9cae-d44a-42e6-af41-3acee69f343a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944039734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1944039734
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.589920709
Short name T388
Test name
Test status
Simulation time 3690056622 ps
CPU time 104.74 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 218588 kb
Host smart-34176808-5eb4-4d85-92c3-17967fddbca6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=589920709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.589920709
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1776787656
Short name T106
Test name
Test status
Simulation time 11828039925 ps
CPU time 234.53 seconds
Started Aug 13 06:33:24 PM PDT 24
Finished Aug 13 06:37:19 PM PDT 24
Peak memory 218352 kb
Host smart-f3ed0378-7fe1-429a-8749-559edb7c64b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776787656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1776787656
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2267329130
Short name T37
Test name
Test status
Simulation time 9730675798 ps
CPU time 11.79 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:31 PM PDT 24
Peak memory 207760 kb
Host smart-104646d6-2065-4c15-831d-8ddb4a26d4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22673
29130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2267329130
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.369717195
Short name T197
Test name
Test status
Simulation time 7429387213 ps
CPU time 35.48 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:34:53 PM PDT 24
Peak memory 223708 kb
Host smart-eefec083-10d5-4b73-b82a-c5858f8aae9c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=369717195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.369717195
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2501097750
Short name T509
Test name
Test status
Simulation time 717462761 ps
CPU time 2.94 seconds
Started Aug 13 05:13:13 PM PDT 24
Finished Aug 13 05:13:16 PM PDT 24
Peak memory 207308 kb
Host smart-820f436e-a5d7-432a-a844-d576205af06b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2501097750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2501097750
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3975208069
Short name T534
Test name
Test status
Simulation time 5111151214 ps
CPU time 39.12 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:33:30 PM PDT 24
Peak memory 207832 kb
Host smart-507dbd03-e228-41e2-9a24-079402547cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39752
08069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3975208069
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2948973969
Short name T536
Test name
Test status
Simulation time 94178706515 ps
CPU time 146.61 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:35:16 PM PDT 24
Peak memory 207760 kb
Host smart-9d0b7615-670e-43f9-9740-5509d67a65e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948973969 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2948973969
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1461240363
Short name T3085
Test name
Test status
Simulation time 1977198153 ps
CPU time 55.76 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 215940 kb
Host smart-912a7201-f717-46e7-bd4c-7bf59b606c2c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1461240363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1461240363
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_rx_full.3870546275
Short name T332
Test name
Test status
Simulation time 282255284 ps
CPU time 1.14 seconds
Started Aug 13 06:33:24 PM PDT 24
Finished Aug 13 06:33:25 PM PDT 24
Peak memory 207540 kb
Host smart-3d60af33-e9ed-4b45-9306-fcdaf218fb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38705
46275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.3870546275
Directory /workspace/1.usbdev_rx_full/latest

Test location /workspace/coverage/default/109.usbdev_endpoint_types.422551413
Short name T3579
Test name
Test status
Simulation time 580701788 ps
CPU time 1.71 seconds
Started Aug 13 06:41:28 PM PDT 24
Finished Aug 13 06:41:32 PM PDT 24
Peak memory 207564 kb
Host smart-375443ec-5841-44ab-ae54-a57389a82da3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=422551413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.422551413
Directory /workspace/109.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/118.usbdev_endpoint_types.3212303739
Short name T465
Test name
Test status
Simulation time 203311509 ps
CPU time 0.89 seconds
Started Aug 13 06:41:07 PM PDT 24
Finished Aug 13 06:41:08 PM PDT 24
Peak memory 207508 kb
Host smart-06a1a9c2-e78a-436f-a545-bc1a00ac531f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3212303739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.3212303739
Directory /workspace/118.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/121.usbdev_endpoint_types.1104681022
Short name T3508
Test name
Test status
Simulation time 403021570 ps
CPU time 1.23 seconds
Started Aug 13 06:41:11 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 207564 kb
Host smart-c0ac2d66-c9a8-49c1-a857-91f6b13e136b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1104681022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.1104681022
Directory /workspace/121.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/123.usbdev_endpoint_types.4076342204
Short name T431
Test name
Test status
Simulation time 266284706 ps
CPU time 1.03 seconds
Started Aug 13 06:41:16 PM PDT 24
Finished Aug 13 06:41:17 PM PDT 24
Peak memory 207580 kb
Host smart-3a861b74-ac15-431d-9cf0-61171c82d3de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4076342204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.4076342204
Directory /workspace/123.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/126.usbdev_endpoint_types.544273397
Short name T369
Test name
Test status
Simulation time 972712712 ps
CPU time 1.99 seconds
Started Aug 13 06:41:29 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 207572 kb
Host smart-ce4a57c4-2982-4f67-bd0b-16c51b3011ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=544273397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.544273397
Directory /workspace/126.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/138.usbdev_endpoint_types.3008167132
Short name T368
Test name
Test status
Simulation time 609303337 ps
CPU time 1.55 seconds
Started Aug 13 06:41:31 PM PDT 24
Finished Aug 13 06:41:33 PM PDT 24
Peak memory 207524 kb
Host smart-4705c0a8-c7bc-4a2b-a344-c741936eedad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3008167132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.3008167132
Directory /workspace/138.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/147.usbdev_endpoint_types.386476215
Short name T364
Test name
Test status
Simulation time 364640501 ps
CPU time 1.29 seconds
Started Aug 13 06:41:44 PM PDT 24
Finished Aug 13 06:41:45 PM PDT 24
Peak memory 207488 kb
Host smart-5c200151-2599-4b66-869f-c5b1b64ae950
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=386476215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.386476215
Directory /workspace/147.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_rx_full.3013900526
Short name T333
Test name
Test status
Simulation time 349987976 ps
CPU time 1.24 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 207420 kb
Host smart-85027308-e930-45d7-9e74-54ea71b3cf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30139
00526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.3013900526
Directory /workspace/15.usbdev_rx_full/latest

Test location /workspace/coverage/default/170.usbdev_endpoint_types.1425772519
Short name T386
Test name
Test status
Simulation time 356917543 ps
CPU time 1.14 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:46 PM PDT 24
Peak memory 207496 kb
Host smart-6cd785be-f392-4acd-90aa-93a4757bd6fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1425772519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.1425772519
Directory /workspace/170.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_types.936733608
Short name T471
Test name
Test status
Simulation time 502476053 ps
CPU time 1.39 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207504 kb
Host smart-573305b7-3a72-4fdb-8a81-34fc5f6d0913
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=936733608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.936733608
Directory /workspace/18.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/189.usbdev_endpoint_types.3623872152
Short name T420
Test name
Test status
Simulation time 685941678 ps
CPU time 1.56 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207568 kb
Host smart-384d9d1b-4481-4ab1-bb54-000c241024e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3623872152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.3623872152
Directory /workspace/189.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_types.2359334167
Short name T397
Test name
Test status
Simulation time 647129070 ps
CPU time 1.8 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:02 PM PDT 24
Peak memory 207516 kb
Host smart-91e67023-d498-4153-ac9c-2760280fb789
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2359334167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.2359334167
Directory /workspace/29.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_types.1294144319
Short name T390
Test name
Test status
Simulation time 476348267 ps
CPU time 1.38 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207564 kb
Host smart-d47e8128-848e-4ce5-84bc-8056e7cb0d36
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1294144319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.1294144319
Directory /workspace/45.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_types.3247978372
Short name T464
Test name
Test status
Simulation time 280082534 ps
CPU time 1.11 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:40:42 PM PDT 24
Peak memory 207552 kb
Host smart-df3001ea-a85a-4a5f-90a7-5668ecdbe525
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3247978372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.3247978372
Directory /workspace/47.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/87.usbdev_endpoint_types.1446874442
Short name T402
Test name
Test status
Simulation time 502836243 ps
CPU time 1.35 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207584 kb
Host smart-be5a5488-eb66-4355-9ee8-24152b3c39be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1446874442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.1446874442
Directory /workspace/87.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.975308197
Short name T884
Test name
Test status
Simulation time 174730711 ps
CPU time 0.84 seconds
Started Aug 13 06:33:14 PM PDT 24
Finished Aug 13 06:33:14 PM PDT 24
Peak memory 207452 kb
Host smart-72b617ea-7cda-4c26-896c-cf429a926d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97530
8197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.975308197
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/101.usbdev_tx_rx_disruption.3709151511
Short name T218
Test name
Test status
Simulation time 472401324 ps
CPU time 1.5 seconds
Started Aug 13 06:41:13 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207632 kb
Host smart-4eda3c75-7232-4a25-a3d3-e75df78318a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709151511 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.usbdev_tx_rx_disruption.3709151511
Directory /workspace/101.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.1219805883
Short name T53
Test name
Test status
Simulation time 137080230 ps
CPU time 0.81 seconds
Started Aug 13 06:33:09 PM PDT 24
Finished Aug 13 06:33:09 PM PDT 24
Peak memory 207496 kb
Host smart-f6e530a0-1617-4b14-9127-ecca38ae900e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12198
05883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.1219805883
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3615075358
Short name T165
Test name
Test status
Simulation time 3175094754 ps
CPU time 33.49 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:44 PM PDT 24
Peak memory 224096 kb
Host smart-5eef92ba-4458-4267-bd8c-03e978a62e99
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3615075358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3615075358
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1347795182
Short name T1128
Test name
Test status
Simulation time 43213949 ps
CPU time 0.69 seconds
Started Aug 13 06:37:26 PM PDT 24
Finished Aug 13 06:37:27 PM PDT 24
Peak memory 207536 kb
Host smart-d3f24014-977f-4cb1-95f2-43baaf9b0eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13477
95182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1347795182
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.2614388663
Short name T2676
Test name
Test status
Simulation time 200424712 ps
CPU time 0.91 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:32:52 PM PDT 24
Peak memory 207536 kb
Host smart-16a1e2c0-6f7d-46a1-9836-6f01a4ce1d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26143
88663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.2614388663
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.897511428
Short name T58
Test name
Test status
Simulation time 4155266219 ps
CPU time 11.08 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:33:02 PM PDT 24
Peak memory 207832 kb
Host smart-ce3f3296-a143-4582-913e-56fb57110cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89751
1428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.897511428
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.344916765
Short name T64
Test name
Test status
Simulation time 425913625 ps
CPU time 1.41 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:32:53 PM PDT 24
Peak memory 207460 kb
Host smart-9d5bea17-b48a-470f-93ae-e8db56194143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491
6765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.344916765
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1427502180
Short name T59
Test name
Test status
Simulation time 210724830 ps
CPU time 0.98 seconds
Started Aug 13 06:32:52 PM PDT 24
Finished Aug 13 06:32:53 PM PDT 24
Peak memory 207468 kb
Host smart-4e260873-0785-4e46-ba68-f8d384a54747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14275
02180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1427502180
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3280240531
Short name T2447
Test name
Test status
Simulation time 159885876 ps
CPU time 0.86 seconds
Started Aug 13 06:32:59 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 207444 kb
Host smart-6bc95a01-6208-4fc5-8fa1-5275ebd6d502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32802
40531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3280240531
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1598915244
Short name T213
Test name
Test status
Simulation time 3783556204 ps
CPU time 114.49 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:40:15 PM PDT 24
Peak memory 217916 kb
Host smart-326a17d9-491b-434b-9180-9a754aa7c709
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1598915244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1598915244
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.5078233
Short name T3691
Test name
Test status
Simulation time 131309499 ps
CPU time 2.09 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:00 PM PDT 24
Peak memory 207212 kb
Host smart-9c6a02e4-e945-475b-aa10-b95df87d3f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=5078233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.5078233
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3859126846
Short name T149
Test name
Test status
Simulation time 202406305 ps
CPU time 0.9 seconds
Started Aug 13 06:32:56 PM PDT 24
Finished Aug 13 06:32:57 PM PDT 24
Peak memory 206368 kb
Host smart-0eef27c1-18ab-44c8-a187-f938b1a0407b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38591
26846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3859126846
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1496187158
Short name T657
Test name
Test status
Simulation time 343905480 ps
CPU time 2.54 seconds
Started Aug 13 06:33:09 PM PDT 24
Finished Aug 13 06:33:12 PM PDT 24
Peak memory 207696 kb
Host smart-155fbfaf-7303-45af-8eac-356ab3fd200b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14961
87158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1496187158
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2787277487
Short name T127
Test name
Test status
Simulation time 192080928 ps
CPU time 0.98 seconds
Started Aug 13 06:33:15 PM PDT 24
Finished Aug 13 06:33:16 PM PDT 24
Peak memory 207476 kb
Host smart-139e90a5-844d-4275-84e4-79a260d54470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27872
77487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2787277487
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1243825039
Short name T2966
Test name
Test status
Simulation time 196646138 ps
CPU time 0.88 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 207544 kb
Host smart-13c26bf2-2876-4788-9b3b-d3f34876aa59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12438
25039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1243825039
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1510440472
Short name T3146
Test name
Test status
Simulation time 198318681 ps
CPU time 0.89 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:21 PM PDT 24
Peak memory 207452 kb
Host smart-fa6d505a-0471-4790-bb59-86addfb32c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15104
40472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1510440472
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/126.usbdev_tx_rx_disruption.3367723794
Short name T178
Test name
Test status
Simulation time 481065311 ps
CPU time 1.55 seconds
Started Aug 13 06:41:12 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207552 kb
Host smart-9f405bc6-2427-4b4b-aaa3-17cbf90e012a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367723794 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.usbdev_tx_rx_disruption.3367723794
Directory /workspace/126.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2466265062
Short name T131
Test name
Test status
Simulation time 211456411 ps
CPU time 0.98 seconds
Started Aug 13 06:35:47 PM PDT 24
Finished Aug 13 06:35:48 PM PDT 24
Peak memory 207460 kb
Host smart-a50b2e10-c898-4435-a6f0-0cb76c4f44d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24662
65062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2466265062
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2342016360
Short name T148
Test name
Test status
Simulation time 203346338 ps
CPU time 0.95 seconds
Started Aug 13 06:36:13 PM PDT 24
Finished Aug 13 06:36:14 PM PDT 24
Peak memory 207524 kb
Host smart-2e2224f3-7d12-4d17-97bd-da699ab31c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23420
16360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2342016360
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.759069060
Short name T80
Test name
Test status
Simulation time 8472288597 ps
CPU time 58.31 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 224156 kb
Host smart-99efbe9f-c79f-4198-83cd-14367eb1a498
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759069060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.759069060
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1787968127
Short name T145
Test name
Test status
Simulation time 192503109 ps
CPU time 0.95 seconds
Started Aug 13 06:37:03 PM PDT 24
Finished Aug 13 06:37:04 PM PDT 24
Peak memory 207452 kb
Host smart-fb1a9c6a-84be-4745-a196-53b50aa553ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17879
68127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1787968127
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.13533987
Short name T140
Test name
Test status
Simulation time 208919740 ps
CPU time 0.95 seconds
Started Aug 13 06:36:53 PM PDT 24
Finished Aug 13 06:36:54 PM PDT 24
Peak memory 207524 kb
Host smart-572068b6-0625-42ec-b345-8382d91bebe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13533
987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.13533987
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_tx_rx_disruption.2861608673
Short name T115
Test name
Test status
Simulation time 637463264 ps
CPU time 1.77 seconds
Started Aug 13 06:36:57 PM PDT 24
Finished Aug 13 06:36:59 PM PDT 24
Peak memory 207592 kb
Host smart-237b8763-4527-4f75-9a15-1bfb4cb9feb9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861608673 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.usbdev_tx_rx_disruption.2861608673
Directory /workspace/22.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2376891225
Short name T3456
Test name
Test status
Simulation time 174826453 ps
CPU time 0.89 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207472 kb
Host smart-2e188b17-c728-4eea-954b-6f2b1084c575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23768
91225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2376891225
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1776037844
Short name T142
Test name
Test status
Simulation time 224629540 ps
CPU time 0.93 seconds
Started Aug 13 06:37:36 PM PDT 24
Finished Aug 13 06:37:37 PM PDT 24
Peak memory 207420 kb
Host smart-a25ece52-df64-4217-8203-acc3eb59f945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17760
37844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1776037844
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.411473383
Short name T137
Test name
Test status
Simulation time 191758290 ps
CPU time 0.93 seconds
Started Aug 13 06:37:37 PM PDT 24
Finished Aug 13 06:37:38 PM PDT 24
Peak memory 207452 kb
Host smart-a1e81adb-c7be-4075-9f1d-866da01fc9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41147
3383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.411473383
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1409869559
Short name T3740
Test name
Test status
Simulation time 121629758 ps
CPU time 3.29 seconds
Started Aug 13 05:13:00 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 207188 kb
Host smart-f54706f9-e502-45b3-a357-2d5c3c171f2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1409869559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1409869559
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3192354850
Short name T3723
Test name
Test status
Simulation time 618839717 ps
CPU time 6.97 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 207024 kb
Host smart-a91df00a-8cbc-459d-9588-499935c39431
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3192354850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3192354850
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2819849046
Short name T3712
Test name
Test status
Simulation time 73374701 ps
CPU time 0.85 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 206844 kb
Host smart-c4a91a92-9944-4589-8b9f-fb105297484f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2819849046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2819849046
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4203812879
Short name T3684
Test name
Test status
Simulation time 128961427 ps
CPU time 1.28 seconds
Started Aug 13 05:12:59 PM PDT 24
Finished Aug 13 05:13:00 PM PDT 24
Peak memory 215424 kb
Host smart-85f69ed1-da77-4d41-a00b-90fc10340212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203812879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.4203812879
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2604286578
Short name T3734
Test name
Test status
Simulation time 44675456 ps
CPU time 0.7 seconds
Started Aug 13 05:13:01 PM PDT 24
Finished Aug 13 05:13:02 PM PDT 24
Peak memory 205800 kb
Host smart-64eb048f-cc6e-4734-ac3a-457fcf2905a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2604286578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2604286578
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4163810600
Short name T3669
Test name
Test status
Simulation time 373838408 ps
CPU time 2.65 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:00 PM PDT 24
Peak memory 206920 kb
Host smart-667ba3a2-10ef-467c-b41b-392fcf3e5ceb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4163810600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.4163810600
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.568457511
Short name T3682
Test name
Test status
Simulation time 76703864 ps
CPU time 1.1 seconds
Started Aug 13 05:13:00 PM PDT 24
Finished Aug 13 05:13:01 PM PDT 24
Peak memory 206884 kb
Host smart-b303fd50-6ac7-43ca-ad39-27338a08e45d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=568457511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.568457511
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1449475928
Short name T503
Test name
Test status
Simulation time 1436768559 ps
CPU time 5.87 seconds
Started Aug 13 05:12:56 PM PDT 24
Finished Aug 13 05:13:02 PM PDT 24
Peak memory 207248 kb
Host smart-7c4f00f3-1f6c-4538-9ca6-b29ac6ab1aca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1449475928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1449475928
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3522703345
Short name T310
Test name
Test status
Simulation time 388413389 ps
CPU time 3.7 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:02 PM PDT 24
Peak memory 207224 kb
Host smart-21ae58d2-dee2-4160-8dca-316185b5c246
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3522703345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3522703345
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1650499901
Short name T3721
Test name
Test status
Simulation time 607558166 ps
CPU time 4.25 seconds
Started Aug 13 05:12:59 PM PDT 24
Finished Aug 13 05:13:03 PM PDT 24
Peak memory 207168 kb
Host smart-ea1bd752-f8f1-4b0a-9bc1-33acb0a6c22d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1650499901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1650499901
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1891247854
Short name T312
Test name
Test status
Simulation time 91496788 ps
CPU time 0.92 seconds
Started Aug 13 05:12:56 PM PDT 24
Finished Aug 13 05:12:57 PM PDT 24
Peak memory 206980 kb
Host smart-6a59c56e-ca29-4786-97b6-d9a7e548e178
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1891247854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1891247854
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3680841777
Short name T3670
Test name
Test status
Simulation time 193415994 ps
CPU time 1.95 seconds
Started Aug 13 05:12:57 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 215576 kb
Host smart-a98a1255-718e-4cfb-a160-86b53ff1bcfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680841777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3680841777
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.285786308
Short name T3681
Test name
Test status
Simulation time 54065348 ps
CPU time 0.83 seconds
Started Aug 13 05:13:00 PM PDT 24
Finished Aug 13 05:13:01 PM PDT 24
Peak memory 207040 kb
Host smart-293a2211-54ba-4e72-ad30-15ef0ac0dca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=285786308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.285786308
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1191575204
Short name T3660
Test name
Test status
Simulation time 83158290 ps
CPU time 0.77 seconds
Started Aug 13 05:12:56 PM PDT 24
Finished Aug 13 05:12:57 PM PDT 24
Peak memory 206836 kb
Host smart-9bc7413f-3b81-4b18-8f7f-f154020116ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1191575204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1191575204
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.112933651
Short name T314
Test name
Test status
Simulation time 208511121 ps
CPU time 2.41 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:01 PM PDT 24
Peak memory 215384 kb
Host smart-91059366-debb-44b3-8d02-e9c9fd192828
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=112933651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.112933651
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1544335715
Short name T3664
Test name
Test status
Simulation time 290591870 ps
CPU time 2.25 seconds
Started Aug 13 05:12:59 PM PDT 24
Finished Aug 13 05:13:01 PM PDT 24
Peak memory 207000 kb
Host smart-e82ef70d-9aa6-49f0-8c18-4f055852ef2b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1544335715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1544335715
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1673541573
Short name T269
Test name
Test status
Simulation time 107953817 ps
CPU time 1.21 seconds
Started Aug 13 05:13:00 PM PDT 24
Finished Aug 13 05:13:01 PM PDT 24
Peak memory 207252 kb
Host smart-f7e0f064-a461-4be6-9303-bd18238b69ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1673541573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1673541573
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3136835438
Short name T3676
Test name
Test status
Simulation time 72814503 ps
CPU time 1.83 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:00 PM PDT 24
Peak memory 207180 kb
Host smart-46d2dceb-4a7f-46f5-8e57-9614e7d2250c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3136835438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3136835438
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1622736025
Short name T3646
Test name
Test status
Simulation time 140398666 ps
CPU time 1.83 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:12 PM PDT 24
Peak memory 215516 kb
Host smart-17b6d292-3a5a-4252-a5f9-d5aeac286d25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622736025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1622736025
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2779838793
Short name T3695
Test name
Test status
Simulation time 69580078 ps
CPU time 0.98 seconds
Started Aug 13 05:13:14 PM PDT 24
Finished Aug 13 05:13:15 PM PDT 24
Peak memory 206824 kb
Host smart-5d0fee2a-786b-45de-a9bb-517967b549a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2779838793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2779838793
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1547911769
Short name T3654
Test name
Test status
Simulation time 42376077 ps
CPU time 0.72 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 206948 kb
Host smart-2e954c3c-acb8-413a-a964-56cdd914dc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1547911769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1547911769
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1231058573
Short name T3718
Test name
Test status
Simulation time 270041886 ps
CPU time 1.8 seconds
Started Aug 13 05:13:12 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 207164 kb
Host smart-83596d27-bae0-4534-b05f-6efb3cc94221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1231058573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1231058573
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3911940117
Short name T3700
Test name
Test status
Simulation time 83560562 ps
CPU time 2.03 seconds
Started Aug 13 05:13:09 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 207228 kb
Host smart-0bca98a2-82b9-4c32-9822-df03925a691f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3911940117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3911940117
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.84276544
Short name T3639
Test name
Test status
Simulation time 198046399 ps
CPU time 1.85 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:20 PM PDT 24
Peak memory 218124 kb
Host smart-fd1ddee0-81ca-4da0-a5b1-152d21b8086d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84276544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev
_csr_mem_rw_with_rand_reset.84276544
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1101212015
Short name T3665
Test name
Test status
Simulation time 98281433 ps
CPU time 1.13 seconds
Started Aug 13 05:13:19 PM PDT 24
Finished Aug 13 05:13:20 PM PDT 24
Peak memory 206924 kb
Host smart-76e55ef8-c87d-4522-b78d-71f14f9465c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1101212015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1101212015
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.551434362
Short name T3638
Test name
Test status
Simulation time 119859494 ps
CPU time 1.23 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:20 PM PDT 24
Peak memory 207156 kb
Host smart-58f9ecf1-5c46-4650-970c-429200315b0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=551434362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.551434362
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1158225480
Short name T286
Test name
Test status
Simulation time 85089549 ps
CPU time 1.82 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:12 PM PDT 24
Peak memory 207096 kb
Host smart-660edf4a-3d84-4d75-bd82-584ff5decbde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1158225480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1158225480
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2936763645
Short name T508
Test name
Test status
Simulation time 1160362753 ps
CPU time 3.62 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:22 PM PDT 24
Peak memory 207208 kb
Host smart-e4e5a5ec-9717-423e-8fec-c23252e5a61e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2936763645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2936763645
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.528280706
Short name T3726
Test name
Test status
Simulation time 61125788 ps
CPU time 1.42 seconds
Started Aug 13 05:13:17 PM PDT 24
Finished Aug 13 05:13:19 PM PDT 24
Peak memory 215460 kb
Host smart-b0f5c0d3-5bd4-4bb9-b9e7-4e6a110240c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528280706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.528280706
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3070936477
Short name T290
Test name
Test status
Simulation time 66603479 ps
CPU time 1 seconds
Started Aug 13 05:13:20 PM PDT 24
Finished Aug 13 05:13:21 PM PDT 24
Peak memory 206892 kb
Host smart-67db10cd-d2c6-4a48-87b9-d33032f11bfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3070936477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3070936477
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.877026389
Short name T3652
Test name
Test status
Simulation time 46530696 ps
CPU time 0.71 seconds
Started Aug 13 05:13:17 PM PDT 24
Finished Aug 13 05:13:18 PM PDT 24
Peak memory 206940 kb
Host smart-b058fee7-7918-4368-8ac0-0bdbb04e489a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=877026389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.877026389
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1607794484
Short name T3647
Test name
Test status
Simulation time 109334679 ps
CPU time 1.05 seconds
Started Aug 13 05:13:16 PM PDT 24
Finished Aug 13 05:13:17 PM PDT 24
Peak memory 207112 kb
Host smart-187a9de3-5f48-474c-99c8-69fa5ebc7678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1607794484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1607794484
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.207138755
Short name T3731
Test name
Test status
Simulation time 76417076 ps
CPU time 1.94 seconds
Started Aug 13 05:13:16 PM PDT 24
Finished Aug 13 05:13:18 PM PDT 24
Peak memory 222960 kb
Host smart-15017e54-0a3a-4d8e-b222-421d619fca76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=207138755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.207138755
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3315453490
Short name T3724
Test name
Test status
Simulation time 65364443 ps
CPU time 1.42 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:19 PM PDT 24
Peak memory 215604 kb
Host smart-89515cab-0685-4785-adc8-3b5f8de6ab8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315453490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3315453490
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.11557555
Short name T3683
Test name
Test status
Simulation time 46170847 ps
CPU time 0.8 seconds
Started Aug 13 05:13:17 PM PDT 24
Finished Aug 13 05:13:18 PM PDT 24
Peak memory 207036 kb
Host smart-aadaeb9f-d559-48aa-af56-7b3cf5fa5a7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=11557555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.11557555
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.411812947
Short name T3714
Test name
Test status
Simulation time 36427307 ps
CPU time 0.71 seconds
Started Aug 13 05:13:17 PM PDT 24
Finished Aug 13 05:13:18 PM PDT 24
Peak memory 206952 kb
Host smart-a1a6ee9b-198b-4a13-810a-8d771e8dbee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=411812947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.411812947
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1876005466
Short name T3693
Test name
Test status
Simulation time 161742033 ps
CPU time 1.57 seconds
Started Aug 13 05:13:19 PM PDT 24
Finished Aug 13 05:13:20 PM PDT 24
Peak memory 207288 kb
Host smart-d500452b-e4df-4446-b524-4c6f431fc269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1876005466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1876005466
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.930692211
Short name T282
Test name
Test status
Simulation time 128362056 ps
CPU time 1.85 seconds
Started Aug 13 05:13:19 PM PDT 24
Finished Aug 13 05:13:21 PM PDT 24
Peak memory 215408 kb
Host smart-60dfc849-22dc-4a41-804b-8394cabfee12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=930692211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.930692211
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3134553195
Short name T514
Test name
Test status
Simulation time 454870636 ps
CPU time 2.66 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:21 PM PDT 24
Peak memory 207328 kb
Host smart-5d39ffb1-fa43-410e-a9a1-406c0f73cef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3134553195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3134553195
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1853440606
Short name T236
Test name
Test status
Simulation time 181674802 ps
CPU time 1.71 seconds
Started Aug 13 05:13:16 PM PDT 24
Finished Aug 13 05:13:18 PM PDT 24
Peak memory 215508 kb
Host smart-24dc0479-40bf-4b29-a959-5053b4927599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853440606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1853440606
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3453173149
Short name T3717
Test name
Test status
Simulation time 59471272 ps
CPU time 0.86 seconds
Started Aug 13 05:13:20 PM PDT 24
Finished Aug 13 05:13:21 PM PDT 24
Peak memory 207036 kb
Host smart-0b453723-ce63-443e-9845-2a122d748935
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3453173149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3453173149
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4129002554
Short name T3644
Test name
Test status
Simulation time 323938696 ps
CPU time 1.9 seconds
Started Aug 13 05:13:19 PM PDT 24
Finished Aug 13 05:13:21 PM PDT 24
Peak memory 207284 kb
Host smart-1d6ec0c7-aa5a-422c-8d7b-79b1195ab74f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4129002554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.4129002554
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.708040661
Short name T3732
Test name
Test status
Simulation time 171796979 ps
CPU time 2.31 seconds
Started Aug 13 05:13:17 PM PDT 24
Finished Aug 13 05:13:20 PM PDT 24
Peak memory 215416 kb
Host smart-0639bbc8-58ff-4b0c-9888-f93ae26c6b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=708040661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.708040661
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.976457519
Short name T291
Test name
Test status
Simulation time 113930745 ps
CPU time 1.25 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:19 PM PDT 24
Peak memory 215224 kb
Host smart-87f4aad6-ff22-453f-8f50-733a8e9740c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976457519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.976457519
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4245233929
Short name T3739
Test name
Test status
Simulation time 104278694 ps
CPU time 0.91 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:19 PM PDT 24
Peak memory 206832 kb
Host smart-7777c893-ab39-4b4c-bdca-da268d639350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4245233929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4245233929
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1057578954
Short name T3708
Test name
Test status
Simulation time 59482263 ps
CPU time 0.72 seconds
Started Aug 13 05:13:19 PM PDT 24
Finished Aug 13 05:13:20 PM PDT 24
Peak memory 206840 kb
Host smart-361a21df-6376-437a-a431-a6dd28f814cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1057578954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1057578954
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2049167755
Short name T3651
Test name
Test status
Simulation time 431119730 ps
CPU time 2.14 seconds
Started Aug 13 05:13:20 PM PDT 24
Finished Aug 13 05:13:22 PM PDT 24
Peak memory 207152 kb
Host smart-1a9ed0d8-8e33-4b77-9506-3157f4dfc868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2049167755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2049167755
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3297594062
Short name T3728
Test name
Test status
Simulation time 157588141 ps
CPU time 1.72 seconds
Started Aug 13 05:13:20 PM PDT 24
Finished Aug 13 05:13:22 PM PDT 24
Peak memory 207152 kb
Host smart-89625024-5f48-43c4-8789-87edb791a4be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3297594062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3297594062
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2367150849
Short name T3706
Test name
Test status
Simulation time 493641318 ps
CPU time 3.99 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:22 PM PDT 24
Peak memory 207300 kb
Host smart-8c54096e-5c63-4413-805e-989161898d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2367150849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2367150849
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2657862961
Short name T3710
Test name
Test status
Simulation time 100494855 ps
CPU time 1.76 seconds
Started Aug 13 05:13:24 PM PDT 24
Finished Aug 13 05:13:25 PM PDT 24
Peak memory 215364 kb
Host smart-bc3c108e-00a5-4199-8647-01153d7d5985
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657862961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2657862961
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1975329096
Short name T3730
Test name
Test status
Simulation time 69008316 ps
CPU time 0.89 seconds
Started Aug 13 05:13:27 PM PDT 24
Finished Aug 13 05:13:28 PM PDT 24
Peak memory 207048 kb
Host smart-1b4d9b17-b228-4be1-935a-e4828ed2c6ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1975329096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1975329096
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4010320946
Short name T3675
Test name
Test status
Simulation time 52994860 ps
CPU time 0.73 seconds
Started Aug 13 05:13:18 PM PDT 24
Finished Aug 13 05:13:19 PM PDT 24
Peak memory 206912 kb
Host smart-dc394fd4-40e5-4d67-be06-8bd51c75ac8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4010320946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.4010320946
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1402866517
Short name T315
Test name
Test status
Simulation time 118071942 ps
CPU time 1.14 seconds
Started Aug 13 05:13:27 PM PDT 24
Finished Aug 13 05:13:28 PM PDT 24
Peak memory 207304 kb
Host smart-4b17e707-3499-43da-bd6d-bb19855fcb33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1402866517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1402866517
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3858943796
Short name T3716
Test name
Test status
Simulation time 94615959 ps
CPU time 1.49 seconds
Started Aug 13 05:13:21 PM PDT 24
Finished Aug 13 05:13:23 PM PDT 24
Peak memory 207300 kb
Host smart-4670aa68-02ac-480b-9f46-58dc792dbdee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3858943796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3858943796
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3948945386
Short name T3736
Test name
Test status
Simulation time 474993065 ps
CPU time 3.05 seconds
Started Aug 13 05:13:20 PM PDT 24
Finished Aug 13 05:13:23 PM PDT 24
Peak memory 207180 kb
Host smart-b301c0ce-5928-4299-bd38-f3d0795e94b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3948945386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3948945386
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2460791847
Short name T234
Test name
Test status
Simulation time 186804941 ps
CPU time 2.09 seconds
Started Aug 13 05:13:25 PM PDT 24
Finished Aug 13 05:13:27 PM PDT 24
Peak memory 215544 kb
Host smart-f1289813-e45f-4758-b337-e4ea14024b19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460791847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2460791847
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1224132079
Short name T3636
Test name
Test status
Simulation time 75272949 ps
CPU time 1.03 seconds
Started Aug 13 05:13:26 PM PDT 24
Finished Aug 13 05:13:27 PM PDT 24
Peak memory 207008 kb
Host smart-584a912c-c805-4983-a58e-49b1df28b1b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1224132079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1224132079
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3106988084
Short name T3666
Test name
Test status
Simulation time 42215312 ps
CPU time 0.71 seconds
Started Aug 13 05:13:26 PM PDT 24
Finished Aug 13 05:13:27 PM PDT 24
Peak memory 206944 kb
Host smart-bae58ce1-6837-4bde-8b55-b204cf065d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3106988084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3106988084
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3912684805
Short name T318
Test name
Test status
Simulation time 252861887 ps
CPU time 1.9 seconds
Started Aug 13 05:13:26 PM PDT 24
Finished Aug 13 05:13:28 PM PDT 24
Peak memory 207268 kb
Host smart-961b1b3e-3164-41ac-b09c-c8580bbe93b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3912684805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3912684805
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1000714278
Short name T289
Test name
Test status
Simulation time 273866864 ps
CPU time 2.66 seconds
Started Aug 13 05:13:26 PM PDT 24
Finished Aug 13 05:13:28 PM PDT 24
Peak memory 220504 kb
Host smart-4e6f2285-6901-4a0c-8dd6-310520a53516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1000714278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1000714278
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2363595747
Short name T275
Test name
Test status
Simulation time 1445374166 ps
CPU time 5.34 seconds
Started Aug 13 05:13:31 PM PDT 24
Finished Aug 13 05:13:36 PM PDT 24
Peak memory 207264 kb
Host smart-eb38b8fe-f367-421a-9267-8cb2f46d3b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2363595747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2363595747
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2302959411
Short name T3690
Test name
Test status
Simulation time 96506567 ps
CPU time 2.61 seconds
Started Aug 13 05:13:23 PM PDT 24
Finished Aug 13 05:13:26 PM PDT 24
Peak memory 215492 kb
Host smart-9a07f475-e650-4fab-a8b4-bdac8bda8630
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302959411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2302959411
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4268443399
Short name T302
Test name
Test status
Simulation time 72139178 ps
CPU time 1.04 seconds
Started Aug 13 05:13:26 PM PDT 24
Finished Aug 13 05:13:28 PM PDT 24
Peak memory 206864 kb
Host smart-341c1f3e-cb05-4330-9114-5ac0db88cc9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4268443399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4268443399
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.864747617
Short name T350
Test name
Test status
Simulation time 78458806 ps
CPU time 0.81 seconds
Started Aug 13 05:13:24 PM PDT 24
Finished Aug 13 05:13:25 PM PDT 24
Peak memory 206824 kb
Host smart-65de790e-382a-4c2c-accb-16e8c83bef83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=864747617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.864747617
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2541328112
Short name T3650
Test name
Test status
Simulation time 86280678 ps
CPU time 1.45 seconds
Started Aug 13 05:13:26 PM PDT 24
Finished Aug 13 05:13:28 PM PDT 24
Peak memory 207276 kb
Host smart-b076cfbd-32a1-41f8-b59f-31ebf1859cb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2541328112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2541328112
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3739156591
Short name T513
Test name
Test status
Simulation time 531872372 ps
CPU time 3.99 seconds
Started Aug 13 05:13:27 PM PDT 24
Finished Aug 13 05:13:31 PM PDT 24
Peak memory 207328 kb
Host smart-dfd50ff8-68d8-4d45-a2d1-effb526f162a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3739156591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3739156591
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.471057339
Short name T3733
Test name
Test status
Simulation time 88567354 ps
CPU time 1.18 seconds
Started Aug 13 05:13:25 PM PDT 24
Finished Aug 13 05:13:26 PM PDT 24
Peak memory 215268 kb
Host smart-69f0216c-739e-4ecd-9a06-53d01a79253c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471057339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.471057339
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4026041660
Short name T3713
Test name
Test status
Simulation time 127070401 ps
CPU time 1.11 seconds
Started Aug 13 05:13:28 PM PDT 24
Finished Aug 13 05:13:30 PM PDT 24
Peak memory 207240 kb
Host smart-f90b9950-dbed-44a0-9a33-ea68c7012f60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4026041660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4026041660
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4259087981
Short name T3687
Test name
Test status
Simulation time 66506886 ps
CPU time 0.75 seconds
Started Aug 13 05:13:23 PM PDT 24
Finished Aug 13 05:13:24 PM PDT 24
Peak memory 206860 kb
Host smart-a073ab67-26c6-4a00-8333-52ade2659349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4259087981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4259087981
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3849803890
Short name T3655
Test name
Test status
Simulation time 159049304 ps
CPU time 1.6 seconds
Started Aug 13 05:13:29 PM PDT 24
Finished Aug 13 05:13:31 PM PDT 24
Peak memory 207276 kb
Host smart-53509413-547b-42f7-85d5-e62ded493211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3849803890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3849803890
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.237523935
Short name T279
Test name
Test status
Simulation time 192910871 ps
CPU time 2.08 seconds
Started Aug 13 05:13:26 PM PDT 24
Finished Aug 13 05:13:28 PM PDT 24
Peak memory 207224 kb
Host smart-cbf88097-56cf-4fdc-98bf-56229a13e405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=237523935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.237523935
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.964954936
Short name T506
Test name
Test status
Simulation time 727988453 ps
CPU time 4.07 seconds
Started Aug 13 05:13:25 PM PDT 24
Finished Aug 13 05:13:29 PM PDT 24
Peak memory 207328 kb
Host smart-f32fe388-8726-4aac-96f9-ae4d9145fa72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=964954936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.964954936
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.190568304
Short name T3711
Test name
Test status
Simulation time 138797611 ps
CPU time 3.4 seconds
Started Aug 13 05:13:14 PM PDT 24
Finished Aug 13 05:13:17 PM PDT 24
Peak memory 207224 kb
Host smart-710e8b3c-efb3-4e97-98de-a9bf8da356ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=190568304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.190568304
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.323845704
Short name T308
Test name
Test status
Simulation time 1673979372 ps
CPU time 9.54 seconds
Started Aug 13 05:13:03 PM PDT 24
Finished Aug 13 05:13:13 PM PDT 24
Peak memory 207168 kb
Host smart-cc46cef8-a7f9-4601-bf82-b63e857cfaeb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=323845704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.323845704
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3884766845
Short name T3649
Test name
Test status
Simulation time 72952213 ps
CPU time 0.84 seconds
Started Aug 13 05:13:03 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 206864 kb
Host smart-1124442f-9a74-459d-93c0-0ff86c359870
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3884766845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3884766845
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3868455367
Short name T292
Test name
Test status
Simulation time 116700568 ps
CPU time 1.33 seconds
Started Aug 13 05:13:07 PM PDT 24
Finished Aug 13 05:13:08 PM PDT 24
Peak memory 215472 kb
Host smart-a468d9de-1c0e-4d6c-95e1-0495acbf9c94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868455367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3868455367
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.396187182
Short name T3720
Test name
Test status
Simulation time 96563836 ps
CPU time 1.08 seconds
Started Aug 13 05:13:14 PM PDT 24
Finished Aug 13 05:13:15 PM PDT 24
Peak memory 207028 kb
Host smart-6c2a6992-2b2d-429c-b879-4e9fc412f284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=396187182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.396187182
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2499437131
Short name T3705
Test name
Test status
Simulation time 36081816 ps
CPU time 0.64 seconds
Started Aug 13 05:12:59 PM PDT 24
Finished Aug 13 05:13:00 PM PDT 24
Peak memory 206836 kb
Host smart-a382fcb4-6953-4fe6-8979-7ce34f629b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2499437131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2499437131
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3808252713
Short name T309
Test name
Test status
Simulation time 212043753 ps
CPU time 2.64 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 215416 kb
Host smart-d1c5049b-60de-42fa-9c6b-31c7780c619c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3808252713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3808252713
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.482968478
Short name T3662
Test name
Test status
Simulation time 749332919 ps
CPU time 4.79 seconds
Started Aug 13 05:13:07 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 206992 kb
Host smart-e2c00746-3a3c-4c17-873f-2110699faa7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=482968478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.482968478
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.739296304
Short name T270
Test name
Test status
Simulation time 257444953 ps
CPU time 1.49 seconds
Started Aug 13 05:13:11 PM PDT 24
Finished Aug 13 05:13:13 PM PDT 24
Peak memory 207268 kb
Host smart-4626597b-366d-402c-b0db-ff945f1f78d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=739296304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.739296304
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.21023204
Short name T3703
Test name
Test status
Simulation time 153589942 ps
CPU time 2.17 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 215484 kb
Host smart-b30788f2-948e-478b-a7c6-949a1794dfc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=21023204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.21023204
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2841626829
Short name T510
Test name
Test status
Simulation time 1151266329 ps
CPU time 5.08 seconds
Started Aug 13 05:12:56 PM PDT 24
Finished Aug 13 05:13:01 PM PDT 24
Peak memory 207260 kb
Host smart-ac677401-289b-4a63-af6e-a7a640d0a209
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2841626829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2841626829
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.29751254
Short name T3738
Test name
Test status
Simulation time 87918784 ps
CPU time 0.81 seconds
Started Aug 13 05:13:24 PM PDT 24
Finished Aug 13 05:13:25 PM PDT 24
Peak memory 206856 kb
Host smart-ab0e0204-26f0-42fc-a43f-f609fb5ed560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=29751254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.29751254
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.279323346
Short name T3679
Test name
Test status
Simulation time 71305970 ps
CPU time 0.74 seconds
Started Aug 13 05:13:27 PM PDT 24
Finished Aug 13 05:13:28 PM PDT 24
Peak memory 206960 kb
Host smart-9b1f26e9-5123-4cf4-a5a2-085ec9b9774d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=279323346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.279323346
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3208979994
Short name T348
Test name
Test status
Simulation time 84227127 ps
CPU time 0.77 seconds
Started Aug 13 05:13:25 PM PDT 24
Finished Aug 13 05:13:26 PM PDT 24
Peak memory 206924 kb
Host smart-bc897456-fab4-4db1-b273-0c314f49ccfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3208979994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3208979994
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3163472391
Short name T3696
Test name
Test status
Simulation time 70164965 ps
CPU time 0.7 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 206936 kb
Host smart-af6dda19-eb37-4b53-af63-ea7a2087fb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3163472391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3163472391
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1433472700
Short name T3640
Test name
Test status
Simulation time 94544810 ps
CPU time 0.84 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 206888 kb
Host smart-c64b6484-c99f-4ecc-a0f2-90b973c6a4c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1433472700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1433472700
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3084965143
Short name T3643
Test name
Test status
Simulation time 57584066 ps
CPU time 0.77 seconds
Started Aug 13 05:13:36 PM PDT 24
Finished Aug 13 05:13:37 PM PDT 24
Peak memory 206940 kb
Host smart-e56253bc-a47c-4718-ad05-515dc914e841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3084965143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3084965143
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3380085219
Short name T3680
Test name
Test status
Simulation time 73590539 ps
CPU time 0.77 seconds
Started Aug 13 05:13:34 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 206764 kb
Host smart-77b9b297-d7a9-4f0e-a888-b63905cd5bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3380085219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3380085219
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1506112893
Short name T3697
Test name
Test status
Simulation time 59773514 ps
CPU time 0.76 seconds
Started Aug 13 05:13:32 PM PDT 24
Finished Aug 13 05:13:33 PM PDT 24
Peak memory 206832 kb
Host smart-2bc9679b-bd49-467f-8742-c9678a2f9372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1506112893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1506112893
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1406699806
Short name T353
Test name
Test status
Simulation time 76579876 ps
CPU time 0.81 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 206948 kb
Host smart-360f9703-dfc6-43d4-9d7e-a0ed3d7b10c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1406699806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1406699806
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3190344157
Short name T3701
Test name
Test status
Simulation time 226260379 ps
CPU time 2.28 seconds
Started Aug 13 05:13:03 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 207164 kb
Host smart-09c6b48d-de13-4267-aed1-5c707a99088b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3190344157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3190344157
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2663991610
Short name T3702
Test name
Test status
Simulation time 909431358 ps
CPU time 4.57 seconds
Started Aug 13 05:13:06 PM PDT 24
Finished Aug 13 05:13:10 PM PDT 24
Peak memory 207240 kb
Host smart-216c99e7-8605-48ec-86da-13ecd874a455
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2663991610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2663991610
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3782401595
Short name T307
Test name
Test status
Simulation time 123961324 ps
CPU time 0.93 seconds
Started Aug 13 05:13:05 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 207036 kb
Host smart-85881431-7fa1-41fb-bc71-61edb44c6b9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3782401595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3782401595
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1294300703
Short name T285
Test name
Test status
Simulation time 140090147 ps
CPU time 1.78 seconds
Started Aug 13 05:13:04 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 215556 kb
Host smart-72b580cf-619c-43fd-9c4c-cfbe694832e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294300703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1294300703
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2401440047
Short name T3694
Test name
Test status
Simulation time 120640367 ps
CPU time 1.02 seconds
Started Aug 13 05:13:04 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 207028 kb
Host smart-4e162484-d7fb-45a6-b329-9d912e6838d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2401440047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2401440047
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.345512320
Short name T3737
Test name
Test status
Simulation time 29876636 ps
CPU time 0.69 seconds
Started Aug 13 05:13:05 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 206924 kb
Host smart-fc3635a7-a126-4881-8b93-23437ac193a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=345512320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.345512320
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3367976014
Short name T3685
Test name
Test status
Simulation time 128529253 ps
CPU time 1.65 seconds
Started Aug 13 05:13:05 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 215420 kb
Host smart-a9809d64-d5c3-4f62-94c7-88afae99e5cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3367976014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3367976014
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.371038987
Short name T3698
Test name
Test status
Simulation time 628046804 ps
CPU time 4.18 seconds
Started Aug 13 05:13:04 PM PDT 24
Finished Aug 13 05:13:08 PM PDT 24
Peak memory 207004 kb
Host smart-cf104c2d-acc2-434a-bc47-bb945995006f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=371038987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.371038987
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3149595930
Short name T317
Test name
Test status
Simulation time 169537113 ps
CPU time 1.56 seconds
Started Aug 13 05:13:04 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 207284 kb
Host smart-90c15442-2310-4343-82f4-ad5a6d6f91fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3149595930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3149595930
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2975832411
Short name T3725
Test name
Test status
Simulation time 90763952 ps
CPU time 2.59 seconds
Started Aug 13 05:13:03 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 207240 kb
Host smart-0687c2cd-5533-46be-88e3-79961a2c3cd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2975832411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2975832411
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1021841671
Short name T294
Test name
Test status
Simulation time 1637280194 ps
CPU time 5.8 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:08 PM PDT 24
Peak memory 207176 kb
Host smart-484fa1ef-c982-4969-81e6-ec596a5504dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1021841671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1021841671
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3170941198
Short name T3729
Test name
Test status
Simulation time 51753078 ps
CPU time 0.77 seconds
Started Aug 13 05:13:36 PM PDT 24
Finished Aug 13 05:13:37 PM PDT 24
Peak memory 206936 kb
Host smart-cadb39e1-4e07-4ed7-a9f9-deec57678680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3170941198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3170941198
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2563720776
Short name T242
Test name
Test status
Simulation time 41584121 ps
CPU time 0.7 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 206856 kb
Host smart-29a2c292-3527-4ced-8e0d-66d6fe4d7f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2563720776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2563720776
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1443774371
Short name T3667
Test name
Test status
Simulation time 40770546 ps
CPU time 0.74 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 206948 kb
Host smart-7d6f6260-7738-4cce-91ae-33929c48a296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1443774371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1443774371
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2996666873
Short name T3671
Test name
Test status
Simulation time 79819510 ps
CPU time 0.82 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 206776 kb
Host smart-b483ba32-3d2b-40a4-bf25-921a67bea6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2996666873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2996666873
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.147647639
Short name T3658
Test name
Test status
Simulation time 35091039 ps
CPU time 0.71 seconds
Started Aug 13 05:13:36 PM PDT 24
Finished Aug 13 05:13:36 PM PDT 24
Peak memory 206920 kb
Host smart-ebf5fc9f-04df-4ec5-9a2a-a89933047321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=147647639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.147647639
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2606319542
Short name T3663
Test name
Test status
Simulation time 36545244 ps
CPU time 0.77 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 206916 kb
Host smart-307eadaf-0af1-4bce-9ab8-314f46aabfd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2606319542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2606319542
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3706122729
Short name T3668
Test name
Test status
Simulation time 53064679 ps
CPU time 0.73 seconds
Started Aug 13 05:13:36 PM PDT 24
Finished Aug 13 05:13:37 PM PDT 24
Peak memory 206948 kb
Host smart-a1c87e54-3300-4eb3-ac2a-9515c59383ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3706122729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3706122729
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3039181164
Short name T3677
Test name
Test status
Simulation time 45052577 ps
CPU time 0.75 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 206892 kb
Host smart-24268f06-b2be-4fd0-b8d2-9bbf2df0981e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3039181164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3039181164
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2979675484
Short name T3719
Test name
Test status
Simulation time 36706180 ps
CPU time 0.72 seconds
Started Aug 13 05:13:33 PM PDT 24
Finished Aug 13 05:13:33 PM PDT 24
Peak memory 206944 kb
Host smart-b905bf49-e634-4ab3-8d9a-65fe46c650e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2979675484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2979675484
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1963015553
Short name T3661
Test name
Test status
Simulation time 51937844 ps
CPU time 0.75 seconds
Started Aug 13 05:13:37 PM PDT 24
Finished Aug 13 05:13:38 PM PDT 24
Peak memory 206952 kb
Host smart-af3a5749-8b50-4945-b061-e84ad1c4e889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1963015553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1963015553
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.111581788
Short name T3686
Test name
Test status
Simulation time 337426121 ps
CPU time 3.5 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 207116 kb
Host smart-56f837b6-6bf5-4d10-b175-0cc41df96435
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=111581788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.111581788
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.360141587
Short name T3689
Test name
Test status
Simulation time 465201017 ps
CPU time 5 seconds
Started Aug 13 05:13:14 PM PDT 24
Finished Aug 13 05:13:19 PM PDT 24
Peak memory 207224 kb
Host smart-2b52e872-a39e-4328-80f1-1ae2f7605d46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=360141587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.360141587
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4169357657
Short name T303
Test name
Test status
Simulation time 104996901 ps
CPU time 0.93 seconds
Started Aug 13 05:13:06 PM PDT 24
Finished Aug 13 05:13:07 PM PDT 24
Peak memory 206844 kb
Host smart-4c4b6538-4f36-4d90-9fdf-fe370b77fe35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4169357657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.4169357657
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3165662055
Short name T283
Test name
Test status
Simulation time 134224490 ps
CPU time 1.41 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 215492 kb
Host smart-d4761a68-75e1-4aab-8e52-8a848cf4e485
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165662055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3165662055
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1698797708
Short name T3637
Test name
Test status
Simulation time 38371526 ps
CPU time 0.78 seconds
Started Aug 13 05:13:14 PM PDT 24
Finished Aug 13 05:13:15 PM PDT 24
Peak memory 206912 kb
Host smart-e592e2b8-8976-428f-a8f4-2bee8769f4ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1698797708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1698797708
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2006561857
Short name T3672
Test name
Test status
Simulation time 38821433 ps
CPU time 0.79 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:03 PM PDT 24
Peak memory 206916 kb
Host smart-864870aa-d7be-4ed9-a822-9707ef4a3e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2006561857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2006561857
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3330234886
Short name T311
Test name
Test status
Simulation time 95603498 ps
CPU time 1.54 seconds
Started Aug 13 05:13:14 PM PDT 24
Finished Aug 13 05:13:15 PM PDT 24
Peak memory 207248 kb
Host smart-77a0a017-8ff7-46c2-9f11-5d4f928d75bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3330234886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3330234886
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2435673873
Short name T3707
Test name
Test status
Simulation time 162111657 ps
CPU time 3.94 seconds
Started Aug 13 05:13:05 PM PDT 24
Finished Aug 13 05:13:09 PM PDT 24
Peak memory 206980 kb
Host smart-2de29a3d-5605-47d8-90ce-2dbd0cb67359
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2435673873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2435673873
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3491853189
Short name T3657
Test name
Test status
Simulation time 126173202 ps
CPU time 1.13 seconds
Started Aug 13 05:13:01 PM PDT 24
Finished Aug 13 05:13:02 PM PDT 24
Peak memory 207216 kb
Host smart-e1530480-2017-4434-a413-bf0812b9a784
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3491853189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3491853189
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2040861980
Short name T287
Test name
Test status
Simulation time 153115581 ps
CPU time 1.78 seconds
Started Aug 13 05:13:05 PM PDT 24
Finished Aug 13 05:13:07 PM PDT 24
Peak memory 215424 kb
Host smart-4336cbae-1de9-4b68-b751-dbe81a8c9308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2040861980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2040861980
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2091226797
Short name T512
Test name
Test status
Simulation time 463991382 ps
CPU time 2.83 seconds
Started Aug 13 05:13:03 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 207324 kb
Host smart-d5bf4c32-5671-49c8-83b8-fe3ca28e82c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2091226797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2091226797
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3120688092
Short name T3678
Test name
Test status
Simulation time 42281639 ps
CPU time 0.75 seconds
Started Aug 13 05:13:36 PM PDT 24
Finished Aug 13 05:13:37 PM PDT 24
Peak memory 206948 kb
Host smart-27d8a5ee-6324-4d2d-8aa0-80a6e510312b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3120688092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3120688092
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1966267989
Short name T245
Test name
Test status
Simulation time 78959297 ps
CPU time 0.78 seconds
Started Aug 13 05:13:32 PM PDT 24
Finished Aug 13 05:13:33 PM PDT 24
Peak memory 206860 kb
Host smart-1d16cdec-f600-4610-920b-c091a2bd719e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1966267989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1966267989
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2116032433
Short name T3735
Test name
Test status
Simulation time 49381492 ps
CPU time 0.85 seconds
Started Aug 13 05:13:35 PM PDT 24
Finished Aug 13 05:13:36 PM PDT 24
Peak memory 206896 kb
Host smart-351cae95-3c7f-4824-890d-5cf79b105dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2116032433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2116032433
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2403679198
Short name T3645
Test name
Test status
Simulation time 34040920 ps
CPU time 0.72 seconds
Started Aug 13 05:13:35 PM PDT 24
Finished Aug 13 05:13:36 PM PDT 24
Peak memory 206900 kb
Host smart-881c37dd-2818-46d0-adcb-76f15577c3e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2403679198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2403679198
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3040544578
Short name T324
Test name
Test status
Simulation time 48637900 ps
CPU time 0.82 seconds
Started Aug 13 05:13:34 PM PDT 24
Finished Aug 13 05:13:35 PM PDT 24
Peak memory 206936 kb
Host smart-9cffaec7-c4f0-4d92-8eb5-514e2a15ce55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3040544578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3040544578
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2646620347
Short name T3709
Test name
Test status
Simulation time 35769782 ps
CPU time 0.71 seconds
Started Aug 13 05:13:37 PM PDT 24
Finished Aug 13 05:13:38 PM PDT 24
Peak memory 206952 kb
Host smart-ac4e71f9-b82c-4ee3-8184-ba745cfe2aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2646620347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2646620347
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1692302080
Short name T323
Test name
Test status
Simulation time 50935500 ps
CPU time 0.77 seconds
Started Aug 13 05:13:32 PM PDT 24
Finished Aug 13 05:13:33 PM PDT 24
Peak memory 206800 kb
Host smart-fbeecfe5-1000-4bd9-866f-4aa51529c070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1692302080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1692302080
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1279703135
Short name T3641
Test name
Test status
Simulation time 42335810 ps
CPU time 0.72 seconds
Started Aug 13 05:13:35 PM PDT 24
Finished Aug 13 05:13:36 PM PDT 24
Peak memory 206900 kb
Host smart-cbe7c971-2269-4b03-89c9-2df5297eba15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1279703135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1279703135
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.942449909
Short name T3642
Test name
Test status
Simulation time 32447274 ps
CPU time 0.71 seconds
Started Aug 13 05:13:32 PM PDT 24
Finished Aug 13 05:13:33 PM PDT 24
Peak memory 206856 kb
Host smart-afee05b5-689f-4a52-b3b4-22828211a170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=942449909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.942449909
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2715785367
Short name T355
Test name
Test status
Simulation time 39224941 ps
CPU time 0.72 seconds
Started Aug 13 05:13:32 PM PDT 24
Finished Aug 13 05:13:33 PM PDT 24
Peak memory 206880 kb
Host smart-ed7d9020-7f54-4679-926b-02fe6d6d605e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2715785367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2715785367
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1490472510
Short name T293
Test name
Test status
Simulation time 170984932 ps
CPU time 1.8 seconds
Started Aug 13 05:13:03 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 215472 kb
Host smart-f7b0ef3d-7b7e-446a-8f80-0386ee4e8115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490472510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1490472510
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2944954647
Short name T305
Test name
Test status
Simulation time 66133820 ps
CPU time 0.89 seconds
Started Aug 13 05:13:03 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 207004 kb
Host smart-756d9242-2f6e-4d3d-a726-6549b064b12f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2944954647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2944954647
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.414561564
Short name T354
Test name
Test status
Simulation time 51440014 ps
CPU time 0.72 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:03 PM PDT 24
Peak memory 206788 kb
Host smart-073b7781-fb92-4ecd-b8cf-388e3127e51b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=414561564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.414561564
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3665336993
Short name T3674
Test name
Test status
Simulation time 251598774 ps
CPU time 1.77 seconds
Started Aug 13 05:13:05 PM PDT 24
Finished Aug 13 05:13:07 PM PDT 24
Peak memory 207296 kb
Host smart-be835c23-dff9-40e7-a653-45299c864814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3665336993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3665336993
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3570906399
Short name T507
Test name
Test status
Simulation time 907294352 ps
CPU time 5.41 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:07 PM PDT 24
Peak memory 207324 kb
Host smart-d2459aaa-f873-4012-9aa5-ad62d69d90d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3570906399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3570906399
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1353420936
Short name T3699
Test name
Test status
Simulation time 102250430 ps
CPU time 1.34 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:12 PM PDT 24
Peak memory 215460 kb
Host smart-aabe39fa-1c14-453a-a820-dbf1f8e0812a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353420936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1353420936
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2491336213
Short name T313
Test name
Test status
Simulation time 68752303 ps
CPU time 0.84 seconds
Started Aug 13 05:13:11 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 206792 kb
Host smart-6629e171-5831-4ac4-9bff-c62be238a3cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2491336213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2491336213
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.588642927
Short name T3722
Test name
Test status
Simulation time 50193682 ps
CPU time 0.75 seconds
Started Aug 13 05:13:14 PM PDT 24
Finished Aug 13 05:13:15 PM PDT 24
Peak memory 206936 kb
Host smart-1db1797a-7f7e-4f7d-954f-7efe533dd729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=588642927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.588642927
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1512223297
Short name T319
Test name
Test status
Simulation time 81594561 ps
CPU time 1.34 seconds
Started Aug 13 05:13:08 PM PDT 24
Finished Aug 13 05:13:10 PM PDT 24
Peak memory 207448 kb
Host smart-3cd19143-910e-41b6-a7ee-72baae45a521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1512223297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1512223297
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1545135665
Short name T3653
Test name
Test status
Simulation time 84674159 ps
CPU time 2.17 seconds
Started Aug 13 05:13:03 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 207340 kb
Host smart-ba14c417-f6e9-445a-8c6f-3da55abe8c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1545135665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1545135665
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4167109169
Short name T3727
Test name
Test status
Simulation time 1668021779 ps
CPU time 6.09 seconds
Started Aug 13 05:13:04 PM PDT 24
Finished Aug 13 05:13:10 PM PDT 24
Peak memory 207252 kb
Host smart-b8cff749-fe30-475b-9bc1-e302ee99e3d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4167109169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.4167109169
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1191493726
Short name T3688
Test name
Test status
Simulation time 87662649 ps
CPU time 1.75 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:12 PM PDT 24
Peak memory 215504 kb
Host smart-f89fb415-3305-43d5-afd9-c7cdaf1113bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191493726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1191493726
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2843562488
Short name T271
Test name
Test status
Simulation time 55624709 ps
CPU time 0.96 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 206856 kb
Host smart-0d053df0-f00e-4621-b13a-7441d753ac4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2843562488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2843562488
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1542018058
Short name T3635
Test name
Test status
Simulation time 235586530 ps
CPU time 1.79 seconds
Started Aug 13 05:13:13 PM PDT 24
Finished Aug 13 05:13:15 PM PDT 24
Peak memory 207136 kb
Host smart-2f0304c0-6fbc-40da-9bd8-5a7a57a4407a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1542018058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1542018058
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2174324843
Short name T3656
Test name
Test status
Simulation time 288867827 ps
CPU time 3.06 seconds
Started Aug 13 05:13:11 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 220884 kb
Host smart-8e52f5d2-d82d-4aca-a3de-a7b00870614d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2174324843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2174324843
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.464843594
Short name T504
Test name
Test status
Simulation time 938162197 ps
CPU time 5.5 seconds
Started Aug 13 05:13:08 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 207156 kb
Host smart-33e7d51a-040c-47c1-9473-d335c1094e83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=464843594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.464843594
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1312664249
Short name T3692
Test name
Test status
Simulation time 97582845 ps
CPU time 1.26 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 215256 kb
Host smart-d1755d48-2b51-41c3-a0df-6a53bbb825ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312664249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1312664249
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.134072086
Short name T316
Test name
Test status
Simulation time 62712293 ps
CPU time 0.92 seconds
Started Aug 13 05:13:08 PM PDT 24
Finished Aug 13 05:13:09 PM PDT 24
Peak memory 206992 kb
Host smart-9b16f1af-5393-4d55-9e08-ec4072a60140
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=134072086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.134072086
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2248626585
Short name T243
Test name
Test status
Simulation time 46772919 ps
CPU time 0.76 seconds
Started Aug 13 05:13:09 PM PDT 24
Finished Aug 13 05:13:10 PM PDT 24
Peak memory 206892 kb
Host smart-ad60a79b-3ffa-424e-9475-1fa764dfaf2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2248626585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2248626585
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1581385984
Short name T3648
Test name
Test status
Simulation time 154176932 ps
CPU time 1.19 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 207224 kb
Host smart-1fa8cc36-3a84-4fea-80cb-532dc562d21b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1581385984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1581385984
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4189148777
Short name T288
Test name
Test status
Simulation time 224188511 ps
CPU time 2.36 seconds
Started Aug 13 05:13:13 PM PDT 24
Finished Aug 13 05:13:16 PM PDT 24
Peak memory 207156 kb
Host smart-ee2724b1-3d8b-4ba9-8b1c-70b612ac7dd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4189148777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4189148777
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2654543748
Short name T268
Test name
Test status
Simulation time 401079823 ps
CPU time 2.62 seconds
Started Aug 13 05:13:11 PM PDT 24
Finished Aug 13 05:13:13 PM PDT 24
Peak memory 207248 kb
Host smart-8513dd60-a15c-4e76-bb51-eca5b3226228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2654543748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2654543748
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1634675895
Short name T3673
Test name
Test status
Simulation time 99179583 ps
CPU time 2.1 seconds
Started Aug 13 05:13:09 PM PDT 24
Finished Aug 13 05:13:12 PM PDT 24
Peak memory 215372 kb
Host smart-56023ff7-58f0-463b-9662-8c49e206acfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634675895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1634675895
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.942026356
Short name T304
Test name
Test status
Simulation time 82817164 ps
CPU time 0.97 seconds
Started Aug 13 05:13:11 PM PDT 24
Finished Aug 13 05:13:12 PM PDT 24
Peak memory 207036 kb
Host smart-da07ee6e-79de-40f2-9df1-b56bd1d0cc1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=942026356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.942026356
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1303563600
Short name T3704
Test name
Test status
Simulation time 42173180 ps
CPU time 0.71 seconds
Started Aug 13 05:13:11 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 206800 kb
Host smart-9f6974d3-b0ea-49d5-930d-d4cdbe623057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1303563600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1303563600
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1499563935
Short name T3659
Test name
Test status
Simulation time 173572143 ps
CPU time 1.67 seconds
Started Aug 13 05:13:10 PM PDT 24
Finished Aug 13 05:13:12 PM PDT 24
Peak memory 207184 kb
Host smart-ae5d6a7b-e9d9-4747-be3b-badb769abcf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1499563935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1499563935
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2006309745
Short name T284
Test name
Test status
Simulation time 110936164 ps
CPU time 1.94 seconds
Started Aug 13 05:13:12 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 207208 kb
Host smart-d3b56bc5-cf44-4437-a4c5-a945c3e33b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2006309745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2006309745
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2118766960
Short name T3715
Test name
Test status
Simulation time 563628046 ps
CPU time 2.78 seconds
Started Aug 13 05:13:12 PM PDT 24
Finished Aug 13 05:13:15 PM PDT 24
Peak memory 207140 kb
Host smart-7b22c045-1d24-40da-9a84-01e399a1c97d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2118766960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2118766960
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.3777670092
Short name T2532
Test name
Test status
Simulation time 38110279 ps
CPU time 0.65 seconds
Started Aug 13 06:33:11 PM PDT 24
Finished Aug 13 06:33:12 PM PDT 24
Peak memory 207488 kb
Host smart-25ceb745-f868-407f-aeef-cac5338da389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3777670092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.3777670092
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.276311194
Short name T1894
Test name
Test status
Simulation time 14044353970 ps
CPU time 17.23 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:33:08 PM PDT 24
Peak memory 216020 kb
Host smart-8b09ecf2-1e49-446f-acce-aee1f8106512
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=276311194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.276311194
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1143168572
Short name T2147
Test name
Test status
Simulation time 29045776703 ps
CPU time 39 seconds
Started Aug 13 06:32:44 PM PDT 24
Finished Aug 13 06:33:23 PM PDT 24
Peak memory 207860 kb
Host smart-8dfca1db-fb75-4fbb-b32d-50d7ed124085
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143168572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.1143168572
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4273677921
Short name T3500
Test name
Test status
Simulation time 155156608 ps
CPU time 0.84 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:32:51 PM PDT 24
Peak memory 207528 kb
Host smart-16e2c404-4896-4abb-b42e-cace7780268a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42736
77921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4273677921
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2439307240
Short name T1786
Test name
Test status
Simulation time 152660235 ps
CPU time 0.87 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:42 PM PDT 24
Peak memory 207592 kb
Host smart-98045e96-6a6e-484d-a827-6f632c46da60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24393
07240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2439307240
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.1753078141
Short name T1321
Test name
Test status
Simulation time 270812953 ps
CPU time 1.23 seconds
Started Aug 13 06:32:52 PM PDT 24
Finished Aug 13 06:32:53 PM PDT 24
Peak memory 207608 kb
Host smart-f4c39460-7c00-480d-b96d-4571d9207301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17530
78141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1753078141
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.910975781
Short name T2391
Test name
Test status
Simulation time 597689786 ps
CPU time 1.77 seconds
Started Aug 13 06:32:43 PM PDT 24
Finished Aug 13 06:32:44 PM PDT 24
Peak memory 207532 kb
Host smart-20a9202d-a65d-4878-ae1a-dd3ff4678467
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=910975781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.910975781
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.789568629
Short name T1712
Test name
Test status
Simulation time 24688505170 ps
CPU time 42.78 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 207832 kb
Host smart-b52d34db-48de-4f49-809c-4e0cc9f79903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78956
8629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.789568629
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.331693068
Short name T1439
Test name
Test status
Simulation time 1944886187 ps
CPU time 47.89 seconds
Started Aug 13 06:32:48 PM PDT 24
Finished Aug 13 06:33:36 PM PDT 24
Peak memory 207724 kb
Host smart-02fe2824-3ec5-4707-a80f-94bcf5c9e6cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331693068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.331693068
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.425509055
Short name T2555
Test name
Test status
Simulation time 495624801 ps
CPU time 1.42 seconds
Started Aug 13 06:32:48 PM PDT 24
Finished Aug 13 06:32:49 PM PDT 24
Peak memory 207512 kb
Host smart-097dc3a7-80bb-430a-b60f-105ce9780a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42550
9055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.425509055
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.473207190
Short name T2707
Test name
Test status
Simulation time 134961457 ps
CPU time 0.81 seconds
Started Aug 13 06:32:43 PM PDT 24
Finished Aug 13 06:32:44 PM PDT 24
Peak memory 207500 kb
Host smart-c89adbe0-70ee-4f9d-9110-d6f7deea9894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47320
7190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.473207190
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.152910058
Short name T2997
Test name
Test status
Simulation time 67401308 ps
CPU time 0.76 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 207472 kb
Host smart-7db7b791-e364-406d-9781-2d34bba4fa31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15291
0058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.152910058
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3081052053
Short name T758
Test name
Test status
Simulation time 945603738 ps
CPU time 2.68 seconds
Started Aug 13 06:32:53 PM PDT 24
Finished Aug 13 06:32:56 PM PDT 24
Peak memory 207796 kb
Host smart-0a582f09-5872-4644-93d4-625e64adefe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30810
52053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3081052053
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_types.680328465
Short name T434
Test name
Test status
Simulation time 378981988 ps
CPU time 1.26 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:32:53 PM PDT 24
Peak memory 207560 kb
Host smart-c8ab3fe9-509f-435d-a18a-daec22fdbb2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=680328465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.680328465
Directory /workspace/0.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.4282872573
Short name T2663
Test name
Test status
Simulation time 374363752 ps
CPU time 2.5 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:32:54 PM PDT 24
Peak memory 207728 kb
Host smart-7d4ece4d-3b50-445d-a875-8078c6c07c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42828
72573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.4282872573
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3905076505
Short name T2459
Test name
Test status
Simulation time 85178072439 ps
CPU time 130.06 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:35:00 PM PDT 24
Peak memory 207704 kb
Host smart-f97674a3-f156-4c04-8d4f-0dfec25c5db3
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3905076505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3905076505
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.923030717
Short name T2404
Test name
Test status
Simulation time 117098084309 ps
CPU time 180.33 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:35:52 PM PDT 24
Peak memory 207732 kb
Host smart-5d6bc2bf-4a20-40a2-9c43-05ca63a959f8
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=923030717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.923030717
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.4101301617
Short name T1139
Test name
Test status
Simulation time 81188264522 ps
CPU time 127 seconds
Started Aug 13 06:32:54 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 207808 kb
Host smart-d531ebc7-5b06-4590-99d3-a7e8cc9561f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101301617 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.4101301617
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.4096043759
Short name T3072
Test name
Test status
Simulation time 170547618 ps
CPU time 0.95 seconds
Started Aug 13 06:33:01 PM PDT 24
Finished Aug 13 06:33:02 PM PDT 24
Peak memory 207508 kb
Host smart-92417ef2-fac4-4ed8-a982-dddc0f0bc1a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4096043759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.4096043759
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2918275936
Short name T1726
Test name
Test status
Simulation time 195222871 ps
CPU time 0.86 seconds
Started Aug 13 06:32:56 PM PDT 24
Finished Aug 13 06:32:57 PM PDT 24
Peak memory 206336 kb
Host smart-fe15e55a-ec0d-4442-92ff-847b7b8e117a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
75936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2918275936
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.367503318
Short name T3368
Test name
Test status
Simulation time 203929231 ps
CPU time 0.92 seconds
Started Aug 13 06:32:57 PM PDT 24
Finished Aug 13 06:32:58 PM PDT 24
Peak memory 207456 kb
Host smart-4d8f68c6-bf8f-456f-a376-d3e5dc0da487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36750
3318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.367503318
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1187937284
Short name T636
Test name
Test status
Simulation time 3103427715 ps
CPU time 91.65 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:34:23 PM PDT 24
Peak memory 224076 kb
Host smart-e15f5dbd-63ba-4b08-9baa-7b7ffa042cea
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1187937284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1187937284
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.602432814
Short name T2150
Test name
Test status
Simulation time 7957057559 ps
CPU time 50.82 seconds
Started Aug 13 06:32:53 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 207820 kb
Host smart-1ee12cb5-ae03-4451-8110-8dbea11104ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=602432814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.602432814
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.958394372
Short name T2875
Test name
Test status
Simulation time 230826660 ps
CPU time 0.95 seconds
Started Aug 13 06:32:57 PM PDT 24
Finished Aug 13 06:32:58 PM PDT 24
Peak memory 206372 kb
Host smart-fefa32b6-44ea-45bc-bede-0ca6010af358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95839
4372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.958394372
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.2362510082
Short name T65
Test name
Test status
Simulation time 566652375 ps
CPU time 1.64 seconds
Started Aug 13 06:33:00 PM PDT 24
Finished Aug 13 06:33:01 PM PDT 24
Peak memory 207584 kb
Host smart-f7504521-7b93-4235-a0ae-d32697aae82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23625
10082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.2362510082
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2857525880
Short name T2797
Test name
Test status
Simulation time 26940034977 ps
CPU time 47.85 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:33:39 PM PDT 24
Peak memory 216656 kb
Host smart-a3d98e00-9e77-45f2-9939-49d4ba9c8ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28575
25880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2857525880
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2653390785
Short name T3131
Test name
Test status
Simulation time 9160969343 ps
CPU time 11.04 seconds
Started Aug 13 06:32:52 PM PDT 24
Finished Aug 13 06:33:03 PM PDT 24
Peak memory 207812 kb
Host smart-0ea8706b-8ebb-4f75-8c1b-4dc2816037c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26533
90785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2653390785
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.1086873653
Short name T3286
Test name
Test status
Simulation time 4472058305 ps
CPU time 34.73 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:33:25 PM PDT 24
Peak memory 216048 kb
Host smart-d14c381b-1b96-4f56-a8ce-960183e2f842
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1086873653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.1086873653
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3802034024
Short name T2680
Test name
Test status
Simulation time 2284517591 ps
CPU time 18.04 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:33:08 PM PDT 24
Peak memory 207860 kb
Host smart-57f0c6cf-0dcb-4766-b055-62b8597ec2ff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3802034024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3802034024
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.457403583
Short name T1456
Test name
Test status
Simulation time 247770349 ps
CPU time 1.02 seconds
Started Aug 13 06:33:04 PM PDT 24
Finished Aug 13 06:33:05 PM PDT 24
Peak memory 207500 kb
Host smart-4c66895e-f983-4533-a534-d8f566598c8d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=457403583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.457403583
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.734350217
Short name T3438
Test name
Test status
Simulation time 283795690 ps
CPU time 1.06 seconds
Started Aug 13 06:32:52 PM PDT 24
Finished Aug 13 06:32:53 PM PDT 24
Peak memory 206364 kb
Host smart-fa03c872-3975-4b23-b66a-d906f0aa3f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73435
0217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.734350217
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.3685975595
Short name T2374
Test name
Test status
Simulation time 3049259567 ps
CPU time 90.09 seconds
Started Aug 13 06:32:52 PM PDT 24
Finished Aug 13 06:34:22 PM PDT 24
Peak memory 223960 kb
Host smart-698ab3aa-29fd-4b8d-99d1-8742824201cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
75595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.3685975595
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2679147040
Short name T2132
Test name
Test status
Simulation time 2451221425 ps
CPU time 70.64 seconds
Started Aug 13 06:32:59 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 218248 kb
Host smart-f6f571a5-a078-4dc2-ab9e-ee459770e8d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2679147040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2679147040
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.612532377
Short name T2562
Test name
Test status
Simulation time 174761341 ps
CPU time 0.88 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:32:52 PM PDT 24
Peak memory 207460 kb
Host smart-cff4a867-bdf6-46cf-8b90-96ac913f9b30
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=612532377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.612532377
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3604127795
Short name T1968
Test name
Test status
Simulation time 147113393 ps
CPU time 0.84 seconds
Started Aug 13 06:33:00 PM PDT 24
Finished Aug 13 06:33:01 PM PDT 24
Peak memory 207508 kb
Host smart-87454323-2a55-41c0-86ca-f8a04241c0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36041
27795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3604127795
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1966651634
Short name T63
Test name
Test status
Simulation time 574275306 ps
CPU time 1.59 seconds
Started Aug 13 06:32:55 PM PDT 24
Finished Aug 13 06:32:57 PM PDT 24
Peak memory 207424 kb
Host smart-b9a7d0a0-9f34-4276-8d63-a7c017d42b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19666
51634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1966651634
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3718279794
Short name T1298
Test name
Test status
Simulation time 212057032 ps
CPU time 0.98 seconds
Started Aug 13 06:32:52 PM PDT 24
Finished Aug 13 06:32:53 PM PDT 24
Peak memory 207396 kb
Host smart-d2535490-c3f4-46e5-a809-319601e6e2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37182
79794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3718279794
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.4068509302
Short name T2128
Test name
Test status
Simulation time 263575931 ps
CPU time 0.91 seconds
Started Aug 13 06:32:55 PM PDT 24
Finished Aug 13 06:32:56 PM PDT 24
Peak memory 207456 kb
Host smart-1ecb3fca-8824-435b-8e6b-71094accade9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40685
09302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.4068509302
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1486106265
Short name T62
Test name
Test status
Simulation time 158830970 ps
CPU time 0.88 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:32:52 PM PDT 24
Peak memory 207608 kb
Host smart-c41b4f2b-79ff-478f-a4c6-d0ad538c2919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14861
06265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1486106265
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.979277191
Short name T3176
Test name
Test status
Simulation time 185948494 ps
CPU time 0.92 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 207588 kb
Host smart-8e11e4a4-0687-49a2-897e-778f23776ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97927
7191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.979277191
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1523671970
Short name T1656
Test name
Test status
Simulation time 167910655 ps
CPU time 0.94 seconds
Started Aug 13 06:32:59 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 207528 kb
Host smart-a4ebb8a0-1b70-452e-ab0f-d5907e88cd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15236
71970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1523671970
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1325537501
Short name T3252
Test name
Test status
Simulation time 245030413 ps
CPU time 1.14 seconds
Started Aug 13 06:32:57 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 207588 kb
Host smart-14181d98-db74-4d6b-85f5-72e593fa013d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1325537501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1325537501
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1351376636
Short name T2851
Test name
Test status
Simulation time 242215387 ps
CPU time 1.09 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 207528 kb
Host smart-6c240ba1-61f5-41a2-85c2-f7e5131ab917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13513
76636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1351376636
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.4236621622
Short name T2564
Test name
Test status
Simulation time 233116574 ps
CPU time 1 seconds
Started Aug 13 06:32:57 PM PDT 24
Finished Aug 13 06:32:58 PM PDT 24
Peak memory 207536 kb
Host smart-6b5f854c-1bb9-40ae-858b-6e9f1c784b0a
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4236621622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.4236621622
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1509018962
Short name T1818
Test name
Test status
Simulation time 216676652 ps
CPU time 1 seconds
Started Aug 13 06:33:00 PM PDT 24
Finished Aug 13 06:33:01 PM PDT 24
Peak memory 207516 kb
Host smart-a7376688-d576-4fc0-9ade-db43fa862287
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1509018962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1509018962
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1357286921
Short name T3034
Test name
Test status
Simulation time 151108062 ps
CPU time 0.83 seconds
Started Aug 13 06:33:00 PM PDT 24
Finished Aug 13 06:33:01 PM PDT 24
Peak memory 207512 kb
Host smart-dc8621aa-69f2-45c7-811b-a7aedb3fde0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
86921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1357286921
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2566877301
Short name T2092
Test name
Test status
Simulation time 50991881 ps
CPU time 0.76 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 207500 kb
Host smart-a3457640-5f82-4a76-b321-c08ff37c1fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25668
77301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2566877301
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2215982406
Short name T3339
Test name
Test status
Simulation time 20148304607 ps
CPU time 51.46 seconds
Started Aug 13 06:33:03 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 215936 kb
Host smart-712df319-0c77-401f-8aeb-9091cd8a91bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22159
82406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2215982406
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2200500746
Short name T3043
Test name
Test status
Simulation time 171209725 ps
CPU time 0.89 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 207484 kb
Host smart-4430e898-bdcd-4c42-87d7-e806312d8a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22005
00746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2200500746
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2238405248
Short name T2699
Test name
Test status
Simulation time 10300719874 ps
CPU time 75.66 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:34:14 PM PDT 24
Peak memory 224048 kb
Host smart-6b0e82ca-fc72-4b87-8dbd-c193e2998416
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238405248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2238405248
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2336379921
Short name T920
Test name
Test status
Simulation time 9008451881 ps
CPU time 48.2 seconds
Started Aug 13 06:33:01 PM PDT 24
Finished Aug 13 06:33:49 PM PDT 24
Peak memory 219368 kb
Host smart-693827c5-c6c3-4440-bdca-88641f3439ef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2336379921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2336379921
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1539338852
Short name T1356
Test name
Test status
Simulation time 10146993122 ps
CPU time 206.88 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:36:25 PM PDT 24
Peak memory 218480 kb
Host smart-7602b00c-289a-43ea-896a-47e599a947db
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539338852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1539338852
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1704936382
Short name T3545
Test name
Test status
Simulation time 253174979 ps
CPU time 1.07 seconds
Started Aug 13 06:32:59 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 207476 kb
Host smart-91128533-9cf6-4bf6-a613-f1a5369f9182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17049
36382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1704936382
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3294108059
Short name T995
Test name
Test status
Simulation time 180352744 ps
CPU time 0.96 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 207492 kb
Host smart-ca3079c0-5e37-4ab0-a5fa-bb15cbb00540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32941
08059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3294108059
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.4047554224
Short name T1006
Test name
Test status
Simulation time 20165709250 ps
CPU time 29.1 seconds
Started Aug 13 06:32:59 PM PDT 24
Finished Aug 13 06:33:29 PM PDT 24
Peak memory 207628 kb
Host smart-ecce04e8-5ce6-4fce-8edd-a40d12fafe0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40475
54224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.4047554224
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1214954000
Short name T2227
Test name
Test status
Simulation time 191482468 ps
CPU time 0.88 seconds
Started Aug 13 06:32:59 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 207496 kb
Host smart-85fabee0-f56b-406e-ac8b-2bf789c58669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12149
54000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1214954000
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.1401436705
Short name T644
Test name
Test status
Simulation time 327658180 ps
CPU time 1.26 seconds
Started Aug 13 06:33:00 PM PDT 24
Finished Aug 13 06:33:01 PM PDT 24
Peak memory 207444 kb
Host smart-bf89498a-8004-40b2-ac44-b79a4c610777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14014
36705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.1401436705
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3987485933
Short name T249
Test name
Test status
Simulation time 471392327 ps
CPU time 1.45 seconds
Started Aug 13 06:33:09 PM PDT 24
Finished Aug 13 06:33:10 PM PDT 24
Peak memory 224384 kb
Host smart-34b76bbf-da2a-4e72-8077-de2774974d4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3987485933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3987485933
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.4028617254
Short name T3250
Test name
Test status
Simulation time 314157906 ps
CPU time 1.1 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 207396 kb
Host smart-45d0dc3b-0458-4b7a-b9b7-5845a4853131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40286
17254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.4028617254
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1517511138
Short name T2833
Test name
Test status
Simulation time 165076590 ps
CPU time 0.92 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 207412 kb
Host smart-aacf8f70-385a-4f6e-b180-85eeab7ff1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15175
11138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1517511138
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3889157911
Short name T254
Test name
Test status
Simulation time 173470513 ps
CPU time 0.94 seconds
Started Aug 13 06:32:59 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 207628 kb
Host smart-950af5b3-ee57-481d-8249-0530da6d058e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38891
57911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3889157911
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2074909269
Short name T1359
Test name
Test status
Simulation time 269025277 ps
CPU time 1.11 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 207536 kb
Host smart-8b4bc646-0be7-438d-a9e7-6a16916f8937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20749
09269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2074909269
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.265599989
Short name T625
Test name
Test status
Simulation time 2780324315 ps
CPU time 27.98 seconds
Started Aug 13 06:32:58 PM PDT 24
Finished Aug 13 06:33:26 PM PDT 24
Peak memory 217628 kb
Host smart-1dfd5475-2600-4bcc-a122-b0ab3b6d9b78
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=265599989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.265599989
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.537731965
Short name T2406
Test name
Test status
Simulation time 196097220 ps
CPU time 0.9 seconds
Started Aug 13 06:33:10 PM PDT 24
Finished Aug 13 06:33:11 PM PDT 24
Peak memory 207536 kb
Host smart-5f00c3ee-a420-44da-a556-180370ef75c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53773
1965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.537731965
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1824094634
Short name T2052
Test name
Test status
Simulation time 154335268 ps
CPU time 0.88 seconds
Started Aug 13 06:33:07 PM PDT 24
Finished Aug 13 06:33:08 PM PDT 24
Peak memory 207540 kb
Host smart-77315598-90e4-448f-808f-b1dcacbe3cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18240
94634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1824094634
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1930146271
Short name T2869
Test name
Test status
Simulation time 968462033 ps
CPU time 2.45 seconds
Started Aug 13 06:33:09 PM PDT 24
Finished Aug 13 06:33:11 PM PDT 24
Peak memory 207732 kb
Host smart-ddbaae99-38e0-46af-ac98-66613ecb9dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19301
46271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1930146271
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.521120935
Short name T3630
Test name
Test status
Simulation time 2593686134 ps
CPU time 75.89 seconds
Started Aug 13 06:33:08 PM PDT 24
Finished Aug 13 06:34:24 PM PDT 24
Peak memory 217500 kb
Host smart-bea5d629-e120-4973-929f-be3d68d2b322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52112
0935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.521120935
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2154146949
Short name T216
Test name
Test status
Simulation time 3499230975 ps
CPU time 94.5 seconds
Started Aug 13 06:33:06 PM PDT 24
Finished Aug 13 06:34:40 PM PDT 24
Peak memory 218516 kb
Host smart-014f5fd7-3180-49e0-bb61-c00fe07aee59
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154146949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2154146949
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.1058064028
Short name T1084
Test name
Test status
Simulation time 1086064968 ps
CPU time 8.82 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 207752 kb
Host smart-97212ce5-d6c7-425f-93da-22f882ae9557
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058064028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.1058064028
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/0.usbdev_tx_rx_disruption.3038529667
Short name T953
Test name
Test status
Simulation time 687642618 ps
CPU time 1.94 seconds
Started Aug 13 06:33:08 PM PDT 24
Finished Aug 13 06:33:10 PM PDT 24
Peak memory 207524 kb
Host smart-75cf2f07-29c4-480e-8c12-2afe5d18a0cf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038529667 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.usbdev_tx_rx_disruption.3038529667
Directory /workspace/0.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2430156098
Short name T1699
Test name
Test status
Simulation time 5480143288 ps
CPU time 7.81 seconds
Started Aug 13 06:33:06 PM PDT 24
Finished Aug 13 06:33:13 PM PDT 24
Peak memory 215992 kb
Host smart-1e5e2a11-5a36-470d-bc06-99af4d4f57b4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430156098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.2430156098
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3753318409
Short name T1194
Test name
Test status
Simulation time 14406229234 ps
CPU time 20.36 seconds
Started Aug 13 06:33:05 PM PDT 24
Finished Aug 13 06:33:25 PM PDT 24
Peak memory 216028 kb
Host smart-b20fa97f-6b61-4078-9c0f-7df16e0cc2cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753318409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3753318409
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2249183962
Short name T3301
Test name
Test status
Simulation time 31287377948 ps
CPU time 39.8 seconds
Started Aug 13 06:33:05 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 207804 kb
Host smart-8432dac7-c2af-4f72-8e54-8739e728ac29
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249183962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.2249183962
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3560787299
Short name T3233
Test name
Test status
Simulation time 144688283 ps
CPU time 0.84 seconds
Started Aug 13 06:33:09 PM PDT 24
Finished Aug 13 06:33:10 PM PDT 24
Peak memory 207428 kb
Host smart-383f2112-9345-4e9c-9376-2ebf20813e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35607
87299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3560787299
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.3195791348
Short name T40
Test name
Test status
Simulation time 154828843 ps
CPU time 0.89 seconds
Started Aug 13 06:33:10 PM PDT 24
Finished Aug 13 06:33:11 PM PDT 24
Peak memory 207392 kb
Host smart-1e583472-f802-45e3-8c1d-0998e2dc280c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31957
91348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3195791348
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3132420785
Short name T1632
Test name
Test status
Simulation time 158351691 ps
CPU time 0.87 seconds
Started Aug 13 06:33:06 PM PDT 24
Finished Aug 13 06:33:07 PM PDT 24
Peak memory 207508 kb
Host smart-8b8ffdcc-9a63-4727-b200-b97594d69287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31324
20785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3132420785
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.618041962
Short name T967
Test name
Test status
Simulation time 539496006 ps
CPU time 1.86 seconds
Started Aug 13 06:33:05 PM PDT 24
Finished Aug 13 06:33:07 PM PDT 24
Peak memory 207584 kb
Host smart-b5d61077-92db-42b0-bc8c-09a833c48fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61804
1962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.618041962
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.599666001
Short name T1097
Test name
Test status
Simulation time 824057630 ps
CPU time 2.45 seconds
Started Aug 13 06:33:07 PM PDT 24
Finished Aug 13 06:33:10 PM PDT 24
Peak memory 207844 kb
Host smart-05ac925b-1420-4567-84a9-d73d0c96e1ba
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=599666001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.599666001
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.366267672
Short name T208
Test name
Test status
Simulation time 32706022946 ps
CPU time 51.47 seconds
Started Aug 13 06:33:06 PM PDT 24
Finished Aug 13 06:33:57 PM PDT 24
Peak memory 207880 kb
Host smart-d5df833c-01be-4ea2-aec2-5ef8de762e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36626
7672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.366267672
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.3077571017
Short name T2175
Test name
Test status
Simulation time 1025801519 ps
CPU time 22.9 seconds
Started Aug 13 06:33:05 PM PDT 24
Finished Aug 13 06:33:28 PM PDT 24
Peak memory 207772 kb
Host smart-9279dea9-de52-4600-b1fb-39b8a8c5495e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077571017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.3077571017
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.388119346
Short name T3592
Test name
Test status
Simulation time 513836340 ps
CPU time 1.55 seconds
Started Aug 13 06:33:05 PM PDT 24
Finished Aug 13 06:33:06 PM PDT 24
Peak memory 207532 kb
Host smart-a9503ae6-a87a-433e-af3f-695da1a89dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38811
9346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.388119346
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.132478901
Short name T2846
Test name
Test status
Simulation time 157829488 ps
CPU time 0.89 seconds
Started Aug 13 06:33:09 PM PDT 24
Finished Aug 13 06:33:10 PM PDT 24
Peak memory 207492 kb
Host smart-2c58548f-b1f1-4655-99e3-533abe6b9c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13247
8901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.132478901
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1241177597
Short name T1064
Test name
Test status
Simulation time 61352493 ps
CPU time 0.75 seconds
Started Aug 13 06:33:11 PM PDT 24
Finished Aug 13 06:33:12 PM PDT 24
Peak memory 207480 kb
Host smart-286c9109-c0d9-4013-946f-ab8a1cbee4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12411
77597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1241177597
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.834068367
Short name T3140
Test name
Test status
Simulation time 872272750 ps
CPU time 2.48 seconds
Started Aug 13 06:33:06 PM PDT 24
Finished Aug 13 06:33:08 PM PDT 24
Peak memory 207772 kb
Host smart-729abfa1-494a-402d-9075-940c125a359b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83406
8367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.834068367
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1222653867
Short name T1919
Test name
Test status
Simulation time 102196373597 ps
CPU time 164.71 seconds
Started Aug 13 06:33:05 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 207712 kb
Host smart-eb9fc342-6af5-451f-8d18-0a4169fb8577
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1222653867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1222653867
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.341968611
Short name T1827
Test name
Test status
Simulation time 85268689507 ps
CPU time 150.44 seconds
Started Aug 13 06:33:09 PM PDT 24
Finished Aug 13 06:35:40 PM PDT 24
Peak memory 207852 kb
Host smart-a9cf5554-463d-4081-b769-c15919563593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341968611 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.341968611
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2981869373
Short name T533
Test name
Test status
Simulation time 105113246149 ps
CPU time 175.45 seconds
Started Aug 13 06:33:12 PM PDT 24
Finished Aug 13 06:36:07 PM PDT 24
Peak memory 207800 kb
Host smart-2f03f0a6-43ec-4c6e-ab2f-4b70ce6b7ce8
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2981869373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2981869373
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.2686990821
Short name T87
Test name
Test status
Simulation time 88234268738 ps
CPU time 146.94 seconds
Started Aug 13 06:33:05 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207780 kb
Host smart-ee89e57d-4657-4acc-9133-637a71be6823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686990821 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.2686990821
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3539540565
Short name T706
Test name
Test status
Simulation time 121108341142 ps
CPU time 194.88 seconds
Started Aug 13 06:33:09 PM PDT 24
Finished Aug 13 06:36:24 PM PDT 24
Peak memory 207744 kb
Host smart-00b5b33d-18c0-4450-9f3d-fe13ec647de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35395
40565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3539540565
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2189424229
Short name T562
Test name
Test status
Simulation time 279206961 ps
CPU time 1.38 seconds
Started Aug 13 06:33:12 PM PDT 24
Finished Aug 13 06:33:14 PM PDT 24
Peak memory 215896 kb
Host smart-484fbaa8-f9aa-4659-930c-2fbf83e2f67e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2189424229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2189424229
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2234011555
Short name T1410
Test name
Test status
Simulation time 159007433 ps
CPU time 0.85 seconds
Started Aug 13 06:33:11 PM PDT 24
Finished Aug 13 06:33:12 PM PDT 24
Peak memory 207404 kb
Host smart-6e5be66a-eac3-4ff5-bb5f-0339532fceff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22340
11555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2234011555
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3566498124
Short name T2297
Test name
Test status
Simulation time 174017181 ps
CPU time 0.91 seconds
Started Aug 13 06:33:13 PM PDT 24
Finished Aug 13 06:33:14 PM PDT 24
Peak memory 207388 kb
Host smart-3ec407fc-f427-4ab4-841f-9f4ba6f9c197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35664
98124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3566498124
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.1146875408
Short name T1070
Test name
Test status
Simulation time 4351230284 ps
CPU time 118.4 seconds
Started Aug 13 06:33:10 PM PDT 24
Finished Aug 13 06:35:08 PM PDT 24
Peak memory 215900 kb
Host smart-20d9bda4-69ce-43ac-8698-36c1c13afdd3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1146875408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.1146875408
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.1163046043
Short name T1061
Test name
Test status
Simulation time 6420020046 ps
CPU time 79.82 seconds
Started Aug 13 06:33:15 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207808 kb
Host smart-5efd4f2a-90d6-4080-be46-39c08a011af1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1163046043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.1163046043
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3838972147
Short name T2360
Test name
Test status
Simulation time 243890733 ps
CPU time 1.03 seconds
Started Aug 13 06:33:12 PM PDT 24
Finished Aug 13 06:33:13 PM PDT 24
Peak memory 207464 kb
Host smart-677dfc1f-05bf-4ddb-aad3-e076dd1b1ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38389
72147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3838972147
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3295819828
Short name T3576
Test name
Test status
Simulation time 10287518425 ps
CPU time 16.73 seconds
Started Aug 13 06:33:14 PM PDT 24
Finished Aug 13 06:33:31 PM PDT 24
Peak memory 207824 kb
Host smart-a05fd644-f000-4648-9f31-a4430982d55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958
19828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3295819828
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2416564335
Short name T2853
Test name
Test status
Simulation time 3278873761 ps
CPU time 98.17 seconds
Started Aug 13 06:33:13 PM PDT 24
Finished Aug 13 06:34:51 PM PDT 24
Peak memory 215996 kb
Host smart-e2c78a83-d2c0-4f65-b2bb-f029bbedae7f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2416564335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2416564335
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.3835998862
Short name T2422
Test name
Test status
Simulation time 3934267542 ps
CPU time 40.22 seconds
Started Aug 13 06:33:16 PM PDT 24
Finished Aug 13 06:33:56 PM PDT 24
Peak memory 217788 kb
Host smart-28e3c68a-c122-4c31-8846-1bb7c6d61199
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3835998862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.3835998862
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3902922807
Short name T3336
Test name
Test status
Simulation time 249104993 ps
CPU time 1.1 seconds
Started Aug 13 06:33:18 PM PDT 24
Finished Aug 13 06:33:19 PM PDT 24
Peak memory 207424 kb
Host smart-66f015c5-3c80-48ac-aafc-67bf3b35e24f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3902922807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3902922807
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2931912917
Short name T2099
Test name
Test status
Simulation time 192977864 ps
CPU time 0.96 seconds
Started Aug 13 06:33:18 PM PDT 24
Finished Aug 13 06:33:19 PM PDT 24
Peak memory 207492 kb
Host smart-8a0476e8-826d-4dda-8e4a-8e90a40f7d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29319
12917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2931912917
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.1719801757
Short name T641
Test name
Test status
Simulation time 2982870394 ps
CPU time 83.62 seconds
Started Aug 13 06:33:13 PM PDT 24
Finished Aug 13 06:34:36 PM PDT 24
Peak memory 217656 kb
Host smart-5049a5ad-96e1-405d-a7b5-75e13ac7c2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17198
01757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.1719801757
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.561101413
Short name T1708
Test name
Test status
Simulation time 3129567881 ps
CPU time 27.94 seconds
Started Aug 13 06:33:18 PM PDT 24
Finished Aug 13 06:33:46 PM PDT 24
Peak memory 215844 kb
Host smart-697e10ce-2418-4b40-b01f-b05343dd26b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=561101413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.561101413
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.997805972
Short name T1573
Test name
Test status
Simulation time 2999789732 ps
CPU time 29.39 seconds
Started Aug 13 06:33:14 PM PDT 24
Finished Aug 13 06:33:43 PM PDT 24
Peak memory 217744 kb
Host smart-e18187ad-2118-4d55-a77c-130bef7ba24d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=997805972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.997805972
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1807357166
Short name T2975
Test name
Test status
Simulation time 151339489 ps
CPU time 0.83 seconds
Started Aug 13 06:33:13 PM PDT 24
Finished Aug 13 06:33:14 PM PDT 24
Peak memory 207448 kb
Host smart-76ec63d8-f5ec-4d56-a835-0de01ec0cfcd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1807357166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1807357166
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.410580542
Short name T1852
Test name
Test status
Simulation time 148638928 ps
CPU time 0.86 seconds
Started Aug 13 06:33:16 PM PDT 24
Finished Aug 13 06:33:17 PM PDT 24
Peak memory 207424 kb
Host smart-6dd9f2bc-8817-4a4b-b758-79d67f3023af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41058
0542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.410580542
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1984218730
Short name T2383
Test name
Test status
Simulation time 162180018 ps
CPU time 0.88 seconds
Started Aug 13 06:33:16 PM PDT 24
Finished Aug 13 06:33:17 PM PDT 24
Peak memory 207500 kb
Host smart-e35c0074-cb4b-4c1b-b425-dc3df0443dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19842
18730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1984218730
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2338737628
Short name T654
Test name
Test status
Simulation time 148682050 ps
CPU time 0.83 seconds
Started Aug 13 06:33:13 PM PDT 24
Finished Aug 13 06:33:14 PM PDT 24
Peak memory 207424 kb
Host smart-c242a8d5-bfdd-41f1-84ec-1f2cb7fa3d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23387
37628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2338737628
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1040899114
Short name T2920
Test name
Test status
Simulation time 155598527 ps
CPU time 0.84 seconds
Started Aug 13 06:33:15 PM PDT 24
Finished Aug 13 06:33:16 PM PDT 24
Peak memory 207576 kb
Host smart-7896e3ac-6dd7-40c4-b2bd-97e33e682807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10408
99114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1040899114
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.4043388859
Short name T2411
Test name
Test status
Simulation time 166094043 ps
CPU time 0.86 seconds
Started Aug 13 06:33:14 PM PDT 24
Finished Aug 13 06:33:15 PM PDT 24
Peak memory 207568 kb
Host smart-c3072e22-f9c6-4a8f-978c-ea1d5321a1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40433
88859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.4043388859
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1131688827
Short name T1830
Test name
Test status
Simulation time 243935888 ps
CPU time 1.06 seconds
Started Aug 13 06:33:15 PM PDT 24
Finished Aug 13 06:33:16 PM PDT 24
Peak memory 207520 kb
Host smart-c71e1a09-62dd-428b-8c87-3054c7508bae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1131688827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1131688827
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3518594886
Short name T1466
Test name
Test status
Simulation time 220526569 ps
CPU time 1.01 seconds
Started Aug 13 06:33:17 PM PDT 24
Finished Aug 13 06:33:18 PM PDT 24
Peak memory 207516 kb
Host smart-2a4ff225-6f5d-48c2-9d51-4ca6265fcf61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185
94886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3518594886
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1197385290
Short name T1040
Test name
Test status
Simulation time 38346817 ps
CPU time 0.7 seconds
Started Aug 13 06:33:14 PM PDT 24
Finished Aug 13 06:33:15 PM PDT 24
Peak memory 207256 kb
Host smart-9555bf12-16dd-474c-8cde-8985170f35ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11973
85290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1197385290
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1397514908
Short name T2693
Test name
Test status
Simulation time 7885846663 ps
CPU time 21.38 seconds
Started Aug 13 06:33:17 PM PDT 24
Finished Aug 13 06:33:38 PM PDT 24
Peak memory 215980 kb
Host smart-07f4d011-024b-46a7-b21e-06c861d43d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13975
14908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1397514908
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1372733470
Short name T2307
Test name
Test status
Simulation time 160542102 ps
CPU time 0.92 seconds
Started Aug 13 06:33:13 PM PDT 24
Finished Aug 13 06:33:14 PM PDT 24
Peak memory 207472 kb
Host smart-0d9ddd54-d991-4cc0-9219-16f05926cf13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13727
33470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1372733470
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.554026328
Short name T1735
Test name
Test status
Simulation time 170530334 ps
CPU time 0.89 seconds
Started Aug 13 06:33:13 PM PDT 24
Finished Aug 13 06:33:14 PM PDT 24
Peak memory 207384 kb
Host smart-94106c99-fe8c-46ea-bd4e-2a2d9f333407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55402
6328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.554026328
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.148227398
Short name T1590
Test name
Test status
Simulation time 2928140176 ps
CPU time 31.24 seconds
Started Aug 13 06:33:12 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 218332 kb
Host smart-4ad323ff-a001-4c45-bf6f-d8c9b307558f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=148227398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.148227398
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.3934151003
Short name T1371
Test name
Test status
Simulation time 8305302737 ps
CPU time 39.51 seconds
Started Aug 13 06:33:16 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 219856 kb
Host smart-39bf1c72-593f-4d29-aebb-747c5bc0d409
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3934151003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.3934151003
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3793908013
Short name T3364
Test name
Test status
Simulation time 5538464448 ps
CPU time 20.09 seconds
Started Aug 13 06:33:24 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 219304 kb
Host smart-13cb55d0-1aa8-4c14-a5ef-e5677dcdd2a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793908013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3793908013
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3032576132
Short name T2683
Test name
Test status
Simulation time 169814844 ps
CPU time 0.95 seconds
Started Aug 13 06:33:16 PM PDT 24
Finished Aug 13 06:33:17 PM PDT 24
Peak memory 207500 kb
Host smart-a9b68b27-c468-45a4-9d56-d0cb49623085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30325
76132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3032576132
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.1779701048
Short name T556
Test name
Test status
Simulation time 150116683 ps
CPU time 0.86 seconds
Started Aug 13 06:33:14 PM PDT 24
Finished Aug 13 06:33:15 PM PDT 24
Peak memory 207324 kb
Host smart-ea9ce56d-c5bf-45e2-9bce-0a14cc09cf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17797
01048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.1779701048
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_resume_link_active.651742270
Short name T1779
Test name
Test status
Simulation time 20161361193 ps
CPU time 25.17 seconds
Started Aug 13 06:33:22 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 207592 kb
Host smart-260a647f-aa90-4bf9-b066-4e85b0392cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65174
2270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.651742270
Directory /workspace/1.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1402360083
Short name T3126
Test name
Test status
Simulation time 173560426 ps
CPU time 0.97 seconds
Started Aug 13 06:33:26 PM PDT 24
Finished Aug 13 06:33:27 PM PDT 24
Peak memory 207436 kb
Host smart-bba299f9-ae17-47e9-84c3-6240e1574c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14023
60083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1402360083
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.733355522
Short name T71
Test name
Test status
Simulation time 174928673 ps
CPU time 0.96 seconds
Started Aug 13 06:33:25 PM PDT 24
Finished Aug 13 06:33:26 PM PDT 24
Peak memory 207520 kb
Host smart-7fcf27eb-b226-45c3-81b8-831fa4cbb1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73335
5522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.733355522
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.963247917
Short name T248
Test name
Test status
Simulation time 365226166 ps
CPU time 1.2 seconds
Started Aug 13 06:33:22 PM PDT 24
Finished Aug 13 06:33:23 PM PDT 24
Peak memory 223188 kb
Host smart-70165ee9-211b-4259-b402-7ecf004faca5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=963247917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.963247917
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.2182547534
Short name T3256
Test name
Test status
Simulation time 430483514 ps
CPU time 1.44 seconds
Started Aug 13 06:33:21 PM PDT 24
Finished Aug 13 06:33:23 PM PDT 24
Peak memory 207500 kb
Host smart-03162348-229c-4b62-a2d2-9bb89edd1857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21825
47534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.2182547534
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.2165498011
Short name T2926
Test name
Test status
Simulation time 221898058 ps
CPU time 1 seconds
Started Aug 13 06:33:21 PM PDT 24
Finished Aug 13 06:33:22 PM PDT 24
Peak memory 207492 kb
Host smart-98a956b4-19af-4306-817a-c7ebeaee05af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21654
98011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2165498011
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2109234274
Short name T2427
Test name
Test status
Simulation time 159207124 ps
CPU time 0.85 seconds
Started Aug 13 06:33:23 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 207496 kb
Host smart-1b47a378-d91c-4c9e-bd85-3b3d11a467fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21092
34274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2109234274
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2783769727
Short name T621
Test name
Test status
Simulation time 152994623 ps
CPU time 0.92 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:33:33 PM PDT 24
Peak memory 207548 kb
Host smart-7b32e3e0-ab65-4e1d-9768-2c8fd4f1cd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27837
69727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2783769727
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3663471695
Short name T1635
Test name
Test status
Simulation time 211691739 ps
CPU time 1 seconds
Started Aug 13 06:33:24 PM PDT 24
Finished Aug 13 06:33:25 PM PDT 24
Peak memory 207468 kb
Host smart-4483bc20-cbf5-4d52-981f-f0f6cd6a51fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36634
71695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3663471695
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.341365854
Short name T2576
Test name
Test status
Simulation time 1916250795 ps
CPU time 54.84 seconds
Started Aug 13 06:33:23 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 215860 kb
Host smart-a22b8945-4f04-4037-9a6a-a03ecf919cee
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=341365854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.341365854
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2805447013
Short name T2359
Test name
Test status
Simulation time 153969936 ps
CPU time 0.85 seconds
Started Aug 13 06:33:23 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 207456 kb
Host smart-52781fba-5bc1-4d4b-9892-4b56cae561ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28054
47013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2805447013
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3603587118
Short name T959
Test name
Test status
Simulation time 169260651 ps
CPU time 0.92 seconds
Started Aug 13 06:33:24 PM PDT 24
Finished Aug 13 06:33:25 PM PDT 24
Peak memory 207472 kb
Host smart-e8ed182f-d0d8-452a-a402-1d4588756280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36035
87118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3603587118
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.3287487477
Short name T2316
Test name
Test status
Simulation time 1134184743 ps
CPU time 2.8 seconds
Started Aug 13 06:33:21 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 207716 kb
Host smart-a1a14bca-7a34-4229-a9aa-13e63a54f8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32874
87477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.3287487477
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.1778875508
Short name T2697
Test name
Test status
Simulation time 2757186147 ps
CPU time 28.48 seconds
Started Aug 13 06:33:25 PM PDT 24
Finished Aug 13 06:33:53 PM PDT 24
Peak memory 224176 kb
Host smart-caa2a1a0-0f8c-4881-9d89-d0e8a7edf492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17788
75508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.1778875508
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.1269850094
Short name T114
Test name
Test status
Simulation time 2034809304 ps
CPU time 18.2 seconds
Started Aug 13 06:33:05 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 207752 kb
Host smart-b69f6dd1-6c89-4933-a1c7-59c1fc47ed0a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269850094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.1269850094
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_tx_rx_disruption.3947648535
Short name T962
Test name
Test status
Simulation time 594554366 ps
CPU time 1.58 seconds
Started Aug 13 06:33:24 PM PDT 24
Finished Aug 13 06:33:26 PM PDT 24
Peak memory 207552 kb
Host smart-d99130eb-58ef-4a8d-94af-7327b8422eb1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947648535 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.usbdev_tx_rx_disruption.3947648535
Directory /workspace/1.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.2533452267
Short name T2238
Test name
Test status
Simulation time 39491532 ps
CPU time 0.72 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 207492 kb
Host smart-9a1b6166-fba3-4daf-98cb-40c899dd483c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2533452267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2533452267
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2539617977
Short name T3259
Test name
Test status
Simulation time 5690983596 ps
CPU time 8.01 seconds
Started Aug 13 06:35:03 PM PDT 24
Finished Aug 13 06:35:11 PM PDT 24
Peak memory 216028 kb
Host smart-7d4862dc-5fd6-45c5-8476-6fe36507db10
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539617977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.2539617977
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1324321725
Short name T1305
Test name
Test status
Simulation time 14689638735 ps
CPU time 17.76 seconds
Started Aug 13 06:35:03 PM PDT 24
Finished Aug 13 06:35:21 PM PDT 24
Peak memory 216024 kb
Host smart-2b79887d-8cf4-44ce-a64b-94086f1c2928
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324321725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1324321725
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.4228888973
Short name T919
Test name
Test status
Simulation time 23346199081 ps
CPU time 34.55 seconds
Started Aug 13 06:34:58 PM PDT 24
Finished Aug 13 06:35:33 PM PDT 24
Peak memory 216008 kb
Host smart-0f816f2a-c939-40f9-9cf5-5975dc3a91a3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228888973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.4228888973
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2542470830
Short name T1292
Test name
Test status
Simulation time 157839069 ps
CPU time 0.91 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 207452 kb
Host smart-87a25010-a7f2-4a47-8168-1eda5ce9434f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25424
70830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2542470830
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3590499440
Short name T848
Test name
Test status
Simulation time 159059478 ps
CPU time 0.83 seconds
Started Aug 13 06:34:57 PM PDT 24
Finished Aug 13 06:34:58 PM PDT 24
Peak memory 207568 kb
Host smart-f3c35928-f34e-453a-82eb-da8e39f9def0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35904
99440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3590499440
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3397950649
Short name T870
Test name
Test status
Simulation time 254910500 ps
CPU time 1.12 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:34:55 PM PDT 24
Peak memory 207580 kb
Host smart-243fda83-b417-42ee-94bf-025610c929eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33979
50649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3397950649
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1279208388
Short name T2714
Test name
Test status
Simulation time 997474723 ps
CPU time 2.76 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:34:56 PM PDT 24
Peak memory 207756 kb
Host smart-d6a8541f-16c0-461b-ad59-13d993ae8f85
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1279208388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1279208388
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.454619444
Short name T1975
Test name
Test status
Simulation time 40644642719 ps
CPU time 64.21 seconds
Started Aug 13 06:34:55 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 207848 kb
Host smart-4f994900-ea22-49ab-ba29-8c34793bfa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45461
9444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.454619444
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.30181383
Short name T2251
Test name
Test status
Simulation time 1075490789 ps
CPU time 9.7 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:35:04 PM PDT 24
Peak memory 207792 kb
Host smart-7c3643f8-ea02-48e0-9a6e-af726db8f3dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30181383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.30181383
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2164238751
Short name T1988
Test name
Test status
Simulation time 742951468 ps
CPU time 1.76 seconds
Started Aug 13 06:34:59 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 207568 kb
Host smart-971d6b62-e1f1-46ab-8d48-c0d2534a83e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21642
38751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2164238751
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2374514073
Short name T3338
Test name
Test status
Simulation time 227075116 ps
CPU time 0.94 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:34:55 PM PDT 24
Peak memory 207552 kb
Host smart-82d2c01f-308f-4145-a84c-956902b7ab96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23745
14073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2374514073
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1861515404
Short name T699
Test name
Test status
Simulation time 45366117 ps
CPU time 0.72 seconds
Started Aug 13 06:34:56 PM PDT 24
Finished Aug 13 06:34:57 PM PDT 24
Peak memory 207476 kb
Host smart-c13750d2-dfdc-4ed3-abeb-969e7fd886f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18615
15404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1861515404
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.504506534
Short name T2040
Test name
Test status
Simulation time 839708529 ps
CPU time 2.23 seconds
Started Aug 13 06:34:58 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 207692 kb
Host smart-f657e96b-9fba-4b4f-b2a9-7ff031053e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50450
6534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.504506534
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.325467502
Short name T2106
Test name
Test status
Simulation time 210634342 ps
CPU time 1.41 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 207696 kb
Host smart-b44a19d5-5f0a-46bc-9fc2-c945b9bf7360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32546
7502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.325467502
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.697551376
Short name T645
Test name
Test status
Simulation time 252436176 ps
CPU time 1.2 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 215924 kb
Host smart-2fcb640e-f3e9-41b0-90ff-dee24f2f905c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=697551376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.697551376
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3696393304
Short name T3309
Test name
Test status
Simulation time 135864623 ps
CPU time 0.86 seconds
Started Aug 13 06:35:03 PM PDT 24
Finished Aug 13 06:35:04 PM PDT 24
Peak memory 207340 kb
Host smart-ba93a7d2-ef35-4622-aa50-db8cdb687c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36963
93304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3696393304
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.4159101258
Short name T3059
Test name
Test status
Simulation time 236058608 ps
CPU time 1.05 seconds
Started Aug 13 06:35:03 PM PDT 24
Finished Aug 13 06:35:04 PM PDT 24
Peak memory 207528 kb
Host smart-4b9922db-b92b-440a-a6c4-53a73a1268d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41591
01258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.4159101258
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.2741657046
Short name T1458
Test name
Test status
Simulation time 3068980795 ps
CPU time 89.06 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:36:29 PM PDT 24
Peak memory 217732 kb
Host smart-b9705ecd-f895-439e-b5cb-c0c9e11b1878
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2741657046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2741657046
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.495708183
Short name T979
Test name
Test status
Simulation time 10786581289 ps
CPU time 78.51 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:36:19 PM PDT 24
Peak memory 207824 kb
Host smart-ad7b1f38-791a-4ae1-b415-2abe46303302
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=495708183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.495708183
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3990787570
Short name T2322
Test name
Test status
Simulation time 224422341 ps
CPU time 1.03 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 207628 kb
Host smart-b3a46957-d882-4ac0-831d-cbc268de4e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39907
87570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3990787570
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3614146773
Short name T2771
Test name
Test status
Simulation time 31720542414 ps
CPU time 44.02 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:35:44 PM PDT 24
Peak memory 207852 kb
Host smart-19e8c95e-7c59-4c29-8df4-dc9b72933c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36141
46773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3614146773
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3479244622
Short name T973
Test name
Test status
Simulation time 4572405100 ps
CPU time 6.51 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:08 PM PDT 24
Peak memory 207812 kb
Host smart-b0194fec-7a12-4f6e-b8c3-c5aa5116bf8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34792
44622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3479244622
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3385228574
Short name T2592
Test name
Test status
Simulation time 3382767838 ps
CPU time 100.84 seconds
Started Aug 13 06:35:05 PM PDT 24
Finished Aug 13 06:36:46 PM PDT 24
Peak memory 215928 kb
Host smart-3f1da339-7e9a-461e-bfc6-62e9b32667e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3385228574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3385228574
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.366078282
Short name T3303
Test name
Test status
Simulation time 2257292066 ps
CPU time 62.46 seconds
Started Aug 13 06:34:59 PM PDT 24
Finished Aug 13 06:36:02 PM PDT 24
Peak memory 215988 kb
Host smart-1bbd87fd-732d-469f-b3ab-f23e58cf24a9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=366078282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.366078282
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.3054323427
Short name T2257
Test name
Test status
Simulation time 298689022 ps
CPU time 1.1 seconds
Started Aug 13 06:35:07 PM PDT 24
Finished Aug 13 06:35:08 PM PDT 24
Peak memory 207476 kb
Host smart-776e1785-acfa-4ddb-aea6-d2d9cb6f5061
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3054323427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.3054323427
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1779169590
Short name T2484
Test name
Test status
Simulation time 231924283 ps
CPU time 1.07 seconds
Started Aug 13 06:35:01 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 207484 kb
Host smart-59cf8372-69cf-46c1-9840-79d2b3d753ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17791
69590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1779169590
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.212504199
Short name T2458
Test name
Test status
Simulation time 2674333671 ps
CPU time 20.66 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:23 PM PDT 24
Peak memory 217960 kb
Host smart-004ad421-13e5-4095-b1d5-c7a4292d5d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21250
4199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.212504199
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1514804504
Short name T2222
Test name
Test status
Simulation time 3111594361 ps
CPU time 91.89 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:36:34 PM PDT 24
Peak memory 217656 kb
Host smart-9858ce38-370f-43e3-b9d1-df69614472a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1514804504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1514804504
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1074744799
Short name T663
Test name
Test status
Simulation time 2360523616 ps
CPU time 68.76 seconds
Started Aug 13 06:35:05 PM PDT 24
Finished Aug 13 06:36:14 PM PDT 24
Peak memory 215884 kb
Host smart-b96261bf-647c-45a0-b811-b089e5abb547
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1074744799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1074744799
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.140373976
Short name T1477
Test name
Test status
Simulation time 148819235 ps
CPU time 0.89 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 207552 kb
Host smart-f3c9ec5a-ea61-4b5f-95a4-3a21db5af9c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=140373976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.140373976
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2797862918
Short name T541
Test name
Test status
Simulation time 154959903 ps
CPU time 0.93 seconds
Started Aug 13 06:35:04 PM PDT 24
Finished Aug 13 06:35:05 PM PDT 24
Peak memory 207424 kb
Host smart-44ebeaeb-3f4c-4b08-9355-adb3ac6deb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27978
62918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2797862918
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2334048425
Short name T2793
Test name
Test status
Simulation time 177099854 ps
CPU time 1.01 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 207532 kb
Host smart-cc9a0e9b-5d39-453b-9d8e-ef2675857ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23340
48425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2334048425
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4125498593
Short name T1578
Test name
Test status
Simulation time 179055382 ps
CPU time 0.96 seconds
Started Aug 13 06:35:07 PM PDT 24
Finished Aug 13 06:35:08 PM PDT 24
Peak memory 207484 kb
Host smart-206ba0a6-4609-4460-85ff-1c5960397d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41254
98593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4125498593
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2401550610
Short name T2121
Test name
Test status
Simulation time 162353762 ps
CPU time 0.87 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 207568 kb
Host smart-81e622eb-39b8-4d62-9ed2-5428f7958807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24015
50610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2401550610
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3399593502
Short name T2094
Test name
Test status
Simulation time 161749284 ps
CPU time 0.87 seconds
Started Aug 13 06:35:01 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 207588 kb
Host smart-d170bc57-cc46-4301-bb4a-9e604b43a258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33995
93502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3399593502
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.61218059
Short name T785
Test name
Test status
Simulation time 280728734 ps
CPU time 1.12 seconds
Started Aug 13 06:35:05 PM PDT 24
Finished Aug 13 06:35:06 PM PDT 24
Peak memory 207468 kb
Host smart-0e8519fa-b5c0-4d61-8051-82088b35435c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=61218059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.61218059
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3964222837
Short name T918
Test name
Test status
Simulation time 145779118 ps
CPU time 0.85 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 207492 kb
Host smart-0d7a161d-153c-4b8c-b8ed-755ead2dafd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39642
22837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3964222837
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2075831401
Short name T3512
Test name
Test status
Simulation time 43260837 ps
CPU time 0.72 seconds
Started Aug 13 06:35:07 PM PDT 24
Finished Aug 13 06:35:08 PM PDT 24
Peak memory 207468 kb
Host smart-81d6ad51-1cb8-483b-bbb3-e5fcfd986752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20758
31401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2075831401
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1375702904
Short name T2955
Test name
Test status
Simulation time 10692070338 ps
CPU time 29.44 seconds
Started Aug 13 06:35:07 PM PDT 24
Finished Aug 13 06:35:36 PM PDT 24
Peak memory 215964 kb
Host smart-43b39c2e-c328-4111-8bb2-258f675606a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757
02904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1375702904
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.4218339725
Short name T3435
Test name
Test status
Simulation time 225704823 ps
CPU time 0.96 seconds
Started Aug 13 06:35:01 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 207616 kb
Host smart-100322c8-741c-49ba-af00-5301f84cb06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42183
39725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.4218339725
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.4007877756
Short name T1376
Test name
Test status
Simulation time 191975779 ps
CPU time 0.92 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 207496 kb
Host smart-90b5b067-167f-4a02-9f71-ef3823239610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40078
77756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.4007877756
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3516968682
Short name T1367
Test name
Test status
Simulation time 154770386 ps
CPU time 0.87 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 207496 kb
Host smart-ad31cea0-8720-4e5c-b5f6-9e65ddc339d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35169
68682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3516968682
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2278204764
Short name T2416
Test name
Test status
Simulation time 158091783 ps
CPU time 0.93 seconds
Started Aug 13 06:35:09 PM PDT 24
Finished Aug 13 06:35:10 PM PDT 24
Peak memory 207540 kb
Host smart-20c61b2b-e9f6-4e46-bde6-0afc409f6308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22782
04764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2278204764
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_resume_link_active.855078701
Short name T2609
Test name
Test status
Simulation time 20204711649 ps
CPU time 22.55 seconds
Started Aug 13 06:35:04 PM PDT 24
Finished Aug 13 06:35:27 PM PDT 24
Peak memory 207548 kb
Host smart-57a8915e-b468-4743-a14f-9b346d856ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85507
8701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.855078701
Directory /workspace/10.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1570302252
Short name T3425
Test name
Test status
Simulation time 134251758 ps
CPU time 0.84 seconds
Started Aug 13 06:35:01 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 207480 kb
Host smart-9ae1248b-50c9-4873-8768-f6e9f3246955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15703
02252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1570302252
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_rx_full.715050480
Short name T2780
Test name
Test status
Simulation time 344674117 ps
CPU time 1.22 seconds
Started Aug 13 06:35:01 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 207456 kb
Host smart-2a59164a-9618-4103-81f4-f4669b73262c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71505
0480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.715050480
Directory /workspace/10.usbdev_rx_full/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1374995497
Short name T1215
Test name
Test status
Simulation time 157434266 ps
CPU time 0.89 seconds
Started Aug 13 06:35:10 PM PDT 24
Finished Aug 13 06:35:11 PM PDT 24
Peak memory 207580 kb
Host smart-e25b7c9e-46df-47db-9527-21caa94ea80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13749
95497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1374995497
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1476006786
Short name T2844
Test name
Test status
Simulation time 199001217 ps
CPU time 0.91 seconds
Started Aug 13 06:35:06 PM PDT 24
Finished Aug 13 06:35:07 PM PDT 24
Peak memory 207504 kb
Host smart-3b783ba8-6c6f-4855-8423-d7a3cde16a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14760
06786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1476006786
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3286695806
Short name T1576
Test name
Test status
Simulation time 208537610 ps
CPU time 1.14 seconds
Started Aug 13 06:35:07 PM PDT 24
Finished Aug 13 06:35:09 PM PDT 24
Peak memory 207488 kb
Host smart-0b0f5f65-56db-4ae9-a8b5-1e22cc3ede70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32866
95806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3286695806
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3842631984
Short name T1511
Test name
Test status
Simulation time 2881587513 ps
CPU time 85.36 seconds
Started Aug 13 06:35:01 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 224008 kb
Host smart-f61c1b1b-d687-41ad-8896-5536951d2775
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3842631984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3842631984
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.4022529088
Short name T917
Test name
Test status
Simulation time 171142048 ps
CPU time 0.92 seconds
Started Aug 13 06:35:09 PM PDT 24
Finished Aug 13 06:35:10 PM PDT 24
Peak memory 207532 kb
Host smart-cd3d0bba-07f9-4727-8ec6-24e174d5b6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40225
29088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.4022529088
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.603466707
Short name T2888
Test name
Test status
Simulation time 182477126 ps
CPU time 0.89 seconds
Started Aug 13 06:35:08 PM PDT 24
Finished Aug 13 06:35:09 PM PDT 24
Peak memory 207536 kb
Host smart-e8317caf-11d4-422a-97a7-8b978def561d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60346
6707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.603466707
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.1244094173
Short name T1659
Test name
Test status
Simulation time 791098477 ps
CPU time 1.93 seconds
Started Aug 13 06:35:03 PM PDT 24
Finished Aug 13 06:35:05 PM PDT 24
Peak memory 207568 kb
Host smart-e63f347b-05ce-4b81-9b31-cd351b35a192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12440
94173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1244094173
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.905127711
Short name T3189
Test name
Test status
Simulation time 3003379846 ps
CPU time 31.2 seconds
Started Aug 13 06:35:01 PM PDT 24
Finished Aug 13 06:35:33 PM PDT 24
Peak memory 217200 kb
Host smart-956df033-988d-491b-b190-6197272a7f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90512
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.905127711
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.3233215080
Short name T1430
Test name
Test status
Simulation time 7023282852 ps
CPU time 45.01 seconds
Started Aug 13 06:34:59 PM PDT 24
Finished Aug 13 06:35:44 PM PDT 24
Peak memory 207760 kb
Host smart-e6fe2879-01a2-4823-a679-c35f5671699a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233215080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.3233215080
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_tx_rx_disruption.1439626616
Short name T3398
Test name
Test status
Simulation time 573819619 ps
CPU time 1.67 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 207552 kb
Host smart-50a1e252-89d0-4e17-bf5e-342d04981336
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439626616 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.usbdev_tx_rx_disruption.1439626616
Directory /workspace/10.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/100.usbdev_tx_rx_disruption.2328950707
Short name T2293
Test name
Test status
Simulation time 526765047 ps
CPU time 1.62 seconds
Started Aug 13 06:41:12 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207612 kb
Host smart-21e03245-76aa-4db5-a4a2-27fa9f738bb9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328950707 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.usbdev_tx_rx_disruption.2328950707
Directory /workspace/100.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/101.usbdev_endpoint_types.2302221744
Short name T3123
Test name
Test status
Simulation time 239972798 ps
CPU time 1.05 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207580 kb
Host smart-7368cf50-d4ab-429d-ba8c-a7526ba1db53
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2302221744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.2302221744
Directory /workspace/101.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/102.usbdev_tx_rx_disruption.1448757176
Short name T2328
Test name
Test status
Simulation time 608479703 ps
CPU time 1.79 seconds
Started Aug 13 06:41:11 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 207596 kb
Host smart-e0594036-ff92-43b4-97d5-837c33728a3e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448757176 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.usbdev_tx_rx_disruption.1448757176
Directory /workspace/102.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/103.usbdev_endpoint_types.1285728748
Short name T440
Test name
Test status
Simulation time 286350482 ps
CPU time 1.1 seconds
Started Aug 13 06:41:14 PM PDT 24
Finished Aug 13 06:41:15 PM PDT 24
Peak memory 207540 kb
Host smart-3406080e-21da-4911-9281-e5a308d35dc2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1285728748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.1285728748
Directory /workspace/103.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/103.usbdev_tx_rx_disruption.2434330378
Short name T1731
Test name
Test status
Simulation time 514604404 ps
CPU time 1.56 seconds
Started Aug 13 06:41:27 PM PDT 24
Finished Aug 13 06:41:29 PM PDT 24
Peak memory 207596 kb
Host smart-afc88c76-7228-4cfd-a13b-54613320ed55
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434330378 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.usbdev_tx_rx_disruption.2434330378
Directory /workspace/103.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/104.usbdev_tx_rx_disruption.3749765981
Short name T182
Test name
Test status
Simulation time 490669534 ps
CPU time 1.58 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207540 kb
Host smart-aea110a1-8719-42c6-a64e-d1394834e3ae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749765981 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.usbdev_tx_rx_disruption.3749765981
Directory /workspace/104.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/105.usbdev_endpoint_types.2758307583
Short name T2187
Test name
Test status
Simulation time 185094168 ps
CPU time 0.97 seconds
Started Aug 13 06:41:11 PM PDT 24
Finished Aug 13 06:41:12 PM PDT 24
Peak memory 207576 kb
Host smart-c8300d72-7335-4138-88c7-0b5afb21930c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2758307583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.2758307583
Directory /workspace/105.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/105.usbdev_tx_rx_disruption.266053432
Short name T1095
Test name
Test status
Simulation time 625932164 ps
CPU time 1.7 seconds
Started Aug 13 06:41:09 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207616 kb
Host smart-4fc1be47-2af6-499e-aa0c-81df2b231b49
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266053432 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 105.usbdev_tx_rx_disruption.266053432
Directory /workspace/105.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/106.usbdev_tx_rx_disruption.2131680212
Short name T1052
Test name
Test status
Simulation time 451294194 ps
CPU time 1.35 seconds
Started Aug 13 06:41:10 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207596 kb
Host smart-76876cf6-41d7-495c-94b3-e1ebf3818725
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131680212 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.usbdev_tx_rx_disruption.2131680212
Directory /workspace/106.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/107.usbdev_tx_rx_disruption.449179596
Short name T3595
Test name
Test status
Simulation time 468865160 ps
CPU time 1.43 seconds
Started Aug 13 06:41:07 PM PDT 24
Finished Aug 13 06:41:09 PM PDT 24
Peak memory 207624 kb
Host smart-d0e224c4-2c4e-4f7e-ac3d-c3f2a3b811e6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449179596 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 107.usbdev_tx_rx_disruption.449179596
Directory /workspace/107.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/108.usbdev_endpoint_types.2725355742
Short name T452
Test name
Test status
Simulation time 422060163 ps
CPU time 1.25 seconds
Started Aug 13 06:41:08 PM PDT 24
Finished Aug 13 06:41:09 PM PDT 24
Peak memory 207520 kb
Host smart-11a511f1-ccb4-490b-862c-f34268235efd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2725355742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.2725355742
Directory /workspace/108.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/108.usbdev_tx_rx_disruption.3033096631
Short name T1100
Test name
Test status
Simulation time 524598152 ps
CPU time 1.67 seconds
Started Aug 13 06:41:11 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 207596 kb
Host smart-ee3a87fb-1b66-4236-9045-5a2b949fb405
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033096631 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.usbdev_tx_rx_disruption.3033096631
Directory /workspace/108.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/109.usbdev_tx_rx_disruption.3486152670
Short name T2102
Test name
Test status
Simulation time 651216764 ps
CPU time 1.63 seconds
Started Aug 13 06:41:07 PM PDT 24
Finished Aug 13 06:41:09 PM PDT 24
Peak memory 207504 kb
Host smart-ed70e384-2b45-40fb-99f3-3ffd787d85d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486152670 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.usbdev_tx_rx_disruption.3486152670
Directory /workspace/109.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.2504618167
Short name T3070
Test name
Test status
Simulation time 60157233 ps
CPU time 0.73 seconds
Started Aug 13 06:35:36 PM PDT 24
Finished Aug 13 06:35:37 PM PDT 24
Peak memory 207500 kb
Host smart-71ec5568-747c-43d0-b739-fa728b131d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2504618167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.2504618167
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.4190968138
Short name T1271
Test name
Test status
Simulation time 4474251554 ps
CPU time 6.87 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:09 PM PDT 24
Peak memory 215972 kb
Host smart-d8cf45d3-c5f0-45f4-a2fe-149419de62e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190968138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.4190968138
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.809843052
Short name T783
Test name
Test status
Simulation time 13425736569 ps
CPU time 16.93 seconds
Started Aug 13 06:35:01 PM PDT 24
Finished Aug 13 06:35:18 PM PDT 24
Peak memory 215992 kb
Host smart-3946994b-a0b6-4ba4-8e65-6edb1da1ab4f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=809843052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.809843052
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.4288276445
Short name T3019
Test name
Test status
Simulation time 23442437981 ps
CPU time 31.01 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:35:31 PM PDT 24
Peak memory 216052 kb
Host smart-a64ca7b3-b04b-4896-8536-d7c5faf8687d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288276445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.4288276445
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.744964013
Short name T1442
Test name
Test status
Simulation time 163984672 ps
CPU time 0.86 seconds
Started Aug 13 06:35:05 PM PDT 24
Finished Aug 13 06:35:06 PM PDT 24
Peak memory 207456 kb
Host smart-29466271-ef56-432e-bb5f-2113f4e7c706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74496
4013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.744964013
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3417945491
Short name T1107
Test name
Test status
Simulation time 155916597 ps
CPU time 0.86 seconds
Started Aug 13 06:35:09 PM PDT 24
Finished Aug 13 06:35:10 PM PDT 24
Peak memory 207612 kb
Host smart-f281ce31-e785-4344-a4b5-36d9dd8cad13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34179
45491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3417945491
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.4005368464
Short name T1505
Test name
Test status
Simulation time 226855550 ps
CPU time 1.02 seconds
Started Aug 13 06:35:10 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207540 kb
Host smart-1edc9f35-07ff-4d28-8480-adefab407d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40053
68464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.4005368464
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.38684222
Short name T2405
Test name
Test status
Simulation time 995761452 ps
CPU time 2.64 seconds
Started Aug 13 06:35:08 PM PDT 24
Finished Aug 13 06:35:11 PM PDT 24
Peak memory 207844 kb
Host smart-63e0502f-7e76-427d-b499-8815c06a73f9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=38684222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.38684222
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2535175369
Short name T3597
Test name
Test status
Simulation time 47884622291 ps
CPU time 79.92 seconds
Started Aug 13 06:35:16 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207776 kb
Host smart-d2c5ff3e-f33b-46b4-97c4-f687394816e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25351
75369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2535175369
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.4292638516
Short name T2223
Test name
Test status
Simulation time 179961684 ps
CPU time 0.9 seconds
Started Aug 13 06:35:10 PM PDT 24
Finished Aug 13 06:35:11 PM PDT 24
Peak memory 207540 kb
Host smart-b6cee744-671d-4b0c-9f4a-be339b9e4a71
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292638516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.4292638516
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.3030733441
Short name T2241
Test name
Test status
Simulation time 866564033 ps
CPU time 1.91 seconds
Started Aug 13 06:35:08 PM PDT 24
Finished Aug 13 06:35:10 PM PDT 24
Peak memory 207560 kb
Host smart-dcb7a122-7c0f-4cbc-acd1-7ecb7e13722e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30307
33441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.3030733441
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2747222941
Short name T3313
Test name
Test status
Simulation time 149044847 ps
CPU time 0.87 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207580 kb
Host smart-ed0ed2c7-407c-4000-bd82-ab451293cadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27472
22941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2747222941
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1015773524
Short name T2296
Test name
Test status
Simulation time 35635172 ps
CPU time 0.71 seconds
Started Aug 13 06:35:09 PM PDT 24
Finished Aug 13 06:35:10 PM PDT 24
Peak memory 207496 kb
Host smart-79260d29-10f1-49a5-94df-49b72063dfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157
73524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1015773524
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2624067725
Short name T2364
Test name
Test status
Simulation time 891119930 ps
CPU time 2.52 seconds
Started Aug 13 06:35:10 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207720 kb
Host smart-95b03a19-1f6d-472e-95ff-e8537080115e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26240
67725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2624067725
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_types.570476884
Short name T489
Test name
Test status
Simulation time 307841794 ps
CPU time 1.16 seconds
Started Aug 13 06:35:08 PM PDT 24
Finished Aug 13 06:35:10 PM PDT 24
Peak memory 207552 kb
Host smart-c7351d5b-eeb4-40eb-8cb2-4c73b77f818b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=570476884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.570476884
Directory /workspace/11.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3399699590
Short name T1841
Test name
Test status
Simulation time 437952144 ps
CPU time 2.91 seconds
Started Aug 13 06:35:12 PM PDT 24
Finished Aug 13 06:35:16 PM PDT 24
Peak memory 207592 kb
Host smart-f833e7c6-9a00-4286-900e-7df30c23363e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33996
99590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3399699590
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1403249249
Short name T2728
Test name
Test status
Simulation time 241064748 ps
CPU time 1.04 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 215824 kb
Host smart-00eef9e7-a001-40e0-9b1a-d43c6a14e8b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1403249249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1403249249
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.113353597
Short name T3199
Test name
Test status
Simulation time 166243500 ps
CPU time 0.91 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207496 kb
Host smart-5a46aef1-3f12-4ef6-9969-7fd4e3a78ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11335
3597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.113353597
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1688370731
Short name T3269
Test name
Test status
Simulation time 247299916 ps
CPU time 1.05 seconds
Started Aug 13 06:35:12 PM PDT 24
Finished Aug 13 06:35:13 PM PDT 24
Peak memory 207500 kb
Host smart-b83db965-bd09-4401-a473-72e818239e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16883
70731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1688370731
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.2230432755
Short name T2538
Test name
Test status
Simulation time 3334582338 ps
CPU time 97.19 seconds
Started Aug 13 06:35:10 PM PDT 24
Finished Aug 13 06:36:48 PM PDT 24
Peak memory 218500 kb
Host smart-b0c14148-62c5-4080-9aae-04bbd35aee6e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2230432755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.2230432755
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.2864476766
Short name T795
Test name
Test status
Simulation time 13200265228 ps
CPU time 170.98 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:38:02 PM PDT 24
Peak memory 207848 kb
Host smart-3eb0839d-7326-4e3f-a6b4-038101dd0d1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2864476766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.2864476766
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.2987224101
Short name T2140
Test name
Test status
Simulation time 227191199 ps
CPU time 1.08 seconds
Started Aug 13 06:35:18 PM PDT 24
Finished Aug 13 06:35:19 PM PDT 24
Peak memory 207552 kb
Host smart-a3706b70-7d90-4a02-92f3-6fc0089cb5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29872
24101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.2987224101
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1867799903
Short name T2964
Test name
Test status
Simulation time 11749712319 ps
CPU time 16.05 seconds
Started Aug 13 06:35:12 PM PDT 24
Finished Aug 13 06:35:28 PM PDT 24
Peak memory 207724 kb
Host smart-ddce6526-7718-4f28-a800-e1ed0593399d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18677
99903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1867799903
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1251034688
Short name T1980
Test name
Test status
Simulation time 10894115291 ps
CPU time 16.67 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:35:27 PM PDT 24
Peak memory 207848 kb
Host smart-649990f2-7e30-458f-af43-ee3b207d8541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12510
34688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1251034688
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2807171008
Short name T1947
Test name
Test status
Simulation time 4544284865 ps
CPU time 44.91 seconds
Started Aug 13 06:35:10 PM PDT 24
Finished Aug 13 06:35:55 PM PDT 24
Peak memory 215920 kb
Host smart-65f99b2d-6f49-47ba-96d2-7541e29eb572
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2807171008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2807171008
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.246065625
Short name T3324
Test name
Test status
Simulation time 4402671417 ps
CPU time 130.4 seconds
Started Aug 13 06:35:12 PM PDT 24
Finished Aug 13 06:37:22 PM PDT 24
Peak memory 215936 kb
Host smart-e53075e9-1f06-4f52-8b61-af3943a6d878
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=246065625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.246065625
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.3158656113
Short name T1447
Test name
Test status
Simulation time 235490169 ps
CPU time 0.99 seconds
Started Aug 13 06:35:14 PM PDT 24
Finished Aug 13 06:35:15 PM PDT 24
Peak memory 207528 kb
Host smart-2e917999-370f-4c79-8382-e9434d954078
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3158656113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.3158656113
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2516634472
Short name T1011
Test name
Test status
Simulation time 195185951 ps
CPU time 1.03 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:35:13 PM PDT 24
Peak memory 207520 kb
Host smart-f0961fed-42bd-452d-ad5a-d822d435d976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25166
34472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2516634472
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.2974954049
Short name T831
Test name
Test status
Simulation time 1620804132 ps
CPU time 50.95 seconds
Started Aug 13 06:35:08 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 215796 kb
Host smart-097aff6f-be67-4401-b24e-a52d64c83e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
54049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.2974954049
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1802602850
Short name T2192
Test name
Test status
Simulation time 2871747253 ps
CPU time 30.81 seconds
Started Aug 13 06:35:12 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 218532 kb
Host smart-6677a029-c19e-46ec-9ae6-fc76135176aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1802602850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1802602850
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.380330578
Short name T1531
Test name
Test status
Simulation time 2202547644 ps
CPU time 17.01 seconds
Started Aug 13 06:35:12 PM PDT 24
Finished Aug 13 06:35:29 PM PDT 24
Peak memory 215984 kb
Host smart-b1c5ffed-863b-4247-a19f-b8f5d2c45936
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=380330578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.380330578
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.1492628218
Short name T1349
Test name
Test status
Simulation time 164891833 ps
CPU time 0.91 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207532 kb
Host smart-b84970da-6514-45aa-9cab-1ab16e2e1296
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1492628218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.1492628218
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2341044610
Short name T1560
Test name
Test status
Simulation time 139826173 ps
CPU time 0.9 seconds
Started Aug 13 06:35:09 PM PDT 24
Finished Aug 13 06:35:10 PM PDT 24
Peak memory 207520 kb
Host smart-3a5ba298-7876-4a92-80f3-40181a775e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23410
44610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2341044610
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3265675659
Short name T2392
Test name
Test status
Simulation time 167522586 ps
CPU time 0.96 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207476 kb
Host smart-76041fc5-f39f-4f7f-b3d5-25451fea97f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32656
75659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3265675659
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1827855617
Short name T2535
Test name
Test status
Simulation time 149270379 ps
CPU time 0.87 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207476 kb
Host smart-125720df-6d11-4a54-9eda-53be16bd7fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18278
55617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1827855617
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1214763576
Short name T2670
Test name
Test status
Simulation time 163429003 ps
CPU time 0.93 seconds
Started Aug 13 06:35:10 PM PDT 24
Finished Aug 13 06:35:11 PM PDT 24
Peak memory 207568 kb
Host smart-7f9276fb-7d48-4c64-ac6e-8b2e8ad36bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12147
63576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1214763576
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2074469636
Short name T3553
Test name
Test status
Simulation time 153082678 ps
CPU time 0.89 seconds
Started Aug 13 06:35:12 PM PDT 24
Finished Aug 13 06:35:13 PM PDT 24
Peak memory 207516 kb
Host smart-46ab308a-e976-4a49-b685-61b41f32b9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20744
69636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2074469636
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1100261218
Short name T1057
Test name
Test status
Simulation time 283407479 ps
CPU time 1.11 seconds
Started Aug 13 06:35:12 PM PDT 24
Finished Aug 13 06:35:13 PM PDT 24
Peak memory 207576 kb
Host smart-f625ba67-5148-4f27-98ab-21e05f6fb81c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1100261218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1100261218
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.531715183
Short name T1671
Test name
Test status
Simulation time 154242954 ps
CPU time 0.87 seconds
Started Aug 13 06:35:10 PM PDT 24
Finished Aug 13 06:35:11 PM PDT 24
Peak memory 207464 kb
Host smart-b08e9cac-2bcf-45c5-87e5-7f916fe21d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53171
5183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.531715183
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.827540490
Short name T32
Test name
Test status
Simulation time 46061086 ps
CPU time 0.73 seconds
Started Aug 13 06:35:10 PM PDT 24
Finished Aug 13 06:35:11 PM PDT 24
Peak memory 207552 kb
Host smart-b35055c6-49e2-44a8-abc8-4aa78f72e9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82754
0490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.827540490
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4110444231
Short name T3188
Test name
Test status
Simulation time 9600251105 ps
CPU time 25.57 seconds
Started Aug 13 06:35:16 PM PDT 24
Finished Aug 13 06:35:42 PM PDT 24
Peak memory 215984 kb
Host smart-cd58e807-7a83-4f38-8a3a-be74ce9f1a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41104
44231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4110444231
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2183222747
Short name T1126
Test name
Test status
Simulation time 170000432 ps
CPU time 0.97 seconds
Started Aug 13 06:35:11 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207528 kb
Host smart-871e618b-76e4-4103-9097-4eba25f22d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21832
22747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2183222747
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3794074758
Short name T1007
Test name
Test status
Simulation time 176992218 ps
CPU time 0.9 seconds
Started Aug 13 06:35:07 PM PDT 24
Finished Aug 13 06:35:08 PM PDT 24
Peak memory 207500 kb
Host smart-2e61d1b2-2b94-4c8a-9ddc-512daea94015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37940
74758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3794074758
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2813249847
Short name T821
Test name
Test status
Simulation time 151940647 ps
CPU time 0.9 seconds
Started Aug 13 06:35:17 PM PDT 24
Finished Aug 13 06:35:18 PM PDT 24
Peak memory 207464 kb
Host smart-c015575a-ae12-4730-ad8e-aba26b093dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28132
49847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2813249847
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.389558322
Short name T894
Test name
Test status
Simulation time 191138801 ps
CPU time 0.94 seconds
Started Aug 13 06:35:09 PM PDT 24
Finished Aug 13 06:35:10 PM PDT 24
Peak memory 207544 kb
Host smart-fc6142ce-a256-4d35-941f-702c33b1f0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38955
8322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.389558322
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_resume_link_active.1391999629
Short name T1471
Test name
Test status
Simulation time 20203775420 ps
CPU time 25.07 seconds
Started Aug 13 06:35:13 PM PDT 24
Finished Aug 13 06:35:38 PM PDT 24
Peak memory 207556 kb
Host smart-9ef78161-ed05-4a29-b02f-807b9032f524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919
99629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.1391999629
Directory /workspace/11.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3757010049
Short name T2077
Test name
Test status
Simulation time 138506838 ps
CPU time 0.94 seconds
Started Aug 13 06:35:28 PM PDT 24
Finished Aug 13 06:35:29 PM PDT 24
Peak memory 207456 kb
Host smart-738ada52-e920-415b-bff4-0bc16fe76436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37570
10049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3757010049
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_rx_full.2787745922
Short name T1056
Test name
Test status
Simulation time 253747842 ps
CPU time 1.06 seconds
Started Aug 13 06:35:25 PM PDT 24
Finished Aug 13 06:35:26 PM PDT 24
Peak memory 207456 kb
Host smart-df815ec9-1975-4dd1-b51c-d0161062407b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
45922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.2787745922
Directory /workspace/11.usbdev_rx_full/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3798534545
Short name T1091
Test name
Test status
Simulation time 160031458 ps
CPU time 0.86 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:20 PM PDT 24
Peak memory 207488 kb
Host smart-c46b5a06-a377-4434-bbfd-e3c7e3d3c3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37985
34545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3798534545
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3158691460
Short name T2474
Test name
Test status
Simulation time 150209506 ps
CPU time 0.86 seconds
Started Aug 13 06:35:25 PM PDT 24
Finished Aug 13 06:35:26 PM PDT 24
Peak memory 207524 kb
Host smart-82e856ff-9ab4-4ea5-9f0d-3053399e4628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31586
91460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3158691460
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1454478794
Short name T1979
Test name
Test status
Simulation time 206325988 ps
CPU time 0.99 seconds
Started Aug 13 06:35:18 PM PDT 24
Finished Aug 13 06:35:19 PM PDT 24
Peak memory 207504 kb
Host smart-c47bfd1e-7f5e-4598-912c-33e63040dc55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14544
78794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1454478794
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.4009989186
Short name T2355
Test name
Test status
Simulation time 2267994273 ps
CPU time 17.38 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:38 PM PDT 24
Peak memory 224068 kb
Host smart-12360b60-c132-4ab2-85d2-bce605c55c67
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4009989186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.4009989186
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1118610715
Short name T500
Test name
Test status
Simulation time 225860851 ps
CPU time 0.95 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:21 PM PDT 24
Peak memory 207536 kb
Host smart-32f36c29-e0da-4f4c-841f-87705975c9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11186
10715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1118610715
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.563077175
Short name T1789
Test name
Test status
Simulation time 200819526 ps
CPU time 0.93 seconds
Started Aug 13 06:35:17 PM PDT 24
Finished Aug 13 06:35:18 PM PDT 24
Peak memory 207408 kb
Host smart-8c7fb3a9-3c83-4e00-a3b6-5b38869658f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56307
7175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.563077175
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.2739542559
Short name T2636
Test name
Test status
Simulation time 1026255803 ps
CPU time 2.44 seconds
Started Aug 13 06:35:21 PM PDT 24
Finished Aug 13 06:35:24 PM PDT 24
Peak memory 207752 kb
Host smart-ff2f925d-b727-425e-a184-bd0880347759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27395
42559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.2739542559
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1817670497
Short name T1278
Test name
Test status
Simulation time 2297081445 ps
CPU time 66.7 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 216048 kb
Host smart-0eca0781-96a6-4e13-a1cf-2894a29e5cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18176
70497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1817670497
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.2705514068
Short name T3162
Test name
Test status
Simulation time 4992252716 ps
CPU time 34.1 seconds
Started Aug 13 06:35:09 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207728 kb
Host smart-31ee6e38-c8d0-4890-b87d-881301b00111
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705514068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.2705514068
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_tx_rx_disruption.1587756560
Short name T2018
Test name
Test status
Simulation time 527070929 ps
CPU time 1.56 seconds
Started Aug 13 06:35:29 PM PDT 24
Finished Aug 13 06:35:30 PM PDT 24
Peak memory 207604 kb
Host smart-15659313-5378-465d-b8a9-0d298af7ce80
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587756560 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.usbdev_tx_rx_disruption.1587756560
Directory /workspace/11.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/110.usbdev_endpoint_types.1134922237
Short name T2906
Test name
Test status
Simulation time 790888469 ps
CPU time 1.82 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207572 kb
Host smart-340741f1-d2a6-43a5-94f7-caa5a631e569
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1134922237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.1134922237
Directory /workspace/110.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/110.usbdev_tx_rx_disruption.162684607
Short name T860
Test name
Test status
Simulation time 586408680 ps
CPU time 1.69 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207560 kb
Host smart-690e530b-4e88-44bf-b617-d944c19d4285
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162684607 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 110.usbdev_tx_rx_disruption.162684607
Directory /workspace/110.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/111.usbdev_endpoint_types.212866294
Short name T20
Test name
Test status
Simulation time 673726904 ps
CPU time 1.59 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207520 kb
Host smart-cd3c19cc-3a14-4877-9826-aa29f616da9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=212866294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.212866294
Directory /workspace/111.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/111.usbdev_tx_rx_disruption.1713407377
Short name T1971
Test name
Test status
Simulation time 593372076 ps
CPU time 1.62 seconds
Started Aug 13 06:41:30 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 207620 kb
Host smart-416d4927-18a1-4254-8327-3f7bbc68c54b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713407377 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.usbdev_tx_rx_disruption.1713407377
Directory /workspace/111.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/112.usbdev_tx_rx_disruption.1148402317
Short name T1418
Test name
Test status
Simulation time 457920382 ps
CPU time 1.59 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207536 kb
Host smart-ff4bf426-515c-445c-88ee-6356fb93d299
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148402317 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.usbdev_tx_rx_disruption.1148402317
Directory /workspace/112.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/113.usbdev_tx_rx_disruption.1644639975
Short name T174
Test name
Test status
Simulation time 502296994 ps
CPU time 1.51 seconds
Started Aug 13 06:41:17 PM PDT 24
Finished Aug 13 06:41:18 PM PDT 24
Peak memory 207612 kb
Host smart-fcf94c5f-b4fe-4fe3-ac8b-029b459ec9b7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644639975 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.usbdev_tx_rx_disruption.1644639975
Directory /workspace/113.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/114.usbdev_endpoint_types.3093494008
Short name T475
Test name
Test status
Simulation time 267258185 ps
CPU time 1.02 seconds
Started Aug 13 06:41:07 PM PDT 24
Finished Aug 13 06:41:08 PM PDT 24
Peak memory 207480 kb
Host smart-06cbfaab-3b70-4f20-8a2c-dc42943e17f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3093494008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.3093494008
Directory /workspace/114.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/114.usbdev_tx_rx_disruption.3942817998
Short name T191
Test name
Test status
Simulation time 666978358 ps
CPU time 1.7 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207588 kb
Host smart-9ead1e2a-fdb3-4013-9ac9-3c97edcc5a9e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942817998 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.usbdev_tx_rx_disruption.3942817998
Directory /workspace/114.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/115.usbdev_endpoint_types.593575545
Short name T488
Test name
Test status
Simulation time 266481642 ps
CPU time 0.99 seconds
Started Aug 13 06:41:10 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207572 kb
Host smart-454c6609-8d15-4d66-b1f0-8b3374bf8391
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=593575545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.593575545
Directory /workspace/115.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/115.usbdev_tx_rx_disruption.2623814395
Short name T2761
Test name
Test status
Simulation time 426493043 ps
CPU time 1.36 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207612 kb
Host smart-8a557780-4d9b-4bac-8800-b64e21e77b13
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623814395 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.usbdev_tx_rx_disruption.2623814395
Directory /workspace/115.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/116.usbdev_endpoint_types.1977917825
Short name T502
Test name
Test status
Simulation time 269547749 ps
CPU time 1.11 seconds
Started Aug 13 06:41:13 PM PDT 24
Finished Aug 13 06:41:15 PM PDT 24
Peak memory 207576 kb
Host smart-ce57b891-bc29-4372-bc96-fe47619abdcb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1977917825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.1977917825
Directory /workspace/116.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/116.usbdev_tx_rx_disruption.3583729122
Short name T1403
Test name
Test status
Simulation time 488932085 ps
CPU time 1.4 seconds
Started Aug 13 06:41:09 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207588 kb
Host smart-59fa0b26-3dda-4d2e-b75c-e4dbc13bf44a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583729122 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.usbdev_tx_rx_disruption.3583729122
Directory /workspace/116.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/117.usbdev_endpoint_types.18494734
Short name T469
Test name
Test status
Simulation time 288917984 ps
CPU time 1.08 seconds
Started Aug 13 06:41:06 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207560 kb
Host smart-cf36b60c-7da2-4211-a66f-8b60827124d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=18494734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.18494734
Directory /workspace/117.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/117.usbdev_tx_rx_disruption.4036425676
Short name T2954
Test name
Test status
Simulation time 630496365 ps
CPU time 1.75 seconds
Started Aug 13 06:41:13 PM PDT 24
Finished Aug 13 06:41:15 PM PDT 24
Peak memory 207576 kb
Host smart-d471e84a-877c-4603-958a-58af5a3b7323
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036425676 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.usbdev_tx_rx_disruption.4036425676
Directory /workspace/117.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/118.usbdev_tx_rx_disruption.861515028
Short name T3224
Test name
Test status
Simulation time 582555050 ps
CPU time 1.73 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207620 kb
Host smart-caac1c36-5404-4830-beb4-80d992ad23e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861515028 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 118.usbdev_tx_rx_disruption.861515028
Directory /workspace/118.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/119.usbdev_tx_rx_disruption.2557993131
Short name T3511
Test name
Test status
Simulation time 461425132 ps
CPU time 1.47 seconds
Started Aug 13 06:41:12 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207612 kb
Host smart-203f7fbb-e7a2-4e98-b5f0-0560a52cfdea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557993131 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.usbdev_tx_rx_disruption.2557993131
Directory /workspace/119.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.2495360504
Short name T1171
Test name
Test status
Simulation time 41783507 ps
CPU time 0.67 seconds
Started Aug 13 06:35:32 PM PDT 24
Finished Aug 13 06:35:33 PM PDT 24
Peak memory 207480 kb
Host smart-220ae590-1073-4d5f-9502-7fcd55e5e68b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2495360504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2495360504
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.335771256
Short name T2321
Test name
Test status
Simulation time 10184761298 ps
CPU time 13.31 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207808 kb
Host smart-d8085dc4-ab5b-4bc0-be94-24a2c74e8764
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335771256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_disconnect.335771256
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3591341076
Short name T2577
Test name
Test status
Simulation time 14967031243 ps
CPU time 18.27 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:39 PM PDT 24
Peak memory 215924 kb
Host smart-d6baed32-583d-4124-a3be-02bec2369fe9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591341076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3591341076
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.3988049089
Short name T8
Test name
Test status
Simulation time 25328130821 ps
CPU time 29.08 seconds
Started Aug 13 06:35:23 PM PDT 24
Finished Aug 13 06:35:52 PM PDT 24
Peak memory 215968 kb
Host smart-6b752112-8661-4db4-b4a9-e4facda7a005
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988049089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.3988049089
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2154413112
Short name T3604
Test name
Test status
Simulation time 155791537 ps
CPU time 0.86 seconds
Started Aug 13 06:35:21 PM PDT 24
Finished Aug 13 06:35:22 PM PDT 24
Peak memory 207428 kb
Host smart-eaccb1dc-95b9-427c-9ad2-dd7f94282576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21544
13112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2154413112
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3614785820
Short name T851
Test name
Test status
Simulation time 143144962 ps
CPU time 0.85 seconds
Started Aug 13 06:35:22 PM PDT 24
Finished Aug 13 06:35:23 PM PDT 24
Peak memory 207540 kb
Host smart-95c9775b-da33-4b79-89db-8e2d80ce3363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36147
85820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3614785820
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.4175653246
Short name T727
Test name
Test status
Simulation time 348656392 ps
CPU time 1.35 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:20 PM PDT 24
Peak memory 207504 kb
Host smart-1609943a-3534-4dbf-968d-bccfd6a6cda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41756
53246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.4175653246
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2640877042
Short name T347
Test name
Test status
Simulation time 954489217 ps
CPU time 2.57 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:23 PM PDT 24
Peak memory 207728 kb
Host smart-dacfe975-5ca2-4a45-a764-e5d0c58556fe
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2640877042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2640877042
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.2590150461
Short name T1252
Test name
Test status
Simulation time 38959962297 ps
CPU time 66.19 seconds
Started Aug 13 06:35:26 PM PDT 24
Finished Aug 13 06:36:33 PM PDT 24
Peak memory 207828 kb
Host smart-374270a4-52c9-41c4-b0d8-4d532c698e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25901
50461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2590150461
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.367153521
Short name T1587
Test name
Test status
Simulation time 4346985002 ps
CPU time 39.45 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 207672 kb
Host smart-11c6c362-bd8a-456c-9934-2f06bb7533a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367153521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.367153521
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.4085164098
Short name T359
Test name
Test status
Simulation time 428932512 ps
CPU time 1.26 seconds
Started Aug 13 06:35:26 PM PDT 24
Finished Aug 13 06:35:27 PM PDT 24
Peak memory 207496 kb
Host smart-8d2757ae-4d3f-4848-82b5-05303068c0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40851
64098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.4085164098
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.14514549
Short name T1566
Test name
Test status
Simulation time 145485099 ps
CPU time 0.87 seconds
Started Aug 13 06:35:27 PM PDT 24
Finished Aug 13 06:35:29 PM PDT 24
Peak memory 207500 kb
Host smart-032fa6d9-9e20-4853-ab9d-ecb31de4f850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14514
549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.14514549
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2995025217
Short name T2545
Test name
Test status
Simulation time 51367097 ps
CPU time 0.74 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:35:31 PM PDT 24
Peak memory 207460 kb
Host smart-d7769261-eb7f-4217-be31-52d1dac8c171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29950
25217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2995025217
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3227406372
Short name T2169
Test name
Test status
Simulation time 914631045 ps
CPU time 2.45 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:22 PM PDT 24
Peak memory 207812 kb
Host smart-9cd54379-f43b-4f02-bb75-4cb6f9d120ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32274
06372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3227406372
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_types.3056973174
Short name T461
Test name
Test status
Simulation time 325918655 ps
CPU time 1.17 seconds
Started Aug 13 06:35:30 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207520 kb
Host smart-8117efca-63e1-4d34-a3ad-81069b5d4268
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3056973174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.3056973174
Directory /workspace/12.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.4088438818
Short name T2233
Test name
Test status
Simulation time 257751394 ps
CPU time 1.85 seconds
Started Aug 13 06:35:23 PM PDT 24
Finished Aug 13 06:35:25 PM PDT 24
Peak memory 207656 kb
Host smart-23c386e6-3589-41c8-b4ef-57dab3c8c01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40884
38818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.4088438818
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1866263363
Short name T2874
Test name
Test status
Simulation time 178231198 ps
CPU time 1.04 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:20 PM PDT 24
Peak memory 207496 kb
Host smart-2d8fe0b7-9c02-489c-8c35-3555815ffe2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1866263363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1866263363
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1587249217
Short name T2669
Test name
Test status
Simulation time 177375838 ps
CPU time 0.87 seconds
Started Aug 13 06:35:29 PM PDT 24
Finished Aug 13 06:35:30 PM PDT 24
Peak memory 207044 kb
Host smart-48c813cc-3d6f-4e10-9969-b630ed9ff63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15872
49217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1587249217
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.935982633
Short name T2071
Test name
Test status
Simulation time 155465755 ps
CPU time 0.93 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:21 PM PDT 24
Peak memory 207504 kb
Host smart-1481ed24-ab03-410f-848f-72040afe6b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93598
2633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.935982633
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.156498828
Short name T2506
Test name
Test status
Simulation time 3991909300 ps
CPU time 39.67 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:36:13 PM PDT 24
Peak memory 218672 kb
Host smart-912a5f6a-52de-4ae5-a952-ec5861ab8439
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=156498828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.156498828
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.2687402194
Short name T1098
Test name
Test status
Simulation time 10560603770 ps
CPU time 67.83 seconds
Started Aug 13 06:35:23 PM PDT 24
Finished Aug 13 06:36:31 PM PDT 24
Peak memory 207780 kb
Host smart-8ef8a5f1-183c-4ea1-b45d-b9fcf229d191
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2687402194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2687402194
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1591342482
Short name T3245
Test name
Test status
Simulation time 209831883 ps
CPU time 0.95 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:20 PM PDT 24
Peak memory 207596 kb
Host smart-e28d4306-e439-4690-9e32-8701d7b14279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15913
42482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1591342482
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.4149550274
Short name T1554
Test name
Test status
Simulation time 15034885663 ps
CPU time 19.85 seconds
Started Aug 13 06:35:30 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 207808 kb
Host smart-d3ba3d3c-f933-439b-bd38-9f9d0c6d300b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41495
50274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.4149550274
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1260134327
Short name T818
Test name
Test status
Simulation time 5573026816 ps
CPU time 165.11 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 218612 kb
Host smart-37deb88f-1dc3-4359-add1-4fb1724cb2a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1260134327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1260134327
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.87725338
Short name T826
Test name
Test status
Simulation time 1819499307 ps
CPU time 13.46 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:34 PM PDT 24
Peak memory 207688 kb
Host smart-2db22655-46c3-4362-b1df-948929233d17
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=87725338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.87725338
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.1479811094
Short name T1607
Test name
Test status
Simulation time 233160024 ps
CPU time 1 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:21 PM PDT 24
Peak memory 207528 kb
Host smart-fdbff282-8c82-4ca4-9083-791306475ceb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1479811094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.1479811094
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2535605556
Short name T1249
Test name
Test status
Simulation time 235991759 ps
CPU time 1 seconds
Started Aug 13 06:35:22 PM PDT 24
Finished Aug 13 06:35:23 PM PDT 24
Peak memory 207508 kb
Host smart-b141f4dd-4026-4dc1-8647-9f453bdd592e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25356
05556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2535605556
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.1178853644
Short name T2264
Test name
Test status
Simulation time 1812149824 ps
CPU time 53.41 seconds
Started Aug 13 06:35:22 PM PDT 24
Finished Aug 13 06:36:15 PM PDT 24
Peak memory 217368 kb
Host smart-f93a3f31-30ba-4fb5-9114-f5dc83d3acf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11788
53644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.1178853644
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.4056384187
Short name T2060
Test name
Test status
Simulation time 2945299742 ps
CPU time 25.17 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:46 PM PDT 24
Peak memory 218920 kb
Host smart-efdefce2-51c0-4e6b-b742-e28bde6cd517
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4056384187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.4056384187
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1445548514
Short name T749
Test name
Test status
Simulation time 2512108312 ps
CPU time 24.18 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 217724 kb
Host smart-a00c9067-5733-47a2-a9f0-cd149afe3d34
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1445548514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1445548514
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.1857919251
Short name T1313
Test name
Test status
Simulation time 159544274 ps
CPU time 0.9 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:20 PM PDT 24
Peak memory 207468 kb
Host smart-add11c52-cbee-4f6b-a9d4-c11cc5a15c6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1857919251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.1857919251
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3446758241
Short name T1455
Test name
Test status
Simulation time 145259953 ps
CPU time 0.83 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:20 PM PDT 24
Peak memory 207456 kb
Host smart-08f91e58-9fe3-4d3d-a40c-02685000da2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34467
58241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3446758241
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.1333873342
Short name T3581
Test name
Test status
Simulation time 167758930 ps
CPU time 0.95 seconds
Started Aug 13 06:35:20 PM PDT 24
Finished Aug 13 06:35:21 PM PDT 24
Peak memory 207512 kb
Host smart-8380e514-de49-479f-9d39-ae3985ddfcfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13338
73342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.1333873342
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.399137749
Short name T2240
Test name
Test status
Simulation time 149877753 ps
CPU time 0.85 seconds
Started Aug 13 06:35:19 PM PDT 24
Finished Aug 13 06:35:20 PM PDT 24
Peak memory 207516 kb
Host smart-86df93e7-87d0-46fa-a3f8-b179f97bb911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39913
7749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.399137749
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.844344136
Short name T3374
Test name
Test status
Simulation time 206656548 ps
CPU time 0.98 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207524 kb
Host smart-96852e4d-c7fa-42a1-bce3-36ee0dd9ec8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84434
4136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.844344136
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.4088663631
Short name T1411
Test name
Test status
Simulation time 148703607 ps
CPU time 0.87 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207572 kb
Host smart-64d558f8-32cb-4403-afeb-711146def5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40886
63631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.4088663631
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2198036451
Short name T999
Test name
Test status
Simulation time 234118734 ps
CPU time 1.09 seconds
Started Aug 13 06:35:32 PM PDT 24
Finished Aug 13 06:35:33 PM PDT 24
Peak memory 207608 kb
Host smart-45d85a44-c6df-488c-9d1b-dd920b22759a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2198036451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2198036451
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1520466845
Short name T231
Test name
Test status
Simulation time 143573423 ps
CPU time 0.86 seconds
Started Aug 13 06:35:36 PM PDT 24
Finished Aug 13 06:35:37 PM PDT 24
Peak memory 207356 kb
Host smart-da10f5a3-02b6-4bdb-a1fa-03598d54fb55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15204
66845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1520466845
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3800634752
Short name T3080
Test name
Test status
Simulation time 43025584 ps
CPU time 0.72 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207476 kb
Host smart-8e4eefa9-c3d0-45f2-9d2e-d05c595f9ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38006
34752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3800634752
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2488253017
Short name T2441
Test name
Test status
Simulation time 9798428924 ps
CPU time 24.23 seconds
Started Aug 13 06:35:28 PM PDT 24
Finished Aug 13 06:35:53 PM PDT 24
Peak memory 215984 kb
Host smart-835c2868-52aa-446c-9ec9-580ffd797deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24882
53017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2488253017
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.4229546158
Short name T2212
Test name
Test status
Simulation time 197826998 ps
CPU time 1.03 seconds
Started Aug 13 06:35:36 PM PDT 24
Finished Aug 13 06:35:37 PM PDT 24
Peak memory 207564 kb
Host smart-0eaa52ea-4684-4e51-bff1-be8ec7a3961c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42295
46158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.4229546158
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2960175917
Short name T2682
Test name
Test status
Simulation time 194768310 ps
CPU time 0.89 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:35:42 PM PDT 24
Peak memory 207528 kb
Host smart-c7042586-13ed-4308-87aa-78598bde8700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29601
75917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2960175917
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1739910033
Short name T3051
Test name
Test status
Simulation time 231495155 ps
CPU time 1.01 seconds
Started Aug 13 06:35:37 PM PDT 24
Finished Aug 13 06:35:38 PM PDT 24
Peak memory 207536 kb
Host smart-a26912f1-0613-446c-9376-630984b3494c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17399
10033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1739910033
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1377818950
Short name T1534
Test name
Test status
Simulation time 198423382 ps
CPU time 0.97 seconds
Started Aug 13 06:35:40 PM PDT 24
Finished Aug 13 06:35:41 PM PDT 24
Peak memory 207532 kb
Host smart-381164a9-12a5-434e-aa54-b6f88bf387e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13778
18950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1377818950
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_resume_link_active.4148336306
Short name T100
Test name
Test status
Simulation time 20165934904 ps
CPU time 24.27 seconds
Started Aug 13 06:35:30 PM PDT 24
Finished Aug 13 06:35:55 PM PDT 24
Peak memory 207588 kb
Host smart-878d05c0-9ee5-4a0a-b5ed-59fc5236466d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41483
36306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.4148336306
Directory /workspace/12.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.600946875
Short name T1928
Test name
Test status
Simulation time 203466316 ps
CPU time 0.92 seconds
Started Aug 13 06:35:26 PM PDT 24
Finished Aug 13 06:35:27 PM PDT 24
Peak memory 207508 kb
Host smart-b354dab9-78f0-4b23-a611-fa039f5a690f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60094
6875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.600946875
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_rx_full.2942673931
Short name T325
Test name
Test status
Simulation time 250874438 ps
CPU time 1.14 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207440 kb
Host smart-d55923b2-c74f-46d3-8adf-f52e8ad710ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29426
73931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.2942673931
Directory /workspace/12.usbdev_rx_full/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.1646742240
Short name T2358
Test name
Test status
Simulation time 150777337 ps
CPU time 0.84 seconds
Started Aug 13 06:35:30 PM PDT 24
Finished Aug 13 06:35:31 PM PDT 24
Peak memory 207556 kb
Host smart-69536173-b8aa-4429-9256-2aac9a2f72d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16467
42240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1646742240
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3025019359
Short name T1653
Test name
Test status
Simulation time 154913662 ps
CPU time 0.84 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207488 kb
Host smart-9fd41b42-1cc0-4af5-a631-c90f1174141d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30250
19359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3025019359
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.102611547
Short name T3559
Test name
Test status
Simulation time 231942106 ps
CPU time 1 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207436 kb
Host smart-b398326f-f562-4cad-8838-81c9741518fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10261
1547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.102611547
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.622044064
Short name T640
Test name
Test status
Simulation time 2408181511 ps
CPU time 23.85 seconds
Started Aug 13 06:35:38 PM PDT 24
Finished Aug 13 06:36:02 PM PDT 24
Peak memory 224080 kb
Host smart-5b57b3bd-5964-4b6a-9c9c-b5777e3e7eb6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=622044064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.622044064
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2770854467
Short name T1819
Test name
Test status
Simulation time 184038613 ps
CPU time 0.96 seconds
Started Aug 13 06:35:32 PM PDT 24
Finished Aug 13 06:35:33 PM PDT 24
Peak memory 207468 kb
Host smart-a034baed-5288-4d78-a974-845dea6def13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27708
54467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2770854467
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2755977641
Short name T2957
Test name
Test status
Simulation time 172116366 ps
CPU time 0.9 seconds
Started Aug 13 06:35:28 PM PDT 24
Finished Aug 13 06:35:29 PM PDT 24
Peak memory 207556 kb
Host smart-27735493-0c18-4a17-b129-6cfcf4764c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27559
77641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2755977641
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.2387782243
Short name T3434
Test name
Test status
Simulation time 858561661 ps
CPU time 2.25 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:35:35 PM PDT 24
Peak memory 207688 kb
Host smart-ea48677f-ae16-4613-9979-9d197627a81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23877
82243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.2387782243
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.408900603
Short name T3154
Test name
Test status
Simulation time 2483336428 ps
CPU time 73.55 seconds
Started Aug 13 06:35:30 PM PDT 24
Finished Aug 13 06:36:43 PM PDT 24
Peak memory 217400 kb
Host smart-462d63b7-8224-4b98-a932-fac0f78a6ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40890
0603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.408900603
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.3994762391
Short name T586
Test name
Test status
Simulation time 3606198706 ps
CPU time 24.82 seconds
Started Aug 13 06:35:21 PM PDT 24
Finished Aug 13 06:35:46 PM PDT 24
Peak memory 207712 kb
Host smart-aa23e0e0-199f-4092-b8c2-1f7e1b91dd45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994762391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.3994762391
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_tx_rx_disruption.3910481071
Short name T1237
Test name
Test status
Simulation time 469269795 ps
CPU time 1.47 seconds
Started Aug 13 06:35:29 PM PDT 24
Finished Aug 13 06:35:31 PM PDT 24
Peak memory 207604 kb
Host smart-473c85fe-f95e-41b2-a6cf-5c3ed2185b0a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910481071 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.usbdev_tx_rx_disruption.3910481071
Directory /workspace/12.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/120.usbdev_endpoint_types.2956254451
Short name T466
Test name
Test status
Simulation time 385593971 ps
CPU time 1.47 seconds
Started Aug 13 06:41:27 PM PDT 24
Finished Aug 13 06:41:29 PM PDT 24
Peak memory 207552 kb
Host smart-3024134b-1335-4854-b681-50399f0ec012
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2956254451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.2956254451
Directory /workspace/120.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/120.usbdev_tx_rx_disruption.3963772061
Short name T3194
Test name
Test status
Simulation time 636815556 ps
CPU time 1.79 seconds
Started Aug 13 06:41:12 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 207612 kb
Host smart-7f6b5143-73e4-449e-8036-090b8bb3baac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963772061 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.usbdev_tx_rx_disruption.3963772061
Directory /workspace/120.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/121.usbdev_tx_rx_disruption.30804805
Short name T877
Test name
Test status
Simulation time 452299997 ps
CPU time 1.54 seconds
Started Aug 13 06:41:28 PM PDT 24
Finished Aug 13 06:41:29 PM PDT 24
Peak memory 207612 kb
Host smart-d3d75b8e-c3a6-41b3-a081-d9700101d6fd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30804805 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 121.usbdev_tx_rx_disruption.30804805
Directory /workspace/121.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/122.usbdev_endpoint_types.1956887439
Short name T1750
Test name
Test status
Simulation time 151426515 ps
CPU time 0.87 seconds
Started Aug 13 06:41:12 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 207512 kb
Host smart-67c6271d-c775-456c-b7f6-66fe88f39cac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1956887439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.1956887439
Directory /workspace/122.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/122.usbdev_tx_rx_disruption.3706428801
Short name T3348
Test name
Test status
Simulation time 673951346 ps
CPU time 1.75 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207568 kb
Host smart-c40c1c97-8135-4862-bfe0-55be1f52b0f3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706428801 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.usbdev_tx_rx_disruption.3706428801
Directory /workspace/122.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/123.usbdev_tx_rx_disruption.1210146854
Short name T2809
Test name
Test status
Simulation time 591277038 ps
CPU time 1.52 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207584 kb
Host smart-beb04753-32e9-4ad1-a070-2a9245dba311
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210146854 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.usbdev_tx_rx_disruption.1210146854
Directory /workspace/123.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/124.usbdev_endpoint_types.2904292065
Short name T450
Test name
Test status
Simulation time 254858016 ps
CPU time 1.04 seconds
Started Aug 13 06:41:10 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207580 kb
Host smart-1bb35bc0-7fef-45f1-8129-ae9c9d80cbcf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2904292065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.2904292065
Directory /workspace/124.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/125.usbdev_endpoint_types.222472254
Short name T423
Test name
Test status
Simulation time 301668814 ps
CPU time 1.04 seconds
Started Aug 13 06:41:38 PM PDT 24
Finished Aug 13 06:41:39 PM PDT 24
Peak memory 207472 kb
Host smart-feb890b5-c049-4585-a2e5-af3d98d1b875
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=222472254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.222472254
Directory /workspace/125.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/125.usbdev_tx_rx_disruption.4223539032
Short name T3605
Test name
Test status
Simulation time 508077836 ps
CPU time 1.54 seconds
Started Aug 13 06:41:37 PM PDT 24
Finished Aug 13 06:41:39 PM PDT 24
Peak memory 207620 kb
Host smart-e57edf08-576f-40fb-9d8e-9188e0eb79b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223539032 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.usbdev_tx_rx_disruption.4223539032
Directory /workspace/125.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/127.usbdev_endpoint_types.688793689
Short name T372
Test name
Test status
Simulation time 584373433 ps
CPU time 1.51 seconds
Started Aug 13 06:41:16 PM PDT 24
Finished Aug 13 06:41:17 PM PDT 24
Peak memory 207540 kb
Host smart-9a8bf701-a47e-4b86-bee5-8849b220fb8b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=688793689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.688793689
Directory /workspace/127.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/127.usbdev_tx_rx_disruption.3424421995
Short name T1891
Test name
Test status
Simulation time 653685133 ps
CPU time 1.74 seconds
Started Aug 13 06:41:34 PM PDT 24
Finished Aug 13 06:41:36 PM PDT 24
Peak memory 207580 kb
Host smart-d8faaf7b-9b69-49c3-946a-0a9679e73acd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424421995 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.usbdev_tx_rx_disruption.3424421995
Directory /workspace/127.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/128.usbdev_endpoint_types.1052577623
Short name T3436
Test name
Test status
Simulation time 152376368 ps
CPU time 0.87 seconds
Started Aug 13 06:41:30 PM PDT 24
Finished Aug 13 06:41:30 PM PDT 24
Peak memory 207476 kb
Host smart-49b74260-dc59-4c3b-a5b2-a223d55324da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1052577623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.1052577623
Directory /workspace/128.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/128.usbdev_tx_rx_disruption.1792896352
Short name T1053
Test name
Test status
Simulation time 609173239 ps
CPU time 1.63 seconds
Started Aug 13 06:41:19 PM PDT 24
Finished Aug 13 06:41:21 PM PDT 24
Peak memory 207572 kb
Host smart-ec1a33b7-7c50-4cd8-ac13-edfed3080854
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792896352 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.usbdev_tx_rx_disruption.1792896352
Directory /workspace/128.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/129.usbdev_endpoint_types.2018410415
Short name T1803
Test name
Test status
Simulation time 181476093 ps
CPU time 0.98 seconds
Started Aug 13 06:41:38 PM PDT 24
Finished Aug 13 06:41:39 PM PDT 24
Peak memory 207568 kb
Host smart-fa3781b6-8862-45f5-ae05-6b04a20f1a75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2018410415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.2018410415
Directory /workspace/129.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/129.usbdev_tx_rx_disruption.854714805
Short name T1423
Test name
Test status
Simulation time 536379787 ps
CPU time 1.63 seconds
Started Aug 13 06:41:23 PM PDT 24
Finished Aug 13 06:41:25 PM PDT 24
Peak memory 207544 kb
Host smart-dc572a02-c27f-49b1-998e-7f1d27d54a5f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854714805 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 129.usbdev_tx_rx_disruption.854714805
Directory /workspace/129.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1191671446
Short name T2267
Test name
Test status
Simulation time 63393247 ps
CPU time 0.71 seconds
Started Aug 13 06:35:39 PM PDT 24
Finished Aug 13 06:35:40 PM PDT 24
Peak memory 207436 kb
Host smart-21451cfa-2599-453a-8f04-fe543d52e31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1191671446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1191671446
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.4270914584
Short name T2120
Test name
Test status
Simulation time 11137587138 ps
CPU time 15.85 seconds
Started Aug 13 06:35:32 PM PDT 24
Finished Aug 13 06:35:48 PM PDT 24
Peak memory 207812 kb
Host smart-51c2dc37-93ac-41f0-9472-36e4b7c8fcd4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270914584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.4270914584
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1563277306
Short name T2395
Test name
Test status
Simulation time 14490325119 ps
CPU time 19.93 seconds
Started Aug 13 06:35:30 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 216012 kb
Host smart-f53dfe32-4b8e-4097-a10d-3fb70a0b8b3d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563277306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1563277306
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2965694320
Short name T13
Test name
Test status
Simulation time 23614084864 ps
CPU time 28.87 seconds
Started Aug 13 06:35:28 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 215940 kb
Host smart-0f1009ec-b424-4547-9abf-c1c32387f4cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965694320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.2965694320
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.609495767
Short name T2689
Test name
Test status
Simulation time 169844459 ps
CPU time 0.94 seconds
Started Aug 13 06:35:26 PM PDT 24
Finished Aug 13 06:35:27 PM PDT 24
Peak memory 207492 kb
Host smart-9ff90cd6-95ab-42b4-9be4-33cc445631e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60949
5767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.609495767
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2207701005
Short name T1911
Test name
Test status
Simulation time 146644054 ps
CPU time 0.83 seconds
Started Aug 13 06:35:27 PM PDT 24
Finished Aug 13 06:35:28 PM PDT 24
Peak memory 207580 kb
Host smart-5891cee4-0ec4-480f-b6d5-3cbc5d20cb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22077
01005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2207701005
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3640976087
Short name T2646
Test name
Test status
Simulation time 464109880 ps
CPU time 1.65 seconds
Started Aug 13 06:35:37 PM PDT 24
Finished Aug 13 06:35:39 PM PDT 24
Peak memory 207572 kb
Host smart-46ef341d-bea1-49e7-9dd2-d0d87e934ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36409
76087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3640976087
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.145937283
Short name T3563
Test name
Test status
Simulation time 617988194 ps
CPU time 1.87 seconds
Started Aug 13 06:35:30 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207576 kb
Host smart-02bc0f11-3f4e-4974-aef3-a6ebc9785562
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=145937283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.145937283
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.2812084334
Short name T761
Test name
Test status
Simulation time 19378368510 ps
CPU time 32.73 seconds
Started Aug 13 06:35:29 PM PDT 24
Finished Aug 13 06:36:02 PM PDT 24
Peak memory 207816 kb
Host smart-75170ed4-992d-4ffe-ae22-c85ed6247aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28120
84334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.2812084334
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.2986446809
Short name T807
Test name
Test status
Simulation time 8363350018 ps
CPU time 55.51 seconds
Started Aug 13 06:35:26 PM PDT 24
Finished Aug 13 06:36:21 PM PDT 24
Peak memory 207844 kb
Host smart-2bfc4c76-35f2-4e59-b137-6c86ae889724
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986446809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.2986446809
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.773058101
Short name T1807
Test name
Test status
Simulation time 618537847 ps
CPU time 1.51 seconds
Started Aug 13 06:35:27 PM PDT 24
Finished Aug 13 06:35:29 PM PDT 24
Peak memory 207552 kb
Host smart-364643ee-dac1-494a-acbf-73953341d9ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77305
8101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.773058101
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2793864492
Short name T1931
Test name
Test status
Simulation time 142729867 ps
CPU time 0.84 seconds
Started Aug 13 06:35:30 PM PDT 24
Finished Aug 13 06:35:31 PM PDT 24
Peak memory 207536 kb
Host smart-8e07d9ce-0ce0-435d-9b3a-f6d1f412598b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938
64492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2793864492
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.4125830476
Short name T1996
Test name
Test status
Simulation time 39472504 ps
CPU time 0.71 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:35:42 PM PDT 24
Peak memory 207404 kb
Host smart-f6578ce2-a806-4e93-8d4d-bf59680b4e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41258
30476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.4125830476
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1114229063
Short name T3261
Test name
Test status
Simulation time 990238349 ps
CPU time 2.46 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:35:36 PM PDT 24
Peak memory 207724 kb
Host smart-9aa39a43-f6de-49bc-914d-36a3f95befa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11142
29063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1114229063
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3347940440
Short name T682
Test name
Test status
Simulation time 157697839 ps
CPU time 1.55 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:35:33 PM PDT 24
Peak memory 207648 kb
Host smart-92ead629-56b1-45d7-a6d0-a40e9e29e930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33479
40440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3347940440
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.110083553
Short name T2033
Test name
Test status
Simulation time 235013353 ps
CPU time 1.22 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 215916 kb
Host smart-3c0ac88e-eadb-43ca-ae5e-bff8ff94be22
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=110083553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.110083553
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2759997319
Short name T2690
Test name
Test status
Simulation time 150869057 ps
CPU time 0.83 seconds
Started Aug 13 06:35:29 PM PDT 24
Finished Aug 13 06:35:30 PM PDT 24
Peak memory 207464 kb
Host smart-557fa5de-47f7-4f83-92e8-d100f787c889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27599
97319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2759997319
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2532793799
Short name T1677
Test name
Test status
Simulation time 239409645 ps
CPU time 1.03 seconds
Started Aug 13 06:35:32 PM PDT 24
Finished Aug 13 06:35:33 PM PDT 24
Peak memory 207508 kb
Host smart-d83f7cca-f6ee-40e1-8698-65519765a4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25327
93799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2532793799
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.1514860062
Short name T3141
Test name
Test status
Simulation time 3984309272 ps
CPU time 41.04 seconds
Started Aug 13 06:35:28 PM PDT 24
Finished Aug 13 06:36:09 PM PDT 24
Peak memory 224176 kb
Host smart-dbd362f6-7f59-4aa4-9615-95edb0724977
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1514860062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.1514860062
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.3415680815
Short name T2765
Test name
Test status
Simulation time 6619977133 ps
CPU time 48.87 seconds
Started Aug 13 06:35:28 PM PDT 24
Finished Aug 13 06:36:17 PM PDT 24
Peak memory 207768 kb
Host smart-fb98e025-94ae-43f9-a2db-e246a8c82f5a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3415680815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.3415680815
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1406727599
Short name T546
Test name
Test status
Simulation time 265150731 ps
CPU time 1.05 seconds
Started Aug 13 06:35:27 PM PDT 24
Finished Aug 13 06:35:28 PM PDT 24
Peak memory 207596 kb
Host smart-36de35b0-1d82-47d1-9070-1b4c4df1cdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14067
27599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1406727599
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3352987369
Short name T1288
Test name
Test status
Simulation time 25436328863 ps
CPU time 41.15 seconds
Started Aug 13 06:35:35 PM PDT 24
Finished Aug 13 06:36:16 PM PDT 24
Peak memory 216340 kb
Host smart-236703eb-2c41-4e28-b152-96116680d0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33529
87369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3352987369
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3249421449
Short name T2237
Test name
Test status
Simulation time 9651644993 ps
CPU time 11.45 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:54 PM PDT 24
Peak memory 207812 kb
Host smart-7d443e67-1283-49cd-97f9-3b7879b38b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32494
21449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3249421449
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.542476005
Short name T1973
Test name
Test status
Simulation time 4910637135 ps
CPU time 47.57 seconds
Started Aug 13 06:35:38 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 224208 kb
Host smart-47e071e3-d3fb-461e-b872-06236a995810
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=542476005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.542476005
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3776221301
Short name T1585
Test name
Test status
Simulation time 2987054858 ps
CPU time 29.64 seconds
Started Aug 13 06:35:34 PM PDT 24
Finished Aug 13 06:36:04 PM PDT 24
Peak memory 217444 kb
Host smart-75a04159-56ab-426b-9df2-d82255164e6d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3776221301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3776221301
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2221980479
Short name T3205
Test name
Test status
Simulation time 292121386 ps
CPU time 1.01 seconds
Started Aug 13 06:35:35 PM PDT 24
Finished Aug 13 06:35:36 PM PDT 24
Peak memory 207480 kb
Host smart-cd39c056-ddf3-4332-8051-45178d046a42
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2221980479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2221980479
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3840544350
Short name T1468
Test name
Test status
Simulation time 205118411 ps
CPU time 0.93 seconds
Started Aug 13 06:35:39 PM PDT 24
Finished Aug 13 06:35:40 PM PDT 24
Peak memory 207472 kb
Host smart-b5bc3d7f-2aeb-46fb-a723-bcc33b6e9b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38405
44350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3840544350
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.3845294249
Short name T3274
Test name
Test status
Simulation time 2738085853 ps
CPU time 21.69 seconds
Started Aug 13 06:35:39 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 218044 kb
Host smart-2e808398-5ba8-4ba7-bfa6-919e4e14120d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38452
94249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.3845294249
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.3032881161
Short name T1488
Test name
Test status
Simulation time 2806612098 ps
CPU time 27.7 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 217964 kb
Host smart-57f79d16-3d87-4bb0-8631-8764aaae5883
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3032881161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.3032881161
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.68825400
Short name T1898
Test name
Test status
Simulation time 2898335816 ps
CPU time 83.55 seconds
Started Aug 13 06:35:32 PM PDT 24
Finished Aug 13 06:36:56 PM PDT 24
Peak memory 217396 kb
Host smart-f5d44f03-c8c5-448e-8e39-0786f9bd59dd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=68825400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.68825400
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.519718906
Short name T2725
Test name
Test status
Simulation time 148566841 ps
CPU time 0.85 seconds
Started Aug 13 06:35:34 PM PDT 24
Finished Aug 13 06:35:35 PM PDT 24
Peak memory 207488 kb
Host smart-86431bcb-aabd-477a-8fe2-a3a34ce214d0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=519718906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.519718906
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3010771397
Short name T2334
Test name
Test status
Simulation time 173447291 ps
CPU time 0.86 seconds
Started Aug 13 06:35:36 PM PDT 24
Finished Aug 13 06:35:37 PM PDT 24
Peak memory 207512 kb
Host smart-40f76f4d-1173-4661-945d-fcaf03947f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30107
71397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3010771397
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1850953109
Short name T129
Test name
Test status
Simulation time 211792839 ps
CPU time 0.95 seconds
Started Aug 13 06:35:43 PM PDT 24
Finished Aug 13 06:35:44 PM PDT 24
Peak memory 207528 kb
Host smart-c71895e8-8c43-4718-9752-b62ce3718dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18509
53109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1850953109
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1559921517
Short name T1066
Test name
Test status
Simulation time 179683410 ps
CPU time 0.87 seconds
Started Aug 13 06:35:40 PM PDT 24
Finished Aug 13 06:35:41 PM PDT 24
Peak memory 207500 kb
Host smart-8a68ce17-20d3-415a-b3b1-dc9baaac3fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15599
21517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1559921517
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2326952853
Short name T1268
Test name
Test status
Simulation time 190287253 ps
CPU time 0.94 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207636 kb
Host smart-75619daa-6014-4c91-adba-01135d02b376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23269
52853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2326952853
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3830607494
Short name T3489
Test name
Test status
Simulation time 170618754 ps
CPU time 0.9 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:35:42 PM PDT 24
Peak memory 207604 kb
Host smart-7c89a231-8a8d-4a73-a6b9-3e9e55be116e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
07494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3830607494
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3037338343
Short name T2460
Test name
Test status
Simulation time 149726021 ps
CPU time 0.85 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207516 kb
Host smart-01470ef6-1b06-4d18-abf4-fbc658f7a810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30373
38343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3037338343
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.4071422289
Short name T2008
Test name
Test status
Simulation time 244380480 ps
CPU time 1.09 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:35:34 PM PDT 24
Peak memory 207556 kb
Host smart-e6c09786-4f59-45ce-83fa-a09c69759953
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4071422289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.4071422289
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1432625106
Short name T2722
Test name
Test status
Simulation time 188770888 ps
CPU time 0.92 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:35:34 PM PDT 24
Peak memory 207460 kb
Host smart-f754a247-807b-4ee8-bcb3-6add8cac7e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14326
25106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1432625106
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3687140937
Short name T1038
Test name
Test status
Simulation time 47971065 ps
CPU time 0.77 seconds
Started Aug 13 06:35:34 PM PDT 24
Finished Aug 13 06:35:35 PM PDT 24
Peak memory 207532 kb
Host smart-ebeb042c-31f2-4f6f-afdc-2f1401c1ad02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36871
40937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3687140937
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.93291081
Short name T3057
Test name
Test status
Simulation time 7512705716 ps
CPU time 22.3 seconds
Started Aug 13 06:35:35 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 215956 kb
Host smart-bb641490-776b-4fb2-8aa5-abeb89707c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93291
081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.93291081
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3013304388
Short name T357
Test name
Test status
Simulation time 194249945 ps
CPU time 1.02 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:35:34 PM PDT 24
Peak memory 207504 kb
Host smart-e50f57f5-dd89-4bc2-b631-6a1e539139da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30133
04388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3013304388
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.981641145
Short name T2656
Test name
Test status
Simulation time 168248273 ps
CPU time 1.05 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207640 kb
Host smart-d28f8c92-8117-4d5c-8967-08ad8b89185c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98164
1145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.981641145
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.1688039596
Short name T2845
Test name
Test status
Simulation time 216416275 ps
CPU time 0.9 seconds
Started Aug 13 06:35:43 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207504 kb
Host smart-bc47977d-52a2-4cf9-88e5-cdb10597c0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16880
39596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.1688039596
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.489416599
Short name T1156
Test name
Test status
Simulation time 217149874 ps
CPU time 0.99 seconds
Started Aug 13 06:35:32 PM PDT 24
Finished Aug 13 06:35:33 PM PDT 24
Peak memory 207428 kb
Host smart-642e1536-79bd-4e66-b427-51c38ffb27ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48941
6599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.489416599
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_resume_link_active.1966845034
Short name T2757
Test name
Test status
Simulation time 20158475752 ps
CPU time 24.44 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:36:05 PM PDT 24
Peak memory 207628 kb
Host smart-334abeb4-754d-4631-9f93-6771ffff0d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19668
45034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.1966845034
Directory /workspace/13.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/13.usbdev_rx_full.2150398298
Short name T3077
Test name
Test status
Simulation time 294465473 ps
CPU time 1.17 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:35:42 PM PDT 24
Peak memory 207540 kb
Host smart-3522b797-1d1a-405c-85a6-190018f5b13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21503
98298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.2150398298
Directory /workspace/13.usbdev_rx_full/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.846345618
Short name T2076
Test name
Test status
Simulation time 197897226 ps
CPU time 0.96 seconds
Started Aug 13 06:35:36 PM PDT 24
Finished Aug 13 06:35:37 PM PDT 24
Peak memory 207460 kb
Host smart-b256e739-8f16-4bb7-a51e-5bd2d407d8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84634
5618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.846345618
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.855107464
Short name T1143
Test name
Test status
Simulation time 157603882 ps
CPU time 0.86 seconds
Started Aug 13 06:35:38 PM PDT 24
Finished Aug 13 06:35:39 PM PDT 24
Peak memory 207552 kb
Host smart-79bc1a5d-96a1-45b8-b591-6e1ab7c61f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85510
7464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.855107464
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.367738690
Short name T2887
Test name
Test status
Simulation time 232325881 ps
CPU time 1.06 seconds
Started Aug 13 06:35:38 PM PDT 24
Finished Aug 13 06:35:39 PM PDT 24
Peak memory 207476 kb
Host smart-93a0c1c8-975b-4276-b0ec-60502c6a105d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36773
8690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.367738690
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2633599712
Short name T3485
Test name
Test status
Simulation time 3226384590 ps
CPU time 96.46 seconds
Started Aug 13 06:35:35 PM PDT 24
Finished Aug 13 06:37:12 PM PDT 24
Peak memory 217676 kb
Host smart-63dc14a9-be15-44d6-943f-d164f884e4b8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2633599712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2633599712
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3396384082
Short name T1751
Test name
Test status
Simulation time 225954595 ps
CPU time 0.97 seconds
Started Aug 13 06:35:43 PM PDT 24
Finished Aug 13 06:35:44 PM PDT 24
Peak memory 207524 kb
Host smart-1ac94ef4-92c6-40f8-8adb-afb865aed1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33963
84082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3396384082
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3969318891
Short name T1191
Test name
Test status
Simulation time 179811636 ps
CPU time 0.9 seconds
Started Aug 13 06:35:34 PM PDT 24
Finished Aug 13 06:35:35 PM PDT 24
Peak memory 207468 kb
Host smart-e7fb05db-e0e3-4544-9751-82151a60e2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39693
18891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3969318891
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1937899909
Short name T543
Test name
Test status
Simulation time 1322803879 ps
CPU time 3.06 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:35:34 PM PDT 24
Peak memory 207708 kb
Host smart-32177c93-e7ea-425d-8ae1-5ce4781d111d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19378
99909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1937899909
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.57440120
Short name T2502
Test name
Test status
Simulation time 3628005749 ps
CPU time 37.22 seconds
Started Aug 13 06:35:31 PM PDT 24
Finished Aug 13 06:36:09 PM PDT 24
Peak memory 217636 kb
Host smart-a0247ce6-d702-442c-ad99-5d5b2ca9385c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57440
120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.57440120
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.1549710779
Short name T2426
Test name
Test status
Simulation time 4319693471 ps
CPU time 39.62 seconds
Started Aug 13 06:35:45 PM PDT 24
Finished Aug 13 06:36:25 PM PDT 24
Peak memory 207772 kb
Host smart-54218d97-29d3-44d3-8a41-184c33d4545f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549710779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.1549710779
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_tx_rx_disruption.830056571
Short name T1559
Test name
Test status
Simulation time 488711627 ps
CPU time 1.42 seconds
Started Aug 13 06:35:38 PM PDT 24
Finished Aug 13 06:35:40 PM PDT 24
Peak memory 207608 kb
Host smart-55f44e46-8ef7-4dfb-84af-f4ef74fabd63
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830056571 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.usbdev_tx_rx_disruption.830056571
Directory /workspace/13.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/130.usbdev_endpoint_types.3597747642
Short name T2123
Test name
Test status
Simulation time 494558544 ps
CPU time 1.35 seconds
Started Aug 13 06:41:16 PM PDT 24
Finished Aug 13 06:41:17 PM PDT 24
Peak memory 207564 kb
Host smart-f70345aa-43c3-4787-97f5-ae90e3cefd79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3597747642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.3597747642
Directory /workspace/130.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/130.usbdev_tx_rx_disruption.3270532051
Short name T2285
Test name
Test status
Simulation time 633374511 ps
CPU time 1.69 seconds
Started Aug 13 06:41:27 PM PDT 24
Finished Aug 13 06:41:29 PM PDT 24
Peak memory 207604 kb
Host smart-0755a7d8-deca-48d8-8f84-c2dd6020d62b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270532051 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.usbdev_tx_rx_disruption.3270532051
Directory /workspace/130.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/131.usbdev_endpoint_types.2150003990
Short name T385
Test name
Test status
Simulation time 422103373 ps
CPU time 1.4 seconds
Started Aug 13 06:41:23 PM PDT 24
Finished Aug 13 06:41:25 PM PDT 24
Peak memory 207516 kb
Host smart-9dbbd450-06d4-4ea5-909a-5b0a0b50f5d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2150003990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.2150003990
Directory /workspace/131.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/131.usbdev_tx_rx_disruption.2037822541
Short name T1695
Test name
Test status
Simulation time 537319910 ps
CPU time 1.56 seconds
Started Aug 13 06:41:28 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 207624 kb
Host smart-d2dc0a6c-7b54-48c3-b89c-1bcd0efbd4af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037822541 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.usbdev_tx_rx_disruption.2037822541
Directory /workspace/131.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/132.usbdev_endpoint_types.1920969088
Short name T485
Test name
Test status
Simulation time 338497830 ps
CPU time 1.18 seconds
Started Aug 13 06:41:25 PM PDT 24
Finished Aug 13 06:41:26 PM PDT 24
Peak memory 207556 kb
Host smart-661ce130-8df4-4b9c-aeb4-73285c899d36
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1920969088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.1920969088
Directory /workspace/132.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/132.usbdev_tx_rx_disruption.4123972548
Short name T2250
Test name
Test status
Simulation time 518713637 ps
CPU time 1.65 seconds
Started Aug 13 06:41:33 PM PDT 24
Finished Aug 13 06:41:35 PM PDT 24
Peak memory 207616 kb
Host smart-b59e07f1-6fce-43f3-b25c-cdbc7a71e05f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123972548 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.usbdev_tx_rx_disruption.4123972548
Directory /workspace/132.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/133.usbdev_endpoint_types.1938780423
Short name T3616
Test name
Test status
Simulation time 274977865 ps
CPU time 1.11 seconds
Started Aug 13 06:41:29 PM PDT 24
Finished Aug 13 06:41:30 PM PDT 24
Peak memory 207552 kb
Host smart-4a1ce3a6-3c5e-4045-a4ff-ef1d36831819
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1938780423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.1938780423
Directory /workspace/133.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/133.usbdev_tx_rx_disruption.1738127613
Short name T1063
Test name
Test status
Simulation time 521806122 ps
CPU time 1.71 seconds
Started Aug 13 06:41:41 PM PDT 24
Finished Aug 13 06:41:43 PM PDT 24
Peak memory 207576 kb
Host smart-e73ab936-7ba5-4b6e-a866-aba15438987b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738127613 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.usbdev_tx_rx_disruption.1738127613
Directory /workspace/133.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/134.usbdev_endpoint_types.550059150
Short name T3074
Test name
Test status
Simulation time 194048316 ps
CPU time 0.95 seconds
Started Aug 13 06:41:23 PM PDT 24
Finished Aug 13 06:41:24 PM PDT 24
Peak memory 207548 kb
Host smart-ac205f00-bdf4-42c0-a6b3-81dbdd4d5212
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=550059150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.550059150
Directory /workspace/134.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/134.usbdev_tx_rx_disruption.82023299
Short name T2825
Test name
Test status
Simulation time 569523617 ps
CPU time 1.7 seconds
Started Aug 13 06:41:27 PM PDT 24
Finished Aug 13 06:41:29 PM PDT 24
Peak memory 207520 kb
Host smart-9517fd43-91e0-4056-8587-bc7268a55c9d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82023299 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 134.usbdev_tx_rx_disruption.82023299
Directory /workspace/134.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/135.usbdev_endpoint_types.8405118
Short name T441
Test name
Test status
Simulation time 478327625 ps
CPU time 1.46 seconds
Started Aug 13 06:41:36 PM PDT 24
Finished Aug 13 06:41:37 PM PDT 24
Peak memory 207556 kb
Host smart-9d01b99f-fadc-4de6-beed-2f16ee8a8c65
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=8405118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.8405118
Directory /workspace/135.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/135.usbdev_tx_rx_disruption.3472791168
Short name T2821
Test name
Test status
Simulation time 492766189 ps
CPU time 1.58 seconds
Started Aug 13 06:41:29 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 207476 kb
Host smart-98bac8df-feee-49fc-b4f8-bc656540f8b3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472791168 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.usbdev_tx_rx_disruption.3472791168
Directory /workspace/135.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/136.usbdev_tx_rx_disruption.3886549165
Short name T1641
Test name
Test status
Simulation time 613262042 ps
CPU time 1.68 seconds
Started Aug 13 06:41:10 PM PDT 24
Finished Aug 13 06:41:12 PM PDT 24
Peak memory 207600 kb
Host smart-523f75c9-6299-4fc6-bd27-ed9f0d69ce1d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886549165 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.usbdev_tx_rx_disruption.3886549165
Directory /workspace/136.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/137.usbdev_endpoint_types.1308275620
Short name T2030
Test name
Test status
Simulation time 286148106 ps
CPU time 1.05 seconds
Started Aug 13 06:41:30 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 207524 kb
Host smart-92e11406-64ed-41db-81e0-db3a1f6be0ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1308275620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.1308275620
Directory /workspace/137.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/137.usbdev_tx_rx_disruption.3480446282
Short name T2274
Test name
Test status
Simulation time 487959183 ps
CPU time 1.44 seconds
Started Aug 13 06:41:13 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207532 kb
Host smart-f1fb9bdd-66df-4f4b-a699-905d1f4fd9a7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480446282 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.usbdev_tx_rx_disruption.3480446282
Directory /workspace/137.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/138.usbdev_tx_rx_disruption.2670360124
Short name T3030
Test name
Test status
Simulation time 468897493 ps
CPU time 1.46 seconds
Started Aug 13 06:41:42 PM PDT 24
Finished Aug 13 06:41:44 PM PDT 24
Peak memory 207612 kb
Host smart-fa9e1c35-155e-4e79-bbed-ce3e7b2dcd1e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670360124 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.usbdev_tx_rx_disruption.2670360124
Directory /workspace/138.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/139.usbdev_endpoint_types.408175467
Short name T415
Test name
Test status
Simulation time 774891351 ps
CPU time 1.73 seconds
Started Aug 13 06:41:20 PM PDT 24
Finished Aug 13 06:41:22 PM PDT 24
Peak memory 207536 kb
Host smart-c2064b99-c348-406f-bfeb-e7b56a510616
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=408175467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.408175467
Directory /workspace/139.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/139.usbdev_tx_rx_disruption.398099050
Short name T1236
Test name
Test status
Simulation time 565070138 ps
CPU time 1.56 seconds
Started Aug 13 06:41:19 PM PDT 24
Finished Aug 13 06:41:21 PM PDT 24
Peak memory 207488 kb
Host smart-192bb15b-1fb1-4a2e-a3b0-4835b01e2a58
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398099050 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 139.usbdev_tx_rx_disruption.398099050
Directory /workspace/139.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2649781601
Short name T3544
Test name
Test status
Simulation time 97484766 ps
CPU time 0.76 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207476 kb
Host smart-9e23de73-2975-4f41-b985-cf0ce87090c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2649781601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2649781601
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3871343622
Short name T3412
Test name
Test status
Simulation time 9678126416 ps
CPU time 12.75 seconds
Started Aug 13 06:35:38 PM PDT 24
Finished Aug 13 06:35:51 PM PDT 24
Peak memory 207780 kb
Host smart-80da2505-1264-4b8c-baf5-0d1b6f92ec07
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871343622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.3871343622
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3993692736
Short name T2007
Test name
Test status
Simulation time 19261950967 ps
CPU time 27.35 seconds
Started Aug 13 06:35:40 PM PDT 24
Finished Aug 13 06:36:08 PM PDT 24
Peak memory 207832 kb
Host smart-92f67811-f35c-45c4-b0d7-7d1753f5200b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993692736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3993692736
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1086557822
Short name T2248
Test name
Test status
Simulation time 30667536618 ps
CPU time 46.98 seconds
Started Aug 13 06:35:39 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 207812 kb
Host smart-c1149931-18cd-4b8d-8c56-747644a7a24c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086557822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.1086557822
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2323929005
Short name T2400
Test name
Test status
Simulation time 160601629 ps
CPU time 0.95 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207636 kb
Host smart-5dc6a5a7-93ee-4d81-b459-5b63b94025b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23239
29005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2323929005
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2300345413
Short name T742
Test name
Test status
Simulation time 186889062 ps
CPU time 0.9 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:35:34 PM PDT 24
Peak memory 207528 kb
Host smart-5c451924-1a52-4922-afaf-e097df048ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23003
45413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2300345413
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3275445098
Short name T1213
Test name
Test status
Simulation time 435806607 ps
CPU time 1.61 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:35:35 PM PDT 24
Peak memory 207540 kb
Host smart-94aa35fa-37f5-40c1-84fd-fa7e1f027a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
45098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3275445098
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1273178759
Short name T339
Test name
Test status
Simulation time 982436050 ps
CPU time 2.91 seconds
Started Aug 13 06:35:32 PM PDT 24
Finished Aug 13 06:35:35 PM PDT 24
Peak memory 207692 kb
Host smart-cd24ceab-88e0-4095-890d-12fb9b1574ec
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1273178759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1273178759
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3373997478
Short name T1863
Test name
Test status
Simulation time 15683978081 ps
CPU time 28.38 seconds
Started Aug 13 06:35:36 PM PDT 24
Finished Aug 13 06:36:05 PM PDT 24
Peak memory 207820 kb
Host smart-f83ec078-27d6-4e8f-9863-18f4bcfa0182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33739
97478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3373997478
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.1647442632
Short name T3555
Test name
Test status
Simulation time 734656103 ps
CPU time 15.5 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:58 PM PDT 24
Peak memory 207792 kb
Host smart-1dea2be2-ea56-4a09-9e6d-f885c2bfc3b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647442632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.1647442632
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.4058339248
Short name T1892
Test name
Test status
Simulation time 802007292 ps
CPU time 1.89 seconds
Started Aug 13 06:35:35 PM PDT 24
Finished Aug 13 06:35:37 PM PDT 24
Peak memory 207480 kb
Host smart-296f3441-9564-4ced-a4a3-5ae94b6ed749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40583
39248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.4058339248
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3605259919
Short name T2858
Test name
Test status
Simulation time 148907254 ps
CPU time 0.89 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207584 kb
Host smart-13a52be9-f786-466e-b8db-05cac17aaac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36052
59919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3605259919
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1585227974
Short name T1878
Test name
Test status
Simulation time 55956848 ps
CPU time 0.72 seconds
Started Aug 13 06:35:43 PM PDT 24
Finished Aug 13 06:35:44 PM PDT 24
Peak memory 207500 kb
Host smart-25db3f1b-a6a6-4cdf-9191-880c8e518a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15852
27974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1585227974
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3568970869
Short name T3421
Test name
Test status
Simulation time 986674029 ps
CPU time 2.52 seconds
Started Aug 13 06:35:43 PM PDT 24
Finished Aug 13 06:35:46 PM PDT 24
Peak memory 207772 kb
Host smart-7280170d-e890-4790-9c7b-9909607223d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35689
70869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3568970869
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_types.1362158151
Short name T3454
Test name
Test status
Simulation time 191220389 ps
CPU time 0.93 seconds
Started Aug 13 06:35:38 PM PDT 24
Finished Aug 13 06:35:40 PM PDT 24
Peak memory 207512 kb
Host smart-2ed592f4-83a5-439d-a921-3ab7f9d5ea55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1362158151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.1362158151
Directory /workspace/14.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.4022385839
Short name T2117
Test name
Test status
Simulation time 342846200 ps
CPU time 2.14 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207640 kb
Host smart-27c7fce5-c7ca-41f3-9b25-90274914fd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40223
85839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.4022385839
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2619066424
Short name T1145
Test name
Test status
Simulation time 273308761 ps
CPU time 1.25 seconds
Started Aug 13 06:35:46 PM PDT 24
Finished Aug 13 06:35:47 PM PDT 24
Peak memory 215900 kb
Host smart-ce0b97b6-d310-4222-820d-157897b4e665
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2619066424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2619066424
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3206065625
Short name T991
Test name
Test status
Simulation time 180667069 ps
CPU time 0.92 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207424 kb
Host smart-95874786-efe3-44d5-b46c-5d1b4bd3cddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32060
65625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3206065625
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.323377238
Short name T2276
Test name
Test status
Simulation time 178600914 ps
CPU time 0.89 seconds
Started Aug 13 06:35:52 PM PDT 24
Finished Aug 13 06:35:53 PM PDT 24
Peak memory 207500 kb
Host smart-d5407b8b-0d79-4827-9b39-177d3de84f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32337
7238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.323377238
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.3794254513
Short name T2880
Test name
Test status
Simulation time 2725193849 ps
CPU time 75.43 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:36:57 PM PDT 24
Peak memory 224300 kb
Host smart-aab16c86-3249-40f9-976a-b5b124a74ed0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3794254513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.3794254513
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.1783531816
Short name T2185
Test name
Test status
Simulation time 9532797572 ps
CPU time 62.43 seconds
Started Aug 13 06:35:43 PM PDT 24
Finished Aug 13 06:36:46 PM PDT 24
Peak memory 207804 kb
Host smart-90af64b6-fcf4-4780-9325-26c2eaa83969
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1783531816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.1783531816
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2689401015
Short name T3443
Test name
Test status
Simulation time 192610935 ps
CPU time 0.92 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:35:42 PM PDT 24
Peak memory 207588 kb
Host smart-2993b1da-8516-4dab-8c7e-e141e1338367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26894
01015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2689401015
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3704031016
Short name T2847
Test name
Test status
Simulation time 6965844492 ps
CPU time 11.54 seconds
Started Aug 13 06:35:47 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 216116 kb
Host smart-05275da9-322e-499f-9c93-19f7f01c6f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37040
31016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3704031016
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.412436143
Short name T2585
Test name
Test status
Simulation time 6245050419 ps
CPU time 8.64 seconds
Started Aug 13 06:35:43 PM PDT 24
Finished Aug 13 06:35:52 PM PDT 24
Peak memory 216152 kb
Host smart-7d12438b-8dd4-4167-bb0b-b57621d1a5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41243
6143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.412436143
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3226196536
Short name T3196
Test name
Test status
Simulation time 2601299262 ps
CPU time 21.31 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:36:04 PM PDT 24
Peak memory 219332 kb
Host smart-471e82c8-e49b-480c-823b-7e6a89bdb79c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3226196536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3226196536
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2195947542
Short name T606
Test name
Test status
Simulation time 2796690700 ps
CPU time 29.64 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:36:18 PM PDT 24
Peak memory 217432 kb
Host smart-20772fee-10c6-474c-8641-08a805194a3b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2195947542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2195947542
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2178473471
Short name T820
Test name
Test status
Simulation time 323827937 ps
CPU time 1.06 seconds
Started Aug 13 06:35:45 PM PDT 24
Finished Aug 13 06:35:47 PM PDT 24
Peak memory 207532 kb
Host smart-218f58a3-1b36-4c2c-a536-c85e350cb053
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2178473471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2178473471
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3282675418
Short name T1117
Test name
Test status
Simulation time 232023626 ps
CPU time 0.95 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207420 kb
Host smart-b405d25f-6cc3-4573-a597-e48aa1718909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32826
75418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3282675418
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.453816104
Short name T635
Test name
Test status
Simulation time 1943705488 ps
CPU time 15.43 seconds
Started Aug 13 06:35:54 PM PDT 24
Finished Aug 13 06:36:09 PM PDT 24
Peak memory 217444 kb
Host smart-3adfff9f-62c8-4410-9d2d-dc87b2ad4fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45381
6104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.453816104
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1556604974
Short name T649
Test name
Test status
Simulation time 2787387483 ps
CPU time 84.27 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:37:09 PM PDT 24
Peak memory 218156 kb
Host smart-7a6f5a65-a7c2-429f-a07d-e372c89a9220
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1556604974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1556604974
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.71763739
Short name T3003
Test name
Test status
Simulation time 3534545136 ps
CPU time 34.07 seconds
Started Aug 13 06:35:45 PM PDT 24
Finished Aug 13 06:36:20 PM PDT 24
Peak memory 216048 kb
Host smart-5852beb6-067d-477b-b842-c9854614e562
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=71763739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.71763739
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1632782314
Short name T2363
Test name
Test status
Simulation time 174588462 ps
CPU time 0.89 seconds
Started Aug 13 06:35:45 PM PDT 24
Finished Aug 13 06:35:46 PM PDT 24
Peak memory 207540 kb
Host smart-82ca2a8f-bc4f-4569-b309-d9de684e393d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1632782314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1632782314
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3552738611
Short name T2399
Test name
Test status
Simulation time 179416086 ps
CPU time 0.98 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207520 kb
Host smart-f0f977ca-bdcc-48fd-8e93-3c34b972889d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35527
38611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3552738611
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1272060392
Short name T3499
Test name
Test status
Simulation time 213518749 ps
CPU time 0.98 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:35:49 PM PDT 24
Peak memory 207516 kb
Host smart-9613b4ae-de1e-42a7-8951-0c0a2ba94ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12720
60392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1272060392
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2309060699
Short name T1017
Test name
Test status
Simulation time 162951191 ps
CPU time 0.89 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207512 kb
Host smart-2d0336e6-be8c-41ca-b1f9-97270926f330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23090
60699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2309060699
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3018144399
Short name T2477
Test name
Test status
Simulation time 173105520 ps
CPU time 0.89 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207492 kb
Host smart-c6e0b1bd-30a5-482e-8150-437bf032f332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30181
44399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3018144399
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.249821272
Short name T1969
Test name
Test status
Simulation time 159577207 ps
CPU time 0.9 seconds
Started Aug 13 06:35:46 PM PDT 24
Finished Aug 13 06:35:47 PM PDT 24
Peak memory 207532 kb
Host smart-50073bc3-2a5d-4d0b-b833-0d43d3c4e067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24982
1272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.249821272
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1222405729
Short name T2864
Test name
Test status
Simulation time 210770204 ps
CPU time 1 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207508 kb
Host smart-2ce38cb1-c7b1-4e5f-9b5c-fe458bed0ecf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1222405729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1222405729
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2499077833
Short name T1723
Test name
Test status
Simulation time 170688195 ps
CPU time 0.86 seconds
Started Aug 13 06:35:40 PM PDT 24
Finished Aug 13 06:35:41 PM PDT 24
Peak memory 207492 kb
Host smart-3a626814-f09c-4099-b081-9cb82aefa617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24990
77833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2499077833
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.4120578552
Short name T2009
Test name
Test status
Simulation time 69245404 ps
CPU time 0.74 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207564 kb
Host smart-3ee447e9-01ce-4e01-954d-196569111ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41205
78552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.4120578552
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1907463318
Short name T3320
Test name
Test status
Simulation time 17442385866 ps
CPU time 44.72 seconds
Started Aug 13 06:35:42 PM PDT 24
Finished Aug 13 06:36:27 PM PDT 24
Peak memory 215960 kb
Host smart-e62a8e77-fa87-4526-ac6f-5e4e5a23eb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19074
63318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1907463318
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3715185223
Short name T2027
Test name
Test status
Simulation time 187719881 ps
CPU time 0.97 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207532 kb
Host smart-742415c3-04d8-46cd-8aa2-c1b6ebf81947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37151
85223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3715185223
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3543003486
Short name T1470
Test name
Test status
Simulation time 173280364 ps
CPU time 0.88 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207360 kb
Host smart-346e73a5-155a-4c0b-97b7-aafd070d00ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35430
03486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3543003486
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.499664405
Short name T2655
Test name
Test status
Simulation time 180652550 ps
CPU time 0.92 seconds
Started Aug 13 06:35:46 PM PDT 24
Finished Aug 13 06:35:47 PM PDT 24
Peak memory 207460 kb
Host smart-a5a8e19d-5881-4f08-88ee-9600b8855617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49966
4405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.499664405
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1608120619
Short name T1600
Test name
Test status
Simulation time 244279479 ps
CPU time 0.98 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207492 kb
Host smart-72cae2e0-deb4-4df3-8ecb-eb3a3072308c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16081
20619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1608120619
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_resume_link_active.1193637718
Short name T1197
Test name
Test status
Simulation time 20174137705 ps
CPU time 24.51 seconds
Started Aug 13 06:35:45 PM PDT 24
Finished Aug 13 06:36:10 PM PDT 24
Peak memory 207632 kb
Host smart-620cb4c4-0051-47c0-b9f8-3168170e6d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
37718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.1193637718
Directory /workspace/14.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2104761574
Short name T2632
Test name
Test status
Simulation time 179754175 ps
CPU time 0.9 seconds
Started Aug 13 06:35:45 PM PDT 24
Finished Aug 13 06:35:46 PM PDT 24
Peak memory 207484 kb
Host smart-e33afdde-f471-4027-b285-09ce09a563c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21047
61574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2104761574
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_rx_full.3346821085
Short name T327
Test name
Test status
Simulation time 251446302 ps
CPU time 1.12 seconds
Started Aug 13 06:35:43 PM PDT 24
Finished Aug 13 06:35:44 PM PDT 24
Peak memory 207488 kb
Host smart-56cfcfac-3a37-44a3-b3a9-995148a75525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33468
21085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.3346821085
Directory /workspace/14.usbdev_rx_full/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2039013646
Short name T1850
Test name
Test status
Simulation time 149656931 ps
CPU time 0.85 seconds
Started Aug 13 06:35:46 PM PDT 24
Finished Aug 13 06:35:47 PM PDT 24
Peak memory 207516 kb
Host smart-7dcd6688-e745-4f62-aff3-13c42ce14032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20390
13646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2039013646
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2953763837
Short name T1613
Test name
Test status
Simulation time 164091069 ps
CPU time 0.93 seconds
Started Aug 13 06:35:45 PM PDT 24
Finished Aug 13 06:35:46 PM PDT 24
Peak memory 207516 kb
Host smart-accc4d20-b963-4430-aa10-c115386db94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537
63837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2953763837
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.801054876
Short name T1209
Test name
Test status
Simulation time 245914128 ps
CPU time 1.03 seconds
Started Aug 13 06:35:47 PM PDT 24
Finished Aug 13 06:35:48 PM PDT 24
Peak memory 207460 kb
Host smart-9702444c-c30d-4431-9be7-52c2790789d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80105
4876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.801054876
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1871759650
Short name T3353
Test name
Test status
Simulation time 3196568215 ps
CPU time 89.5 seconds
Started Aug 13 06:35:49 PM PDT 24
Finished Aug 13 06:37:19 PM PDT 24
Peak memory 215892 kb
Host smart-61f4045c-2881-4baa-b349-7ef4bf32f24c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1871759650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1871759650
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1409581780
Short name T1225
Test name
Test status
Simulation time 169622316 ps
CPU time 0.89 seconds
Started Aug 13 06:35:45 PM PDT 24
Finished Aug 13 06:35:46 PM PDT 24
Peak memory 207524 kb
Host smart-d96538e5-002b-4191-86e1-0bebbe68d407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14095
81780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1409581780
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3484746845
Short name T1372
Test name
Test status
Simulation time 196348652 ps
CPU time 0.97 seconds
Started Aug 13 06:35:44 PM PDT 24
Finished Aug 13 06:35:45 PM PDT 24
Peak memory 207624 kb
Host smart-2e837396-02b4-4880-a771-6bb1d5117d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34847
46845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3484746845
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.4109095024
Short name T893
Test name
Test status
Simulation time 818422710 ps
CPU time 2.24 seconds
Started Aug 13 06:35:41 PM PDT 24
Finished Aug 13 06:35:44 PM PDT 24
Peak memory 207552 kb
Host smart-d693dea2-f7a8-4f45-9e50-15380bd928a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41090
95024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.4109095024
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3300366338
Short name T722
Test name
Test status
Simulation time 2474646957 ps
CPU time 69.97 seconds
Started Aug 13 06:35:46 PM PDT 24
Finished Aug 13 06:36:56 PM PDT 24
Peak memory 217500 kb
Host smart-a5ee3c17-50c0-4c75-85ca-bdfaec26c3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33003
66338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3300366338
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.3116263958
Short name T2430
Test name
Test status
Simulation time 5713451815 ps
CPU time 53.98 seconds
Started Aug 13 06:35:33 PM PDT 24
Finished Aug 13 06:36:27 PM PDT 24
Peak memory 207720 kb
Host smart-da417070-687b-4ba5-a39c-8781ae51b1b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116263958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.3116263958
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_tx_rx_disruption.2320542276
Short name T718
Test name
Test status
Simulation time 475744947 ps
CPU time 1.45 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 207560 kb
Host smart-6a5959b9-766c-4389-9dfe-80bbe06adaad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320542276 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.usbdev_tx_rx_disruption.2320542276
Directory /workspace/14.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/140.usbdev_endpoint_types.1613713035
Short name T418
Test name
Test status
Simulation time 372381359 ps
CPU time 1.38 seconds
Started Aug 13 06:41:34 PM PDT 24
Finished Aug 13 06:41:35 PM PDT 24
Peak memory 207492 kb
Host smart-558363bd-0ca5-429b-877f-39c0eb6a0d8b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1613713035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.1613713035
Directory /workspace/140.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/140.usbdev_tx_rx_disruption.2144992876
Short name T2865
Test name
Test status
Simulation time 517966014 ps
CPU time 1.48 seconds
Started Aug 13 06:41:29 PM PDT 24
Finished Aug 13 06:41:30 PM PDT 24
Peak memory 207620 kb
Host smart-63c5a9d1-da05-4f94-9190-f36342e9ea1e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144992876 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.usbdev_tx_rx_disruption.2144992876
Directory /workspace/140.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/141.usbdev_endpoint_types.1303793959
Short name T437
Test name
Test status
Simulation time 300784791 ps
CPU time 1.12 seconds
Started Aug 13 06:41:16 PM PDT 24
Finished Aug 13 06:41:17 PM PDT 24
Peak memory 207552 kb
Host smart-72402a2a-1596-44be-938a-cd12246139d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1303793959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.1303793959
Directory /workspace/141.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/141.usbdev_tx_rx_disruption.1615764791
Short name T1476
Test name
Test status
Simulation time 618087214 ps
CPU time 1.63 seconds
Started Aug 13 06:41:16 PM PDT 24
Finished Aug 13 06:41:18 PM PDT 24
Peak memory 207572 kb
Host smart-51c241bf-9baa-4df1-ac13-33282e76aaee
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615764791 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.usbdev_tx_rx_disruption.1615764791
Directory /workspace/141.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/142.usbdev_endpoint_types.2000911809
Short name T1060
Test name
Test status
Simulation time 150836652 ps
CPU time 0.86 seconds
Started Aug 13 06:41:14 PM PDT 24
Finished Aug 13 06:41:15 PM PDT 24
Peak memory 207452 kb
Host smart-6e2910fa-d05f-452c-b528-9bf5c23ec54d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2000911809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.2000911809
Directory /workspace/142.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/142.usbdev_tx_rx_disruption.2816091783
Short name T3617
Test name
Test status
Simulation time 577448323 ps
CPU time 1.56 seconds
Started Aug 13 06:41:35 PM PDT 24
Finished Aug 13 06:41:37 PM PDT 24
Peak memory 207616 kb
Host smart-9bee4935-092f-4e60-b3cd-5f1dab00bc7d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816091783 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.usbdev_tx_rx_disruption.2816091783
Directory /workspace/142.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/143.usbdev_endpoint_types.3763873201
Short name T3588
Test name
Test status
Simulation time 301793361 ps
CPU time 1.11 seconds
Started Aug 13 06:41:13 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207504 kb
Host smart-ceb5e899-2976-46ca-ad89-550e5fd0f94b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3763873201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.3763873201
Directory /workspace/143.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/143.usbdev_tx_rx_disruption.4244129405
Short name T2834
Test name
Test status
Simulation time 492728040 ps
CPU time 1.5 seconds
Started Aug 13 06:41:36 PM PDT 24
Finished Aug 13 06:41:43 PM PDT 24
Peak memory 207596 kb
Host smart-82cd405f-3304-45a0-9910-1397fd61ae88
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244129405 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.usbdev_tx_rx_disruption.4244129405
Directory /workspace/143.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/144.usbdev_endpoint_types.2990681823
Short name T479
Test name
Test status
Simulation time 294870637 ps
CPU time 1.03 seconds
Started Aug 13 06:41:21 PM PDT 24
Finished Aug 13 06:41:22 PM PDT 24
Peak memory 207568 kb
Host smart-69f117ff-f70a-496b-a0f1-46bb03c6a1c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2990681823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.2990681823
Directory /workspace/144.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_tx_rx_disruption.1874795324
Short name T2737
Test name
Test status
Simulation time 540990320 ps
CPU time 1.63 seconds
Started Aug 13 06:41:13 PM PDT 24
Finished Aug 13 06:41:15 PM PDT 24
Peak memory 207496 kb
Host smart-14f0460a-b544-4a05-ae76-8155c0197758
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874795324 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.usbdev_tx_rx_disruption.1874795324
Directory /workspace/144.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/145.usbdev_tx_rx_disruption.1904570143
Short name T2807
Test name
Test status
Simulation time 515677639 ps
CPU time 1.52 seconds
Started Aug 13 06:41:16 PM PDT 24
Finished Aug 13 06:41:17 PM PDT 24
Peak memory 207560 kb
Host smart-d383b465-ac8b-4e77-ab0a-a073806e0f65
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904570143 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.usbdev_tx_rx_disruption.1904570143
Directory /workspace/145.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/146.usbdev_endpoint_types.2526187803
Short name T468
Test name
Test status
Simulation time 187035051 ps
CPU time 0.94 seconds
Started Aug 13 06:41:29 PM PDT 24
Finished Aug 13 06:41:30 PM PDT 24
Peak memory 207452 kb
Host smart-60e68a3f-c9b6-4ebd-aa05-6f6277b94fd2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2526187803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.2526187803
Directory /workspace/146.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/146.usbdev_tx_rx_disruption.3456803086
Short name T1994
Test name
Test status
Simulation time 490838353 ps
CPU time 1.71 seconds
Started Aug 13 06:41:35 PM PDT 24
Finished Aug 13 06:41:37 PM PDT 24
Peak memory 207496 kb
Host smart-cff22777-f7e5-49f3-a7f4-5f354dd22d7d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456803086 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.usbdev_tx_rx_disruption.3456803086
Directory /workspace/146.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/147.usbdev_tx_rx_disruption.503775300
Short name T3479
Test name
Test status
Simulation time 586327252 ps
CPU time 1.84 seconds
Started Aug 13 06:41:37 PM PDT 24
Finished Aug 13 06:41:39 PM PDT 24
Peak memory 207576 kb
Host smart-e913c181-419a-4be9-a62b-d09da29fe66e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503775300 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 147.usbdev_tx_rx_disruption.503775300
Directory /workspace/147.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/148.usbdev_endpoint_types.3486801909
Short name T2929
Test name
Test status
Simulation time 628159635 ps
CPU time 1.68 seconds
Started Aug 13 06:41:31 PM PDT 24
Finished Aug 13 06:41:33 PM PDT 24
Peak memory 207572 kb
Host smart-b039520b-2403-4152-9605-7d3fcdd75e29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3486801909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.3486801909
Directory /workspace/148.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/148.usbdev_tx_rx_disruption.592863450
Short name T1596
Test name
Test status
Simulation time 538852051 ps
CPU time 1.8 seconds
Started Aug 13 06:41:32 PM PDT 24
Finished Aug 13 06:41:34 PM PDT 24
Peak memory 207592 kb
Host smart-8200110a-4f82-4e23-acc6-f33b0eba51a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592863450 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 148.usbdev_tx_rx_disruption.592863450
Directory /workspace/148.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/149.usbdev_endpoint_types.3341198537
Short name T365
Test name
Test status
Simulation time 247754568 ps
CPU time 1.01 seconds
Started Aug 13 06:41:28 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 207460 kb
Host smart-cd59813b-1a1c-4885-972c-c4fb41a3bbe1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3341198537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.3341198537
Directory /workspace/149.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/149.usbdev_tx_rx_disruption.358664567
Short name T207
Test name
Test status
Simulation time 460815942 ps
CPU time 1.69 seconds
Started Aug 13 06:41:24 PM PDT 24
Finished Aug 13 06:41:26 PM PDT 24
Peak memory 207520 kb
Host smart-b94abeab-09c4-439d-91d8-89e1bfe822f0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358664567 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 149.usbdev_tx_rx_disruption.358664567
Directory /workspace/149.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.382362001
Short name T3310
Test name
Test status
Simulation time 45336460 ps
CPU time 0.64 seconds
Started Aug 13 06:35:54 PM PDT 24
Finished Aug 13 06:35:55 PM PDT 24
Peak memory 207480 kb
Host smart-ae9a2343-327e-4c74-a82c-c6815727f1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=382362001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.382362001
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2766768509
Short name T1889
Test name
Test status
Simulation time 9500095750 ps
CPU time 12.06 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:36:00 PM PDT 24
Peak memory 207828 kb
Host smart-b6303478-90f9-419d-8c19-3540a03ee12d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766768509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.2766768509
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.528382009
Short name T2790
Test name
Test status
Simulation time 19323260565 ps
CPU time 23.26 seconds
Started Aug 13 06:35:50 PM PDT 24
Finished Aug 13 06:36:13 PM PDT 24
Peak memory 207772 kb
Host smart-3fae82b8-618c-4c8a-aa02-9c732945a0c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=528382009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.528382009
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3391635414
Short name T825
Test name
Test status
Simulation time 180830563 ps
CPU time 0.9 seconds
Started Aug 13 06:35:49 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 207372 kb
Host smart-25f281bd-53d1-4736-acac-caa5c6ab9455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33916
35414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3391635414
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.4107225709
Short name T2058
Test name
Test status
Simulation time 154536653 ps
CPU time 0.85 seconds
Started Aug 13 06:35:49 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 207600 kb
Host smart-e32845ae-08e7-4a68-91cc-9dc6684f518b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41072
25709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.4107225709
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.859798264
Short name T602
Test name
Test status
Simulation time 373259340 ps
CPU time 1.38 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:35:49 PM PDT 24
Peak memory 207572 kb
Host smart-92ad3d4e-49b4-4f0d-9d78-25937d7b614c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85979
8264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.859798264
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3813709907
Short name T2254
Test name
Test status
Simulation time 489593520 ps
CPU time 1.43 seconds
Started Aug 13 06:35:49 PM PDT 24
Finished Aug 13 06:35:51 PM PDT 24
Peak memory 207520 kb
Host smart-bc7c24ca-0b91-490f-bcdc-a7ece97380d3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3813709907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3813709907
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.1209586327
Short name T2342
Test name
Test status
Simulation time 45741431077 ps
CPU time 73.94 seconds
Started Aug 13 06:35:52 PM PDT 24
Finished Aug 13 06:37:06 PM PDT 24
Peak memory 207836 kb
Host smart-8bf985c6-dd05-46f6-b15b-489ebee6d3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12095
86327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.1209586327
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.2026182205
Short name T1962
Test name
Test status
Simulation time 1262730894 ps
CPU time 29.81 seconds
Started Aug 13 06:35:53 PM PDT 24
Finished Aug 13 06:36:23 PM PDT 24
Peak memory 207772 kb
Host smart-7a5cbd72-c0c5-4d96-aa79-fe378d0d2a43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026182205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.2026182205
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2722879463
Short name T1551
Test name
Test status
Simulation time 631307411 ps
CPU time 1.67 seconds
Started Aug 13 06:35:53 PM PDT 24
Finished Aug 13 06:35:55 PM PDT 24
Peak memory 207580 kb
Host smart-def8d8e2-04c6-40a5-9d15-78f019b6c5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27228
79463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2722879463
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1287196853
Short name T2283
Test name
Test status
Simulation time 143864652 ps
CPU time 0.82 seconds
Started Aug 13 06:35:55 PM PDT 24
Finished Aug 13 06:35:56 PM PDT 24
Peak memory 207588 kb
Host smart-d9d62fb9-f51a-4ad6-932b-529f01f17ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12871
96853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1287196853
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2510228769
Short name T1603
Test name
Test status
Simulation time 42089186 ps
CPU time 0.71 seconds
Started Aug 13 06:35:53 PM PDT 24
Finished Aug 13 06:35:54 PM PDT 24
Peak memory 207508 kb
Host smart-91e62a4e-e4e2-4419-9224-e202c5f099c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25102
28769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2510228769
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3672568858
Short name T618
Test name
Test status
Simulation time 857341498 ps
CPU time 2.23 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 207792 kb
Host smart-095ded70-0c53-40cd-bba3-4a5b9e204de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36725
68858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3672568858
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_types.768078085
Short name T616
Test name
Test status
Simulation time 142682290 ps
CPU time 0.85 seconds
Started Aug 13 06:36:15 PM PDT 24
Finished Aug 13 06:36:16 PM PDT 24
Peak memory 207680 kb
Host smart-e2e1d433-bee3-431d-8cfb-64256e5bf9fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=768078085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.768078085
Directory /workspace/15.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2654409985
Short name T2086
Test name
Test status
Simulation time 177718106 ps
CPU time 2.01 seconds
Started Aug 13 06:35:53 PM PDT 24
Finished Aug 13 06:35:55 PM PDT 24
Peak memory 207692 kb
Host smart-cd236600-fc30-4803-87bf-d86f31bbc9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26544
09985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2654409985
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2238783265
Short name T2900
Test name
Test status
Simulation time 226484802 ps
CPU time 1.14 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 215892 kb
Host smart-4eda8de0-7300-48e8-b2e2-bfc3c7893c55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2238783265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2238783265
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.467685805
Short name T2943
Test name
Test status
Simulation time 148342952 ps
CPU time 0.84 seconds
Started Aug 13 06:36:05 PM PDT 24
Finished Aug 13 06:36:06 PM PDT 24
Peak memory 207608 kb
Host smart-fdb05c54-58dd-45f7-b007-41d4c2271356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46768
5805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.467685805
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3774029109
Short name T671
Test name
Test status
Simulation time 268525206 ps
CPU time 1.03 seconds
Started Aug 13 06:35:46 PM PDT 24
Finished Aug 13 06:35:47 PM PDT 24
Peak memory 207424 kb
Host smart-399e1712-5ac8-4a40-9a54-c4ebc2f8a0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37740
29109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3774029109
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3745977851
Short name T2519
Test name
Test status
Simulation time 3824192917 ps
CPU time 107.04 seconds
Started Aug 13 06:35:54 PM PDT 24
Finished Aug 13 06:37:41 PM PDT 24
Peak memory 218428 kb
Host smart-047c859b-a79d-471d-9f7f-37a5631e644a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3745977851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3745977851
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.3431956888
Short name T3251
Test name
Test status
Simulation time 10058774252 ps
CPU time 67.6 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:36:55 PM PDT 24
Peak memory 207812 kb
Host smart-fc194e7a-bddd-4d63-af90-705188232adb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3431956888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.3431956888
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.576056494
Short name T2546
Test name
Test status
Simulation time 254416979 ps
CPU time 1.22 seconds
Started Aug 13 06:36:05 PM PDT 24
Finished Aug 13 06:36:07 PM PDT 24
Peak memory 207616 kb
Host smart-5ec3c6b3-0f31-47f6-b90c-b4d118018bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57605
6494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.576056494
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.512988480
Short name T2589
Test name
Test status
Simulation time 32671407434 ps
CPU time 48.36 seconds
Started Aug 13 06:35:47 PM PDT 24
Finished Aug 13 06:36:35 PM PDT 24
Peak memory 207772 kb
Host smart-192d3c68-b483-4f1d-a923-1a24fdacd49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51298
8480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.512988480
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3977485913
Short name T892
Test name
Test status
Simulation time 11348768212 ps
CPU time 14.66 seconds
Started Aug 13 06:36:06 PM PDT 24
Finished Aug 13 06:36:21 PM PDT 24
Peak memory 207756 kb
Host smart-f76d17e4-2617-4fab-b769-0d0f0f2186b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39774
85913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3977485913
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2151292266
Short name T687
Test name
Test status
Simulation time 3249795074 ps
CPU time 31.85 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:36:20 PM PDT 24
Peak memory 217424 kb
Host smart-9e5205a9-a29b-46c7-8d47-64044660a3a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2151292266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2151292266
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2478689559
Short name T3629
Test name
Test status
Simulation time 2355647172 ps
CPU time 69.37 seconds
Started Aug 13 06:35:56 PM PDT 24
Finished Aug 13 06:37:05 PM PDT 24
Peak memory 217272 kb
Host smart-12e7f128-baed-4e12-8ab0-e25267e0d5a5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2478689559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2478689559
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3745852319
Short name T1014
Test name
Test status
Simulation time 269216464 ps
CPU time 1.08 seconds
Started Aug 13 06:36:00 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 207640 kb
Host smart-9360ce9c-67d4-4c54-85bb-514727cdf0a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3745852319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3745852319
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1004720009
Short name T2917
Test name
Test status
Simulation time 242947212 ps
CPU time 0.96 seconds
Started Aug 13 06:35:49 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 207388 kb
Host smart-d238c9d8-24d4-443a-9f07-5f32a2e28419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10047
20009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1004720009
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.2782876852
Short name T3027
Test name
Test status
Simulation time 3082459366 ps
CPU time 87.29 seconds
Started Aug 13 06:35:50 PM PDT 24
Finished Aug 13 06:37:17 PM PDT 24
Peak memory 217704 kb
Host smart-352d22ed-b9bb-422e-bef9-00ba8f6fc2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27828
76852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.2782876852
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3483229011
Short name T2202
Test name
Test status
Simulation time 2247797921 ps
CPU time 17.83 seconds
Started Aug 13 06:35:47 PM PDT 24
Finished Aug 13 06:36:05 PM PDT 24
Peak memory 217304 kb
Host smart-c9e22426-adf9-4bc2-843d-004bbed9d197
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3483229011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3483229011
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.203246138
Short name T767
Test name
Test status
Simulation time 162077408 ps
CPU time 0.91 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 207440 kb
Host smart-c483a9d0-2f40-4b85-811c-9c7e8933a317
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=203246138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.203246138
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1488242160
Short name T2341
Test name
Test status
Simulation time 167289467 ps
CPU time 0.88 seconds
Started Aug 13 06:35:52 PM PDT 24
Finished Aug 13 06:35:53 PM PDT 24
Peak memory 207452 kb
Host smart-12de7dec-37ff-4a52-9fb6-2aed73339bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14882
42160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1488242160
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3584961295
Short name T151
Test name
Test status
Simulation time 194201904 ps
CPU time 0.89 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:35:49 PM PDT 24
Peak memory 207496 kb
Host smart-9424d81b-9678-4624-b03f-2466af7f788d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35849
61295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3584961295
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.356774106
Short name T1543
Test name
Test status
Simulation time 179891496 ps
CPU time 0.91 seconds
Started Aug 13 06:35:52 PM PDT 24
Finished Aug 13 06:35:53 PM PDT 24
Peak memory 207544 kb
Host smart-cec5dc2d-ebd0-489d-a8e4-ad2ce6724002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35677
4106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.356774106
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1377871065
Short name T1594
Test name
Test status
Simulation time 177514329 ps
CPU time 0.94 seconds
Started Aug 13 06:35:52 PM PDT 24
Finished Aug 13 06:35:53 PM PDT 24
Peak memory 207476 kb
Host smart-0f1d9383-e2cd-4f34-9efb-208b2680a8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13778
71065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1377871065
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.412623434
Short name T3314
Test name
Test status
Simulation time 163064434 ps
CPU time 0.91 seconds
Started Aug 13 06:35:52 PM PDT 24
Finished Aug 13 06:35:53 PM PDT 24
Peak memory 207568 kb
Host smart-03398888-6c5b-4518-89d6-726ff1f98989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41262
3434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.412623434
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1585254601
Short name T1158
Test name
Test status
Simulation time 209457132 ps
CPU time 0.92 seconds
Started Aug 13 06:35:49 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 207468 kb
Host smart-41a63ccc-8cf3-44fc-8758-14223ef7de28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15852
54601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1585254601
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2085621401
Short name T908
Test name
Test status
Simulation time 235390382 ps
CPU time 1.03 seconds
Started Aug 13 06:35:55 PM PDT 24
Finished Aug 13 06:35:56 PM PDT 24
Peak memory 207576 kb
Host smart-4a2661f5-3aca-4f89-b029-a9316604ae80
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2085621401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2085621401
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.588174072
Short name T2742
Test name
Test status
Simulation time 166306702 ps
CPU time 0.86 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:35:49 PM PDT 24
Peak memory 207500 kb
Host smart-496a1e59-3f7d-4b4e-80b9-023ff66bc5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58817
4072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.588174072
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3634935871
Short name T3244
Test name
Test status
Simulation time 46970453 ps
CPU time 0.72 seconds
Started Aug 13 06:35:54 PM PDT 24
Finished Aug 13 06:35:54 PM PDT 24
Peak memory 207580 kb
Host smart-8224a10f-24b1-41ca-be79-e996e09ce3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36349
35871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3634935871
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3971321720
Short name T3237
Test name
Test status
Simulation time 10423335079 ps
CPU time 27.47 seconds
Started Aug 13 06:36:00 PM PDT 24
Finished Aug 13 06:36:27 PM PDT 24
Peak memory 224308 kb
Host smart-228b132e-43ca-49bf-a5f9-7c5539106f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
21720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3971321720
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.306974426
Short name T3271
Test name
Test status
Simulation time 165634438 ps
CPU time 0.91 seconds
Started Aug 13 06:35:52 PM PDT 24
Finished Aug 13 06:35:53 PM PDT 24
Peak memory 207592 kb
Host smart-470f809b-cd7d-4315-bd84-87bff1f85f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30697
4426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.306974426
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1615000334
Short name T3567
Test name
Test status
Simulation time 230353720 ps
CPU time 0.96 seconds
Started Aug 13 06:35:54 PM PDT 24
Finished Aug 13 06:35:55 PM PDT 24
Peak memory 207492 kb
Host smart-b35b74ff-d219-48a4-9c65-e80888973ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16150
00334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1615000334
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3143367646
Short name T1855
Test name
Test status
Simulation time 209710107 ps
CPU time 0.99 seconds
Started Aug 13 06:35:53 PM PDT 24
Finished Aug 13 06:35:54 PM PDT 24
Peak memory 207500 kb
Host smart-cb1af662-2bce-48d7-b6a4-15ddf024f892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31433
67646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3143367646
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1418317959
Short name T1077
Test name
Test status
Simulation time 175671444 ps
CPU time 0.92 seconds
Started Aug 13 06:36:06 PM PDT 24
Finished Aug 13 06:36:07 PM PDT 24
Peak memory 207424 kb
Host smart-9c9bd380-c30e-4cdd-b310-cea0353ec0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14183
17959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1418317959
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_resume_link_active.3452917684
Short name T2731
Test name
Test status
Simulation time 20165019487 ps
CPU time 24.08 seconds
Started Aug 13 06:35:53 PM PDT 24
Finished Aug 13 06:36:17 PM PDT 24
Peak memory 207652 kb
Host smart-031d2cf7-80b3-4616-9d30-cb33cd3902cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
17684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.3452917684
Directory /workspace/15.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.175282582
Short name T2558
Test name
Test status
Simulation time 149103922 ps
CPU time 0.86 seconds
Started Aug 13 06:35:47 PM PDT 24
Finished Aug 13 06:35:48 PM PDT 24
Peak memory 207412 kb
Host smart-f7fad899-e328-4c19-b9ac-fe86319bc717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528
2582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.175282582
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.922637011
Short name T681
Test name
Test status
Simulation time 149171716 ps
CPU time 0.81 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:35:49 PM PDT 24
Peak memory 207432 kb
Host smart-b97065bb-15b4-43b2-b0a1-ca510a65404f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92263
7011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.922637011
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1384227653
Short name T1205
Test name
Test status
Simulation time 159202324 ps
CPU time 0.9 seconds
Started Aug 13 06:35:52 PM PDT 24
Finished Aug 13 06:35:53 PM PDT 24
Peak memory 207536 kb
Host smart-f29fe13c-7279-450f-9d45-08b420b4d400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13842
27653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1384227653
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1053451665
Short name T2471
Test name
Test status
Simulation time 221144170 ps
CPU time 1.03 seconds
Started Aug 13 06:35:52 PM PDT 24
Finished Aug 13 06:35:53 PM PDT 24
Peak memory 207484 kb
Host smart-c184ba35-9c2f-46e1-aada-3e01eb1a5db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10534
51665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1053451665
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.101726678
Short name T1341
Test name
Test status
Simulation time 2262286821 ps
CPU time 18.28 seconds
Started Aug 13 06:36:04 PM PDT 24
Finished Aug 13 06:36:23 PM PDT 24
Peak memory 217828 kb
Host smart-64436ef8-adb1-475e-a948-6c767991c320
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=101726678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.101726678
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3730262088
Short name T2131
Test name
Test status
Simulation time 178695938 ps
CPU time 0.89 seconds
Started Aug 13 06:35:50 PM PDT 24
Finished Aug 13 06:35:51 PM PDT 24
Peak memory 207516 kb
Host smart-2fe56340-61e6-4961-bd31-a00ce2a44531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37302
62088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3730262088
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.4176244669
Short name T698
Test name
Test status
Simulation time 156033541 ps
CPU time 0.9 seconds
Started Aug 13 06:35:50 PM PDT 24
Finished Aug 13 06:35:51 PM PDT 24
Peak memory 207528 kb
Host smart-106a1e5b-c721-4416-bb86-053b4898db4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41762
44669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.4176244669
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3151920285
Short name T2701
Test name
Test status
Simulation time 1267762447 ps
CPU time 3.12 seconds
Started Aug 13 06:36:06 PM PDT 24
Finished Aug 13 06:36:09 PM PDT 24
Peak memory 207700 kb
Host smart-ac958e00-f351-4b1d-9827-1f344b739a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31519
20285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3151920285
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.715043208
Short name T1022
Test name
Test status
Simulation time 2216679075 ps
CPU time 65.44 seconds
Started Aug 13 06:35:53 PM PDT 24
Finished Aug 13 06:36:58 PM PDT 24
Peak memory 217136 kb
Host smart-923928ca-0696-4735-9535-09474065b737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71504
3208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.715043208
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.1227324692
Short name T2217
Test name
Test status
Simulation time 1191593533 ps
CPU time 26.15 seconds
Started Aug 13 06:36:06 PM PDT 24
Finished Aug 13 06:36:32 PM PDT 24
Peak memory 207588 kb
Host smart-f5db65bd-d6ba-4dbb-af96-12f0f6f3a510
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227324692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.1227324692
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_tx_rx_disruption.3395070533
Short name T2016
Test name
Test status
Simulation time 462551354 ps
CPU time 1.41 seconds
Started Aug 13 06:35:56 PM PDT 24
Finished Aug 13 06:35:58 PM PDT 24
Peak memory 207568 kb
Host smart-7c2058cc-0e2b-4a03-aa22-04e972321d53
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395070533 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.usbdev_tx_rx_disruption.3395070533
Directory /workspace/15.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/150.usbdev_endpoint_types.2925350560
Short name T3103
Test name
Test status
Simulation time 299638865 ps
CPU time 1.14 seconds
Started Aug 13 06:41:21 PM PDT 24
Finished Aug 13 06:41:22 PM PDT 24
Peak memory 207460 kb
Host smart-4fc816b4-067c-4f14-9b50-3e10e04b6b1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2925350560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.2925350560
Directory /workspace/150.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/150.usbdev_tx_rx_disruption.3326563944
Short name T240
Test name
Test status
Simulation time 628358774 ps
CPU time 1.6 seconds
Started Aug 13 06:41:11 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 207592 kb
Host smart-56f32343-0869-403b-960b-b97f29a28220
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326563944 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.usbdev_tx_rx_disruption.3326563944
Directory /workspace/150.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/151.usbdev_endpoint_types.1423198518
Short name T447
Test name
Test status
Simulation time 420908199 ps
CPU time 1.33 seconds
Started Aug 13 06:41:40 PM PDT 24
Finished Aug 13 06:41:41 PM PDT 24
Peak memory 207476 kb
Host smart-ece734fd-d0f1-46ea-acf5-902acc73ff8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1423198518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.1423198518
Directory /workspace/151.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/151.usbdev_tx_rx_disruption.2748576355
Short name T659
Test name
Test status
Simulation time 572270455 ps
CPU time 1.57 seconds
Started Aug 13 06:41:36 PM PDT 24
Finished Aug 13 06:41:38 PM PDT 24
Peak memory 207572 kb
Host smart-74e68541-b67f-450c-887e-dcbc8812cece
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748576355 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.usbdev_tx_rx_disruption.2748576355
Directory /workspace/151.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/152.usbdev_endpoint_types.317207823
Short name T2721
Test name
Test status
Simulation time 203378653 ps
CPU time 0.95 seconds
Started Aug 13 06:41:38 PM PDT 24
Finished Aug 13 06:41:39 PM PDT 24
Peak memory 207564 kb
Host smart-2c83d0d0-f7dd-4b5c-99ad-f02ba4b821b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=317207823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.317207823
Directory /workspace/152.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/152.usbdev_tx_rx_disruption.2776634689
Short name T1481
Test name
Test status
Simulation time 477492810 ps
CPU time 1.51 seconds
Started Aug 13 06:41:43 PM PDT 24
Finished Aug 13 06:41:45 PM PDT 24
Peak memory 207608 kb
Host smart-ae5542ec-ba93-42ce-ae88-9693eef79ee3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776634689 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.usbdev_tx_rx_disruption.2776634689
Directory /workspace/152.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/153.usbdev_endpoint_types.1338342663
Short name T426
Test name
Test status
Simulation time 291957539 ps
CPU time 1.1 seconds
Started Aug 13 06:41:27 PM PDT 24
Finished Aug 13 06:41:28 PM PDT 24
Peak memory 207452 kb
Host smart-89ab2e11-bc94-42cb-87f0-572e2e367f6e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1338342663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.1338342663
Directory /workspace/153.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/153.usbdev_tx_rx_disruption.1116177274
Short name T2816
Test name
Test status
Simulation time 642401646 ps
CPU time 1.8 seconds
Started Aug 13 06:41:40 PM PDT 24
Finished Aug 13 06:41:41 PM PDT 24
Peak memory 207512 kb
Host smart-911a7090-8e20-4db9-a5f1-70678df7f39f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116177274 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.usbdev_tx_rx_disruption.1116177274
Directory /workspace/153.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/154.usbdev_endpoint_types.3154875908
Short name T813
Test name
Test status
Simulation time 153105671 ps
CPU time 0.86 seconds
Started Aug 13 06:41:26 PM PDT 24
Finished Aug 13 06:41:27 PM PDT 24
Peak memory 207484 kb
Host smart-05210272-e7a9-472e-898a-dc06fec6b510
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3154875908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.3154875908
Directory /workspace/154.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/154.usbdev_tx_rx_disruption.3120720633
Short name T1625
Test name
Test status
Simulation time 673170996 ps
CPU time 1.81 seconds
Started Aug 13 06:41:35 PM PDT 24
Finished Aug 13 06:41:37 PM PDT 24
Peak memory 207504 kb
Host smart-66792963-7bb6-4076-a195-b5cb76b11cb8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120720633 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.usbdev_tx_rx_disruption.3120720633
Directory /workspace/154.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/155.usbdev_endpoint_types.1941774754
Short name T436
Test name
Test status
Simulation time 277683587 ps
CPU time 1.02 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207576 kb
Host smart-63bfed93-9a63-4aff-9f1b-0db7fd4e318f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1941774754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.1941774754
Directory /workspace/155.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_endpoint_types.3563962480
Short name T445
Test name
Test status
Simulation time 480083212 ps
CPU time 1.39 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207492 kb
Host smart-9d844f9b-74fb-4bc0-9c2e-eace3c9504c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3563962480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.3563962480
Directory /workspace/156.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_tx_rx_disruption.1058133179
Short name T1089
Test name
Test status
Simulation time 518861411 ps
CPU time 1.62 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:48 PM PDT 24
Peak memory 207628 kb
Host smart-6b7c9839-460b-45f3-a838-31e2e6a46d15
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058133179 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.usbdev_tx_rx_disruption.1058133179
Directory /workspace/156.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/157.usbdev_endpoint_types.1921255100
Short name T2910
Test name
Test status
Simulation time 151853982 ps
CPU time 0.87 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207572 kb
Host smart-3d431610-afdc-44e1-9635-9d47b7f65bec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1921255100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.1921255100
Directory /workspace/157.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/157.usbdev_tx_rx_disruption.2576321850
Short name T1375
Test name
Test status
Simulation time 585280564 ps
CPU time 1.63 seconds
Started Aug 13 06:41:29 PM PDT 24
Finished Aug 13 06:41:30 PM PDT 24
Peak memory 207496 kb
Host smart-4a1138c3-08e0-4ed1-8993-6d897c5de67e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576321850 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.usbdev_tx_rx_disruption.2576321850
Directory /workspace/157.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/158.usbdev_endpoint_types.850345911
Short name T379
Test name
Test status
Simulation time 335379231 ps
CPU time 1.11 seconds
Started Aug 13 06:41:41 PM PDT 24
Finished Aug 13 06:41:42 PM PDT 24
Peak memory 207468 kb
Host smart-0515d064-a574-4139-9931-ba8320cc7a16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=850345911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.850345911
Directory /workspace/158.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/158.usbdev_tx_rx_disruption.1825490940
Short name T775
Test name
Test status
Simulation time 575020123 ps
CPU time 1.83 seconds
Started Aug 13 06:41:50 PM PDT 24
Finished Aug 13 06:41:52 PM PDT 24
Peak memory 207608 kb
Host smart-0e2b0601-f9fb-4fe3-8a93-b37205733b6f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825490940 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.usbdev_tx_rx_disruption.1825490940
Directory /workspace/158.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/159.usbdev_endpoint_types.1136047916
Short name T467
Test name
Test status
Simulation time 339517158 ps
CPU time 1.22 seconds
Started Aug 13 06:41:33 PM PDT 24
Finished Aug 13 06:41:35 PM PDT 24
Peak memory 207592 kb
Host smart-8d12290c-4e9d-42ac-b93f-04f351fec11e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1136047916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.1136047916
Directory /workspace/159.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/159.usbdev_tx_rx_disruption.760519599
Short name T2841
Test name
Test status
Simulation time 465413744 ps
CPU time 1.5 seconds
Started Aug 13 06:41:30 PM PDT 24
Finished Aug 13 06:41:32 PM PDT 24
Peak memory 207524 kb
Host smart-c3951580-c103-4cde-868d-a4a80d79547b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760519599 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 159.usbdev_tx_rx_disruption.760519599
Directory /workspace/159.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.3339985616
Short name T2015
Test name
Test status
Simulation time 34976176 ps
CPU time 0.67 seconds
Started Aug 13 06:36:07 PM PDT 24
Finished Aug 13 06:36:08 PM PDT 24
Peak memory 207472 kb
Host smart-4ecdf1e7-08d2-4e9e-84f6-e9c6ddcfb399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3339985616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3339985616
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.842048757
Short name T3297
Test name
Test status
Simulation time 10405567915 ps
CPU time 12.22 seconds
Started Aug 13 06:35:48 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 207744 kb
Host smart-af838512-8663-4851-bfc8-06296654916a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842048757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_disconnect.842048757
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.4141067422
Short name T273
Test name
Test status
Simulation time 16323366627 ps
CPU time 18.42 seconds
Started Aug 13 06:36:08 PM PDT 24
Finished Aug 13 06:36:27 PM PDT 24
Peak memory 215916 kb
Host smart-838dc7bf-08c4-41fc-bb1b-dbad5791f893
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141067422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.4141067422
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.468468683
Short name T2002
Test name
Test status
Simulation time 24736538104 ps
CPU time 37 seconds
Started Aug 13 06:35:54 PM PDT 24
Finished Aug 13 06:36:31 PM PDT 24
Peak memory 216024 kb
Host smart-368c3780-84e0-4be2-9e99-6f6784e6aff9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468468683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_resume.468468683
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1545025659
Short name T599
Test name
Test status
Simulation time 163033211 ps
CPU time 0.91 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 207492 kb
Host smart-5aab3441-a60b-4cfa-aa8c-4324e1465468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15450
25659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1545025659
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1673262627
Short name T1938
Test name
Test status
Simulation time 158036344 ps
CPU time 0.85 seconds
Started Aug 13 06:36:03 PM PDT 24
Finished Aug 13 06:36:04 PM PDT 24
Peak memory 207468 kb
Host smart-652080c0-c19d-419d-91a2-1d9c98e841c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16732
62627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1673262627
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_device_address.478611143
Short name T2412
Test name
Test status
Simulation time 32372015119 ps
CPU time 58.53 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:36:56 PM PDT 24
Peak memory 207784 kb
Host smart-5c59c4a0-b72b-4dea-8174-8116a430e3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47861
1143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.478611143
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.1476669593
Short name T3416
Test name
Test status
Simulation time 2460683714 ps
CPU time 21.53 seconds
Started Aug 13 06:35:57 PM PDT 24
Finished Aug 13 06:36:18 PM PDT 24
Peak memory 207796 kb
Host smart-c6672000-e8ad-4acf-90eb-65664fa10ce9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476669593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.1476669593
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.992000116
Short name T1842
Test name
Test status
Simulation time 756361737 ps
CPU time 1.82 seconds
Started Aug 13 06:35:55 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 207552 kb
Host smart-dfe550d3-8bcb-4866-97ce-b037e9079204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99200
0116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.992000116
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_enable.1797704926
Short name T2953
Test name
Test status
Simulation time 67218446 ps
CPU time 0.76 seconds
Started Aug 13 06:35:55 PM PDT 24
Finished Aug 13 06:35:56 PM PDT 24
Peak memory 207496 kb
Host smart-5eabbe9f-28c0-499e-ae8f-31a9400089f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17977
04926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1797704926
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1161461157
Short name T1348
Test name
Test status
Simulation time 987637049 ps
CPU time 2.72 seconds
Started Aug 13 06:35:57 PM PDT 24
Finished Aug 13 06:36:00 PM PDT 24
Peak memory 207804 kb
Host smart-e7f0dba3-3eb8-413b-b14e-61e88d9f0929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11614
61157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1161461157
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.399428088
Short name T1904
Test name
Test status
Simulation time 174971083 ps
CPU time 1.79 seconds
Started Aug 13 06:35:57 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 207668 kb
Host smart-7117936e-56af-43a5-879c-b795ba97c6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39942
8088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.399428088
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3648132013
Short name T19
Test name
Test status
Simulation time 206548342 ps
CPU time 1.08 seconds
Started Aug 13 06:36:04 PM PDT 24
Finished Aug 13 06:36:05 PM PDT 24
Peak memory 215848 kb
Host smart-4cadd41c-ccf7-4511-aceb-5c8f2abb0931
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3648132013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3648132013
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3133438430
Short name T1326
Test name
Test status
Simulation time 142111619 ps
CPU time 0.83 seconds
Started Aug 13 06:35:56 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 207388 kb
Host smart-605e598b-6fbe-4ad9-9a4c-3daf7b65740d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31334
38430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3133438430
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4217502802
Short name T3584
Test name
Test status
Simulation time 169581057 ps
CPU time 0.88 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 207460 kb
Host smart-ba10d040-dfc2-45d6-af7d-f4b5bcdc7558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175
02802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4217502802
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.3070037088
Short name T2347
Test name
Test status
Simulation time 8436144527 ps
CPU time 61.26 seconds
Started Aug 13 06:36:05 PM PDT 24
Finished Aug 13 06:37:06 PM PDT 24
Peak memory 207772 kb
Host smart-487a38ff-f2e3-49dc-9a0d-7cc2edaa8d96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3070037088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3070037088
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1204380003
Short name T1871
Test name
Test status
Simulation time 189724769 ps
CPU time 0.91 seconds
Started Aug 13 06:36:07 PM PDT 24
Finished Aug 13 06:36:08 PM PDT 24
Peak memory 207604 kb
Host smart-ce0e63ba-3903-498b-ad08-4189d58d61d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12043
80003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1204380003
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3585279755
Short name T1019
Test name
Test status
Simulation time 34612928114 ps
CPU time 55.76 seconds
Started Aug 13 06:36:08 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207724 kb
Host smart-29e47e17-030f-4cba-8472-40d66c67c50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35852
79755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3585279755
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2297909143
Short name T2836
Test name
Test status
Simulation time 3806905650 ps
CPU time 5.99 seconds
Started Aug 13 06:36:03 PM PDT 24
Finished Aug 13 06:36:09 PM PDT 24
Peak memory 207792 kb
Host smart-e6a3e593-6f86-40e2-867d-918a656dd509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
09143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2297909143
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1077257442
Short name T1542
Test name
Test status
Simulation time 3307675470 ps
CPU time 87.6 seconds
Started Aug 13 06:36:04 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 216036 kb
Host smart-d0602a55-49ea-48a3-a237-8e9ae8a9125e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1077257442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1077257442
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.262504328
Short name T2079
Test name
Test status
Simulation time 2332555207 ps
CPU time 67.23 seconds
Started Aug 13 06:35:56 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 217496 kb
Host smart-1aebcaea-68db-4705-baee-d22edbfa7c5b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=262504328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.262504328
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1412160792
Short name T1170
Test name
Test status
Simulation time 283702373 ps
CPU time 1.09 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 207464 kb
Host smart-755b36d2-f149-43e0-a3ac-973e0247f332
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1412160792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1412160792
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3851813105
Short name T3461
Test name
Test status
Simulation time 227025238 ps
CPU time 1.04 seconds
Started Aug 13 06:36:03 PM PDT 24
Finished Aug 13 06:36:04 PM PDT 24
Peak memory 207508 kb
Host smart-bc7fae6c-1b28-40a5-adcb-7b7c9fd61fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38518
13105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3851813105
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.2356765418
Short name T2072
Test name
Test status
Simulation time 2592376915 ps
CPU time 73.27 seconds
Started Aug 13 06:36:02 PM PDT 24
Finished Aug 13 06:37:16 PM PDT 24
Peak memory 217868 kb
Host smart-58e648d3-f747-4c76-8811-628411dd85c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23567
65418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.2356765418
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3664681989
Short name T579
Test name
Test status
Simulation time 2408216750 ps
CPU time 25.37 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:36:24 PM PDT 24
Peak memory 217076 kb
Host smart-6ccdf396-b428-4836-950b-87e9b2699cf1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3664681989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3664681989
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.4243697493
Short name T3254
Test name
Test status
Simulation time 153163380 ps
CPU time 0.91 seconds
Started Aug 13 06:35:57 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 207516 kb
Host smart-417a3bc3-d8fe-497c-a0b2-f16d7ba71117
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4243697493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.4243697493
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3082748035
Short name T1517
Test name
Test status
Simulation time 154127408 ps
CPU time 0.89 seconds
Started Aug 13 06:36:04 PM PDT 24
Finished Aug 13 06:36:05 PM PDT 24
Peak memory 207492 kb
Host smart-0073f48c-e40a-43ca-94cf-a36dc4ccc4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30827
48035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3082748035
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1626752375
Short name T150
Test name
Test status
Simulation time 248065653 ps
CPU time 0.99 seconds
Started Aug 13 06:35:59 PM PDT 24
Finished Aug 13 06:36:00 PM PDT 24
Peak memory 207492 kb
Host smart-042fb301-15c6-47cd-9fc6-2bda786dba10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16267
52375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1626752375
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2100723503
Short name T2219
Test name
Test status
Simulation time 217395227 ps
CPU time 0.95 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 207524 kb
Host smart-25974add-1fc5-451f-8a08-783667292b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21007
23503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2100723503
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2446325622
Short name T2302
Test name
Test status
Simulation time 202758159 ps
CPU time 0.86 seconds
Started Aug 13 06:35:56 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 207512 kb
Host smart-55eb5720-ac6e-4e3f-a42b-3f3bdd9fabdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24463
25622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2446325622
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3241850593
Short name T899
Test name
Test status
Simulation time 259154634 ps
CPU time 1.05 seconds
Started Aug 13 06:35:59 PM PDT 24
Finished Aug 13 06:36:00 PM PDT 24
Peak memory 207528 kb
Host smart-86eade4b-12ff-4e44-89a3-f220355cba55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418
50593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3241850593
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1000832612
Short name T2158
Test name
Test status
Simulation time 153095095 ps
CPU time 0.88 seconds
Started Aug 13 06:35:56 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 207548 kb
Host smart-513f7e25-d4b7-499f-98da-f43650e32d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10008
32612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1000832612
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3834988818
Short name T942
Test name
Test status
Simulation time 189732605 ps
CPU time 0.96 seconds
Started Aug 13 06:36:01 PM PDT 24
Finished Aug 13 06:36:02 PM PDT 24
Peak memory 207560 kb
Host smart-7c6da2ce-2688-4c74-a10e-4ab47675b4af
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3834988818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3834988818
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1248882695
Short name T230
Test name
Test status
Simulation time 175130317 ps
CPU time 0.9 seconds
Started Aug 13 06:36:08 PM PDT 24
Finished Aug 13 06:36:09 PM PDT 24
Peak memory 207388 kb
Host smart-64f321c5-e8b7-46ef-afd0-25620c4600fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12488
82695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1248882695
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3381337259
Short name T768
Test name
Test status
Simulation time 37300441 ps
CPU time 0.69 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:35:58 PM PDT 24
Peak memory 207564 kb
Host smart-dff82e66-7535-456f-8c2b-b58674e5d33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33813
37259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3381337259
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.493197707
Short name T1673
Test name
Test status
Simulation time 11673295772 ps
CPU time 35.95 seconds
Started Aug 13 06:36:10 PM PDT 24
Finished Aug 13 06:36:46 PM PDT 24
Peak memory 215880 kb
Host smart-3ea85018-7465-404b-858b-a29bf81e941b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49319
7707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.493197707
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.807972480
Short name T1867
Test name
Test status
Simulation time 164878527 ps
CPU time 0.86 seconds
Started Aug 13 06:35:56 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 207584 kb
Host smart-451ec2c5-affd-44b0-80ea-8f5679b0d288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80797
2480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.807972480
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2900346869
Short name T3547
Test name
Test status
Simulation time 214493611 ps
CPU time 0.96 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:36:00 PM PDT 24
Peak memory 207452 kb
Host smart-470d369e-a963-4725-8463-e1c0a3e8e86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29003
46869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2900346869
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1672823055
Short name T2160
Test name
Test status
Simulation time 195433071 ps
CPU time 0.97 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:35:59 PM PDT 24
Peak memory 207528 kb
Host smart-37a7e9df-53fe-46a0-9b7d-5fece287f95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16728
23055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1672823055
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.2623881396
Short name T1655
Test name
Test status
Simulation time 170152922 ps
CPU time 0.93 seconds
Started Aug 13 06:35:57 PM PDT 24
Finished Aug 13 06:35:58 PM PDT 24
Peak memory 207544 kb
Host smart-5ca05818-a958-450e-a194-b67e17b496c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26238
81396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.2623881396
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_resume_link_active.2222001903
Short name T2513
Test name
Test status
Simulation time 20155906983 ps
CPU time 27.52 seconds
Started Aug 13 06:36:09 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207540 kb
Host smart-36d7453f-3f59-4ef7-9c67-4ebcec271dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22220
01903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.2222001903
Directory /workspace/16.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2233895897
Short name T3124
Test name
Test status
Simulation time 189929724 ps
CPU time 0.89 seconds
Started Aug 13 06:36:00 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 207476 kb
Host smart-b53596bb-81e8-46f2-9d9d-e396a9dd3e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22338
95897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2233895897
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_rx_full.1760294565
Short name T1730
Test name
Test status
Simulation time 326044159 ps
CPU time 1.31 seconds
Started Aug 13 06:36:00 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 207476 kb
Host smart-820039dd-7233-406a-9ad5-5fffe32135b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17602
94565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.1760294565
Directory /workspace/16.usbdev_rx_full/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1810781379
Short name T2053
Test name
Test status
Simulation time 161292195 ps
CPU time 0.92 seconds
Started Aug 13 06:36:02 PM PDT 24
Finished Aug 13 06:36:03 PM PDT 24
Peak memory 207556 kb
Host smart-ff9348ee-29d0-41fe-834b-6a34ac1926f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
81379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1810781379
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1103017842
Short name T2541
Test name
Test status
Simulation time 208708678 ps
CPU time 0.9 seconds
Started Aug 13 06:36:10 PM PDT 24
Finished Aug 13 06:36:11 PM PDT 24
Peak memory 207512 kb
Host smart-6944652a-bdc8-4b7a-b800-f025290e2f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030
17842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1103017842
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1667403331
Short name T1847
Test name
Test status
Simulation time 243161072 ps
CPU time 1.08 seconds
Started Aug 13 06:36:11 PM PDT 24
Finished Aug 13 06:36:12 PM PDT 24
Peak memory 207504 kb
Host smart-43b398c4-5f07-4ff0-b20e-f5e6241f038b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16674
03331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1667403331
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.608356950
Short name T3341
Test name
Test status
Simulation time 1933192519 ps
CPU time 14.8 seconds
Started Aug 13 06:36:08 PM PDT 24
Finished Aug 13 06:36:23 PM PDT 24
Peak memory 215848 kb
Host smart-9c436c2b-b6b4-4246-9aad-74cbdc5e797a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=608356950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.608356950
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2523238875
Short name T963
Test name
Test status
Simulation time 148435347 ps
CPU time 0.84 seconds
Started Aug 13 06:36:03 PM PDT 24
Finished Aug 13 06:36:04 PM PDT 24
Peak memory 207552 kb
Host smart-65a0366b-9513-4195-af27-f6f415948e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25232
38875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2523238875
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3312918615
Short name T2210
Test name
Test status
Simulation time 197323057 ps
CPU time 0.95 seconds
Started Aug 13 06:36:00 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 207540 kb
Host smart-ffdd73f0-2804-4ac1-87eb-7abe950bfe53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129
18615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3312918615
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3472440314
Short name T2556
Test name
Test status
Simulation time 1079605188 ps
CPU time 2.71 seconds
Started Aug 13 06:35:58 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 207732 kb
Host smart-4a130e45-5260-4b48-a5fa-b5f42b3e4d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34724
40314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3472440314
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.114038621
Short name T4
Test name
Test status
Simulation time 2540467508 ps
CPU time 75.16 seconds
Started Aug 13 06:36:03 PM PDT 24
Finished Aug 13 06:37:18 PM PDT 24
Peak memory 217420 kb
Host smart-bcf0f5a8-b071-4ec6-b5e8-b38c18eed17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11403
8621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.114038621
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.4025693009
Short name T2116
Test name
Test status
Simulation time 883498792 ps
CPU time 17.96 seconds
Started Aug 13 06:36:08 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 207640 kb
Host smart-9a780049-b208-466c-a9e2-0282e907f6f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025693009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.4025693009
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_tx_rx_disruption.2340559410
Short name T1982
Test name
Test status
Simulation time 452481337 ps
CPU time 1.39 seconds
Started Aug 13 06:36:13 PM PDT 24
Finished Aug 13 06:36:15 PM PDT 24
Peak memory 207624 kb
Host smart-18235eec-d426-48ab-8023-044456357360
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340559410 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.usbdev_tx_rx_disruption.2340559410
Directory /workspace/16.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/160.usbdev_endpoint_types.3377377023
Short name T3612
Test name
Test status
Simulation time 200544405 ps
CPU time 0.98 seconds
Started Aug 13 06:41:29 PM PDT 24
Finished Aug 13 06:41:30 PM PDT 24
Peak memory 207508 kb
Host smart-720e965c-5375-4d6c-8d92-19d478c810c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3377377023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.3377377023
Directory /workspace/160.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/160.usbdev_tx_rx_disruption.2632745905
Short name T1812
Test name
Test status
Simulation time 529837908 ps
CPU time 1.67 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207556 kb
Host smart-c9723fbd-9539-4c0e-814e-6844931ea31b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632745905 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.usbdev_tx_rx_disruption.2632745905
Directory /workspace/160.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/161.usbdev_endpoint_types.2128312906
Short name T373
Test name
Test status
Simulation time 611545029 ps
CPU time 1.55 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207496 kb
Host smart-b14855ba-b969-490b-90b5-d8b5459ad777
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2128312906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.2128312906
Directory /workspace/161.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/161.usbdev_tx_rx_disruption.359436782
Short name T203
Test name
Test status
Simulation time 492497919 ps
CPU time 1.51 seconds
Started Aug 13 06:41:41 PM PDT 24
Finished Aug 13 06:41:43 PM PDT 24
Peak memory 207608 kb
Host smart-d043b0a9-a6bf-49fa-9283-dd109c9ed9b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359436782 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 161.usbdev_tx_rx_disruption.359436782
Directory /workspace/161.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/162.usbdev_endpoint_types.2302621394
Short name T381
Test name
Test status
Simulation time 760637693 ps
CPU time 1.94 seconds
Started Aug 13 06:41:28 PM PDT 24
Finished Aug 13 06:41:30 PM PDT 24
Peak memory 207556 kb
Host smart-75f92cd5-013f-4e0d-975c-39d2f51d22ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2302621394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.2302621394
Directory /workspace/162.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/162.usbdev_tx_rx_disruption.3881863667
Short name T2814
Test name
Test status
Simulation time 521829831 ps
CPU time 1.67 seconds
Started Aug 13 06:41:38 PM PDT 24
Finished Aug 13 06:41:40 PM PDT 24
Peak memory 207452 kb
Host smart-d0a97df4-0179-461a-b39a-557ffbd86495
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881863667 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.usbdev_tx_rx_disruption.3881863667
Directory /workspace/162.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/163.usbdev_endpoint_types.2365861469
Short name T473
Test name
Test status
Simulation time 604565637 ps
CPU time 1.53 seconds
Started Aug 13 06:41:36 PM PDT 24
Finished Aug 13 06:41:37 PM PDT 24
Peak memory 207560 kb
Host smart-dde6fc14-19b0-401e-b534-d0a15ab76fd9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2365861469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.2365861469
Directory /workspace/163.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/163.usbdev_tx_rx_disruption.2767050018
Short name T1784
Test name
Test status
Simulation time 665097177 ps
CPU time 1.78 seconds
Started Aug 13 06:41:47 PM PDT 24
Finished Aug 13 06:41:49 PM PDT 24
Peak memory 207608 kb
Host smart-7e4339c2-c21a-4ae8-b996-53aadbd15875
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767050018 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.usbdev_tx_rx_disruption.2767050018
Directory /workspace/163.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/164.usbdev_tx_rx_disruption.948287741
Short name T2389
Test name
Test status
Simulation time 550903740 ps
CPU time 1.71 seconds
Started Aug 13 06:41:36 PM PDT 24
Finished Aug 13 06:41:38 PM PDT 24
Peak memory 207516 kb
Host smart-5189460d-9938-40e5-b082-4e89eb1f95c0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948287741 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 164.usbdev_tx_rx_disruption.948287741
Directory /workspace/164.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/165.usbdev_endpoint_types.2822175061
Short name T455
Test name
Test status
Simulation time 544685315 ps
CPU time 1.58 seconds
Started Aug 13 06:41:41 PM PDT 24
Finished Aug 13 06:41:43 PM PDT 24
Peak memory 207556 kb
Host smart-d9b388fb-7720-4080-816b-b858913dad56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2822175061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.2822175061
Directory /workspace/165.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/165.usbdev_tx_rx_disruption.1726807015
Short name T1583
Test name
Test status
Simulation time 554350185 ps
CPU time 1.68 seconds
Started Aug 13 06:41:40 PM PDT 24
Finished Aug 13 06:41:42 PM PDT 24
Peak memory 207600 kb
Host smart-c0658c1e-ae66-4a7c-a77c-4ed1858041ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726807015 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.usbdev_tx_rx_disruption.1726807015
Directory /workspace/165.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/166.usbdev_endpoint_types.4065294607
Short name T371
Test name
Test status
Simulation time 295541720 ps
CPU time 1.17 seconds
Started Aug 13 06:41:33 PM PDT 24
Finished Aug 13 06:41:34 PM PDT 24
Peak memory 207508 kb
Host smart-dce5199c-8407-4820-b5e7-0dc03f4a858f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4065294607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.4065294607
Directory /workspace/166.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/166.usbdev_tx_rx_disruption.2370265145
Short name T1067
Test name
Test status
Simulation time 608828173 ps
CPU time 1.57 seconds
Started Aug 13 06:41:40 PM PDT 24
Finished Aug 13 06:41:42 PM PDT 24
Peak memory 207620 kb
Host smart-2b02c189-ddd0-4af7-8fb3-436a6bfd8f63
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370265145 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.usbdev_tx_rx_disruption.2370265145
Directory /workspace/166.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/167.usbdev_endpoint_types.626736153
Short name T3089
Test name
Test status
Simulation time 714582994 ps
CPU time 1.9 seconds
Started Aug 13 06:41:43 PM PDT 24
Finished Aug 13 06:41:45 PM PDT 24
Peak memory 207484 kb
Host smart-79d21672-cabc-4d6a-b61e-4226e9aa99d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=626736153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.626736153
Directory /workspace/167.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/167.usbdev_tx_rx_disruption.3403916963
Short name T568
Test name
Test status
Simulation time 511986408 ps
CPU time 1.46 seconds
Started Aug 13 06:41:38 PM PDT 24
Finished Aug 13 06:41:40 PM PDT 24
Peak memory 207584 kb
Host smart-252cd1dd-46f8-4acf-ae51-d7dfb8fe40b0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403916963 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.usbdev_tx_rx_disruption.3403916963
Directory /workspace/167.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/168.usbdev_endpoint_types.3454039416
Short name T3018
Test name
Test status
Simulation time 224626660 ps
CPU time 0.98 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207568 kb
Host smart-45887cb3-98d6-4179-a363-208f0a834617
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3454039416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.3454039416
Directory /workspace/168.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/168.usbdev_tx_rx_disruption.861665300
Short name T2467
Test name
Test status
Simulation time 459693523 ps
CPU time 1.42 seconds
Started Aug 13 06:41:29 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 207620 kb
Host smart-6fd11ab2-20b7-4e83-b430-6298470c5191
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861665300 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 168.usbdev_tx_rx_disruption.861665300
Directory /workspace/168.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/169.usbdev_endpoint_types.2706760685
Short name T2827
Test name
Test status
Simulation time 362610380 ps
CPU time 1.15 seconds
Started Aug 13 06:41:47 PM PDT 24
Finished Aug 13 06:41:48 PM PDT 24
Peak memory 207508 kb
Host smart-c2264925-799b-4656-a392-fa6aeb54cbfc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2706760685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.2706760685
Directory /workspace/169.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/169.usbdev_tx_rx_disruption.459390484
Short name T2452
Test name
Test status
Simulation time 519865228 ps
CPU time 1.53 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207536 kb
Host smart-a2905a9d-27ef-4e9c-b068-8aaa7d4b0bf8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459390484 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 169.usbdev_tx_rx_disruption.459390484
Directory /workspace/169.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3557311301
Short name T3299
Test name
Test status
Simulation time 74649904 ps
CPU time 0.74 seconds
Started Aug 13 06:36:31 PM PDT 24
Finished Aug 13 06:36:32 PM PDT 24
Peak memory 207460 kb
Host smart-5d369109-3b0c-4d00-90b5-104b08cf2e99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3557311301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3557311301
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.647378645
Short name T3248
Test name
Test status
Simulation time 4650511725 ps
CPU time 6.54 seconds
Started Aug 13 06:36:13 PM PDT 24
Finished Aug 13 06:36:20 PM PDT 24
Peak memory 216024 kb
Host smart-f928fb70-635d-439b-ae43-99a24ba6a7e7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647378645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_disconnect.647378645
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.992835079
Short name T2971
Test name
Test status
Simulation time 19966277065 ps
CPU time 24.58 seconds
Started Aug 13 06:36:03 PM PDT 24
Finished Aug 13 06:36:27 PM PDT 24
Peak memory 207752 kb
Host smart-f0edd23f-dcbf-43cd-8c52-4f5de6318ea5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=992835079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.992835079
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3997624884
Short name T929
Test name
Test status
Simulation time 24207223526 ps
CPU time 35.65 seconds
Started Aug 13 06:36:04 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 215944 kb
Host smart-3e376301-e123-46e6-a8a5-7b5733cafb2d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997624884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.3997624884
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3481961146
Short name T3594
Test name
Test status
Simulation time 182537820 ps
CPU time 0.91 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:15 PM PDT 24
Peak memory 207452 kb
Host smart-11d11f43-c93b-473e-a225-adbece427b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34819
61146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3481961146
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1943177356
Short name T1332
Test name
Test status
Simulation time 135554398 ps
CPU time 0.94 seconds
Started Aug 13 06:36:05 PM PDT 24
Finished Aug 13 06:36:06 PM PDT 24
Peak memory 207548 kb
Host smart-c1f8224d-7f3f-4adc-a053-94d48b636d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19431
77356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1943177356
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1608448827
Short name T3564
Test name
Test status
Simulation time 197880353 ps
CPU time 1.04 seconds
Started Aug 13 06:36:11 PM PDT 24
Finished Aug 13 06:36:12 PM PDT 24
Peak memory 207616 kb
Host smart-155776e6-c9ed-483e-8e48-d7ea3fc62142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16084
48827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1608448827
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2137619831
Short name T2439
Test name
Test status
Simulation time 825900176 ps
CPU time 2.32 seconds
Started Aug 13 06:36:07 PM PDT 24
Finished Aug 13 06:36:09 PM PDT 24
Peak memory 207692 kb
Host smart-7fe04d0d-f770-44f4-84d3-b7dd3d492ac9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2137619831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2137619831
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.542272615
Short name T3419
Test name
Test status
Simulation time 43606709814 ps
CPU time 77.28 seconds
Started Aug 13 06:36:18 PM PDT 24
Finished Aug 13 06:37:36 PM PDT 24
Peak memory 207844 kb
Host smart-35ea64ca-52d4-40c7-b6f1-75db4beef7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54227
2615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.542272615
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.1347260452
Short name T873
Test name
Test status
Simulation time 2231624197 ps
CPU time 14.58 seconds
Started Aug 13 06:36:08 PM PDT 24
Finished Aug 13 06:36:23 PM PDT 24
Peak memory 207764 kb
Host smart-96dd9da7-3831-41d8-988d-9aa80d14208b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347260452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.1347260452
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2185036947
Short name T3449
Test name
Test status
Simulation time 831600757 ps
CPU time 1.84 seconds
Started Aug 13 06:36:16 PM PDT 24
Finished Aug 13 06:36:18 PM PDT 24
Peak memory 207540 kb
Host smart-5c1e4898-192d-4358-8eaf-38f71effcbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21850
36947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2185036947
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1578897131
Short name T3474
Test name
Test status
Simulation time 208465764 ps
CPU time 0.89 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:15 PM PDT 24
Peak memory 207492 kb
Host smart-083373e4-0d05-4e71-8fa0-308d5d911a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15788
97131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1578897131
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.886655695
Short name T2034
Test name
Test status
Simulation time 60389331 ps
CPU time 0.74 seconds
Started Aug 13 06:36:06 PM PDT 24
Finished Aug 13 06:36:07 PM PDT 24
Peak memory 207408 kb
Host smart-2359b012-1de8-48cb-8d77-5d70c067d606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88665
5695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.886655695
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.562290660
Short name T3582
Test name
Test status
Simulation time 934905559 ps
CPU time 2.47 seconds
Started Aug 13 06:36:09 PM PDT 24
Finished Aug 13 06:36:11 PM PDT 24
Peak memory 207736 kb
Host smart-c2d221d6-45d1-424d-9dec-870acd0af611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56229
0660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.562290660
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_types.791689779
Short name T1967
Test name
Test status
Simulation time 788609070 ps
CPU time 2.02 seconds
Started Aug 13 06:36:04 PM PDT 24
Finished Aug 13 06:36:06 PM PDT 24
Peak memory 207548 kb
Host smart-9bffd8f4-5107-43b0-ac85-78e093049518
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=791689779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.791689779
Directory /workspace/17.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2097933962
Short name T773
Test name
Test status
Simulation time 303889881 ps
CPU time 2.08 seconds
Started Aug 13 06:36:19 PM PDT 24
Finished Aug 13 06:36:21 PM PDT 24
Peak memory 207656 kb
Host smart-28fea42e-bb0c-4aba-9f9c-db8d376736ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20979
33962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2097933962
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.247056341
Short name T1034
Test name
Test status
Simulation time 183055930 ps
CPU time 0.93 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:15 PM PDT 24
Peak memory 207524 kb
Host smart-da28b137-1f1c-459f-9ec9-c5aefbbc09e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=247056341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.247056341
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2031472384
Short name T2220
Test name
Test status
Simulation time 176544057 ps
CPU time 0.88 seconds
Started Aug 13 06:36:08 PM PDT 24
Finished Aug 13 06:36:09 PM PDT 24
Peak memory 207460 kb
Host smart-8340fb83-96bd-4c10-8b8f-5bf4c6a1dec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20314
72384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2031472384
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1034897433
Short name T1315
Test name
Test status
Simulation time 223016422 ps
CPU time 0.97 seconds
Started Aug 13 06:36:11 PM PDT 24
Finished Aug 13 06:36:12 PM PDT 24
Peak memory 207492 kb
Host smart-e394f14d-26e1-4412-b60a-dcabc1552321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10348
97433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1034897433
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.3227942584
Short name T932
Test name
Test status
Simulation time 5080616145 ps
CPU time 42.85 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:57 PM PDT 24
Peak memory 218556 kb
Host smart-e6983ce5-ff39-430b-a0fe-48adadf19786
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3227942584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3227942584
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.565557796
Short name T1474
Test name
Test status
Simulation time 9998774172 ps
CPU time 74.9 seconds
Started Aug 13 06:36:13 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207820 kb
Host smart-065ab792-2c18-40a5-98ba-9bcede6fb47b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=565557796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.565557796
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3111187645
Short name T1794
Test name
Test status
Simulation time 265883850 ps
CPU time 0.99 seconds
Started Aug 13 06:36:11 PM PDT 24
Finished Aug 13 06:36:12 PM PDT 24
Peak memory 207536 kb
Host smart-d1a3f634-c2e4-4e51-b1f2-0b92a91e2a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31111
87645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3111187645
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.387359196
Short name T1432
Test name
Test status
Simulation time 12913856810 ps
CPU time 18.76 seconds
Started Aug 13 06:36:12 PM PDT 24
Finished Aug 13 06:36:31 PM PDT 24
Peak memory 207772 kb
Host smart-c9ff187c-6856-4cad-978a-538a4856f4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38735
9196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.387359196
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3170749346
Short name T741
Test name
Test status
Simulation time 9631658624 ps
CPU time 15.41 seconds
Started Aug 13 06:36:11 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 207832 kb
Host smart-8d2f2227-60eb-487b-893d-f5a3d687ff17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31707
49346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3170749346
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3765030807
Short name T3226
Test name
Test status
Simulation time 3441976824 ps
CPU time 27.2 seconds
Started Aug 13 06:36:02 PM PDT 24
Finished Aug 13 06:36:29 PM PDT 24
Peak memory 216072 kb
Host smart-71ef9db0-4a57-4967-ad3d-8e32d7a04770
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3765030807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3765030807
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1284794002
Short name T2581
Test name
Test status
Simulation time 2124610587 ps
CPU time 60.93 seconds
Started Aug 13 06:36:08 PM PDT 24
Finished Aug 13 06:37:09 PM PDT 24
Peak memory 215804 kb
Host smart-507be546-03e0-4333-be8a-562ed3d5c647
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1284794002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1284794002
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.4012757174
Short name T22
Test name
Test status
Simulation time 265581044 ps
CPU time 1.05 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:15 PM PDT 24
Peak memory 207508 kb
Host smart-6f492309-54c5-42dd-859c-d9bc431f5458
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4012757174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.4012757174
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2131873950
Short name T3137
Test name
Test status
Simulation time 222880106 ps
CPU time 0.99 seconds
Started Aug 13 06:36:09 PM PDT 24
Finished Aug 13 06:36:10 PM PDT 24
Peak memory 207512 kb
Host smart-3494780d-54cb-443c-8662-8cc1b94dfd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21318
73950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2131873950
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.2461066884
Short name T2938
Test name
Test status
Simulation time 2410334349 ps
CPU time 24.43 seconds
Started Aug 13 06:36:12 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 217788 kb
Host smart-5529ac6c-a61f-4807-852e-8f2cacbe2052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24610
66884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.2461066884
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3406074039
Short name T2977
Test name
Test status
Simulation time 3797165028 ps
CPU time 30.45 seconds
Started Aug 13 06:36:10 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 217636 kb
Host smart-e795fd02-5c51-4f1c-8b7e-02f41dd28970
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3406074039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3406074039
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.2864248402
Short name T680
Test name
Test status
Simulation time 163426801 ps
CPU time 0.88 seconds
Started Aug 13 06:36:10 PM PDT 24
Finished Aug 13 06:36:11 PM PDT 24
Peak memory 207516 kb
Host smart-d9d19524-a117-4226-8ee5-41074fb5a5f6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2864248402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.2864248402
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3766443672
Short name T1499
Test name
Test status
Simulation time 198429906 ps
CPU time 0.89 seconds
Started Aug 13 06:36:03 PM PDT 24
Finished Aug 13 06:36:04 PM PDT 24
Peak memory 207444 kb
Host smart-3fe5798c-4cff-4d6e-8660-91139937e7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37664
43672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3766443672
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2817269726
Short name T1469
Test name
Test status
Simulation time 151733548 ps
CPU time 0.87 seconds
Started Aug 13 06:36:00 PM PDT 24
Finished Aug 13 06:36:01 PM PDT 24
Peak memory 207516 kb
Host smart-35ffd150-144e-4490-8edc-c750004f8445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28172
69726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2817269726
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2653834259
Short name T2732
Test name
Test status
Simulation time 180252070 ps
CPU time 0.88 seconds
Started Aug 13 06:36:08 PM PDT 24
Finished Aug 13 06:36:09 PM PDT 24
Peak memory 207504 kb
Host smart-153f279e-df27-4262-b1b7-f32bc5f198a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26538
34259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2653834259
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2009545185
Short name T1162
Test name
Test status
Simulation time 159360652 ps
CPU time 0.82 seconds
Started Aug 13 06:36:10 PM PDT 24
Finished Aug 13 06:36:11 PM PDT 24
Peak memory 207580 kb
Host smart-ccbee9d7-d597-4603-855e-1c5729dbbc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20095
45185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2009545185
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3381911842
Short name T2830
Test name
Test status
Simulation time 218198362 ps
CPU time 0.91 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:15 PM PDT 24
Peak memory 207600 kb
Host smart-4b4b4721-968e-4d54-8811-f6b6b11df7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33819
11842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3381911842
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.2544338536
Short name T2748
Test name
Test status
Simulation time 230345907 ps
CPU time 1.09 seconds
Started Aug 13 06:36:09 PM PDT 24
Finished Aug 13 06:36:11 PM PDT 24
Peak memory 207612 kb
Host smart-15747c59-6d69-4bf3-bef3-7000ad43efca
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2544338536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.2544338536
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4270219933
Short name T3543
Test name
Test status
Simulation time 142238981 ps
CPU time 0.86 seconds
Started Aug 13 06:36:03 PM PDT 24
Finished Aug 13 06:36:04 PM PDT 24
Peak memory 207420 kb
Host smart-93048e56-b436-4199-bcfa-0f8fc4e4eef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42702
19933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4270219933
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2700377277
Short name T1096
Test name
Test status
Simulation time 38999882 ps
CPU time 0.73 seconds
Started Aug 13 06:36:18 PM PDT 24
Finished Aug 13 06:36:19 PM PDT 24
Peak memory 207488 kb
Host smart-88e70ee8-6619-4f41-8ac6-3ed76279686f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27003
77277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2700377277
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3436331115
Short name T301
Test name
Test status
Simulation time 11363060004 ps
CPU time 30.55 seconds
Started Aug 13 06:36:13 PM PDT 24
Finished Aug 13 06:36:44 PM PDT 24
Peak memory 215988 kb
Host smart-c4f39b02-d7bc-4998-9192-b7b71a0d9e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34363
31115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3436331115
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1223375336
Short name T2974
Test name
Test status
Simulation time 181282237 ps
CPU time 0.88 seconds
Started Aug 13 06:36:25 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 207572 kb
Host smart-f07fb763-8061-41c9-b894-49859c42b06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12233
75336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1223375336
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2410617235
Short name T557
Test name
Test status
Simulation time 220532295 ps
CPU time 1.04 seconds
Started Aug 13 06:36:25 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 207396 kb
Host smart-ecec9cbd-fad5-45c7-9a8a-6e4b90a143e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24106
17235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2410617235
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1626447894
Short name T1087
Test name
Test status
Simulation time 200824649 ps
CPU time 0.91 seconds
Started Aug 13 06:36:20 PM PDT 24
Finished Aug 13 06:36:21 PM PDT 24
Peak memory 207500 kb
Host smart-46c7be4a-2271-4aa2-9fb4-1396ff2cb6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16264
47894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1626447894
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3258958167
Short name T788
Test name
Test status
Simulation time 191907326 ps
CPU time 0.97 seconds
Started Aug 13 06:36:17 PM PDT 24
Finished Aug 13 06:36:18 PM PDT 24
Peak memory 207520 kb
Host smart-de6933ab-959e-47e0-b2e3-5b2ceffff18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32589
58167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3258958167
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_resume_link_active.199608950
Short name T1334
Test name
Test status
Simulation time 20172721431 ps
CPU time 25.83 seconds
Started Aug 13 06:36:15 PM PDT 24
Finished Aug 13 06:36:41 PM PDT 24
Peak memory 207624 kb
Host smart-e387a08f-26fd-4baa-b247-9a4dbb6b0164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19960
8950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.199608950
Directory /workspace/17.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2733120057
Short name T3158
Test name
Test status
Simulation time 134687523 ps
CPU time 0.82 seconds
Started Aug 13 06:36:15 PM PDT 24
Finished Aug 13 06:36:16 PM PDT 24
Peak memory 207456 kb
Host smart-20cbb0c3-aa9a-41ba-81bb-78bd4013d295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27331
20057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2733120057
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_rx_full.2762418991
Short name T3171
Test name
Test status
Simulation time 347729480 ps
CPU time 1.25 seconds
Started Aug 13 06:36:18 PM PDT 24
Finished Aug 13 06:36:19 PM PDT 24
Peak memory 207448 kb
Host smart-c0fb8a2a-005e-4428-b45f-8c7534e70d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27624
18991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.2762418991
Directory /workspace/17.usbdev_rx_full/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3226044888
Short name T1953
Test name
Test status
Simulation time 158985684 ps
CPU time 0.89 seconds
Started Aug 13 06:36:20 PM PDT 24
Finished Aug 13 06:36:21 PM PDT 24
Peak memory 207488 kb
Host smart-7ac9cd8e-89a1-4ebe-bab9-679392512465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260
44888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3226044888
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3044130273
Short name T1883
Test name
Test status
Simulation time 165367600 ps
CPU time 0.88 seconds
Started Aug 13 06:36:22 PM PDT 24
Finished Aug 13 06:36:23 PM PDT 24
Peak memory 207440 kb
Host smart-3f6e0910-bc80-4eae-85ed-9d8dc4959ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30441
30273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3044130273
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2168283067
Short name T2501
Test name
Test status
Simulation time 204570148 ps
CPU time 0.97 seconds
Started Aug 13 06:36:19 PM PDT 24
Finished Aug 13 06:36:20 PM PDT 24
Peak memory 207484 kb
Host smart-6875dcf8-a7d7-4262-b576-cdfc103b52cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21682
83067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2168283067
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2182644104
Short name T1912
Test name
Test status
Simulation time 1782989029 ps
CPU time 18.06 seconds
Started Aug 13 06:36:19 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 217528 kb
Host smart-f3a6deea-2875-47bd-9133-b31043e42333
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2182644104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2182644104
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3914304433
Short name T1899
Test name
Test status
Simulation time 197384953 ps
CPU time 0.89 seconds
Started Aug 13 06:36:17 PM PDT 24
Finished Aug 13 06:36:18 PM PDT 24
Peak memory 207408 kb
Host smart-10515186-94c1-4bad-83f1-fa7d710c717c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39143
04433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3914304433
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2053361755
Short name T2397
Test name
Test status
Simulation time 195567184 ps
CPU time 0.89 seconds
Started Aug 13 06:36:12 PM PDT 24
Finished Aug 13 06:36:13 PM PDT 24
Peak memory 207604 kb
Host smart-5608849f-285e-462e-97b2-8093d5263181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20533
61755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2053361755
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.3964793852
Short name T1317
Test name
Test status
Simulation time 1147145286 ps
CPU time 2.8 seconds
Started Aug 13 06:36:21 PM PDT 24
Finished Aug 13 06:36:24 PM PDT 24
Peak memory 207772 kb
Host smart-70068da5-2d8b-4cc1-83ba-aaf6a590948d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39647
93852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3964793852
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2754821168
Short name T1612
Test name
Test status
Simulation time 2338857255 ps
CPU time 24.33 seconds
Started Aug 13 06:36:17 PM PDT 24
Finished Aug 13 06:36:41 PM PDT 24
Peak memory 216072 kb
Host smart-89e6b6f4-1911-4133-a20d-b8eabe651c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27548
21168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2754821168
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.235194926
Short name T2518
Test name
Test status
Simulation time 799440902 ps
CPU time 5.16 seconds
Started Aug 13 06:36:07 PM PDT 24
Finished Aug 13 06:36:13 PM PDT 24
Peak memory 207664 kb
Host smart-8ce612f3-ee50-4912-b7a3-aebe5b998d2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235194926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_host
_handshake.235194926
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_tx_rx_disruption.3025775212
Short name T1054
Test name
Test status
Simulation time 484283293 ps
CPU time 1.5 seconds
Started Aug 13 06:36:11 PM PDT 24
Finished Aug 13 06:36:13 PM PDT 24
Peak memory 207520 kb
Host smart-309974d9-c6f1-4cf7-a7cb-876549db56f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025775212 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.usbdev_tx_rx_disruption.3025775212
Directory /workspace/17.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/170.usbdev_tx_rx_disruption.3229160831
Short name T2921
Test name
Test status
Simulation time 536005253 ps
CPU time 1.61 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207628 kb
Host smart-2c55e70b-938f-4d41-9df8-d7783cfab5b0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229160831 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.usbdev_tx_rx_disruption.3229160831
Directory /workspace/170.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/171.usbdev_endpoint_types.458568876
Short name T211
Test name
Test status
Simulation time 345995720 ps
CPU time 1.2 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207460 kb
Host smart-57beef42-0529-4845-b038-2597f4cddb81
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=458568876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.458568876
Directory /workspace/171.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_tx_rx_disruption.3648113721
Short name T3258
Test name
Test status
Simulation time 524718421 ps
CPU time 1.47 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207584 kb
Host smart-c156dc15-cc15-4d9b-b3f5-71edcbb6ffd5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648113721 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.usbdev_tx_rx_disruption.3648113721
Directory /workspace/171.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/172.usbdev_endpoint_types.2572214355
Short name T413
Test name
Test status
Simulation time 749230022 ps
CPU time 1.88 seconds
Started Aug 13 06:41:39 PM PDT 24
Finished Aug 13 06:41:42 PM PDT 24
Peak memory 207496 kb
Host smart-11c80f8d-78a6-4152-8189-08e82a6c2724
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2572214355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.2572214355
Directory /workspace/172.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/172.usbdev_tx_rx_disruption.4843730
Short name T1879
Test name
Test status
Simulation time 551043054 ps
CPU time 1.78 seconds
Started Aug 13 06:41:50 PM PDT 24
Finished Aug 13 06:41:52 PM PDT 24
Peak memory 207580 kb
Host smart-6cac6547-be40-4458-b3ca-a706fc2a420d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4843730 -assert nopostproc +UVM_TESTN
AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 172.usbdev_tx_rx_disruption.4843730
Directory /workspace/172.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/173.usbdev_endpoint_types.1410112710
Short name T470
Test name
Test status
Simulation time 317820566 ps
CPU time 1.17 seconds
Started Aug 13 06:41:50 PM PDT 24
Finished Aug 13 06:41:52 PM PDT 24
Peak memory 207564 kb
Host smart-9266dfc2-a20e-46f4-87cc-3b8a08bd1d10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1410112710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.1410112710
Directory /workspace/173.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/173.usbdev_tx_rx_disruption.1237301127
Short name T3090
Test name
Test status
Simulation time 519459234 ps
CPU time 1.6 seconds
Started Aug 13 06:41:29 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 207524 kb
Host smart-1e995f0e-3255-435c-ab77-6ef3d743048f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237301127 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.usbdev_tx_rx_disruption.1237301127
Directory /workspace/173.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/174.usbdev_tx_rx_disruption.3424577608
Short name T1073
Test name
Test status
Simulation time 556385652 ps
CPU time 1.6 seconds
Started Aug 13 06:41:41 PM PDT 24
Finished Aug 13 06:41:43 PM PDT 24
Peak memory 207580 kb
Host smart-20e35541-4a06-4c1b-972d-986dbd8bce2b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424577608 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.usbdev_tx_rx_disruption.3424577608
Directory /workspace/174.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/175.usbdev_endpoint_types.3590083366
Short name T453
Test name
Test status
Simulation time 374616580 ps
CPU time 1.18 seconds
Started Aug 13 06:41:41 PM PDT 24
Finished Aug 13 06:41:42 PM PDT 24
Peak memory 207464 kb
Host smart-31b58c97-a296-44ff-9842-1ddbc78b9633
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3590083366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.3590083366
Directory /workspace/175.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/175.usbdev_tx_rx_disruption.3891012584
Short name T1948
Test name
Test status
Simulation time 654666768 ps
CPU time 1.79 seconds
Started Aug 13 06:41:50 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207580 kb
Host smart-dfd40482-4d5f-4d9c-998a-4c02aac4da24
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891012584 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.usbdev_tx_rx_disruption.3891012584
Directory /workspace/175.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/176.usbdev_endpoint_types.3512565179
Short name T474
Test name
Test status
Simulation time 617397590 ps
CPU time 1.66 seconds
Started Aug 13 06:41:40 PM PDT 24
Finished Aug 13 06:41:42 PM PDT 24
Peak memory 207572 kb
Host smart-fb9a0bd8-ab78-40aa-a24c-f771cf87e4aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3512565179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.3512565179
Directory /workspace/176.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/176.usbdev_tx_rx_disruption.95080492
Short name T1638
Test name
Test status
Simulation time 590029657 ps
CPU time 1.89 seconds
Started Aug 13 06:41:26 PM PDT 24
Finished Aug 13 06:41:28 PM PDT 24
Peak memory 207484 kb
Host smart-15da8150-ae4b-41e5-bbdb-318fe0ac0a90
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95080492 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 176.usbdev_tx_rx_disruption.95080492
Directory /workspace/176.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/177.usbdev_endpoint_types.1730092379
Short name T2168
Test name
Test status
Simulation time 679844835 ps
CPU time 1.67 seconds
Started Aug 13 06:41:39 PM PDT 24
Finished Aug 13 06:41:41 PM PDT 24
Peak memory 207520 kb
Host smart-a15892d9-38ad-4ff3-9513-b654ce40e1bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1730092379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.1730092379
Directory /workspace/177.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/177.usbdev_tx_rx_disruption.552866262
Short name T3100
Test name
Test status
Simulation time 654301335 ps
CPU time 1.88 seconds
Started Aug 13 06:41:39 PM PDT 24
Finished Aug 13 06:41:41 PM PDT 24
Peak memory 207472 kb
Host smart-ae1f718c-8c0f-417e-a3f8-7371cbcac11f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552866262 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 177.usbdev_tx_rx_disruption.552866262
Directory /workspace/177.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/178.usbdev_endpoint_types.1613582333
Short name T457
Test name
Test status
Simulation time 299914783 ps
CPU time 1.13 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207432 kb
Host smart-7269c41d-29d7-46a8-90ac-bcb7ce676612
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1613582333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.1613582333
Directory /workspace/178.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/178.usbdev_tx_rx_disruption.802715960
Short name T2867
Test name
Test status
Simulation time 652810294 ps
CPU time 1.66 seconds
Started Aug 13 06:41:31 PM PDT 24
Finished Aug 13 06:41:33 PM PDT 24
Peak memory 207520 kb
Host smart-c61b1526-39ca-4c11-b930-1b5ea626c9d6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802715960 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 178.usbdev_tx_rx_disruption.802715960
Directory /workspace/178.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/179.usbdev_endpoint_types.1446862051
Short name T396
Test name
Test status
Simulation time 665390731 ps
CPU time 1.69 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207508 kb
Host smart-48499686-a331-4079-8de6-7e64a45802b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1446862051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.1446862051
Directory /workspace/179.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/179.usbdev_tx_rx_disruption.4099449182
Short name T1584
Test name
Test status
Simulation time 596943049 ps
CPU time 1.65 seconds
Started Aug 13 06:41:27 PM PDT 24
Finished Aug 13 06:41:29 PM PDT 24
Peak memory 207512 kb
Host smart-1ac117da-f947-43e7-8bbb-e7bc240794b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099449182 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.usbdev_tx_rx_disruption.4099449182
Directory /workspace/179.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.488287935
Short name T2343
Test name
Test status
Simulation time 44688954 ps
CPU time 0.69 seconds
Started Aug 13 06:36:25 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 207336 kb
Host smart-54dd1479-86b6-407d-8d18-98740b418e7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=488287935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.488287935
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2601256035
Short name T6
Test name
Test status
Simulation time 6032377115 ps
CPU time 8.04 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:22 PM PDT 24
Peak memory 216040 kb
Host smart-617eb814-0ea3-46e8-9706-58ca00eb9f44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601256035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.2601256035
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.970781381
Short name T537
Test name
Test status
Simulation time 21539599822 ps
CPU time 28.81 seconds
Started Aug 13 06:36:12 PM PDT 24
Finished Aug 13 06:36:41 PM PDT 24
Peak memory 207836 kb
Host smart-490caef1-dd81-4181-b0e9-fbd86ea57e02
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=970781381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.970781381
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1140614425
Short name T9
Test name
Test status
Simulation time 26175863634 ps
CPU time 32.14 seconds
Started Aug 13 06:36:16 PM PDT 24
Finished Aug 13 06:36:49 PM PDT 24
Peak memory 216004 kb
Host smart-fb5a819f-d368-413e-8d89-9acd21d50024
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140614425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.1140614425
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2440793595
Short name T3542
Test name
Test status
Simulation time 227262859 ps
CPU time 0.99 seconds
Started Aug 13 06:36:12 PM PDT 24
Finished Aug 13 06:36:13 PM PDT 24
Peak memory 207496 kb
Host smart-b007ab6e-8f0b-4511-b1c8-0032a0e030df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24407
93595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2440793595
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3264878832
Short name T1025
Test name
Test status
Simulation time 154948625 ps
CPU time 0.84 seconds
Started Aug 13 06:36:17 PM PDT 24
Finished Aug 13 06:36:18 PM PDT 24
Peak memory 207540 kb
Host smart-193f2304-ce56-4afd-a6aa-aa2d88796671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32648
78832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3264878832
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.590347644
Short name T774
Test name
Test status
Simulation time 404290623 ps
CPU time 1.49 seconds
Started Aug 13 06:36:18 PM PDT 24
Finished Aug 13 06:36:20 PM PDT 24
Peak memory 207600 kb
Host smart-3e12f7a2-a81a-4d5c-b319-814bb31b4eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59034
7644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.590347644
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3326429336
Short name T1274
Test name
Test status
Simulation time 670170633 ps
CPU time 2.12 seconds
Started Aug 13 06:36:13 PM PDT 24
Finished Aug 13 06:36:15 PM PDT 24
Peak memory 207488 kb
Host smart-399b5060-3eb8-4122-9803-a944e9b6c5b9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3326429336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3326429336
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.3112254701
Short name T2751
Test name
Test status
Simulation time 27751188321 ps
CPU time 51.83 seconds
Started Aug 13 06:36:24 PM PDT 24
Finished Aug 13 06:37:16 PM PDT 24
Peak memory 207816 kb
Host smart-5f40ec11-64c2-4726-9962-ea0048815b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31122
54701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.3112254701
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.612228105
Short name T3204
Test name
Test status
Simulation time 7009048633 ps
CPU time 47.54 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:37:22 PM PDT 24
Peak memory 207764 kb
Host smart-e1c99b15-a2a9-48f9-ad74-a2c2c5bcde60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612228105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.612228105
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.671701848
Short name T740
Test name
Test status
Simulation time 639879801 ps
CPU time 1.59 seconds
Started Aug 13 06:36:28 PM PDT 24
Finished Aug 13 06:36:29 PM PDT 24
Peak memory 207504 kb
Host smart-4940aa2f-63a7-443f-be88-5fa73c32c3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67170
1848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.671701848
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3233885957
Short name T2654
Test name
Test status
Simulation time 168478975 ps
CPU time 0.84 seconds
Started Aug 13 06:36:15 PM PDT 24
Finished Aug 13 06:36:16 PM PDT 24
Peak memory 207532 kb
Host smart-1d5e9c9c-e0f7-485d-b04b-52298eed3e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32338
85957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3233885957
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3388247229
Short name T1352
Test name
Test status
Simulation time 46789824 ps
CPU time 0.68 seconds
Started Aug 13 06:36:31 PM PDT 24
Finished Aug 13 06:36:32 PM PDT 24
Peak memory 207468 kb
Host smart-ef99d3b2-d8b4-4271-9dc9-33b70ef38dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33882
47229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3388247229
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.66297361
Short name T559
Test name
Test status
Simulation time 870674103 ps
CPU time 2.35 seconds
Started Aug 13 06:36:18 PM PDT 24
Finished Aug 13 06:36:21 PM PDT 24
Peak memory 207788 kb
Host smart-e7c0eca1-b398-4fa8-8115-035e28119d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66297
361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.66297361
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.4252530993
Short name T221
Test name
Test status
Simulation time 393457245 ps
CPU time 2.39 seconds
Started Aug 13 06:36:27 PM PDT 24
Finished Aug 13 06:36:30 PM PDT 24
Peak memory 207672 kb
Host smart-91207da0-0a70-4c70-b497-e75138c27770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42525
30993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.4252530993
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2793254403
Short name T3170
Test name
Test status
Simulation time 197816893 ps
CPU time 1.02 seconds
Started Aug 13 06:36:16 PM PDT 24
Finished Aug 13 06:36:17 PM PDT 24
Peak memory 215828 kb
Host smart-d36fd3dd-6d5d-4146-916e-5f6645b27007
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2793254403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2793254403
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1822482332
Short name T2598
Test name
Test status
Simulation time 210542133 ps
CPU time 0.9 seconds
Started Aug 13 06:36:15 PM PDT 24
Finished Aug 13 06:36:16 PM PDT 24
Peak memory 207476 kb
Host smart-be0ab726-f70b-48c4-a00d-d5dbfde58f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18224
82332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1822482332
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.518420617
Short name T1222
Test name
Test status
Simulation time 245298799 ps
CPU time 1.01 seconds
Started Aug 13 06:36:18 PM PDT 24
Finished Aug 13 06:36:20 PM PDT 24
Peak memory 207380 kb
Host smart-5642ba07-0be8-42c9-a38d-cc6898c11956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51842
0617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.518420617
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.2446580631
Short name T214
Test name
Test status
Simulation time 4841100894 ps
CPU time 149.35 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:38:44 PM PDT 24
Peak memory 216028 kb
Host smart-30ba9b51-8870-43f7-85c7-06e0fe95fe34
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2446580631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2446580631
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.3669436919
Short name T2407
Test name
Test status
Simulation time 6460772950 ps
CPU time 72.48 seconds
Started Aug 13 06:36:24 PM PDT 24
Finished Aug 13 06:37:36 PM PDT 24
Peak memory 207808 kb
Host smart-7b1f702a-1014-42d3-b50c-09027f0ea101
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3669436919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.3669436919
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3904317949
Short name T2730
Test name
Test status
Simulation time 240094042 ps
CPU time 1.02 seconds
Started Aug 13 06:36:12 PM PDT 24
Finished Aug 13 06:36:13 PM PDT 24
Peak memory 207600 kb
Host smart-567c80d9-160b-460b-9d17-379838b96b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39043
17949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3904317949
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.4212438476
Short name T60
Test name
Test status
Simulation time 31832102258 ps
CPU time 48.1 seconds
Started Aug 13 06:36:15 PM PDT 24
Finished Aug 13 06:37:04 PM PDT 24
Peak memory 207852 kb
Host smart-6951fa98-ab9a-43a2-8bd1-5c4978dcc9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42124
38476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.4212438476
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3233133043
Short name T1231
Test name
Test status
Simulation time 10093111909 ps
CPU time 15.94 seconds
Started Aug 13 06:36:29 PM PDT 24
Finished Aug 13 06:36:45 PM PDT 24
Peak memory 207828 kb
Host smart-90250fdf-286e-4d00-9a90-50c134b84ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
33043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3233133043
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.1124961613
Short name T792
Test name
Test status
Simulation time 4597025902 ps
CPU time 46.84 seconds
Started Aug 13 06:36:15 PM PDT 24
Finished Aug 13 06:37:02 PM PDT 24
Peak memory 218576 kb
Host smart-fe457d19-f577-425a-a395-dd2f13fb2d73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1124961613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1124961613
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1998303215
Short name T1934
Test name
Test status
Simulation time 1961148647 ps
CPU time 15.24 seconds
Started Aug 13 06:36:17 PM PDT 24
Finished Aug 13 06:36:32 PM PDT 24
Peak memory 217404 kb
Host smart-9010b25c-f329-4ec1-a1d0-04970be29aeb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1998303215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1998303215
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3709371707
Short name T1048
Test name
Test status
Simulation time 244301883 ps
CPU time 1.05 seconds
Started Aug 13 06:36:19 PM PDT 24
Finished Aug 13 06:36:20 PM PDT 24
Peak memory 207480 kb
Host smart-19a2708c-8c70-4a97-b8b3-c841f6d46af4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3709371707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3709371707
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3491303436
Short name T1910
Test name
Test status
Simulation time 191040064 ps
CPU time 0.96 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:16 PM PDT 24
Peak memory 207448 kb
Host smart-41c2ac30-b09b-44ba-bd04-e72c99c52c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34913
03436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3491303436
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.669335649
Short name T1485
Test name
Test status
Simulation time 2108388254 ps
CPU time 60.05 seconds
Started Aug 13 06:36:13 PM PDT 24
Finished Aug 13 06:37:14 PM PDT 24
Peak memory 224072 kb
Host smart-efddd352-606d-4ff7-b940-2b31b2b99009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66933
5649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.669335649
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.776574973
Short name T3482
Test name
Test status
Simulation time 2797135834 ps
CPU time 26.43 seconds
Started Aug 13 06:36:24 PM PDT 24
Finished Aug 13 06:36:50 PM PDT 24
Peak memory 217716 kb
Host smart-48a276b7-e4b0-48f9-a0fd-ea4af16d76a8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=776574973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.776574973
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3040703592
Short name T2424
Test name
Test status
Simulation time 152621493 ps
CPU time 0.88 seconds
Started Aug 13 06:36:12 PM PDT 24
Finished Aug 13 06:36:13 PM PDT 24
Peak memory 207516 kb
Host smart-6487f9ba-4e37-4902-a126-b4be5810c489
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3040703592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3040703592
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1464093497
Short name T3587
Test name
Test status
Simulation time 175149338 ps
CPU time 0.89 seconds
Started Aug 13 06:36:18 PM PDT 24
Finished Aug 13 06:36:19 PM PDT 24
Peak memory 207456 kb
Host smart-767274f4-83de-468e-9806-325f6ad91be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14640
93497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1464093497
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.939820517
Short name T2965
Test name
Test status
Simulation time 183017668 ps
CPU time 0.93 seconds
Started Aug 13 06:36:17 PM PDT 24
Finished Aug 13 06:36:18 PM PDT 24
Peak memory 207516 kb
Host smart-d738789b-c10e-401b-aaf2-86dad9dab427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93982
0517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.939820517
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2904100157
Short name T3096
Test name
Test status
Simulation time 157110789 ps
CPU time 0.93 seconds
Started Aug 13 06:36:24 PM PDT 24
Finished Aug 13 06:36:25 PM PDT 24
Peak memory 207416 kb
Host smart-94e25f5d-3e5f-4238-9bf3-aa55618ddf71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29041
00157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2904100157
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2469784581
Short name T3548
Test name
Test status
Simulation time 228558363 ps
CPU time 0.95 seconds
Started Aug 13 06:36:15 PM PDT 24
Finished Aug 13 06:36:16 PM PDT 24
Peak memory 207488 kb
Host smart-22e389a9-763c-4db2-a84c-cee62dc61073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24697
84581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2469784581
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1787974134
Short name T1003
Test name
Test status
Simulation time 175892724 ps
CPU time 0.91 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:15 PM PDT 24
Peak memory 207564 kb
Host smart-7b5f044e-9b64-4739-a663-717d3629f2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17879
74134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1787974134
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1663680353
Short name T2403
Test name
Test status
Simulation time 194860870 ps
CPU time 0.93 seconds
Started Aug 13 06:36:28 PM PDT 24
Finished Aug 13 06:36:29 PM PDT 24
Peak memory 207580 kb
Host smart-f763252a-cf85-41ab-98d4-af80761582a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16636
80353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1663680353
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3009347395
Short name T3036
Test name
Test status
Simulation time 246898269 ps
CPU time 1.08 seconds
Started Aug 13 06:36:32 PM PDT 24
Finished Aug 13 06:36:34 PM PDT 24
Peak memory 207580 kb
Host smart-dfa7b1ab-2f22-4c58-997d-0f44a62a0658
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3009347395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3009347395
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1218094412
Short name T2011
Test name
Test status
Simulation time 148018696 ps
CPU time 0.85 seconds
Started Aug 13 06:36:32 PM PDT 24
Finished Aug 13 06:36:33 PM PDT 24
Peak memory 207468 kb
Host smart-251566e2-5e0c-4b09-9e7b-3967565d86c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
94412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1218094412
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3614702516
Short name T2601
Test name
Test status
Simulation time 40918785 ps
CPU time 0.7 seconds
Started Aug 13 06:36:27 PM PDT 24
Finished Aug 13 06:36:28 PM PDT 24
Peak memory 207556 kb
Host smart-bc3ab668-ebc9-4905-9610-e35789bb75ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36147
02516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3614702516
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.787758480
Short name T1845
Test name
Test status
Simulation time 18541402192 ps
CPU time 46.93 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:37:22 PM PDT 24
Peak memory 215884 kb
Host smart-19015d52-bed8-4517-8bc0-603d4ad970c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78775
8480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.787758480
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1706754247
Short name T2986
Test name
Test status
Simulation time 187112788 ps
CPU time 0.97 seconds
Started Aug 13 06:36:24 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 207572 kb
Host smart-346dab91-c54b-4a58-8895-a6a0c52f04d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17067
54247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1706754247
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1812700677
Short name T1796
Test name
Test status
Simulation time 245635504 ps
CPU time 1.04 seconds
Started Aug 13 06:36:19 PM PDT 24
Finished Aug 13 06:36:20 PM PDT 24
Peak memory 207424 kb
Host smart-b8b9619e-ac69-49a2-809b-eb8f0767f214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18127
00677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1812700677
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.1355245997
Short name T2038
Test name
Test status
Simulation time 232875265 ps
CPU time 1.02 seconds
Started Aug 13 06:36:38 PM PDT 24
Finished Aug 13 06:36:39 PM PDT 24
Peak memory 207500 kb
Host smart-8cd17baa-fe17-4ec3-853c-7c007b7c074a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13552
45997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1355245997
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3389611937
Short name T926
Test name
Test status
Simulation time 185076653 ps
CPU time 0.95 seconds
Started Aug 13 06:36:31 PM PDT 24
Finished Aug 13 06:36:33 PM PDT 24
Peak memory 207536 kb
Host smart-e7113434-58a3-4af1-ac3e-a2beed6c0173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33896
11937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3389611937
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_resume_link_active.3250292617
Short name T1916
Test name
Test status
Simulation time 20174603205 ps
CPU time 22.91 seconds
Started Aug 13 06:36:29 PM PDT 24
Finished Aug 13 06:36:52 PM PDT 24
Peak memory 207612 kb
Host smart-aa1ecad5-7472-42f3-8cc3-75656ad1fcd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32502
92617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.3250292617
Directory /workspace/18.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2106928447
Short name T3492
Test name
Test status
Simulation time 145447841 ps
CPU time 0.79 seconds
Started Aug 13 06:36:21 PM PDT 24
Finished Aug 13 06:36:22 PM PDT 24
Peak memory 207404 kb
Host smart-efa54957-89fb-481c-8d17-6dec9e26ed9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21069
28447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2106928447
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_rx_full.2904976942
Short name T737
Test name
Test status
Simulation time 305876273 ps
CPU time 1.15 seconds
Started Aug 13 06:36:22 PM PDT 24
Finished Aug 13 06:36:23 PM PDT 24
Peak memory 207460 kb
Host smart-3a4cd738-7bc1-41f6-8332-c1d4929f43b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
76942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.2904976942
Directory /workspace/18.usbdev_rx_full/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.157073233
Short name T696
Test name
Test status
Simulation time 174496652 ps
CPU time 0.95 seconds
Started Aug 13 06:36:28 PM PDT 24
Finished Aug 13 06:36:29 PM PDT 24
Peak memory 207508 kb
Host smart-29567298-3a92-4403-9a73-ce8358bb5279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15707
3233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.157073233
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.356324883
Short name T1379
Test name
Test status
Simulation time 145550590 ps
CPU time 0.85 seconds
Started Aug 13 06:36:33 PM PDT 24
Finished Aug 13 06:36:34 PM PDT 24
Peak memory 207604 kb
Host smart-cc70c234-4088-44aa-b719-1d9b0f5e5551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35632
4883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.356324883
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.355703228
Short name T3046
Test name
Test status
Simulation time 223774692 ps
CPU time 1.08 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207500 kb
Host smart-232dabb8-a53e-4493-9ec7-989e4842ab12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35570
3228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.355703228
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.26015814
Short name T168
Test name
Test status
Simulation time 1931517634 ps
CPU time 15.39 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:52 PM PDT 24
Peak memory 207652 kb
Host smart-5b1d2749-e0db-4b74-9c05-143c0226932f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=26015814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.26015814
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1807441
Short name T853
Test name
Test status
Simulation time 196833006 ps
CPU time 0.95 seconds
Started Aug 13 06:36:27 PM PDT 24
Finished Aug 13 06:36:28 PM PDT 24
Peak memory 207492 kb
Host smart-ffe3e2ff-f664-425a-b4ae-66b4d35891f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18074
41 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1807441
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3240983142
Short name T1083
Test name
Test status
Simulation time 167271271 ps
CPU time 0.87 seconds
Started Aug 13 06:36:26 PM PDT 24
Finished Aug 13 06:36:27 PM PDT 24
Peak memory 207616 kb
Host smart-7a3991e1-b5b0-4b6b-9af2-48735de97f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32409
83142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3240983142
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.2337428149
Short name T3203
Test name
Test status
Simulation time 426185583 ps
CPU time 1.29 seconds
Started Aug 13 06:36:33 PM PDT 24
Finished Aug 13 06:36:34 PM PDT 24
Peak memory 207500 kb
Host smart-fd687b6a-1303-457f-a6d5-7176f75f50f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23374
28149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.2337428149
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.970136608
Short name T2523
Test name
Test status
Simulation time 3869744232 ps
CPU time 108.51 seconds
Started Aug 13 06:36:19 PM PDT 24
Finished Aug 13 06:38:08 PM PDT 24
Peak memory 217412 kb
Host smart-ca85c3b5-a04b-44db-983b-782fdc6f8162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97013
6608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.970136608
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.3700082189
Short name T1884
Test name
Test status
Simulation time 3408240500 ps
CPU time 28.62 seconds
Started Aug 13 06:36:14 PM PDT 24
Finished Aug 13 06:36:42 PM PDT 24
Peak memory 207784 kb
Host smart-2de4b2f8-80fd-4a0a-812f-f0afafb37157
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700082189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.3700082189
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_tx_rx_disruption.2874521833
Short name T888
Test name
Test status
Simulation time 598681830 ps
CPU time 1.65 seconds
Started Aug 13 06:36:31 PM PDT 24
Finished Aug 13 06:36:32 PM PDT 24
Peak memory 207552 kb
Host smart-d602c8c4-9746-44fb-bc8c-8b7dcce17e6c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874521833 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.usbdev_tx_rx_disruption.2874521833
Directory /workspace/18.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/180.usbdev_endpoint_types.2375169596
Short name T253
Test name
Test status
Simulation time 723334113 ps
CPU time 1.71 seconds
Started Aug 13 06:41:30 PM PDT 24
Finished Aug 13 06:41:32 PM PDT 24
Peak memory 207488 kb
Host smart-614d3bac-9bbc-4856-b6e6-73e4beb0b3ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2375169596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.2375169596
Directory /workspace/180.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/180.usbdev_tx_rx_disruption.173865111
Short name T3481
Test name
Test status
Simulation time 527271714 ps
CPU time 1.41 seconds
Started Aug 13 06:41:47 PM PDT 24
Finished Aug 13 06:41:48 PM PDT 24
Peak memory 207536 kb
Host smart-b72e1d3d-35c1-4ccd-84d3-d0d8387811f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173865111 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 180.usbdev_tx_rx_disruption.173865111
Directory /workspace/180.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/181.usbdev_endpoint_types.3888742747
Short name T392
Test name
Test status
Simulation time 428100553 ps
CPU time 1.31 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207528 kb
Host smart-96c7a3d5-ba44-43d0-8471-4b30f7160a65
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3888742747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.3888742747
Directory /workspace/181.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/181.usbdev_tx_rx_disruption.2499850034
Short name T717
Test name
Test status
Simulation time 538857608 ps
CPU time 1.66 seconds
Started Aug 13 06:41:26 PM PDT 24
Finished Aug 13 06:41:28 PM PDT 24
Peak memory 207500 kb
Host smart-7ae899b6-5375-41f3-8a4d-c3ac36e82103
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499850034 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.usbdev_tx_rx_disruption.2499850034
Directory /workspace/181.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/182.usbdev_endpoint_types.1455057458
Short name T428
Test name
Test status
Simulation time 275277471 ps
CPU time 1.03 seconds
Started Aug 13 06:41:47 PM PDT 24
Finished Aug 13 06:41:48 PM PDT 24
Peak memory 207484 kb
Host smart-a78cd2be-5876-4b85-b95b-2f93547e4e56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1455057458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.1455057458
Directory /workspace/182.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/182.usbdev_tx_rx_disruption.948827613
Short name T921
Test name
Test status
Simulation time 457375224 ps
CPU time 1.38 seconds
Started Aug 13 06:41:37 PM PDT 24
Finished Aug 13 06:41:38 PM PDT 24
Peak memory 207520 kb
Host smart-1227edea-83c0-4827-8f33-35e0e5937ed3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948827613 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 182.usbdev_tx_rx_disruption.948827613
Directory /workspace/182.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/183.usbdev_endpoint_types.1069596409
Short name T367
Test name
Test status
Simulation time 287994917 ps
CPU time 1.08 seconds
Started Aug 13 06:41:30 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 207556 kb
Host smart-5beea496-5c59-4729-a7b4-74ffdd3e5628
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1069596409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.1069596409
Directory /workspace/183.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/183.usbdev_tx_rx_disruption.2279676861
Short name T716
Test name
Test status
Simulation time 513076092 ps
CPU time 1.56 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207628 kb
Host smart-af9a7394-2793-4478-8d8f-e087287bf8a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279676861 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.usbdev_tx_rx_disruption.2279676861
Directory /workspace/183.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/184.usbdev_endpoint_types.3738935655
Short name T407
Test name
Test status
Simulation time 616403728 ps
CPU time 1.63 seconds
Started Aug 13 06:41:44 PM PDT 24
Finished Aug 13 06:41:46 PM PDT 24
Peak memory 207480 kb
Host smart-75793a7a-bfd3-47a2-8593-cf45d64d9a60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3738935655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.3738935655
Directory /workspace/184.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/184.usbdev_tx_rx_disruption.3661628923
Short name T2912
Test name
Test status
Simulation time 518920635 ps
CPU time 1.51 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207596 kb
Host smart-559e2193-51d3-4108-b049-fd2a60028842
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661628923 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.usbdev_tx_rx_disruption.3661628923
Directory /workspace/184.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/185.usbdev_endpoint_types.3504426684
Short name T393
Test name
Test status
Simulation time 278532760 ps
CPU time 1.14 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207564 kb
Host smart-5160d78b-b921-4b95-ac37-6c7865e0e147
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3504426684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.3504426684
Directory /workspace/185.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/185.usbdev_tx_rx_disruption.762547147
Short name T1229
Test name
Test status
Simulation time 696777319 ps
CPU time 1.79 seconds
Started Aug 13 06:42:09 PM PDT 24
Finished Aug 13 06:42:11 PM PDT 24
Peak memory 207620 kb
Host smart-9e95e924-61b3-4a32-b0f7-9126154be95a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762547147 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 185.usbdev_tx_rx_disruption.762547147
Directory /workspace/185.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/186.usbdev_endpoint_types.1916137637
Short name T3463
Test name
Test status
Simulation time 309676560 ps
CPU time 1.26 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207516 kb
Host smart-52f04f70-dabd-4db7-b0b2-a307f8490509
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1916137637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.1916137637
Directory /workspace/186.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/187.usbdev_endpoint_types.378906403
Short name T395
Test name
Test status
Simulation time 345495953 ps
CPU time 1.1 seconds
Started Aug 13 06:41:48 PM PDT 24
Finished Aug 13 06:41:49 PM PDT 24
Peak memory 207576 kb
Host smart-9e6a0a0e-7491-49fe-bc37-2ec07e661ce6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=378906403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.378906403
Directory /workspace/187.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/187.usbdev_tx_rx_disruption.2424661118
Short name T1538
Test name
Test status
Simulation time 653769141 ps
CPU time 1.65 seconds
Started Aug 13 06:41:41 PM PDT 24
Finished Aug 13 06:41:43 PM PDT 24
Peak memory 207520 kb
Host smart-f512b9be-8e8c-4f32-9c38-d7db8d49bef0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424661118 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.usbdev_tx_rx_disruption.2424661118
Directory /workspace/187.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/188.usbdev_endpoint_types.3487129199
Short name T360
Test name
Test status
Simulation time 432563351 ps
CPU time 1.28 seconds
Started Aug 13 06:42:00 PM PDT 24
Finished Aug 13 06:42:01 PM PDT 24
Peak memory 207568 kb
Host smart-40ad1693-d237-45cb-8b20-7040cea37cd5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3487129199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.3487129199
Directory /workspace/188.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/188.usbdev_tx_rx_disruption.2070565558
Short name T2741
Test name
Test status
Simulation time 607622952 ps
CPU time 1.62 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207536 kb
Host smart-27abbed9-091f-48d8-9bda-19afa2b5f811
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070565558 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.usbdev_tx_rx_disruption.2070565558
Directory /workspace/188.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/189.usbdev_tx_rx_disruption.1493914431
Short name T179
Test name
Test status
Simulation time 588574799 ps
CPU time 1.61 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207572 kb
Host smart-02664222-0ca0-4e46-a16b-be106b2ef27d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493914431 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.usbdev_tx_rx_disruption.1493914431
Directory /workspace/189.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2495921914
Short name T605
Test name
Test status
Simulation time 53291661 ps
CPU time 0.67 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207436 kb
Host smart-18aca37d-9613-4f21-b8e3-ef6b3afcf075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2495921914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2495921914
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2005795020
Short name T2684
Test name
Test status
Simulation time 5785534131 ps
CPU time 7.97 seconds
Started Aug 13 06:36:40 PM PDT 24
Finished Aug 13 06:36:48 PM PDT 24
Peak memory 216020 kb
Host smart-6a0a9306-b0c8-4b48-b22d-b916fa04ee4a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005795020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.2005795020
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1497114675
Short name T105
Test name
Test status
Simulation time 14990605068 ps
CPU time 21.35 seconds
Started Aug 13 06:36:27 PM PDT 24
Finished Aug 13 06:36:49 PM PDT 24
Peak memory 216024 kb
Host smart-4330be80-2ce5-4b93-8c8f-bb77ec99e8e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497114675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1497114675
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.3636956483
Short name T2289
Test name
Test status
Simulation time 28664997267 ps
CPU time 34.38 seconds
Started Aug 13 06:36:29 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207840 kb
Host smart-2ab26c1f-3752-458e-b359-6cded9d4e352
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636956483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.3636956483
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3945544378
Short name T3331
Test name
Test status
Simulation time 155050640 ps
CPU time 0.87 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207440 kb
Host smart-6409db2c-ba5c-40f9-be2f-e253d85a9e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39455
44378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3945544378
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.4068098504
Short name T2883
Test name
Test status
Simulation time 154796006 ps
CPU time 0.84 seconds
Started Aug 13 06:36:21 PM PDT 24
Finished Aug 13 06:36:22 PM PDT 24
Peak memory 207564 kb
Host smart-6577d14f-c76d-497b-b482-0c164b4c345b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40680
98504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.4068098504
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.485961699
Short name T2958
Test name
Test status
Simulation time 227655737 ps
CPU time 1.07 seconds
Started Aug 13 06:36:23 PM PDT 24
Finished Aug 13 06:36:24 PM PDT 24
Peak memory 207500 kb
Host smart-3b3a4128-7871-4cba-8464-45fbd793a617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48596
1699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.485961699
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1127567463
Short name T1770
Test name
Test status
Simulation time 1066236775 ps
CPU time 2.7 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207616 kb
Host smart-99bd9e5c-6b40-4d01-b00d-b355525eb9d5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1127567463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1127567463
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.3679665806
Short name T2438
Test name
Test status
Simulation time 30653080606 ps
CPU time 58 seconds
Started Aug 13 06:36:29 PM PDT 24
Finished Aug 13 06:37:27 PM PDT 24
Peak memory 207832 kb
Host smart-1233c051-f173-4a81-8b40-b1b051a951a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36796
65806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.3679665806
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.265833998
Short name T2126
Test name
Test status
Simulation time 193475575 ps
CPU time 0.92 seconds
Started Aug 13 06:36:30 PM PDT 24
Finished Aug 13 06:36:31 PM PDT 24
Peak memory 207460 kb
Host smart-ae8c8b94-6e07-48cf-a79b-8d2ba82ff6ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265833998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.265833998
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3483416589
Short name T331
Test name
Test status
Simulation time 547843833 ps
CPU time 1.42 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207508 kb
Host smart-ac4bd2e0-0527-4bb8-bbc1-fa4d9d338017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34834
16589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3483416589
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1539983113
Short name T3417
Test name
Test status
Simulation time 192745443 ps
CPU time 0.93 seconds
Started Aug 13 06:36:23 PM PDT 24
Finished Aug 13 06:36:24 PM PDT 24
Peak memory 207540 kb
Host smart-cdf402b0-d553-45c3-be0b-844f9d5f4056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15399
83113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1539983113
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3024312362
Short name T2991
Test name
Test status
Simulation time 59908701 ps
CPU time 0.73 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207392 kb
Host smart-531b807a-be98-424b-922b-ec34058331a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30243
12362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3024312362
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3814455826
Short name T1787
Test name
Test status
Simulation time 973154743 ps
CPU time 2.6 seconds
Started Aug 13 06:36:26 PM PDT 24
Finished Aug 13 06:36:28 PM PDT 24
Peak memory 207776 kb
Host smart-a192f28b-4475-408e-a86c-14d9c4aa2b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
55826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3814455826
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_types.2868839784
Short name T463
Test name
Test status
Simulation time 305500574 ps
CPU time 1.22 seconds
Started Aug 13 06:36:25 PM PDT 24
Finished Aug 13 06:36:27 PM PDT 24
Peak memory 207560 kb
Host smart-36f6f9c9-1c05-404c-8819-cbc46183320d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2868839784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.2868839784
Directory /workspace/19.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2109928034
Short name T3190
Test name
Test status
Simulation time 152096284 ps
CPU time 1.31 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 207532 kb
Host smart-75c9c309-1680-45c4-b38f-bd0382fca44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21099
28034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2109928034
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2486248948
Short name T2754
Test name
Test status
Simulation time 219806761 ps
CPU time 1.25 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 215864 kb
Host smart-6e4a43df-d909-4adf-b4b7-4d31c2428e06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2486248948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2486248948
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.985224532
Short name T679
Test name
Test status
Simulation time 139142359 ps
CPU time 0.88 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207424 kb
Host smart-826bef9f-0c04-4e38-88ad-eaa8554e4d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98522
4532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.985224532
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3778629438
Short name T2167
Test name
Test status
Simulation time 214634127 ps
CPU time 1.01 seconds
Started Aug 13 06:36:29 PM PDT 24
Finished Aug 13 06:36:30 PM PDT 24
Peak memory 207488 kb
Host smart-a3cf3436-2818-48e1-a9c7-fc4e2f15feca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37786
29438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3778629438
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.2636222838
Short name T2339
Test name
Test status
Simulation time 3664388650 ps
CPU time 107.35 seconds
Started Aug 13 06:36:33 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 217856 kb
Host smart-21584197-7734-4076-8f3d-72bd33e81a24
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2636222838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2636222838
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.3986152843
Short name T2382
Test name
Test status
Simulation time 9487961495 ps
CPU time 61.86 seconds
Started Aug 13 06:36:27 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207688 kb
Host smart-c72a2f47-0a34-4794-8793-fe4fc71b8445
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3986152843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.3986152843
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1584278273
Short name T1765
Test name
Test status
Simulation time 215511159 ps
CPU time 0.95 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207588 kb
Host smart-0b251b22-0c8f-43d7-9877-840c1d4b4243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15842
78273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1584278273
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.2784636877
Short name T1130
Test name
Test status
Simulation time 32897568888 ps
CPU time 52.89 seconds
Started Aug 13 06:36:32 PM PDT 24
Finished Aug 13 06:37:25 PM PDT 24
Peak memory 207848 kb
Host smart-d4ed59f3-0df5-4d85-a406-8605f4f4062e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27846
36877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.2784636877
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.567947532
Short name T3152
Test name
Test status
Simulation time 10512304796 ps
CPU time 13.72 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:51 PM PDT 24
Peak memory 207864 kb
Host smart-3545dd75-6451-4c6e-8918-c47a052c1b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56794
7532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.567947532
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2369250546
Short name T724
Test name
Test status
Simulation time 3384689371 ps
CPU time 96.72 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:38:15 PM PDT 24
Peak memory 224028 kb
Host smart-6972e4f9-a85e-48ee-967f-93484e96983b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2369250546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2369250546
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3524713519
Short name T1232
Test name
Test status
Simulation time 1883811161 ps
CPU time 14.45 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:50 PM PDT 24
Peak memory 207720 kb
Host smart-967329ff-14e8-4282-818d-5cd8f22d25ca
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3524713519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3524713519
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2944107015
Short name T1561
Test name
Test status
Simulation time 245468647 ps
CPU time 1.05 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207536 kb
Host smart-29ab959b-91b2-48aa-826b-ee831c895daa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2944107015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2944107015
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1246786332
Short name T86
Test name
Test status
Simulation time 185404333 ps
CPU time 0.94 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207488 kb
Host smart-c12905bc-3ace-4028-b2d5-61d48af35fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
86332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1246786332
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.1374101545
Short name T1688
Test name
Test status
Simulation time 3622024409 ps
CPU time 35.41 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 218132 kb
Host smart-77272c0d-7fe0-4c86-94bf-63f5e6b00edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13741
01545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.1374101545
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1938449403
Short name T1408
Test name
Test status
Simulation time 3621169646 ps
CPU time 38.54 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 215956 kb
Host smart-56b5431f-b792-42f1-9a5c-5cf0fed22711
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1938449403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1938449403
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.382132981
Short name T2244
Test name
Test status
Simulation time 213392344 ps
CPU time 0.93 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207480 kb
Host smart-fa4182ed-886b-4fa9-85ee-27646ba02f49
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=382132981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.382132981
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1725688728
Short name T3108
Test name
Test status
Simulation time 147585421 ps
CPU time 0.87 seconds
Started Aug 13 06:36:33 PM PDT 24
Finished Aug 13 06:36:34 PM PDT 24
Peak memory 207496 kb
Host smart-ae94b0eb-e69e-404c-ada9-30bb98f49239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17256
88728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1725688728
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3817917372
Short name T3480
Test name
Test status
Simulation time 224976160 ps
CPU time 1.06 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 207368 kb
Host smart-8dc717db-4132-4512-9fac-2803af467115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38179
17372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3817917372
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3685128499
Short name T1384
Test name
Test status
Simulation time 150545556 ps
CPU time 0.85 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207508 kb
Host smart-7c2acf3b-bbe4-468e-a2dd-fbb1b75c8141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36851
28499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3685128499
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.454237224
Short name T1159
Test name
Test status
Simulation time 182116740 ps
CPU time 0.93 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 207500 kb
Host smart-9c637b4c-7371-489b-9174-7b5fe59ade40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45423
7224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.454237224
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.194500511
Short name T2820
Test name
Test status
Simulation time 177394839 ps
CPU time 0.88 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207552 kb
Host smart-e723b5ca-06f4-41a4-b66a-a0bd8628c18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19450
0511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.194500511
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3334733313
Short name T2907
Test name
Test status
Simulation time 153136736 ps
CPU time 0.84 seconds
Started Aug 13 06:36:38 PM PDT 24
Finished Aug 13 06:36:39 PM PDT 24
Peak memory 207500 kb
Host smart-20df181b-41e0-487e-bdcc-ac69387ab620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33347
33313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3334733313
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.2516355295
Short name T961
Test name
Test status
Simulation time 247766050 ps
CPU time 1.09 seconds
Started Aug 13 06:36:33 PM PDT 24
Finished Aug 13 06:36:35 PM PDT 24
Peak memory 207592 kb
Host smart-a1fbf203-d731-4a37-994e-c70ee3a0d84a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2516355295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.2516355295
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2219294288
Short name T1460
Test name
Test status
Simulation time 136258183 ps
CPU time 0.85 seconds
Started Aug 13 06:36:38 PM PDT 24
Finished Aug 13 06:36:39 PM PDT 24
Peak memory 207500 kb
Host smart-26ed24dd-e2a4-4ec9-ad00-7f0b2dea8dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22192
94288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2219294288
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1631258819
Short name T2155
Test name
Test status
Simulation time 111405415 ps
CPU time 0.79 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:36:35 PM PDT 24
Peak memory 207516 kb
Host smart-0058fd6d-21fe-4e03-905a-790c45a0fe84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16312
58819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1631258819
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.223093289
Short name T2453
Test name
Test status
Simulation time 10258352976 ps
CPU time 24.97 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:37:01 PM PDT 24
Peak memory 215996 kb
Host smart-2a3396cb-6f76-49dc-a792-708e71d3e2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22309
3289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.223093289
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2149933058
Short name T1627
Test name
Test status
Simulation time 193368124 ps
CPU time 0.93 seconds
Started Aug 13 06:36:32 PM PDT 24
Finished Aug 13 06:36:33 PM PDT 24
Peak memory 207616 kb
Host smart-a620311b-9fa5-47bd-962b-44c4bdd6669a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21499
33058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2149933058
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1849716985
Short name T33
Test name
Test status
Simulation time 193541208 ps
CPU time 0.93 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207496 kb
Host smart-5eaec415-d430-42f8-9059-66b2f3c380c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18497
16985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1849716985
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3273787789
Short name T1353
Test name
Test status
Simulation time 174334964 ps
CPU time 0.9 seconds
Started Aug 13 06:36:33 PM PDT 24
Finished Aug 13 06:36:34 PM PDT 24
Peak memory 207524 kb
Host smart-9ded2b98-c0f2-44e8-8c9c-b606de9ddde7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32737
87789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3273787789
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1913716343
Short name T3603
Test name
Test status
Simulation time 167721520 ps
CPU time 0.95 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:36:35 PM PDT 24
Peak memory 207532 kb
Host smart-5c83aa2f-4238-4902-967d-9f5023ce7f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19137
16343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1913716343
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_resume_link_active.1984715792
Short name T1915
Test name
Test status
Simulation time 20165762711 ps
CPU time 25.27 seconds
Started Aug 13 06:36:33 PM PDT 24
Finished Aug 13 06:36:59 PM PDT 24
Peak memory 207548 kb
Host smart-350ddcd0-9fe2-43de-a703-14eb789ac9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19847
15792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.1984715792
Directory /workspace/19.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2266551544
Short name T2130
Test name
Test status
Simulation time 218958209 ps
CPU time 0.95 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207444 kb
Host smart-b95d048d-939c-493a-8016-c5784bd50846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665
51544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2266551544
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_rx_full.2949789159
Short name T2085
Test name
Test status
Simulation time 277184097 ps
CPU time 1.19 seconds
Started Aug 13 06:36:45 PM PDT 24
Finished Aug 13 06:36:46 PM PDT 24
Peak memory 207440 kb
Host smart-67f42a19-4acf-4d65-9e00-76d561152389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29497
89159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.2949789159
Directory /workspace/19.usbdev_rx_full/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3026195970
Short name T2340
Test name
Test status
Simulation time 199474803 ps
CPU time 0.96 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207520 kb
Host smart-c7c95073-e4ff-4fb5-8171-5a3fe024be2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30261
95970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3026195970
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1323093077
Short name T23
Test name
Test status
Simulation time 140651848 ps
CPU time 0.88 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207468 kb
Host smart-d0e80ed1-2775-4670-987f-3da837bd05fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13230
93077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1323093077
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2789417239
Short name T665
Test name
Test status
Simulation time 242589889 ps
CPU time 1.08 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207524 kb
Host smart-5b6c94cb-71ca-4fa7-9f1a-4ccaea38fcff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27894
17239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2789417239
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.170892037
Short name T2756
Test name
Test status
Simulation time 3290945445 ps
CPU time 32.54 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:37:07 PM PDT 24
Peak memory 224124 kb
Host smart-405908c6-f83e-45a0-b7f4-bae33e7bdacf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=170892037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.170892037
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3901068457
Short name T1365
Test name
Test status
Simulation time 166593364 ps
CPU time 0.86 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207472 kb
Host smart-146ce06d-543f-4a18-ac56-ccebc8fbaaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39010
68457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3901068457
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3357712539
Short name T832
Test name
Test status
Simulation time 165690222 ps
CPU time 0.87 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207564 kb
Host smart-1e1d525c-df4b-4928-96d0-f119739050fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33577
12539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3357712539
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.1884143868
Short name T1030
Test name
Test status
Simulation time 1264375505 ps
CPU time 3.09 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 207648 kb
Host smart-5d64680b-03f5-465b-a5b8-43041156092f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
43868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.1884143868
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1057426992
Short name T1138
Test name
Test status
Simulation time 2471565408 ps
CPU time 24.2 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:36:59 PM PDT 24
Peak memory 217236 kb
Host smart-88ae3d49-5cfb-4246-8b58-8bd7a754b1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10574
26992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1057426992
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.1136005347
Short name T746
Test name
Test status
Simulation time 1094030801 ps
CPU time 8.74 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:44 PM PDT 24
Peak memory 207596 kb
Host smart-36a834cf-9679-44cb-afc7-9566bf9e039b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136005347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.1136005347
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_tx_rx_disruption.3458223586
Short name T1793
Test name
Test status
Simulation time 618873492 ps
CPU time 1.68 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:36:35 PM PDT 24
Peak memory 207608 kb
Host smart-141f4688-0e81-427c-83ee-a7b9d726df4b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458223586 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.usbdev_tx_rx_disruption.3458223586
Directory /workspace/19.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/190.usbdev_endpoint_types.3925039589
Short name T501
Test name
Test status
Simulation time 207755664 ps
CPU time 0.93 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207508 kb
Host smart-f767d75f-73c6-4c81-ab7f-3bb6cae33075
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3925039589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.3925039589
Directory /workspace/190.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/190.usbdev_tx_rx_disruption.1763984866
Short name T751
Test name
Test status
Simulation time 625739487 ps
CPU time 1.83 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207556 kb
Host smart-dab63a20-d059-497c-81db-cf818765d7d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763984866 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 190.usbdev_tx_rx_disruption.1763984866
Directory /workspace/190.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/191.usbdev_endpoint_types.3457156204
Short name T427
Test name
Test status
Simulation time 296308133 ps
CPU time 1.05 seconds
Started Aug 13 06:41:44 PM PDT 24
Finished Aug 13 06:41:45 PM PDT 24
Peak memory 207568 kb
Host smart-6c9025b6-b230-49c8-847c-800427fb9f8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3457156204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.3457156204
Directory /workspace/191.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/191.usbdev_tx_rx_disruption.837802580
Short name T3217
Test name
Test status
Simulation time 545282217 ps
CPU time 1.54 seconds
Started Aug 13 06:41:44 PM PDT 24
Finished Aug 13 06:41:46 PM PDT 24
Peak memory 207600 kb
Host smart-9aae4259-fda8-467e-a5e8-dd520cfbc5cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837802580 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 191.usbdev_tx_rx_disruption.837802580
Directory /workspace/191.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/192.usbdev_endpoint_types.3857706413
Short name T486
Test name
Test status
Simulation time 158043847 ps
CPU time 0.85 seconds
Started Aug 13 06:41:41 PM PDT 24
Finished Aug 13 06:41:42 PM PDT 24
Peak memory 207488 kb
Host smart-155a8934-3f57-4592-a89a-609ee91a3d2a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3857706413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.3857706413
Directory /workspace/192.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/192.usbdev_tx_rx_disruption.159296394
Short name T3626
Test name
Test status
Simulation time 655016684 ps
CPU time 1.61 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207560 kb
Host smart-4c9f9b63-a5c5-4d91-8f8e-c2d429df4a23
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159296394 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 192.usbdev_tx_rx_disruption.159296394
Directory /workspace/192.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/193.usbdev_endpoint_types.670809514
Short name T374
Test name
Test status
Simulation time 549244239 ps
CPU time 1.47 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207556 kb
Host smart-c31e4f82-4c5d-4ff3-84b2-8e2bd29426f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=670809514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.670809514
Directory /workspace/193.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/193.usbdev_tx_rx_disruption.466059032
Short name T1160
Test name
Test status
Simulation time 527270093 ps
CPU time 1.52 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207524 kb
Host smart-fb34bdf7-5b1d-4150-88dc-6ea9dba84013
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466059032 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 193.usbdev_tx_rx_disruption.466059032
Directory /workspace/193.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/194.usbdev_endpoint_types.3842838573
Short name T497
Test name
Test status
Simulation time 291499642 ps
CPU time 1.08 seconds
Started Aug 13 06:41:50 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207568 kb
Host smart-989ad44e-49a2-483d-a5bf-c32e312ce09c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3842838573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.3842838573
Directory /workspace/194.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/194.usbdev_tx_rx_disruption.2891407282
Short name T3410
Test name
Test status
Simulation time 520769380 ps
CPU time 1.75 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:48 PM PDT 24
Peak memory 207596 kb
Host smart-15c8ebb5-3ffe-421a-8296-3639526e5082
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891407282 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.usbdev_tx_rx_disruption.2891407282
Directory /workspace/194.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/195.usbdev_endpoint_types.4273195801
Short name T210
Test name
Test status
Simulation time 308377305 ps
CPU time 1.19 seconds
Started Aug 13 06:42:05 PM PDT 24
Finished Aug 13 06:42:06 PM PDT 24
Peak memory 207528 kb
Host smart-13358ab9-f0fa-432e-b4d7-a169be4024e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4273195801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.4273195801
Directory /workspace/195.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/195.usbdev_tx_rx_disruption.2873175896
Short name T896
Test name
Test status
Simulation time 501277984 ps
CPU time 1.54 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207524 kb
Host smart-ebd805e1-08ee-454f-864e-ba3e754e5b0c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873175896 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.usbdev_tx_rx_disruption.2873175896
Directory /workspace/195.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/196.usbdev_endpoint_types.1413678352
Short name T2859
Test name
Test status
Simulation time 556783574 ps
CPU time 1.57 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207532 kb
Host smart-e009d4d7-3492-4041-9f4d-dbbc80df3e31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1413678352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.1413678352
Directory /workspace/196.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/196.usbdev_tx_rx_disruption.348960427
Short name T2892
Test name
Test status
Simulation time 560632727 ps
CPU time 1.6 seconds
Started Aug 13 06:42:00 PM PDT 24
Finished Aug 13 06:42:02 PM PDT 24
Peak memory 207616 kb
Host smart-79aac8c7-0df8-4783-bdf0-fddbba4b4f83
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348960427 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 196.usbdev_tx_rx_disruption.348960427
Directory /workspace/196.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/197.usbdev_endpoint_types.1317388307
Short name T481
Test name
Test status
Simulation time 244386344 ps
CPU time 1.01 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:52 PM PDT 24
Peak memory 207508 kb
Host smart-2ac62768-3865-493c-9e97-a65d0a1735da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1317388307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.1317388307
Directory /workspace/197.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/197.usbdev_tx_rx_disruption.1785225588
Short name T3462
Test name
Test status
Simulation time 581338147 ps
CPU time 1.58 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:02 PM PDT 24
Peak memory 207584 kb
Host smart-226d83b5-75ae-4617-9433-0631ebe77666
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785225588 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.usbdev_tx_rx_disruption.1785225588
Directory /workspace/197.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/198.usbdev_endpoint_types.3450681763
Short name T451
Test name
Test status
Simulation time 563389044 ps
CPU time 1.53 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:52 PM PDT 24
Peak memory 207568 kb
Host smart-ab634584-df01-4e08-8b64-60c3e324ea86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3450681763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.3450681763
Directory /workspace/198.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/198.usbdev_tx_rx_disruption.4165504202
Short name T3593
Test name
Test status
Simulation time 481829582 ps
CPU time 1.5 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:46 PM PDT 24
Peak memory 207512 kb
Host smart-2346506b-394b-4090-9f29-57d15b6433b4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165504202 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.usbdev_tx_rx_disruption.4165504202
Directory /workspace/198.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/199.usbdev_endpoint_types.2214021619
Short name T456
Test name
Test status
Simulation time 263918627 ps
CPU time 1.06 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207564 kb
Host smart-f4d11d5c-24ba-49d0-b543-e82daa574b4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2214021619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.2214021619
Directory /workspace/199.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/199.usbdev_tx_rx_disruption.2888429324
Short name T1489
Test name
Test status
Simulation time 547419111 ps
CPU time 1.68 seconds
Started Aug 13 06:41:44 PM PDT 24
Finished Aug 13 06:41:46 PM PDT 24
Peak memory 207468 kb
Host smart-987fc735-4344-4531-802e-5fc394e777cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888429324 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.usbdev_tx_rx_disruption.2888429324
Directory /workspace/199.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.2259097955
Short name T226
Test name
Test status
Simulation time 47270730 ps
CPU time 0.66 seconds
Started Aug 13 06:33:35 PM PDT 24
Finished Aug 13 06:33:35 PM PDT 24
Peak memory 207504 kb
Host smart-917c4d7d-a814-4a3b-b0d4-1b75e857b0fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2259097955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.2259097955
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.986221701
Short name T1465
Test name
Test status
Simulation time 10663161971 ps
CPU time 14.2 seconds
Started Aug 13 06:33:21 PM PDT 24
Finished Aug 13 06:33:35 PM PDT 24
Peak memory 207800 kb
Host smart-02eba043-94a9-452b-ad30-ade6bd608ba0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986221701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon
_wake_disconnect.986221701
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2089505235
Short name T1521
Test name
Test status
Simulation time 16296476967 ps
CPU time 19.8 seconds
Started Aug 13 06:33:22 PM PDT 24
Finished Aug 13 06:33:42 PM PDT 24
Peak memory 216020 kb
Host smart-c1d92b03-ceef-4d95-8424-6bd6bd250ec7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089505235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2089505235
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1309640377
Short name T1522
Test name
Test status
Simulation time 26304595185 ps
CPU time 33.18 seconds
Started Aug 13 06:33:26 PM PDT 24
Finished Aug 13 06:33:59 PM PDT 24
Peak memory 216012 kb
Host smart-4950352d-91c8-4c97-9f3f-74db41878425
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309640377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.1309640377
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2031217275
Short name T1501
Test name
Test status
Simulation time 176250379 ps
CPU time 0.86 seconds
Started Aug 13 06:33:22 PM PDT 24
Finished Aug 13 06:33:23 PM PDT 24
Peak memory 207448 kb
Host smart-78d06351-fcbc-4c9f-90bc-1132e54fe278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20312
17275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2031217275
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2842046613
Short name T39
Test name
Test status
Simulation time 192847250 ps
CPU time 1 seconds
Started Aug 13 06:33:23 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 207524 kb
Host smart-a1bfc222-e2f2-426b-b04d-468a39717ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28420
46613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2842046613
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.3650392747
Short name T52
Test name
Test status
Simulation time 140157230 ps
CPU time 0.83 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:33:31 PM PDT 24
Peak memory 207432 kb
Host smart-6f1cea09-c67c-4077-8a53-3246f17aab75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36503
92747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.3650392747
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1860698347
Short name T1806
Test name
Test status
Simulation time 149624407 ps
CPU time 0.86 seconds
Started Aug 13 06:33:21 PM PDT 24
Finished Aug 13 06:33:22 PM PDT 24
Peak memory 207532 kb
Host smart-71e68fa9-6b8f-4c28-9bcc-31bbecf7244a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
98347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1860698347
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3040363996
Short name T798
Test name
Test status
Simulation time 195476315 ps
CPU time 0.99 seconds
Started Aug 13 06:33:23 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 207580 kb
Host smart-753e0ecd-0c90-48a3-b43a-a82010d0dc56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30403
63996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3040363996
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.620170989
Short name T344
Test name
Test status
Simulation time 823724044 ps
CPU time 2.26 seconds
Started Aug 13 06:33:21 PM PDT 24
Finished Aug 13 06:33:23 PM PDT 24
Peak memory 207604 kb
Host smart-49d2b1f8-294f-4ede-bd1a-62d89a479c1f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=620170989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.620170989
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1210526855
Short name T3528
Test name
Test status
Simulation time 29809241147 ps
CPU time 53.17 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:34:25 PM PDT 24
Peak memory 207756 kb
Host smart-f0c376f5-afae-44e5-a3ec-c8fc546452ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12105
26855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1210526855
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.1914249308
Short name T1385
Test name
Test status
Simulation time 2853574639 ps
CPU time 18.81 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:33:49 PM PDT 24
Peak memory 207752 kb
Host smart-c6aff376-f28e-4053-bec1-dd6bead3e3d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914249308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.1914249308
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2881809932
Short name T1927
Test name
Test status
Simulation time 494046172 ps
CPU time 1.58 seconds
Started Aug 13 06:33:24 PM PDT 24
Finished Aug 13 06:33:26 PM PDT 24
Peak memory 207580 kb
Host smart-557d5156-c370-479c-b5a6-6de8a143e832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28818
09932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2881809932
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3314778726
Short name T844
Test name
Test status
Simulation time 158065689 ps
CPU time 0.89 seconds
Started Aug 13 06:33:22 PM PDT 24
Finished Aug 13 06:33:23 PM PDT 24
Peak memory 207568 kb
Host smart-f81a2d8e-737a-4524-8868-0feb4604513c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33147
78726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3314778726
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2023960383
Short name T629
Test name
Test status
Simulation time 53143398 ps
CPU time 0.72 seconds
Started Aug 13 06:33:26 PM PDT 24
Finished Aug 13 06:33:26 PM PDT 24
Peak memory 207456 kb
Host smart-603a66aa-b323-40a2-91a9-e2472a162093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20239
60383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2023960383
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1816039080
Short name T2089
Test name
Test status
Simulation time 784204044 ps
CPU time 2.33 seconds
Started Aug 13 06:33:21 PM PDT 24
Finished Aug 13 06:33:23 PM PDT 24
Peak memory 207768 kb
Host smart-b6d11229-ea6c-495d-a4d4-b961384ed9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160
39080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1816039080
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_types.3706634167
Short name T2668
Test name
Test status
Simulation time 213070104 ps
CPU time 1.02 seconds
Started Aug 13 06:33:23 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 207580 kb
Host smart-69557499-a17a-4be0-9234-477c1946a0c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3706634167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.3706634167
Directory /workspace/2.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1500376473
Short name T1533
Test name
Test status
Simulation time 240017415 ps
CPU time 1.7 seconds
Started Aug 13 06:33:27 PM PDT 24
Finished Aug 13 06:33:29 PM PDT 24
Peak memory 207656 kb
Host smart-aaeab58f-c559-4b8f-b27a-f14051982445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15003
76473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1500376473
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1865496268
Short name T1406
Test name
Test status
Simulation time 106200140957 ps
CPU time 192.11 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:36:41 PM PDT 24
Peak memory 207612 kb
Host smart-9243afbd-7172-46db-91b6-7df9ac2d8068
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1865496268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1865496268
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1568470326
Short name T84
Test name
Test status
Simulation time 116376149164 ps
CPU time 183.23 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:36:32 PM PDT 24
Peak memory 207692 kb
Host smart-def6c5ee-811e-4b48-b88e-95cac5c0d11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568470326 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1568470326
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1633505966
Short name T2157
Test name
Test status
Simulation time 108116099720 ps
CPU time 172.72 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:36:23 PM PDT 24
Peak memory 207704 kb
Host smart-cedad6a2-5ee6-487a-b20f-10647328a23f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1633505966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1633505966
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1319187016
Short name T535
Test name
Test status
Simulation time 115273795598 ps
CPU time 189.94 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 207832 kb
Host smart-6aafdf7e-040a-4acf-bceb-a12823e05e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319187016 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1319187016
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.2563022161
Short name T3111
Test name
Test status
Simulation time 91128402119 ps
CPU time 138.28 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:35:47 PM PDT 24
Peak memory 207704 kb
Host smart-a854e54d-c7b5-4bf0-9924-ad57ccad4078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25630
22161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.2563022161
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1604097726
Short name T2279
Test name
Test status
Simulation time 194070661 ps
CPU time 1.01 seconds
Started Aug 13 06:33:33 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 215904 kb
Host smart-fa949819-28c7-4ffe-a568-a9e1b5829ce7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1604097726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1604097726
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3240125093
Short name T1995
Test name
Test status
Simulation time 151307440 ps
CPU time 0.87 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:33:33 PM PDT 24
Peak memory 207416 kb
Host smart-466ef63a-566e-4c42-a0ff-70e8763a6d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32401
25093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3240125093
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.278222673
Short name T1704
Test name
Test status
Simulation time 246095560 ps
CPU time 0.96 seconds
Started Aug 13 06:33:33 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 207512 kb
Host smart-500ed481-dd5f-4c30-a6c5-28d488052a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27822
2673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.278222673
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.12573002
Short name T1027
Test name
Test status
Simulation time 4883933256 ps
CPU time 39.5 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 216000 kb
Host smart-b347707e-b4d2-40ce-a2c8-8a3022948f2d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=12573002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.12573002
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3812961882
Short name T2137
Test name
Test status
Simulation time 9645006972 ps
CPU time 119.54 seconds
Started Aug 13 06:33:31 PM PDT 24
Finished Aug 13 06:35:30 PM PDT 24
Peak memory 207784 kb
Host smart-dd76b0c0-cc5e-45b6-91b0-a85d05eb09a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3812961882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3812961882
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.4040360639
Short name T570
Test name
Test status
Simulation time 171925941 ps
CPU time 0.98 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:33:33 PM PDT 24
Peak memory 207496 kb
Host smart-6f4a78bc-ebfc-4aed-a2e1-e47a033ee87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40403
60639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.4040360639
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1738554555
Short name T1925
Test name
Test status
Simulation time 32671441344 ps
CPU time 51.68 seconds
Started Aug 13 06:33:31 PM PDT 24
Finished Aug 13 06:34:22 PM PDT 24
Peak memory 207732 kb
Host smart-5712bd9b-1506-4247-b1f5-de161d2f7d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17385
54555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1738554555
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2790030604
Short name T678
Test name
Test status
Simulation time 10385509601 ps
CPU time 16.26 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:33:46 PM PDT 24
Peak memory 207868 kb
Host smart-c6442444-7554-4b66-8097-346298062b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27900
30604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2790030604
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3617538629
Short name T2263
Test name
Test status
Simulation time 3836460048 ps
CPU time 112.5 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:35:22 PM PDT 24
Peak memory 224168 kb
Host smart-886a78a5-0129-414e-86f2-1282096199fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3617538629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3617538629
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3622143572
Short name T1645
Test name
Test status
Simulation time 3268997482 ps
CPU time 34.95 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:34:07 PM PDT 24
Peak memory 216944 kb
Host smart-d86daa20-f818-43d2-a475-0c76e96046e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3622143572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3622143572
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2421465476
Short name T3431
Test name
Test status
Simulation time 274767934 ps
CPU time 1.04 seconds
Started Aug 13 06:33:31 PM PDT 24
Finished Aug 13 06:33:32 PM PDT 24
Peak memory 207516 kb
Host smart-627307ee-619a-4ffd-b9f9-dab0272fbcc9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2421465476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2421465476
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1387817858
Short name T1876
Test name
Test status
Simulation time 194979107 ps
CPU time 0.95 seconds
Started Aug 13 06:33:28 PM PDT 24
Finished Aug 13 06:33:29 PM PDT 24
Peak memory 207424 kb
Host smart-e139d53a-9fe0-4ecf-9f6c-84c65b469789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13878
17858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1387817858
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.2906710585
Short name T1412
Test name
Test status
Simulation time 1906019640 ps
CPU time 14.43 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:33:43 PM PDT 24
Peak memory 223936 kb
Host smart-3626ec87-da87-4934-9465-85fa3e5f78ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29067
10585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.2906710585
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1856317955
Short name T1464
Test name
Test status
Simulation time 2443973352 ps
CPU time 21.47 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:33:50 PM PDT 24
Peak memory 224208 kb
Host smart-58fe0150-ebba-402b-b655-942e2ac48286
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1856317955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1856317955
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3444192946
Short name T251
Test name
Test status
Simulation time 1650680087 ps
CPU time 12.17 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 224128 kb
Host smart-81cf50bd-4095-4645-8bc1-cab5a8a20c31
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3444192946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3444192946
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1385370020
Short name T2594
Test name
Test status
Simulation time 169145499 ps
CPU time 0.9 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:33:31 PM PDT 24
Peak memory 207480 kb
Host smart-11b41d20-cb37-4078-a437-6edc7ac8a468
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1385370020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1385370020
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3358418094
Short name T1238
Test name
Test status
Simulation time 148236971 ps
CPU time 0.88 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:33:30 PM PDT 24
Peak memory 207528 kb
Host smart-c3d16917-a5d2-4fa0-8311-fea293760558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33584
18094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3358418094
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1411102889
Short name T3305
Test name
Test status
Simulation time 211903847 ps
CPU time 0.98 seconds
Started Aug 13 06:33:33 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 207528 kb
Host smart-28b071ee-0af3-4842-9922-9497ce474739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14111
02889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1411102889
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.169965196
Short name T3415
Test name
Test status
Simulation time 171165407 ps
CPU time 0.95 seconds
Started Aug 13 06:33:33 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 207524 kb
Host smart-1407787d-3de4-4010-90be-2a3a8b67408d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16996
5196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.169965196
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2727856803
Short name T1175
Test name
Test status
Simulation time 204321553 ps
CPU time 0.96 seconds
Started Aug 13 06:33:31 PM PDT 24
Finished Aug 13 06:33:32 PM PDT 24
Peak memory 207456 kb
Host smart-e936d9f6-5bd8-4b77-b9ae-fb79cb5de5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27278
56803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2727856803
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2316620153
Short name T2473
Test name
Test status
Simulation time 162895121 ps
CPU time 0.86 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:33:33 PM PDT 24
Peak memory 207572 kb
Host smart-c0aa5b3c-63e3-4518-895a-e64831adeb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23166
20153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2316620153
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1388724872
Short name T1105
Test name
Test status
Simulation time 159483049 ps
CPU time 0.85 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:33:31 PM PDT 24
Peak memory 207616 kb
Host smart-24cf0bba-4faf-4b78-8849-b04bf99b355a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13887
24872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1388724872
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2256708385
Short name T1422
Test name
Test status
Simulation time 207012732 ps
CPU time 0.95 seconds
Started Aug 13 06:33:33 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 207584 kb
Host smart-3975d92b-8534-49ff-9e8c-e7ce9b0dad99
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2256708385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2256708385
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.2875760363
Short name T983
Test name
Test status
Simulation time 264076608 ps
CPU time 1.14 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:33:30 PM PDT 24
Peak memory 207420 kb
Host smart-f89dc3ce-899b-4e37-96f3-0b78346e8817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28757
60363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.2875760363
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3615290406
Short name T1906
Test name
Test status
Simulation time 169519690 ps
CPU time 0.86 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:33:30 PM PDT 24
Peak memory 207428 kb
Host smart-25fa354e-3177-4bf1-8771-7149374e5da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36152
90406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3615290406
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1131617348
Short name T2154
Test name
Test status
Simulation time 49556044 ps
CPU time 0.78 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:33:33 PM PDT 24
Peak memory 207568 kb
Host smart-79c6e8b8-e770-4e7e-8dbc-55bc45689f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11316
17348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1131617348
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1988380922
Short name T1732
Test name
Test status
Simulation time 13687055067 ps
CPU time 35.5 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:34:04 PM PDT 24
Peak memory 215980 kb
Host smart-cc27db64-de47-46b6-ac60-cf62d9305fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19883
80922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1988380922
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2425846561
Short name T1507
Test name
Test status
Simulation time 147148011 ps
CPU time 0.85 seconds
Started Aug 13 06:33:34 PM PDT 24
Finished Aug 13 06:33:35 PM PDT 24
Peak memory 207592 kb
Host smart-596a45dc-9a22-4257-a019-c9d8ead12c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24258
46561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2425846561
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3038632976
Short name T660
Test name
Test status
Simulation time 251967275 ps
CPU time 1.02 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:33:30 PM PDT 24
Peak memory 207480 kb
Host smart-7ed44af9-b349-4e42-9b65-c4d56e1b0986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30386
32976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3038632976
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1404364173
Short name T175
Test name
Test status
Simulation time 3272748238 ps
CPU time 86.2 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:34:58 PM PDT 24
Peak memory 215952 kb
Host smart-888c95b1-1c06-4e3c-aa83-d1d2770958f4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404364173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1404364173
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.235635513
Short name T2336
Test name
Test status
Simulation time 2418673194 ps
CPU time 19.88 seconds
Started Aug 13 06:33:31 PM PDT 24
Finished Aug 13 06:33:51 PM PDT 24
Peak memory 217176 kb
Host smart-760124ed-763d-4719-9daf-d2ce1cb54ba0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=235635513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.235635513
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3121374625
Short name T188
Test name
Test status
Simulation time 7341787210 ps
CPU time 44.2 seconds
Started Aug 13 06:33:31 PM PDT 24
Finished Aug 13 06:34:15 PM PDT 24
Peak memory 219064 kb
Host smart-e1781e14-3c21-4436-a850-91db5d3d0fb3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121374625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3121374625
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1887163518
Short name T545
Test name
Test status
Simulation time 187181988 ps
CPU time 0.92 seconds
Started Aug 13 06:33:32 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 207504 kb
Host smart-5ad93904-0641-40d2-96d1-71e4ac61da17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18871
63518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1887163518
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.4122276482
Short name T1164
Test name
Test status
Simulation time 168115513 ps
CPU time 0.95 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:33:31 PM PDT 24
Peak memory 207536 kb
Host smart-0120369e-2274-4ce8-8ab4-e1b9a2e38510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41222
76482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.4122276482
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_resume_link_active.2419260944
Short name T2387
Test name
Test status
Simulation time 20164155036 ps
CPU time 29.21 seconds
Started Aug 13 06:33:29 PM PDT 24
Finished Aug 13 06:33:58 PM PDT 24
Peak memory 207628 kb
Host smart-9284f4af-8804-438a-b90d-a09e404f6ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24192
60944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.2419260944
Directory /workspace/2.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1722167188
Short name T3529
Test name
Test status
Simulation time 176139375 ps
CPU time 0.86 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:33:31 PM PDT 24
Peak memory 207496 kb
Host smart-b91db064-0758-4959-893e-aeaa8378c899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17221
67188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1722167188
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_full.4004248787
Short name T42
Test name
Test status
Simulation time 272591401 ps
CPU time 1.18 seconds
Started Aug 13 06:33:30 PM PDT 24
Finished Aug 13 06:33:32 PM PDT 24
Peak memory 207492 kb
Host smart-61878751-8c42-43e6-9dc4-cc1dc6c45516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042
48787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.4004248787
Directory /workspace/2.usbdev_rx_full/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1420341679
Short name T74
Test name
Test status
Simulation time 161380298 ps
CPU time 0.85 seconds
Started Aug 13 06:33:36 PM PDT 24
Finished Aug 13 06:33:37 PM PDT 24
Peak memory 207488 kb
Host smart-474a1f19-941e-4c91-8edd-6ce80676b6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14203
41679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1420341679
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.933283880
Short name T247
Test name
Test status
Simulation time 482244642 ps
CPU time 1.39 seconds
Started Aug 13 06:33:39 PM PDT 24
Finished Aug 13 06:33:40 PM PDT 24
Peak memory 223936 kb
Host smart-99e316fd-d7bc-48bc-ae7f-dda07c9d6207
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=933283880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.933283880
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1939641642
Short name T46
Test name
Test status
Simulation time 436458234 ps
CPU time 1.52 seconds
Started Aug 13 06:33:39 PM PDT 24
Finished Aug 13 06:33:41 PM PDT 24
Peak memory 207612 kb
Host smart-1b61dd1a-5a98-4ece-965f-0ce67d4f691d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19396
41642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1939641642
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3046812992
Short name T2768
Test name
Test status
Simulation time 205801079 ps
CPU time 0.96 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 207444 kb
Host smart-7a4156dc-4abf-4a3e-bbaf-ebade38dbf8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30468
12992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3046812992
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.137897366
Short name T2206
Test name
Test status
Simulation time 152655599 ps
CPU time 0.84 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 207388 kb
Host smart-d11d1637-2df7-49aa-9800-20cf939a23df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13789
7366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.137897366
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3806572125
Short name T1629
Test name
Test status
Simulation time 150841582 ps
CPU time 0.83 seconds
Started Aug 13 06:33:42 PM PDT 24
Finished Aug 13 06:33:43 PM PDT 24
Peak memory 207532 kb
Host smart-0f91c2b8-a852-4b77-a87f-598d5a776dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38065
72125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3806572125
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1820643245
Short name T1161
Test name
Test status
Simulation time 216787642 ps
CPU time 0.99 seconds
Started Aug 13 06:33:38 PM PDT 24
Finished Aug 13 06:33:39 PM PDT 24
Peak memory 207528 kb
Host smart-0e702429-db4c-4d0c-9bd7-c7d1061e1766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18206
43245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1820643245
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1355689962
Short name T2499
Test name
Test status
Simulation time 2269150794 ps
CPU time 18.15 seconds
Started Aug 13 06:33:39 PM PDT 24
Finished Aug 13 06:33:57 PM PDT 24
Peak memory 217632 kb
Host smart-f07e59a5-f4fa-4a4d-9bde-598e586f84ea
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1355689962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1355689962
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.928120492
Short name T728
Test name
Test status
Simulation time 182345210 ps
CPU time 0.97 seconds
Started Aug 13 06:33:38 PM PDT 24
Finished Aug 13 06:33:39 PM PDT 24
Peak memory 207432 kb
Host smart-cc338654-e417-49b1-8444-a2c04950baa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92812
0492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.928120492
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3069254469
Short name T3133
Test name
Test status
Simulation time 173396010 ps
CPU time 0.91 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 207420 kb
Host smart-11dc7dcc-cecc-4086-824f-f4d840c1d1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30692
54469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3069254469
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.644125351
Short name T2500
Test name
Test status
Simulation time 1199778095 ps
CPU time 3.27 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:46 PM PDT 24
Peak memory 207700 kb
Host smart-1be52591-25b9-4486-99d3-e2ac6186d54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64412
5351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.644125351
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.947234567
Short name T276
Test name
Test status
Simulation time 1972025365 ps
CPU time 15.49 seconds
Started Aug 13 06:33:38 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 207816 kb
Host smart-e2f61216-5622-4927-b418-54ee441e5b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94723
4567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.947234567
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.379195029
Short name T2488
Test name
Test status
Simulation time 3859375913 ps
CPU time 33.38 seconds
Started Aug 13 06:33:22 PM PDT 24
Finished Aug 13 06:33:56 PM PDT 24
Peak memory 207788 kb
Host smart-8881fb38-fd72-47d6-b98f-15c6d469d56f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379195029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host_
handshake.379195029
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_tx_rx_disruption.2538872168
Short name T2098
Test name
Test status
Simulation time 540168655 ps
CPU time 1.59 seconds
Started Aug 13 06:33:39 PM PDT 24
Finished Aug 13 06:33:40 PM PDT 24
Peak memory 207616 kb
Host smart-a3a5007a-4635-49c7-956f-8fededc9dcb9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538872168 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.usbdev_tx_rx_disruption.2538872168
Directory /workspace/2.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3353479364
Short name T1498
Test name
Test status
Simulation time 40268549 ps
CPU time 0.69 seconds
Started Aug 13 06:36:43 PM PDT 24
Finished Aug 13 06:36:44 PM PDT 24
Peak memory 207484 kb
Host smart-6be50772-64a9-42c4-9646-4e268ef4f2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3353479364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3353479364
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.754494214
Short name T1941
Test name
Test status
Simulation time 10256915095 ps
CPU time 13.65 seconds
Started Aug 13 06:36:44 PM PDT 24
Finished Aug 13 06:36:58 PM PDT 24
Peak memory 207796 kb
Host smart-f4ee6c9e-d47f-4a7d-a423-e9ffb4a0857b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754494214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ao
n_wake_disconnect.754494214
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1236850490
Short name T1821
Test name
Test status
Simulation time 19913849547 ps
CPU time 23.31 seconds
Started Aug 13 06:36:30 PM PDT 24
Finished Aug 13 06:36:54 PM PDT 24
Peak memory 207860 kb
Host smart-77d114a3-0dac-4bfe-8769-7bf02fdb50b1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236850490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1236850490
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1901055560
Short name T1185
Test name
Test status
Simulation time 29529602218 ps
CPU time 36.07 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 207876 kb
Host smart-e6c1ce71-da40-4f2d-bbb8-91418a9f6526
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901055560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.1901055560
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3621049359
Short name T1965
Test name
Test status
Simulation time 196955362 ps
CPU time 0.95 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207476 kb
Host smart-045b9543-5e7d-4bd4-b205-271e53d4074c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36210
49359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3621049359
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.138111570
Short name T3343
Test name
Test status
Simulation time 148464029 ps
CPU time 0.81 seconds
Started Aug 13 06:36:38 PM PDT 24
Finished Aug 13 06:36:39 PM PDT 24
Peak memory 207576 kb
Host smart-eb045e1d-97e9-4421-ab83-95f4996012e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13811
1570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.138111570
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.231355889
Short name T1029
Test name
Test status
Simulation time 345007175 ps
CPU time 1.23 seconds
Started Aug 13 06:36:43 PM PDT 24
Finished Aug 13 06:36:45 PM PDT 24
Peak memory 207540 kb
Host smart-07f0f7de-23c3-4edf-83e2-3abc2b22bb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23135
5889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.231355889
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1070427438
Short name T342
Test name
Test status
Simulation time 1001325070 ps
CPU time 2.67 seconds
Started Aug 13 06:36:52 PM PDT 24
Finished Aug 13 06:36:55 PM PDT 24
Peak memory 207688 kb
Host smart-e47394bd-42a6-4a6a-8ae4-93af56e79d96
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1070427438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1070427438
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.1429799125
Short name T1523
Test name
Test status
Simulation time 1419400720 ps
CPU time 33.56 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 207696 kb
Host smart-baf6c1e9-b1e9-405b-8b27-255f5c0b08b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429799125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.1429799125
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2537995479
Short name T2096
Test name
Test status
Simulation time 428047872 ps
CPU time 1.42 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:41 PM PDT 24
Peak memory 207568 kb
Host smart-aab39f22-78b3-44ce-b628-e048fc0885d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25379
95479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2537995479
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2876998774
Short name T2463
Test name
Test status
Simulation time 145916375 ps
CPU time 0.83 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207504 kb
Host smart-6c1755c0-67ac-479c-86f9-e560ada3f08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28769
98774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2876998774
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.885765504
Short name T2664
Test name
Test status
Simulation time 43263639 ps
CPU time 0.73 seconds
Started Aug 13 06:36:31 PM PDT 24
Finished Aug 13 06:36:32 PM PDT 24
Peak memory 207504 kb
Host smart-f8225d93-f302-48a3-9f3d-68e4eb5849c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88576
5504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.885765504
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3694191288
Short name T1944
Test name
Test status
Simulation time 856241058 ps
CPU time 2.43 seconds
Started Aug 13 06:36:32 PM PDT 24
Finished Aug 13 06:36:35 PM PDT 24
Peak memory 207836 kb
Host smart-35c01a8c-0c3c-453e-8208-ce4e558c2343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36941
91288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3694191288
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2909567549
Short name T3478
Test name
Test status
Simulation time 227148317 ps
CPU time 1.71 seconds
Started Aug 13 06:36:30 PM PDT 24
Finished Aug 13 06:36:31 PM PDT 24
Peak memory 207584 kb
Host smart-13002902-3cf8-4ed3-92da-961933c99318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095
67549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2909567549
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2740360656
Short name T731
Test name
Test status
Simulation time 257039106 ps
CPU time 1.27 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 215900 kb
Host smart-ea0f44b7-a955-4feb-bb24-919349e008f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2740360656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2740360656
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3364170444
Short name T1790
Test name
Test status
Simulation time 203111567 ps
CPU time 0.92 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:36:35 PM PDT 24
Peak memory 207508 kb
Host smart-1c52b76a-e61f-4842-bda0-1f9e14eddf5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33641
70444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3364170444
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3025108253
Short name T3222
Test name
Test status
Simulation time 172983200 ps
CPU time 0.87 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207516 kb
Host smart-d281cd33-8188-421a-8f7c-a9ca0bad2cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30251
08253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3025108253
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.1106626211
Short name T2786
Test name
Test status
Simulation time 3490285150 ps
CPU time 27.18 seconds
Started Aug 13 06:36:34 PM PDT 24
Finished Aug 13 06:37:01 PM PDT 24
Peak memory 218336 kb
Host smart-01640f97-a44a-40b3-9662-79f21fa32360
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1106626211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.1106626211
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2218091114
Short name T3460
Test name
Test status
Simulation time 13433716442 ps
CPU time 91.29 seconds
Started Aug 13 06:36:33 PM PDT 24
Finished Aug 13 06:38:04 PM PDT 24
Peak memory 207836 kb
Host smart-889a0862-39d5-43e9-8291-37602b165e68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2218091114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2218091114
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2236888920
Short name T3041
Test name
Test status
Simulation time 196810609 ps
CPU time 0.92 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207536 kb
Host smart-b61e8039-a2da-4765-a9f7-a99a2916b652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22368
88920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2236888920
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1671550025
Short name T2709
Test name
Test status
Simulation time 25342249214 ps
CPU time 31.8 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:37:07 PM PDT 24
Peak memory 207776 kb
Host smart-2d1c2ed8-836d-4037-8486-0993cfb3edc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16715
50025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1671550025
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.4247352202
Short name T3526
Test name
Test status
Simulation time 6279561620 ps
CPU time 9.02 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:45 PM PDT 24
Peak memory 207808 kb
Host smart-fdd33365-5d4a-4b92-8e04-be10335e947d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42473
52202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.4247352202
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.2889500160
Short name T389
Test name
Test status
Simulation time 2826845775 ps
CPU time 81.77 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 218496 kb
Host smart-5f4485ac-bd04-40b1-85ad-6564551a3f9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2889500160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2889500160
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2249987769
Short name T2723
Test name
Test status
Simulation time 1540745134 ps
CPU time 11.62 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:49 PM PDT 24
Peak memory 207672 kb
Host smart-c2059ea4-49e7-4426-844d-f9d3ae0ad82f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2249987769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2249987769
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.971982136
Short name T689
Test name
Test status
Simulation time 254036869 ps
CPU time 1 seconds
Started Aug 13 06:36:35 PM PDT 24
Finished Aug 13 06:36:36 PM PDT 24
Peak memory 207484 kb
Host smart-4a576def-588d-42a0-aeca-3301c7f05a26
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=971982136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.971982136
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3398407918
Short name T2569
Test name
Test status
Simulation time 202426984 ps
CPU time 0.97 seconds
Started Aug 13 06:36:33 PM PDT 24
Finished Aug 13 06:36:34 PM PDT 24
Peak memory 207508 kb
Host smart-169a5383-cd48-42bd-a0d8-fd5a6ab54de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33984
07918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3398407918
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.3021321240
Short name T614
Test name
Test status
Simulation time 1952201149 ps
CPU time 55.22 seconds
Started Aug 13 06:36:31 PM PDT 24
Finished Aug 13 06:37:27 PM PDT 24
Peak memory 224040 kb
Host smart-4152fd97-c2ae-473d-9bc5-725b4e384c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30213
21240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.3021321240
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2140933663
Short name T736
Test name
Test status
Simulation time 3822433667 ps
CPU time 36.82 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 215948 kb
Host smart-b387f275-2f5a-4ea5-83c1-8b0ffd2b498e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2140933663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2140933663
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.2865581733
Short name T1497
Test name
Test status
Simulation time 239566426 ps
CPU time 0.95 seconds
Started Aug 13 06:36:44 PM PDT 24
Finished Aug 13 06:36:45 PM PDT 24
Peak memory 207516 kb
Host smart-defe8d5e-6203-4119-8e3f-9abf3819196e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2865581733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.2865581733
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.4115129927
Short name T3572
Test name
Test status
Simulation time 193821643 ps
CPU time 0.84 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207452 kb
Host smart-26da8349-be7b-44f0-9e0b-aa5633a1e34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41151
29927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.4115129927
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3928339055
Short name T157
Test name
Test status
Simulation time 188728906 ps
CPU time 0.94 seconds
Started Aug 13 06:36:45 PM PDT 24
Finished Aug 13 06:36:46 PM PDT 24
Peak memory 207636 kb
Host smart-be65c746-1e15-4a08-b699-4edb55b5f6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39283
39055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3928339055
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.425246683
Short name T1626
Test name
Test status
Simulation time 258260440 ps
CPU time 0.98 seconds
Started Aug 13 06:36:38 PM PDT 24
Finished Aug 13 06:36:39 PM PDT 24
Peak memory 207548 kb
Host smart-c675da65-f98b-449d-b3fc-e666243e0f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42524
6683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.425246683
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1906384196
Short name T923
Test name
Test status
Simulation time 145264443 ps
CPU time 0.91 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 207636 kb
Host smart-b62f6659-1ed9-422c-8347-d767cc279db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19063
84196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1906384196
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.4293062112
Short name T2125
Test name
Test status
Simulation time 179362862 ps
CPU time 0.92 seconds
Started Aug 13 06:36:38 PM PDT 24
Finished Aug 13 06:36:39 PM PDT 24
Peak memory 207712 kb
Host smart-5a130eda-f9a5-478e-a91a-982f75691617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42930
62112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.4293062112
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.374338480
Short name T2394
Test name
Test status
Simulation time 152928637 ps
CPU time 0.82 seconds
Started Aug 13 06:36:41 PM PDT 24
Finished Aug 13 06:36:47 PM PDT 24
Peak memory 207620 kb
Host smart-e61ead2f-76b6-42a7-8662-259e32da0048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37433
8480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.374338480
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2608894040
Short name T3182
Test name
Test status
Simulation time 222082092 ps
CPU time 1 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:39 PM PDT 24
Peak memory 207564 kb
Host smart-f04eeca1-55a0-4033-97a5-a669d7af5b0b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2608894040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2608894040
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1234558029
Short name T2517
Test name
Test status
Simulation time 144494999 ps
CPU time 0.85 seconds
Started Aug 13 06:36:43 PM PDT 24
Finished Aug 13 06:36:43 PM PDT 24
Peak memory 207436 kb
Host smart-763f0e07-3a64-4223-bf63-1f282e3c3787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12345
58029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1234558029
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.736518952
Short name T1151
Test name
Test status
Simulation time 68192280 ps
CPU time 0.74 seconds
Started Aug 13 06:36:47 PM PDT 24
Finished Aug 13 06:36:48 PM PDT 24
Peak memory 207464 kb
Host smart-a52b0f38-4599-4786-a803-291c80806b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73651
8952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.736518952
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2389579243
Short name T3144
Test name
Test status
Simulation time 22047761368 ps
CPU time 56.3 seconds
Started Aug 13 06:36:45 PM PDT 24
Finished Aug 13 06:37:42 PM PDT 24
Peak memory 215948 kb
Host smart-72e3e8da-b804-45a4-9c16-7f5b3289de36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23895
79243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2389579243
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.4238514883
Short name T2165
Test name
Test status
Simulation time 154512961 ps
CPU time 0.92 seconds
Started Aug 13 06:36:47 PM PDT 24
Finished Aug 13 06:36:48 PM PDT 24
Peak memory 207500 kb
Host smart-99e0abd7-b357-4088-9e73-20b42c85d56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42385
14883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.4238514883
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.957086531
Short name T691
Test name
Test status
Simulation time 190454582 ps
CPU time 0.89 seconds
Started Aug 13 06:36:55 PM PDT 24
Finished Aug 13 06:36:56 PM PDT 24
Peak memory 207504 kb
Host smart-adfd9cad-8c03-43f5-b40f-026512e8da2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95708
6531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.957086531
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3326517255
Short name T1804
Test name
Test status
Simulation time 231457199 ps
CPU time 0.98 seconds
Started Aug 13 06:36:40 PM PDT 24
Finished Aug 13 06:36:41 PM PDT 24
Peak memory 207536 kb
Host smart-b3df9248-7e93-4be9-a6f8-314f43da7e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33265
17255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3326517255
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3036298336
Short name T3392
Test name
Test status
Simulation time 244210631 ps
CPU time 0.96 seconds
Started Aug 13 06:36:48 PM PDT 24
Finished Aug 13 06:36:49 PM PDT 24
Peak memory 207508 kb
Host smart-19fa1cac-ac83-4268-915e-a258f4149f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30362
98336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3036298336
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1140572978
Short name T3611
Test name
Test status
Simulation time 189186717 ps
CPU time 0.98 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 207448 kb
Host smart-48c47084-e200-476c-9f0c-192a0df42851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11405
72978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1140572978
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_rx_full.2006742479
Short name T1344
Test name
Test status
Simulation time 252567347 ps
CPU time 1.1 seconds
Started Aug 13 06:36:42 PM PDT 24
Finished Aug 13 06:36:44 PM PDT 24
Peak memory 207484 kb
Host smart-981f8890-b5b8-452f-a197-25d2e816286d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20067
42479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.2006742479
Directory /workspace/20.usbdev_rx_full/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1942859831
Short name T1234
Test name
Test status
Simulation time 192543385 ps
CPU time 0.91 seconds
Started Aug 13 06:36:38 PM PDT 24
Finished Aug 13 06:36:39 PM PDT 24
Peak memory 207584 kb
Host smart-d077c3d8-366c-45ba-9a6f-296cd1c0c09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19428
59831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1942859831
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3943220497
Short name T3113
Test name
Test status
Simulation time 183493130 ps
CPU time 0.87 seconds
Started Aug 13 06:36:42 PM PDT 24
Finished Aug 13 06:36:43 PM PDT 24
Peak memory 207516 kb
Host smart-0a5d4238-2ac4-4e84-b266-acf49575eeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39432
20497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3943220497
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.993799727
Short name T3473
Test name
Test status
Simulation time 230912119 ps
CPU time 1.04 seconds
Started Aug 13 06:36:50 PM PDT 24
Finished Aug 13 06:36:52 PM PDT 24
Peak memory 207448 kb
Host smart-c6d7b258-8426-4874-8abe-6000b176fced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99379
9727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.993799727
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.550515072
Short name T1657
Test name
Test status
Simulation time 3623559498 ps
CPU time 26.68 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:37:04 PM PDT 24
Peak memory 224112 kb
Host smart-b999cfa9-65c8-4dff-9d56-d44afe8e417b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=550515072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.550515072
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.903769565
Short name T1854
Test name
Test status
Simulation time 172309978 ps
CPU time 0.86 seconds
Started Aug 13 06:36:41 PM PDT 24
Finished Aug 13 06:36:42 PM PDT 24
Peak memory 207524 kb
Host smart-ea18b1a3-eb78-463e-b645-188b0c938945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90376
9565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.903769565
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1601008883
Short name T1386
Test name
Test status
Simulation time 161140420 ps
CPU time 0.85 seconds
Started Aug 13 06:36:36 PM PDT 24
Finished Aug 13 06:36:37 PM PDT 24
Peak memory 207572 kb
Host smart-1adab6b5-123d-40c7-af84-21fdee76ba62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16010
08883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1601008883
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2850765232
Short name T2996
Test name
Test status
Simulation time 701134804 ps
CPU time 1.89 seconds
Started Aug 13 06:36:42 PM PDT 24
Finished Aug 13 06:36:44 PM PDT 24
Peak memory 207536 kb
Host smart-5aa41d08-bde2-4b54-a173-2cb063476615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28507
65232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2850765232
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.1009002499
Short name T1036
Test name
Test status
Simulation time 2932716598 ps
CPU time 21.46 seconds
Started Aug 13 06:36:38 PM PDT 24
Finished Aug 13 06:36:59 PM PDT 24
Peak memory 217772 kb
Host smart-1edb55df-65ef-4a0d-b304-3e970980009d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10090
02499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.1009002499
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.3977273686
Short name T2065
Test name
Test status
Simulation time 1523680915 ps
CPU time 9.82 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:49 PM PDT 24
Peak memory 207592 kb
Host smart-1faf74f1-7ef9-4f8f-aec0-81503bcdfd74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977273686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.3977273686
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_tx_rx_disruption.2993862470
Short name T1663
Test name
Test status
Simulation time 540700620 ps
CPU time 1.65 seconds
Started Aug 13 06:36:41 PM PDT 24
Finished Aug 13 06:36:42 PM PDT 24
Peak memory 207596 kb
Host smart-1f6c758b-4bd6-4ee5-94bf-f3472e82d956
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993862470 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.usbdev_tx_rx_disruption.2993862470
Directory /workspace/20.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/200.usbdev_tx_rx_disruption.1196330497
Short name T685
Test name
Test status
Simulation time 563002059 ps
CPU time 1.6 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207612 kb
Host smart-82c49040-9648-4698-a1f0-3d0fec63af50
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196330497 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.usbdev_tx_rx_disruption.1196330497
Directory /workspace/200.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/201.usbdev_tx_rx_disruption.2158967285
Short name T1065
Test name
Test status
Simulation time 565867864 ps
CPU time 1.51 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207612 kb
Host smart-ed730c29-9cfd-41c9-bffe-b966be3f983c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158967285 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.usbdev_tx_rx_disruption.2158967285
Directory /workspace/201.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/202.usbdev_tx_rx_disruption.3029565129
Short name T3441
Test name
Test status
Simulation time 479178309 ps
CPU time 1.46 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207608 kb
Host smart-22b70976-ee93-4f53-8361-d1fde9482ea9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029565129 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.usbdev_tx_rx_disruption.3029565129
Directory /workspace/202.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/203.usbdev_tx_rx_disruption.4256428973
Short name T2068
Test name
Test status
Simulation time 574837698 ps
CPU time 1.6 seconds
Started Aug 13 06:41:48 PM PDT 24
Finished Aug 13 06:41:50 PM PDT 24
Peak memory 207572 kb
Host smart-0417d30a-b7b5-49ef-ac53-85a1f28d6956
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256428973 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.usbdev_tx_rx_disruption.4256428973
Directory /workspace/203.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/204.usbdev_tx_rx_disruption.753442249
Short name T3580
Test name
Test status
Simulation time 564486155 ps
CPU time 1.56 seconds
Started Aug 13 06:42:04 PM PDT 24
Finished Aug 13 06:42:06 PM PDT 24
Peak memory 207612 kb
Host smart-df00da75-55f0-4044-9353-bbf9a51bbae7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753442249 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 204.usbdev_tx_rx_disruption.753442249
Directory /workspace/204.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/205.usbdev_tx_rx_disruption.2986596269
Short name T3388
Test name
Test status
Simulation time 585811485 ps
CPU time 1.78 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207576 kb
Host smart-c3713c0f-5f7d-4d29-bdd0-f6b7bc3e6133
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986596269 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.usbdev_tx_rx_disruption.2986596269
Directory /workspace/205.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/207.usbdev_tx_rx_disruption.4074573182
Short name T2080
Test name
Test status
Simulation time 485581324 ps
CPU time 1.53 seconds
Started Aug 13 06:41:48 PM PDT 24
Finished Aug 13 06:41:50 PM PDT 24
Peak memory 207600 kb
Host smart-1f119510-b964-4138-93d0-1e9c6194f740
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074573182 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.usbdev_tx_rx_disruption.4074573182
Directory /workspace/207.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/208.usbdev_tx_rx_disruption.1321595662
Short name T1943
Test name
Test status
Simulation time 455432435 ps
CPU time 1.48 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207572 kb
Host smart-d13b1847-bd48-41d8-853b-02f054916d5a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321595662 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.usbdev_tx_rx_disruption.1321595662
Directory /workspace/208.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/209.usbdev_tx_rx_disruption.590787572
Short name T1397
Test name
Test status
Simulation time 543073179 ps
CPU time 1.62 seconds
Started Aug 13 06:41:48 PM PDT 24
Finished Aug 13 06:41:50 PM PDT 24
Peak memory 207620 kb
Host smart-8ec3abf0-507f-4cfe-8328-f9b6e6faa99e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590787572 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 209.usbdev_tx_rx_disruption.590787572
Directory /workspace/209.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.560610497
Short name T1875
Test name
Test status
Simulation time 41500108 ps
CPU time 0.69 seconds
Started Aug 13 06:36:51 PM PDT 24
Finished Aug 13 06:36:52 PM PDT 24
Peak memory 207572 kb
Host smart-8ee9c2c8-e98f-4322-bee9-03b7db7a3b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=560610497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.560610497
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.809391760
Short name T2849
Test name
Test status
Simulation time 10691585372 ps
CPU time 13.81 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:50 PM PDT 24
Peak memory 207840 kb
Host smart-e53a95c4-d316-4b0f-a67c-ccc5cf17b297
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809391760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ao
n_wake_disconnect.809391760
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2438775982
Short name T1880
Test name
Test status
Simulation time 20921664508 ps
CPU time 23.52 seconds
Started Aug 13 06:36:42 PM PDT 24
Finished Aug 13 06:37:06 PM PDT 24
Peak memory 207792 kb
Host smart-4ba30684-d0f8-4888-a67e-1e255374a2db
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438775982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2438775982
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1500713455
Short name T1429
Test name
Test status
Simulation time 23505622319 ps
CPU time 27.79 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:37:05 PM PDT 24
Peak memory 215964 kb
Host smart-49702fbc-5e81-4aeb-9a5b-509fae7b69f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500713455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.1500713455
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2237813349
Short name T169
Test name
Test status
Simulation time 173450153 ps
CPU time 0.9 seconds
Started Aug 13 06:36:53 PM PDT 24
Finished Aug 13 06:36:54 PM PDT 24
Peak memory 207488 kb
Host smart-27aeeddf-762b-43c1-b569-a0cb23865948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22378
13349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2237813349
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.777354278
Short name T2239
Test name
Test status
Simulation time 168319601 ps
CPU time 0.91 seconds
Started Aug 13 06:36:53 PM PDT 24
Finished Aug 13 06:36:54 PM PDT 24
Peak memory 207572 kb
Host smart-80b0f88e-22fb-4266-ab09-7336a8e849a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77735
4278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.777354278
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2810476984
Short name T1155
Test name
Test status
Simulation time 343300051 ps
CPU time 1.33 seconds
Started Aug 13 06:36:41 PM PDT 24
Finished Aug 13 06:36:43 PM PDT 24
Peak memory 207548 kb
Host smart-96742825-deb4-40ce-bbfd-1ca40a4105c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28104
76984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2810476984
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.202180778
Short name T1181
Test name
Test status
Simulation time 531388094 ps
CPU time 1.53 seconds
Started Aug 13 06:36:57 PM PDT 24
Finished Aug 13 06:36:59 PM PDT 24
Peak memory 207604 kb
Host smart-24d116da-4d7c-4cfe-9804-e80cf25419c8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=202180778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.202180778
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.4239709683
Short name T686
Test name
Test status
Simulation time 302308541 ps
CPU time 4.47 seconds
Started Aug 13 06:36:37 PM PDT 24
Finished Aug 13 06:36:42 PM PDT 24
Peak memory 207740 kb
Host smart-2a8ce69e-3663-4d18-88f8-c388d7fcecce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239709683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.4239709683
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3323633632
Short name T1286
Test name
Test status
Simulation time 637898216 ps
CPU time 1.63 seconds
Started Aug 13 06:36:43 PM PDT 24
Finished Aug 13 06:36:45 PM PDT 24
Peak memory 207544 kb
Host smart-c5669aa6-7c6e-46ad-87f8-158f2bd5b571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33236
33632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3323633632
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.904199771
Short name T3061
Test name
Test status
Simulation time 185901603 ps
CPU time 0.9 seconds
Started Aug 13 06:36:51 PM PDT 24
Finished Aug 13 06:36:52 PM PDT 24
Peak memory 207512 kb
Host smart-a80fc238-201e-40ab-9230-d385da4069b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90419
9771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.904199771
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1910795971
Short name T1382
Test name
Test status
Simulation time 48561571 ps
CPU time 0.73 seconds
Started Aug 13 06:36:46 PM PDT 24
Finished Aug 13 06:36:46 PM PDT 24
Peak memory 207404 kb
Host smart-3fc07ae9-2c99-4316-8f8a-caeebdbf8841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19107
95971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1910795971
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.557350955
Short name T2195
Test name
Test status
Simulation time 714265602 ps
CPU time 2.05 seconds
Started Aug 13 06:36:47 PM PDT 24
Finished Aug 13 06:36:49 PM PDT 24
Peak memory 207820 kb
Host smart-a693bf87-e84e-43e3-9321-737cc3f2362f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55735
0955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.557350955
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_types.2604003154
Short name T403
Test name
Test status
Simulation time 384403474 ps
CPU time 1.2 seconds
Started Aug 13 06:36:40 PM PDT 24
Finished Aug 13 06:36:42 PM PDT 24
Peak memory 207508 kb
Host smart-2b6b7767-b7b3-4547-a446-b9e84e40292c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2604003154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.2604003154
Directory /workspace/21.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1962694283
Short name T956
Test name
Test status
Simulation time 172761644 ps
CPU time 2.03 seconds
Started Aug 13 06:36:47 PM PDT 24
Finished Aug 13 06:36:49 PM PDT 24
Peak memory 207684 kb
Host smart-efe59227-f47a-4e68-b723-abf39004d397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19626
94283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1962694283
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.4023051112
Short name T3571
Test name
Test status
Simulation time 229674678 ps
CPU time 1.21 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 215824 kb
Host smart-abb13c0e-32e9-436c-b695-e9a0933a870a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4023051112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.4023051112
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1736424371
Short name T2776
Test name
Test status
Simulation time 140408381 ps
CPU time 0.85 seconds
Started Aug 13 06:36:47 PM PDT 24
Finished Aug 13 06:36:48 PM PDT 24
Peak memory 207416 kb
Host smart-82d7fb47-2671-4302-b309-4071617aa342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17364
24371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1736424371
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1907839569
Short name T3361
Test name
Test status
Simulation time 219775142 ps
CPU time 0.99 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 207452 kb
Host smart-5c225a6d-ae67-4675-bbef-343c02631c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19078
39569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1907839569
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.2108382985
Short name T2718
Test name
Test status
Simulation time 3073065036 ps
CPU time 85.65 seconds
Started Aug 13 06:36:40 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 224196 kb
Host smart-88c4a77a-b65a-45d2-8ca5-c7890ad05efa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2108382985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.2108382985
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.3996729377
Short name T694
Test name
Test status
Simulation time 5115581777 ps
CPU time 60.86 seconds
Started Aug 13 06:36:41 PM PDT 24
Finished Aug 13 06:37:42 PM PDT 24
Peak memory 207812 kb
Host smart-dd8eef4a-56fc-4316-9ccd-1d85663f5c59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3996729377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.3996729377
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3034110884
Short name T3208
Test name
Test status
Simulation time 244559290 ps
CPU time 1.02 seconds
Started Aug 13 06:36:47 PM PDT 24
Finished Aug 13 06:36:48 PM PDT 24
Peak memory 207584 kb
Host smart-417b8ada-461d-4e12-a1df-224113094637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30341
10884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3034110884
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.1162094911
Short name T3161
Test name
Test status
Simulation time 7304026496 ps
CPU time 10.35 seconds
Started Aug 13 06:36:41 PM PDT 24
Finished Aug 13 06:36:51 PM PDT 24
Peak memory 216652 kb
Host smart-89a17767-081b-4aaa-83b8-75623d1e09b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11620
94911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1162094911
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2866320341
Short name T1208
Test name
Test status
Simulation time 8344254527 ps
CPU time 10.62 seconds
Started Aug 13 06:36:43 PM PDT 24
Finished Aug 13 06:36:54 PM PDT 24
Peak memory 207876 kb
Host smart-c64fd871-c104-4229-9d55-f614f86487ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28663
20341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2866320341
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.13519864
Short name T1311
Test name
Test status
Simulation time 4212952484 ps
CPU time 44.92 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:37:24 PM PDT 24
Peak memory 218712 kb
Host smart-c6ea5fb5-2060-4388-a678-1950a57bacb6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=13519864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.13519864
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2837269089
Short name T3574
Test name
Test status
Simulation time 3420269053 ps
CPU time 97.86 seconds
Started Aug 13 06:37:00 PM PDT 24
Finished Aug 13 06:38:38 PM PDT 24
Peak memory 217376 kb
Host smart-7676057c-cab9-4fe8-a60e-a82a26d0c0cf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2837269089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2837269089
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2719052209
Short name T1133
Test name
Test status
Simulation time 235497098 ps
CPU time 1.06 seconds
Started Aug 13 06:36:41 PM PDT 24
Finished Aug 13 06:36:43 PM PDT 24
Peak memory 207528 kb
Host smart-3a354e1e-db92-4829-be50-acc4dd92688e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2719052209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2719052209
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2957395943
Short name T3078
Test name
Test status
Simulation time 226598995 ps
CPU time 1 seconds
Started Aug 13 06:36:40 PM PDT 24
Finished Aug 13 06:36:41 PM PDT 24
Peak memory 207468 kb
Host smart-7922e935-a417-428b-80cf-e7aeef6b662c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29573
95943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2957395943
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.576176609
Short name T3180
Test name
Test status
Simulation time 2595338780 ps
CPU time 21.57 seconds
Started Aug 13 06:37:01 PM PDT 24
Finished Aug 13 06:37:23 PM PDT 24
Peak memory 217920 kb
Host smart-7bc64156-76f9-4462-8a92-bf93f4d54a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57617
6609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.576176609
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3531446096
Short name T576
Test name
Test status
Simulation time 2579790302 ps
CPU time 79.74 seconds
Started Aug 13 06:36:38 PM PDT 24
Finished Aug 13 06:37:58 PM PDT 24
Peak memory 215856 kb
Host smart-3037b3fc-05b4-4ef0-8753-64e4153c9acd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3531446096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3531446096
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.2013359771
Short name T3464
Test name
Test status
Simulation time 172164853 ps
CPU time 0.89 seconds
Started Aug 13 06:36:39 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 207504 kb
Host smart-5415154f-38aa-4fac-8482-95f35b34ab05
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2013359771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.2013359771
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2220468863
Short name T3390
Test name
Test status
Simulation time 150268086 ps
CPU time 0.81 seconds
Started Aug 13 06:36:56 PM PDT 24
Finished Aug 13 06:36:57 PM PDT 24
Peak memory 207492 kb
Host smart-3a264a00-9d24-4273-b644-669a333a9cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22204
68863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2220468863
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2447596631
Short name T1277
Test name
Test status
Simulation time 199865543 ps
CPU time 0.92 seconds
Started Aug 13 06:36:56 PM PDT 24
Finished Aug 13 06:36:57 PM PDT 24
Peak memory 207516 kb
Host smart-3c5d044d-2b48-4fc4-a3fd-e6b264cf7bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24475
96631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2447596631
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2064553707
Short name T2146
Test name
Test status
Simulation time 208694047 ps
CPU time 0.89 seconds
Started Aug 13 06:37:04 PM PDT 24
Finished Aug 13 06:37:06 PM PDT 24
Peak memory 207532 kb
Host smart-b01e3d90-f3b9-4423-9914-d1f6ed8c9c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20645
53707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2064553707
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2025820584
Short name T2470
Test name
Test status
Simulation time 196807849 ps
CPU time 0.9 seconds
Started Aug 13 06:36:52 PM PDT 24
Finished Aug 13 06:36:53 PM PDT 24
Peak memory 207588 kb
Host smart-485b1e74-23fd-4122-b718-3e488f7281ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20258
20584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2025820584
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3730088883
Short name T1390
Test name
Test status
Simulation time 194802314 ps
CPU time 0.93 seconds
Started Aug 13 06:36:54 PM PDT 24
Finished Aug 13 06:36:55 PM PDT 24
Peak memory 207568 kb
Host smart-044322d1-8d17-4dc8-a3b1-f50c5d24fee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37300
88883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3730088883
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.865325315
Short name T2419
Test name
Test status
Simulation time 208750655 ps
CPU time 1 seconds
Started Aug 13 06:37:01 PM PDT 24
Finished Aug 13 06:37:02 PM PDT 24
Peak memory 207524 kb
Host smart-bb1720b5-fb67-4f9c-98ff-f097acdaaf04
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=865325315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.865325315
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3774398903
Short name T3525
Test name
Test status
Simulation time 136129393 ps
CPU time 0.83 seconds
Started Aug 13 06:37:01 PM PDT 24
Finished Aug 13 06:37:02 PM PDT 24
Peak memory 207476 kb
Host smart-d23f9323-65bf-42bf-9c6b-d2d82a947917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37743
98903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3774398903
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1540576489
Short name T258
Test name
Test status
Simulation time 17426787146 ps
CPU time 43.42 seconds
Started Aug 13 06:36:56 PM PDT 24
Finished Aug 13 06:37:39 PM PDT 24
Peak memory 224168 kb
Host smart-693766c0-0544-46af-b25c-eee43185ae5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15405
76489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1540576489
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3929380647
Short name T2982
Test name
Test status
Simulation time 233537052 ps
CPU time 1.01 seconds
Started Aug 13 06:36:55 PM PDT 24
Finished Aug 13 06:36:56 PM PDT 24
Peak memory 207604 kb
Host smart-b145af71-92d3-4d6d-a753-8a6424d2be41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39293
80647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3929380647
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.540727266
Short name T2806
Test name
Test status
Simulation time 239132354 ps
CPU time 1.01 seconds
Started Aug 13 06:36:54 PM PDT 24
Finished Aug 13 06:36:55 PM PDT 24
Peak memory 207636 kb
Host smart-b77da59f-214b-4a89-b37f-00d510a9f51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54072
7266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.540727266
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.203401238
Short name T1618
Test name
Test status
Simulation time 164606274 ps
CPU time 0.9 seconds
Started Aug 13 06:36:59 PM PDT 24
Finished Aug 13 06:37:00 PM PDT 24
Peak memory 207456 kb
Host smart-d3aa897c-f0ef-4032-9b84-942c66cb910b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20340
1238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.203401238
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.610305227
Short name T1218
Test name
Test status
Simulation time 177579587 ps
CPU time 0.89 seconds
Started Aug 13 06:36:57 PM PDT 24
Finished Aug 13 06:36:58 PM PDT 24
Peak memory 207504 kb
Host smart-539bc928-c466-4bff-b00d-146d5c4cdaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61030
5227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.610305227
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.154689719
Short name T938
Test name
Test status
Simulation time 199973534 ps
CPU time 0.93 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 207512 kb
Host smart-f431e36f-0965-4e6e-b639-684029e22a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15468
9719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.154689719
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_rx_full.2674989310
Short name T2356
Test name
Test status
Simulation time 434106266 ps
CPU time 1.34 seconds
Started Aug 13 06:36:46 PM PDT 24
Finished Aug 13 06:36:47 PM PDT 24
Peak memory 207528 kb
Host smart-9b13b185-7c27-4260-a0a3-a854ee082d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26749
89310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.2674989310
Directory /workspace/21.usbdev_rx_full/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.20299101
Short name T2927
Test name
Test status
Simulation time 153564600 ps
CPU time 0.84 seconds
Started Aug 13 06:36:59 PM PDT 24
Finished Aug 13 06:37:00 PM PDT 24
Peak memory 207476 kb
Host smart-7d300d9c-c9ec-4a5c-a80b-943e3818a23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20299
101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.20299101
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3363552318
Short name T2588
Test name
Test status
Simulation time 169056980 ps
CPU time 0.93 seconds
Started Aug 13 06:36:51 PM PDT 24
Finished Aug 13 06:36:52 PM PDT 24
Peak memory 207472 kb
Host smart-0e194343-3675-44e3-9c85-d27399d04a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33635
52318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3363552318
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1686920304
Short name T1347
Test name
Test status
Simulation time 213768309 ps
CPU time 1.02 seconds
Started Aug 13 06:36:51 PM PDT 24
Finished Aug 13 06:36:52 PM PDT 24
Peak memory 207488 kb
Host smart-3532a191-6848-4e68-8408-bb481050a29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869
20304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1686920304
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.574955210
Short name T3470
Test name
Test status
Simulation time 2095445910 ps
CPU time 59.25 seconds
Started Aug 13 06:36:55 PM PDT 24
Finished Aug 13 06:37:55 PM PDT 24
Peak memory 217364 kb
Host smart-3e0bdc0c-3934-4731-91c1-f12cea635876
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=574955210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.574955210
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.728076142
Short name T2197
Test name
Test status
Simulation time 180498836 ps
CPU time 0.92 seconds
Started Aug 13 06:37:02 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207420 kb
Host smart-89fe5547-fe20-4e00-a318-addfdfc23b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72807
6142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.728076142
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.836736482
Short name T573
Test name
Test status
Simulation time 151629607 ps
CPU time 0.82 seconds
Started Aug 13 06:37:01 PM PDT 24
Finished Aug 13 06:37:02 PM PDT 24
Peak memory 207616 kb
Host smart-59bcb3b4-4bec-4806-a688-21284370da4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83673
6482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.836736482
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.4274709176
Short name T1848
Test name
Test status
Simulation time 1333291741 ps
CPU time 3.15 seconds
Started Aug 13 06:36:59 PM PDT 24
Finished Aug 13 06:37:02 PM PDT 24
Peak memory 207776 kb
Host smart-f5de9776-af1e-4097-be38-6cf11a4e262f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42747
09176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.4274709176
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2645093522
Short name T713
Test name
Test status
Simulation time 2476578026 ps
CPU time 18.86 seconds
Started Aug 13 06:36:54 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 215940 kb
Host smart-f1861708-1878-418b-9db5-12abd3bca5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26450
93522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2645093522
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.2470189112
Short name T2584
Test name
Test status
Simulation time 147048754 ps
CPU time 0.86 seconds
Started Aug 13 06:36:51 PM PDT 24
Finished Aug 13 06:36:52 PM PDT 24
Peak memory 207504 kb
Host smart-1339f8b8-8031-45b5-a304-fc098a051169
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470189112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.2470189112
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_tx_rx_disruption.2969719695
Short name T2565
Test name
Test status
Simulation time 464695823 ps
CPU time 1.57 seconds
Started Aug 13 06:36:58 PM PDT 24
Finished Aug 13 06:37:00 PM PDT 24
Peak memory 207620 kb
Host smart-6b48c2bb-bd5d-4ec3-9d0b-374304627aa3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969719695 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.usbdev_tx_rx_disruption.2969719695
Directory /workspace/21.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/210.usbdev_tx_rx_disruption.1366454209
Short name T3015
Test name
Test status
Simulation time 569202439 ps
CPU time 1.61 seconds
Started Aug 13 06:42:13 PM PDT 24
Finished Aug 13 06:42:14 PM PDT 24
Peak memory 207476 kb
Host smart-e4bf9849-903f-4473-8c0d-ad34acae1a08
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366454209 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 210.usbdev_tx_rx_disruption.1366454209
Directory /workspace/210.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/211.usbdev_tx_rx_disruption.1210428761
Short name T3263
Test name
Test status
Simulation time 539439950 ps
CPU time 1.57 seconds
Started Aug 13 06:42:05 PM PDT 24
Finished Aug 13 06:42:06 PM PDT 24
Peak memory 207588 kb
Host smart-75e091a8-82a9-44ef-962b-65879094fa81
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210428761 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.usbdev_tx_rx_disruption.1210428761
Directory /workspace/211.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/212.usbdev_tx_rx_disruption.3362366233
Short name T3360
Test name
Test status
Simulation time 465072001 ps
CPU time 1.44 seconds
Started Aug 13 06:41:48 PM PDT 24
Finished Aug 13 06:41:49 PM PDT 24
Peak memory 207588 kb
Host smart-0575c948-95ad-4086-867b-ecd0aaa2553f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362366233 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.usbdev_tx_rx_disruption.3362366233
Directory /workspace/212.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/213.usbdev_tx_rx_disruption.1145379016
Short name T2361
Test name
Test status
Simulation time 651348396 ps
CPU time 1.71 seconds
Started Aug 13 06:41:55 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207628 kb
Host smart-d5c2071a-ee59-4948-9f0a-54b72f614939
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145379016 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.usbdev_tx_rx_disruption.1145379016
Directory /workspace/213.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/214.usbdev_tx_rx_disruption.199867731
Short name T2280
Test name
Test status
Simulation time 456557851 ps
CPU time 1.4 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207604 kb
Host smart-0ed5d564-ceee-44bf-a849-d8e592da3cd1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199867731 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 214.usbdev_tx_rx_disruption.199867731
Directory /workspace/214.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/215.usbdev_tx_rx_disruption.2382447140
Short name T1467
Test name
Test status
Simulation time 444743784 ps
CPU time 1.43 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207496 kb
Host smart-5107a36d-5d88-40c7-be79-23f556ef4e83
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382447140 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.usbdev_tx_rx_disruption.2382447140
Directory /workspace/215.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/216.usbdev_tx_rx_disruption.535971844
Short name T1921
Test name
Test status
Simulation time 510900794 ps
CPU time 1.58 seconds
Started Aug 13 06:42:09 PM PDT 24
Finished Aug 13 06:42:11 PM PDT 24
Peak memory 207508 kb
Host smart-878014d5-6e65-4523-867d-5fe555c510c3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535971844 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 216.usbdev_tx_rx_disruption.535971844
Directory /workspace/216.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/217.usbdev_tx_rx_disruption.1736234304
Short name T2490
Test name
Test status
Simulation time 678601839 ps
CPU time 1.74 seconds
Started Aug 13 06:41:43 PM PDT 24
Finished Aug 13 06:41:45 PM PDT 24
Peak memory 207572 kb
Host smart-7bb50aeb-0763-4863-930d-5b227f40d983
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736234304 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.usbdev_tx_rx_disruption.1736234304
Directory /workspace/217.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/218.usbdev_tx_rx_disruption.1658547944
Short name T1169
Test name
Test status
Simulation time 567208715 ps
CPU time 1.68 seconds
Started Aug 13 06:41:55 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207600 kb
Host smart-6da8380f-bda0-4491-a57e-df5de59b1181
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658547944 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.usbdev_tx_rx_disruption.1658547944
Directory /workspace/218.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/219.usbdev_tx_rx_disruption.2427319291
Short name T3109
Test name
Test status
Simulation time 545708917 ps
CPU time 1.52 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207572 kb
Host smart-8ef1d807-217a-4fe1-a733-dbd1c192efeb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427319291 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.usbdev_tx_rx_disruption.2427319291
Directory /workspace/219.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.739972173
Short name T3172
Test name
Test status
Simulation time 75361266 ps
CPU time 0.75 seconds
Started Aug 13 06:37:01 PM PDT 24
Finished Aug 13 06:37:02 PM PDT 24
Peak memory 207440 kb
Host smart-f707b8e1-077e-4cc6-9bd3-0ea8b248b92b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=739972173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.739972173
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3644701733
Short name T981
Test name
Test status
Simulation time 9069064596 ps
CPU time 11.71 seconds
Started Aug 13 06:37:05 PM PDT 24
Finished Aug 13 06:37:17 PM PDT 24
Peak memory 207820 kb
Host smart-f0f8dffd-a1d9-42fc-bfff-5fc4e016d6f1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644701733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.3644701733
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3417755114
Short name T3178
Test name
Test status
Simulation time 13317635327 ps
CPU time 15.41 seconds
Started Aug 13 06:36:56 PM PDT 24
Finished Aug 13 06:37:12 PM PDT 24
Peak memory 216032 kb
Host smart-74223bb2-c5ab-4d02-b569-e50d64b8391b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417755114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3417755114
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1472382718
Short name T2281
Test name
Test status
Simulation time 31499551236 ps
CPU time 41.04 seconds
Started Aug 13 06:36:50 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207872 kb
Host smart-2ea71635-f762-4f5b-95f6-36cd09da1c5a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472382718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_resume.1472382718
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.995628522
Short name T1270
Test name
Test status
Simulation time 187830475 ps
CPU time 0.91 seconds
Started Aug 13 06:36:56 PM PDT 24
Finished Aug 13 06:36:57 PM PDT 24
Peak memory 207544 kb
Host smart-49997759-68c3-4e9d-ab63-617e85b2c70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99562
8522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.995628522
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.279763778
Short name T809
Test name
Test status
Simulation time 157770761 ps
CPU time 0.86 seconds
Started Aug 13 06:37:02 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207604 kb
Host smart-c54dae53-8f1c-4b91-bf3d-c48094b25a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27976
3778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.279763778
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3803130964
Short name T1283
Test name
Test status
Simulation time 286195481 ps
CPU time 1.15 seconds
Started Aug 13 06:36:58 PM PDT 24
Finished Aug 13 06:36:59 PM PDT 24
Peak memory 207588 kb
Host smart-307b3da4-9d32-43d5-9a9b-0c6f4552fdb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38031
30964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3803130964
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1307881540
Short name T341
Test name
Test status
Simulation time 350462217 ps
CPU time 1.37 seconds
Started Aug 13 06:36:52 PM PDT 24
Finished Aug 13 06:36:53 PM PDT 24
Peak memory 207492 kb
Host smart-ca8a0e7c-3fa5-4349-82bc-9d352a089bf1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1307881540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1307881540
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3111580956
Short name T2000
Test name
Test status
Simulation time 50174206885 ps
CPU time 95.36 seconds
Started Aug 13 06:36:46 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207828 kb
Host smart-eef6b676-675a-4ee3-9207-ac000167023e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31115
80956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3111580956
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.3988404643
Short name T1736
Test name
Test status
Simulation time 602187358 ps
CPU time 11.83 seconds
Started Aug 13 06:37:06 PM PDT 24
Finished Aug 13 06:37:18 PM PDT 24
Peak memory 207776 kb
Host smart-87d823bb-53a3-41dd-af7a-755b29304ef1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988404643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.3988404643
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.765800731
Short name T387
Test name
Test status
Simulation time 543019019 ps
CPU time 1.48 seconds
Started Aug 13 06:36:56 PM PDT 24
Finished Aug 13 06:36:57 PM PDT 24
Peak memory 207504 kb
Host smart-e5a2979a-7229-40a6-b184-efb977b416e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76580
0731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.765800731
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.589576299
Short name T35
Test name
Test status
Simulation time 158969825 ps
CPU time 0.85 seconds
Started Aug 13 06:36:45 PM PDT 24
Finished Aug 13 06:36:46 PM PDT 24
Peak memory 207484 kb
Host smart-34a024dd-b717-4378-9f80-04cbc8c3aa82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58957
6299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.589576299
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2665968057
Short name T702
Test name
Test status
Simulation time 40471967 ps
CPU time 0.71 seconds
Started Aug 13 06:37:06 PM PDT 24
Finished Aug 13 06:37:06 PM PDT 24
Peak memory 207500 kb
Host smart-2c0cdeb8-2aa9-428c-8cf0-cd2d5f800549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
68057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2665968057
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1442700383
Short name T2988
Test name
Test status
Simulation time 795435608 ps
CPU time 2.41 seconds
Started Aug 13 06:37:04 PM PDT 24
Finished Aug 13 06:37:06 PM PDT 24
Peak memory 207788 kb
Host smart-0377a070-3c11-42d2-bbcf-81a2574ddf66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14427
00383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1442700383
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_types.1537328362
Short name T3201
Test name
Test status
Simulation time 381242191 ps
CPU time 1.26 seconds
Started Aug 13 06:37:01 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207552 kb
Host smart-0f50a614-2011-454d-bf5e-3423f604cdd6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1537328362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.1537328362
Directory /workspace/22.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.444371580
Short name T1168
Test name
Test status
Simulation time 161109167 ps
CPU time 1.68 seconds
Started Aug 13 06:37:01 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207588 kb
Host smart-21d7630f-55b9-49e6-854a-2e0c96e270c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44437
1580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.444371580
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1814389825
Short name T3613
Test name
Test status
Simulation time 217470806 ps
CPU time 1.1 seconds
Started Aug 13 06:36:50 PM PDT 24
Finished Aug 13 06:36:51 PM PDT 24
Peak memory 215896 kb
Host smart-8419ce87-eb24-4a66-b9a8-a2b5130dfaf2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1814389825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1814389825
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.291809014
Short name T122
Test name
Test status
Simulation time 153473054 ps
CPU time 0.85 seconds
Started Aug 13 06:36:51 PM PDT 24
Finished Aug 13 06:36:52 PM PDT 24
Peak memory 207412 kb
Host smart-d17bf124-7599-459a-aae6-1b93af7be89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29180
9014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.291809014
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.274497222
Short name T38
Test name
Test status
Simulation time 294296912 ps
CPU time 1.11 seconds
Started Aug 13 06:37:03 PM PDT 24
Finished Aug 13 06:37:04 PM PDT 24
Peak memory 207540 kb
Host smart-bdc97706-e687-4921-a9eb-2c8331df417d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27449
7222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.274497222
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1126792353
Short name T3523
Test name
Test status
Simulation time 3473895585 ps
CPU time 36.45 seconds
Started Aug 13 06:36:52 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 217836 kb
Host smart-5d455e43-1683-43ec-a201-64cdad413e02
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1126792353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1126792353
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.1408581264
Short name T92
Test name
Test status
Simulation time 12564550656 ps
CPU time 95.18 seconds
Started Aug 13 06:36:50 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207828 kb
Host smart-a7c32761-ea5c-43e3-a8c6-22e2a64dc583
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1408581264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1408581264
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3570487889
Short name T2992
Test name
Test status
Simulation time 167828589 ps
CPU time 0.88 seconds
Started Aug 13 06:36:58 PM PDT 24
Finished Aug 13 06:36:59 PM PDT 24
Peak memory 207584 kb
Host smart-fdb90527-dee5-49c9-bb7c-cb92624c768b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35704
87889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3570487889
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.2657270489
Short name T1734
Test name
Test status
Simulation time 22147280605 ps
CPU time 40.66 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:49 PM PDT 24
Peak memory 216100 kb
Host smart-85de943a-95f2-4d54-820c-00a69dac6742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26572
70489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.2657270489
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3484843851
Short name T2410
Test name
Test status
Simulation time 6114222350 ps
CPU time 8.58 seconds
Started Aug 13 06:37:04 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 216812 kb
Host smart-afb1216b-088a-4a19-84ef-563156f74ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34848
43851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3484843851
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.2837018971
Short name T528
Test name
Test status
Simulation time 2623484700 ps
CPU time 19.48 seconds
Started Aug 13 06:36:52 PM PDT 24
Finished Aug 13 06:37:12 PM PDT 24
Peak memory 224224 kb
Host smart-70d6ddce-da99-40b6-a838-861fa5d1e039
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2837018971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2837018971
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.2790397824
Short name T1949
Test name
Test status
Simulation time 2187421914 ps
CPU time 18.2 seconds
Started Aug 13 06:37:00 PM PDT 24
Finished Aug 13 06:37:19 PM PDT 24
Peak memory 217252 kb
Host smart-0477fb95-b053-4357-8435-744ae99efd9e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2790397824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.2790397824
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1646242247
Short name T1493
Test name
Test status
Simulation time 242236235 ps
CPU time 0.98 seconds
Started Aug 13 06:37:00 PM PDT 24
Finished Aug 13 06:37:01 PM PDT 24
Peak memory 207520 kb
Host smart-84f0c1ad-3e4b-4791-a806-b08610b0ccba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1646242247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1646242247
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2028326052
Short name T1795
Test name
Test status
Simulation time 186510047 ps
CPU time 0.96 seconds
Started Aug 13 06:36:53 PM PDT 24
Finished Aug 13 06:36:54 PM PDT 24
Peak memory 207488 kb
Host smart-a708f317-cddf-4bc5-be88-5c0fe86be508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20283
26052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2028326052
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.3797514651
Short name T2949
Test name
Test status
Simulation time 3193539065 ps
CPU time 87.63 seconds
Started Aug 13 06:36:56 PM PDT 24
Finished Aug 13 06:38:24 PM PDT 24
Peak memory 224040 kb
Host smart-0e0764b4-22c2-482b-8d9e-2b90f554512a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37975
14651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.3797514651
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.4122122817
Short name T2749
Test name
Test status
Simulation time 2428611348 ps
CPU time 66.06 seconds
Started Aug 13 06:36:59 PM PDT 24
Finished Aug 13 06:38:06 PM PDT 24
Peak memory 217664 kb
Host smart-492b96dc-bdf2-4bd4-8d0a-de6090b4027e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4122122817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.4122122817
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.3389051551
Short name T2660
Test name
Test status
Simulation time 161086431 ps
CPU time 0.86 seconds
Started Aug 13 06:36:50 PM PDT 24
Finished Aug 13 06:36:51 PM PDT 24
Peak memory 207484 kb
Host smart-723a9dc8-52f2-412b-bac2-a17cebe5ee61
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3389051551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.3389051551
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3917394001
Short name T2451
Test name
Test status
Simulation time 163344107 ps
CPU time 0.94 seconds
Started Aug 13 06:37:02 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207528 kb
Host smart-200ee697-b713-40d3-8579-e5c3f6c8872a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39173
94001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3917394001
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2634141326
Short name T3483
Test name
Test status
Simulation time 266372197 ps
CPU time 1.01 seconds
Started Aug 13 06:36:57 PM PDT 24
Finished Aug 13 06:36:58 PM PDT 24
Peak memory 207516 kb
Host smart-4ff943e6-00f4-4adc-bd1b-a5695717e124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26341
41326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2634141326
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1980143183
Short name T1700
Test name
Test status
Simulation time 183073295 ps
CPU time 0.93 seconds
Started Aug 13 06:36:59 PM PDT 24
Finished Aug 13 06:37:00 PM PDT 24
Peak memory 207448 kb
Host smart-646af2c8-0b15-44f8-a319-e8361106e52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19801
43183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1980143183
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1197164187
Short name T1203
Test name
Test status
Simulation time 178581098 ps
CPU time 0.94 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:09 PM PDT 24
Peak memory 207528 kb
Host smart-774fe942-199e-4030-85db-4ccac41b261a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11971
64187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1197164187
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1587558668
Short name T2939
Test name
Test status
Simulation time 184171309 ps
CPU time 0.93 seconds
Started Aug 13 06:37:02 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207608 kb
Host smart-43cda386-32d4-4ed6-b376-fa68bbe16a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15875
58668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1587558668
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1429736117
Short name T2025
Test name
Test status
Simulation time 219790553 ps
CPU time 1.07 seconds
Started Aug 13 06:37:07 PM PDT 24
Finished Aug 13 06:37:08 PM PDT 24
Peak memory 207592 kb
Host smart-ac90bda7-13e3-425a-a206-9cbd57086396
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1429736117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1429736117
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2489042571
Short name T2269
Test name
Test status
Simulation time 162090418 ps
CPU time 0.87 seconds
Started Aug 13 06:37:00 PM PDT 24
Finished Aug 13 06:37:01 PM PDT 24
Peak memory 207480 kb
Host smart-5d365ab6-d704-4f9f-a721-e9edee547b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24890
42571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2489042571
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.319408700
Short name T2987
Test name
Test status
Simulation time 39922201 ps
CPU time 0.75 seconds
Started Aug 13 06:37:00 PM PDT 24
Finished Aug 13 06:37:01 PM PDT 24
Peak memory 207560 kb
Host smart-d28d47e1-85ad-45a0-818d-c7a2b8409ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31940
8700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.319408700
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.686549089
Short name T295
Test name
Test status
Simulation time 7476091427 ps
CPU time 19.76 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 215940 kb
Host smart-7a7ac683-1b4d-4f1c-831b-d88dbfa3fef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68654
9089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.686549089
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3825868394
Short name T2229
Test name
Test status
Simulation time 205044057 ps
CPU time 1 seconds
Started Aug 13 06:37:01 PM PDT 24
Finished Aug 13 06:37:02 PM PDT 24
Peak memory 207588 kb
Host smart-c137ccc2-7bb8-4507-be4e-33c06034aad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38258
68394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3825868394
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2950713432
Short name T2494
Test name
Test status
Simulation time 216443544 ps
CPU time 0.93 seconds
Started Aug 13 06:37:02 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207396 kb
Host smart-b7acc41e-58e3-4188-bca8-087965e4ab87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29507
13432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2950713432
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.3990538727
Short name T2184
Test name
Test status
Simulation time 190901207 ps
CPU time 0.92 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:09 PM PDT 24
Peak memory 207492 kb
Host smart-65e6d974-3f57-4422-8868-44c8991cdebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39905
38727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.3990538727
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3106822327
Short name T2509
Test name
Test status
Simulation time 182602430 ps
CPU time 0.94 seconds
Started Aug 13 06:36:56 PM PDT 24
Finished Aug 13 06:36:57 PM PDT 24
Peak memory 207528 kb
Host smart-f2cabe4b-1028-431b-830f-f50b5a733094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31068
22327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3106822327
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1436874427
Short name T3504
Test name
Test status
Simulation time 179385320 ps
CPU time 0.84 seconds
Started Aug 13 06:37:15 PM PDT 24
Finished Aug 13 06:37:16 PM PDT 24
Peak memory 207460 kb
Host smart-b3efc28d-1d7e-442a-8ff6-b7e1695dedd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14368
74427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1436874427
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_rx_full.1802110611
Short name T1529
Test name
Test status
Simulation time 344863743 ps
CPU time 1.25 seconds
Started Aug 13 06:37:04 PM PDT 24
Finished Aug 13 06:37:05 PM PDT 24
Peak memory 207496 kb
Host smart-b5da8bfd-b46e-474e-a0e9-7f8fb89073f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18021
10611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.1802110611
Directory /workspace/22.usbdev_rx_full/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2493372832
Short name T2433
Test name
Test status
Simulation time 180841936 ps
CPU time 0.9 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:37:12 PM PDT 24
Peak memory 207556 kb
Host smart-32038b12-2ce1-4b0f-a92b-49bb69d265f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24933
72832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2493372832
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3096376530
Short name T1013
Test name
Test status
Simulation time 160948048 ps
CPU time 0.84 seconds
Started Aug 13 06:37:14 PM PDT 24
Finished Aug 13 06:37:15 PM PDT 24
Peak memory 207500 kb
Host smart-117aa628-08b3-4b89-9455-c5c1a8b262c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30963
76530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3096376530
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.247636016
Short name T2886
Test name
Test status
Simulation time 217201883 ps
CPU time 1.06 seconds
Started Aug 13 06:37:00 PM PDT 24
Finished Aug 13 06:37:02 PM PDT 24
Peak memory 207448 kb
Host smart-be78b405-9ed0-4021-9883-00aece9b920c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24763
6016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.247636016
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2360075367
Short name T1714
Test name
Test status
Simulation time 2059621296 ps
CPU time 55.58 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:38:06 PM PDT 24
Peak memory 223996 kb
Host smart-2d433fb9-5db6-4686-a6a0-200bcb34028d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2360075367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2360075367
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2471038251
Short name T1110
Test name
Test status
Simulation time 179386127 ps
CPU time 0.96 seconds
Started Aug 13 06:37:05 PM PDT 24
Finished Aug 13 06:37:06 PM PDT 24
Peak memory 207484 kb
Host smart-349ca18b-2da8-4495-b683-deb7dc472d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24710
38251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2471038251
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1782515622
Short name T1661
Test name
Test status
Simulation time 161825456 ps
CPU time 0.9 seconds
Started Aug 13 06:37:09 PM PDT 24
Finished Aug 13 06:37:10 PM PDT 24
Peak memory 207552 kb
Host smart-15b4f4f8-e272-4e90-a9c3-cbc6b0ac2233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17825
15622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1782515622
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3430823027
Short name T3053
Test name
Test status
Simulation time 383976493 ps
CPU time 1.28 seconds
Started Aug 13 06:37:14 PM PDT 24
Finished Aug 13 06:37:15 PM PDT 24
Peak memory 207436 kb
Host smart-35cf4fae-aad4-4e8f-bcaf-13d0b5a9a032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34308
23027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3430823027
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.1686768302
Short name T1597
Test name
Test status
Simulation time 2008251503 ps
CPU time 57.46 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:38:08 PM PDT 24
Peak memory 217216 kb
Host smart-36de8bab-d8b1-4190-8ddb-73d9d98597a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16867
68302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.1686768302
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.71915120
Short name T3623
Test name
Test status
Simulation time 699150205 ps
CPU time 15.16 seconds
Started Aug 13 06:37:05 PM PDT 24
Finished Aug 13 06:37:20 PM PDT 24
Peak memory 207644 kb
Host smart-3825eae9-bc2f-457f-8006-9ea2159ab000
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71915120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_host_
handshake.71915120
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/220.usbdev_tx_rx_disruption.1069704272
Short name T183
Test name
Test status
Simulation time 497400543 ps
CPU time 1.57 seconds
Started Aug 13 06:41:41 PM PDT 24
Finished Aug 13 06:41:43 PM PDT 24
Peak memory 207524 kb
Host smart-c5215a84-5aa4-40cb-bf0b-6188f1ab9d4b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069704272 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.usbdev_tx_rx_disruption.1069704272
Directory /workspace/220.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/221.usbdev_tx_rx_disruption.1570829469
Short name T3025
Test name
Test status
Simulation time 564934424 ps
CPU time 1.72 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:48 PM PDT 24
Peak memory 207580 kb
Host smart-c5cee764-060c-4629-ba49-9ca852964f5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570829469 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.usbdev_tx_rx_disruption.1570829469
Directory /workspace/221.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/222.usbdev_tx_rx_disruption.3323511449
Short name T1824
Test name
Test status
Simulation time 553623356 ps
CPU time 1.65 seconds
Started Aug 13 06:41:43 PM PDT 24
Finished Aug 13 06:41:45 PM PDT 24
Peak memory 207572 kb
Host smart-74f6da48-6086-4867-8edc-ce5cdc7cfa13
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323511449 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.usbdev_tx_rx_disruption.3323511449
Directory /workspace/222.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/223.usbdev_tx_rx_disruption.3659587044
Short name T81
Test name
Test status
Simulation time 444601916 ps
CPU time 1.49 seconds
Started Aug 13 06:41:49 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207600 kb
Host smart-33fa33e2-6e2b-44b6-b81c-e9b5ce2eabff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659587044 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.usbdev_tx_rx_disruption.3659587044
Directory /workspace/223.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/224.usbdev_tx_rx_disruption.2340785414
Short name T688
Test name
Test status
Simulation time 501535742 ps
CPU time 1.54 seconds
Started Aug 13 06:42:29 PM PDT 24
Finished Aug 13 06:42:31 PM PDT 24
Peak memory 207616 kb
Host smart-657a8884-f314-492a-927d-14fac7d82f43
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340785414 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.usbdev_tx_rx_disruption.2340785414
Directory /workspace/224.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/225.usbdev_tx_rx_disruption.3161823330
Short name T239
Test name
Test status
Simulation time 482140773 ps
CPU time 1.58 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:46 PM PDT 24
Peak memory 207540 kb
Host smart-30901276-b706-4ae5-96ad-3ee4fa28d4ee
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161823330 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.usbdev_tx_rx_disruption.3161823330
Directory /workspace/225.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/226.usbdev_tx_rx_disruption.3454955718
Short name T2386
Test name
Test status
Simulation time 420061029 ps
CPU time 1.38 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:52 PM PDT 24
Peak memory 207524 kb
Host smart-953f642f-dd39-4907-93aa-dfc5e71c3c47
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454955718 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.usbdev_tx_rx_disruption.3454955718
Directory /workspace/226.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/227.usbdev_tx_rx_disruption.430599275
Short name T2587
Test name
Test status
Simulation time 575121342 ps
CPU time 1.54 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207524 kb
Host smart-5371ddba-e9c1-40d8-9a33-615a906b1283
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430599275 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 227.usbdev_tx_rx_disruption.430599275
Directory /workspace/227.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/228.usbdev_tx_rx_disruption.3386446884
Short name T2067
Test name
Test status
Simulation time 568592597 ps
CPU time 1.78 seconds
Started Aug 13 06:41:42 PM PDT 24
Finished Aug 13 06:41:44 PM PDT 24
Peak memory 207504 kb
Host smart-92695848-aa3b-4fd5-9413-eea6e36cb809
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386446884 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.usbdev_tx_rx_disruption.3386446884
Directory /workspace/228.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/229.usbdev_tx_rx_disruption.3365289147
Short name T36
Test name
Test status
Simulation time 496090714 ps
CPU time 1.47 seconds
Started Aug 13 06:42:06 PM PDT 24
Finished Aug 13 06:42:07 PM PDT 24
Peak memory 207560 kb
Host smart-140b780f-bd8f-45a4-979e-1bac749bd9b6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365289147 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.usbdev_tx_rx_disruption.3365289147
Directory /workspace/229.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2596713149
Short name T2259
Test name
Test status
Simulation time 58690132 ps
CPU time 0.7 seconds
Started Aug 13 06:37:19 PM PDT 24
Finished Aug 13 06:37:19 PM PDT 24
Peak memory 207460 kb
Host smart-cac3a56b-62d7-4056-8cf9-63602e3e91d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2596713149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2596713149
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.162434423
Short name T2896
Test name
Test status
Simulation time 6290408961 ps
CPU time 9.27 seconds
Started Aug 13 06:37:03 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 216004 kb
Host smart-907f5137-dc7b-417e-9178-13d164b71b22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162434423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_ao
n_wake_disconnect.162434423
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.217876077
Short name T3
Test name
Test status
Simulation time 14687032267 ps
CPU time 18.68 seconds
Started Aug 13 06:37:04 PM PDT 24
Finished Aug 13 06:37:23 PM PDT 24
Peak memory 215944 kb
Host smart-62873f22-79c0-4277-a52d-bb39e5f17505
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=217876077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.217876077
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.2816282558
Short name T3129
Test name
Test status
Simulation time 25177516262 ps
CPU time 29.26 seconds
Started Aug 13 06:37:03 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 216000 kb
Host smart-d11e67fa-201f-48ec-9e44-c445893e1f25
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816282558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.2816282558
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1317549008
Short name T786
Test name
Test status
Simulation time 160469500 ps
CPU time 0.89 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:09 PM PDT 24
Peak memory 207492 kb
Host smart-34c7edf7-9796-46d6-95c9-65dd9a634ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13175
49008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1317549008
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3630774109
Short name T866
Test name
Test status
Simulation time 160139976 ps
CPU time 0.95 seconds
Started Aug 13 06:37:13 PM PDT 24
Finished Aug 13 06:37:14 PM PDT 24
Peak memory 207620 kb
Host smart-2fffb26f-a88d-400d-9c54-ec8890ca77a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36307
74109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3630774109
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.589798760
Short name T3159
Test name
Test status
Simulation time 243186721 ps
CPU time 1.15 seconds
Started Aug 13 06:37:06 PM PDT 24
Finished Aug 13 06:37:07 PM PDT 24
Peak memory 207616 kb
Host smart-2db523d5-4599-4994-8ad9-3eefb86719bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58979
8760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.589798760
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_device_address.140684879
Short name T2211
Test name
Test status
Simulation time 40651244640 ps
CPU time 62.1 seconds
Started Aug 13 06:37:09 PM PDT 24
Finished Aug 13 06:38:12 PM PDT 24
Peak memory 207792 kb
Host smart-162b057b-05cb-4a07-a9da-ded1a06e29c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14068
4879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.140684879
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.1352259221
Short name T1049
Test name
Test status
Simulation time 2886131774 ps
CPU time 19.3 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207840 kb
Host smart-652496dd-55f5-49b3-b146-c9eab874f813
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352259221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.1352259221
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.1232117908
Short name T1108
Test name
Test status
Simulation time 669327539 ps
CPU time 1.93 seconds
Started Aug 13 06:37:05 PM PDT 24
Finished Aug 13 06:37:07 PM PDT 24
Peak memory 207504 kb
Host smart-e4574d86-f3fa-40e7-b7d0-6ffae65b1c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
17908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.1232117908
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1954500082
Short name T996
Test name
Test status
Simulation time 142841272 ps
CPU time 0.78 seconds
Started Aug 13 06:36:58 PM PDT 24
Finished Aug 13 06:36:59 PM PDT 24
Peak memory 207540 kb
Host smart-c62214b8-a8cd-4800-ae97-982859e8633b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19545
00082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1954500082
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2069215834
Short name T1239
Test name
Test status
Simulation time 66298377 ps
CPU time 0.77 seconds
Started Aug 13 06:37:02 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207416 kb
Host smart-9280929b-dc6a-458d-a39b-9cb4d9e19e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20692
15834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2069215834
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2819367721
Short name T2631
Test name
Test status
Simulation time 836490148 ps
CPU time 2.45 seconds
Started Aug 13 06:37:00 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 207712 kb
Host smart-d52d01ea-659d-45ad-b625-13a870ef3212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28193
67721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2819367721
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_types.2901846117
Short name T492
Test name
Test status
Simulation time 375524176 ps
CPU time 1.35 seconds
Started Aug 13 06:36:58 PM PDT 24
Finished Aug 13 06:37:00 PM PDT 24
Peak memory 207548 kb
Host smart-f922035c-2c42-459b-8053-6e3280eaadfd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2901846117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.2901846117
Directory /workspace/23.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3510608706
Short name T1028
Test name
Test status
Simulation time 360847443 ps
CPU time 2.22 seconds
Started Aug 13 06:37:06 PM PDT 24
Finished Aug 13 06:37:08 PM PDT 24
Peak memory 207724 kb
Host smart-23bc87f5-253f-42c0-8d03-68b938fdb20a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35106
08706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3510608706
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3620375271
Short name T2262
Test name
Test status
Simulation time 218150468 ps
CPU time 1.16 seconds
Started Aug 13 06:37:02 PM PDT 24
Finished Aug 13 06:37:03 PM PDT 24
Peak memory 215940 kb
Host smart-6acdf421-b1b2-427b-8c99-6a2b06e83b80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3620375271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3620375271
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.162524053
Short name T2625
Test name
Test status
Simulation time 147528518 ps
CPU time 0.83 seconds
Started Aug 13 06:37:06 PM PDT 24
Finished Aug 13 06:37:06 PM PDT 24
Peak memory 207512 kb
Host smart-7198d441-3a20-48b7-89ed-cb945948d7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
4053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.162524053
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1720938824
Short name T2390
Test name
Test status
Simulation time 203352687 ps
CPU time 1 seconds
Started Aug 13 06:37:06 PM PDT 24
Finished Aug 13 06:37:07 PM PDT 24
Peak memory 207444 kb
Host smart-630eedc5-7320-4b19-b3b1-3d4b9507e47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17209
38824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1720938824
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.841537757
Short name T611
Test name
Test status
Simulation time 3376317761 ps
CPU time 34.02 seconds
Started Aug 13 06:37:04 PM PDT 24
Finished Aug 13 06:37:38 PM PDT 24
Peak memory 217716 kb
Host smart-aa0c8629-b70a-48b4-8c5c-2ba8a5a5cbfd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=841537757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.841537757
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.4273560052
Short name T603
Test name
Test status
Simulation time 11551555729 ps
CPU time 80.07 seconds
Started Aug 13 06:37:06 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207820 kb
Host smart-fa64cf17-64be-4913-8280-65a49f689165
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4273560052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.4273560052
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1171594817
Short name T676
Test name
Test status
Simulation time 261377920 ps
CPU time 1.04 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 207596 kb
Host smart-7dba2615-e04d-41df-8875-0c561615809e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11715
94817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1171594817
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.513256839
Short name T1833
Test name
Test status
Simulation time 11297098814 ps
CPU time 15.39 seconds
Started Aug 13 06:36:59 PM PDT 24
Finished Aug 13 06:37:15 PM PDT 24
Peak memory 207644 kb
Host smart-6709a77f-3ac9-4be1-bedf-f80155b2fbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51325
6839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.513256839
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2888992109
Short name T2595
Test name
Test status
Simulation time 9269943534 ps
CPU time 13.46 seconds
Started Aug 13 06:37:07 PM PDT 24
Finished Aug 13 06:37:21 PM PDT 24
Peak memory 207836 kb
Host smart-2fc0e313-7d6b-4b5a-8607-3f61a164fc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28889
92109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2888992109
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.402448744
Short name T1383
Test name
Test status
Simulation time 4597245930 ps
CPU time 138.02 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:39:29 PM PDT 24
Peak memory 218628 kb
Host smart-c78dfa2e-9ec0-456e-a3ce-382d5dd96986
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=402448744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.402448744
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1151468187
Short name T3107
Test name
Test status
Simulation time 2392539221 ps
CPU time 24.5 seconds
Started Aug 13 06:37:05 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 216836 kb
Host smart-c017118e-cf94-4e03-af49-76217d7acd19
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1151468187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1151468187
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3706443831
Short name T1562
Test name
Test status
Simulation time 232888575 ps
CPU time 0.98 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:09 PM PDT 24
Peak memory 207416 kb
Host smart-82d775ec-4f86-4554-a408-b35b54345131
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3706443831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3706443831
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.145392469
Short name T3246
Test name
Test status
Simulation time 209565695 ps
CPU time 1.04 seconds
Started Aug 13 06:37:13 PM PDT 24
Finished Aug 13 06:37:15 PM PDT 24
Peak memory 207620 kb
Host smart-dbf2515b-6d62-46c2-8f4e-e974f3f99b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14539
2469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.145392469
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.491334162
Short name T201
Test name
Test status
Simulation time 2953846116 ps
CPU time 85.27 seconds
Started Aug 13 06:37:14 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 224060 kb
Host smart-0b4a19d2-e0a6-4ef6-bfc2-2ebcf495b206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49133
4162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.491334162
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2114137381
Short name T204
Test name
Test status
Simulation time 1760910994 ps
CPU time 50.64 seconds
Started Aug 13 06:37:12 PM PDT 24
Finished Aug 13 06:38:03 PM PDT 24
Peak memory 217336 kb
Host smart-0a00e7d7-caaf-4b73-8feb-6e4837720080
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2114137381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2114137381
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2273588525
Short name T628
Test name
Test status
Simulation time 187889451 ps
CPU time 0.92 seconds
Started Aug 13 06:37:14 PM PDT 24
Finished Aug 13 06:37:15 PM PDT 24
Peak memory 207516 kb
Host smart-a69aff7a-e395-4282-a36f-bdc933e32cae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2273588525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2273588525
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3516894293
Short name T2884
Test name
Test status
Simulation time 147701399 ps
CPU time 0.81 seconds
Started Aug 13 06:37:05 PM PDT 24
Finished Aug 13 06:37:05 PM PDT 24
Peak memory 207484 kb
Host smart-d3df42dc-d8d7-42a1-82bc-d4c7b5572cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35168
94293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3516894293
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3890272551
Short name T147
Test name
Test status
Simulation time 151048470 ps
CPU time 0.87 seconds
Started Aug 13 06:37:13 PM PDT 24
Finished Aug 13 06:37:14 PM PDT 24
Peak memory 207460 kb
Host smart-b750e13f-bded-4ad7-8485-746b24a9e835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38902
72551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3890272551
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.900517613
Short name T2839
Test name
Test status
Simulation time 196664482 ps
CPU time 0.98 seconds
Started Aug 13 06:37:16 PM PDT 24
Finished Aug 13 06:37:17 PM PDT 24
Peak memory 207528 kb
Host smart-b9833125-b731-4c5c-8d46-ddf50f9ef315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90051
7613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.900517613
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3817480379
Short name T2083
Test name
Test status
Simulation time 227940033 ps
CPU time 0.93 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:09 PM PDT 24
Peak memory 207492 kb
Host smart-c7e98d67-1eca-4f35-9843-a9a077abfe03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38174
80379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3817480379
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1402516355
Short name T1837
Test name
Test status
Simulation time 149174794 ps
CPU time 0.83 seconds
Started Aug 13 06:37:14 PM PDT 24
Finished Aug 13 06:37:15 PM PDT 24
Peak memory 207576 kb
Host smart-b4571102-9c0d-4971-a99d-56548d64068a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14025
16355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1402516355
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2831250945
Short name T1300
Test name
Test status
Simulation time 156215452 ps
CPU time 0.9 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:37:12 PM PDT 24
Peak memory 207452 kb
Host smart-48a96b0a-7284-4ce5-973c-684747cbe4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28312
50945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2831250945
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.666787914
Short name T2531
Test name
Test status
Simulation time 218613748 ps
CPU time 1 seconds
Started Aug 13 06:37:15 PM PDT 24
Finished Aug 13 06:37:16 PM PDT 24
Peak memory 207564 kb
Host smart-4832e4a3-ad10-4176-8554-c1272af225d0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=666787914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.666787914
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3048468979
Short name T1862
Test name
Test status
Simulation time 136167613 ps
CPU time 0.81 seconds
Started Aug 13 06:37:13 PM PDT 24
Finished Aug 13 06:37:14 PM PDT 24
Peak memory 207464 kb
Host smart-7602649c-7f23-4b59-9e0b-2437af9a0b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30484
68979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3048468979
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.4161247767
Short name T25
Test name
Test status
Simulation time 57750162 ps
CPU time 0.7 seconds
Started Aug 13 06:37:14 PM PDT 24
Finished Aug 13 06:37:15 PM PDT 24
Peak memory 207500 kb
Host smart-74aa8372-92c1-4a40-b1fe-6835f00c0df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41612
47767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.4161247767
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2465949220
Short name T1763
Test name
Test status
Simulation time 22231379546 ps
CPU time 60.36 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:38:11 PM PDT 24
Peak memory 215928 kb
Host smart-884d057e-f7ec-4c51-91f2-1a67fbf6965c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24659
49220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2465949220
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3533744371
Short name T2074
Test name
Test status
Simulation time 174441240 ps
CPU time 0.95 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 207516 kb
Host smart-124f834a-32f1-49fd-b440-afdf0910b8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35337
44371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3533744371
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1145740155
Short name T2810
Test name
Test status
Simulation time 200639758 ps
CPU time 0.95 seconds
Started Aug 13 06:37:09 PM PDT 24
Finished Aug 13 06:37:10 PM PDT 24
Peak memory 207432 kb
Host smart-15d78787-ed65-4989-bf21-3fcfd10afff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11457
40155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1145740155
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3601493536
Short name T1075
Test name
Test status
Simulation time 202437997 ps
CPU time 1 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:37:12 PM PDT 24
Peak memory 207504 kb
Host smart-cbe3e65e-b2cc-4f0e-93fe-eaf540283237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36014
93536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3601493536
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2790928277
Short name T1331
Test name
Test status
Simulation time 169139724 ps
CPU time 0.9 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 207444 kb
Host smart-07be39a5-297c-4fc8-b06f-86698122657b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27909
28277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2790928277
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3592440188
Short name T2568
Test name
Test status
Simulation time 248343053 ps
CPU time 1.19 seconds
Started Aug 13 06:37:13 PM PDT 24
Finished Aug 13 06:37:14 PM PDT 24
Peak memory 207448 kb
Host smart-a84f48fa-99c7-419e-a6c1-9a06ef0ff9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35924
40188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3592440188
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_rx_full.3412107933
Short name T2829
Test name
Test status
Simulation time 242782878 ps
CPU time 1.2 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:37:12 PM PDT 24
Peak memory 207636 kb
Host smart-bdd09729-1b46-492d-86ca-99379fae6b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34121
07933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.3412107933
Directory /workspace/23.usbdev_rx_full/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1117730569
Short name T701
Test name
Test status
Simulation time 148810206 ps
CPU time 0.86 seconds
Started Aug 13 06:37:05 PM PDT 24
Finished Aug 13 06:37:06 PM PDT 24
Peak memory 207508 kb
Host smart-dbc6a003-9fc4-4d46-8899-a40533b3b9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11177
30569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1117730569
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1637941317
Short name T2985
Test name
Test status
Simulation time 193923773 ps
CPU time 0.88 seconds
Started Aug 13 06:37:15 PM PDT 24
Finished Aug 13 06:37:16 PM PDT 24
Peak memory 207500 kb
Host smart-93c090f3-8e06-4253-953e-8d82bcedf5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16379
41317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1637941317
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3851969453
Short name T1527
Test name
Test status
Simulation time 219824944 ps
CPU time 1.02 seconds
Started Aug 13 06:37:15 PM PDT 24
Finished Aug 13 06:37:16 PM PDT 24
Peak memory 207416 kb
Host smart-977cbdc8-9bb5-4edf-826f-9b4a9c5b3254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38519
69453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3851969453
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2271399338
Short name T1536
Test name
Test status
Simulation time 163115211 ps
CPU time 0.87 seconds
Started Aug 13 06:37:17 PM PDT 24
Finished Aug 13 06:37:18 PM PDT 24
Peak memory 207496 kb
Host smart-6d0a30b5-c510-4b99-8446-845bb62d26d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22713
99338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2271399338
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.162266890
Short name T3219
Test name
Test status
Simulation time 180786055 ps
CPU time 0.9 seconds
Started Aug 13 06:37:15 PM PDT 24
Finished Aug 13 06:37:16 PM PDT 24
Peak memory 207508 kb
Host smart-1aa06e60-ed4e-441d-8b43-dac31297ceaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16226
6890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.162266890
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.1757692215
Short name T1935
Test name
Test status
Simulation time 383216935 ps
CPU time 1.4 seconds
Started Aug 13 06:37:15 PM PDT 24
Finished Aug 13 06:37:17 PM PDT 24
Peak memory 207572 kb
Host smart-1b26f78d-b340-4f2e-bb1d-e838c149891a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576
92215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.1757692215
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.951143371
Short name T529
Test name
Test status
Simulation time 1841345832 ps
CPU time 18.75 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:27 PM PDT 24
Peak memory 224108 kb
Host smart-d1521366-4982-4b31-b1d9-e44b151c4388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95114
3371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.951143371
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.544606915
Short name T1399
Test name
Test status
Simulation time 3837511752 ps
CPU time 33.42 seconds
Started Aug 13 06:37:03 PM PDT 24
Finished Aug 13 06:37:36 PM PDT 24
Peak memory 207776 kb
Host smart-637133ab-aaa0-49b2-a2e0-713fa41949af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544606915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_host
_handshake.544606915
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_tx_rx_disruption.3626446785
Short name T1445
Test name
Test status
Simulation time 514051422 ps
CPU time 1.52 seconds
Started Aug 13 06:37:14 PM PDT 24
Finished Aug 13 06:37:16 PM PDT 24
Peak memory 207616 kb
Host smart-99a148dc-724b-4443-9add-077d2a294735
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626446785 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.usbdev_tx_rx_disruption.3626446785
Directory /workspace/23.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/230.usbdev_tx_rx_disruption.1099529313
Short name T2934
Test name
Test status
Simulation time 469328432 ps
CPU time 1.68 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207628 kb
Host smart-17291dd6-09f3-4342-b5b5-be1d6eafbc77
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099529313 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.usbdev_tx_rx_disruption.1099529313
Directory /workspace/230.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/231.usbdev_tx_rx_disruption.1413976814
Short name T810
Test name
Test status
Simulation time 584589364 ps
CPU time 1.58 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207596 kb
Host smart-f27daf1b-cb8f-454b-8f75-26bd04e66d6d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413976814 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.usbdev_tx_rx_disruption.1413976814
Directory /workspace/231.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/232.usbdev_tx_rx_disruption.70915851
Short name T261
Test name
Test status
Simulation time 646947258 ps
CPU time 1.61 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207600 kb
Host smart-ae3a48f9-ae0d-4277-8dde-4facec87b1f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70915851 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 232.usbdev_tx_rx_disruption.70915851
Directory /workspace/232.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/233.usbdev_tx_rx_disruption.390954538
Short name T3414
Test name
Test status
Simulation time 604957070 ps
CPU time 1.58 seconds
Started Aug 13 06:41:58 PM PDT 24
Finished Aug 13 06:42:02 PM PDT 24
Peak memory 207596 kb
Host smart-a6c8eef7-4ef3-4b39-a513-dc31df23e10d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390954538 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 233.usbdev_tx_rx_disruption.390954538
Directory /workspace/233.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/234.usbdev_tx_rx_disruption.3197359453
Short name T1074
Test name
Test status
Simulation time 513989288 ps
CPU time 1.72 seconds
Started Aug 13 06:41:49 PM PDT 24
Finished Aug 13 06:41:50 PM PDT 24
Peak memory 207588 kb
Host smart-c1e8df3a-ca0f-47b7-affa-afb00311f00c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197359453 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.usbdev_tx_rx_disruption.3197359453
Directory /workspace/234.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/235.usbdev_tx_rx_disruption.3872499374
Short name T3300
Test name
Test status
Simulation time 575126941 ps
CPU time 1.66 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207584 kb
Host smart-99c06058-a750-4537-bf6e-6229f61f648c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872499374 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.usbdev_tx_rx_disruption.3872499374
Directory /workspace/235.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/236.usbdev_tx_rx_disruption.1207706671
Short name T2448
Test name
Test status
Simulation time 509122627 ps
CPU time 1.53 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207616 kb
Host smart-f4c4e676-19dd-4f09-b9d1-cdd8a8c7b0c1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207706671 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.usbdev_tx_rx_disruption.1207706671
Directory /workspace/236.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/237.usbdev_tx_rx_disruption.3336051371
Short name T719
Test name
Test status
Simulation time 611567966 ps
CPU time 1.52 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207612 kb
Host smart-5e2746d5-009f-4e7a-8f78-f4d0c706161c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336051371 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.usbdev_tx_rx_disruption.3336051371
Directory /workspace/237.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/238.usbdev_tx_rx_disruption.775349569
Short name T1325
Test name
Test status
Simulation time 586903449 ps
CPU time 1.61 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207516 kb
Host smart-9bbe70ff-80c2-4145-ba37-057432bb2f88
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775349569 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 238.usbdev_tx_rx_disruption.775349569
Directory /workspace/238.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/239.usbdev_tx_rx_disruption.3771512389
Short name T2648
Test name
Test status
Simulation time 596631430 ps
CPU time 1.69 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207588 kb
Host smart-8ef39a2e-6ca0-4493-acce-feb19ff0a686
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771512389 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.usbdev_tx_rx_disruption.3771512389
Directory /workspace/239.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.1805797445
Short name T2734
Test name
Test status
Simulation time 52226063 ps
CPU time 0.67 seconds
Started Aug 13 06:37:18 PM PDT 24
Finished Aug 13 06:37:18 PM PDT 24
Peak memory 207492 kb
Host smart-8de72591-0548-4571-b502-cf856ad2567e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1805797445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.1805797445
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3272825015
Short name T2706
Test name
Test status
Simulation time 5531377901 ps
CPU time 7.77 seconds
Started Aug 13 06:37:15 PM PDT 24
Finished Aug 13 06:37:23 PM PDT 24
Peak memory 215940 kb
Host smart-ecb78fd5-d024-427e-b478-54b224fbafa0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272825015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.3272825015
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.4272031055
Short name T3277
Test name
Test status
Simulation time 21030733805 ps
CPU time 27.4 seconds
Started Aug 13 06:37:09 PM PDT 24
Finished Aug 13 06:37:36 PM PDT 24
Peak memory 207808 kb
Host smart-9c68526c-e5d9-4141-8a60-3f550fe50e44
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272031055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.4272031055
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1040970892
Short name T1893
Test name
Test status
Simulation time 24110781040 ps
CPU time 30.43 seconds
Started Aug 13 06:37:13 PM PDT 24
Finished Aug 13 06:37:43 PM PDT 24
Peak memory 215908 kb
Host smart-10e7eb67-3640-4b0e-b0d1-7937370a8931
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040970892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.1040970892
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3858642802
Short name T1361
Test name
Test status
Simulation time 151076248 ps
CPU time 0.83 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 207384 kb
Host smart-321624ff-abf1-44b4-b495-ff51786d2120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38586
42802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3858642802
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3016306013
Short name T2286
Test name
Test status
Simulation time 166341790 ps
CPU time 0.92 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:09 PM PDT 24
Peak memory 207528 kb
Host smart-98d49232-b681-431b-8e8a-8c49368abccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30163
06013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3016306013
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1739749857
Short name T730
Test name
Test status
Simulation time 358516566 ps
CPU time 1.38 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 207600 kb
Host smart-7cf8e3c7-61e4-4a4b-b3e4-bf7ac4cf9287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17397
49857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1739749857
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1470405822
Short name T3596
Test name
Test status
Simulation time 501686060 ps
CPU time 1.73 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:10 PM PDT 24
Peak memory 207372 kb
Host smart-fe0c4b35-cb2e-4dd0-9a05-8dfc60f96ec6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1470405822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1470405822
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2929428825
Short name T3375
Test name
Test status
Simulation time 50829063811 ps
CPU time 83.3 seconds
Started Aug 13 06:37:16 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 207812 kb
Host smart-f5536a5c-df4e-4a51-a3fe-679e24b9651e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29294
28825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2929428825
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.2050196088
Short name T1008
Test name
Test status
Simulation time 1063853124 ps
CPU time 8.93 seconds
Started Aug 13 06:37:21 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207744 kb
Host smart-37f64a27-a456-47e8-9116-40687d03f6ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050196088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.2050196088
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3695682564
Short name T3104
Test name
Test status
Simulation time 766128118 ps
CPU time 1.81 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:10 PM PDT 24
Peak memory 207504 kb
Host smart-65f133f5-e931-4500-9fa9-df0a838d3bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36956
82564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3695682564
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3963942017
Short name T655
Test name
Test status
Simulation time 146467844 ps
CPU time 0.86 seconds
Started Aug 13 06:37:12 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 207540 kb
Host smart-e1b46402-1fdb-445d-9bb9-65d358d9be7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39639
42017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3963942017
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.206681825
Short name T2914
Test name
Test status
Simulation time 51740485 ps
CPU time 0.72 seconds
Started Aug 13 06:37:07 PM PDT 24
Finished Aug 13 06:37:08 PM PDT 24
Peak memory 207388 kb
Host smart-24d4e063-ebf5-4fb2-9f59-88e1f213d63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20668
1825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.206681825
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.641725475
Short name T1457
Test name
Test status
Simulation time 982346688 ps
CPU time 2.5 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 207796 kb
Host smart-d54ed128-082b-45de-87ee-09bbf03717e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64172
5475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.641725475
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_types.2810514661
Short name T482
Test name
Test status
Simulation time 201765682 ps
CPU time 1.07 seconds
Started Aug 13 06:37:13 PM PDT 24
Finished Aug 13 06:37:14 PM PDT 24
Peak memory 207508 kb
Host smart-10abf2d0-bb53-4cdc-b264-81a91fbdfca4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2810514661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.2810514661
Directory /workspace/24.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.4031135686
Short name T2764
Test name
Test status
Simulation time 193420302 ps
CPU time 2.13 seconds
Started Aug 13 06:37:22 PM PDT 24
Finished Aug 13 06:37:25 PM PDT 24
Peak memory 207652 kb
Host smart-f7073d15-7db3-41a2-8c5c-05dfa7df3d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40311
35686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.4031135686
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1855945512
Short name T3498
Test name
Test status
Simulation time 180961794 ps
CPU time 0.93 seconds
Started Aug 13 06:37:12 PM PDT 24
Finished Aug 13 06:37:13 PM PDT 24
Peak memory 207492 kb
Host smart-52484ade-a854-45d0-a6ae-6c10439873d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1855945512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1855945512
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3173870823
Short name T2304
Test name
Test status
Simulation time 140363944 ps
CPU time 0.84 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 207508 kb
Host smart-efd61941-7fc6-4037-8784-91b985e19b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31738
70823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3173870823
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1357953483
Short name T2235
Test name
Test status
Simulation time 253814137 ps
CPU time 0.96 seconds
Started Aug 13 06:37:10 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 207516 kb
Host smart-317182fb-4dc0-413b-8bca-12ae03885d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13579
53483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1357953483
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1748787165
Short name T2752
Test name
Test status
Simulation time 3610133289 ps
CPU time 104.38 seconds
Started Aug 13 06:37:16 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 216044 kb
Host smart-e35779e2-2d4e-40e2-9779-2914786a6bc9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1748787165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1748787165
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.263024235
Short name T1123
Test name
Test status
Simulation time 7954599184 ps
CPU time 49.16 seconds
Started Aug 13 06:37:08 PM PDT 24
Finished Aug 13 06:37:58 PM PDT 24
Peak memory 207812 kb
Host smart-efd774fb-e056-4c0d-8b90-946c9d808afb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=263024235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.263024235
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.389333057
Short name T3253
Test name
Test status
Simulation time 260419365 ps
CPU time 1.11 seconds
Started Aug 13 06:37:14 PM PDT 24
Finished Aug 13 06:37:15 PM PDT 24
Peak memory 207540 kb
Host smart-3461c40d-c35e-42b1-83f0-e525ddf10aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38933
3057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.389333057
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1192422128
Short name T709
Test name
Test status
Simulation time 23061088004 ps
CPU time 35.38 seconds
Started Aug 13 06:37:11 PM PDT 24
Finished Aug 13 06:37:47 PM PDT 24
Peak memory 216060 kb
Host smart-dbb25f99-426b-4c21-a693-139f44c8e393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
22128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1192422128
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1623337655
Short name T2063
Test name
Test status
Simulation time 8447375487 ps
CPU time 11.26 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:42 PM PDT 24
Peak memory 207868 kb
Host smart-862a655d-46d2-4532-8b90-49e8ae719b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16233
37655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1623337655
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.3382982741
Short name T1706
Test name
Test status
Simulation time 3225396090 ps
CPU time 31.14 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 224180 kb
Host smart-b44aec3f-bb74-4072-9b7b-fbb4f0e30c44
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3382982741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.3382982741
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.2231795469
Short name T3541
Test name
Test status
Simulation time 2330944881 ps
CPU time 23.04 seconds
Started Aug 13 06:37:17 PM PDT 24
Finished Aug 13 06:37:40 PM PDT 24
Peak memory 215940 kb
Host smart-407b6ddd-b6a6-4c3a-bbe8-dd288d56cb3d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2231795469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2231795469
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.2331020934
Short name T3602
Test name
Test status
Simulation time 231891124 ps
CPU time 0.99 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:35 PM PDT 24
Peak memory 207416 kb
Host smart-288dcbe5-6c8f-48c0-8668-ff162e0d09b7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2331020934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.2331020934
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.605989471
Short name T3601
Test name
Test status
Simulation time 273715095 ps
CPU time 1.05 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207496 kb
Host smart-f99658aa-87c3-41f4-b7d2-0366e42ddfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60598
9471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.605989471
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.1949139838
Short name T816
Test name
Test status
Simulation time 1438578747 ps
CPU time 10.96 seconds
Started Aug 13 06:37:34 PM PDT 24
Finished Aug 13 06:37:45 PM PDT 24
Peak memory 217724 kb
Host smart-e9b8eaa3-bf39-4161-9c6d-e9585c6d69ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19491
39838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.1949139838
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.2236313144
Short name T1512
Test name
Test status
Simulation time 2704703887 ps
CPU time 19.95 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:37:53 PM PDT 24
Peak memory 217684 kb
Host smart-5cda2fe7-fc18-4ade-bb47-e56e619cab5f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2236313144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.2236313144
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3083397357
Short name T2372
Test name
Test status
Simulation time 176328501 ps
CPU time 0.88 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207432 kb
Host smart-71ffb3de-0c6a-4300-b0f6-cd6dfcd528a3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3083397357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3083397357
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3471834661
Short name T827
Test name
Test status
Simulation time 148107419 ps
CPU time 0.86 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207456 kb
Host smart-820e068d-71a9-4b4e-b003-25ce357c1d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34718
34661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3471834661
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.266352153
Short name T215
Test name
Test status
Simulation time 151009193 ps
CPU time 0.86 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:32 PM PDT 24
Peak memory 207524 kb
Host smart-25d78e5b-8d8b-4b4e-87f4-df8bf6bd2a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26635
2153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.266352153
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3822780675
Short name T990
Test name
Test status
Simulation time 173802730 ps
CPU time 0.88 seconds
Started Aug 13 06:37:18 PM PDT 24
Finished Aug 13 06:37:19 PM PDT 24
Peak memory 207448 kb
Host smart-c236342e-6b74-4db3-ac1d-0a4e0f428cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
80675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3822780675
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2106487922
Short name T3215
Test name
Test status
Simulation time 167974496 ps
CPU time 0.86 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207564 kb
Host smart-ff00ffc0-033d-4cab-a5fd-59ffac8b674e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21064
87922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2106487922
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3689590742
Short name T966
Test name
Test status
Simulation time 152854639 ps
CPU time 0.84 seconds
Started Aug 13 06:37:34 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 207604 kb
Host smart-ff047214-f637-46a4-861f-a4f17107db94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36895
90742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3689590742
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.898117934
Short name T1058
Test name
Test status
Simulation time 214466647 ps
CPU time 0.99 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207596 kb
Host smart-9146fbad-bf8c-468e-b4ba-dba6e742cb4f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=898117934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.898117934
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3917358429
Short name T229
Test name
Test status
Simulation time 132848268 ps
CPU time 0.8 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207356 kb
Host smart-14d5c9d6-e8c7-4259-af99-4e1fc72f9e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39173
58429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3917358429
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.4277362769
Short name T1120
Test name
Test status
Simulation time 228113310 ps
CPU time 0.95 seconds
Started Aug 13 06:37:25 PM PDT 24
Finished Aug 13 06:37:26 PM PDT 24
Peak memory 207512 kb
Host smart-e3ec8e26-6f14-4ceb-9709-168d7bd908e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42773
62769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.4277362769
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3528009151
Short name T1890
Test name
Test status
Simulation time 249996400 ps
CPU time 1.1 seconds
Started Aug 13 06:37:35 PM PDT 24
Finished Aug 13 06:37:36 PM PDT 24
Peak memory 207456 kb
Host smart-0eb88f3d-cccb-4dd2-bda1-09e2ffa012d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280
09151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3528009151
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.767220593
Short name T27
Test name
Test status
Simulation time 223621459 ps
CPU time 0.95 seconds
Started Aug 13 06:37:22 PM PDT 24
Finished Aug 13 06:37:23 PM PDT 24
Peak memory 207532 kb
Host smart-9f09cc11-3825-4ffd-8591-76bd3be7aa3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76722
0593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.767220593
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3391682451
Short name T1660
Test name
Test status
Simulation time 189817341 ps
CPU time 0.92 seconds
Started Aug 13 06:37:21 PM PDT 24
Finished Aug 13 06:37:22 PM PDT 24
Peak memory 207512 kb
Host smart-6a6078a4-7384-4678-88f7-4e7282b448e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33916
82451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3391682451
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.731045362
Short name T67
Test name
Test status
Simulation time 187401673 ps
CPU time 0.89 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207524 kb
Host smart-7cd79431-d6e6-4599-9050-e71111d0b51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73104
5362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.731045362
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_rx_full.2809363137
Short name T2385
Test name
Test status
Simulation time 322391970 ps
CPU time 1.2 seconds
Started Aug 13 06:37:46 PM PDT 24
Finished Aug 13 06:37:47 PM PDT 24
Peak memory 207512 kb
Host smart-f79abe93-d4e8-4b1d-a392-8822e0d672ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28093
63137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.2809363137
Directory /workspace/24.usbdev_rx_full/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.17217106
Short name T2605
Test name
Test status
Simulation time 149806660 ps
CPU time 0.85 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207496 kb
Host smart-7490d69a-6f78-4f25-bf63-b7a057b41d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17217
106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.17217106
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2277941890
Short name T2124
Test name
Test status
Simulation time 158237966 ps
CPU time 0.87 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207396 kb
Host smart-d1b86e43-0291-4ae2-b0d7-577d4953d8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22779
41890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2277941890
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.400661055
Short name T3038
Test name
Test status
Simulation time 231382585 ps
CPU time 1.01 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207472 kb
Host smart-11e0072f-3662-44cd-b888-54fe2a8e10fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40066
1055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.400661055
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3047726866
Short name T1895
Test name
Test status
Simulation time 1909161017 ps
CPU time 17.66 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:47 PM PDT 24
Peak memory 217056 kb
Host smart-f068faad-00c6-4790-986c-7727b0a24578
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3047726866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3047726866
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3238975279
Short name T1134
Test name
Test status
Simulation time 170150058 ps
CPU time 0.85 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207540 kb
Host smart-426894ec-f5be-4c03-a1d1-9454254cca68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32389
75279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3238975279
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2345380598
Short name T2110
Test name
Test status
Simulation time 182045924 ps
CPU time 0.95 seconds
Started Aug 13 06:37:26 PM PDT 24
Finished Aug 13 06:37:27 PM PDT 24
Peak memory 207468 kb
Host smart-3e94db38-1bab-4e7a-8773-309b51b986ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23453
80598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2345380598
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1185053928
Short name T1851
Test name
Test status
Simulation time 972492368 ps
CPU time 2.6 seconds
Started Aug 13 06:37:25 PM PDT 24
Finished Aug 13 06:37:27 PM PDT 24
Peak memory 207816 kb
Host smart-8782aca2-2984-493c-8c8f-b693715befe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11850
53928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1185053928
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1614626164
Short name T1388
Test name
Test status
Simulation time 2511326323 ps
CPU time 19.12 seconds
Started Aug 13 06:37:34 PM PDT 24
Finished Aug 13 06:37:53 PM PDT 24
Peak memory 217776 kb
Host smart-e6728814-8627-4ce3-be22-89f52fa141eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16146
26164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1614626164
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.1243168855
Short name T948
Test name
Test status
Simulation time 3824179152 ps
CPU time 32.81 seconds
Started Aug 13 06:37:15 PM PDT 24
Finished Aug 13 06:37:48 PM PDT 24
Peak memory 207788 kb
Host smart-6312eb48-06de-40b2-a165-03b3f38c456b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243168855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.1243168855
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_tx_rx_disruption.4122616598
Short name T2924
Test name
Test status
Simulation time 589422887 ps
CPU time 1.79 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207552 kb
Host smart-c8558f1d-4c5c-4e6a-8dfe-f3c0017f4a20
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122616598 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.usbdev_tx_rx_disruption.4122616598
Directory /workspace/24.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/240.usbdev_tx_rx_disruption.1063899067
Short name T3039
Test name
Test status
Simulation time 518034613 ps
CPU time 1.56 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207496 kb
Host smart-7a0ba417-6710-4651-81e7-a4e92484f9ca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063899067 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.usbdev_tx_rx_disruption.1063899067
Directory /workspace/240.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/241.usbdev_tx_rx_disruption.2349684836
Short name T187
Test name
Test status
Simulation time 548224558 ps
CPU time 1.67 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207588 kb
Host smart-162e5928-0a21-4935-a436-267fc10258f5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349684836 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.usbdev_tx_rx_disruption.2349684836
Directory /workspace/241.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/242.usbdev_tx_rx_disruption.2204701318
Short name T2449
Test name
Test status
Simulation time 477584360 ps
CPU time 1.56 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207560 kb
Host smart-aee08cc0-2a44-47e2-9891-4c23a640d358
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204701318 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.usbdev_tx_rx_disruption.2204701318
Directory /workspace/242.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/243.usbdev_tx_rx_disruption.4060972240
Short name T3075
Test name
Test status
Simulation time 646393321 ps
CPU time 1.74 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207612 kb
Host smart-7e069bb6-d0b6-4720-9186-9d64dd31462e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060972240 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.usbdev_tx_rx_disruption.4060972240
Directory /workspace/243.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/244.usbdev_tx_rx_disruption.2267993043
Short name T2760
Test name
Test status
Simulation time 550747886 ps
CPU time 1.66 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207612 kb
Host smart-297acb66-bfa1-45b8-8203-885f076cb983
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267993043 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.usbdev_tx_rx_disruption.2267993043
Directory /workspace/244.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/245.usbdev_tx_rx_disruption.251293360
Short name T3260
Test name
Test status
Simulation time 495155602 ps
CPU time 1.48 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207616 kb
Host smart-48a7ce98-afc5-4ca0-97a7-bf7d749d746d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251293360 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 245.usbdev_tx_rx_disruption.251293360
Directory /workspace/245.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/246.usbdev_tx_rx_disruption.3953082847
Short name T890
Test name
Test status
Simulation time 650056463 ps
CPU time 1.73 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207568 kb
Host smart-7ba8b366-f922-4ea1-acf0-acb31d3d9c43
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953082847 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.usbdev_tx_rx_disruption.3953082847
Directory /workspace/246.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/247.usbdev_tx_rx_disruption.411356116
Short name T1958
Test name
Test status
Simulation time 464624144 ps
CPU time 1.43 seconds
Started Aug 13 06:41:48 PM PDT 24
Finished Aug 13 06:41:50 PM PDT 24
Peak memory 207592 kb
Host smart-45867906-a434-489b-ba1b-c1f2da8fdf78
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411356116 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 247.usbdev_tx_rx_disruption.411356116
Directory /workspace/247.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/248.usbdev_tx_rx_disruption.1685695170
Short name T1113
Test name
Test status
Simulation time 606215994 ps
CPU time 1.81 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207568 kb
Host smart-ccc2e624-3b2b-44ea-b5ee-e9831af81bd8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685695170 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.usbdev_tx_rx_disruption.1685695170
Directory /workspace/248.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/249.usbdev_tx_rx_disruption.4117448908
Short name T3359
Test name
Test status
Simulation time 433124839 ps
CPU time 1.44 seconds
Started Aug 13 06:41:55 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207568 kb
Host smart-1a3467ae-cc7c-4af6-8fc6-f5566d1b5cf1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117448908 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.usbdev_tx_rx_disruption.4117448908
Directory /workspace/249.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2888348915
Short name T225
Test name
Test status
Simulation time 61190581 ps
CPU time 0.68 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207440 kb
Host smart-b2c12834-c543-4ad7-a95e-e43b4633f83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2888348915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2888348915
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1251280509
Short name T11
Test name
Test status
Simulation time 9258038850 ps
CPU time 13.06 seconds
Started Aug 13 06:37:17 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207744 kb
Host smart-90aff960-9952-4bab-8a8d-d5ae8aac409e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251280509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.1251280509
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.902374583
Short name T1000
Test name
Test status
Simulation time 19120476227 ps
CPU time 23.19 seconds
Started Aug 13 06:37:24 PM PDT 24
Finished Aug 13 06:37:48 PM PDT 24
Peak memory 207796 kb
Host smart-2abab0d8-87ff-468d-9be0-451707a002c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=902374583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.902374583
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.4251689245
Short name T2365
Test name
Test status
Simulation time 30029330246 ps
CPU time 36.53 seconds
Started Aug 13 06:37:36 PM PDT 24
Finished Aug 13 06:38:13 PM PDT 24
Peak memory 207840 kb
Host smart-d927ed86-9c5d-4f74-b1cd-922fa68a3538
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251689245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.4251689245
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1626867911
Short name T3101
Test name
Test status
Simulation time 156404140 ps
CPU time 0.96 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207460 kb
Host smart-c450572d-a693-4434-8cd8-1ccbbad1b1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16268
67911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1626867911
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2525467584
Short name T2677
Test name
Test status
Simulation time 148178636 ps
CPU time 0.9 seconds
Started Aug 13 06:37:19 PM PDT 24
Finished Aug 13 06:37:20 PM PDT 24
Peak memory 207496 kb
Host smart-99e7c785-d0ce-46d9-bfa9-335f0abb86e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25254
67584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2525467584
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1496617377
Short name T907
Test name
Test status
Simulation time 526820672 ps
CPU time 1.76 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207620 kb
Host smart-a3ba5265-a587-4632-86d1-b72a8a9b8246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14966
17377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1496617377
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2292751989
Short name T3084
Test name
Test status
Simulation time 1241814942 ps
CPU time 3.12 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:32 PM PDT 24
Peak memory 207720 kb
Host smart-9b682ca7-1ada-4428-bfe1-7b29a5e24f79
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2292751989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2292751989
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.265744257
Short name T517
Test name
Test status
Simulation time 31090999184 ps
CPU time 48.26 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207856 kb
Host smart-2f39b405-806a-47d5-8bc1-cf8e0c430e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26574
4257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.265744257
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.964068591
Short name T1296
Test name
Test status
Simulation time 2544900476 ps
CPU time 18.57 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:50 PM PDT 24
Peak memory 207808 kb
Host smart-0f021769-7fef-415d-b8ed-b0ad0e266220
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964068591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.964068591
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.824149344
Short name T1381
Test name
Test status
Simulation time 652228568 ps
CPU time 1.75 seconds
Started Aug 13 06:37:25 PM PDT 24
Finished Aug 13 06:37:27 PM PDT 24
Peak memory 207440 kb
Host smart-8f5a0750-f0b4-4cef-9e0e-0296a4a7685a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82414
9344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.824149344
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.2130174191
Short name T2443
Test name
Test status
Simulation time 162601702 ps
CPU time 0.85 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207532 kb
Host smart-7580bfb4-0537-4ccb-aba3-77c9d76a63f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21301
74191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.2130174191
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3002185085
Short name T1923
Test name
Test status
Simulation time 46664437 ps
CPU time 0.71 seconds
Started Aug 13 06:37:18 PM PDT 24
Finished Aug 13 06:37:19 PM PDT 24
Peak memory 207452 kb
Host smart-57e10766-981b-47d4-8c32-cd95f1c433dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30021
85085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3002185085
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.785206046
Short name T1272
Test name
Test status
Simulation time 991438185 ps
CPU time 2.36 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207768 kb
Host smart-9bf334fd-8e9e-4642-89d6-45e5300e29bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78520
6046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.785206046
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2878188047
Short name T2236
Test name
Test status
Simulation time 237082530 ps
CPU time 2.65 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:35 PM PDT 24
Peak memory 207616 kb
Host smart-c2113e03-19c3-47fe-9324-a3811371661e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28781
88047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2878188047
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3449508555
Short name T992
Test name
Test status
Simulation time 219250032 ps
CPU time 1.1 seconds
Started Aug 13 06:37:23 PM PDT 24
Finished Aug 13 06:37:24 PM PDT 24
Peak memory 216868 kb
Host smart-bb7b8f15-c062-4dcc-ae06-0a492412a754
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3449508555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3449508555
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3176100504
Short name T2268
Test name
Test status
Simulation time 142846822 ps
CPU time 0.86 seconds
Started Aug 13 06:37:41 PM PDT 24
Finished Aug 13 06:37:42 PM PDT 24
Peak memory 207604 kb
Host smart-296cdb11-5789-4fb0-a234-7acf2ef70599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31761
00504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3176100504
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3774006334
Short name T2070
Test name
Test status
Simulation time 234162808 ps
CPU time 1.05 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207532 kb
Host smart-36fd0a40-3975-445d-a489-c08174a8b28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37740
06334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3774006334
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.2708045174
Short name T2574
Test name
Test status
Simulation time 4024160866 ps
CPU time 118.4 seconds
Started Aug 13 06:37:34 PM PDT 24
Finished Aug 13 06:39:33 PM PDT 24
Peak memory 218324 kb
Host smart-7fd3d099-af12-4ea0-bdfd-dfc367578759
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2708045174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2708045174
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.2089817187
Short name T1589
Test name
Test status
Simulation time 11340777725 ps
CPU time 76.95 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:38:46 PM PDT 24
Peak memory 207688 kb
Host smart-6a0b7c67-1d14-451c-b51c-3f02f9169ceb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2089817187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.2089817187
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2911284813
Short name T863
Test name
Test status
Simulation time 193636164 ps
CPU time 0.91 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207552 kb
Host smart-ab0954f3-a8a5-4ced-a05c-407a71af1500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29112
84813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2911284813
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.136123713
Short name T975
Test name
Test status
Simulation time 26088621243 ps
CPU time 42.74 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:38:15 PM PDT 24
Peak memory 216164 kb
Host smart-b94cac27-139a-462b-a4fd-0dc071b00adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13612
3713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.136123713
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2799037787
Short name T3285
Test name
Test status
Simulation time 11414640409 ps
CPU time 16.02 seconds
Started Aug 13 06:37:36 PM PDT 24
Finished Aug 13 06:37:52 PM PDT 24
Peak memory 207832 kb
Host smart-94bdbad3-46ee-4be7-992b-a9074d39c29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27990
37787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2799037787
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.559973252
Short name T82
Test name
Test status
Simulation time 3787202013 ps
CPU time 30.24 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:59 PM PDT 24
Peak memory 224112 kb
Host smart-a081b14d-fee7-479c-91f9-174655902112
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=559973252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.559973252
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.1864813360
Short name T2989
Test name
Test status
Simulation time 2473091549 ps
CPU time 71.58 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 217656 kb
Host smart-b83bc7ec-7678-4ecc-9d5f-532aef1823c5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1864813360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.1864813360
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1192291969
Short name T3326
Test name
Test status
Simulation time 245136393 ps
CPU time 1 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 207368 kb
Host smart-fa383022-0f35-4407-9f83-5d19c7e4f161
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1192291969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1192291969
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1180768021
Short name T2466
Test name
Test status
Simulation time 225660059 ps
CPU time 0.94 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207536 kb
Host smart-b6839ce5-da4d-496a-8953-62bac33f7504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11807
68021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1180768021
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1241197895
Short name T904
Test name
Test status
Simulation time 1969337444 ps
CPU time 55.73 seconds
Started Aug 13 06:37:22 PM PDT 24
Finished Aug 13 06:38:18 PM PDT 24
Peak memory 217176 kb
Host smart-7b1da8c2-9586-4aa1-8c42-f77032425d66
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1241197895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1241197895
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2565410426
Short name T1103
Test name
Test status
Simulation time 182793168 ps
CPU time 0.9 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 207544 kb
Host smart-6b9ade5d-7d20-4be4-8fb9-8bfe88197d3f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2565410426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2565410426
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.36012540
Short name T1524
Test name
Test status
Simulation time 144986846 ps
CPU time 0.83 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207508 kb
Host smart-6f969d86-e989-4c9f-9c01-8d8dab6ea31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36012
540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.36012540
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3916505472
Short name T763
Test name
Test status
Simulation time 141475283 ps
CPU time 0.84 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207524 kb
Host smart-e8a30fb1-1b15-4c6d-ad0c-f253817e1734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39165
05472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3916505472
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3943227460
Short name T2979
Test name
Test status
Simulation time 156049027 ps
CPU time 0.9 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207504 kb
Host smart-439f890d-3239-418e-878f-940613f29184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39432
27460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3943227460
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1820567114
Short name T2483
Test name
Test status
Simulation time 173607462 ps
CPU time 0.89 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207584 kb
Host smart-adb597e5-da8f-4fb7-8fc3-5833338617b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18205
67114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1820567114
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2091558710
Short name T1913
Test name
Test status
Simulation time 159598526 ps
CPU time 0.84 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207616 kb
Host smart-fedbb4ff-5810-49c9-8ca7-ebd47e7eadf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20915
58710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2091558710
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.1628417069
Short name T3220
Test name
Test status
Simulation time 210519751 ps
CPU time 1.04 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207560 kb
Host smart-2bddc0c8-c417-412b-90e5-1702c99e4536
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1628417069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.1628417069
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3300694897
Short name T2871
Test name
Test status
Simulation time 143264381 ps
CPU time 0.81 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207504 kb
Host smart-3a5a4bba-f60d-41c8-acf7-9fc3922c1803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33006
94897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3300694897
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2863854906
Short name T2970
Test name
Test status
Simulation time 43793253 ps
CPU time 0.71 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207488 kb
Host smart-bb13c9d2-8809-4829-8f73-9716ef20592f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28638
54906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2863854906
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3210082356
Short name T299
Test name
Test status
Simulation time 21820356898 ps
CPU time 54.64 seconds
Started Aug 13 06:37:37 PM PDT 24
Finished Aug 13 06:38:32 PM PDT 24
Peak memory 215964 kb
Host smart-45212c2d-b562-4e9d-9c12-5601c3864e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100
82356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3210082356
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2015469566
Short name T356
Test name
Test status
Simulation time 154669171 ps
CPU time 0.91 seconds
Started Aug 13 06:37:26 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207452 kb
Host smart-1fa9a44f-2b51-4c90-a3cb-9576e75cb457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20154
69566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2015469566
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1410488966
Short name T3619
Test name
Test status
Simulation time 203237112 ps
CPU time 0.92 seconds
Started Aug 13 06:37:34 PM PDT 24
Finished Aug 13 06:37:35 PM PDT 24
Peak memory 207440 kb
Host smart-181a58b0-5a6a-4ed4-bae8-a61332c4ad2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14104
88966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1410488966
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.1051468899
Short name T2837
Test name
Test status
Simulation time 162286352 ps
CPU time 0.87 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 207528 kb
Host smart-107d3583-08f6-4d92-a0a8-faa15f65434e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10514
68899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.1051468899
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.1343660585
Short name T752
Test name
Test status
Simulation time 179573953 ps
CPU time 0.93 seconds
Started Aug 13 06:37:35 PM PDT 24
Finished Aug 13 06:37:36 PM PDT 24
Peak memory 207544 kb
Host smart-2209aea3-1411-45df-aaac-f7cd3ddd1ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13436
60585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.1343660585
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1566498082
Short name T1360
Test name
Test status
Simulation time 146490157 ps
CPU time 0.85 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207500 kb
Host smart-1ac27200-865d-4552-997a-07e820d758d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15664
98082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1566498082
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3468544761
Short name T2415
Test name
Test status
Simulation time 176548009 ps
CPU time 0.86 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207572 kb
Host smart-a947b47b-c4b9-441b-8456-304d5abd53ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34685
44761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3468544761
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2318368409
Short name T2876
Test name
Test status
Simulation time 159507612 ps
CPU time 0.84 seconds
Started Aug 13 06:37:34 PM PDT 24
Finished Aug 13 06:37:35 PM PDT 24
Peak memory 207524 kb
Host smart-0ae98142-55e7-4603-b496-83c7f52cc0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23183
68409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2318368409
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2211750569
Short name T1316
Test name
Test status
Simulation time 227592328 ps
CPU time 1.06 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 207520 kb
Host smart-9b6e5d68-d3d6-4499-9750-6b770f9ffcff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22117
50569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2211750569
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.2769492674
Short name T2783
Test name
Test status
Simulation time 3031106459 ps
CPU time 23.09 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:53 PM PDT 24
Peak memory 217908 kb
Host smart-b6290970-3e7d-4dd8-895a-60a069ad0d97
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2769492674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2769492674
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2441700128
Short name T2090
Test name
Test status
Simulation time 163111589 ps
CPU time 0.92 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207444 kb
Host smart-887fdcb5-e98d-4997-aaac-add1223c0583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24417
00128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2441700128
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.323964921
Short name T683
Test name
Test status
Simulation time 183768119 ps
CPU time 0.96 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207464 kb
Host smart-77398e4c-2495-42c9-8f0c-9176c3e172fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
4921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.323964921
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.3937992372
Short name T903
Test name
Test status
Simulation time 274057861 ps
CPU time 1.16 seconds
Started Aug 13 06:37:39 PM PDT 24
Finished Aug 13 06:37:40 PM PDT 24
Peak memory 207464 kb
Host smart-a4c05a23-9572-499d-a380-5c5c0f5cc0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39379
92372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3937992372
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.340491342
Short name T3160
Test name
Test status
Simulation time 2601675798 ps
CPU time 19.43 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:53 PM PDT 24
Peak memory 217740 kb
Host smart-26a4660f-f993-4317-a958-85920e615b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34049
1342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.340491342
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.1245079688
Short name T2622
Test name
Test status
Simulation time 316418440 ps
CPU time 4.35 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 207668 kb
Host smart-f129c6ad-d0e1-47d7-86c7-57735d9eb9e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245079688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.1245079688
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_tx_rx_disruption.2559226237
Short name T1574
Test name
Test status
Simulation time 450192508 ps
CPU time 1.49 seconds
Started Aug 13 06:37:34 PM PDT 24
Finished Aug 13 06:37:36 PM PDT 24
Peak memory 207716 kb
Host smart-652cedd5-2531-4114-b12e-44419c516c7f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559226237 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.usbdev_tx_rx_disruption.2559226237
Directory /workspace/25.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/250.usbdev_tx_rx_disruption.4114776888
Short name T3622
Test name
Test status
Simulation time 494709891 ps
CPU time 1.51 seconds
Started Aug 13 06:42:21 PM PDT 24
Finished Aug 13 06:42:23 PM PDT 24
Peak memory 207608 kb
Host smart-a2d55dcf-c895-49bf-ab9b-4e0dba60b27d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114776888 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.usbdev_tx_rx_disruption.4114776888
Directory /workspace/250.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/251.usbdev_tx_rx_disruption.3718522888
Short name T1909
Test name
Test status
Simulation time 454302107 ps
CPU time 1.41 seconds
Started Aug 13 06:41:55 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207572 kb
Host smart-678bf036-ef2b-40fe-9c77-ad4b8b8e5c6c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718522888 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.usbdev_tx_rx_disruption.3718522888
Directory /workspace/251.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/252.usbdev_tx_rx_disruption.1452322409
Short name T2877
Test name
Test status
Simulation time 458113914 ps
CPU time 1.47 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207592 kb
Host smart-4312e0e9-fc8a-4405-b2bf-d4bc96414ed2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452322409 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.usbdev_tx_rx_disruption.1452322409
Directory /workspace/252.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/253.usbdev_tx_rx_disruption.875236703
Short name T3155
Test name
Test status
Simulation time 560703118 ps
CPU time 1.56 seconds
Started Aug 13 06:41:58 PM PDT 24
Finished Aug 13 06:42:00 PM PDT 24
Peak memory 207588 kb
Host smart-2bd0886f-77f6-4e5f-bd04-b485a6fc3b5f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875236703 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 253.usbdev_tx_rx_disruption.875236703
Directory /workspace/253.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/254.usbdev_tx_rx_disruption.1162900324
Short name T2323
Test name
Test status
Simulation time 477306659 ps
CPU time 1.46 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207612 kb
Host smart-b84aa9a1-ced5-4713-9ea7-33c08ee1f09a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162900324 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.usbdev_tx_rx_disruption.1162900324
Directory /workspace/254.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/255.usbdev_tx_rx_disruption.3295659784
Short name T2464
Test name
Test status
Simulation time 547243875 ps
CPU time 1.7 seconds
Started Aug 13 06:42:35 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 207584 kb
Host smart-ad9e109e-4e97-48d9-a163-61bb64647817
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295659784 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.usbdev_tx_rx_disruption.3295659784
Directory /workspace/255.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/256.usbdev_tx_rx_disruption.1501014616
Short name T951
Test name
Test status
Simulation time 591942335 ps
CPU time 1.6 seconds
Started Aug 13 06:41:49 PM PDT 24
Finished Aug 13 06:41:51 PM PDT 24
Peak memory 207452 kb
Host smart-d4be102d-3210-4231-806b-6743571028f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501014616 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.usbdev_tx_rx_disruption.1501014616
Directory /workspace/256.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/257.usbdev_tx_rx_disruption.1943755325
Short name T2993
Test name
Test status
Simulation time 489222116 ps
CPU time 1.52 seconds
Started Aug 13 06:41:46 PM PDT 24
Finished Aug 13 06:41:48 PM PDT 24
Peak memory 207580 kb
Host smart-28bd4fd2-f270-4ced-8465-fc03062d9659
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943755325 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.usbdev_tx_rx_disruption.1943755325
Directory /workspace/257.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/258.usbdev_tx_rx_disruption.2916202497
Short name T638
Test name
Test status
Simulation time 545350569 ps
CPU time 1.65 seconds
Started Aug 13 06:41:58 PM PDT 24
Finished Aug 13 06:41:59 PM PDT 24
Peak memory 207472 kb
Host smart-91db5a46-8881-429c-9be1-9c91e60798f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916202497 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.usbdev_tx_rx_disruption.2916202497
Directory /workspace/258.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/259.usbdev_tx_rx_disruption.331994280
Short name T3064
Test name
Test status
Simulation time 466682470 ps
CPU time 1.45 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207580 kb
Host smart-bd2bc6c1-63a3-4399-9dde-d12d7423d45d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331994280 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 259.usbdev_tx_rx_disruption.331994280
Directory /workspace/259.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.1623201661
Short name T1539
Test name
Test status
Simulation time 33136586 ps
CPU time 0.67 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207452 kb
Host smart-9a7136f1-b825-4d97-8e1b-b4ec5e54fd4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1623201661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.1623201661
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1935098035
Short name T2200
Test name
Test status
Simulation time 5890456246 ps
CPU time 8.38 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:41 PM PDT 24
Peak memory 216020 kb
Host smart-a9e5946f-bf21-4ae2-b921-cad282493d87
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935098035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.1935098035
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.1741589974
Short name T1124
Test name
Test status
Simulation time 14131093462 ps
CPU time 18.27 seconds
Started Aug 13 06:37:38 PM PDT 24
Finished Aug 13 06:37:56 PM PDT 24
Peak memory 216036 kb
Host smart-26e2b2a8-ca05-4cac-85e9-6d45d85a37d6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741589974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.1741589974
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3039451562
Short name T643
Test name
Test status
Simulation time 24114519315 ps
CPU time 29.38 seconds
Started Aug 13 06:37:38 PM PDT 24
Finished Aug 13 06:38:07 PM PDT 24
Peak memory 215992 kb
Host smart-37b7657c-95e4-4e9f-8bcb-389a99398c54
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039451562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.3039451562
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3197356112
Short name T2715
Test name
Test status
Simulation time 179761316 ps
CPU time 0.93 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 207424 kb
Host smart-5a8efad2-4776-40f9-bead-f6acc2b64059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31973
56112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3197356112
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2483315242
Short name T1650
Test name
Test status
Simulation time 151331747 ps
CPU time 0.86 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207600 kb
Host smart-6b1c0bf2-594e-42bc-9150-e332248d756f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24833
15242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2483315242
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.152705883
Short name T1831
Test name
Test status
Simulation time 521788833 ps
CPU time 1.8 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207524 kb
Host smart-ed0b2791-ca45-49c3-b20c-b9e0acbfdd0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15270
5883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.152705883
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.228310421
Short name T337
Test name
Test status
Simulation time 1260654122 ps
CPU time 3.23 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 207844 kb
Host smart-53007253-a6e1-4e20-b248-5071442f4012
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=228310421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.228310421
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.3913207505
Short name T3491
Test name
Test status
Simulation time 5650478486 ps
CPU time 37.12 seconds
Started Aug 13 06:37:26 PM PDT 24
Finished Aug 13 06:38:03 PM PDT 24
Peak memory 207788 kb
Host smart-3c8d266a-60af-483e-925f-5a643972efc4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913207505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.3913207505
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.2336913791
Short name T458
Test name
Test status
Simulation time 606047781 ps
CPU time 1.63 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207568 kb
Host smart-0371ed2d-f96b-4d16-ad73-023a1f79df58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23369
13791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.2336913791
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.230339922
Short name T3399
Test name
Test status
Simulation time 147950874 ps
CPU time 0.85 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207576 kb
Host smart-2a79603f-a921-41bc-8752-abacdb185e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23033
9922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.230339922
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3967998471
Short name T1570
Test name
Test status
Simulation time 70225199 ps
CPU time 0.74 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207500 kb
Host smart-47ba891f-71a1-4d0e-aa57-a53801897752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39679
98471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3967998471
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.342078895
Short name T2899
Test name
Test status
Simulation time 931517056 ps
CPU time 2.44 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:36 PM PDT 24
Peak memory 207812 kb
Host smart-71e6cd6a-9d4b-41e2-b788-89faa72e3146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34207
8895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.342078895
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_types.3059427456
Short name T2951
Test name
Test status
Simulation time 466674550 ps
CPU time 1.41 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:32 PM PDT 24
Peak memory 207532 kb
Host smart-1aff9ed9-2da7-4087-a97e-549ae9546e84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3059427456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.3059427456
Directory /workspace/26.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3056461301
Short name T700
Test name
Test status
Simulation time 267557412 ps
CPU time 2.38 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:35 PM PDT 24
Peak memory 207504 kb
Host smart-95d1df5a-84c9-4890-81f8-dc6ef0a38b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564
61301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3056461301
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2344903656
Short name T1374
Test name
Test status
Simulation time 208739553 ps
CPU time 1.14 seconds
Started Aug 13 06:37:38 PM PDT 24
Finished Aug 13 06:37:39 PM PDT 24
Peak memory 215856 kb
Host smart-98bfe18a-bfbf-4b02-a6d6-a00bee2a7949
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2344903656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2344903656
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2297524058
Short name T3187
Test name
Test status
Simulation time 143008999 ps
CPU time 0.87 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207480 kb
Host smart-aafd3c86-bfec-4b38-b601-be7d575207d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22975
24058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2297524058
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.4045983004
Short name T1844
Test name
Test status
Simulation time 167432549 ps
CPU time 0.87 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 207452 kb
Host smart-c3f3d1b7-ad01-4fa3-a8cc-dccf21b84b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40459
83004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.4045983004
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.278747608
Short name T3490
Test name
Test status
Simulation time 3659089551 ps
CPU time 103.53 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 217884 kb
Host smart-bb9822f5-ae18-4794-8078-56139b62272f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=278747608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.278747608
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.49437082
Short name T2189
Test name
Test status
Simulation time 9475489093 ps
CPU time 110.31 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:39:21 PM PDT 24
Peak memory 207756 kb
Host smart-dc44af02-3c8a-4d26-89f0-ce92748fe9ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=49437082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.49437082
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1827226615
Short name T723
Test name
Test status
Simulation time 189730042 ps
CPU time 0.93 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207548 kb
Host smart-0075f056-e511-49f0-8954-707538d3ab64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18272
26615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1827226615
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.2696993692
Short name T2882
Test name
Test status
Simulation time 26646586376 ps
CPU time 45.98 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:38:16 PM PDT 24
Peak memory 207828 kb
Host smart-e6d33ec6-4318-4551-a6cc-b8cab7704a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26969
93692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.2696993692
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.763482175
Short name T256
Test name
Test status
Simulation time 5103054755 ps
CPU time 6.43 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:37 PM PDT 24
Peak memory 207824 kb
Host smart-ccfa0974-ab18-4099-97e5-734b67216eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76348
2175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.763482175
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2814251593
Short name T523
Test name
Test status
Simulation time 5554574717 ps
CPU time 153.26 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:40:04 PM PDT 24
Peak memory 218524 kb
Host smart-4293a9e9-0ab2-41b8-9266-1584814f0db2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2814251593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2814251593
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.4094375821
Short name T3536
Test name
Test status
Simulation time 3032948043 ps
CPU time 31.31 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 215944 kb
Host smart-666f4a95-db24-44ea-bba2-3cb05857c1f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4094375821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.4094375821
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.761455420
Short name T2344
Test name
Test status
Simulation time 258854396 ps
CPU time 1.01 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:32 PM PDT 24
Peak memory 207524 kb
Host smart-ca13c9c0-a69a-45e7-8c8a-9afb87d367d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=761455420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.761455420
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3852212339
Short name T1258
Test name
Test status
Simulation time 209349148 ps
CPU time 1 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207508 kb
Host smart-2c35a8c0-2140-49cf-a85e-0b1501eb6dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38522
12339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3852212339
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1754556936
Short name T3281
Test name
Test status
Simulation time 4153866543 ps
CPU time 123.14 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:39:35 PM PDT 24
Peak memory 217220 kb
Host smart-20787f63-ab7d-4618-bb5a-d9f26dfd33c3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1754556936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1754556936
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3566389041
Short name T2848
Test name
Test status
Simulation time 169217364 ps
CPU time 0.88 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207524 kb
Host smart-88d9c067-1072-4fd1-8a56-0e96228e88db
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3566389041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3566389041
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.733136520
Short name T2108
Test name
Test status
Simulation time 143336943 ps
CPU time 0.83 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207472 kb
Host smart-efe71806-d198-4f32-8b03-a80f11bb3a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73313
6520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.733136520
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.448553036
Short name T156
Test name
Test status
Simulation time 191516813 ps
CPU time 0.92 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207420 kb
Host smart-2581bb80-bbdf-408d-88f9-aa67a3400be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44855
3036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.448553036
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.185662827
Short name T3385
Test name
Test status
Simulation time 192168830 ps
CPU time 0.92 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:37 PM PDT 24
Peak memory 207500 kb
Host smart-3ef36a8b-4656-4a59-9d72-3c2553c752d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18566
2827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.185662827
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1439602724
Short name T3058
Test name
Test status
Simulation time 218958460 ps
CPU time 0.96 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207460 kb
Host smart-d52f30d2-3449-433a-a615-5ac04a4d744c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14396
02724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1439602724
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1146104851
Short name T3121
Test name
Test status
Simulation time 170133324 ps
CPU time 0.85 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207600 kb
Host smart-91ebdfb4-df6c-4ca4-b470-b76cef089bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11461
04851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1146104851
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2673268941
Short name T1592
Test name
Test status
Simulation time 157412990 ps
CPU time 0.9 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207504 kb
Host smart-a8fd586b-9f4f-4576-87c6-7d13d89bafb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26732
68941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2673268941
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2891957590
Short name T1870
Test name
Test status
Simulation time 175469667 ps
CPU time 0.93 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207600 kb
Host smart-804a6b2c-3a54-461b-9b09-7da89ccc096b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2891957590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2891957590
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2964652135
Short name T1233
Test name
Test status
Simulation time 158934844 ps
CPU time 0.87 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207392 kb
Host smart-4e0fd98d-d699-4645-b9c5-c466a0b10470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29646
52135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2964652135
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1711151103
Short name T1981
Test name
Test status
Simulation time 39066923 ps
CPU time 0.71 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207532 kb
Host smart-00175b5d-f057-4d3e-aaaf-f0d89646b6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17111
51103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1711151103
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.864716621
Short name T17
Test name
Test status
Simulation time 13304686289 ps
CPU time 38.4 seconds
Started Aug 13 06:37:35 PM PDT 24
Finished Aug 13 06:38:13 PM PDT 24
Peak memory 223980 kb
Host smart-cddb249b-f87e-4ef4-8f87-3cde77dfc15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86471
6621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.864716621
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.216770081
Short name T1127
Test name
Test status
Simulation time 192762515 ps
CPU time 0.91 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:28 PM PDT 24
Peak memory 207588 kb
Host smart-e9b73322-1a71-4c83-8820-6afe63e55578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21677
0081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.216770081
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.4139809927
Short name T764
Test name
Test status
Simulation time 224331770 ps
CPU time 1.05 seconds
Started Aug 13 06:37:35 PM PDT 24
Finished Aug 13 06:37:36 PM PDT 24
Peak memory 207376 kb
Host smart-fd132700-0881-49f1-8c04-6a43fa621b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41398
09927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.4139809927
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2517803344
Short name T1813
Test name
Test status
Simulation time 191230552 ps
CPU time 1.01 seconds
Started Aug 13 06:37:43 PM PDT 24
Finished Aug 13 06:37:44 PM PDT 24
Peak memory 207508 kb
Host smart-7f152e9b-966c-41ef-8850-d5f6506cc13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25178
03344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2517803344
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.3241727091
Short name T2679
Test name
Test status
Simulation time 199016745 ps
CPU time 0.96 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207440 kb
Host smart-10f3927b-3f3a-4840-8d75-5d0cde89c1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32417
27091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.3241727091
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2710391031
Short name T1608
Test name
Test status
Simulation time 219537349 ps
CPU time 0.93 seconds
Started Aug 13 06:37:41 PM PDT 24
Finished Aug 13 06:37:42 PM PDT 24
Peak memory 207512 kb
Host smart-7212f750-3307-4e2d-84b7-51d9ad1e84f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27103
91031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2710391031
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_rx_full.1556780772
Short name T1055
Test name
Test status
Simulation time 248077625 ps
CPU time 1.14 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207440 kb
Host smart-b079a84a-c9da-4d83-8ee7-451a154667d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15567
80772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.1556780772
Directory /workspace/26.usbdev_rx_full/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3120990751
Short name T2377
Test name
Test status
Simulation time 150685335 ps
CPU time 0.88 seconds
Started Aug 13 06:37:41 PM PDT 24
Finished Aug 13 06:37:42 PM PDT 24
Peak memory 207488 kb
Host smart-be6a9350-682c-4515-a4a5-d3f96ad79d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31209
90751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3120990751
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.653882096
Short name T2980
Test name
Test status
Simulation time 162440639 ps
CPU time 0.87 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207568 kb
Host smart-270d084c-641e-4297-8ca3-920f3e4ff33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65388
2096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.653882096
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2783848248
Short name T3634
Test name
Test status
Simulation time 251745531 ps
CPU time 1.05 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:37 PM PDT 24
Peak memory 207540 kb
Host smart-3bc15a4c-df64-4525-88e3-4c01d03bb36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27838
48248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2783848248
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.778201248
Short name T3128
Test name
Test status
Simulation time 2744419796 ps
CPU time 27.98 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:58 PM PDT 24
Peak memory 215876 kb
Host smart-b15c5a8b-df92-460c-9c85-3c5270ab31df
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=778201248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.778201248
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2332022023
Short name T856
Test name
Test status
Simulation time 182179408 ps
CPU time 0.86 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207524 kb
Host smart-10141651-22ed-466e-8d90-b19ae46b56ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23320
22023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2332022023
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.429632174
Short name T1380
Test name
Test status
Simulation time 176423999 ps
CPU time 0.95 seconds
Started Aug 13 06:37:53 PM PDT 24
Finished Aug 13 06:37:54 PM PDT 24
Peak memory 207528 kb
Host smart-73132a36-6116-4eab-b7fc-c6c6289ef192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42963
2174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.429632174
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.521635348
Short name T1843
Test name
Test status
Simulation time 1005224561 ps
CPU time 2.62 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207740 kb
Host smart-93edd541-2a6f-4d81-97a3-e0ab3aa5bff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52163
5348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.521635348
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.769089861
Short name T164
Test name
Test status
Simulation time 1514103709 ps
CPU time 42.57 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:38:41 PM PDT 24
Peak memory 215992 kb
Host smart-4c31613c-7b70-4916-bbae-1ef0191d40b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76908
9861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.769089861
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.1040511078
Short name T2796
Test name
Test status
Simulation time 2009544199 ps
CPU time 16.69 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:48 PM PDT 24
Peak memory 207680 kb
Host smart-201294b9-dfcb-45ef-96dc-e758cee28fac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040511078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.1040511078
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_tx_rx_disruption.3144203727
Short name T2310
Test name
Test status
Simulation time 573489058 ps
CPU time 1.73 seconds
Started Aug 13 06:37:35 PM PDT 24
Finished Aug 13 06:37:37 PM PDT 24
Peak memory 207540 kb
Host smart-ee8796b5-7162-4652-b2ef-7bc2aea4643c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144203727 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.usbdev_tx_rx_disruption.3144203727
Directory /workspace/26.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/260.usbdev_tx_rx_disruption.1808989273
Short name T1670
Test name
Test status
Simulation time 520713185 ps
CPU time 1.67 seconds
Started Aug 13 06:41:48 PM PDT 24
Finished Aug 13 06:41:50 PM PDT 24
Peak memory 207452 kb
Host smart-9261cc41-a0cc-46e4-91d3-d023baf4d08b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808989273 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 260.usbdev_tx_rx_disruption.1808989273
Directory /workspace/260.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/261.usbdev_tx_rx_disruption.2913608257
Short name T2001
Test name
Test status
Simulation time 561722670 ps
CPU time 1.71 seconds
Started Aug 13 06:42:16 PM PDT 24
Finished Aug 13 06:42:18 PM PDT 24
Peak memory 207544 kb
Host smart-a9453b08-d6c5-448f-9de1-fe9c102a9be8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913608257 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.usbdev_tx_rx_disruption.2913608257
Directory /workspace/261.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/262.usbdev_tx_rx_disruption.2306165818
Short name T2144
Test name
Test status
Simulation time 504036678 ps
CPU time 1.6 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207532 kb
Host smart-8ae97497-9dd5-42f1-a7c6-9de255a09d27
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306165818 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.usbdev_tx_rx_disruption.2306165818
Directory /workspace/262.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/263.usbdev_tx_rx_disruption.3783649154
Short name T622
Test name
Test status
Simulation time 552567955 ps
CPU time 1.62 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207532 kb
Host smart-e6522ab8-3b3d-4673-8303-a0a333e15e7d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783649154 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.usbdev_tx_rx_disruption.3783649154
Directory /workspace/263.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/264.usbdev_tx_rx_disruption.1239719984
Short name T1823
Test name
Test status
Simulation time 483735799 ps
CPU time 1.5 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207628 kb
Host smart-3a73764f-af06-48a1-86eb-e27870066f6f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239719984 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.usbdev_tx_rx_disruption.1239719984
Directory /workspace/264.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/265.usbdev_tx_rx_disruption.590260578
Short name T2575
Test name
Test status
Simulation time 578946924 ps
CPU time 1.55 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207604 kb
Host smart-b140931d-08fd-4822-94d1-277ffdbe6811
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590260578 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 265.usbdev_tx_rx_disruption.590260578
Directory /workspace/265.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/266.usbdev_tx_rx_disruption.1365430341
Short name T171
Test name
Test status
Simulation time 669213384 ps
CPU time 1.76 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207588 kb
Host smart-556bb30d-793d-4662-9571-a0a9cd2d51c6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365430341 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.usbdev_tx_rx_disruption.1365430341
Directory /workspace/266.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/267.usbdev_tx_rx_disruption.695992686
Short name T2151
Test name
Test status
Simulation time 518029628 ps
CPU time 1.55 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207592 kb
Host smart-5691d27f-da12-4b72-9cdf-974976316ab0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695992686 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 267.usbdev_tx_rx_disruption.695992686
Directory /workspace/267.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/269.usbdev_tx_rx_disruption.3709365751
Short name T232
Test name
Test status
Simulation time 500885755 ps
CPU time 1.49 seconds
Started Aug 13 06:41:55 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207576 kb
Host smart-7ded0277-303e-4bef-a3eb-844c764499c6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709365751 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.usbdev_tx_rx_disruption.3709365751
Directory /workspace/269.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.1883295445
Short name T797
Test name
Test status
Simulation time 56650257 ps
CPU time 0.72 seconds
Started Aug 13 06:37:42 PM PDT 24
Finished Aug 13 06:37:43 PM PDT 24
Peak memory 207416 kb
Host smart-5ae61c2d-c4c5-4627-a15d-f05224e2ff63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1883295445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.1883295445
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1763399736
Short name T3406
Test name
Test status
Simulation time 10398564928 ps
CPU time 12.38 seconds
Started Aug 13 06:37:35 PM PDT 24
Finished Aug 13 06:37:48 PM PDT 24
Peak memory 207756 kb
Host smart-a95361f1-b051-40fe-9365-0da429bced3d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763399736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.1763399736
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.48708486
Short name T1454
Test name
Test status
Simulation time 16105707644 ps
CPU time 22.05 seconds
Started Aug 13 06:37:38 PM PDT 24
Finished Aug 13 06:38:00 PM PDT 24
Peak memory 216004 kb
Host smart-58da0008-c4d4-4cc2-b473-5ce913b062e3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=48708486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.48708486
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2904995431
Short name T2698
Test name
Test status
Simulation time 29315263617 ps
CPU time 36.62 seconds
Started Aug 13 06:37:44 PM PDT 24
Finished Aug 13 06:38:20 PM PDT 24
Peak memory 207816 kb
Host smart-64ea0a89-7304-4644-af36-f10f894e018d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904995431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.2904995431
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3669048176
Short name T1697
Test name
Test status
Simulation time 174949173 ps
CPU time 0.91 seconds
Started Aug 13 06:37:53 PM PDT 24
Finished Aug 13 06:37:54 PM PDT 24
Peak memory 207488 kb
Host smart-bcc5c7ab-4078-487a-9d62-4caa53e393a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36690
48176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3669048176
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3573719485
Short name T1081
Test name
Test status
Simulation time 144272063 ps
CPU time 0.87 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:32 PM PDT 24
Peak memory 207576 kb
Host smart-483bfbec-47b1-4996-ae6b-9dc8ae9bbf02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35737
19485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3573719485
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1517278437
Short name T2019
Test name
Test status
Simulation time 461415381 ps
CPU time 1.51 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:38 PM PDT 24
Peak memory 207620 kb
Host smart-7534a6ab-4764-40ad-8940-7f440eb84120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15172
78437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1517278437
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.233334912
Short name T336
Test name
Test status
Simulation time 1473303298 ps
CPU time 3.54 seconds
Started Aug 13 06:37:53 PM PDT 24
Finished Aug 13 06:37:57 PM PDT 24
Peak memory 207832 kb
Host smart-4f882737-559a-4dac-9403-e7a8d29fca9d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=233334912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.233334912
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.1022148106
Short name T3238
Test name
Test status
Simulation time 32742054158 ps
CPU time 48.93 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207792 kb
Host smart-4bf8ffc2-35f3-4cbc-8af4-840c43697ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10221
48106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.1022148106
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.102060145
Short name T1047
Test name
Test status
Simulation time 2944855938 ps
CPU time 24.52 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:54 PM PDT 24
Peak memory 207760 kb
Host smart-76d7bf31-564a-4408-831b-49a75ce110f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102060145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.102060145
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1834057403
Short name T1617
Test name
Test status
Simulation time 1042478949 ps
CPU time 2.29 seconds
Started Aug 13 06:37:27 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207540 kb
Host smart-ce4ef3cb-2ccd-4998-8cc0-9fc0df88c802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340
57403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1834057403
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.252653657
Short name T1504
Test name
Test status
Simulation time 137475940 ps
CPU time 0.81 seconds
Started Aug 13 06:37:46 PM PDT 24
Finished Aug 13 06:37:47 PM PDT 24
Peak memory 207556 kb
Host smart-619428e2-c889-48e7-961d-4a65c0fa5a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25265
3657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.252653657
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1687256761
Short name T1811
Test name
Test status
Simulation time 44764030 ps
CPU time 0.72 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207476 kb
Host smart-c5fd9638-7353-4ba5-8162-e5085d058b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16872
56761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1687256761
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.783647972
Short name T2122
Test name
Test status
Simulation time 952961385 ps
CPU time 2.52 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:37:35 PM PDT 24
Peak memory 207728 kb
Host smart-88068001-b6f2-4fd9-84f7-2f1d5fe53821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78364
7972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.783647972
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_types.2544822745
Short name T484
Test name
Test status
Simulation time 438135530 ps
CPU time 1.43 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:32 PM PDT 24
Peak memory 207508 kb
Host smart-438d709f-5aff-4873-b936-da4d03eb1941
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2544822745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.2544822745
Directory /workspace/27.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1706186000
Short name T941
Test name
Test status
Simulation time 233159970 ps
CPU time 1.76 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:35 PM PDT 24
Peak memory 207696 kb
Host smart-e15d7d1e-0596-4023-9280-af4c76378d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17061
86000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1706186000
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.4217702350
Short name T2478
Test name
Test status
Simulation time 227907143 ps
CPU time 1.16 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 215916 kb
Host smart-52afa2bf-0962-4aa2-a00c-a24aee9def8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4217702350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.4217702350
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3718670754
Short name T782
Test name
Test status
Simulation time 151909441 ps
CPU time 0.85 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207492 kb
Host smart-fbeeb342-b77c-4282-a177-875d1da81123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37186
70754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3718670754
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3928837383
Short name T1593
Test name
Test status
Simulation time 175461446 ps
CPU time 0.89 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207492 kb
Host smart-e4231b43-0e41-4c3c-ab15-acd23ae10244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
37383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3928837383
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.942840553
Short name T2713
Test name
Test status
Simulation time 3245426154 ps
CPU time 24.63 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:56 PM PDT 24
Peak memory 224144 kb
Host smart-e73e5784-130f-4aed-a7f5-5ea83e0759d6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=942840553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.942840553
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.2712707308
Short name T1415
Test name
Test status
Simulation time 12625161653 ps
CPU time 86.74 seconds
Started Aug 13 06:37:32 PM PDT 24
Finished Aug 13 06:38:59 PM PDT 24
Peak memory 207808 kb
Host smart-6f766497-15ba-4f1c-ba66-9e06343f52ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2712707308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.2712707308
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.547757853
Short name T2163
Test name
Test status
Simulation time 234267889 ps
CPU time 0.96 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:39 PM PDT 24
Peak memory 207512 kb
Host smart-30505844-38ea-4a16-bf09-06a52521a650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54775
7853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.547757853
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2093343865
Short name T34
Test name
Test status
Simulation time 34263738769 ps
CPU time 49.26 seconds
Started Aug 13 06:37:37 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207816 kb
Host smart-d1327f12-f5b0-4a13-9949-e2965015108e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20933
43865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2093343865
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.392228275
Short name T639
Test name
Test status
Simulation time 4413704348 ps
CPU time 7.49 seconds
Started Aug 13 06:37:33 PM PDT 24
Finished Aug 13 06:37:41 PM PDT 24
Peak memory 216844 kb
Host smart-aca229cb-edbb-4da3-9ebf-79490ac5bc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39222
8275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.392228275
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.869130516
Short name T982
Test name
Test status
Simulation time 3440910166 ps
CPU time 101.28 seconds
Started Aug 13 06:37:44 PM PDT 24
Finished Aug 13 06:39:26 PM PDT 24
Peak memory 218500 kb
Host smart-a28a2d81-c465-4281-853c-271a1bc8d82b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=869130516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.869130516
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.140053042
Short name T2799
Test name
Test status
Simulation time 2690359793 ps
CPU time 78.35 seconds
Started Aug 13 06:37:36 PM PDT 24
Finished Aug 13 06:38:55 PM PDT 24
Peak memory 224120 kb
Host smart-43c06873-01ff-4318-997e-9e8b946df267
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=140053042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.140053042
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2470571886
Short name T2277
Test name
Test status
Simulation time 299621285 ps
CPU time 1.05 seconds
Started Aug 13 06:37:31 PM PDT 24
Finished Aug 13 06:37:33 PM PDT 24
Peak memory 207556 kb
Host smart-13163f41-e947-49ea-ac2b-12b85db01803
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2470571886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2470571886
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3810601532
Short name T2330
Test name
Test status
Simulation time 187818087 ps
CPU time 0.99 seconds
Started Aug 13 06:37:54 PM PDT 24
Finished Aug 13 06:37:56 PM PDT 24
Peak memory 207492 kb
Host smart-3bfa8aa2-9064-43f4-8558-79cae724e1e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38106
01532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3810601532
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.3497676011
Short name T1340
Test name
Test status
Simulation time 2257366608 ps
CPU time 65.17 seconds
Started Aug 13 06:37:30 PM PDT 24
Finished Aug 13 06:38:35 PM PDT 24
Peak memory 215920 kb
Host smart-602d1a7f-1a1c-43b2-b763-8d5fd663dc2b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3497676011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.3497676011
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3531837376
Short name T1377
Test name
Test status
Simulation time 154908878 ps
CPU time 0.87 seconds
Started Aug 13 06:37:28 PM PDT 24
Finished Aug 13 06:37:29 PM PDT 24
Peak memory 207468 kb
Host smart-3db724cf-518a-4608-bbe4-f6debe47732c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3531837376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3531837376
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3397409751
Short name T3457
Test name
Test status
Simulation time 147324180 ps
CPU time 0.84 seconds
Started Aug 13 06:38:01 PM PDT 24
Finished Aug 13 06:38:02 PM PDT 24
Peak memory 207524 kb
Host smart-cb546895-f31f-452e-9694-93f723255046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33974
09751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3397409751
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.910326251
Short name T738
Test name
Test status
Simulation time 184076806 ps
CPU time 0.91 seconds
Started Aug 13 06:37:41 PM PDT 24
Finished Aug 13 06:37:42 PM PDT 24
Peak memory 207532 kb
Host smart-6e68c6e8-0e82-48f7-8517-50df51ac4ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91032
6251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.910326251
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2544597101
Short name T1933
Test name
Test status
Simulation time 157515496 ps
CPU time 0.86 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:30 PM PDT 24
Peak memory 207488 kb
Host smart-fe330ddc-2f5e-4704-8fdc-5b3280ed915c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25445
97101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2544597101
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3777616059
Short name T3451
Test name
Test status
Simulation time 173082136 ps
CPU time 0.88 seconds
Started Aug 13 06:37:36 PM PDT 24
Finished Aug 13 06:37:37 PM PDT 24
Peak memory 207584 kb
Host smart-61035c49-256b-47a4-87b7-f3c5d064c094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37776
16059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3777616059
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.55102440
Short name T1877
Test name
Test status
Simulation time 168155855 ps
CPU time 0.86 seconds
Started Aug 13 06:37:53 PM PDT 24
Finished Aug 13 06:37:54 PM PDT 24
Peak memory 207572 kb
Host smart-bed5ee9b-c3ad-4334-a8a4-5317020581b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55102
440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.55102440
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.281641238
Short name T1959
Test name
Test status
Simulation time 225826627 ps
CPU time 1.01 seconds
Started Aug 13 06:37:29 PM PDT 24
Finished Aug 13 06:37:31 PM PDT 24
Peak memory 207608 kb
Host smart-a4b7a232-cde6-48a2-81e1-35abd3f5fad7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=281641238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.281641238
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.815702240
Short name T1450
Test name
Test status
Simulation time 142738880 ps
CPU time 0.78 seconds
Started Aug 13 06:37:50 PM PDT 24
Finished Aug 13 06:37:51 PM PDT 24
Peak memory 207460 kb
Host smart-b34c17b5-a261-4bec-83e6-7f4e95b30a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81570
2240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.815702240
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1521547744
Short name T624
Test name
Test status
Simulation time 42598905 ps
CPU time 0.71 seconds
Started Aug 13 06:37:50 PM PDT 24
Finished Aug 13 06:37:51 PM PDT 24
Peak memory 207572 kb
Host smart-15902bec-baf2-4a40-a0a2-8d65d07c5321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15215
47744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1521547744
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2372347454
Short name T3032
Test name
Test status
Simulation time 6202870202 ps
CPU time 16.6 seconds
Started Aug 13 06:37:57 PM PDT 24
Finished Aug 13 06:38:14 PM PDT 24
Peak memory 216016 kb
Host smart-84223d17-b325-4cbf-bdb8-0b5a12837ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23723
47454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2372347454
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1498175266
Short name T358
Test name
Test status
Simulation time 187640619 ps
CPU time 1.01 seconds
Started Aug 13 06:37:51 PM PDT 24
Finished Aug 13 06:37:52 PM PDT 24
Peak memory 207616 kb
Host smart-e4cc217e-d06c-40e7-9b0e-5b1ca454f90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14981
75266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1498175266
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1139909000
Short name T952
Test name
Test status
Simulation time 184265797 ps
CPU time 0.91 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:37:59 PM PDT 24
Peak memory 207496 kb
Host smart-afe5e45f-7225-407f-921f-21d703ed3869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11399
09000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1139909000
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2246226992
Short name T3266
Test name
Test status
Simulation time 185529825 ps
CPU time 0.9 seconds
Started Aug 13 06:37:53 PM PDT 24
Finished Aug 13 06:37:54 PM PDT 24
Peak memory 207492 kb
Host smart-e8630ace-07bf-4244-8e21-c013155f4c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22462
26992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2246226992
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.371310905
Short name T553
Test name
Test status
Simulation time 181761444 ps
CPU time 0.93 seconds
Started Aug 13 06:37:53 PM PDT 24
Finished Aug 13 06:37:54 PM PDT 24
Peak memory 207520 kb
Host smart-8dc9cdc3-4c55-4eab-86bb-c324ad7c4433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37131
0905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.371310905
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1533562117
Short name T1733
Test name
Test status
Simulation time 198637982 ps
CPU time 0.87 seconds
Started Aug 13 06:37:40 PM PDT 24
Finished Aug 13 06:37:41 PM PDT 24
Peak memory 207532 kb
Host smart-b8bd1b11-e46c-4ef4-bbb9-073d87573d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15335
62117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1533562117
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_rx_full.1698347402
Short name T3420
Test name
Test status
Simulation time 290623909 ps
CPU time 1.08 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207636 kb
Host smart-30368ae7-712e-41d7-9a64-86ae4656c0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16983
47402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.1698347402
Directory /workspace/27.usbdev_rx_full/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1538703320
Short name T2287
Test name
Test status
Simulation time 225304574 ps
CPU time 0.89 seconds
Started Aug 13 06:37:50 PM PDT 24
Finished Aug 13 06:37:52 PM PDT 24
Peak memory 207524 kb
Host smart-4a93d9a0-ef0f-490d-a3f9-7cc9360af209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15387
03320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1538703320
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3369449767
Short name T1345
Test name
Test status
Simulation time 153183521 ps
CPU time 0.86 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:00 PM PDT 24
Peak memory 207512 kb
Host smart-e0c98c95-0014-4104-8f13-4ac839c05e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33694
49767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3369449767
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2994074028
Short name T1746
Test name
Test status
Simulation time 220589732 ps
CPU time 0.99 seconds
Started Aug 13 06:37:54 PM PDT 24
Finished Aug 13 06:37:56 PM PDT 24
Peak memory 207416 kb
Host smart-bc19d8b0-2eff-4a83-a3cd-efc087ca43ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29940
74028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2994074028
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.3278862420
Short name T2620
Test name
Test status
Simulation time 3073700924 ps
CPU time 23.57 seconds
Started Aug 13 06:37:49 PM PDT 24
Finished Aug 13 06:38:12 PM PDT 24
Peak memory 217940 kb
Host smart-2a48d808-c879-46ae-a4c2-ba1f6cad39d9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3278862420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.3278862420
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3205987974
Short name T886
Test name
Test status
Simulation time 183436195 ps
CPU time 0.9 seconds
Started Aug 13 06:37:56 PM PDT 24
Finished Aug 13 06:37:57 PM PDT 24
Peak memory 207464 kb
Host smart-5e1d5ae6-b40d-46ae-a972-16d02fb51fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32059
87974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3205987974
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3520304010
Short name T1838
Test name
Test status
Simulation time 167167296 ps
CPU time 0.89 seconds
Started Aug 13 06:37:57 PM PDT 24
Finished Aug 13 06:37:58 PM PDT 24
Peak memory 207512 kb
Host smart-80f9ee56-6db2-41bc-8306-6799082cfd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35203
04010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3520304010
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.3987758910
Short name T2566
Test name
Test status
Simulation time 384876538 ps
CPU time 1.25 seconds
Started Aug 13 06:37:56 PM PDT 24
Finished Aug 13 06:37:58 PM PDT 24
Peak memory 207572 kb
Host smart-ae7a2371-34ad-450e-87a9-3bd3247d3fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39877
58910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.3987758910
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1389401882
Short name T3521
Test name
Test status
Simulation time 1942093051 ps
CPU time 18.91 seconds
Started Aug 13 06:37:56 PM PDT 24
Finished Aug 13 06:38:15 PM PDT 24
Peak memory 216824 kb
Host smart-aecb118f-ec93-42a3-837a-b70ca4ed6828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13894
01882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1389401882
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.2262691919
Short name T3110
Test name
Test status
Simulation time 621461492 ps
CPU time 4.86 seconds
Started Aug 13 06:37:54 PM PDT 24
Finished Aug 13 06:37:59 PM PDT 24
Peak memory 207700 kb
Host smart-74faae8f-ae98-4566-878e-229ef868fd23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262691919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.2262691919
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_tx_rx_disruption.3921106903
Short name T2813
Test name
Test status
Simulation time 594290360 ps
CPU time 1.69 seconds
Started Aug 13 06:37:38 PM PDT 24
Finished Aug 13 06:37:39 PM PDT 24
Peak memory 207544 kb
Host smart-652c54f8-1a08-4c8a-a357-d23bb8e9b20f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921106903 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.usbdev_tx_rx_disruption.3921106903
Directory /workspace/27.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/270.usbdev_tx_rx_disruption.1682662212
Short name T1121
Test name
Test status
Simulation time 534094065 ps
CPU time 1.62 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207536 kb
Host smart-9b62fe8b-a98b-45a1-8b85-c858e2077858
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682662212 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.usbdev_tx_rx_disruption.1682662212
Directory /workspace/270.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/271.usbdev_tx_rx_disruption.2763196745
Short name T1492
Test name
Test status
Simulation time 458840631 ps
CPU time 1.45 seconds
Started Aug 13 06:41:58 PM PDT 24
Finished Aug 13 06:42:00 PM PDT 24
Peak memory 207532 kb
Host smart-e0821685-6e75-41de-8f22-11f58d9d1a32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763196745 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.usbdev_tx_rx_disruption.2763196745
Directory /workspace/271.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/272.usbdev_tx_rx_disruption.515753665
Short name T205
Test name
Test status
Simulation time 499962247 ps
CPU time 1.56 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207552 kb
Host smart-54b14162-017d-4586-8b78-afa0eb3726de
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515753665 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 272.usbdev_tx_rx_disruption.515753665
Directory /workspace/272.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/273.usbdev_tx_rx_disruption.2992944411
Short name T2234
Test name
Test status
Simulation time 612878789 ps
CPU time 1.64 seconds
Started Aug 13 06:41:49 PM PDT 24
Finished Aug 13 06:41:50 PM PDT 24
Peak memory 207468 kb
Host smart-49e6183f-7549-46e1-ba6b-60d4cd3a68b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992944411 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.usbdev_tx_rx_disruption.2992944411
Directory /workspace/273.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/274.usbdev_tx_rx_disruption.1962153153
Short name T2891
Test name
Test status
Simulation time 478239552 ps
CPU time 1.55 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207572 kb
Host smart-f7dfe954-200b-437f-8198-ea8c01a168a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962153153 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.usbdev_tx_rx_disruption.1962153153
Directory /workspace/274.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/275.usbdev_tx_rx_disruption.740092786
Short name T1993
Test name
Test status
Simulation time 484185166 ps
CPU time 1.67 seconds
Started Aug 13 06:41:45 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207552 kb
Host smart-61e4ac4e-bb8e-4f2f-b38d-30d8afa6e71a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740092786 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 275.usbdev_tx_rx_disruption.740092786
Directory /workspace/275.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/276.usbdev_tx_rx_disruption.230673601
Short name T1302
Test name
Test status
Simulation time 471625744 ps
CPU time 1.65 seconds
Started Aug 13 06:42:30 PM PDT 24
Finished Aug 13 06:42:32 PM PDT 24
Peak memory 207612 kb
Host smart-a7efa660-4566-4443-8581-69ee7192f2c2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230673601 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 276.usbdev_tx_rx_disruption.230673601
Directory /workspace/276.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/277.usbdev_tx_rx_disruption.3393579094
Short name T1773
Test name
Test status
Simulation time 516260433 ps
CPU time 1.64 seconds
Started Aug 13 06:41:59 PM PDT 24
Finished Aug 13 06:42:02 PM PDT 24
Peak memory 207612 kb
Host smart-0a8a2acb-045b-47cf-b5e8-ca9acfb9f56f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393579094 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.usbdev_tx_rx_disruption.3393579094
Directory /workspace/277.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/278.usbdev_tx_rx_disruption.3663815811
Short name T1329
Test name
Test status
Simulation time 559986301 ps
CPU time 1.48 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207588 kb
Host smart-6b12dfc7-74c8-4691-8873-90c038a6cb0c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663815811 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.usbdev_tx_rx_disruption.3663815811
Directory /workspace/278.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/279.usbdev_tx_rx_disruption.1525145985
Short name T2649
Test name
Test status
Simulation time 489774100 ps
CPU time 1.43 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:59 PM PDT 24
Peak memory 207524 kb
Host smart-df458957-4c58-4853-b860-6a3f97acf991
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525145985 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.usbdev_tx_rx_disruption.1525145985
Directory /workspace/279.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3858187950
Short name T1275
Test name
Test status
Simulation time 63610655 ps
CPU time 0.7 seconds
Started Aug 13 06:38:05 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 207480 kb
Host smart-94f69e6d-f53f-4b68-b3a8-e8f7c8d223ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3858187950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3858187950
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.337573064
Short name T955
Test name
Test status
Simulation time 8809116422 ps
CPU time 10.5 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:38:09 PM PDT 24
Peak memory 207796 kb
Host smart-6b68c611-2c64-4d97-aeaf-8cee9a44e627
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337573064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_ao
n_wake_disconnect.337573064
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1627814622
Short name T1327
Test name
Test status
Simulation time 18941106862 ps
CPU time 23.62 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207844 kb
Host smart-a79dea00-9f11-4595-a7b7-b7e9408a1ddb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627814622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1627814622
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.1246257123
Short name T1932
Test name
Test status
Simulation time 30707805663 ps
CPU time 38.86 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:38:37 PM PDT 24
Peak memory 207780 kb
Host smart-3a43cf41-7506-46f3-8a12-469cd22769da
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246257123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.1246257123
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1339628924
Short name T3291
Test name
Test status
Simulation time 186061845 ps
CPU time 0.98 seconds
Started Aug 13 06:37:41 PM PDT 24
Finished Aug 13 06:37:43 PM PDT 24
Peak memory 207488 kb
Host smart-34465fd1-8dc1-46cb-a97d-35405721e02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13396
28924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1339628924
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.4287362454
Short name T3591
Test name
Test status
Simulation time 166570520 ps
CPU time 0.88 seconds
Started Aug 13 06:38:03 PM PDT 24
Finished Aug 13 06:38:04 PM PDT 24
Peak memory 207572 kb
Host smart-668a40c5-e76b-4e0b-a0b4-b589358edba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42873
62454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.4287362454
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1134347424
Short name T2045
Test name
Test status
Simulation time 336198930 ps
CPU time 1.34 seconds
Started Aug 13 06:37:49 PM PDT 24
Finished Aug 13 06:37:50 PM PDT 24
Peak memory 207524 kb
Host smart-8834b8e5-27b3-4126-8c65-e06c5122fd1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11343
47424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1134347424
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3793671571
Short name T345
Test name
Test status
Simulation time 925358598 ps
CPU time 2.76 seconds
Started Aug 13 06:37:43 PM PDT 24
Finished Aug 13 06:37:46 PM PDT 24
Peak memory 207688 kb
Host smart-ffdef85a-652d-4aa3-ab1a-b6fd20091ea2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3793671571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3793671571
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3728650498
Short name T2963
Test name
Test status
Simulation time 44528812181 ps
CPU time 76.75 seconds
Started Aug 13 06:38:01 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207724 kb
Host smart-2250b73b-e760-4a8d-bd8d-cd79a78ea56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
50498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3728650498
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.138714759
Short name T1247
Test name
Test status
Simulation time 2997280407 ps
CPU time 26.06 seconds
Started Aug 13 06:37:57 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207752 kb
Host smart-c983765f-0ba4-4a92-a1a9-5bc62f8f0316
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138714759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.138714759
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3327151159
Short name T1888
Test name
Test status
Simulation time 615931530 ps
CPU time 1.85 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:38:00 PM PDT 24
Peak memory 207536 kb
Host smart-5947e22c-09d8-4830-b580-bad5c08563c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33271
51159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3327151159
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2278138406
Short name T3069
Test name
Test status
Simulation time 157731885 ps
CPU time 0.85 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:37:59 PM PDT 24
Peak memory 207560 kb
Host smart-7e5ba303-4e32-40f2-a423-c01b49754ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22781
38406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2278138406
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3696839175
Short name T1721
Test name
Test status
Simulation time 66928453 ps
CPU time 0.79 seconds
Started Aug 13 06:37:53 PM PDT 24
Finished Aug 13 06:37:54 PM PDT 24
Peak memory 207460 kb
Host smart-23bcdf51-1a31-4d83-9202-a09d93a43a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36968
39175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3696839175
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.4279293664
Short name T3013
Test name
Test status
Simulation time 885435488 ps
CPU time 2.31 seconds
Started Aug 13 06:37:59 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207764 kb
Host smart-dcd0cd31-63cb-41ed-af4b-28324eb4f7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42792
93664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.4279293664
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_types.1041100410
Short name T2109
Test name
Test status
Simulation time 391755775 ps
CPU time 1.26 seconds
Started Aug 13 06:37:49 PM PDT 24
Finished Aug 13 06:37:50 PM PDT 24
Peak memory 207572 kb
Host smart-4b0da1a1-a980-4aec-9ce4-a7b8de5a7bc8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1041100410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.1041100410
Directory /workspace/28.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3816375245
Short name T1679
Test name
Test status
Simulation time 414357335 ps
CPU time 2.84 seconds
Started Aug 13 06:37:49 PM PDT 24
Finished Aug 13 06:37:52 PM PDT 24
Peak memory 207648 kb
Host smart-bb21b591-1490-47cb-b95e-935ef37f9110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38163
75245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3816375245
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2358399003
Short name T564
Test name
Test status
Simulation time 218744221 ps
CPU time 1.11 seconds
Started Aug 13 06:37:54 PM PDT 24
Finished Aug 13 06:37:55 PM PDT 24
Peak memory 215916 kb
Host smart-a1dac601-d497-40c7-a631-7bdea5209efc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2358399003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2358399003
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3108966422
Short name T1556
Test name
Test status
Simulation time 165736059 ps
CPU time 0.93 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:03 PM PDT 24
Peak memory 207488 kb
Host smart-c1c4f8b8-8aca-48c5-9dd5-cadee6692820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31089
66422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3108966422
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2283945291
Short name T2950
Test name
Test status
Simulation time 202342884 ps
CPU time 1.06 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207488 kb
Host smart-0155072f-7123-4f56-bc2d-6465e3f06a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22839
45291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2283945291
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3289607880
Short name T2275
Test name
Test status
Simulation time 4025363435 ps
CPU time 118.9 seconds
Started Aug 13 06:37:54 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 215948 kb
Host smart-341d2869-51b7-4e09-9002-b2ef707147d8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3289607880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3289607880
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.3689097597
Short name T1680
Test name
Test status
Simulation time 11820018492 ps
CPU time 156.64 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:40:35 PM PDT 24
Peak memory 207840 kb
Host smart-313e8b7c-424c-48bc-b8da-0d88c785a1e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3689097597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.3689097597
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1529108556
Short name T627
Test name
Test status
Simulation time 205695820 ps
CPU time 0.9 seconds
Started Aug 13 06:37:50 PM PDT 24
Finished Aug 13 06:37:52 PM PDT 24
Peak memory 207588 kb
Host smart-463b61c5-0dd3-44b0-b257-9d1687bcd50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15291
08556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1529108556
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2586685697
Short name T2231
Test name
Test status
Simulation time 27459280610 ps
CPU time 32.11 seconds
Started Aug 13 06:37:49 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 216008 kb
Host smart-b7af1f7d-cf93-4330-8ef3-b7d13c89562f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25866
85697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2586685697
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2405432450
Short name T1369
Test name
Test status
Simulation time 5567667468 ps
CPU time 8.97 seconds
Started Aug 13 06:37:59 PM PDT 24
Finished Aug 13 06:38:08 PM PDT 24
Peak memory 215996 kb
Host smart-cde89c18-a324-455b-ae64-59d498817702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24054
32450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2405432450
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.3105979801
Short name T1997
Test name
Test status
Simulation time 2712019976 ps
CPU time 81.31 seconds
Started Aug 13 06:37:51 PM PDT 24
Finished Aug 13 06:39:12 PM PDT 24
Peak memory 218484 kb
Host smart-f4102f56-8055-44f2-8cf8-cd603920b751
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3105979801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.3105979801
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.1207947170
Short name T574
Test name
Test status
Simulation time 3377012279 ps
CPU time 32.66 seconds
Started Aug 13 06:37:56 PM PDT 24
Finished Aug 13 06:38:29 PM PDT 24
Peak memory 217584 kb
Host smart-5eba70ed-2249-4e1f-b7af-9f532365a5dd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1207947170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.1207947170
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.3196389864
Short name T2995
Test name
Test status
Simulation time 262047223 ps
CPU time 1.01 seconds
Started Aug 13 06:37:47 PM PDT 24
Finished Aug 13 06:37:48 PM PDT 24
Peak memory 207512 kb
Host smart-01c15d72-63e5-4c87-8afb-44426791eeb5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3196389864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3196389864
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.370443411
Short name T2301
Test name
Test status
Simulation time 209529124 ps
CPU time 0.99 seconds
Started Aug 13 06:37:59 PM PDT 24
Finished Aug 13 06:38:00 PM PDT 24
Peak memory 207516 kb
Host smart-5becb405-4b1d-44f8-b03c-f5721ca69620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37044
3411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.370443411
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1715187120
Short name T3283
Test name
Test status
Simulation time 2355655560 ps
CPU time 67.95 seconds
Started Aug 13 06:37:57 PM PDT 24
Finished Aug 13 06:39:05 PM PDT 24
Peak memory 217528 kb
Host smart-119927fc-5fa4-4e5a-aee9-6f7af33a440b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1715187120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1715187120
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.4143281756
Short name T793
Test name
Test status
Simulation time 170062107 ps
CPU time 0.89 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:03 PM PDT 24
Peak memory 207444 kb
Host smart-12f507c8-8b2e-4b07-879a-75657336c72f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4143281756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.4143281756
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3411696987
Short name T872
Test name
Test status
Simulation time 145925198 ps
CPU time 0.88 seconds
Started Aug 13 06:37:56 PM PDT 24
Finished Aug 13 06:37:57 PM PDT 24
Peak memory 207620 kb
Host smart-6f65cce8-6a7f-4a95-9dc8-608a69d030ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34116
96987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3411696987
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1711993185
Short name T3408
Test name
Test status
Simulation time 259864300 ps
CPU time 0.97 seconds
Started Aug 13 06:38:08 PM PDT 24
Finished Aug 13 06:38:09 PM PDT 24
Peak memory 207392 kb
Host smart-f7135855-3e58-4452-8306-fbc89747006c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17119
93185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1711993185
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3727001807
Short name T540
Test name
Test status
Simulation time 169725472 ps
CPU time 0.9 seconds
Started Aug 13 06:37:54 PM PDT 24
Finished Aug 13 06:37:55 PM PDT 24
Peak memory 207540 kb
Host smart-8d561248-baed-42ca-9617-fe2bda05dc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37270
01807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3727001807
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3376694814
Short name T1654
Test name
Test status
Simulation time 222304380 ps
CPU time 0.97 seconds
Started Aug 13 06:37:55 PM PDT 24
Finished Aug 13 06:37:56 PM PDT 24
Peak memory 207416 kb
Host smart-991afc0f-3f67-4db4-9247-c23ca5b5d496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33766
94814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3376694814
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2808020857
Short name T3372
Test name
Test status
Simulation time 181509393 ps
CPU time 0.87 seconds
Started Aug 13 06:37:38 PM PDT 24
Finished Aug 13 06:37:39 PM PDT 24
Peak memory 207568 kb
Host smart-c3bd51a8-db52-4d03-b019-1b70f4c2d936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28080
20857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2808020857
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1670291287
Short name T2396
Test name
Test status
Simulation time 157648376 ps
CPU time 0.84 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207604 kb
Host smart-b9359c7d-8418-4707-a063-dd74528663d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16702
91287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1670291287
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1810979279
Short name T1463
Test name
Test status
Simulation time 221916260 ps
CPU time 1 seconds
Started Aug 13 06:38:06 PM PDT 24
Finished Aug 13 06:38:07 PM PDT 24
Peak memory 207616 kb
Host smart-b9fc76e6-bfc4-4718-b1de-bb7806a9e239
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1810979279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1810979279
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2987894381
Short name T1330
Test name
Test status
Simulation time 138421948 ps
CPU time 0.85 seconds
Started Aug 13 06:38:04 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 207440 kb
Host smart-27c4da5d-461a-4033-a1e1-c4563e320f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878
94381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2987894381
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1620871930
Short name T31
Test name
Test status
Simulation time 55888695 ps
CPU time 0.69 seconds
Started Aug 13 06:37:59 PM PDT 24
Finished Aug 13 06:38:00 PM PDT 24
Peak memory 207516 kb
Host smart-106afcee-8e1b-4bc4-b2dd-51348bb19c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16208
71930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1620871930
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.356498206
Short name T2999
Test name
Test status
Simulation time 21472231658 ps
CPU time 59.63 seconds
Started Aug 13 06:37:53 PM PDT 24
Finished Aug 13 06:38:53 PM PDT 24
Peak memory 215888 kb
Host smart-2627861c-d6df-4968-a907-40cd4f331185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35649
8206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.356498206
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2901482604
Short name T2644
Test name
Test status
Simulation time 181286283 ps
CPU time 0.94 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207604 kb
Host smart-9a274127-ff5d-4910-b13b-498d9f9c2df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29014
82604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2901482604
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2885620167
Short name T2312
Test name
Test status
Simulation time 245116010 ps
CPU time 1.07 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207480 kb
Host smart-5c33a402-9a0d-4957-8764-1de22f5c7d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28856
20167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2885620167
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3911427499
Short name T3257
Test name
Test status
Simulation time 244834784 ps
CPU time 0.94 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:08 PM PDT 24
Peak memory 207624 kb
Host smart-e03404fa-6c43-41d9-9edc-53bf125d8b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
27499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3911427499
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1078271354
Short name T1937
Test name
Test status
Simulation time 177110417 ps
CPU time 0.88 seconds
Started Aug 13 06:37:54 PM PDT 24
Finished Aug 13 06:37:55 PM PDT 24
Peak memory 207436 kb
Host smart-14eb6535-9921-4b56-8215-363d642d1e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10782
71354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1078271354
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2189244008
Short name T1200
Test name
Test status
Simulation time 170432578 ps
CPU time 0.86 seconds
Started Aug 13 06:38:08 PM PDT 24
Finished Aug 13 06:38:09 PM PDT 24
Peak memory 207464 kb
Host smart-8be5e152-f103-48d2-87f5-d0bd29a3fc8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21892
44008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2189244008
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_rx_full.4126390289
Short name T2170
Test name
Test status
Simulation time 317545312 ps
CPU time 1.2 seconds
Started Aug 13 06:38:01 PM PDT 24
Finished Aug 13 06:38:02 PM PDT 24
Peak memory 207528 kb
Host smart-6b34e5d0-6b7f-4add-9ca7-df7a72acaa40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41263
90289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.4126390289
Directory /workspace/28.usbdev_rx_full/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2202014835
Short name T2272
Test name
Test status
Simulation time 150339854 ps
CPU time 0.85 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207452 kb
Host smart-e773d8b1-6b9e-478c-b900-e80d9753b91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22020
14835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2202014835
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1684986665
Short name T3177
Test name
Test status
Simulation time 183920623 ps
CPU time 0.85 seconds
Started Aug 13 06:38:03 PM PDT 24
Finished Aug 13 06:38:04 PM PDT 24
Peak memory 207516 kb
Host smart-3bdce3df-2a83-4f3e-b3c8-3d39c0a2ee3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16849
86665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1684986665
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.812182035
Short name T1015
Test name
Test status
Simulation time 192214469 ps
CPU time 1 seconds
Started Aug 13 06:37:59 PM PDT 24
Finished Aug 13 06:38:00 PM PDT 24
Peak memory 207540 kb
Host smart-0c011e67-a0f8-4da2-ace9-caed7b6a4202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81218
2035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.812182035
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.506881791
Short name T2549
Test name
Test status
Simulation time 2521426415 ps
CPU time 70.24 seconds
Started Aug 13 06:38:06 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 215932 kb
Host smart-cd82b825-18e2-441c-971a-82ea917455be
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=506881791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.506881791
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1130892635
Short name T1989
Test name
Test status
Simulation time 178087960 ps
CPU time 0.91 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207512 kb
Host smart-6f11ada6-8a64-4b52-b764-10ae42866a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11308
92635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1130892635
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2908793510
Short name T3026
Test name
Test status
Simulation time 160790439 ps
CPU time 0.86 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:08 PM PDT 24
Peak memory 207624 kb
Host smart-ebec75a3-2854-4e12-b074-502d52d7774f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29087
93510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2908793510
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.638698294
Short name T2273
Test name
Test status
Simulation time 1147209646 ps
CPU time 2.59 seconds
Started Aug 13 06:38:08 PM PDT 24
Finished Aug 13 06:38:11 PM PDT 24
Peak memory 207772 kb
Host smart-a83da4be-ad04-4233-bd7e-eb1b74eae009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63869
8294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.638698294
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1782705630
Short name T2193
Test name
Test status
Simulation time 2049778376 ps
CPU time 57.17 seconds
Started Aug 13 06:38:12 PM PDT 24
Finished Aug 13 06:39:09 PM PDT 24
Peak memory 217592 kb
Host smart-31178a37-8ddc-4419-969e-69e08e54e6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17827
05630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1782705630
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.4274893257
Short name T3377
Test name
Test status
Simulation time 1100133282 ps
CPU time 9.15 seconds
Started Aug 13 06:37:43 PM PDT 24
Finished Aug 13 06:37:53 PM PDT 24
Peak memory 207684 kb
Host smart-d08c56bf-062d-4f81-8936-1e902d7705bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274893257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.4274893257
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_tx_rx_disruption.3980232613
Short name T117
Test name
Test status
Simulation time 577997557 ps
CPU time 1.58 seconds
Started Aug 13 06:37:56 PM PDT 24
Finished Aug 13 06:37:58 PM PDT 24
Peak memory 207576 kb
Host smart-6258d5c2-3baf-4821-8fe7-e64e3544b7a6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980232613 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.usbdev_tx_rx_disruption.3980232613
Directory /workspace/28.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/280.usbdev_tx_rx_disruption.1438206140
Short name T3004
Test name
Test status
Simulation time 464252740 ps
CPU time 1.45 seconds
Started Aug 13 06:42:16 PM PDT 24
Finished Aug 13 06:42:18 PM PDT 24
Peak memory 207592 kb
Host smart-132cae3f-ec48-4256-be23-37b8f7e204c4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438206140 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.usbdev_tx_rx_disruption.1438206140
Directory /workspace/280.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/281.usbdev_tx_rx_disruption.1638409
Short name T2727
Test name
Test status
Simulation time 522530590 ps
CPU time 1.51 seconds
Started Aug 13 06:42:02 PM PDT 24
Finished Aug 13 06:42:04 PM PDT 24
Peak memory 207584 kb
Host smart-ea5877f7-b010-48ab-96e4-eb73908ca9e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638409 -assert nopostproc +UVM_TESTN
AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 281.usbdev_tx_rx_disruption.1638409
Directory /workspace/281.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/282.usbdev_tx_rx_disruption.1053306475
Short name T2795
Test name
Test status
Simulation time 552008383 ps
CPU time 1.53 seconds
Started Aug 13 06:42:00 PM PDT 24
Finished Aug 13 06:42:01 PM PDT 24
Peak memory 207584 kb
Host smart-a3806ce5-6f3c-4c06-8c4a-11a891c97c18
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053306475 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.usbdev_tx_rx_disruption.1053306475
Directory /workspace/282.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/283.usbdev_tx_rx_disruption.1477045743
Short name T2332
Test name
Test status
Simulation time 479227665 ps
CPU time 1.67 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207580 kb
Host smart-e819adc6-76f2-457c-9e94-a75ad17d94ea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477045743 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.usbdev_tx_rx_disruption.1477045743
Directory /workspace/283.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/284.usbdev_tx_rx_disruption.33228160
Short name T262
Test name
Test status
Simulation time 542528195 ps
CPU time 1.47 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207620 kb
Host smart-532b9776-2cf7-462a-8b07-6aabb089741e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228160 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 284.usbdev_tx_rx_disruption.33228160
Directory /workspace/284.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/285.usbdev_tx_rx_disruption.3824437401
Short name T2738
Test name
Test status
Simulation time 435722785 ps
CPU time 1.41 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 207600 kb
Host smart-54541813-ee87-4712-81e3-a6bab0d4901a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824437401 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.usbdev_tx_rx_disruption.3824437401
Directory /workspace/285.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/286.usbdev_tx_rx_disruption.101027918
Short name T3325
Test name
Test status
Simulation time 430066075 ps
CPU time 1.32 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207516 kb
Host smart-8d38e36f-a7cd-46ff-9b8e-5e57a17d5b35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101027918 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 286.usbdev_tx_rx_disruption.101027918
Directory /workspace/286.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/287.usbdev_tx_rx_disruption.2617147208
Short name T3600
Test name
Test status
Simulation time 495407221 ps
CPU time 1.64 seconds
Started Aug 13 06:41:55 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207612 kb
Host smart-72a6d41f-02dd-4bd0-b037-e8a9024380c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617147208 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.usbdev_tx_rx_disruption.2617147208
Directory /workspace/287.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/288.usbdev_tx_rx_disruption.3521319702
Short name T1772
Test name
Test status
Simulation time 640205602 ps
CPU time 1.74 seconds
Started Aug 13 06:42:28 PM PDT 24
Finished Aug 13 06:42:30 PM PDT 24
Peak memory 207616 kb
Host smart-95374f54-97b5-4381-91d8-d3932ea701c8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521319702 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.usbdev_tx_rx_disruption.3521319702
Directory /workspace/288.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/289.usbdev_tx_rx_disruption.937569620
Short name T2831
Test name
Test status
Simulation time 483362849 ps
CPU time 1.55 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 207608 kb
Host smart-6183055d-900b-4a9f-ba8d-5580752c3f84
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937569620 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 289.usbdev_tx_rx_disruption.937569620
Directory /workspace/289.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.2069406627
Short name T968
Test name
Test status
Simulation time 41796792 ps
CPU time 0.71 seconds
Started Aug 13 06:38:10 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207404 kb
Host smart-6458d03d-03b6-4242-912d-14c70acc5e24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2069406627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.2069406627
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1269400781
Short name T3017
Test name
Test status
Simulation time 12147231656 ps
CPU time 15.18 seconds
Started Aug 13 06:38:05 PM PDT 24
Finished Aug 13 06:38:20 PM PDT 24
Peak memory 207772 kb
Host smart-7ed17aaa-1145-463d-901a-c15f9df9ecf2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269400781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.1269400781
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.4028460456
Short name T1509
Test name
Test status
Simulation time 14568835545 ps
CPU time 16.95 seconds
Started Aug 13 06:37:54 PM PDT 24
Finished Aug 13 06:38:11 PM PDT 24
Peak memory 215992 kb
Host smart-e8aeaa40-c26b-4d67-9fe2-0ebc46c0b7f8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028460456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.4028460456
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2725197442
Short name T1532
Test name
Test status
Simulation time 29173623313 ps
CPU time 34.11 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:38:32 PM PDT 24
Peak memory 207840 kb
Host smart-01863df4-ed7b-4012-94fb-c753968e8cd3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725197442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.2725197442
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2369136781
Short name T2540
Test name
Test status
Simulation time 187252933 ps
CPU time 0.98 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:03 PM PDT 24
Peak memory 207488 kb
Host smart-3829eee7-165a-4959-91c4-19331f8d881d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23691
36781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2369136781
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1756290130
Short name T3071
Test name
Test status
Simulation time 149988050 ps
CPU time 0.83 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207572 kb
Host smart-f2f2c0a6-fb08-4173-a0a5-87a3b7e0387d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17562
90130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1756290130
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.2460343004
Short name T1780
Test name
Test status
Simulation time 344013381 ps
CPU time 1.37 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207608 kb
Host smart-4587d03e-4699-463c-b5fb-6cdb3477657f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24603
43004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.2460343004
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1006830273
Short name T338
Test name
Test status
Simulation time 742757510 ps
CPU time 2.06 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207680 kb
Host smart-0c9065ad-fc71-49d5-896b-168dfd4f8c7c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1006830273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1006830273
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1254513106
Short name T2021
Test name
Test status
Simulation time 17670646354 ps
CPU time 30.39 seconds
Started Aug 13 06:38:08 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 207808 kb
Host smart-69a7378e-79f8-4b6f-b378-bae651cf2b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12545
13106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1254513106
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.1930405368
Short name T1018
Test name
Test status
Simulation time 4757133696 ps
CPU time 39.87 seconds
Started Aug 13 06:38:01 PM PDT 24
Finished Aug 13 06:38:41 PM PDT 24
Peak memory 207780 kb
Host smart-bbaee043-6094-4f8a-bf26-2491f269ab2a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930405368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.1930405368
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.2627857030
Short name T1609
Test name
Test status
Simulation time 547395925 ps
CPU time 1.61 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:11 PM PDT 24
Peak memory 207504 kb
Host smart-c13588cb-d902-487b-98aa-b008f5039c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26278
57030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.2627857030
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3011245980
Short name T2789
Test name
Test status
Simulation time 188635453 ps
CPU time 0.92 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:37:59 PM PDT 24
Peak memory 207568 kb
Host smart-48c96ad8-2a96-492c-8cc5-efac7b580340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30112
45980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3011245980
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.663024497
Short name T3076
Test name
Test status
Simulation time 42476997 ps
CPU time 0.69 seconds
Started Aug 13 06:38:03 PM PDT 24
Finished Aug 13 06:38:04 PM PDT 24
Peak memory 207480 kb
Host smart-a479326d-46a0-4fe8-94dc-c28e7519373a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66302
4497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.663024497
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1314768014
Short name T2981
Test name
Test status
Simulation time 983207518 ps
CPU time 2.68 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 207520 kb
Host smart-4972b6e7-0eb7-4e14-bf56-f133c09ce19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13147
68014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1314768014
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2397478508
Short name T3294
Test name
Test status
Simulation time 202965028 ps
CPU time 1.72 seconds
Started Aug 13 06:38:06 PM PDT 24
Finished Aug 13 06:38:08 PM PDT 24
Peak memory 207656 kb
Host smart-a5a5cd08-0249-4f04-8303-b2d2cd803eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23974
78508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2397478508
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3545200898
Short name T3332
Test name
Test status
Simulation time 181506069 ps
CPU time 0.93 seconds
Started Aug 13 06:37:59 PM PDT 24
Finished Aug 13 06:38:00 PM PDT 24
Peak memory 207488 kb
Host smart-5a5c86bd-5af3-49b0-b06a-3221c3e725fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3545200898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3545200898
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1828213237
Short name T1354
Test name
Test status
Simulation time 174535685 ps
CPU time 0.98 seconds
Started Aug 13 06:38:10 PM PDT 24
Finished Aug 13 06:38:11 PM PDT 24
Peak memory 207476 kb
Host smart-32aa5f96-ca7a-4b15-bf37-82e4e5c73ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18282
13237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1828213237
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3270603191
Short name T3164
Test name
Test status
Simulation time 151781999 ps
CPU time 0.87 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207448 kb
Host smart-adf0f119-9501-4355-b017-11470aade994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32706
03191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3270603191
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.3828813951
Short name T3292
Test name
Test status
Simulation time 3269743156 ps
CPU time 25.47 seconds
Started Aug 13 06:38:05 PM PDT 24
Finished Aug 13 06:38:30 PM PDT 24
Peak memory 224120 kb
Host smart-ee1b6c24-ad58-48cb-bb90-0a93bbe70078
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3828813951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.3828813951
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.2730672143
Short name T1256
Test name
Test status
Simulation time 4235056136 ps
CPU time 29.49 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:32 PM PDT 24
Peak memory 207828 kb
Host smart-b36042f8-4aae-439d-9f4b-fbb9e8b740ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2730672143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.2730672143
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.4283527519
Short name T1487
Test name
Test status
Simulation time 206457675 ps
CPU time 0.97 seconds
Started Aug 13 06:38:03 PM PDT 24
Finished Aug 13 06:38:04 PM PDT 24
Peak memory 207608 kb
Host smart-86f0957b-e1f1-43e6-a153-71aabcb82911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42835
27519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.4283527519
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3053002392
Short name T2408
Test name
Test status
Simulation time 22604802691 ps
CPU time 36.58 seconds
Started Aug 13 06:37:58 PM PDT 24
Finished Aug 13 06:38:35 PM PDT 24
Peak memory 216164 kb
Host smart-67d0894b-a9ae-4160-ac25-8bb217a9ebdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
02392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3053002392
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3959504322
Short name T1610
Test name
Test status
Simulation time 10044006542 ps
CPU time 13.95 seconds
Started Aug 13 06:37:59 PM PDT 24
Finished Aug 13 06:38:13 PM PDT 24
Peak memory 207784 kb
Host smart-5e2dfe89-b273-40ff-afbb-dc3e6048f529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39595
04322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3959504322
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2430292698
Short name T3510
Test name
Test status
Simulation time 2537019877 ps
CPU time 25.48 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:32 PM PDT 24
Peak memory 224152 kb
Host smart-1cd387d1-92f7-4335-b3b3-b5a421a1b300
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2430292698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2430292698
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.805633995
Short name T1692
Test name
Test status
Simulation time 3162245390 ps
CPU time 33.72 seconds
Started Aug 13 06:37:54 PM PDT 24
Finished Aug 13 06:38:28 PM PDT 24
Peak memory 217748 kb
Host smart-36c91709-2492-4d79-8337-2783516415cf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=805633995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.805633995
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1144247299
Short name T1328
Test name
Test status
Simulation time 234145532 ps
CPU time 0.96 seconds
Started Aug 13 06:37:56 PM PDT 24
Finished Aug 13 06:37:57 PM PDT 24
Peak memory 207532 kb
Host smart-ec4f3b3a-9d25-46a1-8bd9-1eb8e62f5009
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1144247299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1144247299
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3032938407
Short name T2103
Test name
Test status
Simulation time 220697043 ps
CPU time 0.96 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207512 kb
Host smart-c222f362-8fe1-4fcc-9750-f205ec8dd80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30329
38407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3032938407
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.1884593201
Short name T1616
Test name
Test status
Simulation time 2573212494 ps
CPU time 19.83 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 217608 kb
Host smart-056541b4-9f60-4433-a7a7-4c6c0282acf6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1884593201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1884593201
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.980213876
Short name T1167
Test name
Test status
Simulation time 159913197 ps
CPU time 0.85 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207448 kb
Host smart-093f47a0-73f3-4bd2-8e1f-715e3631de54
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=980213876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.980213876
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3131855018
Short name T3052
Test name
Test status
Simulation time 207970592 ps
CPU time 0.98 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:03 PM PDT 24
Peak memory 207316 kb
Host smart-2cece524-afa9-49ec-8468-5c867e50bb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31318
55018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3131855018
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2598986401
Short name T128
Test name
Test status
Simulation time 223641492 ps
CPU time 0.96 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207532 kb
Host smart-4a96c73c-3192-4560-9a46-4d40dfdf5c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25989
86401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2598986401
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.451978265
Short name T620
Test name
Test status
Simulation time 194280174 ps
CPU time 0.99 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:03 PM PDT 24
Peak memory 207524 kb
Host smart-2c329b64-8a97-462d-b645-ab6837960d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45197
8265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.451978265
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.4142637797
Short name T2455
Test name
Test status
Simulation time 228619122 ps
CPU time 0.99 seconds
Started Aug 13 06:38:05 PM PDT 24
Finished Aug 13 06:38:06 PM PDT 24
Peak memory 207492 kb
Host smart-ce6682f0-659b-4f96-aac2-044ad1d87dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41426
37797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.4142637797
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1401367011
Short name T3191
Test name
Test status
Simulation time 143898227 ps
CPU time 0.88 seconds
Started Aug 13 06:37:55 PM PDT 24
Finished Aug 13 06:37:56 PM PDT 24
Peak memory 207592 kb
Host smart-4c608f42-7744-417b-9183-84d97c93c2a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14013
67011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1401367011
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.474116296
Short name T1696
Test name
Test status
Simulation time 156630553 ps
CPU time 0.85 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207564 kb
Host smart-f09fbad4-4296-4158-a802-85429d43c985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47411
6296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.474116296
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.354778846
Short name T1676
Test name
Test status
Simulation time 314721521 ps
CPU time 1.14 seconds
Started Aug 13 06:38:10 PM PDT 24
Finished Aug 13 06:38:11 PM PDT 24
Peak memory 207472 kb
Host smart-dcec408f-daa4-4485-adbb-fca1d0cd4028
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=354778846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.354778846
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.777694092
Short name T3432
Test name
Test status
Simulation time 189151004 ps
CPU time 0.9 seconds
Started Aug 13 06:38:03 PM PDT 24
Finished Aug 13 06:38:04 PM PDT 24
Peak memory 207460 kb
Host smart-5ea73fd5-d6e6-41f3-bdba-fa2d1eb27822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77769
4092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.777694092
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1135124297
Short name T1250
Test name
Test status
Simulation time 40583635 ps
CPU time 0.69 seconds
Started Aug 13 06:37:56 PM PDT 24
Finished Aug 13 06:37:56 PM PDT 24
Peak memory 207552 kb
Host smart-0775352e-bff3-47cc-95c3-5ef6149708d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
24297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1135124297
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2515010277
Short name T2702
Test name
Test status
Simulation time 12795007979 ps
CPU time 31.75 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:34 PM PDT 24
Peak memory 216000 kb
Host smart-439ab6a1-8bc4-4e87-b15c-9affe51a2a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25150
10277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2515010277
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.223206353
Short name T2712
Test name
Test status
Simulation time 172808080 ps
CPU time 0.9 seconds
Started Aug 13 06:38:06 PM PDT 24
Finished Aug 13 06:38:07 PM PDT 24
Peak memory 207588 kb
Host smart-421b059b-a103-46bc-89b4-e04dd43beac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22320
6353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.223206353
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1552054722
Short name T1518
Test name
Test status
Simulation time 215193821 ps
CPU time 0.95 seconds
Started Aug 13 06:38:04 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 207492 kb
Host smart-7538b032-8e43-4b8e-a088-13d8c5ae2bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15520
54722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1552054722
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2265375598
Short name T1146
Test name
Test status
Simulation time 237525939 ps
CPU time 1.05 seconds
Started Aug 13 06:38:10 PM PDT 24
Finished Aug 13 06:38:11 PM PDT 24
Peak memory 207396 kb
Host smart-557016aa-810b-485c-bbb3-d28633913b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22653
75598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2265375598
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1618075802
Short name T846
Test name
Test status
Simulation time 185377285 ps
CPU time 0.92 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207520 kb
Host smart-3af5aa47-2706-434b-83ae-7ccc47d078ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16180
75802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1618075802
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3544331121
Short name T947
Test name
Test status
Simulation time 233327424 ps
CPU time 0.98 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207544 kb
Host smart-c5df5058-80c6-4ed2-87ef-fb296752df12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35443
31121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3544331121
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_rx_full.566003677
Short name T44
Test name
Test status
Simulation time 353134156 ps
CPU time 1.2 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207512 kb
Host smart-4b16b1b7-fd39-4ee1-8a9d-bb93a4cdcfc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56600
3677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.566003677
Directory /workspace/29.usbdev_rx_full/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1335566644
Short name T1598
Test name
Test status
Simulation time 177587916 ps
CPU time 0.88 seconds
Started Aug 13 06:38:01 PM PDT 24
Finished Aug 13 06:38:02 PM PDT 24
Peak memory 207540 kb
Host smart-9a63b5bc-dd58-4311-b645-b0bc64350967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13355
66644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1335566644
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1096465631
Short name T2435
Test name
Test status
Simulation time 193943561 ps
CPU time 0.92 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207528 kb
Host smart-9d44957d-fe10-49c9-b1be-f5b37277b84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10964
65631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1096465631
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2238006069
Short name T2421
Test name
Test status
Simulation time 226993418 ps
CPU time 1.1 seconds
Started Aug 13 06:38:06 PM PDT 24
Finished Aug 13 06:38:07 PM PDT 24
Peak memory 207504 kb
Host smart-898564d7-f8ed-49a5-8250-60ee01ee696b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22380
06069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2238006069
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.1017266414
Short name T2425
Test name
Test status
Simulation time 2628041091 ps
CPU time 20.97 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:43 PM PDT 24
Peak memory 218004 kb
Host smart-175c0c12-656f-4513-9871-8a7ae68ec2f6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1017266414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.1017266414
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1982151998
Short name T1952
Test name
Test status
Simulation time 156616891 ps
CPU time 0.91 seconds
Started Aug 13 06:38:05 PM PDT 24
Finished Aug 13 06:38:06 PM PDT 24
Peak memory 207436 kb
Host smart-778ae25c-897b-42fd-9dce-752af144eaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19821
51998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1982151998
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2130522419
Short name T1687
Test name
Test status
Simulation time 165390136 ps
CPU time 0.89 seconds
Started Aug 13 06:38:01 PM PDT 24
Finished Aug 13 06:38:02 PM PDT 24
Peak memory 207616 kb
Host smart-0eeef2a4-3617-415d-861e-90ac4081012e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21305
22419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2130522419
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1364489924
Short name T664
Test name
Test status
Simulation time 960380368 ps
CPU time 2.4 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:09 PM PDT 24
Peak memory 207660 kb
Host smart-c95a42ae-ffcb-4b33-9494-6eceb2577c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13644
89924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1364489924
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3891284845
Short name T1669
Test name
Test status
Simulation time 2668890733 ps
CPU time 76.14 seconds
Started Aug 13 06:38:08 PM PDT 24
Finished Aug 13 06:39:24 PM PDT 24
Peak memory 224168 kb
Host smart-aa2e2284-dfda-4c9f-968a-86d5618e5d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38912
84845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3891284845
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.3170422375
Short name T3362
Test name
Test status
Simulation time 6127509503 ps
CPU time 42.11 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:49 PM PDT 24
Peak memory 207892 kb
Host smart-eeb2b432-14a0-42d6-a25e-56b18257ab5a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170422375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.3170422375
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_tx_rx_disruption.3094045178
Short name T1178
Test name
Test status
Simulation time 582578182 ps
CPU time 1.61 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:09 PM PDT 24
Peak memory 207592 kb
Host smart-9d112f9e-80f3-4dc9-923b-1f9bfab13c3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094045178 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.usbdev_tx_rx_disruption.3094045178
Directory /workspace/29.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/290.usbdev_tx_rx_disruption.3450647435
Short name T1251
Test name
Test status
Simulation time 432457122 ps
CPU time 1.31 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207556 kb
Host smart-7dd834f9-20c8-4ee0-90e5-37fd5301fc93
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450647435 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.usbdev_tx_rx_disruption.3450647435
Directory /workspace/290.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/291.usbdev_tx_rx_disruption.2595428295
Short name T2075
Test name
Test status
Simulation time 553736159 ps
CPU time 1.57 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207572 kb
Host smart-9e67e831-d1e3-4ce7-9c05-8dc6e75b8edf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595428295 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.usbdev_tx_rx_disruption.2595428295
Directory /workspace/291.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/292.usbdev_tx_rx_disruption.3390756953
Short name T3373
Test name
Test status
Simulation time 585110422 ps
CPU time 1.66 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207616 kb
Host smart-9d457f46-942e-429d-b728-35bee8804a87
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390756953 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.usbdev_tx_rx_disruption.3390756953
Directory /workspace/292.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/293.usbdev_tx_rx_disruption.211175394
Short name T3114
Test name
Test status
Simulation time 498080009 ps
CPU time 1.59 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207472 kb
Host smart-09f8b6f6-37f5-4c3d-ae3d-058a2f11d92d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211175394 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 293.usbdev_tx_rx_disruption.211175394
Directory /workspace/293.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/294.usbdev_tx_rx_disruption.4120567998
Short name T2521
Test name
Test status
Simulation time 467219542 ps
CPU time 1.54 seconds
Started Aug 13 06:42:28 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 207612 kb
Host smart-d9999f0a-1ffc-4ce3-951c-da5f5ed24be2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120567998 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.usbdev_tx_rx_disruption.4120567998
Directory /workspace/294.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/295.usbdev_tx_rx_disruption.240399224
Short name T1744
Test name
Test status
Simulation time 402081471 ps
CPU time 1.39 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:59 PM PDT 24
Peak memory 207588 kb
Host smart-7f19b0c2-8bf5-4721-86ac-8609e947f953
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240399224 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 295.usbdev_tx_rx_disruption.240399224
Directory /workspace/295.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/296.usbdev_tx_rx_disruption.1892627410
Short name T2428
Test name
Test status
Simulation time 514125377 ps
CPU time 1.86 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207556 kb
Host smart-7d454f7f-032b-446f-8904-7900665721af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892627410 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.usbdev_tx_rx_disruption.1892627410
Directory /workspace/296.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/297.usbdev_tx_rx_disruption.1141813639
Short name T634
Test name
Test status
Simulation time 429047138 ps
CPU time 1.36 seconds
Started Aug 13 06:42:11 PM PDT 24
Finished Aug 13 06:42:12 PM PDT 24
Peak memory 207612 kb
Host smart-869e941d-f297-4909-8cb6-41acba0c837a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141813639 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.usbdev_tx_rx_disruption.1141813639
Directory /workspace/297.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/298.usbdev_tx_rx_disruption.450144533
Short name T1564
Test name
Test status
Simulation time 610939249 ps
CPU time 1.59 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207624 kb
Host smart-99494f52-5aa5-4967-9349-01333c8c7232
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450144533 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 298.usbdev_tx_rx_disruption.450144533
Directory /workspace/298.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/299.usbdev_tx_rx_disruption.2869070261
Short name T2662
Test name
Test status
Simulation time 491520102 ps
CPU time 1.5 seconds
Started Aug 13 06:42:20 PM PDT 24
Finished Aug 13 06:42:22 PM PDT 24
Peak memory 207476 kb
Host smart-7721a769-2ab1-4d89-9750-f3f2037ef8a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869070261 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.usbdev_tx_rx_disruption.2869070261
Directory /workspace/299.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.1639194123
Short name T3530
Test name
Test status
Simulation time 32794720 ps
CPU time 0.69 seconds
Started Aug 13 06:33:52 PM PDT 24
Finished Aug 13 06:33:53 PM PDT 24
Peak memory 207424 kb
Host smart-6f722925-8ae6-4ac5-9fe6-5a4103dce7d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1639194123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1639194123
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3468095073
Short name T2515
Test name
Test status
Simulation time 4677373574 ps
CPU time 6.29 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:49 PM PDT 24
Peak memory 215608 kb
Host smart-1423f0a3-0ceb-492a-9ef9-12317a473912
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468095073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.3468095073
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2177076204
Short name T1111
Test name
Test status
Simulation time 19652895133 ps
CPU time 24.47 seconds
Started Aug 13 06:33:39 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207840 kb
Host smart-494c5c6a-a733-4096-8d7d-d593039a4059
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177076204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2177076204
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1226987121
Short name T1577
Test name
Test status
Simulation time 29150130982 ps
CPU time 38.45 seconds
Started Aug 13 06:33:36 PM PDT 24
Finished Aug 13 06:34:15 PM PDT 24
Peak memory 207832 kb
Host smart-7603ebf4-2e79-40f1-beda-15c70cf9fbea
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226987121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.1226987121
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2756177135
Short name T1503
Test name
Test status
Simulation time 153231748 ps
CPU time 0.89 seconds
Started Aug 13 06:33:35 PM PDT 24
Finished Aug 13 06:33:36 PM PDT 24
Peak memory 207424 kb
Host smart-2e00316e-a72a-4bbe-897b-52f281725eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27561
77135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2756177135
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1442820
Short name T3014
Test name
Test status
Simulation time 176022638 ps
CPU time 0.89 seconds
Started Aug 13 06:33:35 PM PDT 24
Finished Aug 13 06:33:36 PM PDT 24
Peak memory 207500 kb
Host smart-73bc1674-ba5a-445c-839d-91632cdb4a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14428
20 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1442820
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2430466411
Short name T89
Test name
Test status
Simulation time 217550407 ps
CPU time 0.92 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 207100 kb
Host smart-63490a02-7dce-4741-97f7-1c6ca6a9c212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24304
66411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2430466411
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3919563741
Short name T547
Test name
Test status
Simulation time 140840056 ps
CPU time 0.81 seconds
Started Aug 13 06:33:35 PM PDT 24
Finished Aug 13 06:33:36 PM PDT 24
Peak memory 207608 kb
Host smart-c35616d2-9c6f-428e-b9c1-1a78ffb856f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39195
63741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3919563741
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.38218092
Short name T978
Test name
Test status
Simulation time 234967011 ps
CPU time 1.03 seconds
Started Aug 13 06:33:37 PM PDT 24
Finished Aug 13 06:33:38 PM PDT 24
Peak memory 207468 kb
Host smart-ba7844d0-c1f1-42af-b255-eace6f6cfc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38218
092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.38218092
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.4227792817
Short name T2805
Test name
Test status
Simulation time 747821976 ps
CPU time 2.35 seconds
Started Aug 13 06:33:35 PM PDT 24
Finished Aug 13 06:33:38 PM PDT 24
Peak memory 207508 kb
Host smart-b6d72636-8476-4479-a7fc-e5046f6ceaa7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4227792817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.4227792817
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.4171084047
Short name T1743
Test name
Test status
Simulation time 42986470763 ps
CPU time 75.51 seconds
Started Aug 13 06:33:38 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 207844 kb
Host smart-bbd08b11-913a-493f-a6e3-c4e215870f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41710
84047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.4171084047
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.2734037892
Short name T847
Test name
Test status
Simulation time 940017656 ps
CPU time 18.87 seconds
Started Aug 13 06:33:36 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 207772 kb
Host smart-d6bde80b-663f-4b06-9c84-014306afe14b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734037892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.2734037892
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3629086479
Short name T2637
Test name
Test status
Simulation time 839161441 ps
CPU time 1.98 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 207484 kb
Host smart-45dface0-8ecf-439a-a860-f5697768f9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36290
86479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3629086479
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1310764434
Short name T3585
Test name
Test status
Simulation time 138777204 ps
CPU time 0.79 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 207484 kb
Host smart-22c29e4d-d687-4970-9017-04f4263463d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13107
64434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1310764434
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.246712564
Short name T3116
Test name
Test status
Simulation time 48362016 ps
CPU time 0.75 seconds
Started Aug 13 06:33:38 PM PDT 24
Finished Aug 13 06:33:39 PM PDT 24
Peak memory 207488 kb
Host smart-d5ac10c7-d963-4d6b-957b-396cf0638b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24671
2564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.246712564
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.4199957949
Short name T3056
Test name
Test status
Simulation time 714957196 ps
CPU time 2.19 seconds
Started Aug 13 06:33:39 PM PDT 24
Finished Aug 13 06:33:41 PM PDT 24
Peak memory 207828 kb
Host smart-f4af6a68-76dc-43f1-bed9-7a244ba0d794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41999
57949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.4199957949
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_types.2959479043
Short name T409
Test name
Test status
Simulation time 284395899 ps
CPU time 1.05 seconds
Started Aug 13 06:33:36 PM PDT 24
Finished Aug 13 06:33:37 PM PDT 24
Peak memory 207544 kb
Host smart-eb0b96e3-ab39-4a9a-a28d-4269bb70e952
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2959479043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.2959479043
Directory /workspace/3.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3216498498
Short name T2216
Test name
Test status
Simulation time 190737044 ps
CPU time 2.53 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 207620 kb
Host smart-d257838a-41a3-450a-be79-49898e73feaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32164
98498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3216498498
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.2936249955
Short name T2036
Test name
Test status
Simulation time 102183721897 ps
CPU time 198.2 seconds
Started Aug 13 06:33:37 PM PDT 24
Finished Aug 13 06:36:56 PM PDT 24
Peak memory 207752 kb
Host smart-ca924deb-32b8-4cd9-b303-53a53735e9d3
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2936249955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.2936249955
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3203757449
Short name T3507
Test name
Test status
Simulation time 91297579743 ps
CPU time 144.39 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:36:08 PM PDT 24
Peak memory 207776 kb
Host smart-f9f600d3-9b09-4775-9393-0d4995f1bad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203757449 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3203757449
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.86257610
Short name T3517
Test name
Test status
Simulation time 100098353421 ps
CPU time 168.36 seconds
Started Aug 13 06:33:37 PM PDT 24
Finished Aug 13 06:36:26 PM PDT 24
Peak memory 207760 kb
Host smart-5cd4283e-a73b-4b97-928d-52afd2b59993
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=86257610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.86257610
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.1172877684
Short name T2941
Test name
Test status
Simulation time 119203549026 ps
CPU time 182.01 seconds
Started Aug 13 06:33:36 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 207772 kb
Host smart-43c848b7-a3e7-4f8f-9b97-2b202c056b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172877684 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1172877684
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.3919749889
Short name T532
Test name
Test status
Simulation time 102166045882 ps
CPU time 164.48 seconds
Started Aug 13 06:33:39 PM PDT 24
Finished Aug 13 06:36:23 PM PDT 24
Peak memory 207776 kb
Host smart-69f21e69-6e1f-488a-b81f-49e3f1b74d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39197
49889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.3919749889
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1465007927
Short name T673
Test name
Test status
Simulation time 158056523 ps
CPU time 0.97 seconds
Started Aug 13 06:33:38 PM PDT 24
Finished Aug 13 06:33:39 PM PDT 24
Peak memory 207524 kb
Host smart-e5dda3dd-ec19-405d-a965-91cc6f62a865
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1465007927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1465007927
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3682435850
Short name T796
Test name
Test status
Simulation time 155479032 ps
CPU time 0.9 seconds
Started Aug 13 06:33:44 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 207384 kb
Host smart-ad5731dd-1964-4c70-8303-72165e011e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36824
35850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3682435850
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1888160521
Short name T839
Test name
Test status
Simulation time 208428704 ps
CPU time 0.95 seconds
Started Aug 13 06:33:46 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 207512 kb
Host smart-f9cf4376-a4e9-43aa-a882-73bb38564f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18881
60521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1888160521
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.892665817
Short name T838
Test name
Test status
Simulation time 3322501401 ps
CPU time 34.77 seconds
Started Aug 13 06:33:37 PM PDT 24
Finished Aug 13 06:34:12 PM PDT 24
Peak memory 218220 kb
Host smart-205061c6-511b-461c-9c60-8043b9c88507
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=892665817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.892665817
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.2596318935
Short name T2781
Test name
Test status
Simulation time 7826593570 ps
CPU time 83.39 seconds
Started Aug 13 06:33:49 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207840 kb
Host smart-be62873e-4d29-4d68-b9ce-dbf04ef80e53
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2596318935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.2596318935
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.245417599
Short name T666
Test name
Test status
Simulation time 217075014 ps
CPU time 1 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:33:46 PM PDT 24
Peak memory 207472 kb
Host smart-4a53f97c-0533-45cf-ae90-cab3a96231f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24541
7599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.245417599
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1418689968
Short name T937
Test name
Test status
Simulation time 29287925990 ps
CPU time 48.98 seconds
Started Aug 13 06:33:46 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207648 kb
Host smart-f327427a-8099-4c35-a209-935733c1ad5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14186
89968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1418689968
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1295750645
Short name T3433
Test name
Test status
Simulation time 3423879852 ps
CPU time 5.18 seconds
Started Aug 13 06:33:44 PM PDT 24
Finished Aug 13 06:33:49 PM PDT 24
Peak memory 207712 kb
Host smart-65960a21-02a7-4b05-8948-61a20c07b963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12957
50645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1295750645
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2819825055
Short name T520
Test name
Test status
Simulation time 2686749506 ps
CPU time 27.89 seconds
Started Aug 13 06:33:47 PM PDT 24
Finished Aug 13 06:34:15 PM PDT 24
Peak memory 218724 kb
Host smart-3c291ce6-e8f7-4a4e-ba38-6c24e9ecbe6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2819825055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2819825055
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1121737041
Short name T1964
Test name
Test status
Simulation time 1708125211 ps
CPU time 17.28 seconds
Started Aug 13 06:33:48 PM PDT 24
Finished Aug 13 06:34:05 PM PDT 24
Peak memory 216932 kb
Host smart-84a160f0-47b0-4c9d-8fd0-5f1d3601848d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1121737041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1121737041
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1155415340
Short name T1978
Test name
Test status
Simulation time 263643179 ps
CPU time 1 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:33:46 PM PDT 24
Peak memory 207456 kb
Host smart-83136ff0-bb96-4791-b64f-5cfc70fb60f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1155415340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1155415340
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.250582464
Short name T2843
Test name
Test status
Simulation time 193293460 ps
CPU time 0.96 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 207504 kb
Host smart-57b8999b-6bf2-47a6-8b4c-36d1bb9287cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058
2464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.250582464
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.668672326
Short name T1280
Test name
Test status
Simulation time 1798321591 ps
CPU time 18.78 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:34:04 PM PDT 24
Peak memory 223956 kb
Host smart-2bbf4089-36ca-4c0c-86e5-2a0d30b31989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66867
2326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.668672326
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2750358040
Short name T2290
Test name
Test status
Simulation time 2335227704 ps
CPU time 18.91 seconds
Started Aug 13 06:33:48 PM PDT 24
Finished Aug 13 06:34:07 PM PDT 24
Peak memory 224224 kb
Host smart-821ceb33-f01c-42e8-8130-b188003b8f10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2750358040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2750358040
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.1670591069
Short name T879
Test name
Test status
Simulation time 3407632658 ps
CPU time 101.69 seconds
Started Aug 13 06:33:46 PM PDT 24
Finished Aug 13 06:35:28 PM PDT 24
Peak memory 217552 kb
Host smart-eedde422-b0d5-4d84-b4f9-87dab9483bb0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1670591069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.1670591069
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2030425415
Short name T885
Test name
Test status
Simulation time 222090218 ps
CPU time 0.94 seconds
Started Aug 13 06:33:48 PM PDT 24
Finished Aug 13 06:33:49 PM PDT 24
Peak memory 207476 kb
Host smart-8f00cf3d-1c2f-4850-9e1d-18587e4a161d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2030425415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2030425415
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.654796267
Short name T1262
Test name
Test status
Simulation time 136411164 ps
CPU time 0.84 seconds
Started Aug 13 06:33:44 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 207492 kb
Host smart-0f37c1b6-68cc-4e9d-a27c-76a40dfd4c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65479
6267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.654796267
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3518423728
Short name T3020
Test name
Test status
Simulation time 207614450 ps
CPU time 1.01 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 207524 kb
Host smart-7c6743e0-1fa5-41c6-a6ee-6e3020192e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35184
23728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3518423728
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.1943042730
Short name T3570
Test name
Test status
Simulation time 160565480 ps
CPU time 0.87 seconds
Started Aug 13 06:33:47 PM PDT 24
Finished Aug 13 06:33:48 PM PDT 24
Peak memory 207456 kb
Host smart-37f71415-85b3-4b12-8019-fab81742dde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19430
42730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1943042730
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.407001318
Short name T1547
Test name
Test status
Simulation time 158081382 ps
CPU time 0.88 seconds
Started Aug 13 06:33:44 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 207492 kb
Host smart-57f62e0b-92d8-45d7-876f-82d747cbe3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40700
1318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.407001318
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3082795341
Short name T1713
Test name
Test status
Simulation time 165363940 ps
CPU time 0.9 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:33:46 PM PDT 24
Peak memory 207604 kb
Host smart-672e91af-4ba2-4579-aa53-8f3f5f7677a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30827
95341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3082795341
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.4116090075
Short name T3519
Test name
Test status
Simulation time 164465624 ps
CPU time 0.87 seconds
Started Aug 13 06:33:43 PM PDT 24
Finished Aug 13 06:33:44 PM PDT 24
Peak memory 207508 kb
Host smart-c453050a-b8b0-4fe2-921e-b6e67d2b24df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41160
90075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.4116090075
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.510731404
Short name T3401
Test name
Test status
Simulation time 212542920 ps
CPU time 0.99 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:33:46 PM PDT 24
Peak memory 207560 kb
Host smart-e52b2ade-f446-44ce-a738-d3372aa11140
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=510731404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.510731404
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3898831565
Short name T1166
Test name
Test status
Simulation time 195992873 ps
CPU time 0.97 seconds
Started Aug 13 06:33:47 PM PDT 24
Finished Aug 13 06:33:48 PM PDT 24
Peak memory 207520 kb
Host smart-fb1eb0f8-07b1-4f0f-b790-49d5c3a18016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38988
31565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3898831565
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2673967716
Short name T3117
Test name
Test status
Simulation time 140563265 ps
CPU time 0.81 seconds
Started Aug 13 06:33:44 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 207508 kb
Host smart-f5a25115-ad84-411c-addf-cfb1656320fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26739
67716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2673967716
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2062638081
Short name T2960
Test name
Test status
Simulation time 85877609 ps
CPU time 0.76 seconds
Started Aug 13 06:33:46 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 207464 kb
Host smart-47b81495-e534-4f56-a719-d819be20afaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20626
38081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2062638081
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2880449344
Short name T2524
Test name
Test status
Simulation time 20159026024 ps
CPU time 56.68 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 220612 kb
Host smart-4997aab8-d8a1-4e0a-9f4c-3adb37ba16b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28804
49344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2880449344
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3348917554
Short name T3354
Test name
Test status
Simulation time 162140750 ps
CPU time 0.95 seconds
Started Aug 13 06:33:47 PM PDT 24
Finished Aug 13 06:33:48 PM PDT 24
Peak memory 207552 kb
Host smart-894455f9-cbe3-48cd-9532-b11046dc50ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33489
17554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3348917554
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1309373528
Short name T3091
Test name
Test status
Simulation time 167518986 ps
CPU time 0.9 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 207424 kb
Host smart-519b45ac-91ce-479d-97f4-63999d0c3948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13093
73528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1309373528
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2788130523
Short name T745
Test name
Test status
Simulation time 6277602737 ps
CPU time 28.77 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:34:14 PM PDT 24
Peak memory 219236 kb
Host smart-45aba286-b5ea-4bed-a0f0-cfc0864c1c36
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2788130523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2788130523
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2237660629
Short name T2533
Test name
Test status
Simulation time 5002939453 ps
CPU time 21.87 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:34:07 PM PDT 24
Peak memory 219532 kb
Host smart-703df15c-d98b-4363-8a3d-c5289348d8a3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237660629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2237660629
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3195181691
Short name T2047
Test name
Test status
Simulation time 197611836 ps
CPU time 0.92 seconds
Started Aug 13 06:33:49 PM PDT 24
Finished Aug 13 06:33:50 PM PDT 24
Peak memory 207452 kb
Host smart-3fe314e0-c04c-444b-b5f0-302c99a809eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31951
81691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3195181691
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.368410272
Short name T1436
Test name
Test status
Simulation time 161428721 ps
CPU time 0.96 seconds
Started Aug 13 06:33:51 PM PDT 24
Finished Aug 13 06:33:52 PM PDT 24
Peak memory 207456 kb
Host smart-a1400e05-477b-4651-bbee-f3de9dc7b6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36841
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.368410272
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_resume_link_active.2823441655
Short name T1351
Test name
Test status
Simulation time 20166860742 ps
CPU time 26.84 seconds
Started Aug 13 06:33:51 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 207552 kb
Host smart-9b7c2cc7-528c-4c09-bdf4-0d2856173605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28234
41655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.2823441655
Directory /workspace/3.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2488363228
Short name T2136
Test name
Test status
Simulation time 162209900 ps
CPU time 0.86 seconds
Started Aug 13 06:33:46 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 207476 kb
Host smart-c39adf62-4ee8-4722-93dd-5ef4d332b148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24883
63228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2488363228
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_full.3398701839
Short name T1391
Test name
Test status
Simulation time 330891544 ps
CPU time 1.2 seconds
Started Aug 13 06:33:49 PM PDT 24
Finished Aug 13 06:33:51 PM PDT 24
Peak memory 207444 kb
Host smart-91c6ad4a-7cec-4923-a8de-3be28f681e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33987
01839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.3398701839
Directory /workspace/3.usbdev_rx_full/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2402976483
Short name T73
Test name
Test status
Simulation time 211571717 ps
CPU time 0.9 seconds
Started Aug 13 06:33:47 PM PDT 24
Finished Aug 13 06:33:48 PM PDT 24
Peak memory 207536 kb
Host smart-82bbf26e-fe17-47d3-9bc5-eb4cb8e6f666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029
76483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2402976483
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1713397339
Short name T250
Test name
Test status
Simulation time 245877785 ps
CPU time 1.1 seconds
Started Aug 13 06:33:52 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 223284 kb
Host smart-6c23f924-bcf1-4ecb-9e29-44195529ff6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1713397339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1713397339
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3545558091
Short name T48
Test name
Test status
Simulation time 439735590 ps
CPU time 1.54 seconds
Started Aug 13 06:33:48 PM PDT 24
Finished Aug 13 06:33:50 PM PDT 24
Peak memory 207536 kb
Host smart-80e4fe63-614a-46ea-ba99-611f65cbc043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35455
58091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3545558091
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.4244786233
Short name T2770
Test name
Test status
Simulation time 210245518 ps
CPU time 1.03 seconds
Started Aug 13 06:33:47 PM PDT 24
Finished Aug 13 06:33:48 PM PDT 24
Peak memory 207468 kb
Host smart-cfb0297a-194d-41ae-956a-ba3c5b58ff72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42447
86233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.4244786233
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3090476405
Short name T3267
Test name
Test status
Simulation time 196630389 ps
CPU time 0.85 seconds
Started Aug 13 06:33:47 PM PDT 24
Finished Aug 13 06:33:48 PM PDT 24
Peak memory 207500 kb
Host smart-7d542747-cc37-4124-aed3-3e4d30ec78c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30904
76405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3090476405
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3310425703
Short name T2661
Test name
Test status
Simulation time 174781221 ps
CPU time 0.95 seconds
Started Aug 13 06:33:46 PM PDT 24
Finished Aug 13 06:33:48 PM PDT 24
Peak memory 207500 kb
Host smart-8413e811-9902-45e5-a5e3-0293797e25e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33104
25703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3310425703
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3382545357
Short name T1853
Test name
Test status
Simulation time 231612255 ps
CPU time 1.11 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 207492 kb
Host smart-1b74d3b7-1233-4da2-8e8d-42218b56d5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33825
45357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3382545357
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3642947796
Short name T1196
Test name
Test status
Simulation time 1843493321 ps
CPU time 19.05 seconds
Started Aug 13 06:33:52 PM PDT 24
Finished Aug 13 06:34:11 PM PDT 24
Peak memory 223996 kb
Host smart-d54c99c7-40ee-4243-bc1e-de7804396044
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3642947796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3642947796
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.25945442
Short name T1322
Test name
Test status
Simulation time 181487185 ps
CPU time 0.92 seconds
Started Aug 13 06:33:45 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 207472 kb
Host smart-9d4990d8-e1d8-43ec-bf6b-5ca17493a9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25945
442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.25945442
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.961529057
Short name T1633
Test name
Test status
Simulation time 172099496 ps
CPU time 0.91 seconds
Started Aug 13 06:33:46 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 207532 kb
Host smart-4df48b91-f2cf-4526-8539-c01390a609ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96152
9057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.961529057
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.1773067812
Short name T3540
Test name
Test status
Simulation time 714914432 ps
CPU time 1.96 seconds
Started Aug 13 06:33:48 PM PDT 24
Finished Aug 13 06:33:50 PM PDT 24
Peak memory 207576 kb
Host smart-a9d7a10c-441b-4108-b55e-64e1f73630bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17730
67812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1773067812
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.127018776
Short name T252
Test name
Test status
Simulation time 2984995312 ps
CPU time 27.45 seconds
Started Aug 13 06:33:47 PM PDT 24
Finished Aug 13 06:34:14 PM PDT 24
Peak memory 216032 kb
Host smart-7fd1ec58-62b8-4da1-9049-c543c65130a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12701
8776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.127018776
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.3452023081
Short name T79
Test name
Test status
Simulation time 6492246442 ps
CPU time 94.55 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:35:27 PM PDT 24
Peak memory 216016 kb
Host smart-9b285e89-70e0-4926-a487-21550405c095
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452023081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3452023081
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.3572264001
Short name T2078
Test name
Test status
Simulation time 1176739960 ps
CPU time 25.28 seconds
Started Aug 13 06:33:38 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207764 kb
Host smart-af7ec678-5b17-4b05-9108-3b47bf89dd98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572264001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.3572264001
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_tx_rx_disruption.3539090666
Short name T2252
Test name
Test status
Simulation time 525982510 ps
CPU time 1.75 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:33:56 PM PDT 24
Peak memory 207616 kb
Host smart-c2c012dc-058b-4fbb-989f-dfd02f30da23
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539090666 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.usbdev_tx_rx_disruption.3539090666
Directory /workspace/3.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.448009988
Short name T1009
Test name
Test status
Simulation time 40414272 ps
CPU time 0.67 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207432 kb
Host smart-a6adfdf2-801a-4474-8888-b3a6bbc3840e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=448009988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.448009988
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.986566437
Short name T1707
Test name
Test status
Simulation time 10501479383 ps
CPU time 13.59 seconds
Started Aug 13 06:38:08 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207800 kb
Host smart-d4002af5-da00-4738-80d6-410c2d0afd60
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986566437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ao
n_wake_disconnect.986566437
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2318007478
Short name T97
Test name
Test status
Simulation time 19962023722 ps
CPU time 23.75 seconds
Started Aug 13 06:38:10 PM PDT 24
Finished Aug 13 06:38:34 PM PDT 24
Peak memory 207756 kb
Host smart-1a53c459-c8d7-4aab-a638-b3c3d57d0c0b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318007478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2318007478
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1495981808
Short name T900
Test name
Test status
Simulation time 24526198990 ps
CPU time 38.55 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:55 PM PDT 24
Peak memory 215976 kb
Host smart-b5dbcab4-4e37-4a1e-b4a0-341cda71f2b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495981808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.1495981808
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3558926970
Short name T874
Test name
Test status
Simulation time 166406397 ps
CPU time 0.92 seconds
Started Aug 13 06:38:05 PM PDT 24
Finished Aug 13 06:38:06 PM PDT 24
Peak memory 207368 kb
Host smart-9f6d81dc-7646-4cb7-b3e4-0d0fa7ae3dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35589
26970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3558926970
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.660972859
Short name T1513
Test name
Test status
Simulation time 187304356 ps
CPU time 0.93 seconds
Started Aug 13 06:38:13 PM PDT 24
Finished Aug 13 06:38:14 PM PDT 24
Peak memory 207572 kb
Host smart-fd09c25d-cf1a-4292-a31d-0f52dd5dd6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66097
2859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.660972859
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.363447478
Short name T2745
Test name
Test status
Simulation time 382374214 ps
CPU time 1.37 seconds
Started Aug 13 06:38:05 PM PDT 24
Finished Aug 13 06:38:07 PM PDT 24
Peak memory 207580 kb
Host smart-d0417aa5-afb6-48ab-b5a2-208d7ce78c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36344
7478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.363447478
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.835265407
Short name T1393
Test name
Test status
Simulation time 455435963 ps
CPU time 1.48 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:09 PM PDT 24
Peak memory 207492 kb
Host smart-ebd292a7-34e7-4967-b28e-f74bb3127a76
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=835265407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.835265407
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3140652692
Short name T2671
Test name
Test status
Simulation time 40038840238 ps
CPU time 62.45 seconds
Started Aug 13 06:38:11 PM PDT 24
Finished Aug 13 06:39:14 PM PDT 24
Peak memory 207812 kb
Host smart-05086f99-9d67-4073-ac20-9e96e83084f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31406
52692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3140652692
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.189174166
Short name T771
Test name
Test status
Simulation time 447583741 ps
CPU time 7.75 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:25 PM PDT 24
Peak memory 207768 kb
Host smart-df1a510d-3e04-48e0-91bf-7f40f9cd4b68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189174166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.189174166
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3258567368
Short name T3468
Test name
Test status
Simulation time 747207138 ps
CPU time 1.76 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:02 PM PDT 24
Peak memory 207540 kb
Host smart-74083113-0dbc-4a63-8ac8-19c3f2ab7068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32585
67368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3258567368
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1063748738
Short name T16
Test name
Test status
Simulation time 188223481 ps
CPU time 0.84 seconds
Started Aug 13 06:38:03 PM PDT 24
Finished Aug 13 06:38:04 PM PDT 24
Peak memory 207680 kb
Host smart-b89219f2-f1ac-44e8-be01-a5bd6d0ac151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10637
48738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1063748738
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2967000760
Short name T1535
Test name
Test status
Simulation time 44241440 ps
CPU time 0.68 seconds
Started Aug 13 06:38:05 PM PDT 24
Finished Aug 13 06:38:06 PM PDT 24
Peak memory 207464 kb
Host smart-510eda3c-658e-48da-92d6-1dbd71629d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29670
00760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2967000760
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.641635041
Short name T1149
Test name
Test status
Simulation time 1001043899 ps
CPU time 2.61 seconds
Started Aug 13 06:38:10 PM PDT 24
Finished Aug 13 06:38:12 PM PDT 24
Peak memory 207792 kb
Host smart-5a9fce1c-fd84-4670-b36a-acee45c86a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64163
5041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.641635041
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_types.2099933160
Short name T487
Test name
Test status
Simulation time 224218372 ps
CPU time 0.99 seconds
Started Aug 13 06:38:19 PM PDT 24
Finished Aug 13 06:38:20 PM PDT 24
Peak memory 207560 kb
Host smart-356adf9f-c742-4b97-9307-8c37c6db2f27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2099933160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.2099933160
Directory /workspace/30.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.4050656483
Short name T1546
Test name
Test status
Simulation time 368123155 ps
CPU time 2.62 seconds
Started Aug 13 06:38:03 PM PDT 24
Finished Aug 13 06:38:06 PM PDT 24
Peak memory 207656 kb
Host smart-63d33800-636a-4bec-b570-94294bdc55be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40506
56483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.4050656483
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1095781470
Short name T1157
Test name
Test status
Simulation time 236732718 ps
CPU time 1.17 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 216956 kb
Host smart-592d1f13-ed24-4bee-a92f-04081eee4cdd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1095781470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1095781470
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3649448518
Short name T2940
Test name
Test status
Simulation time 157369905 ps
CPU time 0.84 seconds
Started Aug 13 06:38:08 PM PDT 24
Finished Aug 13 06:38:09 PM PDT 24
Peak memory 207400 kb
Host smart-f9d64b46-2cdf-4786-9fc5-d64c5d54520b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36494
48518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3649448518
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3740054109
Short name T3509
Test name
Test status
Simulation time 191687764 ps
CPU time 0.94 seconds
Started Aug 13 06:38:13 PM PDT 24
Finished Aug 13 06:38:14 PM PDT 24
Peak memory 207444 kb
Host smart-3e3952d6-d29a-491a-9353-941f9b6f8111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37400
54109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3740054109
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2806787883
Short name T2740
Test name
Test status
Simulation time 2365662133 ps
CPU time 17.48 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 216044 kb
Host smart-d3aca01e-d856-4d39-9349-367f2627a554
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2806787883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2806787883
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.1275675856
Short name T656
Test name
Test status
Simulation time 6917902241 ps
CPU time 50.02 seconds
Started Aug 13 06:38:12 PM PDT 24
Finished Aug 13 06:39:02 PM PDT 24
Peak memory 207708 kb
Host smart-5128b0c4-7ada-4f51-b375-a39d266f9ec1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1275675856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1275675856
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.863136807
Short name T3062
Test name
Test status
Simulation time 157466999 ps
CPU time 0.86 seconds
Started Aug 13 06:38:11 PM PDT 24
Finished Aug 13 06:38:12 PM PDT 24
Peak memory 207536 kb
Host smart-9b4fedd2-358b-4f20-bd99-9178d38513f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86313
6807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.863136807
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.782816940
Short name T255
Test name
Test status
Simulation time 5006075409 ps
CPU time 7.92 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:25 PM PDT 24
Peak memory 207736 kb
Host smart-6f3ec68b-d211-47d1-903a-771330e19b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78281
6940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.782816940
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3928650535
Short name T104
Test name
Test status
Simulation time 5135365802 ps
CPU time 7.37 seconds
Started Aug 13 06:38:18 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207800 kb
Host smart-dc6726cc-6485-46ed-854f-ec31c41c3373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39286
50535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3928650535
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2316469222
Short name T1667
Test name
Test status
Simulation time 4518177658 ps
CPU time 36 seconds
Started Aug 13 06:38:06 PM PDT 24
Finished Aug 13 06:38:42 PM PDT 24
Peak memory 219236 kb
Host smart-507cedcc-5e80-4b97-b4bf-54fc1e5e08fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2316469222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2316469222
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1907770280
Short name T849
Test name
Test status
Simulation time 3352348890 ps
CPU time 91.84 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:39:49 PM PDT 24
Peak memory 217648 kb
Host smart-80ceca02-9e05-4126-949b-a91000ada45f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1907770280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1907770280
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.906345793
Short name T1643
Test name
Test status
Simulation time 247407183 ps
CPU time 1.03 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:03 PM PDT 24
Peak memory 207532 kb
Host smart-c85e6128-6087-4ae1-aa8e-446483edf845
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=906345793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.906345793
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2846082273
Short name T521
Test name
Test status
Simulation time 220529547 ps
CPU time 0.94 seconds
Started Aug 13 06:38:19 PM PDT 24
Finished Aug 13 06:38:20 PM PDT 24
Peak memory 207444 kb
Host smart-6217d522-643b-4c33-a53d-cf11afee21a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28460
82273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2846082273
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2644929239
Short name T1976
Test name
Test status
Simulation time 2903313708 ps
CPU time 80.35 seconds
Started Aug 13 06:38:01 PM PDT 24
Finished Aug 13 06:39:21 PM PDT 24
Peak memory 215884 kb
Host smart-fa41be2b-d966-44e0-95e6-4e4a2a07411f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2644929239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2644929239
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.4220456948
Short name T3209
Test name
Test status
Simulation time 161410535 ps
CPU time 0.92 seconds
Started Aug 13 06:38:01 PM PDT 24
Finished Aug 13 06:38:02 PM PDT 24
Peak memory 207468 kb
Host smart-19f4d3ab-f950-4cb4-8022-6152573b0be4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4220456948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.4220456948
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1263264639
Short name T675
Test name
Test status
Simulation time 167563160 ps
CPU time 0.9 seconds
Started Aug 13 06:38:13 PM PDT 24
Finished Aug 13 06:38:14 PM PDT 24
Peak memory 207520 kb
Host smart-70fcb631-a483-4486-92c4-24dec323902f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12632
64639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1263264639
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3743454883
Short name T3589
Test name
Test status
Simulation time 222508627 ps
CPU time 0.99 seconds
Started Aug 13 06:38:03 PM PDT 24
Finished Aug 13 06:38:04 PM PDT 24
Peak memory 207540 kb
Host smart-f7071e0e-d895-48ae-9fd6-4d78c0fe3ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37434
54883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3743454883
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.2487578282
Short name T2931
Test name
Test status
Simulation time 188488045 ps
CPU time 0.97 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207496 kb
Host smart-75436cbd-d6d9-45df-aefa-dc3235a96c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24875
78282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.2487578282
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.748928541
Short name T1335
Test name
Test status
Simulation time 181420906 ps
CPU time 0.93 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:18 PM PDT 24
Peak memory 207528 kb
Host smart-d34d70a8-1474-4b3f-9942-a6c262459bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74892
8541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.748928541
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1255761807
Short name T3437
Test name
Test status
Simulation time 279863529 ps
CPU time 1.07 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207616 kb
Host smart-86e7e507-be86-4100-82a2-9860c5f37613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12557
61807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1255761807
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.4281895724
Short name T3001
Test name
Test status
Simulation time 148157812 ps
CPU time 0.86 seconds
Started Aug 13 06:38:06 PM PDT 24
Finished Aug 13 06:38:07 PM PDT 24
Peak memory 207468 kb
Host smart-3a994696-4fb3-4f3e-93e3-716a2d28cf9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42818
95724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4281895724
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.677364101
Short name T1188
Test name
Test status
Simulation time 195055838 ps
CPU time 0.95 seconds
Started Aug 13 06:38:04 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 207520 kb
Host smart-657ee903-7da4-405f-88de-05fa5451d85d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=677364101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.677364101
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.103107948
Short name T3067
Test name
Test status
Simulation time 143794672 ps
CPU time 0.82 seconds
Started Aug 13 06:38:12 PM PDT 24
Finished Aug 13 06:38:13 PM PDT 24
Peak memory 207480 kb
Host smart-31b6d616-3e9c-479a-b6b2-5b5f795f9c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10310
7948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.103107948
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3393273301
Short name T3040
Test name
Test status
Simulation time 44877466 ps
CPU time 0.68 seconds
Started Aug 13 06:38:04 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 207576 kb
Host smart-76bdb632-686b-4f4c-b4b6-d9c3b84fec80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33932
73301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3393273301
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3737883176
Short name T1085
Test name
Test status
Simulation time 17805068967 ps
CPU time 48.44 seconds
Started Aug 13 06:38:02 PM PDT 24
Finished Aug 13 06:38:51 PM PDT 24
Peak memory 215984 kb
Host smart-dde365f6-bd63-456f-ae4c-266ba7db8f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37378
83176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3737883176
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1521067176
Short name T1719
Test name
Test status
Simulation time 158962394 ps
CPU time 0.84 seconds
Started Aug 13 06:38:10 PM PDT 24
Finished Aug 13 06:38:11 PM PDT 24
Peak memory 207576 kb
Host smart-7845c452-07c6-491f-bad0-3c0bd086bb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
67176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1521067176
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1475358347
Short name T1427
Test name
Test status
Simulation time 235337137 ps
CPU time 1.03 seconds
Started Aug 13 06:38:04 PM PDT 24
Finished Aug 13 06:38:05 PM PDT 24
Peak memory 207504 kb
Host smart-b57e79ae-4c53-428a-b553-fa1d6d907994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14753
58347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1475358347
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1167813679
Short name T1395
Test name
Test status
Simulation time 304327270 ps
CPU time 1.11 seconds
Started Aug 13 06:38:01 PM PDT 24
Finished Aug 13 06:38:02 PM PDT 24
Peak memory 207516 kb
Host smart-98fb334b-79c5-41eb-8867-4188eaf40d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11678
13679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1167813679
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1239634035
Short name T1727
Test name
Test status
Simulation time 180831368 ps
CPU time 0.88 seconds
Started Aug 13 06:38:18 PM PDT 24
Finished Aug 13 06:38:19 PM PDT 24
Peak memory 207492 kb
Host smart-430b6f3c-b1e9-4a65-9ac0-7cf16993ae65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12396
34035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1239634035
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2922387450
Short name T1582
Test name
Test status
Simulation time 137297504 ps
CPU time 0.84 seconds
Started Aug 13 06:38:09 PM PDT 24
Finished Aug 13 06:38:10 PM PDT 24
Peak memory 207476 kb
Host smart-5316f2f0-20e8-409c-96fa-4540441a9b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29223
87450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2922387450
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_rx_full.2622979039
Short name T2720
Test name
Test status
Simulation time 315676933 ps
CPU time 1.15 seconds
Started Aug 13 06:38:11 PM PDT 24
Finished Aug 13 06:38:12 PM PDT 24
Peak memory 207488 kb
Host smart-9213b0c0-55c5-4e5b-b114-4aa3042c5ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26229
79039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.2622979039
Directory /workspace/30.usbdev_rx_full/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3896219472
Short name T1986
Test name
Test status
Simulation time 155713837 ps
CPU time 0.82 seconds
Started Aug 13 06:38:00 PM PDT 24
Finished Aug 13 06:38:01 PM PDT 24
Peak memory 207496 kb
Host smart-9f1ddc53-dc32-4d40-aa9a-0f57c1066d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38962
19472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3896219472
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1292061714
Short name T3423
Test name
Test status
Simulation time 177004844 ps
CPU time 0.92 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:08 PM PDT 24
Peak memory 207540 kb
Host smart-f7e63c48-c2d0-4018-ac64-d2c97a59393f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12920
61714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1292061714
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2194602654
Short name T3556
Test name
Test status
Simulation time 254879574 ps
CPU time 1.08 seconds
Started Aug 13 06:38:18 PM PDT 24
Finished Aug 13 06:38:19 PM PDT 24
Peak memory 207504 kb
Host smart-7120170b-fd83-41e9-b9a0-a1ffb73917d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21946
02654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2194602654
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2881113298
Short name T2703
Test name
Test status
Simulation time 1972228931 ps
CPU time 13.71 seconds
Started Aug 13 06:38:13 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207632 kb
Host smart-ffab30d0-871d-4cfc-a132-a1447b941423
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2881113298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2881113298
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2585274633
Short name T2937
Test name
Test status
Simulation time 208977131 ps
CPU time 0.93 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:38:17 PM PDT 24
Peak memory 207496 kb
Host smart-6cc61d38-3b57-4ac5-8688-038fb1411483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
74633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2585274633
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1692488055
Short name T3453
Test name
Test status
Simulation time 191598032 ps
CPU time 0.87 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207588 kb
Host smart-df4f8546-346c-4a3b-af42-45947cb9e999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16924
88055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1692488055
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3736178618
Short name T1426
Test name
Test status
Simulation time 615282016 ps
CPU time 1.86 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:19 PM PDT 24
Peak memory 207580 kb
Host smart-f0dc1f2e-2f84-4106-a949-8cea427fbe29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37361
78618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3736178618
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.1533301588
Short name T1437
Test name
Test status
Simulation time 3242121654 ps
CPU time 98.18 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 217724 kb
Host smart-897a867a-ad77-4fd2-8b49-7b8b2e809606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15333
01588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.1533301588
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.1618911417
Short name T608
Test name
Test status
Simulation time 730622557 ps
CPU time 16.05 seconds
Started Aug 13 06:38:10 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207700 kb
Host smart-efe473ef-03e7-40db-8cc2-7389377bbfe5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618911417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.1618911417
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_tx_rx_disruption.1759955125
Short name T75
Test name
Test status
Simulation time 551079965 ps
CPU time 1.7 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:38:17 PM PDT 24
Peak memory 207608 kb
Host smart-5ed3d050-6ec6-4a47-9b1f-a318011d6b58
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759955125 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.usbdev_tx_rx_disruption.1759955125
Directory /workspace/30.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/300.usbdev_tx_rx_disruption.3728778605
Short name T2772
Test name
Test status
Simulation time 463788889 ps
CPU time 1.53 seconds
Started Aug 13 06:41:50 PM PDT 24
Finished Aug 13 06:41:51 PM PDT 24
Peak memory 207600 kb
Host smart-06973719-9aff-4c35-a659-445c73f91ff8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728778605 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 300.usbdev_tx_rx_disruption.3728778605
Directory /workspace/300.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/301.usbdev_tx_rx_disruption.380414069
Short name T1263
Test name
Test status
Simulation time 615221042 ps
CPU time 1.67 seconds
Started Aug 13 06:42:16 PM PDT 24
Finished Aug 13 06:42:17 PM PDT 24
Peak memory 207580 kb
Host smart-55745ad8-70a3-4712-8ff5-99ae54eeaf3e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380414069 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 301.usbdev_tx_rx_disruption.380414069
Directory /workspace/301.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/302.usbdev_tx_rx_disruption.334448378
Short name T2318
Test name
Test status
Simulation time 603738058 ps
CPU time 1.63 seconds
Started Aug 13 06:41:59 PM PDT 24
Finished Aug 13 06:42:01 PM PDT 24
Peak memory 207608 kb
Host smart-8ee7193d-4427-403c-bc79-e8740b45245f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334448378 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 302.usbdev_tx_rx_disruption.334448378
Directory /workspace/302.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/303.usbdev_tx_rx_disruption.2477776376
Short name T1184
Test name
Test status
Simulation time 502237523 ps
CPU time 1.55 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207612 kb
Host smart-86352a87-a579-493d-8296-99e4284e98f5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477776376 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 303.usbdev_tx_rx_disruption.2477776376
Directory /workspace/303.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/304.usbdev_tx_rx_disruption.843821674
Short name T575
Test name
Test status
Simulation time 616162632 ps
CPU time 1.74 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207576 kb
Host smart-f890bb64-bb92-4e75-afcd-02d55194e2ed
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843821674 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 304.usbdev_tx_rx_disruption.843821674
Directory /workspace/304.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/305.usbdev_tx_rx_disruption.1677404745
Short name T2557
Test name
Test status
Simulation time 605807073 ps
CPU time 1.55 seconds
Started Aug 13 06:41:58 PM PDT 24
Finished Aug 13 06:41:59 PM PDT 24
Peak memory 207496 kb
Host smart-34522be1-da86-4163-b1d2-4d801a5e2534
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677404745 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 305.usbdev_tx_rx_disruption.1677404745
Directory /workspace/305.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/306.usbdev_tx_rx_disruption.344559545
Short name T2366
Test name
Test status
Simulation time 472574410 ps
CPU time 1.6 seconds
Started Aug 13 06:42:12 PM PDT 24
Finished Aug 13 06:42:14 PM PDT 24
Peak memory 207476 kb
Host smart-9b0d57ce-1733-4bcc-b711-ef58e1e32524
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344559545 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 306.usbdev_tx_rx_disruption.344559545
Directory /workspace/306.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/307.usbdev_tx_rx_disruption.1064373437
Short name T2481
Test name
Test status
Simulation time 502280494 ps
CPU time 1.56 seconds
Started Aug 13 06:42:06 PM PDT 24
Finished Aug 13 06:42:08 PM PDT 24
Peak memory 207576 kb
Host smart-4f848274-33e3-4617-bacc-3c6b9accaf23
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064373437 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 307.usbdev_tx_rx_disruption.1064373437
Directory /workspace/307.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/308.usbdev_tx_rx_disruption.3420955678
Short name T2842
Test name
Test status
Simulation time 482111429 ps
CPU time 1.57 seconds
Started Aug 13 06:42:14 PM PDT 24
Finished Aug 13 06:42:15 PM PDT 24
Peak memory 207596 kb
Host smart-e62a6f46-b2b6-4306-a1e9-888dab5e378b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420955678 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 308.usbdev_tx_rx_disruption.3420955678
Directory /workspace/308.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/309.usbdev_tx_rx_disruption.612837610
Short name T667
Test name
Test status
Simulation time 465795405 ps
CPU time 1.48 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207544 kb
Host smart-00f8e911-4a93-4567-af42-540d06709873
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612837610 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 309.usbdev_tx_rx_disruption.612837610
Directory /workspace/309.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.4273226976
Short name T1701
Test name
Test status
Simulation time 122483238 ps
CPU time 0.77 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207492 kb
Host smart-b1b296e3-ebcd-4dc6-8415-e593aea711b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4273226976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.4273226976
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.631745501
Short name T615
Test name
Test status
Simulation time 5710757934 ps
CPU time 8.6 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:16 PM PDT 24
Peak memory 215952 kb
Host smart-c1ed5eae-e283-4603-8bae-441eb0dc3a0e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631745501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_ao
n_wake_disconnect.631745501
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3338435003
Short name T2362
Test name
Test status
Simulation time 20806119569 ps
CPU time 25.19 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:47 PM PDT 24
Peak memory 207736 kb
Host smart-080649e9-c24b-47e6-855d-4a418da66d16
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338435003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3338435003
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2729614648
Short name T2380
Test name
Test status
Simulation time 24975706413 ps
CPU time 35.19 seconds
Started Aug 13 06:38:16 PM PDT 24
Finished Aug 13 06:38:51 PM PDT 24
Peak memory 215972 kb
Host smart-61750e74-b4e7-4181-8f40-0a3b57d27f84
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729614648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.2729614648
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2636021598
Short name T2180
Test name
Test status
Simulation time 161209008 ps
CPU time 0.88 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207472 kb
Host smart-a6280555-082a-41f4-84ab-86f7c398f0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26360
21598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2636021598
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.107206151
Short name T3459
Test name
Test status
Simulation time 150476847 ps
CPU time 0.87 seconds
Started Aug 13 06:38:24 PM PDT 24
Finished Aug 13 06:38:29 PM PDT 24
Peak memory 207544 kb
Host smart-424e65da-3fdb-4565-b7ed-0e8ec9b1711c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10720
6151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.107206151
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3884826394
Short name T1119
Test name
Test status
Simulation time 160303696 ps
CPU time 0.81 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207664 kb
Host smart-48fa9f45-72a8-4f8c-9890-4cacd12e1622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38848
26394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3884826394
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2791254290
Short name T2295
Test name
Test status
Simulation time 812706343 ps
CPU time 2.28 seconds
Started Aug 13 06:38:23 PM PDT 24
Finished Aug 13 06:38:25 PM PDT 24
Peak memory 207720 kb
Host smart-2b3db017-551d-4aee-b68a-54cf480b090b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2791254290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2791254290
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1993269431
Short name T3502
Test name
Test status
Simulation time 31078753985 ps
CPU time 53.07 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207832 kb
Host smart-16cfd6d8-acc4-4f3a-a919-cf078882f5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19932
69431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1993269431
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.163045602
Short name T1323
Test name
Test status
Simulation time 845973253 ps
CPU time 18.58 seconds
Started Aug 13 06:38:19 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 207800 kb
Host smart-6daa3cad-1c31-4f04-9070-4be28344e0fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163045602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.163045602
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2471625952
Short name T980
Test name
Test status
Simulation time 906902993 ps
CPU time 2.03 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:24 PM PDT 24
Peak memory 207468 kb
Host smart-774eddf9-f9f0-44ca-8fbd-db5944217f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24716
25952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2471625952
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3400252034
Short name T2878
Test name
Test status
Simulation time 144260435 ps
CPU time 0.84 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:38:15 PM PDT 24
Peak memory 207520 kb
Host smart-910fb922-7932-49c9-a0f9-a9295bdaeac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34002
52034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3400252034
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3736512012
Short name T988
Test name
Test status
Simulation time 37700090 ps
CPU time 0.71 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207356 kb
Host smart-42cfe755-00b6-4e8c-a61b-bf287ea277e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37365
12012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3736512012
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1897886126
Short name T1774
Test name
Test status
Simulation time 995569730 ps
CPU time 2.77 seconds
Started Aug 13 06:38:13 PM PDT 24
Finished Aug 13 06:38:16 PM PDT 24
Peak memory 207780 kb
Host smart-7b6ce9db-b006-4f46-bfe7-3a9c242a55f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18978
86126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1897886126
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.928774440
Short name T1955
Test name
Test status
Simulation time 332607810 ps
CPU time 2.81 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:38:18 PM PDT 24
Peak memory 207596 kb
Host smart-54d658d1-81a3-4e5c-8826-5952f5ce2fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92877
4440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.928774440
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4165852163
Short name T1068
Test name
Test status
Simulation time 216857532 ps
CPU time 1.18 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 215812 kb
Host smart-2cf3d434-fed9-40c9-ba54-1270c03b0ee5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4165852163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4165852163
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.205612623
Short name T578
Test name
Test status
Simulation time 145117369 ps
CPU time 0.88 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:18 PM PDT 24
Peak memory 207480 kb
Host smart-2a0a4785-1b58-4ae1-9259-2786713d44e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20561
2623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.205612623
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1657961393
Short name T2143
Test name
Test status
Simulation time 175667169 ps
CPU time 0.95 seconds
Started Aug 13 06:38:07 PM PDT 24
Finished Aug 13 06:38:08 PM PDT 24
Peak memory 207500 kb
Host smart-f1d8b3db-1c48-4fec-be57-54dcc7a6b4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16579
61393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1657961393
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.1656232219
Short name T1709
Test name
Test status
Simulation time 4253145212 ps
CPU time 34.04 seconds
Started Aug 13 06:38:16 PM PDT 24
Finished Aug 13 06:38:50 PM PDT 24
Peak memory 218332 kb
Host smart-069acc8c-2f60-4b2c-86a0-a3747ebf81e1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1656232219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1656232219
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.1882135702
Short name T1602
Test name
Test status
Simulation time 4949138063 ps
CPU time 33.26 seconds
Started Aug 13 06:38:36 PM PDT 24
Finished Aug 13 06:39:10 PM PDT 24
Peak memory 207688 kb
Host smart-e2a33113-3ee7-477a-bd0f-7b445cab7d1d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1882135702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.1882135702
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1655695561
Short name T2413
Test name
Test status
Simulation time 242657037 ps
CPU time 0.96 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207604 kb
Host smart-c59a4091-b331-4b24-8424-b288f92bee52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16556
95561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1655695561
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3095692090
Short name T2023
Test name
Test status
Simulation time 9444671409 ps
CPU time 12.45 seconds
Started Aug 13 06:38:24 PM PDT 24
Finished Aug 13 06:38:37 PM PDT 24
Peak memory 207780 kb
Host smart-7c3e7159-2323-4c8d-9b80-c923edf45a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30956
92090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3095692090
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1471580873
Short name T2778
Test name
Test status
Simulation time 6015014320 ps
CPU time 8.14 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 216924 kb
Host smart-17525099-e041-4dda-ae91-061b55d1ee2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14715
80873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1471580873
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.221048501
Short name T3153
Test name
Test status
Simulation time 4495472002 ps
CPU time 46.81 seconds
Started Aug 13 06:38:13 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 224148 kb
Host smart-195e2085-be84-4426-aec2-c429787bf431
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=221048501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.221048501
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2598413146
Short name T160
Test name
Test status
Simulation time 2570485397 ps
CPU time 76.41 seconds
Started Aug 13 06:38:16 PM PDT 24
Finished Aug 13 06:39:32 PM PDT 24
Peak memory 215924 kb
Host smart-5458a15e-7f2c-4a6e-9c43-a6f8a93c905b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2598413146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2598413146
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.1448527664
Short name T2353
Test name
Test status
Simulation time 239413412 ps
CPU time 1.05 seconds
Started Aug 13 06:38:12 PM PDT 24
Finished Aug 13 06:38:13 PM PDT 24
Peak memory 207500 kb
Host smart-758a6085-5af9-4cc9-ac91-2cc3619df05f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1448527664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.1448527664
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3581256366
Short name T2431
Test name
Test status
Simulation time 197314336 ps
CPU time 0.94 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:18 PM PDT 24
Peak memory 207432 kb
Host smart-248df58f-2668-40bb-8d04-ed2659ec04e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35812
56366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3581256366
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2636502531
Short name T2445
Test name
Test status
Simulation time 2609342266 ps
CPU time 71.56 seconds
Started Aug 13 06:38:16 PM PDT 24
Finished Aug 13 06:39:28 PM PDT 24
Peak memory 217556 kb
Host smart-d1c6ea6a-2678-4fa6-ac30-9e74aa08cd47
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2636502531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2636502531
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.2541879595
Short name T3516
Test name
Test status
Simulation time 155401995 ps
CPU time 0.85 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207368 kb
Host smart-ceee7085-ce8d-4460-a934-2c4183c6e9c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2541879595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.2541879595
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3698684305
Short name T1446
Test name
Test status
Simulation time 172295712 ps
CPU time 0.88 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:38:16 PM PDT 24
Peak memory 207512 kb
Host smart-fa11b0d0-c2d0-4813-ad10-366299e8a615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36986
84305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3698684305
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2948858057
Short name T141
Test name
Test status
Simulation time 266299064 ps
CPU time 1.03 seconds
Started Aug 13 06:38:11 PM PDT 24
Finished Aug 13 06:38:12 PM PDT 24
Peak memory 207412 kb
Host smart-670a1396-da85-4785-9be6-084cf3155530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29488
58057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2948858057
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2635321082
Short name T989
Test name
Test status
Simulation time 148797338 ps
CPU time 0.85 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207516 kb
Host smart-0e46640a-f87a-4ed0-8067-b08a78edafc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26353
21082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2635321082
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1915438931
Short name T725
Test name
Test status
Simulation time 154016422 ps
CPU time 0.81 seconds
Started Aug 13 06:38:23 PM PDT 24
Finished Aug 13 06:38:24 PM PDT 24
Peak memory 207524 kb
Host smart-5265b892-e653-4ab6-892a-09220adae533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19154
38931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1915438931
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3820713828
Short name T593
Test name
Test status
Simulation time 187219562 ps
CPU time 0.91 seconds
Started Aug 13 06:38:31 PM PDT 24
Finished Aug 13 06:38:32 PM PDT 24
Peak memory 207580 kb
Host smart-08c9f97c-c353-4de5-b359-2586d225339f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38207
13828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3820713828
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3175766446
Short name T2530
Test name
Test status
Simulation time 150109725 ps
CPU time 0.85 seconds
Started Aug 13 06:38:28 PM PDT 24
Finished Aug 13 06:38:29 PM PDT 24
Peak memory 207580 kb
Host smart-910642c2-0680-4bd0-9dbc-2fe11254b83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31757
66446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3175766446
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.423258744
Short name T3163
Test name
Test status
Simulation time 207511181 ps
CPU time 1.02 seconds
Started Aug 13 06:38:36 PM PDT 24
Finished Aug 13 06:38:38 PM PDT 24
Peak memory 207628 kb
Host smart-373f549f-3e94-4278-a92b-13c94433796f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=423258744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.423258744
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3050003958
Short name T2782
Test name
Test status
Simulation time 186753560 ps
CPU time 0.92 seconds
Started Aug 13 06:38:23 PM PDT 24
Finished Aug 13 06:38:24 PM PDT 24
Peak memory 207424 kb
Host smart-45d9e5c5-55ea-4378-9317-a0f234d9b175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
03958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3050003958
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.684074507
Short name T2775
Test name
Test status
Simulation time 29269090 ps
CPU time 0.7 seconds
Started Aug 13 06:38:24 PM PDT 24
Finished Aug 13 06:38:25 PM PDT 24
Peak memory 207500 kb
Host smart-7c84c2c0-ebba-44d1-8c88-5cc08396f849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68407
4507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.684074507
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.302873822
Short name T298
Test name
Test status
Simulation time 15299485193 ps
CPU time 45.9 seconds
Started Aug 13 06:38:27 PM PDT 24
Finished Aug 13 06:39:13 PM PDT 24
Peak memory 224096 kb
Host smart-b118266a-cdce-4745-8805-8e9481058880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30287
3822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.302873822
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3790583231
Short name T3011
Test name
Test status
Simulation time 156796582 ps
CPU time 0.88 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207608 kb
Host smart-b69c07f1-9daa-413c-a648-890b00516b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37905
83231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3790583231
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2786922001
Short name T944
Test name
Test status
Simulation time 246977431 ps
CPU time 0.92 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 207412 kb
Host smart-9cb13a0a-fac0-4229-bc1c-c2f89391b175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27869
22001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2786922001
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3358634471
Short name T3568
Test name
Test status
Simulation time 233074066 ps
CPU time 1.02 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 207528 kb
Host smart-a28dbc54-0d28-4a8f-a9b4-c3921ec7e07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33586
34471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3358634471
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.4079773807
Short name T567
Test name
Test status
Simulation time 180899350 ps
CPU time 0.89 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207492 kb
Host smart-922d03ce-1270-4f4c-b541-0f448b8ae452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40797
73807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.4079773807
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.760387054
Short name T2645
Test name
Test status
Simulation time 144227891 ps
CPU time 0.81 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207456 kb
Host smart-ae70ce2c-8206-4acb-a212-766ac6355728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76038
7054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.760387054
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_rx_full.2575622267
Short name T3447
Test name
Test status
Simulation time 253989262 ps
CPU time 1.11 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:18 PM PDT 24
Peak memory 207440 kb
Host smart-f82eefe1-a247-418a-925d-dc7edc67dd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25756
22267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.2575622267
Directory /workspace/31.usbdev_rx_full/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3066900644
Short name T2903
Test name
Test status
Simulation time 169535166 ps
CPU time 0.85 seconds
Started Aug 13 06:38:19 PM PDT 24
Finished Aug 13 06:38:20 PM PDT 24
Peak memory 207468 kb
Host smart-9dca6a6c-3e8b-49e4-ba0c-8a24a77b6ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30669
00644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3066900644
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1561978295
Short name T662
Test name
Test status
Simulation time 194625186 ps
CPU time 0.94 seconds
Started Aug 13 06:38:23 PM PDT 24
Finished Aug 13 06:38:24 PM PDT 24
Peak memory 207392 kb
Host smart-a4b7fe6d-e9b8-4f05-8b9f-b653b9618e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15619
78295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1561978295
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2106322771
Short name T2536
Test name
Test status
Simulation time 240058565 ps
CPU time 1.02 seconds
Started Aug 13 06:38:29 PM PDT 24
Finished Aug 13 06:38:31 PM PDT 24
Peak memory 207424 kb
Host smart-fc648378-fa2c-4a42-9e89-fbc758d1b056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21063
22771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2106322771
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2336063090
Short name T1173
Test name
Test status
Simulation time 1972940928 ps
CPU time 14.5 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:36 PM PDT 24
Peak memory 223980 kb
Host smart-4e95f713-c645-4c76-9569-49252c4f8c27
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2336063090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2336063090
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.830879769
Short name T2628
Test name
Test status
Simulation time 158330606 ps
CPU time 0.83 seconds
Started Aug 13 06:38:34 PM PDT 24
Finished Aug 13 06:38:35 PM PDT 24
Peak memory 207508 kb
Host smart-27cee863-d359-4437-b924-9c434af72d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83087
9769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.830879769
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2997342241
Short name T1939
Test name
Test status
Simulation time 158722585 ps
CPU time 0.88 seconds
Started Aug 13 06:38:30 PM PDT 24
Finished Aug 13 06:38:31 PM PDT 24
Peak memory 207556 kb
Host smart-c1b741da-64a8-4487-acd7-e02f374b000a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29973
42241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2997342241
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2426774062
Short name T1963
Test name
Test status
Simulation time 1402874621 ps
CPU time 3.31 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207732 kb
Host smart-1d111682-692c-41e8-aeb5-774c25404395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24267
74062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2426774062
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.4273544600
Short name T2716
Test name
Test status
Simulation time 2183379683 ps
CPU time 21.69 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:42 PM PDT 24
Peak memory 216792 kb
Host smart-6800c264-1f64-494e-ad12-84df856b7a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42735
44600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.4273544600
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.2807090871
Short name T1362
Test name
Test status
Simulation time 2885132222 ps
CPU time 18.52 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 207732 kb
Host smart-1233734a-e9c3-4746-8ea1-bd12d1b08208
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807090871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.2807090871
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_tx_rx_disruption.1113849342
Short name T3452
Test name
Test status
Simulation time 592448539 ps
CPU time 1.79 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207544 kb
Host smart-d6568169-8787-4c4d-bf4e-31b1f2b230b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113849342 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.usbdev_tx_rx_disruption.1113849342
Directory /workspace/31.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/310.usbdev_tx_rx_disruption.4203602878
Short name T2510
Test name
Test status
Simulation time 622650014 ps
CPU time 1.7 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207576 kb
Host smart-da84e09d-5fd5-4f89-b0b8-14a18496d6f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203602878 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 310.usbdev_tx_rx_disruption.4203602878
Directory /workspace/310.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/311.usbdev_tx_rx_disruption.3466167268
Short name T1421
Test name
Test status
Simulation time 614707636 ps
CPU time 1.74 seconds
Started Aug 13 06:42:06 PM PDT 24
Finished Aug 13 06:42:08 PM PDT 24
Peak memory 207524 kb
Host smart-4b9fcd85-9ab3-4e10-90f4-6b23d7b784f4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466167268 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 311.usbdev_tx_rx_disruption.3466167268
Directory /workspace/311.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/312.usbdev_tx_rx_disruption.480118116
Short name T3577
Test name
Test status
Simulation time 435120486 ps
CPU time 1.62 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207612 kb
Host smart-46fc89f2-05d0-4a48-8b03-da5576334afd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480118116 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 312.usbdev_tx_rx_disruption.480118116
Directory /workspace/312.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/313.usbdev_tx_rx_disruption.318356040
Short name T2578
Test name
Test status
Simulation time 490566394 ps
CPU time 1.45 seconds
Started Aug 13 06:42:12 PM PDT 24
Finished Aug 13 06:42:14 PM PDT 24
Peak memory 207608 kb
Host smart-68fbf59b-77bf-498d-ab57-24bbd1a62ada
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318356040 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 313.usbdev_tx_rx_disruption.318356040
Directory /workspace/313.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/314.usbdev_tx_rx_disruption.1159118028
Short name T1404
Test name
Test status
Simulation time 538171890 ps
CPU time 1.58 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207620 kb
Host smart-6ed64b54-b3b5-4d05-92a9-873712584c7e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159118028 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 314.usbdev_tx_rx_disruption.1159118028
Directory /workspace/314.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/315.usbdev_tx_rx_disruption.3276641475
Short name T1195
Test name
Test status
Simulation time 533743447 ps
CPU time 1.61 seconds
Started Aug 13 06:41:50 PM PDT 24
Finished Aug 13 06:41:52 PM PDT 24
Peak memory 207600 kb
Host smart-0c45c27c-9be9-405d-b446-f68814d280d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276641475 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 315.usbdev_tx_rx_disruption.3276641475
Directory /workspace/315.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/316.usbdev_tx_rx_disruption.2603499584
Short name T1076
Test name
Test status
Simulation time 452338805 ps
CPU time 1.52 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207576 kb
Host smart-9500ab78-a23a-4e6e-be48-50b7aabaffd3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603499584 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 316.usbdev_tx_rx_disruption.2603499584
Directory /workspace/316.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/317.usbdev_tx_rx_disruption.2459348397
Short name T238
Test name
Test status
Simulation time 497487361 ps
CPU time 1.63 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207572 kb
Host smart-e3a94018-3ca7-4f59-8725-00bc5dcb4375
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459348397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 317.usbdev_tx_rx_disruption.2459348397
Directory /workspace/317.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/318.usbdev_tx_rx_disruption.2017475887
Short name T1235
Test name
Test status
Simulation time 658110287 ps
CPU time 1.73 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207612 kb
Host smart-7e64a955-f27b-41a9-98be-12411247f87a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017475887 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 318.usbdev_tx_rx_disruption.2017475887
Directory /workspace/318.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/319.usbdev_tx_rx_disruption.1542134743
Short name T1782
Test name
Test status
Simulation time 505322413 ps
CPU time 1.56 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207592 kb
Host smart-553fb223-c2b2-44d9-9ee5-701216752ca4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542134743 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 319.usbdev_tx_rx_disruption.1542134743
Directory /workspace/319.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1808657483
Short name T1389
Test name
Test status
Simulation time 42810359 ps
CPU time 0.65 seconds
Started Aug 13 06:38:23 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207436 kb
Host smart-caa1ffce-71ab-498f-aa0c-fbef1410932e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1808657483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1808657483
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2319195641
Short name T2476
Test name
Test status
Simulation time 9633728720 ps
CPU time 12.72 seconds
Started Aug 13 06:38:25 PM PDT 24
Finished Aug 13 06:38:38 PM PDT 24
Peak memory 207808 kb
Host smart-01f7a38f-334a-49b5-b54c-554e7cc190b2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319195641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.2319195641
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3675767748
Short name T1080
Test name
Test status
Simulation time 19756475303 ps
CPU time 22.29 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:44 PM PDT 24
Peak memory 207844 kb
Host smart-d7894b60-a1b2-4f42-b624-cca5ddc5ed77
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675767748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3675767748
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1850459698
Short name T2815
Test name
Test status
Simulation time 29949179701 ps
CPU time 43.01 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:39:04 PM PDT 24
Peak memory 207692 kb
Host smart-b3dee46d-463c-454a-8fbe-a643a43ddbd4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850459698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.1850459698
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.421195536
Short name T1041
Test name
Test status
Simulation time 234234853 ps
CPU time 0.96 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207524 kb
Host smart-12d62d4e-a4bf-4e49-80e0-684b387db411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42119
5536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.421195536
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3575400899
Short name T3583
Test name
Test status
Simulation time 149986212 ps
CPU time 0.82 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207520 kb
Host smart-86444af0-4e64-4786-81b8-6ac04b1dcc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35754
00899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3575400899
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.4027480448
Short name T2346
Test name
Test status
Simulation time 344692474 ps
CPU time 1.28 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207572 kb
Host smart-8df9aa6d-de66-4a06-b46d-331a5334495f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40274
80448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.4027480448
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_device_address.1888301689
Short name T2186
Test name
Test status
Simulation time 38629846818 ps
CPU time 57.09 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:39:15 PM PDT 24
Peak memory 207848 kb
Host smart-3706bcbd-1037-457e-a83f-d44d02f46026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18883
01689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.1888301689
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.4152585182
Short name T1760
Test name
Test status
Simulation time 2451354858 ps
CPU time 22.39 seconds
Started Aug 13 06:38:16 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 207888 kb
Host smart-4520b998-b62c-47e5-94d9-d99933891302
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152585182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.4152585182
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2414406884
Short name T2261
Test name
Test status
Simulation time 839623944 ps
CPU time 1.99 seconds
Started Aug 13 06:38:39 PM PDT 24
Finished Aug 13 06:38:41 PM PDT 24
Peak memory 207556 kb
Host smart-b41bb5b7-cc0d-466f-895d-e3d9d0d10987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24144
06884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2414406884
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.29551098
Short name T1857
Test name
Test status
Simulation time 133095707 ps
CPU time 0.82 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207460 kb
Host smart-e2d16517-5603-4736-8f81-7b7dc57efaef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29551
098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.29551098
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.4160691637
Short name T1865
Test name
Test status
Simulation time 42326365 ps
CPU time 0.72 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207480 kb
Host smart-c079bacd-b839-40d5-8c42-516ddbe02c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41606
91637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.4160691637
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3769147514
Short name T2107
Test name
Test status
Simulation time 859501200 ps
CPU time 2.41 seconds
Started Aug 13 06:38:16 PM PDT 24
Finished Aug 13 06:38:19 PM PDT 24
Peak memory 207800 kb
Host smart-ade40fc6-189e-4e50-8f32-8539a81463b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37691
47514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3769147514
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_types.285087616
Short name T3465
Test name
Test status
Simulation time 597336279 ps
CPU time 1.51 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207528 kb
Host smart-f55f5e14-bdbd-4217-849f-b8d0598f5983
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=285087616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.285087616
Directory /workspace/32.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3582301612
Short name T3537
Test name
Test status
Simulation time 193873312 ps
CPU time 1.9 seconds
Started Aug 13 06:38:28 PM PDT 24
Finished Aug 13 06:38:30 PM PDT 24
Peak memory 207656 kb
Host smart-58548c5d-e10c-4937-9c32-723f7be3d5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35823
01612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3582301612
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.989948525
Short name T1755
Test name
Test status
Simulation time 190195797 ps
CPU time 1.04 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 215856 kb
Host smart-f0295edb-421c-4f82-bb76-731d8dbdc558
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=989948525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.989948525
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1033830320
Short name T1520
Test name
Test status
Simulation time 145983903 ps
CPU time 0.82 seconds
Started Aug 13 06:38:24 PM PDT 24
Finished Aug 13 06:38:25 PM PDT 24
Peak memory 207496 kb
Host smart-678409b4-7363-4861-9299-44e9445f482a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10338
30320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1033830320
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.415257726
Short name T2583
Test name
Test status
Simulation time 229127340 ps
CPU time 1.02 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207516 kb
Host smart-98856e4a-9061-4dd0-af58-f9642dbe5249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41525
7726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.415257726
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.1319019302
Short name T3351
Test name
Test status
Simulation time 10191993442 ps
CPU time 65.14 seconds
Started Aug 13 06:38:24 PM PDT 24
Finished Aug 13 06:39:29 PM PDT 24
Peak memory 207816 kb
Host smart-6be35d85-819a-4106-ae3d-14ea6520cbd4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1319019302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.1319019302
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1002100011
Short name T2898
Test name
Test status
Simulation time 187367059 ps
CPU time 0.91 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207468 kb
Host smart-8c18e087-e277-4302-9936-ffc16627b257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10021
00011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1002100011
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3376985322
Short name T1623
Test name
Test status
Simulation time 24272010713 ps
CPU time 47.66 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:39:14 PM PDT 24
Peak memory 216144 kb
Host smart-06a5eabc-723b-4e1c-815c-8e9eb3069d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769
85322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3376985322
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1036776231
Short name T1902
Test name
Test status
Simulation time 10606886607 ps
CPU time 12.33 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:30 PM PDT 24
Peak memory 207860 kb
Host smart-5dc16df3-ab9f-4d8c-8b5d-006175dd594e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10367
76231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1036776231
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3925498301
Short name T1189
Test name
Test status
Simulation time 4574889507 ps
CPU time 43.77 seconds
Started Aug 13 06:38:16 PM PDT 24
Finished Aug 13 06:38:59 PM PDT 24
Peak memory 218572 kb
Host smart-77f371cc-7c85-4600-a2c9-03f9e720dfeb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3925498301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3925498301
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2696122708
Short name T3028
Test name
Test status
Simulation time 3588703045 ps
CPU time 36.32 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:58 PM PDT 24
Peak memory 215876 kb
Host smart-6969ecb5-0cfd-44d8-ae3d-03270c142d80
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2696122708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2696122708
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1248654653
Short name T1297
Test name
Test status
Simulation time 234718560 ps
CPU time 0.97 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 207532 kb
Host smart-f54eb0a7-d440-4022-9f73-67cc06e50e1a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1248654653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1248654653
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.212980586
Short name T2485
Test name
Test status
Simulation time 195315150 ps
CPU time 0.92 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207416 kb
Host smart-ff43cc80-f22d-4d8f-89c8-121fa2f9740e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21298
0586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.212980586
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.18957732
Short name T1207
Test name
Test status
Simulation time 2963810887 ps
CPU time 86.14 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:39:46 PM PDT 24
Peak memory 217716 kb
Host smart-7081f0fe-4629-4250-91be-2e75b3eeea6c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=18957732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.18957732
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3565524428
Short name T1525
Test name
Test status
Simulation time 227561805 ps
CPU time 0.99 seconds
Started Aug 13 06:38:34 PM PDT 24
Finished Aug 13 06:38:35 PM PDT 24
Peak memory 207528 kb
Host smart-c9b814fb-3587-405c-b7a9-5c0c0b84823c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3565524428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3565524428
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1921668319
Short name T3255
Test name
Test status
Simulation time 151371364 ps
CPU time 0.83 seconds
Started Aug 13 06:38:34 PM PDT 24
Finished Aug 13 06:38:35 PM PDT 24
Peak memory 207508 kb
Host smart-c6705fda-14dd-4a8f-9c6c-2a52443b9f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19216
68319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1921668319
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2955555795
Short name T126
Test name
Test status
Simulation time 175436484 ps
CPU time 0.89 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207488 kb
Host smart-848abc91-1775-4d6e-8863-bc39e585d3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29555
55795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2955555795
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.381339563
Short name T1147
Test name
Test status
Simulation time 164081239 ps
CPU time 0.84 seconds
Started Aug 13 06:38:13 PM PDT 24
Finished Aug 13 06:38:14 PM PDT 24
Peak memory 207420 kb
Host smart-93737111-cf81-438c-b283-128edb68cddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38133
9563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.381339563
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3659624287
Short name T1132
Test name
Test status
Simulation time 194476840 ps
CPU time 0.91 seconds
Started Aug 13 06:38:25 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207516 kb
Host smart-51d3fe9b-d1b4-4c98-abab-6eb5e7e95115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36596
24287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3659624287
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3771638509
Short name T1757
Test name
Test status
Simulation time 184975030 ps
CPU time 0.91 seconds
Started Aug 13 06:38:24 PM PDT 24
Finished Aug 13 06:38:25 PM PDT 24
Peak memory 207600 kb
Host smart-0effd947-1f76-4c12-b6cc-2a2a2b0c8a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37716
38509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3771638509
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.4000459868
Short name T1154
Test name
Test status
Simulation time 170525297 ps
CPU time 0.85 seconds
Started Aug 13 06:38:23 PM PDT 24
Finished Aug 13 06:38:24 PM PDT 24
Peak memory 207500 kb
Host smart-04beb045-96bd-4535-b5f8-c497e5f4ffaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40004
59868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.4000459868
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3763391193
Short name T2221
Test name
Test status
Simulation time 169648365 ps
CPU time 0.95 seconds
Started Aug 13 06:38:19 PM PDT 24
Finished Aug 13 06:38:20 PM PDT 24
Peak memory 207580 kb
Host smart-6691189c-6558-4280-acca-2230612365de
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3763391193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3763391193
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.592199671
Short name T2291
Test name
Test status
Simulation time 145149979 ps
CPU time 0.91 seconds
Started Aug 13 06:38:20 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207488 kb
Host smart-cd361c51-13e2-4224-9a16-1f335e3c03bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59219
9671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.592199671
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1150424020
Short name T1548
Test name
Test status
Simulation time 74632266 ps
CPU time 0.73 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207568 kb
Host smart-fa5bbbea-a362-4561-9f9d-ba9c9ecf664b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
24020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1150424020
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2198877137
Short name T3264
Test name
Test status
Simulation time 10515023556 ps
CPU time 29.98 seconds
Started Aug 13 06:38:25 PM PDT 24
Finished Aug 13 06:38:56 PM PDT 24
Peak memory 215988 kb
Host smart-7570e825-4660-4781-880f-4af9c1058a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21988
77137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2198877137
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2967662083
Short name T1835
Test name
Test status
Simulation time 198022371 ps
CPU time 0.89 seconds
Started Aug 13 06:38:29 PM PDT 24
Finished Aug 13 06:38:30 PM PDT 24
Peak memory 207588 kb
Host smart-1fc28277-2469-4ca9-9208-bd9d82d30eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29676
62083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2967662083
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3631136974
Short name T3166
Test name
Test status
Simulation time 210869238 ps
CPU time 1.06 seconds
Started Aug 13 06:38:27 PM PDT 24
Finished Aug 13 06:38:33 PM PDT 24
Peak memory 207452 kb
Host smart-e5a5ade7-6486-42aa-a7d4-8008f56ebabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36311
36974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3631136974
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.25804968
Short name T2642
Test name
Test status
Simulation time 202493402 ps
CPU time 0.93 seconds
Started Aug 13 06:38:19 PM PDT 24
Finished Aug 13 06:38:20 PM PDT 24
Peak memory 207524 kb
Host smart-d4c811b8-7496-4a45-9b64-f2677a6ea9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25804
968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.25804968
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.3357927552
Short name T3427
Test name
Test status
Simulation time 194450794 ps
CPU time 0.93 seconds
Started Aug 13 06:38:31 PM PDT 24
Finished Aug 13 06:38:32 PM PDT 24
Peak memory 207468 kb
Host smart-d5aa2f63-39b8-468b-9b80-c17a5d4c3e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33579
27552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.3357927552
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3539595965
Short name T1649
Test name
Test status
Simulation time 236144524 ps
CPU time 0.93 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:22 PM PDT 24
Peak memory 207476 kb
Host smart-65097709-d9f0-40a5-9b92-4fc80b87a4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35395
95965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3539595965
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_rx_full.1880874308
Short name T1072
Test name
Test status
Simulation time 267678441 ps
CPU time 1.24 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 207504 kb
Host smart-9ad839c0-6092-4e72-b014-f25f630293b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808
74308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.1880874308
Directory /workspace/32.usbdev_rx_full/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3603232950
Short name T811
Test name
Test status
Simulation time 177251029 ps
CPU time 0.9 seconds
Started Aug 13 06:38:37 PM PDT 24
Finished Aug 13 06:38:38 PM PDT 24
Peak memory 207520 kb
Host smart-f962d5a7-d7ac-4f99-91d4-32e35d1a0f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36032
32950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3603232950
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.945348114
Short name T2050
Test name
Test status
Simulation time 157124653 ps
CPU time 0.91 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:24 PM PDT 24
Peak memory 207564 kb
Host smart-53659a07-76a4-4dde-abbe-a2bc3ff427f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94534
8114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.945348114
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.4161597299
Short name T729
Test name
Test status
Simulation time 214354735 ps
CPU time 1.05 seconds
Started Aug 13 06:38:39 PM PDT 24
Finished Aug 13 06:38:40 PM PDT 24
Peak memory 207508 kb
Host smart-990aae63-338a-4d53-a0ae-5d11e39b5e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41615
97299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.4161597299
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.921674342
Short name T1767
Test name
Test status
Simulation time 3185508960 ps
CPU time 32.27 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:53 PM PDT 24
Peak memory 217832 kb
Host smart-9e4916e3-f076-47a0-b8f3-a7ec89b1310b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=921674342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.921674342
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3225420587
Short name T2678
Test name
Test status
Simulation time 184483548 ps
CPU time 0.9 seconds
Started Aug 13 06:38:34 PM PDT 24
Finished Aug 13 06:38:35 PM PDT 24
Peak memory 207480 kb
Host smart-e9124501-5b80-42fa-b29a-e945a4a6dca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32254
20587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3225420587
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1215128053
Short name T1869
Test name
Test status
Simulation time 177821325 ps
CPU time 0.89 seconds
Started Aug 13 06:38:18 PM PDT 24
Finished Aug 13 06:38:19 PM PDT 24
Peak memory 207548 kb
Host smart-7b656f45-0fcd-4991-9e58-cee0849a4944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12151
28053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1215128053
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.3819266208
Short name T1042
Test name
Test status
Simulation time 966809064 ps
CPU time 2.3 seconds
Started Aug 13 06:38:43 PM PDT 24
Finished Aug 13 06:38:45 PM PDT 24
Peak memory 207760 kb
Host smart-310c1c17-a8bc-4caa-8139-f7a57b956b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38192
66208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.3819266208
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2061753036
Short name T3185
Test name
Test status
Simulation time 4022469800 ps
CPU time 119.13 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:40:22 PM PDT 24
Peak memory 217692 kb
Host smart-fb4e51fb-a33a-42fa-bcc9-57c95d93a3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20617
53036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2061753036
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.310222561
Short name T1515
Test name
Test status
Simulation time 2918267363 ps
CPU time 26.27 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:49 PM PDT 24
Peak memory 207756 kb
Host smart-87751510-79ca-4d68-84d9-9f85c0ba924f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310222561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_host
_handshake.310222561
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_tx_rx_disruption.2110819859
Short name T1785
Test name
Test status
Simulation time 656690245 ps
CPU time 1.82 seconds
Started Aug 13 06:38:19 PM PDT 24
Finished Aug 13 06:38:21 PM PDT 24
Peak memory 207604 kb
Host smart-44ae27ff-db8b-449f-af56-d5abb5ac6aa2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110819859 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.usbdev_tx_rx_disruption.2110819859
Directory /workspace/32.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/320.usbdev_tx_rx_disruption.4226666948
Short name T3494
Test name
Test status
Simulation time 658049058 ps
CPU time 1.79 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207616 kb
Host smart-2d178eb4-5a21-4c77-aa84-358c80c9d836
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226666948 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 320.usbdev_tx_rx_disruption.4226666948
Directory /workspace/320.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/321.usbdev_tx_rx_disruption.1916965776
Short name T780
Test name
Test status
Simulation time 616920826 ps
CPU time 1.78 seconds
Started Aug 13 06:42:08 PM PDT 24
Finished Aug 13 06:42:10 PM PDT 24
Peak memory 207592 kb
Host smart-d3a71cf1-648b-44a4-9ace-f82b8c8598b3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916965776 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 321.usbdev_tx_rx_disruption.1916965776
Directory /workspace/321.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/322.usbdev_tx_rx_disruption.2145616359
Short name T1936
Test name
Test status
Simulation time 601652541 ps
CPU time 1.55 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207580 kb
Host smart-87cb3aa0-8f37-4c2b-b725-b4fce2317c5e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145616359 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 322.usbdev_tx_rx_disruption.2145616359
Directory /workspace/322.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/323.usbdev_tx_rx_disruption.4073926447
Short name T1291
Test name
Test status
Simulation time 532878056 ps
CPU time 1.57 seconds
Started Aug 13 06:42:14 PM PDT 24
Finished Aug 13 06:42:15 PM PDT 24
Peak memory 207616 kb
Host smart-f3dba28c-aefe-4300-8c24-db0515ae8be7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073926447 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 323.usbdev_tx_rx_disruption.4073926447
Directory /workspace/323.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/324.usbdev_tx_rx_disruption.3437169073
Short name T3321
Test name
Test status
Simulation time 628429620 ps
CPU time 1.59 seconds
Started Aug 13 06:42:19 PM PDT 24
Finished Aug 13 06:42:21 PM PDT 24
Peak memory 207612 kb
Host smart-7efa06b4-7e71-45a4-af23-658da13c4685
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437169073 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 324.usbdev_tx_rx_disruption.3437169073
Directory /workspace/324.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/325.usbdev_tx_rx_disruption.1201174616
Short name T1580
Test name
Test status
Simulation time 622838608 ps
CPU time 1.82 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207572 kb
Host smart-8499c3f3-a627-4cec-b7b3-d75a9e75e0a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201174616 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 325.usbdev_tx_rx_disruption.1201174616
Directory /workspace/325.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/326.usbdev_tx_rx_disruption.2143355139
Short name T1998
Test name
Test status
Simulation time 498877603 ps
CPU time 1.53 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207576 kb
Host smart-21f74253-c5c8-4288-922c-d2ded977c40c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143355139 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 326.usbdev_tx_rx_disruption.2143355139
Directory /workspace/326.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/327.usbdev_tx_rx_disruption.548101510
Short name T882
Test name
Test status
Simulation time 496190055 ps
CPU time 1.53 seconds
Started Aug 13 06:42:10 PM PDT 24
Finished Aug 13 06:42:11 PM PDT 24
Peak memory 207612 kb
Host smart-3659abd8-78a6-4a92-a0ed-6a8726a659c3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548101510 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 327.usbdev_tx_rx_disruption.548101510
Directory /workspace/327.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/328.usbdev_tx_rx_disruption.3720127506
Short name T335
Test name
Test status
Simulation time 632398125 ps
CPU time 1.61 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:59 PM PDT 24
Peak memory 207584 kb
Host smart-567a8ac9-66c6-492f-8bb0-a81f3d6b74e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720127506 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 328.usbdev_tx_rx_disruption.3720127506
Directory /workspace/328.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/329.usbdev_tx_rx_disruption.351322068
Short name T2354
Test name
Test status
Simulation time 457403781 ps
CPU time 1.46 seconds
Started Aug 13 06:41:51 PM PDT 24
Finished Aug 13 06:41:52 PM PDT 24
Peak memory 207544 kb
Host smart-839e1cdf-446f-4708-8a6a-7c5921570334
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351322068 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 329.usbdev_tx_rx_disruption.351322068
Directory /workspace/329.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.2557119544
Short name T2862
Test name
Test status
Simulation time 95184216 ps
CPU time 0.77 seconds
Started Aug 13 06:38:27 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 207452 kb
Host smart-f9275899-1ecf-4b8a-b43b-a99b19bd53c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2557119544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.2557119544
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.221507006
Short name T2326
Test name
Test status
Simulation time 4382817507 ps
CPU time 6.55 seconds
Started Aug 13 06:38:22 PM PDT 24
Finished Aug 13 06:38:29 PM PDT 24
Peak memory 216044 kb
Host smart-60c90347-59a9-42f0-860f-bc0fcde4c56f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221507006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ao
n_wake_disconnect.221507006
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2559697361
Short name T1644
Test name
Test status
Simulation time 13514674092 ps
CPU time 15.01 seconds
Started Aug 13 06:38:25 PM PDT 24
Finished Aug 13 06:38:40 PM PDT 24
Peak memory 216008 kb
Host smart-41080776-23e3-46a4-864d-5e1285f67264
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559697361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2559697361
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3429064032
Short name T272
Test name
Test status
Simulation time 23566172026 ps
CPU time 28.83 seconds
Started Aug 13 06:38:25 PM PDT 24
Finished Aug 13 06:38:54 PM PDT 24
Peak memory 216032 kb
Host smart-f5928462-7d80-49e6-8b4d-163fff627145
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429064032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.3429064032
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3143794954
Short name T1954
Test name
Test status
Simulation time 206009309 ps
CPU time 0.91 seconds
Started Aug 13 06:38:15 PM PDT 24
Finished Aug 13 06:38:16 PM PDT 24
Peak memory 207484 kb
Host smart-92c762cb-0643-4f7b-968f-095b19a727d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31437
94954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3143794954
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.448461033
Short name T76
Test name
Test status
Simulation time 142580672 ps
CPU time 0.83 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207616 kb
Host smart-4e38c828-ab50-4349-ba66-d862b1b0feaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44846
1033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.448461033
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1115300055
Short name T3218
Test name
Test status
Simulation time 395185590 ps
CPU time 1.41 seconds
Started Aug 13 06:38:16 PM PDT 24
Finished Aug 13 06:38:17 PM PDT 24
Peak memory 207524 kb
Host smart-fcae2334-56d4-4ded-b9ce-657523ae76cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11153
00055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1115300055
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2766124057
Short name T2792
Test name
Test status
Simulation time 561865698 ps
CPU time 1.69 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207464 kb
Host smart-d92687db-d822-40c7-a635-8dc9bcf8d53e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2766124057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2766124057
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.810657382
Short name T940
Test name
Test status
Simulation time 35289981146 ps
CPU time 68.02 seconds
Started Aug 13 06:38:16 PM PDT 24
Finished Aug 13 06:39:24 PM PDT 24
Peak memory 207752 kb
Host smart-f8140d2e-6883-4392-8534-6def30d9db29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81065
7382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.810657382
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.2560993809
Short name T2913
Test name
Test status
Simulation time 3125652637 ps
CPU time 22.02 seconds
Started Aug 13 06:38:17 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 207808 kb
Host smart-d1e7998a-3b4f-432f-a274-b0f423800973
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560993809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.2560993809
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.4162002689
Short name T1440
Test name
Test status
Simulation time 718365119 ps
CPU time 1.76 seconds
Started Aug 13 06:38:32 PM PDT 24
Finished Aug 13 06:38:34 PM PDT 24
Peak memory 207484 kb
Host smart-3bbfffc2-c14d-45ed-b238-44473503b408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41620
02689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.4162002689
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2261187457
Short name T3486
Test name
Test status
Simulation time 135715701 ps
CPU time 0.78 seconds
Started Aug 13 06:38:49 PM PDT 24
Finished Aug 13 06:38:51 PM PDT 24
Peak memory 207568 kb
Host smart-a340cf6f-7a7d-4ec8-8d5e-631152adad2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22611
87457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2261187457
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.498536076
Short name T1514
Test name
Test status
Simulation time 50001186 ps
CPU time 0.72 seconds
Started Aug 13 06:38:29 PM PDT 24
Finished Aug 13 06:38:30 PM PDT 24
Peak memory 207496 kb
Host smart-709e769f-03a4-4ff4-844d-dba0728054ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49853
6076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.498536076
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.4060207217
Short name T548
Test name
Test status
Simulation time 921436227 ps
CPU time 2.43 seconds
Started Aug 13 06:38:27 PM PDT 24
Finished Aug 13 06:38:30 PM PDT 24
Peak memory 207816 kb
Host smart-20a85c04-f561-4b54-a819-c8ae232e4eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40602
07217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.4060207217
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_types.2314583430
Short name T449
Test name
Test status
Simulation time 359826554 ps
CPU time 1.24 seconds
Started Aug 13 06:38:28 PM PDT 24
Finished Aug 13 06:38:29 PM PDT 24
Peak memory 207524 kb
Host smart-74fc20bd-80bf-4d30-9c68-259b95bf3091
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2314583430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.2314583430
Directory /workspace/33.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3579711205
Short name T2962
Test name
Test status
Simulation time 172440033 ps
CPU time 2 seconds
Started Aug 13 06:38:24 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207732 kb
Host smart-3ecee4be-63ab-4e62-bd84-a808b76e8cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35797
11205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3579711205
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3279973872
Short name T1214
Test name
Test status
Simulation time 232585260 ps
CPU time 1 seconds
Started Aug 13 06:38:34 PM PDT 24
Finished Aug 13 06:38:35 PM PDT 24
Peak memory 207636 kb
Host smart-b3362d92-fa93-4750-bb9c-42e3ee8aae85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3279973872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3279973872
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.461164470
Short name T2659
Test name
Test status
Simulation time 176819946 ps
CPU time 0.83 seconds
Started Aug 13 06:38:34 PM PDT 24
Finished Aug 13 06:38:35 PM PDT 24
Peak memory 207512 kb
Host smart-6ac5dfaf-d07b-4b46-85b5-b81fa9ce39f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46116
4470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.461164470
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3886056209
Short name T1588
Test name
Test status
Simulation time 207489044 ps
CPU time 1.03 seconds
Started Aug 13 06:38:28 PM PDT 24
Finished Aug 13 06:38:29 PM PDT 24
Peak memory 207508 kb
Host smart-dad84062-8ab3-4978-ab7d-ca0699073ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38860
56209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3886056209
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1785805684
Short name T805
Test name
Test status
Simulation time 3290411505 ps
CPU time 34.86 seconds
Started Aug 13 06:38:54 PM PDT 24
Finished Aug 13 06:39:29 PM PDT 24
Peak memory 218428 kb
Host smart-9abc2375-c570-45f4-a21b-6f61647cafd3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1785805684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1785805684
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2853022847
Short name T1069
Test name
Test status
Simulation time 6900489539 ps
CPU time 47.79 seconds
Started Aug 13 06:38:29 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207740 kb
Host smart-eaf4c1ea-592c-478a-bef4-fc17c2f07996
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2853022847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2853022847
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3401540165
Short name T3102
Test name
Test status
Simulation time 220991534 ps
CPU time 0.96 seconds
Started Aug 13 06:38:24 PM PDT 24
Finished Aug 13 06:38:25 PM PDT 24
Peak memory 207588 kb
Host smart-af84c274-7743-4e3e-9217-5e21bb7bb918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34015
40165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3401540165
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1095177217
Short name T915
Test name
Test status
Simulation time 9718441743 ps
CPU time 13.47 seconds
Started Aug 13 06:38:34 PM PDT 24
Finished Aug 13 06:38:47 PM PDT 24
Peak memory 207836 kb
Host smart-ead12601-c89d-4994-b786-39244bc78402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10951
77217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1095177217
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3159603965
Short name T99
Test name
Test status
Simulation time 9703951399 ps
CPU time 11.82 seconds
Started Aug 13 06:38:36 PM PDT 24
Finished Aug 13 06:38:48 PM PDT 24
Peak memory 207844 kb
Host smart-427213f8-d248-49e1-87c7-e849b66ecf2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31596
03965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3159603965
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1837808208
Short name T3520
Test name
Test status
Simulation time 2785336589 ps
CPU time 27.22 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:38:53 PM PDT 24
Peak memory 215892 kb
Host smart-fd389d15-2bf9-4120-9e55-cb39196c60a8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1837808208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1837808208
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.410525704
Short name T2762
Test name
Test status
Simulation time 236487939 ps
CPU time 1.04 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:38:46 PM PDT 24
Peak memory 207532 kb
Host smart-d3ae7a85-dbbe-4283-b33d-40116a54b658
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=410525704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.410525704
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.4204989260
Short name T2504
Test name
Test status
Simulation time 189340299 ps
CPU time 0.92 seconds
Started Aug 13 06:38:31 PM PDT 24
Finished Aug 13 06:38:32 PM PDT 24
Peak memory 207500 kb
Host smart-e64602a4-49d9-4acb-9df1-36718fa6ff2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42049
89260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.4204989260
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2127135972
Short name T1373
Test name
Test status
Simulation time 2753492347 ps
CPU time 77.66 seconds
Started Aug 13 06:38:43 PM PDT 24
Finished Aug 13 06:40:01 PM PDT 24
Peak memory 217748 kb
Host smart-d9d59a83-c680-44a4-b79c-d4b1d8d1c399
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2127135972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2127135972
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.1081158259
Short name T3120
Test name
Test status
Simulation time 158724453 ps
CPU time 0.86 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 207432 kb
Host smart-acf49a68-a188-48a4-8119-1ec12694c9a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1081158259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.1081158259
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.748505019
Short name T561
Test name
Test status
Simulation time 145091431 ps
CPU time 0.82 seconds
Started Aug 13 06:38:50 PM PDT 24
Finished Aug 13 06:38:52 PM PDT 24
Peak memory 207524 kb
Host smart-20a9e9ba-2d84-457e-ab02-fe4ff91d7728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74850
5019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.748505019
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2325645989
Short name T2994
Test name
Test status
Simulation time 186361303 ps
CPU time 0.9 seconds
Started Aug 13 06:38:33 PM PDT 24
Finished Aug 13 06:38:34 PM PDT 24
Peak memory 207444 kb
Host smart-fd48c7ef-3d7a-41ee-a924-26ca0bb41b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23256
45989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2325645989
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2610080313
Short name T883
Test name
Test status
Simulation time 165369819 ps
CPU time 0.83 seconds
Started Aug 13 06:38:27 PM PDT 24
Finished Aug 13 06:38:28 PM PDT 24
Peak memory 207488 kb
Host smart-597e12d3-a8dd-45bd-9475-96da2dde4fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26100
80313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2610080313
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3475233489
Short name T1917
Test name
Test status
Simulation time 225007737 ps
CPU time 0.9 seconds
Started Aug 13 06:38:25 PM PDT 24
Finished Aug 13 06:38:26 PM PDT 24
Peak memory 207516 kb
Host smart-b9c9049f-5296-45ff-8ae9-f3536e12809b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34752
33489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3475233489
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3590251906
Short name T1135
Test name
Test status
Simulation time 142260376 ps
CPU time 0.83 seconds
Started Aug 13 06:38:32 PM PDT 24
Finished Aug 13 06:38:33 PM PDT 24
Peak memory 207564 kb
Host smart-73016145-9435-42e5-928c-adfdb209cb7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35902
51906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3590251906
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2700389461
Short name T1611
Test name
Test status
Simulation time 183747218 ps
CPU time 0.89 seconds
Started Aug 13 06:38:34 PM PDT 24
Finished Aug 13 06:38:35 PM PDT 24
Peak memory 207468 kb
Host smart-c3b45924-1dc4-4e67-b69e-aac137a95844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27003
89461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2700389461
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.1542320035
Short name T3538
Test name
Test status
Simulation time 199680454 ps
CPU time 0.96 seconds
Started Aug 13 06:38:43 PM PDT 24
Finished Aug 13 06:38:44 PM PDT 24
Peak memory 207596 kb
Host smart-9504dff3-21c0-46f5-be19-8b66258713b6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1542320035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.1542320035
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3238071239
Short name T2586
Test name
Test status
Simulation time 142469343 ps
CPU time 0.81 seconds
Started Aug 13 06:38:25 PM PDT 24
Finished Aug 13 06:38:25 PM PDT 24
Peak memory 207476 kb
Host smart-94e2f753-24b0-4cb0-8d98-b532f7030207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32380
71239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3238071239
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1123537800
Short name T2082
Test name
Test status
Simulation time 39957722 ps
CPU time 0.78 seconds
Started Aug 13 06:38:39 PM PDT 24
Finished Aug 13 06:38:40 PM PDT 24
Peak memory 207460 kb
Host smart-9f42205a-1c58-43fd-a996-ee0a6a13074c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
37800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1123537800
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.526941923
Short name T3539
Test name
Test status
Simulation time 16905144460 ps
CPU time 42.15 seconds
Started Aug 13 06:38:30 PM PDT 24
Finished Aug 13 06:39:12 PM PDT 24
Peak memory 220424 kb
Host smart-2d7bac47-7c74-44cc-bef4-c9bd9a262013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52694
1923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.526941923
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2104547614
Short name T2138
Test name
Test status
Simulation time 180952064 ps
CPU time 0.95 seconds
Started Aug 13 06:38:31 PM PDT 24
Finished Aug 13 06:38:32 PM PDT 24
Peak memory 207604 kb
Host smart-82acd648-2c1c-454f-8e16-6d24eb0dc81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
47614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2104547614
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2018185714
Short name T1419
Test name
Test status
Simulation time 192656795 ps
CPU time 0.94 seconds
Started Aug 13 06:38:33 PM PDT 24
Finished Aug 13 06:38:34 PM PDT 24
Peak memory 207476 kb
Host smart-c01e025f-1bc1-41ac-bf57-15864d831b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20181
85714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2018185714
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3663228253
Short name T2139
Test name
Test status
Simulation time 246067601 ps
CPU time 0.94 seconds
Started Aug 13 06:38:28 PM PDT 24
Finished Aug 13 06:38:29 PM PDT 24
Peak memory 207460 kb
Host smart-ae64fced-8af3-4f44-81a4-cf78cfeb93f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36632
28253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3663228253
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3328725589
Short name T3060
Test name
Test status
Simulation time 171614694 ps
CPU time 0.92 seconds
Started Aug 13 06:38:41 PM PDT 24
Finished Aug 13 06:38:42 PM PDT 24
Peak memory 207512 kb
Host smart-da1814a1-b117-492d-8207-c961eaa1d446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33287
25589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3328725589
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.3927897024
Short name T1482
Test name
Test status
Simulation time 200432831 ps
CPU time 1.01 seconds
Started Aug 13 06:38:37 PM PDT 24
Finished Aug 13 06:38:38 PM PDT 24
Peak memory 207528 kb
Host smart-843b7591-704b-4662-966d-15a7793f7f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39278
97024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3927897024
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_rx_full.1009616424
Short name T1769
Test name
Test status
Simulation time 311967455 ps
CPU time 1.3 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 207488 kb
Host smart-9974edfc-352e-47ed-adb3-34e1b0f9e1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10096
16424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.1009616424
Directory /workspace/33.usbdev_rx_full/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2617574062
Short name T862
Test name
Test status
Simulation time 188173970 ps
CPU time 1.01 seconds
Started Aug 13 06:38:38 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 207552 kb
Host smart-2567e1f0-3f92-49f8-86dc-06b9db85077f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26175
74062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2617574062
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1481935413
Short name T703
Test name
Test status
Simulation time 149228013 ps
CPU time 0.83 seconds
Started Aug 13 06:38:38 PM PDT 24
Finished Aug 13 06:38:39 PM PDT 24
Peak memory 207408 kb
Host smart-d2201404-4f7e-4814-97ae-ae0a7be274c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14819
35413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1481935413
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3521409200
Short name T1908
Test name
Test status
Simulation time 220074663 ps
CPU time 1.02 seconds
Started Aug 13 06:38:21 PM PDT 24
Finished Aug 13 06:38:23 PM PDT 24
Peak memory 207524 kb
Host smart-c928c603-783f-4b26-af48-34e750b31de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35214
09200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3521409200
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1224676923
Short name T2134
Test name
Test status
Simulation time 2571981514 ps
CPU time 18.84 seconds
Started Aug 13 06:38:50 PM PDT 24
Finished Aug 13 06:39:09 PM PDT 24
Peak memory 224044 kb
Host smart-9604c253-2694-400d-9709-b94d29d2d5a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1224676923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1224676923
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3169426905
Short name T858
Test name
Test status
Simulation time 183952908 ps
CPU time 0.88 seconds
Started Aug 13 06:38:50 PM PDT 24
Finished Aug 13 06:38:51 PM PDT 24
Peak memory 207520 kb
Host smart-0dcf76bb-ca03-4388-8446-4d6754a13eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31694
26905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3169426905
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1241460258
Short name T843
Test name
Test status
Simulation time 249449863 ps
CPU time 0.99 seconds
Started Aug 13 06:38:35 PM PDT 24
Finished Aug 13 06:38:36 PM PDT 24
Peak memory 207552 kb
Host smart-c358eeb0-ccd6-418a-9179-ce4f3eec63ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12414
60258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1241460258
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1686197855
Short name T3444
Test name
Test status
Simulation time 939538087 ps
CPU time 2.36 seconds
Started Aug 13 06:38:32 PM PDT 24
Finished Aug 13 06:38:34 PM PDT 24
Peak memory 207736 kb
Host smart-48f0a5ad-1cf8-4756-93c2-73bcd6eab138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16861
97855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1686197855
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.666731863
Short name T1771
Test name
Test status
Simulation time 3051030955 ps
CPU time 83.99 seconds
Started Aug 13 06:38:27 PM PDT 24
Finished Aug 13 06:39:52 PM PDT 24
Peak memory 216036 kb
Host smart-7f8c9278-95b4-41cc-96b4-de1e5f765c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66673
1863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.666731863
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.1494198981
Short name T3566
Test name
Test status
Simulation time 2035833499 ps
CPU time 17.3 seconds
Started Aug 13 06:38:29 PM PDT 24
Finished Aug 13 06:38:47 PM PDT 24
Peak memory 207628 kb
Host smart-059b4cdc-5e67-43b3-bf7f-5cdb65089645
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494198981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.1494198981
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_tx_rx_disruption.1645950523
Short name T1756
Test name
Test status
Simulation time 432323696 ps
CPU time 1.48 seconds
Started Aug 13 06:38:25 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 207580 kb
Host smart-4dc78b56-d1af-4dc5-8eab-e958e79ecb53
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645950523 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.usbdev_tx_rx_disruption.1645950523
Directory /workspace/33.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/330.usbdev_tx_rx_disruption.1715760883
Short name T2909
Test name
Test status
Simulation time 551238485 ps
CPU time 1.69 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207588 kb
Host smart-d06833fb-08f5-4940-a805-c9d782819f4b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715760883 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 330.usbdev_tx_rx_disruption.1715760883
Directory /workspace/330.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/331.usbdev_tx_rx_disruption.970378774
Short name T708
Test name
Test status
Simulation time 542918429 ps
CPU time 1.51 seconds
Started Aug 13 06:42:03 PM PDT 24
Finished Aug 13 06:42:05 PM PDT 24
Peak memory 207624 kb
Host smart-bb044cab-60f1-453c-9361-1b2495a76970
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970378774 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 331.usbdev_tx_rx_disruption.970378774
Directory /workspace/331.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/332.usbdev_tx_rx_disruption.1521413681
Short name T895
Test name
Test status
Simulation time 506437322 ps
CPU time 1.49 seconds
Started Aug 13 06:41:58 PM PDT 24
Finished Aug 13 06:41:59 PM PDT 24
Peak memory 207496 kb
Host smart-dbc5cba5-fb3c-48ba-a722-a48e5739275d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521413681 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 332.usbdev_tx_rx_disruption.1521413681
Directory /workspace/332.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/333.usbdev_tx_rx_disruption.2166462669
Short name T3347
Test name
Test status
Simulation time 442562199 ps
CPU time 1.61 seconds
Started Aug 13 06:42:06 PM PDT 24
Finished Aug 13 06:42:08 PM PDT 24
Peak memory 207580 kb
Host smart-67851e21-8ffb-4845-a3d7-3a9b3a0c879e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166462669 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 333.usbdev_tx_rx_disruption.2166462669
Directory /workspace/333.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/334.usbdev_tx_rx_disruption.1682103034
Short name T715
Test name
Test status
Simulation time 553760464 ps
CPU time 1.65 seconds
Started Aug 13 06:42:17 PM PDT 24
Finished Aug 13 06:42:18 PM PDT 24
Peak memory 207588 kb
Host smart-30927511-8369-4f69-8758-a98cbe76219e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682103034 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 334.usbdev_tx_rx_disruption.1682103034
Directory /workspace/334.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/335.usbdev_tx_rx_disruption.1259678799
Short name T914
Test name
Test status
Simulation time 512043179 ps
CPU time 1.64 seconds
Started Aug 13 06:41:58 PM PDT 24
Finished Aug 13 06:42:00 PM PDT 24
Peak memory 207504 kb
Host smart-71bb3647-6892-49c2-b67a-e2f408f44694
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259678799 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 335.usbdev_tx_rx_disruption.1259678799
Directory /workspace/335.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/336.usbdev_tx_rx_disruption.4065010716
Short name T2166
Test name
Test status
Simulation time 514445836 ps
CPU time 1.79 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207496 kb
Host smart-09f771fd-20a5-4a0e-abb1-83a9acc0d47d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065010716 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 336.usbdev_tx_rx_disruption.4065010716
Directory /workspace/336.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/337.usbdev_tx_rx_disruption.1438200466
Short name T1717
Test name
Test status
Simulation time 456754776 ps
CPU time 1.53 seconds
Started Aug 13 06:42:31 PM PDT 24
Finished Aug 13 06:42:32 PM PDT 24
Peak memory 207624 kb
Host smart-5c219f84-498b-407f-8050-283ad9e2fec3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438200466 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 337.usbdev_tx_rx_disruption.1438200466
Directory /workspace/337.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/338.usbdev_tx_rx_disruption.541039512
Short name T1357
Test name
Test status
Simulation time 577609068 ps
CPU time 1.57 seconds
Started Aug 13 06:42:15 PM PDT 24
Finished Aug 13 06:42:22 PM PDT 24
Peak memory 207616 kb
Host smart-ca8f0b31-e155-411e-9bce-ccfc5ea4282f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541039512 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 338.usbdev_tx_rx_disruption.541039512
Directory /workspace/338.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/339.usbdev_tx_rx_disruption.2257486793
Short name T2591
Test name
Test status
Simulation time 495527870 ps
CPU time 1.59 seconds
Started Aug 13 06:42:19 PM PDT 24
Finished Aug 13 06:42:21 PM PDT 24
Peak memory 207588 kb
Host smart-2e4dd529-f18e-41e5-a06c-e426129e8318
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257486793 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 339.usbdev_tx_rx_disruption.2257486793
Directory /workspace/339.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3416947919
Short name T2313
Test name
Test status
Simulation time 83803459 ps
CPU time 0.82 seconds
Started Aug 13 06:38:48 PM PDT 24
Finished Aug 13 06:38:49 PM PDT 24
Peak memory 207456 kb
Host smart-47cce173-3278-4bdb-93cb-0f9eeb91e2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3416947919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3416947919
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3498325044
Short name T580
Test name
Test status
Simulation time 10427748108 ps
CPU time 13.28 seconds
Started Aug 13 06:38:38 PM PDT 24
Finished Aug 13 06:38:52 PM PDT 24
Peak memory 207848 kb
Host smart-9755f1fd-8016-4065-95df-2b6c23022f93
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498325044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.3498325044
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1235379749
Short name T597
Test name
Test status
Simulation time 24868689028 ps
CPU time 32.84 seconds
Started Aug 13 06:38:33 PM PDT 24
Finished Aug 13 06:39:06 PM PDT 24
Peak memory 216056 kb
Host smart-cd70f64b-0c24-4702-8683-6a99ffc97da2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235379749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.1235379749
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1983995498
Short name T2152
Test name
Test status
Simulation time 228324562 ps
CPU time 0.97 seconds
Started Aug 13 06:38:37 PM PDT 24
Finished Aug 13 06:38:38 PM PDT 24
Peak memory 207512 kb
Host smart-49d5f7f3-3bc5-4eac-b20f-0a8fa4ed9920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839
95498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1983995498
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1592249984
Short name T2253
Test name
Test status
Simulation time 160012055 ps
CPU time 0.89 seconds
Started Aug 13 06:38:39 PM PDT 24
Finished Aug 13 06:38:40 PM PDT 24
Peak memory 207524 kb
Host smart-1ee75af8-1828-40d0-a9cf-76263180fbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15922
49984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1592249984
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.300160307
Short name T3007
Test name
Test status
Simulation time 413576995 ps
CPU time 1.41 seconds
Started Aug 13 06:38:26 PM PDT 24
Finished Aug 13 06:38:27 PM PDT 24
Peak memory 207572 kb
Host smart-cae5fd52-9b38-42cb-95b7-c848315f833f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30016
0307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.300160307
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3541814127
Short name T3157
Test name
Test status
Simulation time 1097596220 ps
CPU time 2.86 seconds
Started Aug 13 06:38:41 PM PDT 24
Finished Aug 13 06:38:44 PM PDT 24
Peak memory 207708 kb
Host smart-0c08b111-6698-43a2-a1fd-4e25df087554
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3541814127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3541814127
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3778056745
Short name T1224
Test name
Test status
Simulation time 48891216716 ps
CPU time 74.09 seconds
Started Aug 13 06:38:50 PM PDT 24
Finished Aug 13 06:40:04 PM PDT 24
Peak memory 207796 kb
Host smart-12d0c170-9165-4b58-aa69-12bc3f9e5067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37780
56745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3778056745
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.3187029724
Short name T1407
Test name
Test status
Simulation time 2076698950 ps
CPU time 51.88 seconds
Started Aug 13 06:38:44 PM PDT 24
Finished Aug 13 06:39:36 PM PDT 24
Peak memory 207728 kb
Host smart-94f7906a-e224-4c6c-a3da-0573d0c14338
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187029724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.3187029724
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.3373880030
Short name T3083
Test name
Test status
Simulation time 666267682 ps
CPU time 1.97 seconds
Started Aug 13 06:38:35 PM PDT 24
Finished Aug 13 06:38:37 PM PDT 24
Peak memory 207536 kb
Host smart-0c57e4b5-a469-4d55-a118-644843f20fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33738
80030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.3373880030
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1066891545
Short name T2028
Test name
Test status
Simulation time 132172853 ps
CPU time 0.88 seconds
Started Aug 13 06:38:42 PM PDT 24
Finished Aug 13 06:38:43 PM PDT 24
Peak memory 207500 kb
Host smart-37b00f1c-8606-41d9-a86b-67781ae021e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10668
91545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1066891545
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.89665777
Short name T2127
Test name
Test status
Simulation time 33685587 ps
CPU time 0.7 seconds
Started Aug 13 06:38:55 PM PDT 24
Finished Aug 13 06:38:55 PM PDT 24
Peak memory 207500 kb
Host smart-2237e52b-0dec-4a75-ac29-d19f27fab1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89665
777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.89665777
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1687134013
Short name T2367
Test name
Test status
Simulation time 852233152 ps
CPU time 2.3 seconds
Started Aug 13 06:38:54 PM PDT 24
Finished Aug 13 06:38:56 PM PDT 24
Peak memory 207808 kb
Host smart-3b5c722d-c472-4614-b4a0-b9a67efd1d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16871
34013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1687134013
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_types.1767147499
Short name T476
Test name
Test status
Simulation time 164228620 ps
CPU time 0.82 seconds
Started Aug 13 06:38:52 PM PDT 24
Finished Aug 13 06:38:53 PM PDT 24
Peak memory 207492 kb
Host smart-70aaa06c-1ddb-4391-ba60-8aa331393fe4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1767147499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.1767147499
Directory /workspace/34.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2963040285
Short name T1828
Test name
Test status
Simulation time 320059129 ps
CPU time 2.67 seconds
Started Aug 13 06:38:56 PM PDT 24
Finished Aug 13 06:38:58 PM PDT 24
Peak memory 207732 kb
Host smart-beba5a6a-e076-439b-aa5c-5cd02beac5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
40285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2963040285
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3342997391
Short name T1698
Test name
Test status
Simulation time 232343114 ps
CPU time 1.19 seconds
Started Aug 13 06:38:56 PM PDT 24
Finished Aug 13 06:38:57 PM PDT 24
Peak memory 215924 kb
Host smart-39d4276c-60e3-4d52-84fa-ac7937840f71
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3342997391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3342997391
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.378606548
Short name T1241
Test name
Test status
Simulation time 154991701 ps
CPU time 0.83 seconds
Started Aug 13 06:38:43 PM PDT 24
Finished Aug 13 06:38:44 PM PDT 24
Peak memory 207476 kb
Host smart-b907eef0-3569-4840-8cab-1fbf5119dad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37860
6548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.378606548
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3525478353
Short name T3290
Test name
Test status
Simulation time 243678025 ps
CPU time 1.15 seconds
Started Aug 13 06:38:46 PM PDT 24
Finished Aug 13 06:38:48 PM PDT 24
Peak memory 207536 kb
Host smart-4cee1b24-52aa-48d0-ac2f-e69d8b275880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35254
78353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3525478353
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3642658066
Short name T1112
Test name
Test status
Simulation time 5101041493 ps
CPU time 148.15 seconds
Started Aug 13 06:38:58 PM PDT 24
Finished Aug 13 06:41:26 PM PDT 24
Peak memory 218444 kb
Host smart-9a70b54c-1ca5-4531-83bb-5c1116fe6023
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3642658066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3642658066
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.3513458487
Short name T3366
Test name
Test status
Simulation time 6115026004 ps
CPU time 72.03 seconds
Started Aug 13 06:38:46 PM PDT 24
Finished Aug 13 06:39:59 PM PDT 24
Peak memory 207688 kb
Host smart-e730dbb6-1df8-4cf1-8d58-6be8f9b05b20
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3513458487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3513458487
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1049517228
Short name T3125
Test name
Test status
Simulation time 210891267 ps
CPU time 0.97 seconds
Started Aug 13 06:38:39 PM PDT 24
Finished Aug 13 06:38:40 PM PDT 24
Peak memory 207604 kb
Host smart-305a1714-8bca-4197-9969-27b3d18f59b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10495
17228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1049517228
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1950083679
Short name T3065
Test name
Test status
Simulation time 12966532324 ps
CPU time 17.92 seconds
Started Aug 13 06:38:41 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207860 kb
Host smart-43d96b2a-4642-49d2-87f7-20c3a7846153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19500
83679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1950083679
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.631279084
Short name T1106
Test name
Test status
Simulation time 3754917833 ps
CPU time 5.83 seconds
Started Aug 13 06:38:40 PM PDT 24
Finished Aug 13 06:38:46 PM PDT 24
Peak memory 216140 kb
Host smart-09a455e6-36e6-4773-90f4-efe0b9a3cced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63127
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.631279084
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.1442029133
Short name T199
Test name
Test status
Simulation time 4931154752 ps
CPU time 50.92 seconds
Started Aug 13 06:38:47 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 224200 kb
Host smart-4326768d-2842-46d8-802b-b556cd110a3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1442029133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.1442029133
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2173385400
Short name T551
Test name
Test status
Simulation time 2206365644 ps
CPU time 62.51 seconds
Started Aug 13 06:38:41 PM PDT 24
Finished Aug 13 06:39:43 PM PDT 24
Peak memory 215956 kb
Host smart-a9075c52-4686-4409-ae93-5b4abd1de6a3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2173385400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2173385400
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.2461366694
Short name T2870
Test name
Test status
Simulation time 276382922 ps
CPU time 1.02 seconds
Started Aug 13 06:38:55 PM PDT 24
Finished Aug 13 06:38:56 PM PDT 24
Peak memory 207528 kb
Host smart-3de36a9d-936c-402e-ae58-d1f1edd1699b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2461366694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2461366694
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.346122391
Short name T693
Test name
Test status
Simulation time 192264840 ps
CPU time 0.97 seconds
Started Aug 13 06:38:53 PM PDT 24
Finished Aug 13 06:38:54 PM PDT 24
Peak memory 207532 kb
Host smart-7d27c7b6-f08b-4cb8-973c-2a045ff03fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34612
2391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.346122391
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.99367876
Short name T2606
Test name
Test status
Simulation time 3842435871 ps
CPU time 29.27 seconds
Started Aug 13 06:38:49 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 215968 kb
Host smart-adb4ecfb-5d57-41ad-b5a8-1f93f21a4d3c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=99367876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.99367876
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.656911338
Short name T1366
Test name
Test status
Simulation time 151825830 ps
CPU time 0.84 seconds
Started Aug 13 06:38:40 PM PDT 24
Finished Aug 13 06:38:41 PM PDT 24
Peak memory 207472 kb
Host smart-39cae786-dabe-4484-a488-53450b460494
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=656911338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.656911338
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2746554617
Short name T3501
Test name
Test status
Simulation time 150345868 ps
CPU time 0.84 seconds
Started Aug 13 06:38:51 PM PDT 24
Finished Aug 13 06:38:52 PM PDT 24
Peak memory 207420 kb
Host smart-9377abee-8ff8-4450-b2a0-f4c950e4f5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27465
54617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2746554617
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3028720883
Short name T2736
Test name
Test status
Simulation time 213209120 ps
CPU time 1.06 seconds
Started Aug 13 06:38:49 PM PDT 24
Finished Aug 13 06:38:51 PM PDT 24
Peak memory 207500 kb
Host smart-24927f95-44fd-41d6-a8fd-10a2f379b146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30287
20883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3028720883
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.885728774
Short name T2303
Test name
Test status
Simulation time 183665618 ps
CPU time 1 seconds
Started Aug 13 06:38:39 PM PDT 24
Finished Aug 13 06:38:40 PM PDT 24
Peak memory 207536 kb
Host smart-68d22323-db52-43d8-a6d1-667cba837d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88572
8774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.885728774
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2209015687
Short name T1693
Test name
Test status
Simulation time 184621389 ps
CPU time 0.88 seconds
Started Aug 13 06:38:39 PM PDT 24
Finished Aug 13 06:38:40 PM PDT 24
Peak memory 207500 kb
Host smart-e098ea1e-6eb7-4e97-bac4-47a2dd8a4b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22090
15687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2209015687
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1205623821
Short name T950
Test name
Test status
Simulation time 216602128 ps
CPU time 0.95 seconds
Started Aug 13 06:38:50 PM PDT 24
Finished Aug 13 06:38:51 PM PDT 24
Peak memory 207528 kb
Host smart-d06dbee0-e4fc-4f27-8f38-5d306d30767c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12056
23821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1205623821
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1200570416
Short name T2375
Test name
Test status
Simulation time 154712093 ps
CPU time 0.88 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:38:46 PM PDT 24
Peak memory 207588 kb
Host smart-d7c633b9-3d77-49a1-bb75-f84d1e465fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005
70416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1200570416
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.346570370
Short name T1306
Test name
Test status
Simulation time 213869610 ps
CPU time 1.05 seconds
Started Aug 13 06:38:35 PM PDT 24
Finished Aug 13 06:38:36 PM PDT 24
Peak memory 207548 kb
Host smart-ab7bc149-9c0b-4abd-b5ff-b56e52f69786
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=346570370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.346570370
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2777071050
Short name T1622
Test name
Test status
Simulation time 163411306 ps
CPU time 0.86 seconds
Started Aug 13 06:38:49 PM PDT 24
Finished Aug 13 06:38:50 PM PDT 24
Peak memory 207496 kb
Host smart-ea677790-2194-45bd-9b98-694632aaf42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27770
71050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2777071050
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2095903005
Short name T1748
Test name
Test status
Simulation time 37179783 ps
CPU time 0.71 seconds
Started Aug 13 06:38:44 PM PDT 24
Finished Aug 13 06:38:45 PM PDT 24
Peak memory 207552 kb
Host smart-d5d3a5d4-1d7f-4688-a843-086622a9384b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
03005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2095903005
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1720062944
Short name T57
Test name
Test status
Simulation time 11541188203 ps
CPU time 31.81 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 224148 kb
Host smart-833ec056-5870-4eb0-b7c6-103361944cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17200
62944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1720062944
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3284515289
Short name T2916
Test name
Test status
Simulation time 154358233 ps
CPU time 0.93 seconds
Started Aug 13 06:38:47 PM PDT 24
Finished Aug 13 06:38:48 PM PDT 24
Peak memory 207568 kb
Host smart-679ed7bc-dcc2-4401-ac43-b44384483813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32845
15289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3284515289
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.300552445
Short name T3315
Test name
Test status
Simulation time 204626744 ps
CPU time 0.99 seconds
Started Aug 13 06:38:49 PM PDT 24
Finished Aug 13 06:38:51 PM PDT 24
Peak memory 207492 kb
Host smart-e1005394-7096-4196-8324-d2d9d467d7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30055
2445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.300552445
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2265162235
Short name T600
Test name
Test status
Simulation time 186584241 ps
CPU time 0.91 seconds
Started Aug 13 06:38:54 PM PDT 24
Finished Aug 13 06:38:55 PM PDT 24
Peak memory 207500 kb
Host smart-d4adff53-f5e1-421b-acb4-2c16aac8f728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22651
62235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2265162235
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.613132010
Short name T1221
Test name
Test status
Simulation time 197691117 ps
CPU time 0.9 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:38:46 PM PDT 24
Peak memory 207460 kb
Host smart-58045d0a-6e76-4e39-8ec0-242167adebd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61313
2010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.613132010
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2235515643
Short name T69
Test name
Test status
Simulation time 150933159 ps
CPU time 0.83 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:38:46 PM PDT 24
Peak memory 207424 kb
Host smart-4b590622-8983-4f2a-aa0e-7b30cd836b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22355
15643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2235515643
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1692864683
Short name T868
Test name
Test status
Simulation time 194439561 ps
CPU time 0.89 seconds
Started Aug 13 06:38:49 PM PDT 24
Finished Aug 13 06:38:50 PM PDT 24
Peak memory 207508 kb
Host smart-b9494024-3a09-4538-8a09-6eec74284c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16928
64683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1692864683
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3644066735
Short name T3216
Test name
Test status
Simulation time 143377515 ps
CPU time 0.82 seconds
Started Aug 13 06:38:48 PM PDT 24
Finished Aug 13 06:38:49 PM PDT 24
Peak memory 207540 kb
Host smart-c60a37a8-6301-4983-a01b-d038653c2df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
66735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3644066735
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2683694195
Short name T569
Test name
Test status
Simulation time 208949995 ps
CPU time 1.03 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:38:46 PM PDT 24
Peak memory 207420 kb
Host smart-b7529731-2b93-4276-b66b-721f4c58f5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26836
94195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2683694195
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2647221143
Short name T2327
Test name
Test status
Simulation time 3422241910 ps
CPU time 26.35 seconds
Started Aug 13 06:39:07 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 217932 kb
Host smart-ad06331e-b94b-4bb4-bf07-0f987d35e9a8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2647221143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2647221143
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3328555614
Short name T1942
Test name
Test status
Simulation time 184788662 ps
CPU time 0.92 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:38:46 PM PDT 24
Peak memory 207444 kb
Host smart-9475da7e-2f9a-4636-b27f-df99eacea100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33285
55614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3328555614
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.4034659328
Short name T3198
Test name
Test status
Simulation time 150109292 ps
CPU time 0.87 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:38:46 PM PDT 24
Peak memory 207588 kb
Host smart-8475f091-3847-4bfd-bef1-6df140361e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40346
59328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.4034659328
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.3514217107
Short name T2930
Test name
Test status
Simulation time 1014482523 ps
CPU time 2.45 seconds
Started Aug 13 06:38:54 PM PDT 24
Finished Aug 13 06:38:56 PM PDT 24
Peak memory 207660 kb
Host smart-3beb3a38-6521-4133-8378-34ac1839a0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35142
17107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.3514217107
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2074697117
Short name T2350
Test name
Test status
Simulation time 2598125885 ps
CPU time 77.3 seconds
Started Aug 13 06:39:00 PM PDT 24
Finished Aug 13 06:40:17 PM PDT 24
Peak memory 217580 kb
Host smart-84f5dca8-0758-4759-bb47-fb8f66c45ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
97117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2074697117
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.3950225869
Short name T2022
Test name
Test status
Simulation time 829051831 ps
CPU time 5.41 seconds
Started Aug 13 06:38:42 PM PDT 24
Finished Aug 13 06:38:48 PM PDT 24
Peak memory 207700 kb
Host smart-db0b314d-5f07-4a37-b510-843d0c15d28e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950225869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.3950225869
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_tx_rx_disruption.2363105729
Short name T1745
Test name
Test status
Simulation time 562003768 ps
CPU time 1.59 seconds
Started Aug 13 06:38:43 PM PDT 24
Finished Aug 13 06:38:45 PM PDT 24
Peak memory 207628 kb
Host smart-c4378925-d3a9-4f90-8642-6a93a23aa7bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363105729 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.usbdev_tx_rx_disruption.2363105729
Directory /workspace/34.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/340.usbdev_tx_rx_disruption.1200492504
Short name T2879
Test name
Test status
Simulation time 463098825 ps
CPU time 1.45 seconds
Started Aug 13 06:42:18 PM PDT 24
Finished Aug 13 06:42:20 PM PDT 24
Peak memory 207592 kb
Host smart-9dc1fbbf-2302-4985-a630-11050d239672
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200492504 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 340.usbdev_tx_rx_disruption.1200492504
Directory /workspace/340.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/341.usbdev_tx_rx_disruption.2945333843
Short name T711
Test name
Test status
Simulation time 600367332 ps
CPU time 1.72 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207524 kb
Host smart-ec90b4c8-d233-435c-829e-9315241fd61e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945333843 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 341.usbdev_tx_rx_disruption.2945333843
Directory /workspace/341.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/342.usbdev_tx_rx_disruption.811726030
Short name T1839
Test name
Test status
Simulation time 451127552 ps
CPU time 1.43 seconds
Started Aug 13 06:42:18 PM PDT 24
Finished Aug 13 06:42:19 PM PDT 24
Peak memory 207624 kb
Host smart-a9373155-ed4e-4ca1-9698-72dfe3584f0d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811726030 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 342.usbdev_tx_rx_disruption.811726030
Directory /workspace/342.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/343.usbdev_tx_rx_disruption.3246357031
Short name T518
Test name
Test status
Simulation time 602612466 ps
CPU time 1.58 seconds
Started Aug 13 06:42:00 PM PDT 24
Finished Aug 13 06:42:01 PM PDT 24
Peak memory 207520 kb
Host smart-6896662d-3304-4573-a6df-513bb0fbdba4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246357031 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 343.usbdev_tx_rx_disruption.3246357031
Directory /workspace/343.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/344.usbdev_tx_rx_disruption.2207569172
Short name T1791
Test name
Test status
Simulation time 487783225 ps
CPU time 1.6 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 207536 kb
Host smart-d7c5a33c-b28c-4238-89b6-ba0a3fb6465b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207569172 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 344.usbdev_tx_rx_disruption.2207569172
Directory /workspace/344.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/345.usbdev_tx_rx_disruption.1586388379
Short name T2111
Test name
Test status
Simulation time 481938518 ps
CPU time 1.48 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207616 kb
Host smart-b71c9189-5aee-4488-aa0e-29f93c434015
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586388379 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 345.usbdev_tx_rx_disruption.1586388379
Directory /workspace/345.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/346.usbdev_tx_rx_disruption.2991569030
Short name T3335
Test name
Test status
Simulation time 483945610 ps
CPU time 1.61 seconds
Started Aug 13 06:42:12 PM PDT 24
Finished Aug 13 06:42:13 PM PDT 24
Peak memory 207584 kb
Host smart-b5b0f598-7911-4830-a26a-b20723186c46
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991569030 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 346.usbdev_tx_rx_disruption.2991569030
Directory /workspace/346.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/347.usbdev_tx_rx_disruption.2012256959
Short name T935
Test name
Test status
Simulation time 589571461 ps
CPU time 1.53 seconds
Started Aug 13 06:42:06 PM PDT 24
Finished Aug 13 06:42:08 PM PDT 24
Peak memory 207584 kb
Host smart-b2b0ad71-5ebf-42ff-88c1-7df7d0e735d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012256959 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 347.usbdev_tx_rx_disruption.2012256959
Directory /workspace/347.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/348.usbdev_tx_rx_disruption.4088940658
Short name T933
Test name
Test status
Simulation time 390312425 ps
CPU time 1.27 seconds
Started Aug 13 06:42:15 PM PDT 24
Finished Aug 13 06:42:16 PM PDT 24
Peak memory 207588 kb
Host smart-0fdc05da-6343-444d-a9d5-78eef7ff395d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088940658 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 348.usbdev_tx_rx_disruption.4088940658
Directory /workspace/348.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/349.usbdev_tx_rx_disruption.1170386167
Short name T192
Test name
Test status
Simulation time 570081896 ps
CPU time 1.53 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207572 kb
Host smart-8b508b51-a42d-4926-b202-8a181917bb93
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170386167 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 349.usbdev_tx_rx_disruption.1170386167
Directory /workspace/349.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.778615808
Short name T3466
Test name
Test status
Simulation time 35761834 ps
CPU time 0.68 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:39:02 PM PDT 24
Peak memory 207460 kb
Host smart-e975c290-90db-4222-a3b7-9bd072dd69e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=778615808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.778615808
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2729058314
Short name T1115
Test name
Test status
Simulation time 11413415651 ps
CPU time 15.9 seconds
Started Aug 13 06:38:48 PM PDT 24
Finished Aug 13 06:39:04 PM PDT 24
Peak memory 207784 kb
Host smart-e4591d53-b31c-41c7-b7bb-ef1a6f7c4b92
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729058314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.2729058314
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.488252891
Short name T1059
Test name
Test status
Simulation time 15716646261 ps
CPU time 20.23 seconds
Started Aug 13 06:38:50 PM PDT 24
Finished Aug 13 06:39:11 PM PDT 24
Peak memory 215984 kb
Host smart-8c373e07-d74e-4364-862d-da9022323ee4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=488252891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.488252891
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.499519884
Short name T1674
Test name
Test status
Simulation time 28871577743 ps
CPU time 34.97 seconds
Started Aug 13 06:38:48 PM PDT 24
Finished Aug 13 06:39:23 PM PDT 24
Peak memory 207744 kb
Host smart-3af33bfd-1586-46d8-85f4-395d2dc1e17a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499519884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ao
n_wake_resume.499519884
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1031564691
Short name T2803
Test name
Test status
Simulation time 154266424 ps
CPU time 0.83 seconds
Started Aug 13 06:38:57 PM PDT 24
Finished Aug 13 06:38:57 PM PDT 24
Peak memory 207488 kb
Host smart-d06f83ea-d674-4d6e-88b6-25f1f10c114e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10315
64691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1031564691
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2147995660
Short name T1176
Test name
Test status
Simulation time 160032400 ps
CPU time 0.89 seconds
Started Aug 13 06:38:44 PM PDT 24
Finished Aug 13 06:38:45 PM PDT 24
Peak memory 207492 kb
Host smart-209a57cd-fc7c-44a3-a87a-fde8b998436e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21479
95660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2147995660
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.3429016523
Short name T2923
Test name
Test status
Simulation time 383050366 ps
CPU time 1.53 seconds
Started Aug 13 06:38:48 PM PDT 24
Finished Aug 13 06:38:50 PM PDT 24
Peak memory 207512 kb
Host smart-b8779bdb-e9aa-454b-87ed-30b26afce5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34290
16523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.3429016523
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3004894883
Short name T2652
Test name
Test status
Simulation time 1199923252 ps
CPU time 3.08 seconds
Started Aug 13 06:38:50 PM PDT 24
Finished Aug 13 06:38:54 PM PDT 24
Peak memory 207696 kb
Host smart-a35c0816-ea45-44af-b91a-2698cebf9a2e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3004894883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3004894883
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.2713650775
Short name T1392
Test name
Test status
Simulation time 1299286304 ps
CPU time 31.3 seconds
Started Aug 13 06:38:56 PM PDT 24
Finished Aug 13 06:39:28 PM PDT 24
Peak memory 207728 kb
Host smart-d0adba5e-5278-47a5-adb7-98a80858bb34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713650775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.2713650775
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.2656013402
Short name T1228
Test name
Test status
Simulation time 536548769 ps
CPU time 1.61 seconds
Started Aug 13 06:38:51 PM PDT 24
Finished Aug 13 06:38:53 PM PDT 24
Peak memory 207540 kb
Host smart-5613c455-6448-4feb-9c87-6ef257fa0c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26560
13402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.2656013402
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2650615807
Short name T2969
Test name
Test status
Simulation time 131657951 ps
CPU time 0.87 seconds
Started Aug 13 06:38:50 PM PDT 24
Finished Aug 13 06:38:52 PM PDT 24
Peak memory 207540 kb
Host smart-53bcad41-61f4-4756-84c0-b6765c16c919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26506
15807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2650615807
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.2272089510
Short name T876
Test name
Test status
Simulation time 32177426 ps
CPU time 0.72 seconds
Started Aug 13 06:39:00 PM PDT 24
Finished Aug 13 06:39:01 PM PDT 24
Peak memory 207480 kb
Host smart-1e4e2dc1-69e6-4dd6-981f-f80354f1ef65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22720
89510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2272089510
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.710464851
Short name T1428
Test name
Test status
Simulation time 847390666 ps
CPU time 2.35 seconds
Started Aug 13 06:39:04 PM PDT 24
Finished Aug 13 06:39:06 PM PDT 24
Peak memory 207792 kb
Host smart-09b4a4a2-35db-456a-b19b-2746026c3d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71046
4851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.710464851
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1403430420
Short name T637
Test name
Test status
Simulation time 406970702 ps
CPU time 2.69 seconds
Started Aug 13 06:38:54 PM PDT 24
Finished Aug 13 06:38:57 PM PDT 24
Peak memory 207704 kb
Host smart-2d446ebf-0b6d-4548-bc94-1c8779fe6aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14034
30420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1403430420
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1019294905
Short name T3624
Test name
Test status
Simulation time 173329646 ps
CPU time 0.93 seconds
Started Aug 13 06:38:51 PM PDT 24
Finished Aug 13 06:38:53 PM PDT 24
Peak memory 207496 kb
Host smart-30fdcdc1-235a-442d-98a9-51703540d81a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1019294905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1019294905
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.607506663
Short name T757
Test name
Test status
Simulation time 180967296 ps
CPU time 0.9 seconds
Started Aug 13 06:38:56 PM PDT 24
Finished Aug 13 06:38:57 PM PDT 24
Peak memory 207508 kb
Host smart-beaa8178-72f4-48e6-91ec-37227e450f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60750
6663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.607506663
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.242059582
Short name T2003
Test name
Test status
Simulation time 244255095 ps
CPU time 1.08 seconds
Started Aug 13 06:38:52 PM PDT 24
Finished Aug 13 06:38:53 PM PDT 24
Peak memory 207436 kb
Host smart-98f8dd42-0816-4335-ac64-8ccbc8f64763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24205
9582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.242059582
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.2482909499
Short name T828
Test name
Test status
Simulation time 4395895048 ps
CPU time 36.16 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 218024 kb
Host smart-3461893e-1f18-4c61-87b7-7a4b8cd68d23
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2482909499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.2482909499
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.325400163
Short name T2729
Test name
Test status
Simulation time 10449660114 ps
CPU time 69.98 seconds
Started Aug 13 06:38:49 PM PDT 24
Finished Aug 13 06:39:59 PM PDT 24
Peak memory 207824 kb
Host smart-9e05e938-31f6-40d7-90ee-a38e98d5a1de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=325400163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.325400163
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3097819023
Short name T3145
Test name
Test status
Simulation time 213277661 ps
CPU time 0.9 seconds
Started Aug 13 06:38:56 PM PDT 24
Finished Aug 13 06:38:57 PM PDT 24
Peak memory 207528 kb
Host smart-2655e9cd-0e7e-402d-9f35-e1879bc6966a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30978
19023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3097819023
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.2439601899
Short name T2612
Test name
Test status
Simulation time 30284780922 ps
CPU time 52.76 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 207852 kb
Host smart-b01affc1-0a4b-46ea-8f46-7fa42943e14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24396
01899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.2439601899
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2700012454
Short name T3288
Test name
Test status
Simulation time 8522866987 ps
CPU time 10.83 seconds
Started Aug 13 06:38:45 PM PDT 24
Finished Aug 13 06:38:56 PM PDT 24
Peak memory 207852 kb
Host smart-00a3ac94-0c54-4458-bb06-474296e140cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27000
12454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2700012454
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.767539863
Short name T957
Test name
Test status
Simulation time 2803134047 ps
CPU time 27 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:26 PM PDT 24
Peak memory 224212 kb
Host smart-656236f7-508b-4fa5-9048-5b9643609df6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=767539863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.767539863
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2811462967
Short name T2271
Test name
Test status
Simulation time 2475884921 ps
CPU time 24.89 seconds
Started Aug 13 06:39:11 PM PDT 24
Finished Aug 13 06:39:36 PM PDT 24
Peak memory 216908 kb
Host smart-ab1c5af2-188b-42a4-a10b-9dfc0fe35097
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2811462967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2811462967
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3386733231
Short name T3513
Test name
Test status
Simulation time 237738981 ps
CPU time 0.98 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207520 kb
Host smart-82f77b3f-6b6a-401d-bd71-3de08e552dc4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3386733231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3386733231
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.4171530427
Short name T3197
Test name
Test status
Simulation time 219630911 ps
CPU time 1.01 seconds
Started Aug 13 06:38:57 PM PDT 24
Finished Aug 13 06:38:58 PM PDT 24
Peak memory 207512 kb
Host smart-1ffdafd1-f51a-4ec3-9383-d20c78855cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41715
30427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.4171530427
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.722233537
Short name T1114
Test name
Test status
Simulation time 2380235763 ps
CPU time 26.26 seconds
Started Aug 13 06:39:03 PM PDT 24
Finished Aug 13 06:39:30 PM PDT 24
Peak memory 217700 kb
Host smart-e8e67dfe-9f25-4f0c-8bfd-dc7c8f74d4e5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=722233537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.722233537
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.1831882774
Short name T2373
Test name
Test status
Simulation time 148615732 ps
CPU time 0.86 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207504 kb
Host smart-79d311a4-229e-4c81-a723-f7fa9b285e4e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1831882774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.1831882774
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2942645931
Short name T1336
Test name
Test status
Simulation time 142477663 ps
CPU time 0.92 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:39:03 PM PDT 24
Peak memory 207480 kb
Host smart-76b29a34-5958-466a-9244-0c9faa01fbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29426
45931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2942645931
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3778924874
Short name T154
Test name
Test status
Simulation time 197911793 ps
CPU time 0.92 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207488 kb
Host smart-69e37468-8138-488c-a43f-b2167b8eaa6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37789
24874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3778924874
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3370376779
Short name T1664
Test name
Test status
Simulation time 200809664 ps
CPU time 1.01 seconds
Started Aug 13 06:39:07 PM PDT 24
Finished Aug 13 06:39:08 PM PDT 24
Peak memory 207528 kb
Host smart-1383a433-222c-4dca-9c72-a5353890fd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
76779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3370376779
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1023835953
Short name T595
Test name
Test status
Simulation time 151630929 ps
CPU time 0.83 seconds
Started Aug 13 06:38:55 PM PDT 24
Finished Aug 13 06:39:01 PM PDT 24
Peak memory 207368 kb
Host smart-4f97653e-7d2f-4acc-8ec3-2c1c98f05554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10238
35953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1023835953
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1964760968
Short name T954
Test name
Test status
Simulation time 166761798 ps
CPU time 0.84 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207612 kb
Host smart-4bfc85ba-c3e9-43d3-a5c2-870ab01ad745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19647
60968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1964760968
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2670680069
Short name T3370
Test name
Test status
Simulation time 165557205 ps
CPU time 0.86 seconds
Started Aug 13 06:38:54 PM PDT 24
Finished Aug 13 06:38:55 PM PDT 24
Peak memory 207496 kb
Host smart-1d8d672b-0b46-42eb-9260-7dc6f3fc059c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26706
80069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2670680069
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.3325130162
Short name T2039
Test name
Test status
Simulation time 226253164 ps
CPU time 0.99 seconds
Started Aug 13 06:38:57 PM PDT 24
Finished Aug 13 06:38:58 PM PDT 24
Peak memory 207520 kb
Host smart-60b36845-9463-4194-a318-b8495e23e42c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3325130162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.3325130162
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.612255394
Short name T3273
Test name
Test status
Simulation time 230948905 ps
CPU time 0.91 seconds
Started Aug 13 06:39:15 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 207508 kb
Host smart-07e0a2a2-145b-4a69-992b-0e6f08e2163a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61225
5394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.612255394
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3617312363
Short name T1565
Test name
Test status
Simulation time 37145470 ps
CPU time 0.72 seconds
Started Aug 13 06:39:10 PM PDT 24
Finished Aug 13 06:39:11 PM PDT 24
Peak memory 207580 kb
Host smart-4d3d68ee-e72a-42ac-b8e9-cbfc61d0c735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36173
12363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3617312363
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.441834540
Short name T3350
Test name
Test status
Simulation time 11807270082 ps
CPU time 29.09 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:39:31 PM PDT 24
Peak memory 216024 kb
Host smart-d0082773-9ecb-4d70-b1eb-3c48d81ee67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44183
4540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.441834540
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3888113315
Short name T2623
Test name
Test status
Simulation time 199387776 ps
CPU time 0.92 seconds
Started Aug 13 06:38:54 PM PDT 24
Finished Aug 13 06:38:55 PM PDT 24
Peak memory 207580 kb
Host smart-de6689a4-7055-4002-b3df-5a4755bc9831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38881
13315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3888113315
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.315597185
Short name T2335
Test name
Test status
Simulation time 164994392 ps
CPU time 0.87 seconds
Started Aug 13 06:38:57 PM PDT 24
Finished Aug 13 06:38:58 PM PDT 24
Peak memory 207392 kb
Host smart-340d735d-2858-4b9a-b74c-30d5decb0a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31559
7185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.315597185
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1338867005
Short name T652
Test name
Test status
Simulation time 270286493 ps
CPU time 1.06 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:02 PM PDT 24
Peak memory 207512 kb
Host smart-f50c117d-466f-44fd-9701-0ed13231c797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13388
67005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1338867005
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2685044108
Short name T2064
Test name
Test status
Simulation time 195863670 ps
CPU time 0.91 seconds
Started Aug 13 06:39:00 PM PDT 24
Finished Aug 13 06:39:01 PM PDT 24
Peak memory 207480 kb
Host smart-339a5c41-0ec2-4218-9aff-8dff4db16a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26850
44108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2685044108
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2142249144
Short name T1762
Test name
Test status
Simulation time 175134388 ps
CPU time 0.94 seconds
Started Aug 13 06:38:55 PM PDT 24
Finished Aug 13 06:38:56 PM PDT 24
Peak memory 207460 kb
Host smart-20fef6a1-fac0-4372-99da-63bc471ccc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21422
49144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2142249144
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_rx_full.2294606021
Short name T2486
Test name
Test status
Simulation time 250287914 ps
CPU time 1.05 seconds
Started Aug 13 06:39:00 PM PDT 24
Finished Aug 13 06:39:01 PM PDT 24
Peak memory 207428 kb
Host smart-2eb427fd-c1cd-4fed-b9cc-187a2327cc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22946
06021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.2294606021
Directory /workspace/35.usbdev_rx_full/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3581438075
Short name T3239
Test name
Test status
Simulation time 151520342 ps
CPU time 0.88 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207556 kb
Host smart-8d372c7a-adaa-4b96-a09f-68ed5194f972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35814
38075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3581438075
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3217145808
Short name T648
Test name
Test status
Simulation time 180889333 ps
CPU time 0.89 seconds
Started Aug 13 06:39:10 PM PDT 24
Finished Aug 13 06:39:11 PM PDT 24
Peak memory 207440 kb
Host smart-4586961c-2f4f-472a-b1a3-54e2d1c99331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32171
45808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3217145808
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.198107544
Short name T583
Test name
Test status
Simulation time 244627854 ps
CPU time 1.07 seconds
Started Aug 13 06:39:06 PM PDT 24
Finished Aug 13 06:39:07 PM PDT 24
Peak memory 207496 kb
Host smart-9064d4ef-c645-41d2-a886-f8c7aa8e3dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19810
7544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.198107544
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1453926626
Short name T2596
Test name
Test status
Simulation time 1583953073 ps
CPU time 11.92 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:13 PM PDT 24
Peak memory 217584 kb
Host smart-a51b66ca-4aaa-4e35-99e0-50f5035fd8e1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1453926626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1453926626
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2665618647
Short name T2826
Test name
Test status
Simulation time 192238208 ps
CPU time 1.01 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:39:03 PM PDT 24
Peak memory 207488 kb
Host smart-49235d62-0f4d-405d-9703-e8f4e5a334d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26656
18647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2665618647
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.611101204
Short name T647
Test name
Test status
Simulation time 157930376 ps
CPU time 0.9 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:39:03 PM PDT 24
Peak memory 207512 kb
Host smart-a37274bb-6607-45e6-b2ce-470cd1e5c17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61110
1204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.611101204
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2981496084
Short name T3207
Test name
Test status
Simulation time 1419954752 ps
CPU time 3.23 seconds
Started Aug 13 06:38:58 PM PDT 24
Finished Aug 13 06:39:01 PM PDT 24
Peak memory 207756 kb
Host smart-ee29fe17-7ada-48c2-9064-12811ef72dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29814
96084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2981496084
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2096667786
Short name T2437
Test name
Test status
Simulation time 2631444743 ps
CPU time 73.02 seconds
Started Aug 13 06:39:13 PM PDT 24
Finished Aug 13 06:40:26 PM PDT 24
Peak memory 217488 kb
Host smart-2b1d8f1a-599c-4a8f-9360-db14deac38fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20966
67786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2096667786
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.1439479441
Short name T3311
Test name
Test status
Simulation time 2531121147 ps
CPU time 18.03 seconds
Started Aug 13 06:38:51 PM PDT 24
Finished Aug 13 06:39:09 PM PDT 24
Peak memory 207772 kb
Host smart-7cc1a5dc-dc7b-4350-811a-265be81df956
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439479441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.1439479441
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_tx_rx_disruption.2570940696
Short name T1281
Test name
Test status
Simulation time 513463640 ps
CPU time 1.64 seconds
Started Aug 13 06:38:58 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207608 kb
Host smart-feab6713-e880-456b-a1d2-ed0be518f505
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570940696 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.usbdev_tx_rx_disruption.2570940696
Directory /workspace/35.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/350.usbdev_tx_rx_disruption.3723242906
Short name T3115
Test name
Test status
Simulation time 557718778 ps
CPU time 1.56 seconds
Started Aug 13 06:42:17 PM PDT 24
Finished Aug 13 06:42:19 PM PDT 24
Peak memory 207612 kb
Host smart-fd943de8-21ce-40b8-9459-eae4d36d7023
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723242906 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 350.usbdev_tx_rx_disruption.3723242906
Directory /workspace/350.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/351.usbdev_tx_rx_disruption.1462308973
Short name T2944
Test name
Test status
Simulation time 542140981 ps
CPU time 1.48 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207584 kb
Host smart-d1aca8bb-adb9-43f5-b2d8-11894f98ee88
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462308973 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 351.usbdev_tx_rx_disruption.1462308973
Directory /workspace/351.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/352.usbdev_tx_rx_disruption.1247864241
Short name T1683
Test name
Test status
Simulation time 585756655 ps
CPU time 1.56 seconds
Started Aug 13 06:42:06 PM PDT 24
Finished Aug 13 06:42:08 PM PDT 24
Peak memory 207584 kb
Host smart-461b439b-ac06-4bfa-ae89-dbbbcc0e6591
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247864241 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 352.usbdev_tx_rx_disruption.1247864241
Directory /workspace/352.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/353.usbdev_tx_rx_disruption.972161818
Short name T3403
Test name
Test status
Simulation time 473644477 ps
CPU time 1.42 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207572 kb
Host smart-d04cbd1d-17bd-45d0-9778-c5914a0679e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972161818 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 353.usbdev_tx_rx_disruption.972161818
Directory /workspace/353.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/354.usbdev_tx_rx_disruption.1277158848
Short name T1396
Test name
Test status
Simulation time 535847699 ps
CPU time 1.78 seconds
Started Aug 13 06:41:55 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207612 kb
Host smart-db765987-d918-403e-a677-c138ac13ac28
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277158848 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 354.usbdev_tx_rx_disruption.1277158848
Directory /workspace/354.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/355.usbdev_tx_rx_disruption.458714042
Short name T3477
Test name
Test status
Simulation time 509567166 ps
CPU time 1.49 seconds
Started Aug 13 06:42:06 PM PDT 24
Finished Aug 13 06:42:07 PM PDT 24
Peak memory 207608 kb
Host smart-6199bea5-2ac8-45c0-a208-4a5c1665c9c0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458714042 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 355.usbdev_tx_rx_disruption.458714042
Directory /workspace/355.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/356.usbdev_tx_rx_disruption.4207259129
Short name T705
Test name
Test status
Simulation time 497581238 ps
CPU time 1.61 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207588 kb
Host smart-b510b6b9-193c-40ed-a0fb-2fb644d59725
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207259129 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 356.usbdev_tx_rx_disruption.4207259129
Directory /workspace/356.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/357.usbdev_tx_rx_disruption.555314617
Short name T1639
Test name
Test status
Simulation time 562272571 ps
CPU time 1.56 seconds
Started Aug 13 06:42:14 PM PDT 24
Finished Aug 13 06:42:15 PM PDT 24
Peak memory 207608 kb
Host smart-94819024-3456-4503-8600-cf777c882fc6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555314617 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 357.usbdev_tx_rx_disruption.555314617
Directory /workspace/357.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/358.usbdev_tx_rx_disruption.3180146424
Short name T3156
Test name
Test status
Simulation time 410153892 ps
CPU time 1.28 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:23 PM PDT 24
Peak memory 207572 kb
Host smart-e490f210-9de7-4366-a550-8fc52fb9cb52
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180146424 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 358.usbdev_tx_rx_disruption.3180146424
Directory /workspace/358.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/359.usbdev_tx_rx_disruption.2338903061
Short name T177
Test name
Test status
Simulation time 603456155 ps
CPU time 1.72 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207608 kb
Host smart-4c014230-b431-42af-aa4f-f64b6601b87c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338903061 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 359.usbdev_tx_rx_disruption.2338903061
Directory /workspace/359.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1734933147
Short name T1945
Test name
Test status
Simulation time 48587685 ps
CPU time 0.68 seconds
Started Aug 13 06:39:09 PM PDT 24
Finished Aug 13 06:39:10 PM PDT 24
Peak memory 207412 kb
Host smart-ca322dd4-8a76-429e-a6b1-32f5412d088b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1734933147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1734933147
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1233444446
Short name T2314
Test name
Test status
Simulation time 15549444691 ps
CPU time 22.43 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:39:39 PM PDT 24
Peak memory 216032 kb
Host smart-f0d9b7c7-e361-4143-ad56-c246fa1f8389
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233444446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1233444446
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1490410802
Short name T2607
Test name
Test status
Simulation time 25170977022 ps
CPU time 28.52 seconds
Started Aug 13 06:39:12 PM PDT 24
Finished Aug 13 06:39:50 PM PDT 24
Peak memory 216356 kb
Host smart-2b7daaeb-63c7-4160-bad3-29969af97152
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490410802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.1490410802
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2223912032
Short name T658
Test name
Test status
Simulation time 149287029 ps
CPU time 0.92 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:39:03 PM PDT 24
Peak memory 207540 kb
Host smart-5a3fb937-28c0-416d-b703-88be5193710a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22239
12032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2223912032
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1383147837
Short name T2597
Test name
Test status
Simulation time 151013323 ps
CPU time 0.85 seconds
Started Aug 13 06:39:00 PM PDT 24
Finished Aug 13 06:39:01 PM PDT 24
Peak memory 207588 kb
Host smart-890b7cc6-3ad2-4998-82c0-fd6ec42ddcf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13831
47837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1383147837
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3984767750
Short name T3393
Test name
Test status
Simulation time 355180204 ps
CPU time 1.44 seconds
Started Aug 13 06:39:04 PM PDT 24
Finished Aug 13 06:39:05 PM PDT 24
Peak memory 207612 kb
Host smart-2033e5e0-047f-45e0-9496-c24f6e0bcc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39847
67750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3984767750
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1791959956
Short name T3223
Test name
Test status
Simulation time 914868651 ps
CPU time 2.38 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:01 PM PDT 24
Peak memory 207704 kb
Host smart-af651c3d-ae57-4cbe-ace2-e30d30e45432
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1791959956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1791959956
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.210572264
Short name T1689
Test name
Test status
Simulation time 47226216145 ps
CPU time 68.82 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207780 kb
Host smart-23a00baa-2a57-4350-8157-66766e79e972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
2264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.210572264
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.171219957
Short name T2388
Test name
Test status
Simulation time 4329086131 ps
CPU time 38.76 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:40 PM PDT 24
Peak memory 207812 kb
Host smart-49f18212-8298-4f5b-a293-a0967f8d67a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171219957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.171219957
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.1467122101
Short name T1805
Test name
Test status
Simulation time 759299313 ps
CPU time 1.87 seconds
Started Aug 13 06:39:07 PM PDT 24
Finished Aug 13 06:39:09 PM PDT 24
Peak memory 207520 kb
Host smart-c7b70596-298a-438a-b48e-f2c2da2ca038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14671
22101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.1467122101
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1067886944
Short name T1502
Test name
Test status
Simulation time 173664117 ps
CPU time 0.89 seconds
Started Aug 13 06:39:04 PM PDT 24
Finished Aug 13 06:39:05 PM PDT 24
Peak memory 207544 kb
Host smart-45571e29-f1c4-4be6-a62f-1069fda5db7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10678
86944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1067886944
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1543463056
Short name T280
Test name
Test status
Simulation time 35148538 ps
CPU time 0.73 seconds
Started Aug 13 06:39:10 PM PDT 24
Finished Aug 13 06:39:11 PM PDT 24
Peak memory 207456 kb
Host smart-5e137a04-87f7-4e6a-b9b5-149da126b92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15434
63056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1543463056
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3321835422
Short name T2651
Test name
Test status
Simulation time 881227578 ps
CPU time 2.54 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:39:05 PM PDT 24
Peak memory 207840 kb
Host smart-b67e99e6-ccc8-4538-a844-32fd08e96000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33218
35422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3321835422
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_types.1674806467
Short name T494
Test name
Test status
Simulation time 416631627 ps
CPU time 1.4 seconds
Started Aug 13 06:39:00 PM PDT 24
Finished Aug 13 06:39:02 PM PDT 24
Peak memory 207568 kb
Host smart-5a1c9abf-77c4-4107-b368-728cff69969f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1674806467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.1674806467
Directory /workspace/36.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2999329078
Short name T3357
Test name
Test status
Simulation time 201189394 ps
CPU time 1.84 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:03 PM PDT 24
Peak memory 207696 kb
Host smart-6c5a2da0-9da9-4537-8c82-814cacbf2d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29993
29078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2999329078
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3821108881
Short name T2572
Test name
Test status
Simulation time 160918957 ps
CPU time 0.88 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:02 PM PDT 24
Peak memory 207496 kb
Host smart-a7181834-58fb-4719-a637-d321388d307e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3821108881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3821108881
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2954044394
Short name T3230
Test name
Test status
Simulation time 155999875 ps
CPU time 0.87 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:02 PM PDT 24
Peak memory 207460 kb
Host smart-a6ac1f0a-e16f-4e6e-8a17-d46135b032d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29540
44394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2954044394
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1503705501
Short name T166
Test name
Test status
Simulation time 156864291 ps
CPU time 0.85 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207452 kb
Host smart-45a5853c-932f-4995-b743-f99f3c560913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15037
05501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1503705501
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.2795137001
Short name T747
Test name
Test status
Simulation time 2411751514 ps
CPU time 19.19 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 224208 kb
Host smart-631bb448-36e4-4f27-8b44-32994e2a3da4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2795137001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.2795137001
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.1145691403
Short name T2857
Test name
Test status
Simulation time 14861575480 ps
CPU time 97.73 seconds
Started Aug 13 06:38:55 PM PDT 24
Finished Aug 13 06:40:33 PM PDT 24
Peak memory 207752 kb
Host smart-5607fcda-cd80-4130-a1a6-887e93ae342d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1145691403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.1145691403
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.3145365102
Short name T3227
Test name
Test status
Simulation time 220946861 ps
CPU time 1.01 seconds
Started Aug 13 06:38:51 PM PDT 24
Finished Aug 13 06:38:53 PM PDT 24
Peak memory 207484 kb
Host smart-c81ef2f7-b971-431f-8013-4a399530bfe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31453
65102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.3145365102
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.539393504
Short name T830
Test name
Test status
Simulation time 25199239019 ps
CPU time 43.69 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:45 PM PDT 24
Peak memory 216688 kb
Host smart-685e6924-c31e-4288-bb09-5e9ded75703a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53939
3504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.539393504
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3001161031
Short name T2215
Test name
Test status
Simulation time 5392689650 ps
CPU time 8.14 seconds
Started Aug 13 06:38:57 PM PDT 24
Finished Aug 13 06:39:06 PM PDT 24
Peak memory 216076 kb
Host smart-35671aae-fae4-48cc-b4ad-a66e712bbce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30011
61031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3001161031
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.1437090517
Short name T3484
Test name
Test status
Simulation time 3196332572 ps
CPU time 24.43 seconds
Started Aug 13 06:39:11 PM PDT 24
Finished Aug 13 06:39:35 PM PDT 24
Peak memory 224180 kb
Host smart-36fddf96-bcb7-4770-a48a-62a616d751f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1437090517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.1437090517
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3685360260
Short name T1809
Test name
Test status
Simulation time 2354287320 ps
CPU time 67.91 seconds
Started Aug 13 06:38:57 PM PDT 24
Finished Aug 13 06:40:05 PM PDT 24
Peak memory 217128 kb
Host smart-a7b03047-82a3-4e28-876c-cf4debedaac1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3685360260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3685360260
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2399970870
Short name T1240
Test name
Test status
Simulation time 241340355 ps
CPU time 1.01 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:15 PM PDT 24
Peak memory 207484 kb
Host smart-7f93be3e-225c-4012-8c3f-f1295927c068
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2399970870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2399970870
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.4159592721
Short name T2629
Test name
Test status
Simulation time 257591933 ps
CPU time 1 seconds
Started Aug 13 06:39:10 PM PDT 24
Finished Aug 13 06:39:11 PM PDT 24
Peak memory 207508 kb
Host smart-87fed60b-5af0-4828-a0c1-4bb250b28410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41595
92721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.4159592721
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3484852574
Short name T3610
Test name
Test status
Simulation time 2936923994 ps
CPU time 22 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:24 PM PDT 24
Peak memory 217708 kb
Host smart-0618bf5d-ecc3-4cb2-91cc-0b7d8fa155c6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3484852574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3484852574
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3895934340
Short name T617
Test name
Test status
Simulation time 195974235 ps
CPU time 0.97 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:02 PM PDT 24
Peak memory 207504 kb
Host smart-fa48eb6d-51a8-4e80-af05-2e469fb8a6c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3895934340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3895934340
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1120164784
Short name T1544
Test name
Test status
Simulation time 144022210 ps
CPU time 0.81 seconds
Started Aug 13 06:39:28 PM PDT 24
Finished Aug 13 06:39:28 PM PDT 24
Peak memory 207488 kb
Host smart-7561cd53-4e09-4f40-90ba-3f93a74fed62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11201
64784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1120164784
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3707884476
Short name T2258
Test name
Test status
Simulation time 213574555 ps
CPU time 0.93 seconds
Started Aug 13 06:38:56 PM PDT 24
Finished Aug 13 06:38:57 PM PDT 24
Peak memory 207488 kb
Host smart-b2533f52-5945-4564-9160-a790404b9fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37078
84476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3707884476
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3467985076
Short name T2379
Test name
Test status
Simulation time 189220766 ps
CPU time 1 seconds
Started Aug 13 06:39:03 PM PDT 24
Finished Aug 13 06:39:04 PM PDT 24
Peak memory 207516 kb
Host smart-17ad7efc-e11c-4345-9e54-0123f91484c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34679
85076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3467985076
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.107128003
Short name T1026
Test name
Test status
Simulation time 140774275 ps
CPU time 0.83 seconds
Started Aug 13 06:39:06 PM PDT 24
Finished Aug 13 06:39:07 PM PDT 24
Peak memory 207540 kb
Host smart-d44abc9d-0335-42a0-a0b6-6c938a7d2293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10712
8003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.107128003
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1433835904
Short name T912
Test name
Test status
Simulation time 184649262 ps
CPU time 0.87 seconds
Started Aug 13 06:39:12 PM PDT 24
Finished Aug 13 06:39:13 PM PDT 24
Peak memory 207612 kb
Host smart-c2091eba-710a-4e91-8edb-c08acdafcca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14338
35904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1433835904
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3751270956
Short name T1624
Test name
Test status
Simulation time 209299486 ps
CPU time 0.95 seconds
Started Aug 13 06:39:00 PM PDT 24
Finished Aug 13 06:39:01 PM PDT 24
Peak memory 207604 kb
Host smart-32e67cdd-a3d3-4a3f-b607-7aa065455e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37512
70956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3751270956
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1161753618
Short name T2687
Test name
Test status
Simulation time 202162051 ps
CPU time 0.99 seconds
Started Aug 13 06:38:54 PM PDT 24
Finished Aug 13 06:38:55 PM PDT 24
Peak memory 207556 kb
Host smart-49e571ff-b391-4759-a817-d7df984c5799
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1161753618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1161753618
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.981279863
Short name T3400
Test name
Test status
Simulation time 159106718 ps
CPU time 0.89 seconds
Started Aug 13 06:38:58 PM PDT 24
Finished Aug 13 06:38:59 PM PDT 24
Peak memory 207476 kb
Host smart-875ef95e-f9f7-4e06-9076-35b6fb69883c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98127
9863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.981279863
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2622234138
Short name T1478
Test name
Test status
Simulation time 46355531 ps
CPU time 0.71 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207488 kb
Host smart-7af81444-7592-4d82-ba5c-4c30560844c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
34138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2622234138
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2174851757
Short name T3439
Test name
Test status
Simulation time 9955532064 ps
CPU time 29.52 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:31 PM PDT 24
Peak memory 215988 kb
Host smart-a3414c5c-f930-4ed1-99d4-67af94853349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21748
51757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2174851757
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.4275415308
Short name T2854
Test name
Test status
Simulation time 148657043 ps
CPU time 0.86 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207588 kb
Host smart-165d00e2-b08d-4d48-b168-29df4aef71e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42754
15308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.4275415308
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.4075135510
Short name T3424
Test name
Test status
Simulation time 195438182 ps
CPU time 0.91 seconds
Started Aug 13 06:38:55 PM PDT 24
Finished Aug 13 06:38:56 PM PDT 24
Peak memory 207372 kb
Host smart-0952caa8-8e79-46e2-9f2f-f10f03b2a2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751
35510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.4075135510
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3899549507
Short name T2602
Test name
Test status
Simulation time 249443729 ps
CPU time 1.09 seconds
Started Aug 13 06:39:03 PM PDT 24
Finished Aug 13 06:39:04 PM PDT 24
Peak memory 207528 kb
Host smart-1060c6b2-a0a2-483c-bd93-d4689014fc73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995
49507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3899549507
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3739019005
Short name T928
Test name
Test status
Simulation time 178829353 ps
CPU time 1.02 seconds
Started Aug 13 06:39:01 PM PDT 24
Finished Aug 13 06:39:02 PM PDT 24
Peak memory 207532 kb
Host smart-dc67cae0-1304-4857-bb02-33902779d320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37390
19005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3739019005
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3262576498
Short name T277
Test name
Test status
Simulation time 167710408 ps
CPU time 0.87 seconds
Started Aug 13 06:38:59 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207480 kb
Host smart-3a24effd-6a5f-456b-8484-0360ac902cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32625
76498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3262576498
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_rx_full.4182123570
Short name T328
Test name
Test status
Simulation time 266102030 ps
CPU time 1.15 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:15 PM PDT 24
Peak memory 207540 kb
Host smart-5cbe852a-78c9-4d16-9efc-c16429813b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41821
23570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.4182123570
Directory /workspace/36.usbdev_rx_full/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.614827916
Short name T1148
Test name
Test status
Simulation time 152432164 ps
CPU time 0.91 seconds
Started Aug 13 06:38:57 PM PDT 24
Finished Aug 13 06:38:58 PM PDT 24
Peak memory 207516 kb
Host smart-ff894b04-1fcc-45cd-b6a6-600a469e3194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61482
7916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.614827916
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1393335127
Short name T1628
Test name
Test status
Simulation time 150129241 ps
CPU time 0.82 seconds
Started Aug 13 06:39:07 PM PDT 24
Finished Aug 13 06:39:08 PM PDT 24
Peak memory 207540 kb
Host smart-ae12ccb4-7aea-4ae6-82b9-13e7fa63d9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13933
35127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1393335127
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3317906441
Short name T3009
Test name
Test status
Simulation time 224629470 ps
CPU time 1.03 seconds
Started Aug 13 06:39:02 PM PDT 24
Finished Aug 13 06:39:03 PM PDT 24
Peak memory 207536 kb
Host smart-c39e8db8-edc3-4a8e-bf24-ab86105c185c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33179
06441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3317906441
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.969430149
Short name T1920
Test name
Test status
Simulation time 3252995166 ps
CPU time 92.18 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:40:46 PM PDT 24
Peak memory 224100 kb
Host smart-f3b3b5fd-c084-46c8-92d7-436a6e4dd39d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=969430149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.969430149
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1141806930
Short name T2062
Test name
Test status
Simulation time 179486382 ps
CPU time 0.95 seconds
Started Aug 13 06:39:03 PM PDT 24
Finished Aug 13 06:39:04 PM PDT 24
Peak memory 207452 kb
Host smart-17fbd4ad-b7ee-4030-83f6-60261adfc078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11418
06930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1141806930
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3316185823
Short name T1257
Test name
Test status
Simulation time 212759960 ps
CPU time 0.9 seconds
Started Aug 13 06:38:57 PM PDT 24
Finished Aug 13 06:38:58 PM PDT 24
Peak memory 207624 kb
Host smart-d974ed1b-8b64-47ee-b52f-629629017d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33161
85823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3316185823
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.409651566
Short name T2619
Test name
Test status
Simulation time 1346542448 ps
CPU time 3.13 seconds
Started Aug 13 06:39:00 PM PDT 24
Finished Aug 13 06:39:03 PM PDT 24
Peak memory 207776 kb
Host smart-4d7d85ac-c6d3-46f7-9d6d-31b11c3a5d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40965
1566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.409651566
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.2666340883
Short name T3493
Test name
Test status
Simulation time 2912053924 ps
CPU time 82.44 seconds
Started Aug 13 06:39:04 PM PDT 24
Finished Aug 13 06:40:27 PM PDT 24
Peak memory 216012 kb
Host smart-79a667ec-181f-4552-b1b5-1210a89c5b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26663
40883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.2666340883
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.2804128622
Short name T1849
Test name
Test status
Simulation time 2912012794 ps
CPU time 23.05 seconds
Started Aug 13 06:38:53 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 207680 kb
Host smart-bf350767-fa82-44b7-a423-cd5e33d98b07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804128622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.2804128622
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_tx_rx_disruption.1698799749
Short name T2006
Test name
Test status
Simulation time 664705839 ps
CPU time 1.76 seconds
Started Aug 13 06:38:58 PM PDT 24
Finished Aug 13 06:39:00 PM PDT 24
Peak memory 207472 kb
Host smart-4ad1f5d7-8ddf-4d7e-9142-294f9cb48444
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698799749 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.usbdev_tx_rx_disruption.1698799749
Directory /workspace/36.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/360.usbdev_tx_rx_disruption.311447109
Short name T591
Test name
Test status
Simulation time 524298787 ps
CPU time 1.51 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207560 kb
Host smart-fac1cb1c-ad93-4d7e-835c-a98aa95fba5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311447109 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 360.usbdev_tx_rx_disruption.311447109
Directory /workspace/360.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/361.usbdev_tx_rx_disruption.1639409553
Short name T2101
Test name
Test status
Simulation time 576526302 ps
CPU time 1.55 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207572 kb
Host smart-e36e3d2d-49f4-41ca-b65c-4317a621d818
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639409553 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 361.usbdev_tx_rx_disruption.1639409553
Directory /workspace/361.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/362.usbdev_tx_rx_disruption.3825689427
Short name T1758
Test name
Test status
Simulation time 548594812 ps
CPU time 1.7 seconds
Started Aug 13 06:41:52 PM PDT 24
Finished Aug 13 06:41:54 PM PDT 24
Peak memory 207508 kb
Host smart-689e9dec-deed-4a9f-a27c-1da16f15a1d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825689427 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 362.usbdev_tx_rx_disruption.3825689427
Directory /workspace/362.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/363.usbdev_tx_rx_disruption.1817689567
Short name T3093
Test name
Test status
Simulation time 408608428 ps
CPU time 1.36 seconds
Started Aug 13 06:42:13 PM PDT 24
Finished Aug 13 06:42:14 PM PDT 24
Peak memory 207544 kb
Host smart-4f4e61b9-51cd-445e-afcb-f45c13060262
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817689567 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 363.usbdev_tx_rx_disruption.1817689567
Directory /workspace/363.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/364.usbdev_tx_rx_disruption.3577794336
Short name T1424
Test name
Test status
Simulation time 552677306 ps
CPU time 1.59 seconds
Started Aug 13 06:42:13 PM PDT 24
Finished Aug 13 06:42:15 PM PDT 24
Peak memory 207596 kb
Host smart-e43df606-8230-465e-8541-756e829d3b0f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577794336 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 364.usbdev_tx_rx_disruption.3577794336
Directory /workspace/364.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/365.usbdev_tx_rx_disruption.1735940070
Short name T2626
Test name
Test status
Simulation time 483040634 ps
CPU time 1.48 seconds
Started Aug 13 06:42:02 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207532 kb
Host smart-c5dfb5c9-bd14-4d4e-9ba2-5b3afbd8de84
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735940070 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 365.usbdev_tx_rx_disruption.1735940070
Directory /workspace/365.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/366.usbdev_tx_rx_disruption.1414161546
Short name T1637
Test name
Test status
Simulation time 578347712 ps
CPU time 1.64 seconds
Started Aug 13 06:42:08 PM PDT 24
Finished Aug 13 06:42:10 PM PDT 24
Peak memory 207580 kb
Host smart-aade87fd-e485-4123-95f4-d909f7812d7d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414161546 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 366.usbdev_tx_rx_disruption.1414161546
Directory /workspace/366.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/367.usbdev_tx_rx_disruption.3447465616
Short name T3119
Test name
Test status
Simulation time 527725732 ps
CPU time 1.56 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207612 kb
Host smart-fbfac9a6-d736-4428-8686-b1b994066452
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447465616 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 367.usbdev_tx_rx_disruption.3447465616
Directory /workspace/367.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/368.usbdev_tx_rx_disruption.3535993333
Short name T2503
Test name
Test status
Simulation time 609677008 ps
CPU time 1.77 seconds
Started Aug 13 06:42:38 PM PDT 24
Finished Aug 13 06:42:39 PM PDT 24
Peak memory 207524 kb
Host smart-7e75ad82-8721-4e90-ab05-f22cf7744914
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535993333 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 368.usbdev_tx_rx_disruption.3535993333
Directory /workspace/368.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/369.usbdev_tx_rx_disruption.2267455984
Short name T934
Test name
Test status
Simulation time 623911403 ps
CPU time 1.64 seconds
Started Aug 13 06:41:55 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207572 kb
Host smart-d740437b-691c-4975-98d1-9f704b0bee7e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267455984 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 369.usbdev_tx_rx_disruption.2267455984
Directory /workspace/369.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2244470439
Short name T1977
Test name
Test status
Simulation time 52856002 ps
CPU time 0.67 seconds
Started Aug 13 06:39:09 PM PDT 24
Finished Aug 13 06:39:10 PM PDT 24
Peak memory 207412 kb
Host smart-ef82f3dc-0174-4b5c-9c9e-804bbf8fe600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2244470439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2244470439
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3674250282
Short name T94
Test name
Test status
Simulation time 4896642577 ps
CPU time 7.26 seconds
Started Aug 13 06:39:05 PM PDT 24
Finished Aug 13 06:39:13 PM PDT 24
Peak memory 215952 kb
Host smart-c4da8b86-03fa-4f94-8c6b-20ae9b384501
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674250282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.3674250282
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3847342278
Short name T1749
Test name
Test status
Simulation time 15637500056 ps
CPU time 19.51 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:37 PM PDT 24
Peak memory 216020 kb
Host smart-9106084c-ffcf-491b-b0d0-cd9971566dab
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847342278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3847342278
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.1464435442
Short name T2744
Test name
Test status
Simulation time 24945278452 ps
CPU time 30.72 seconds
Started Aug 13 06:39:10 PM PDT 24
Finished Aug 13 06:39:41 PM PDT 24
Peak memory 215988 kb
Host smart-49e6eca4-95f8-4bf2-affa-0f0f23cfb236
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464435442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.1464435442
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3600220392
Short name T1563
Test name
Test status
Simulation time 187834518 ps
CPU time 0.95 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207436 kb
Host smart-5744b2fd-08f6-4863-bddf-044c608f861b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36002
20392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3600220392
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3608651063
Short name T930
Test name
Test status
Simulation time 151712597 ps
CPU time 0.91 seconds
Started Aug 13 06:39:05 PM PDT 24
Finished Aug 13 06:39:06 PM PDT 24
Peak memory 207576 kb
Host smart-869e67f3-0827-4756-9ac3-16f3366d7df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36086
51063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3608651063
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3732355785
Short name T2788
Test name
Test status
Simulation time 477164099 ps
CPU time 1.75 seconds
Started Aug 13 06:39:11 PM PDT 24
Finished Aug 13 06:39:12 PM PDT 24
Peak memory 207500 kb
Host smart-1afe56bd-70d4-4b6a-9087-9028ac53c91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323
55785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3732355785
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2984853698
Short name T1260
Test name
Test status
Simulation time 467062920 ps
CPU time 1.37 seconds
Started Aug 13 06:39:12 PM PDT 24
Finished Aug 13 06:39:13 PM PDT 24
Peak memory 207468 kb
Host smart-b345b630-d39b-47e5-bf0a-5cf1fe3fe244
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2984853698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2984853698
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1609630830
Short name T1647
Test name
Test status
Simulation time 20354158971 ps
CPU time 34.75 seconds
Started Aug 13 06:39:09 PM PDT 24
Finished Aug 13 06:39:44 PM PDT 24
Peak memory 207816 kb
Host smart-a882aa5c-4354-4a16-a36c-c2f1241bd692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16096
30830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1609630830
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.2257164965
Short name T2641
Test name
Test status
Simulation time 184652682 ps
CPU time 0.9 seconds
Started Aug 13 06:39:12 PM PDT 24
Finished Aug 13 06:39:13 PM PDT 24
Peak memory 207532 kb
Host smart-3ab53efb-c887-460d-a583-5ffb5feebf2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257164965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.2257164965
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2301202992
Short name T2004
Test name
Test status
Simulation time 918707451 ps
CPU time 2.3 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207572 kb
Host smart-0a0c0c4a-05c4-415d-912d-48020bd98683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23012
02992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2301202992
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1149966467
Short name T3363
Test name
Test status
Simulation time 158784463 ps
CPU time 0.85 seconds
Started Aug 13 06:39:13 PM PDT 24
Finished Aug 13 06:39:14 PM PDT 24
Peak memory 207532 kb
Host smart-fcd277c9-e924-4891-8bcd-c3e95ca880f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11499
66467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1149966467
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3081119923
Short name T2650
Test name
Test status
Simulation time 40507307 ps
CPU time 0.71 seconds
Started Aug 13 06:39:13 PM PDT 24
Finished Aug 13 06:39:14 PM PDT 24
Peak memory 207456 kb
Host smart-cbcafbbd-ae24-491e-baaa-8ce923e2cf64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30811
19923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3081119923
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3664378053
Short name T2351
Test name
Test status
Simulation time 912237087 ps
CPU time 2.36 seconds
Started Aug 13 06:39:09 PM PDT 24
Finished Aug 13 06:39:12 PM PDT 24
Peak memory 207800 kb
Host smart-bebb32ec-2182-4485-bfcf-e8f59af26c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36643
78053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3664378053
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_types.737020809
Short name T430
Test name
Test status
Simulation time 346161434 ps
CPU time 1.08 seconds
Started Aug 13 06:39:06 PM PDT 24
Finished Aug 13 06:39:07 PM PDT 24
Peak memory 207584 kb
Host smart-33540641-48ee-426d-b4b9-f675b503ef0f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=737020809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.737020809
Directory /workspace/37.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2033821211
Short name T3308
Test name
Test status
Simulation time 209258659 ps
CPU time 1.34 seconds
Started Aug 13 06:39:11 PM PDT 24
Finished Aug 13 06:39:13 PM PDT 24
Peak memory 207584 kb
Host smart-b4143d5d-09fa-4ef0-bad1-034c3a4f697f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20338
21211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2033821211
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2333653358
Short name T3430
Test name
Test status
Simulation time 227718618 ps
CPU time 1.1 seconds
Started Aug 13 06:39:15 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 215932 kb
Host smart-421b9abe-3016-488e-aa95-91c40264a02d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2333653358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2333653358
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2241860664
Short name T1182
Test name
Test status
Simulation time 139127206 ps
CPU time 0.86 seconds
Started Aug 13 06:39:05 PM PDT 24
Finished Aug 13 06:39:06 PM PDT 24
Peak memory 207472 kb
Host smart-08510aa2-e3b0-4dc1-a769-f7d12bb73192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22418
60664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2241860664
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3543799522
Short name T2454
Test name
Test status
Simulation time 242399151 ps
CPU time 1.03 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 207496 kb
Host smart-6d2101c6-980e-4ef0-8cb5-fd35cef7ef05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35437
99522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3543799522
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1390563401
Short name T2208
Test name
Test status
Simulation time 2672341668 ps
CPU time 27.03 seconds
Started Aug 13 06:39:03 PM PDT 24
Finished Aug 13 06:39:31 PM PDT 24
Peak memory 218268 kb
Host smart-ce7cc649-b4d3-4c0a-9c0c-1c2244c1cecf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1390563401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1390563401
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.1994246256
Short name T1310
Test name
Test status
Simulation time 4122639086 ps
CPU time 50.94 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207804 kb
Host smart-4b6da331-e782-48d9-b66d-fcac974cfb3f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1994246256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.1994246256
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3376442777
Short name T1729
Test name
Test status
Simulation time 217037068 ps
CPU time 0.89 seconds
Started Aug 13 06:39:04 PM PDT 24
Finished Aug 13 06:39:05 PM PDT 24
Peak memory 207604 kb
Host smart-24a55dc5-dcad-4cdd-aa37-4ead749faa86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33764
42777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3376442777
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2131304793
Short name T61
Test name
Test status
Simulation time 9844442859 ps
CPU time 16.09 seconds
Started Aug 13 06:39:03 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 207820 kb
Host smart-459334ec-f39b-41bf-9e14-5cabd2d322ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21313
04793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2131304793
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1358998274
Short name T1199
Test name
Test status
Simulation time 6072964254 ps
CPU time 8.38 seconds
Started Aug 13 06:39:11 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 216148 kb
Host smart-9832c805-cd17-4023-9cbd-34d1ee9c5c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13589
98274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1358998274
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1546448927
Short name T190
Test name
Test status
Simulation time 4532162134 ps
CPU time 45.9 seconds
Started Aug 13 06:39:03 PM PDT 24
Finished Aug 13 06:39:49 PM PDT 24
Peak memory 224176 kb
Host smart-9c6ccc7c-ee9b-4b16-b7bd-632c83e579c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1546448927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1546448927
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.4007307651
Short name T2226
Test name
Test status
Simulation time 1642568121 ps
CPU time 12.58 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:39:33 PM PDT 24
Peak memory 217480 kb
Host smart-c8d6f9ab-7c4e-4767-80d4-6d1ae2cdbdac
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4007307651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.4007307651
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1164638949
Short name T2191
Test name
Test status
Simulation time 325884163 ps
CPU time 1.06 seconds
Started Aug 13 06:39:10 PM PDT 24
Finished Aug 13 06:39:11 PM PDT 24
Peak memory 207396 kb
Host smart-ec5285c0-3598-405c-8fe8-a98c0a4c3c2a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1164638949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1164638949
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.616278170
Short name T2968
Test name
Test status
Simulation time 207699069 ps
CPU time 0.92 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:39:21 PM PDT 24
Peak memory 207500 kb
Host smart-ac4d46b7-a419-4913-b2fb-9a807714108b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61627
8170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.616278170
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1261741330
Short name T871
Test name
Test status
Simulation time 2440635180 ps
CPU time 69.42 seconds
Started Aug 13 06:39:12 PM PDT 24
Finished Aug 13 06:40:22 PM PDT 24
Peak memory 217292 kb
Host smart-5c789687-7950-4ac7-8a7a-5e433bce128e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1261741330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1261741330
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3369366509
Short name T2472
Test name
Test status
Simulation time 158696723 ps
CPU time 0.83 seconds
Started Aug 13 06:39:15 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 207480 kb
Host smart-1a150397-a72b-4825-ab7e-35de1890043e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3369366509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3369366509
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1989108804
Short name T1451
Test name
Test status
Simulation time 146140974 ps
CPU time 0.84 seconds
Started Aug 13 06:39:12 PM PDT 24
Finished Aug 13 06:39:13 PM PDT 24
Peak memory 207484 kb
Host smart-2689c432-ec89-46fd-b759-8c79eb26790d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19891
08804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1989108804
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2791182176
Short name T152
Test name
Test status
Simulation time 192727408 ps
CPU time 0.95 seconds
Started Aug 13 06:39:05 PM PDT 24
Finished Aug 13 06:39:06 PM PDT 24
Peak memory 207488 kb
Host smart-406ea571-6ba7-4f01-aed9-592857c4c155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27911
82176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2791182176
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3780464600
Short name T1646
Test name
Test status
Simulation time 188868069 ps
CPU time 0.94 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:15 PM PDT 24
Peak memory 207392 kb
Host smart-fe6c6d1d-0c8b-485f-a1e6-5eb302b17494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37804
64600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3780464600
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.729268444
Short name T2133
Test name
Test status
Simulation time 175890454 ps
CPU time 0.92 seconds
Started Aug 13 06:39:05 PM PDT 24
Finished Aug 13 06:39:06 PM PDT 24
Peak memory 207452 kb
Host smart-64398205-31da-4420-8241-b4d1512df7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72926
8444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.729268444
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3092562636
Short name T2432
Test name
Test status
Simulation time 141046801 ps
CPU time 0.83 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:15 PM PDT 24
Peak memory 207488 kb
Host smart-1eb8f1a5-5459-4e47-96ef-bdf4523d217d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30925
62636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3092562636
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.952929117
Short name T1153
Test name
Test status
Simulation time 154753573 ps
CPU time 0.88 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207568 kb
Host smart-551e5b20-81b9-4a5d-9200-57bf64e8ff04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95292
9117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.952929117
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.2287042855
Short name T237
Test name
Test status
Simulation time 200417021 ps
CPU time 1 seconds
Started Aug 13 06:39:04 PM PDT 24
Finished Aug 13 06:39:05 PM PDT 24
Peak memory 207592 kb
Host smart-7034ad33-a1ea-4d1c-b5ae-25c89714c9dd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2287042855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2287042855
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1835373965
Short name T2014
Test name
Test status
Simulation time 204044070 ps
CPU time 0.92 seconds
Started Aug 13 06:39:04 PM PDT 24
Finished Aug 13 06:39:05 PM PDT 24
Peak memory 207472 kb
Host smart-cd418c1f-3132-4727-ba5b-e4d4d23ebee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18353
73965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1835373965
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.195833063
Short name T2861
Test name
Test status
Simulation time 40313142 ps
CPU time 0.69 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:15 PM PDT 24
Peak memory 207568 kb
Host smart-af61b9b5-4b0f-489b-bd24-b786d030551d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
3063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.195833063
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3189876173
Short name T321
Test name
Test status
Simulation time 16509928285 ps
CPU time 39.47 seconds
Started Aug 13 06:39:12 PM PDT 24
Finished Aug 13 06:39:52 PM PDT 24
Peak memory 215956 kb
Host smart-d98b8666-2de4-47d8-ad99-f9e9b5b759b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31898
76173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3189876173
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1404556657
Short name T1088
Test name
Test status
Simulation time 186681545 ps
CPU time 0.9 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207552 kb
Host smart-fb7ff8a9-80e3-449a-bd0e-2ffb0e172443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14045
56657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1404556657
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1692655211
Short name T2315
Test name
Test status
Simulation time 183452447 ps
CPU time 0.95 seconds
Started Aug 13 06:39:13 PM PDT 24
Finished Aug 13 06:39:14 PM PDT 24
Peak memory 207492 kb
Host smart-d9c6baef-b0e9-49d7-9e4e-074bade67b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16926
55211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1692655211
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.749250110
Short name T2153
Test name
Test status
Simulation time 175432525 ps
CPU time 0.96 seconds
Started Aug 13 06:39:05 PM PDT 24
Finished Aug 13 06:39:06 PM PDT 24
Peak memory 207528 kb
Host smart-9f74b7d8-e0a0-47c6-a90e-0b36f3b7e802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74925
0110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.749250110
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2195964158
Short name T1086
Test name
Test status
Simulation time 145026076 ps
CPU time 0.85 seconds
Started Aug 13 06:39:05 PM PDT 24
Finished Aug 13 06:39:06 PM PDT 24
Peak memory 207500 kb
Host smart-ceea7344-006f-479a-a135-ae7e99673345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21959
64158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2195964158
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2183031681
Short name T257
Test name
Test status
Simulation time 157649491 ps
CPU time 0.85 seconds
Started Aug 13 06:39:11 PM PDT 24
Finished Aug 13 06:39:12 PM PDT 24
Peak memory 207392 kb
Host smart-f01d2d95-9a96-48d6-8413-17f377cd651d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21830
31681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2183031681
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_rx_full.2078162229
Short name T1776
Test name
Test status
Simulation time 373475286 ps
CPU time 1.24 seconds
Started Aug 13 06:39:15 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 207424 kb
Host smart-3d9cbbc3-7b64-4c89-81ff-7b5ba2f45b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20781
62229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.2078162229
Directory /workspace/37.usbdev_rx_full/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1275780430
Short name T555
Test name
Test status
Simulation time 167903040 ps
CPU time 0.84 seconds
Started Aug 13 06:39:09 PM PDT 24
Finished Aug 13 06:39:10 PM PDT 24
Peak memory 207540 kb
Host smart-01081ca6-7aa1-4a4a-94c9-64627d50ebf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12757
80430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1275780430
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2326862271
Short name T3200
Test name
Test status
Simulation time 149556702 ps
CPU time 0.84 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207492 kb
Host smart-af37abb6-8479-44c5-b3a2-1c5c5b516ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23268
62271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2326862271
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.4221773076
Short name T3047
Test name
Test status
Simulation time 244373484 ps
CPU time 1.07 seconds
Started Aug 13 06:39:13 PM PDT 24
Finished Aug 13 06:39:14 PM PDT 24
Peak memory 207492 kb
Host smart-fa4263e9-4c4a-4493-8479-3395436cd56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42217
73076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.4221773076
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2518098709
Short name T2005
Test name
Test status
Simulation time 3957528082 ps
CPU time 42 seconds
Started Aug 13 06:39:03 PM PDT 24
Finished Aug 13 06:39:46 PM PDT 24
Peak memory 217868 kb
Host smart-43f3c61b-071f-4247-95a3-486494f52e5a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2518098709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2518098709
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1741678651
Short name T2548
Test name
Test status
Simulation time 251442781 ps
CPU time 0.95 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207520 kb
Host smart-9f2e228c-b4fc-4f46-88bb-9ccd6e725e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
78651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1741678651
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1248926007
Short name T2705
Test name
Test status
Simulation time 177223294 ps
CPU time 0.89 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:15 PM PDT 24
Peak memory 207600 kb
Host smart-4ba71ab9-3fa9-46ed-8358-2718c70cf306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12489
26007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1248926007
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.1670424780
Short name T2719
Test name
Test status
Simulation time 329796685 ps
CPU time 1.22 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 207532 kb
Host smart-10e7ed1c-fb2c-4e65-8744-ed6b9d8889e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16704
24780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.1670424780
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2829666955
Short name T803
Test name
Test status
Simulation time 3215244134 ps
CPU time 93.68 seconds
Started Aug 13 06:39:12 PM PDT 24
Finished Aug 13 06:40:45 PM PDT 24
Peak memory 217576 kb
Host smart-58afcb44-ce99-4007-b971-7c74f5478871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28296
66955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2829666955
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.2970628198
Short name T2863
Test name
Test status
Simulation time 839388965 ps
CPU time 5.11 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 207684 kb
Host smart-4a47832f-df1d-4cfd-8245-256fe245669f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970628198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.2970628198
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_tx_rx_disruption.3081403863
Short name T1710
Test name
Test status
Simulation time 583785109 ps
CPU time 1.68 seconds
Started Aug 13 06:39:08 PM PDT 24
Finished Aug 13 06:39:10 PM PDT 24
Peak memory 207576 kb
Host smart-2b1031a8-2c91-48c5-821f-262404bb18f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081403863 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.usbdev_tx_rx_disruption.3081403863
Directory /workspace/37.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/370.usbdev_tx_rx_disruption.2176774574
Short name T2696
Test name
Test status
Simulation time 560186866 ps
CPU time 1.61 seconds
Started Aug 13 06:42:14 PM PDT 24
Finished Aug 13 06:42:16 PM PDT 24
Peak memory 207596 kb
Host smart-07eb1d56-15ba-408e-8b2b-24f59b744c7a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176774574 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 370.usbdev_tx_rx_disruption.2176774574
Directory /workspace/370.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/371.usbdev_tx_rx_disruption.3722453198
Short name T1246
Test name
Test status
Simulation time 582222458 ps
CPU time 1.62 seconds
Started Aug 13 06:42:38 PM PDT 24
Finished Aug 13 06:42:40 PM PDT 24
Peak memory 207612 kb
Host smart-b529c815-4f86-451f-9313-3b005e21cf80
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722453198 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 371.usbdev_tx_rx_disruption.3722453198
Directory /workspace/371.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/372.usbdev_tx_rx_disruption.864982844
Short name T2717
Test name
Test status
Simulation time 473070870 ps
CPU time 1.49 seconds
Started Aug 13 06:42:00 PM PDT 24
Finished Aug 13 06:42:01 PM PDT 24
Peak memory 207556 kb
Host smart-523b7dd6-c6e2-4d12-99bd-c5817cd03dea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864982844 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 372.usbdev_tx_rx_disruption.864982844
Directory /workspace/372.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/373.usbdev_tx_rx_disruption.196402954
Short name T936
Test name
Test status
Simulation time 512338664 ps
CPU time 1.51 seconds
Started Aug 13 06:42:05 PM PDT 24
Finished Aug 13 06:42:07 PM PDT 24
Peak memory 207556 kb
Host smart-3a70d8d2-7936-4a11-b251-dcb7ea2d06d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196402954 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 373.usbdev_tx_rx_disruption.196402954
Directory /workspace/373.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/374.usbdev_tx_rx_disruption.4120203972
Short name T1043
Test name
Test status
Simulation time 444719021 ps
CPU time 1.47 seconds
Started Aug 13 06:42:10 PM PDT 24
Finished Aug 13 06:42:11 PM PDT 24
Peak memory 207536 kb
Host smart-f71b4bf0-d112-4870-9a00-a798556eb4b0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120203972 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 374.usbdev_tx_rx_disruption.4120203972
Directory /workspace/374.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/375.usbdev_tx_rx_disruption.2790050907
Short name T2667
Test name
Test status
Simulation time 502367733 ps
CPU time 1.54 seconds
Started Aug 13 06:42:35 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 207560 kb
Host smart-dc98d4cc-9683-4b42-978e-62389231de6c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790050907 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 375.usbdev_tx_rx_disruption.2790050907
Directory /workspace/375.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/376.usbdev_tx_rx_disruption.160022145
Short name T2148
Test name
Test status
Simulation time 535335760 ps
CPU time 1.77 seconds
Started Aug 13 06:42:07 PM PDT 24
Finished Aug 13 06:42:08 PM PDT 24
Peak memory 207592 kb
Host smart-9247ed32-87d2-42f3-b8eb-52b44e7a20ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160022145 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 376.usbdev_tx_rx_disruption.160022145
Directory /workspace/376.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/377.usbdev_tx_rx_disruption.2388235921
Short name T2457
Test name
Test status
Simulation time 469989707 ps
CPU time 1.6 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207544 kb
Host smart-f2a637ae-cece-4a05-a9f4-39f0e1cab28b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388235921 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 377.usbdev_tx_rx_disruption.2388235921
Directory /workspace/377.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/378.usbdev_tx_rx_disruption.382028709
Short name T829
Test name
Test status
Simulation time 713443707 ps
CPU time 1.92 seconds
Started Aug 13 06:42:29 PM PDT 24
Finished Aug 13 06:42:31 PM PDT 24
Peak memory 207552 kb
Host smart-8abfde6e-6da3-4afb-bd9e-ed3a08bf7aea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382028709 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 378.usbdev_tx_rx_disruption.382028709
Directory /workspace/378.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/379.usbdev_tx_rx_disruption.613128643
Short name T710
Test name
Test status
Simulation time 486219244 ps
CPU time 1.43 seconds
Started Aug 13 06:42:08 PM PDT 24
Finished Aug 13 06:42:14 PM PDT 24
Peak memory 207632 kb
Host smart-4fc4fa72-cecf-4050-88f8-797a7d48c4f3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613128643 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 379.usbdev_tx_rx_disruption.613128643
Directory /workspace/379.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.3362773736
Short name T95
Test name
Test status
Simulation time 34096101 ps
CPU time 0.66 seconds
Started Aug 13 06:39:43 PM PDT 24
Finished Aug 13 06:39:44 PM PDT 24
Peak memory 207436 kb
Host smart-918a82a4-5f08-40c5-a43b-100cf47deec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3362773736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.3362773736
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2265549522
Short name T3557
Test name
Test status
Simulation time 5836657526 ps
CPU time 7.96 seconds
Started Aug 13 06:39:12 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 215988 kb
Host smart-79de0c81-55ac-4950-b39c-e5f4c60fcb81
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265549522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.2265549522
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.4115201001
Short name T1558
Test name
Test status
Simulation time 14086180682 ps
CPU time 20.83 seconds
Started Aug 13 06:39:11 PM PDT 24
Finished Aug 13 06:39:32 PM PDT 24
Peak memory 215988 kb
Host smart-d380ed3b-8b00-49ab-8d50-5891f38db9cb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115201001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.4115201001
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1669796474
Short name T1640
Test name
Test status
Simulation time 26194094153 ps
CPU time 37.72 seconds
Started Aug 13 06:39:06 PM PDT 24
Finished Aug 13 06:39:44 PM PDT 24
Peak memory 215984 kb
Host smart-0fe4736e-1051-439e-ae12-0df0cfaa5cab
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669796474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.1669796474
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2206965155
Short name T2959
Test name
Test status
Simulation time 179626598 ps
CPU time 0.84 seconds
Started Aug 13 06:39:03 PM PDT 24
Finished Aug 13 06:39:03 PM PDT 24
Peak memory 207444 kb
Host smart-10354fcc-5335-4675-bb55-07fcf7f10ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22069
65155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2206965155
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.985596914
Short name T77
Test name
Test status
Simulation time 174894891 ps
CPU time 0.88 seconds
Started Aug 13 06:39:10 PM PDT 24
Finished Aug 13 06:39:11 PM PDT 24
Peak memory 207528 kb
Host smart-0e7c09d7-d73c-4d3f-ab36-452d0b089dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98559
6914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.985596914
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.3352326582
Short name T2475
Test name
Test status
Simulation time 464434374 ps
CPU time 1.63 seconds
Started Aug 13 06:39:11 PM PDT 24
Finished Aug 13 06:39:13 PM PDT 24
Peak memory 207512 kb
Host smart-83c6cd6c-7fe5-4a6f-bd04-784e6c7f7ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33523
26582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.3352326582
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3436876426
Short name T2319
Test name
Test status
Simulation time 739275502 ps
CPU time 2.15 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 207420 kb
Host smart-b505a21d-117a-4764-9996-045c66c3fdc2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3436876426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3436876426
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.724217468
Short name T2627
Test name
Test status
Simulation time 49551530987 ps
CPU time 77.74 seconds
Started Aug 13 06:39:15 PM PDT 24
Finished Aug 13 06:40:32 PM PDT 24
Peak memory 207736 kb
Host smart-702e3e20-13bc-44f2-b3fd-ae436532746d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72421
7468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.724217468
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.2396734247
Short name T1764
Test name
Test status
Simulation time 721192212 ps
CPU time 15.24 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:29 PM PDT 24
Peak memory 207776 kb
Host smart-13ed8051-d4ef-4054-a47d-a46e59981571
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396734247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.2396734247
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.1264913506
Short name T3165
Test name
Test status
Simulation time 844499914 ps
CPU time 2.26 seconds
Started Aug 13 06:39:15 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207556 kb
Host smart-b62da757-5258-4037-a0a6-6d1195fd2fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12649
13506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1264913506
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.93515822
Short name T1324
Test name
Test status
Simulation time 147597023 ps
CPU time 0.81 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 207480 kb
Host smart-0ad238a9-ec1a-4a2e-9af1-ab635c235127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93515
822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.93515822
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.261347168
Short name T1459
Test name
Test status
Simulation time 40672656 ps
CPU time 0.7 seconds
Started Aug 13 06:39:15 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 207420 kb
Host smart-bd3fe800-6816-46da-aef7-714faf749881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26134
7168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.261347168
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2364229735
Short name T2967
Test name
Test status
Simulation time 738380881 ps
CPU time 2.14 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 207672 kb
Host smart-979f0c3e-8840-48f0-89f8-a0940c500362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23642
29735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2364229735
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_types.3409385098
Short name T408
Test name
Test status
Simulation time 284201288 ps
CPU time 1.06 seconds
Started Aug 13 06:39:27 PM PDT 24
Finished Aug 13 06:39:29 PM PDT 24
Peak memory 207448 kb
Host smart-f31e4c9c-18e4-4b82-999d-c79c93950a30
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3409385098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.3409385098
Directory /workspace/38.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3574971071
Short name T2956
Test name
Test status
Simulation time 185448290 ps
CPU time 2.42 seconds
Started Aug 13 06:39:35 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 207640 kb
Host smart-28ec67f8-1311-42e3-b8b8-a2ed5261dc9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35749
71071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3574971071
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2906645251
Short name T558
Test name
Test status
Simulation time 296610966 ps
CPU time 1.27 seconds
Started Aug 13 06:39:21 PM PDT 24
Finished Aug 13 06:39:22 PM PDT 24
Peak memory 215928 kb
Host smart-c6343fa0-55ac-4900-ae5b-ee82b3c1fbdd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2906645251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2906645251
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.140611281
Short name T1416
Test name
Test status
Simulation time 140646047 ps
CPU time 0.86 seconds
Started Aug 13 06:39:34 PM PDT 24
Finished Aug 13 06:39:35 PM PDT 24
Peak memory 207488 kb
Host smart-435c9f43-5ce3-41a9-bb0b-0a1cee26a798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14061
1281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.140611281
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1843587773
Short name T3021
Test name
Test status
Simulation time 166258273 ps
CPU time 0.91 seconds
Started Aug 13 06:39:59 PM PDT 24
Finished Aug 13 06:40:00 PM PDT 24
Peak memory 207528 kb
Host smart-7d682b3b-a0b9-4fcc-b735-1c1cbe793e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18435
87773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1843587773
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.2336107842
Short name T721
Test name
Test status
Simulation time 3996661790 ps
CPU time 114.88 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 216016 kb
Host smart-0cbb7920-1b85-4c45-9c56-ed3e80a17c85
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2336107842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.2336107842
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.1178247767
Short name T1946
Test name
Test status
Simulation time 7115881105 ps
CPU time 48.59 seconds
Started Aug 13 06:39:23 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207820 kb
Host smart-c98505c2-91d0-417e-9202-699feeb80025
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1178247767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.1178247767
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3900251537
Short name T3302
Test name
Test status
Simulation time 204145580 ps
CPU time 0.93 seconds
Started Aug 13 06:39:31 PM PDT 24
Finished Aug 13 06:39:32 PM PDT 24
Peak memory 207604 kb
Host smart-a586c37b-e549-44f0-b81a-505cc0dd1e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39002
51537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3900251537
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1781736025
Short name T2640
Test name
Test status
Simulation time 33240253247 ps
CPU time 52.22 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207844 kb
Host smart-8e6dfef4-5423-4428-9af4-6708c02d25a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17817
36025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1781736025
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3442352871
Short name T2105
Test name
Test status
Simulation time 11098084621 ps
CPU time 14.66 seconds
Started Aug 13 06:39:22 PM PDT 24
Finished Aug 13 06:39:37 PM PDT 24
Peak memory 207840 kb
Host smart-62bfa8aa-943c-4d9a-9e9f-bd9e98ac04e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34423
52871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3442352871
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1049071890
Short name T2516
Test name
Test status
Simulation time 2466059902 ps
CPU time 73 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:40:32 PM PDT 24
Peak memory 215928 kb
Host smart-8473d00f-441a-4549-9507-ed00a1bc17d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1049071890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1049071890
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3958418848
Short name T2784
Test name
Test status
Simulation time 3034907930 ps
CPU time 85.24 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:40:41 PM PDT 24
Peak memory 217224 kb
Host smart-378bfe29-a32d-48e2-bf81-a9ebab824856
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3958418848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3958418848
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.36252826
Short name T2547
Test name
Test status
Simulation time 251890313 ps
CPU time 0.99 seconds
Started Aug 13 06:39:25 PM PDT 24
Finished Aug 13 06:39:26 PM PDT 24
Peak memory 207532 kb
Host smart-cbbd63bb-352b-466b-8a5a-c8bade3355e5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=36252826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.36252826
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1200909622
Short name T2704
Test name
Test status
Simulation time 213393947 ps
CPU time 0.98 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 207460 kb
Host smart-894febb3-1ab3-4a0e-8e1c-ddd230d28a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12009
09622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1200909622
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.3953662947
Short name T3551
Test name
Test status
Simulation time 2662263194 ps
CPU time 74.68 seconds
Started Aug 13 06:39:24 PM PDT 24
Finished Aug 13 06:40:39 PM PDT 24
Peak memory 215864 kb
Host smart-e150a12e-0667-428c-80c1-b3d9d15df70a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3953662947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.3953662947
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2518934052
Short name T2608
Test name
Test status
Simulation time 157143192 ps
CPU time 0.94 seconds
Started Aug 13 06:39:24 PM PDT 24
Finished Aug 13 06:39:25 PM PDT 24
Peak memory 207544 kb
Host smart-4fdfc016-dd15-45d0-b8fe-5f30668fcaa2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2518934052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2518934052
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.914773726
Short name T2465
Test name
Test status
Simulation time 202875016 ps
CPU time 0.9 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207492 kb
Host smart-90c4df22-df12-4c80-9bd8-413ebbdd72e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91477
3726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.914773726
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3294203471
Short name T144
Test name
Test status
Simulation time 233952259 ps
CPU time 0.98 seconds
Started Aug 13 06:39:35 PM PDT 24
Finished Aug 13 06:39:36 PM PDT 24
Peak memory 207392 kb
Host smart-484f92ed-e3e2-4478-bc32-c006acd34018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32942
03471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3294203471
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2579678084
Short name T2489
Test name
Test status
Simulation time 168702313 ps
CPU time 0.88 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 207424 kb
Host smart-4a49426d-5228-408f-84a3-67485092e14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25796
78084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2579678084
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2567729537
Short name T2818
Test name
Test status
Simulation time 169785400 ps
CPU time 0.89 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:39:21 PM PDT 24
Peak memory 207488 kb
Host smart-04c76957-7d7e-4e1b-8c45-abc62265a727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25677
29537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2567729537
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.65543733
Short name T1668
Test name
Test status
Simulation time 184440925 ps
CPU time 0.87 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 207524 kb
Host smart-faae9ff1-12c8-4bf3-a46d-7e0a2ad57492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65543
733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.65543733
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.83068614
Short name T2450
Test name
Test status
Simulation time 150062284 ps
CPU time 0.85 seconds
Started Aug 13 06:39:21 PM PDT 24
Finished Aug 13 06:39:22 PM PDT 24
Peak memory 207604 kb
Host smart-29879ab6-356b-4113-ba06-6403e0f254ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83068
614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.83068614
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2855432834
Short name T3243
Test name
Test status
Simulation time 196141599 ps
CPU time 0.98 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207560 kb
Host smart-f5f59711-2d84-43ae-b5f7-68d36e053630
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2855432834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2855432834
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1725237517
Short name T1808
Test name
Test status
Simulation time 151462273 ps
CPU time 0.84 seconds
Started Aug 13 06:39:24 PM PDT 24
Finished Aug 13 06:39:25 PM PDT 24
Peak memory 207464 kb
Host smart-9f35b1a8-e7f6-4875-848e-e2d8cea5f01a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17252
37517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1725237517
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1616477496
Short name T3213
Test name
Test status
Simulation time 37414562 ps
CPU time 0.74 seconds
Started Aug 13 06:39:15 PM PDT 24
Finished Aug 13 06:39:16 PM PDT 24
Peak memory 207532 kb
Host smart-a1068bd3-18ff-40b4-b684-36914a0ddfbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16164
77496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1616477496
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1651982314
Short name T3428
Test name
Test status
Simulation time 21751491250 ps
CPU time 57.24 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:40:16 PM PDT 24
Peak memory 216032 kb
Host smart-73ca6b93-55fa-4f78-b87e-186b552f1805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16519
82314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1651982314
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3245464715
Short name T577
Test name
Test status
Simulation time 178853927 ps
CPU time 0.92 seconds
Started Aug 13 06:39:38 PM PDT 24
Finished Aug 13 06:39:39 PM PDT 24
Peak memory 207500 kb
Host smart-739f0c17-f958-46f9-bb75-893c5ca0ed37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32454
64715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3245464715
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2438787722
Short name T2141
Test name
Test status
Simulation time 169127657 ps
CPU time 0.89 seconds
Started Aug 13 06:39:14 PM PDT 24
Finished Aug 13 06:39:15 PM PDT 24
Peak memory 207508 kb
Host smart-007f6b8f-479c-4c76-936e-559f2b970a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24387
87722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2438787722
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.1143588172
Short name T530
Test name
Test status
Simulation time 182759185 ps
CPU time 0.87 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 207440 kb
Host smart-5f962f6f-5abb-4840-aecf-6dd7fb5ba3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11435
88172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.1143588172
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1942314326
Short name T1062
Test name
Test status
Simulation time 201226137 ps
CPU time 1 seconds
Started Aug 13 06:39:26 PM PDT 24
Finished Aug 13 06:39:27 PM PDT 24
Peak memory 207508 kb
Host smart-2ab31c19-3975-45e6-9ace-2b5f5d95c112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423
14326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1942314326
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.758273977
Short name T1814
Test name
Test status
Simulation time 152962520 ps
CPU time 0.89 seconds
Started Aug 13 06:39:36 PM PDT 24
Finished Aug 13 06:39:37 PM PDT 24
Peak memory 207456 kb
Host smart-08040b67-42ae-4dc5-839d-13fd4867ac1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75827
3977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.758273977
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_rx_full.3288798377
Short name T3429
Test name
Test status
Simulation time 352850333 ps
CPU time 1.19 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 207500 kb
Host smart-53ff5720-29e5-4d66-96e5-b890a34370ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32887
98377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.3288798377
Directory /workspace/38.usbdev_rx_full/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.423947059
Short name T1665
Test name
Test status
Simulation time 214416188 ps
CPU time 0.92 seconds
Started Aug 13 06:39:23 PM PDT 24
Finished Aug 13 06:39:24 PM PDT 24
Peak memory 207480 kb
Host smart-0b3d7dbd-fc4c-4dd2-a3dd-7ddbfdb37b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42394
7059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.423947059
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2386045738
Short name T472
Test name
Test status
Simulation time 143540687 ps
CPU time 0.88 seconds
Started Aug 13 06:39:32 PM PDT 24
Finished Aug 13 06:39:33 PM PDT 24
Peak memory 207516 kb
Host smart-b81b9bc0-1274-4802-9708-c152a82b1c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23860
45738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2386045738
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3746449086
Short name T1956
Test name
Test status
Simulation time 204234302 ps
CPU time 0.99 seconds
Started Aug 13 06:39:16 PM PDT 24
Finished Aug 13 06:39:17 PM PDT 24
Peak memory 207496 kb
Host smart-208b5f97-6d8d-4c9f-8df8-414562c39ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37464
49086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3746449086
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.325265170
Short name T769
Test name
Test status
Simulation time 1710901508 ps
CPU time 17.22 seconds
Started Aug 13 06:39:25 PM PDT 24
Finished Aug 13 06:39:42 PM PDT 24
Peak memory 216680 kb
Host smart-2d558fef-5b06-4239-83f7-c60539a61dcf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=325265170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.325265170
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.771811655
Short name T2444
Test name
Test status
Simulation time 175208196 ps
CPU time 0.88 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207440 kb
Host smart-4c765f62-1cc3-46d3-a247-596c27231676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77181
1655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.771811655
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1734536967
Short name T2292
Test name
Test status
Simulation time 170649234 ps
CPU time 0.88 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:39:21 PM PDT 24
Peak memory 207596 kb
Host smart-a388a63c-7a53-4a68-94a3-cf7ae7ae5e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17345
36967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1734536967
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.1302913877
Short name T3319
Test name
Test status
Simulation time 505070312 ps
CPU time 1.56 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 207576 kb
Host smart-bb40e600-077f-486c-b7e7-a4a5fccfc68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13029
13877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.1302913877
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.233731350
Short name T5
Test name
Test status
Simulation time 2761526862 ps
CPU time 22.18 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:42 PM PDT 24
Peak memory 207840 kb
Host smart-1c424fc5-3a08-4b1a-a89c-85bbff002309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23373
1350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.233731350
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.1828804048
Short name T2800
Test name
Test status
Simulation time 209938606 ps
CPU time 1.01 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207464 kb
Host smart-1c6bac89-8edf-4e82-99fd-ff9ce0389f5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828804048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.1828804048
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_tx_rx_disruption.722379911
Short name T1339
Test name
Test status
Simulation time 588984762 ps
CPU time 1.75 seconds
Started Aug 13 06:39:22 PM PDT 24
Finished Aug 13 06:39:24 PM PDT 24
Peak memory 207588 kb
Host smart-d1095289-a6b4-4044-ad2b-a17ca3eba276
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722379911 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.usbdev_tx_rx_disruption.722379911
Directory /workspace/38.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/380.usbdev_tx_rx_disruption.878405070
Short name T3183
Test name
Test status
Simulation time 507340667 ps
CPU time 1.6 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 207552 kb
Host smart-d8318ebe-e982-4eec-93cd-434e21ecf238
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878405070 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 380.usbdev_tx_rx_disruption.878405070
Directory /workspace/380.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/381.usbdev_tx_rx_disruption.3734747849
Short name T233
Test name
Test status
Simulation time 475330234 ps
CPU time 1.53 seconds
Started Aug 13 06:42:12 PM PDT 24
Finished Aug 13 06:42:13 PM PDT 24
Peak memory 207532 kb
Host smart-31e871aa-99a6-4ba2-b413-b57c3957dca6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734747849 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 381.usbdev_tx_rx_disruption.3734747849
Directory /workspace/381.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/382.usbdev_tx_rx_disruption.4183852996
Short name T1204
Test name
Test status
Simulation time 552270842 ps
CPU time 1.62 seconds
Started Aug 13 06:42:03 PM PDT 24
Finished Aug 13 06:42:05 PM PDT 24
Peak memory 207468 kb
Host smart-408913dd-8ec4-44c5-88a0-89b27129ffd0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183852996 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 382.usbdev_tx_rx_disruption.4183852996
Directory /workspace/382.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/383.usbdev_tx_rx_disruption.2328537634
Short name T3531
Test name
Test status
Simulation time 590906505 ps
CPU time 1.58 seconds
Started Aug 13 06:42:03 PM PDT 24
Finished Aug 13 06:42:04 PM PDT 24
Peak memory 207596 kb
Host smart-7dd86503-5936-42f6-a1bf-ec11120ba1d2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328537634 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 383.usbdev_tx_rx_disruption.2328537634
Directory /workspace/383.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/384.usbdev_tx_rx_disruption.1833990498
Short name T1555
Test name
Test status
Simulation time 485370790 ps
CPU time 1.5 seconds
Started Aug 13 06:42:05 PM PDT 24
Finished Aug 13 06:42:06 PM PDT 24
Peak memory 207512 kb
Host smart-0c47b105-8c2d-4e4d-8eb8-abdad160cc71
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833990498 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 384.usbdev_tx_rx_disruption.1833990498
Directory /workspace/384.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/385.usbdev_tx_rx_disruption.3041677025
Short name T880
Test name
Test status
Simulation time 550493502 ps
CPU time 1.53 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:59 PM PDT 24
Peak memory 207504 kb
Host smart-38bda18e-e720-4250-982b-b3354df19fff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041677025 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 385.usbdev_tx_rx_disruption.3041677025
Directory /workspace/385.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/386.usbdev_tx_rx_disruption.3983078817
Short name T2305
Test name
Test status
Simulation time 424131620 ps
CPU time 1.33 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207588 kb
Host smart-d2576aee-9c68-45a4-af41-4471565106aa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983078817 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 386.usbdev_tx_rx_disruption.3983078817
Directory /workspace/386.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/387.usbdev_tx_rx_disruption.633296118
Short name T3024
Test name
Test status
Simulation time 450799217 ps
CPU time 1.48 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207524 kb
Host smart-abc51738-cb8a-4245-8074-4f834e842f08
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633296118 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 387.usbdev_tx_rx_disruption.633296118
Directory /workspace/387.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/388.usbdev_tx_rx_disruption.3413269261
Short name T1005
Test name
Test status
Simulation time 720610975 ps
CPU time 1.8 seconds
Started Aug 13 06:42:11 PM PDT 24
Finished Aug 13 06:42:13 PM PDT 24
Peak memory 207596 kb
Host smart-7987dad3-4c4b-48b6-9f0f-5a05a94df578
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413269261 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 388.usbdev_tx_rx_disruption.3413269261
Directory /workspace/388.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/389.usbdev_tx_rx_disruption.4245783495
Short name T1261
Test name
Test status
Simulation time 548423579 ps
CPU time 1.43 seconds
Started Aug 13 06:42:39 PM PDT 24
Finished Aug 13 06:42:40 PM PDT 24
Peak memory 207592 kb
Host smart-e49a204e-6801-4d02-a745-a862cbb49662
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245783495 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 389.usbdev_tx_rx_disruption.4245783495
Directory /workspace/389.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1823342762
Short name T3262
Test name
Test status
Simulation time 44899268 ps
CPU time 0.67 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207488 kb
Host smart-4a9477b5-e5d2-4ecd-b147-077d67f6687d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1823342762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1823342762
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3263436069
Short name T588
Test name
Test status
Simulation time 5224296058 ps
CPU time 7.24 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:26 PM PDT 24
Peak memory 215980 kb
Host smart-3529a8bc-7b31-4f09-9215-c82be121e35e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263436069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.3263436069
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2559233207
Short name T274
Test name
Test status
Simulation time 20721755390 ps
CPU time 23.01 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:39:43 PM PDT 24
Peak memory 207828 kb
Host smart-ada370da-afa0-43c6-8c4b-6d4944932e7f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559233207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2559233207
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3296429219
Short name T1413
Test name
Test status
Simulation time 24856646359 ps
CPU time 31.3 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:39:51 PM PDT 24
Peak memory 216032 kb
Host smart-2099a2f7-bffb-4468-8b95-137a118754c2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296429219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.3296429219
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3355969030
Short name T1739
Test name
Test status
Simulation time 151200877 ps
CPU time 0.82 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:39:21 PM PDT 24
Peak memory 207456 kb
Host smart-c5237bfc-9437-4687-9a6f-5e4ed240799d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33559
69030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3355969030
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1557804536
Short name T2333
Test name
Test status
Simulation time 147596033 ps
CPU time 0.88 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 207484 kb
Host smart-25b6aaa3-2542-479d-b0dd-0a0860fee970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15578
04536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1557804536
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.2088339386
Short name T653
Test name
Test status
Simulation time 314147973 ps
CPU time 1.28 seconds
Started Aug 13 06:39:36 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 207564 kb
Host smart-ebaa2669-8338-4282-bf02-69552adebc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20883
39386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2088339386
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1941485101
Short name T1541
Test name
Test status
Simulation time 1103544676 ps
CPU time 2.86 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:22 PM PDT 24
Peak memory 207704 kb
Host smart-a1d276a8-077c-4617-9611-47a52c633138
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1941485101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1941485101
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.490914789
Short name T2675
Test name
Test status
Simulation time 27122044785 ps
CPU time 41.23 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:39:59 PM PDT 24
Peak memory 207760 kb
Host smart-ff6f8539-bc3b-4aac-b838-1ba995ba2f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49091
4789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.490914789
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.4173622470
Short name T2893
Test name
Test status
Simulation time 4900541599 ps
CPU time 35.91 seconds
Started Aug 13 06:39:24 PM PDT 24
Finished Aug 13 06:40:00 PM PDT 24
Peak memory 207788 kb
Host smart-1b2859dc-dd3b-4f14-9aeb-967c65129fab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173622470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.4173622470
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1960453669
Short name T1810
Test name
Test status
Simulation time 392814733 ps
CPU time 1.32 seconds
Started Aug 13 06:39:33 PM PDT 24
Finished Aug 13 06:39:35 PM PDT 24
Peak memory 207548 kb
Host smart-c86c1f6e-df7b-49e7-b475-32cc6e8b0a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19604
53669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1960453669
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3428260724
Short name T3349
Test name
Test status
Simulation time 133507238 ps
CPU time 0.82 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:39:21 PM PDT 24
Peak memory 207556 kb
Host smart-14be9762-97e0-4b44-b56f-0af965e0bcb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34282
60724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3428260724
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1969122122
Short name T3033
Test name
Test status
Simulation time 39998641 ps
CPU time 0.78 seconds
Started Aug 13 06:39:27 PM PDT 24
Finished Aug 13 06:39:28 PM PDT 24
Peak memory 207412 kb
Host smart-761da44a-d643-4645-b390-1a7f34fcafa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19691
22122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1969122122
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3285238164
Short name T1174
Test name
Test status
Simulation time 921434840 ps
CPU time 2.78 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:39:21 PM PDT 24
Peak memory 207748 kb
Host smart-466cb6a3-40c7-4481-b290-1399d00bb9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32852
38164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3285238164
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_types.8890347
Short name T3450
Test name
Test status
Simulation time 411250161 ps
CPU time 1.3 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 207548 kb
Host smart-d5682509-8f76-4ed0-bde5-8ecfb23a239a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=8890347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.8890347
Directory /workspace/39.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.438045867
Short name T1269
Test name
Test status
Simulation time 169079686 ps
CPU time 1.6 seconds
Started Aug 13 06:39:26 PM PDT 24
Finished Aug 13 06:39:27 PM PDT 24
Peak memory 207692 kb
Host smart-bed33f3a-0f65-4628-a261-5f53c70145b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43804
5867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.438045867
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.331584173
Short name T1342
Test name
Test status
Simulation time 179384058 ps
CPU time 0.96 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207504 kb
Host smart-15663e3c-3249-4e69-a310-6b823148e8f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=331584173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.331584173
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1623090691
Short name T1253
Test name
Test status
Simulation time 146063097 ps
CPU time 0.85 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:39:21 PM PDT 24
Peak memory 207412 kb
Host smart-4afd8155-f710-4072-a6e5-61564c36a831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16230
90691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1623090691
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2693216132
Short name T159
Test name
Test status
Simulation time 190479509 ps
CPU time 0.94 seconds
Started Aug 13 06:39:30 PM PDT 24
Finished Aug 13 06:39:31 PM PDT 24
Peak memory 207444 kb
Host smart-d5e9bf54-d5fd-472c-adb7-b81a748ff054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26932
16132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2693216132
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.1909197206
Short name T1137
Test name
Test status
Simulation time 5115301586 ps
CPU time 146.75 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 217776 kb
Host smart-b21f281e-9bd1-42d6-9982-cf03109199fe
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1909197206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.1909197206
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.3567169607
Short name T2739
Test name
Test status
Simulation time 10762018235 ps
CPU time 79.32 seconds
Started Aug 13 06:39:22 PM PDT 24
Finished Aug 13 06:40:41 PM PDT 24
Peak memory 207796 kb
Host smart-bed35d32-820c-45c8-8032-015c42ee846c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3567169607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.3567169607
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.4106334740
Short name T984
Test name
Test status
Simulation time 180670978 ps
CPU time 0.92 seconds
Started Aug 13 06:39:23 PM PDT 24
Finished Aug 13 06:39:24 PM PDT 24
Peak memory 207540 kb
Host smart-a04f49c5-3ffe-4253-8c46-fc344db04187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41063
34740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.4106334740
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2432203594
Short name T906
Test name
Test status
Simulation time 28397736803 ps
CPU time 52.96 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 216716 kb
Host smart-781e7284-e5d2-4f87-95fe-837a728420f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24322
03594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2432203594
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3307764227
Short name T1681
Test name
Test status
Simulation time 8335478948 ps
CPU time 12.34 seconds
Started Aug 13 06:39:48 PM PDT 24
Finished Aug 13 06:40:01 PM PDT 24
Peak memory 207860 kb
Host smart-ba342f74-9498-4493-9137-54bcb2f92e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33077
64227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3307764227
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2465131917
Short name T902
Test name
Test status
Simulation time 3384759111 ps
CPU time 96.17 seconds
Started Aug 13 06:39:20 PM PDT 24
Finished Aug 13 06:40:57 PM PDT 24
Peak memory 215948 kb
Host smart-28a7e666-85cd-4cc1-ad2b-31b28e52195a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2465131917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2465131917
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.390304151
Short name T3409
Test name
Test status
Simulation time 4322322881 ps
CPU time 124.47 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:41:51 PM PDT 24
Peak memory 216008 kb
Host smart-8a75b4a2-dcbc-4abb-8fcd-da69f24cff1a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=390304151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.390304151
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3248016322
Short name T2539
Test name
Test status
Simulation time 253322335 ps
CPU time 1.04 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:39:48 PM PDT 24
Peak memory 207532 kb
Host smart-c90b016f-2921-4e78-8a6a-7510de6f91ea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3248016322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3248016322
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3945274551
Short name T901
Test name
Test status
Simulation time 187553492 ps
CPU time 0.92 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 207512 kb
Host smart-c583c922-29ff-4b49-ba6a-4d3d85a9aefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39452
74551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3945274551
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3885942991
Short name T2922
Test name
Test status
Simulation time 2606667454 ps
CPU time 20.35 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 216204 kb
Host smart-b647f35f-af51-4a76-8f7b-660a213aa94e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3885942991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3885942991
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.1880058970
Short name T1259
Test name
Test status
Simulation time 215527313 ps
CPU time 0.92 seconds
Started Aug 13 06:39:27 PM PDT 24
Finished Aug 13 06:39:28 PM PDT 24
Peak memory 207540 kb
Host smart-708a9746-7057-40a6-bd2b-fae4efd941d5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1880058970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.1880058970
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3821104782
Short name T2835
Test name
Test status
Simulation time 159417216 ps
CPU time 0.95 seconds
Started Aug 13 06:39:28 PM PDT 24
Finished Aug 13 06:39:29 PM PDT 24
Peak memory 207516 kb
Host smart-81a393d6-38dc-43fd-b2ab-442345b47cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38211
04782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3821104782
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3013686484
Short name T153
Test name
Test status
Simulation time 240526399 ps
CPU time 0.99 seconds
Started Aug 13 06:39:34 PM PDT 24
Finished Aug 13 06:39:36 PM PDT 24
Peak memory 207516 kb
Host smart-cafe6b1d-f2af-4d28-a346-ca89f1c8bfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30136
86484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3013686484
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1845340137
Short name T841
Test name
Test status
Simulation time 154128841 ps
CPU time 0.89 seconds
Started Aug 13 06:39:30 PM PDT 24
Finished Aug 13 06:39:31 PM PDT 24
Peak memory 207512 kb
Host smart-82ae0e04-09ad-4bea-82b0-2431afcca163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18453
40137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1845340137
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1701144792
Short name T1400
Test name
Test status
Simulation time 162737841 ps
CPU time 0.89 seconds
Started Aug 13 06:39:23 PM PDT 24
Finished Aug 13 06:39:24 PM PDT 24
Peak memory 207440 kb
Host smart-ff5dd1dc-970f-485b-9ced-ab17b016a1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17011
44792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1701144792
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.4040673151
Short name T2527
Test name
Test status
Simulation time 242426132 ps
CPU time 0.93 seconds
Started Aug 13 06:39:24 PM PDT 24
Finished Aug 13 06:39:25 PM PDT 24
Peak memory 207616 kb
Host smart-5362de0a-d519-4850-a564-93af25bcbca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40406
73151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.4040673151
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3161680087
Short name T195
Test name
Test status
Simulation time 148672778 ps
CPU time 0.88 seconds
Started Aug 13 06:39:26 PM PDT 24
Finished Aug 13 06:39:27 PM PDT 24
Peak memory 207600 kb
Host smart-ad4cd357-22ac-4c85-af72-933bf1d5b700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31616
80087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3161680087
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.241678774
Short name T3088
Test name
Test status
Simulation time 222906131 ps
CPU time 1.03 seconds
Started Aug 13 06:39:21 PM PDT 24
Finished Aug 13 06:39:22 PM PDT 24
Peak memory 207524 kb
Host smart-acabc02a-7b47-4d7f-9921-9381f450ab1f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=241678774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.241678774
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2006715629
Short name T1441
Test name
Test status
Simulation time 143088987 ps
CPU time 0.85 seconds
Started Aug 13 06:39:33 PM PDT 24
Finished Aug 13 06:39:34 PM PDT 24
Peak memory 207404 kb
Host smart-c0ad35bb-dd37-43fb-a006-fb856f9d09be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20067
15629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2006715629
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1594180647
Short name T3173
Test name
Test status
Simulation time 59105529 ps
CPU time 0.73 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 207504 kb
Host smart-856769f2-dd4d-4b8f-bcaa-e859a6118233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15941
80647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1594180647
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1736159686
Short name T3247
Test name
Test status
Simulation time 6689129121 ps
CPU time 16.61 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:34 PM PDT 24
Peak memory 215932 kb
Host smart-8c8bbd59-e960-4746-bc24-a21a519ada31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17361
59686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1736159686
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.4232707551
Short name T2743
Test name
Test status
Simulation time 225659689 ps
CPU time 0.94 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:20 PM PDT 24
Peak memory 207608 kb
Host smart-9d0b6423-4ec0-4c4f-b531-26e85fd938a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42327
07551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.4232707551
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3842582392
Short name T563
Test name
Test status
Simulation time 160771746 ps
CPU time 0.94 seconds
Started Aug 13 06:39:36 PM PDT 24
Finished Aug 13 06:39:37 PM PDT 24
Peak memory 207512 kb
Host smart-de1d43d5-55fb-4bbd-8f31-477bb6a9f643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38425
82392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3842582392
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.4054111497
Short name T158
Test name
Test status
Simulation time 186422505 ps
CPU time 0.97 seconds
Started Aug 13 06:39:22 PM PDT 24
Finished Aug 13 06:39:23 PM PDT 24
Peak memory 207536 kb
Host smart-47c23354-4cf1-4766-b407-51644eaf57ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40541
11497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.4054111497
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3121673861
Short name T2104
Test name
Test status
Simulation time 165209525 ps
CPU time 0.88 seconds
Started Aug 13 06:39:30 PM PDT 24
Finished Aug 13 06:39:31 PM PDT 24
Peak memory 207528 kb
Host smart-f268dc42-e06c-4b5e-a8e5-54c398228c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31216
73861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3121673861
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.95828684
Short name T2119
Test name
Test status
Simulation time 149251549 ps
CPU time 0.87 seconds
Started Aug 13 06:39:29 PM PDT 24
Finished Aug 13 06:39:30 PM PDT 24
Peak memory 207488 kb
Host smart-4b4dcf9e-ea5e-4132-9289-6c519be71ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95828
684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.95828684
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_rx_full.2257433076
Short name T43
Test name
Test status
Simulation time 249424701 ps
CPU time 1.06 seconds
Started Aug 13 06:39:30 PM PDT 24
Finished Aug 13 06:39:31 PM PDT 24
Peak memory 207512 kb
Host smart-50e04022-c40b-4ce7-86e3-53ce4da785b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22574
33076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.2257433076
Directory /workspace/39.usbdev_rx_full/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2460038679
Short name T1634
Test name
Test status
Simulation time 151441841 ps
CPU time 0.84 seconds
Started Aug 13 06:39:18 PM PDT 24
Finished Aug 13 06:39:19 PM PDT 24
Peak memory 207552 kb
Host smart-2dce6480-d994-4ab8-9a33-3696d78e019a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24600
38679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2460038679
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.742972452
Short name T2029
Test name
Test status
Simulation time 172653091 ps
CPU time 0.88 seconds
Started Aug 13 06:39:21 PM PDT 24
Finished Aug 13 06:39:22 PM PDT 24
Peak memory 207604 kb
Host smart-6f37b204-6ae2-40ee-8c81-03ba27057e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74297
2452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.742972452
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3341039257
Short name T3212
Test name
Test status
Simulation time 216321504 ps
CPU time 1.05 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:39:48 PM PDT 24
Peak memory 207504 kb
Host smart-9d8cfa22-652a-4048-a94a-9175d6d2d271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33410
39257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3341039257
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.268388197
Short name T2802
Test name
Test status
Simulation time 1609405102 ps
CPU time 42.95 seconds
Started Aug 13 06:39:33 PM PDT 24
Finished Aug 13 06:40:17 PM PDT 24
Peak memory 224000 kb
Host smart-f55b571d-2b0e-4506-9659-f9100992a8b3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=268388197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.268388197
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3696965687
Short name T499
Test name
Test status
Simulation time 202032106 ps
CPU time 1 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207504 kb
Host smart-5077d82d-3c69-437a-8501-bc7aa37f75a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36969
65687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3696965687
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.4236345043
Short name T1435
Test name
Test status
Simulation time 179211247 ps
CPU time 0.96 seconds
Started Aug 13 06:39:21 PM PDT 24
Finished Aug 13 06:39:22 PM PDT 24
Peak memory 207604 kb
Host smart-65b1859c-3271-4ceb-a82a-3c890dea1081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42363
45043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.4236345043
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3807103137
Short name T2320
Test name
Test status
Simulation time 1264957998 ps
CPU time 3.17 seconds
Started Aug 13 06:39:21 PM PDT 24
Finished Aug 13 06:39:24 PM PDT 24
Peak memory 207776 kb
Host smart-012637f9-224a-45ba-9065-3d18f1f7f155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38071
03137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3807103137
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.3826761883
Short name T2785
Test name
Test status
Simulation time 1448926000 ps
CPU time 14.57 seconds
Started Aug 13 06:39:40 PM PDT 24
Finished Aug 13 06:39:54 PM PDT 24
Peak memory 217520 kb
Host smart-8036a603-fd6c-45df-83fd-48847311e047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38267
61883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3826761883
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.1703402188
Short name T3122
Test name
Test status
Simulation time 413353914 ps
CPU time 7.99 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:27 PM PDT 24
Peak memory 207716 kb
Host smart-bf7bdd1c-0f5b-4332-b31b-b74b80e8a5f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703402188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.1703402188
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_tx_rx_disruption.2971373160
Short name T3369
Test name
Test status
Simulation time 507853266 ps
CPU time 1.57 seconds
Started Aug 13 06:39:27 PM PDT 24
Finished Aug 13 06:39:29 PM PDT 24
Peak memory 207608 kb
Host smart-6c639b41-307e-4eea-9b78-9e8c29504023
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971373160 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.usbdev_tx_rx_disruption.2971373160
Directory /workspace/39.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/390.usbdev_tx_rx_disruption.708698232
Short name T162
Test name
Test status
Simulation time 555825633 ps
CPU time 1.51 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207496 kb
Host smart-7db0332e-3696-46a9-b86f-4fb2d3b61ad2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708698232 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 390.usbdev_tx_rx_disruption.708698232
Directory /workspace/390.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/391.usbdev_tx_rx_disruption.3915242371
Short name T2559
Test name
Test status
Simulation time 511304605 ps
CPU time 1.53 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:23 PM PDT 24
Peak memory 207592 kb
Host smart-1160702f-7f18-4e8c-b143-5d2df1fe766b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915242371 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 391.usbdev_tx_rx_disruption.3915242371
Directory /workspace/391.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/392.usbdev_tx_rx_disruption.4226965744
Short name T891
Test name
Test status
Simulation time 659593019 ps
CPU time 1.71 seconds
Started Aug 13 06:42:39 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 207624 kb
Host smart-0825551a-789e-4cfe-9750-10f1e0292b8a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226965744 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 392.usbdev_tx_rx_disruption.4226965744
Directory /workspace/392.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/393.usbdev_tx_rx_disruption.2088212694
Short name T119
Test name
Test status
Simulation time 543777476 ps
CPU time 1.63 seconds
Started Aug 13 06:42:25 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 207608 kb
Host smart-ca59798b-a73e-40a2-9208-092a0236da7e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088212694 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 393.usbdev_tx_rx_disruption.2088212694
Directory /workspace/393.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/394.usbdev_tx_rx_disruption.1602283778
Short name T2214
Test name
Test status
Simulation time 518922576 ps
CPU time 1.5 seconds
Started Aug 13 06:42:00 PM PDT 24
Finished Aug 13 06:42:02 PM PDT 24
Peak memory 207624 kb
Host smart-bcfaed45-e2dc-49fd-b98e-4a5ec0312454
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602283778 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 394.usbdev_tx_rx_disruption.1602283778
Directory /workspace/394.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/395.usbdev_tx_rx_disruption.543931926
Short name T3192
Test name
Test status
Simulation time 486332280 ps
CPU time 1.48 seconds
Started Aug 13 06:41:57 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207560 kb
Host smart-587907ab-1d3e-488e-a899-464c2a9d946c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543931926 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 395.usbdev_tx_rx_disruption.543931926
Directory /workspace/395.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/396.usbdev_tx_rx_disruption.747720337
Short name T650
Test name
Test status
Simulation time 524077659 ps
CPU time 1.48 seconds
Started Aug 13 06:41:59 PM PDT 24
Finished Aug 13 06:42:01 PM PDT 24
Peak memory 207520 kb
Host smart-3db8b63b-89ea-417a-8933-9f2b2e6f9118
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747720337 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 396.usbdev_tx_rx_disruption.747720337
Directory /workspace/396.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/397.usbdev_tx_rx_disruption.1687601852
Short name T202
Test name
Test status
Simulation time 618124786 ps
CPU time 1.59 seconds
Started Aug 13 06:42:11 PM PDT 24
Finished Aug 13 06:42:12 PM PDT 24
Peak memory 207584 kb
Host smart-f01af9e9-eba7-4832-a6e7-6c64860a30af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687601852 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 397.usbdev_tx_rx_disruption.1687601852
Directory /workspace/397.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/398.usbdev_tx_rx_disruption.329300892
Short name T1666
Test name
Test status
Simulation time 516631496 ps
CPU time 1.59 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 207536 kb
Host smart-53df9b70-a746-43c5-b24c-cf9d218a3698
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329300892 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 398.usbdev_tx_rx_disruption.329300892
Directory /workspace/398.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/399.usbdev_tx_rx_disruption.958572156
Short name T1929
Test name
Test status
Simulation time 527820157 ps
CPU time 1.44 seconds
Started Aug 13 06:42:02 PM PDT 24
Finished Aug 13 06:42:04 PM PDT 24
Peak memory 207584 kb
Host smart-4a46ce3e-197a-4e29-974d-a929784201ab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958572156 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 399.usbdev_tx_rx_disruption.958572156
Directory /workspace/399.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3584833250
Short name T1099
Test name
Test status
Simulation time 54805363 ps
CPU time 0.69 seconds
Started Aug 13 06:34:10 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 207468 kb
Host smart-cc14ac86-ebc0-49d5-8592-95b1391055f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3584833250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3584833250
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.817644747
Short name T3181
Test name
Test status
Simulation time 10202759232 ps
CPU time 13.47 seconds
Started Aug 13 06:33:55 PM PDT 24
Finished Aug 13 06:34:08 PM PDT 24
Peak memory 207800 kb
Host smart-5215dd15-ed34-4653-aefd-3d39734e5b07
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817644747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon
_wake_disconnect.817644747
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2250728960
Short name T1021
Test name
Test status
Simulation time 20381330329 ps
CPU time 28.43 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:34:21 PM PDT 24
Peak memory 207820 kb
Host smart-6e04ec65-6593-4b72-b6f9-651ccdca6c79
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250728960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2250728960
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1698293667
Short name T7
Test name
Test status
Simulation time 26209913352 ps
CPU time 38.18 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 216012 kb
Host smart-6428b6ab-96c8-4856-94c0-2eaee9f0fba8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698293667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.1698293667
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.486758900
Short name T3337
Test name
Test status
Simulation time 182414402 ps
CPU time 0.93 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 207500 kb
Host smart-93bc4d5d-1c27-45fa-be02-3231147bc483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48675
8900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.486758900
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.4199180237
Short name T41
Test name
Test status
Simulation time 182505360 ps
CPU time 0.91 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 207512 kb
Host smart-c612f7d0-4e2c-4bd1-8836-8f2dd1908113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41991
80237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.4199180237
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.3284033818
Short name T88
Test name
Test status
Simulation time 146798198 ps
CPU time 0.85 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207400 kb
Host smart-d51e9fc5-643e-459c-a093-2f7fde8e05fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840
33818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.3284033818
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.101397703
Short name T3293
Test name
Test status
Simulation time 146657679 ps
CPU time 0.83 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207408 kb
Host smart-15ba7bbd-f86f-40e5-b9f4-13148ed804ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10139
7703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.101397703
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.333752062
Short name T850
Test name
Test status
Simulation time 403660616 ps
CPU time 1.63 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 207588 kb
Host smart-cd0604de-d624-4e33-8e10-ebdd8d921bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33375
2062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.333752062
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2504640392
Short name T1648
Test name
Test status
Simulation time 1126192150 ps
CPU time 2.89 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:33:57 PM PDT 24
Peak memory 207708 kb
Host smart-876c1bb5-4381-4894-9807-5b2bb4e232c8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2504640392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2504640392
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.4131938557
Short name T2507
Test name
Test status
Simulation time 47631583061 ps
CPU time 77.03 seconds
Started Aug 13 06:33:57 PM PDT 24
Finished Aug 13 06:35:14 PM PDT 24
Peak memory 207844 kb
Host smart-223deede-273c-4150-bb35-d3248dec9da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41319
38557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.4131938557
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.4139975774
Short name T840
Test name
Test status
Simulation time 630181092 ps
CPU time 5.21 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:33:59 PM PDT 24
Peak memory 207824 kb
Host smart-05b429b0-37db-4f2d-a441-df2cf8c820ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139975774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.4139975774
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3015951692
Short name T1950
Test name
Test status
Simulation time 489780224 ps
CPU time 1.43 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 207568 kb
Host smart-71fc186e-2e67-45aa-aaf1-7a19b44ca6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30159
51692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3015951692
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.535503687
Short name T1572
Test name
Test status
Simulation time 146951725 ps
CPU time 0.85 seconds
Started Aug 13 06:33:55 PM PDT 24
Finished Aug 13 06:33:56 PM PDT 24
Peak memory 207488 kb
Host smart-0b039019-2278-4f43-a970-1b83a566053c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53550
3687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.535503687
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.36073388
Short name T2369
Test name
Test status
Simulation time 93269909 ps
CPU time 0.84 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 207420 kb
Host smart-88d191d2-8c0d-4612-8ea0-21f5ee78ec9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36073
388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.36073388
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2737747241
Short name T754
Test name
Test status
Simulation time 955024542 ps
CPU time 2.71 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:56 PM PDT 24
Peak memory 207804 kb
Host smart-6ab27439-e8e3-4aee-a892-88ffc72fff9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27377
47241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2737747241
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_types.3904537464
Short name T406
Test name
Test status
Simulation time 368384903 ps
CPU time 1.28 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 207580 kb
Host smart-c75bf83e-f4af-4694-9c36-47d0a2726064
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3904537464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.3904537464
Directory /workspace/4.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2884035784
Short name T1984
Test name
Test status
Simulation time 311209993 ps
CPU time 2.91 seconds
Started Aug 13 06:33:52 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 207680 kb
Host smart-62697c7d-961a-4b21-9446-2559374c3ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28840
35784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2884035784
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.921375190
Short name T3407
Test name
Test status
Simulation time 83174609823 ps
CPU time 149.6 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:36:24 PM PDT 24
Peak memory 207780 kb
Host smart-86d0d9ed-dcae-4c69-8d1a-8e81d400816e
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=921375190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.921375190
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.357975835
Short name T3382
Test name
Test status
Simulation time 120288584039 ps
CPU time 201.05 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:37:15 PM PDT 24
Peak memory 207760 kb
Host smart-277c3f79-bc1a-4755-a378-6da091a7952b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357975835 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.357975835
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1193073418
Short name T3045
Test name
Test status
Simulation time 99105290639 ps
CPU time 186.56 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:37:01 PM PDT 24
Peak memory 207732 kb
Host smart-9c9bdc91-7ff1-445c-92fe-d26ddda6de6e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1193073418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1193073418
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.3721138938
Short name T2528
Test name
Test status
Simulation time 113058214734 ps
CPU time 193.84 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:37:07 PM PDT 24
Peak memory 207740 kb
Host smart-68d838d0-d66e-47e2-8426-057ebc172798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721138938 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.3721138938
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.2050601653
Short name T1320
Test name
Test status
Simulation time 111165685921 ps
CPU time 183.41 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:36:57 PM PDT 24
Peak memory 207684 kb
Host smart-b1b7a2af-6e63-421c-9592-ba54aef810d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20506
01653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.2050601653
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.801008378
Short name T1761
Test name
Test status
Simulation time 204970294 ps
CPU time 1 seconds
Started Aug 13 06:33:51 PM PDT 24
Finished Aug 13 06:33:52 PM PDT 24
Peak memory 207424 kb
Host smart-8d4e8cf7-3e27-4b90-bad1-3e4c4e8f3460
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=801008378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.801008378
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.4202964319
Short name T3063
Test name
Test status
Simulation time 147346140 ps
CPU time 0.93 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 207412 kb
Host smart-b72602f4-4e97-4cab-925b-ae69b9c90e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42029
64319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.4202964319
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1125101266
Short name T3304
Test name
Test status
Simulation time 214837753 ps
CPU time 1.03 seconds
Started Aug 13 06:33:56 PM PDT 24
Finished Aug 13 06:33:57 PM PDT 24
Peak memory 207496 kb
Host smart-0fd7e21d-2c01-4584-8fc8-55fc99868e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11251
01266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1125101266
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.3299216833
Short name T1480
Test name
Test status
Simulation time 4423540579 ps
CPU time 42.95 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:34:37 PM PDT 24
Peak memory 224020 kb
Host smart-b4476d4e-9aee-4509-b7b3-e2cc6678b1fd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3299216833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3299216833
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.984650980
Short name T1129
Test name
Test status
Simulation time 4885869398 ps
CPU time 34.38 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:36 PM PDT 24
Peak memory 207720 kb
Host smart-eac12c99-5f09-406c-8417-0643abec37f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=984650980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.984650980
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3974148562
Short name T1141
Test name
Test status
Simulation time 218383438 ps
CPU time 1.04 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 207444 kb
Host smart-94d553cb-da15-4c80-99a4-c5aa2f0fa0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39741
48562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3974148562
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.2814284423
Short name T2059
Test name
Test status
Simulation time 27408583870 ps
CPU time 45.22 seconds
Started Aug 13 06:33:56 PM PDT 24
Finished Aug 13 06:34:41 PM PDT 24
Peak memory 207732 kb
Host smart-fda267d8-c00b-44a3-aea4-a8e706637870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28142
84423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.2814284423
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3196733729
Short name T609
Test name
Test status
Simulation time 6075015450 ps
CPU time 8.45 seconds
Started Aug 13 06:33:55 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207844 kb
Host smart-7e96056c-8422-4a06-9d28-88e1837c9a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31967
33729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3196733729
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.357113572
Short name T522
Test name
Test status
Simulation time 5017304414 ps
CPU time 49.53 seconds
Started Aug 13 06:34:02 PM PDT 24
Finished Aug 13 06:34:52 PM PDT 24
Peak memory 224112 kb
Host smart-ed8a61a3-d37c-4455-bdc6-1c37cd53ae2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=357113572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.357113572
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.345709621
Short name T584
Test name
Test status
Simulation time 2743021846 ps
CPU time 83.94 seconds
Started Aug 13 06:33:58 PM PDT 24
Finished Aug 13 06:35:22 PM PDT 24
Peak memory 217544 kb
Host smart-be6ee46c-6c11-499d-a2c3-0ff294991105
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=345709621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.345709621
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.4045091282
Short name T1990
Test name
Test status
Simulation time 238366855 ps
CPU time 0.97 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 207500 kb
Host smart-1c2ec292-dd66-470d-ad7d-89ac9f5ba082
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4045091282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.4045091282
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3756721198
Short name T1496
Test name
Test status
Simulation time 207257576 ps
CPU time 0.97 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 207460 kb
Host smart-4da59a26-8daa-4c87-87ab-581db20c61dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37567
21198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3756721198
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.2750577005
Short name T3426
Test name
Test status
Simulation time 3219412073 ps
CPU time 93.65 seconds
Started Aug 13 06:33:56 PM PDT 24
Finished Aug 13 06:35:30 PM PDT 24
Peak memory 217928 kb
Host smart-0d532f6b-febe-4b2c-a814-e423839e43cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27505
77005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.2750577005
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.90222138
Short name T1284
Test name
Test status
Simulation time 2424086132 ps
CPU time 24 seconds
Started Aug 13 06:33:56 PM PDT 24
Finished Aug 13 06:34:20 PM PDT 24
Peak memory 217776 kb
Host smart-fbb2c1db-37e4-4547-99f2-e5f5497ee409
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=90222138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.90222138
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.4198667220
Short name T1951
Test name
Test status
Simulation time 2468514889 ps
CPU time 17.94 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:34:12 PM PDT 24
Peak memory 207692 kb
Host smart-4d31c610-202b-4601-b905-b02192226abd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4198667220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.4198667220
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.628087586
Short name T2563
Test name
Test status
Simulation time 158693833 ps
CPU time 0.88 seconds
Started Aug 13 06:34:02 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207404 kb
Host smart-7ce490be-c1ec-4200-9f8a-5e0e1ee2f372
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=628087586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.628087586
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2435000617
Short name T2561
Test name
Test status
Simulation time 156296364 ps
CPU time 0.84 seconds
Started Aug 13 06:33:55 PM PDT 24
Finished Aug 13 06:33:56 PM PDT 24
Peak memory 207488 kb
Host smart-0eea186d-78cc-405e-9f0d-d421d1491568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
00617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2435000617
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.4191009592
Short name T124
Test name
Test status
Simulation time 192021742 ps
CPU time 0.96 seconds
Started Aug 13 06:33:51 PM PDT 24
Finished Aug 13 06:33:53 PM PDT 24
Peak memory 207528 kb
Host smart-ba01f452-6310-44af-8888-b4c823541814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41910
09592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.4191009592
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.943990082
Short name T2665
Test name
Test status
Simulation time 151669218 ps
CPU time 0.85 seconds
Started Aug 13 06:33:53 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 207496 kb
Host smart-cdb95c08-5e8c-41d5-bd6c-d5a5de88c10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94399
0082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.943990082
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1139009865
Short name T3395
Test name
Test status
Simulation time 204108334 ps
CPU time 0.94 seconds
Started Aug 13 06:33:55 PM PDT 24
Finished Aug 13 06:33:56 PM PDT 24
Peak memory 207524 kb
Host smart-f1094c02-c531-42e1-94cb-e0085d022710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11390
09865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1139009865
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2753620142
Short name T2224
Test name
Test status
Simulation time 189541261 ps
CPU time 0.93 seconds
Started Aug 13 06:33:56 PM PDT 24
Finished Aug 13 06:33:57 PM PDT 24
Peak memory 207580 kb
Host smart-556cf82d-34bc-45f5-852f-05263187f2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27536
20142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2753620142
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1312965363
Short name T1394
Test name
Test status
Simulation time 153839473 ps
CPU time 0.88 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:02 PM PDT 24
Peak memory 207500 kb
Host smart-9c3a04c1-c86c-482a-b4e9-e4f897fbb18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13129
65363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1312965363
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3461914912
Short name T2309
Test name
Test status
Simulation time 235220967 ps
CPU time 1.03 seconds
Started Aug 13 06:34:00 PM PDT 24
Finished Aug 13 06:34:01 PM PDT 24
Peak memory 207596 kb
Host smart-8366263a-e5c3-4e30-b1a9-97cac8189944
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3461914912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3461914912
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.1412099023
Short name T2054
Test name
Test status
Simulation time 225207974 ps
CPU time 1.08 seconds
Started Aug 13 06:34:03 PM PDT 24
Finished Aug 13 06:34:04 PM PDT 24
Peak memory 207484 kb
Host smart-a1bf449b-ae0f-4e20-8711-24cc64f6bf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14120
99023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.1412099023
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2156295553
Short name T732
Test name
Test status
Simulation time 144989683 ps
CPU time 0.91 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207464 kb
Host smart-34266346-a8c5-486d-b6ac-f5d702514401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21562
95553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2156295553
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2324716585
Short name T2173
Test name
Test status
Simulation time 49589280 ps
CPU time 0.75 seconds
Started Aug 13 06:34:02 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207432 kb
Host smart-49bf2255-58cd-4cb3-8e03-9147e4c0befc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23247
16585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2324716585
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2429693924
Short name T1508
Test name
Test status
Simulation time 12281379803 ps
CPU time 34.97 seconds
Started Aug 13 06:34:03 PM PDT 24
Finished Aug 13 06:34:38 PM PDT 24
Peak memory 224120 kb
Host smart-02c88334-845d-473c-916f-6f7283458d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24296
93924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2429693924
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2012111300
Short name T1550
Test name
Test status
Simulation time 193335481 ps
CPU time 0.99 seconds
Started Aug 13 06:34:03 PM PDT 24
Finished Aug 13 06:34:04 PM PDT 24
Peak memory 207572 kb
Host smart-c87637fb-ec3c-41d5-ac0a-6edea6d303da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20121
11300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2012111300
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.643161440
Short name T3550
Test name
Test status
Simulation time 159497854 ps
CPU time 0.95 seconds
Started Aug 13 06:34:02 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207484 kb
Host smart-15af7ef8-bbe5-4196-9306-ccd1293e174c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64316
1440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.643161440
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.2233940681
Short name T909
Test name
Test status
Simulation time 6932619606 ps
CPU time 32.22 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 219280 kb
Host smart-a50c3929-e783-444e-82e4-1a338f417c85
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233940681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.2233940681
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2392752943
Short name T3186
Test name
Test status
Simulation time 9513268308 ps
CPU time 62.52 seconds
Started Aug 13 06:34:00 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 224120 kb
Host smart-b63144cd-0fc0-4048-a66d-b5fbda4ff8cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2392752943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2392752943
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2458163858
Short name T1140
Test name
Test status
Simulation time 6193802728 ps
CPU time 71.6 seconds
Started Aug 13 06:34:03 PM PDT 24
Finished Aug 13 06:35:15 PM PDT 24
Peak memory 216032 kb
Host smart-e5e3c2eb-57fc-4ddd-bba8-1bb4eb1c20af
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458163858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2458163858
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.3085035330
Short name T756
Test name
Test status
Simulation time 201446099 ps
CPU time 0.98 seconds
Started Aug 13 06:33:59 PM PDT 24
Finished Aug 13 06:34:00 PM PDT 24
Peak memory 207428 kb
Host smart-8623c5d2-7a42-4ae6-af7a-7d59e5a86d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30850
35330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.3085035330
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.4219982070
Short name T1180
Test name
Test status
Simulation time 183833431 ps
CPU time 0.97 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:02 PM PDT 24
Peak memory 207532 kb
Host smart-a0f21549-0b75-40ab-a0aa-924e04475142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42199
82070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.4219982070
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_resume_link_active.1383718103
Short name T1285
Test name
Test status
Simulation time 20158580625 ps
CPU time 24.85 seconds
Started Aug 13 06:34:00 PM PDT 24
Finished Aug 13 06:34:25 PM PDT 24
Peak memory 207576 kb
Host smart-4f71df80-12fe-4907-8a54-bfab4fa0e601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13837
18103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.1383718103
Directory /workspace/4.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2437735776
Short name T2571
Test name
Test status
Simulation time 217087578 ps
CPU time 1.07 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207448 kb
Host smart-1b20bb2a-b7fc-42c6-8b53-21b7886d3962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24377
35776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2437735776
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_full.1333534260
Short name T1289
Test name
Test status
Simulation time 251133798 ps
CPU time 1.1 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:02 PM PDT 24
Peak memory 207368 kb
Host smart-a2aabfe4-4e18-46ac-be22-d12e4eb33b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13335
34260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.1333534260
Directory /workspace/4.usbdev_rx_full/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1487724113
Short name T3621
Test name
Test status
Simulation time 155366594 ps
CPU time 0.88 seconds
Started Aug 13 06:34:00 PM PDT 24
Finished Aug 13 06:34:01 PM PDT 24
Peak memory 207496 kb
Host smart-2a20f4bf-ccb9-4034-82f6-60b7d3efb9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14877
24113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1487724113
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.4189485399
Short name T47
Test name
Test status
Simulation time 412467136 ps
CPU time 1.38 seconds
Started Aug 13 06:34:00 PM PDT 24
Finished Aug 13 06:34:01 PM PDT 24
Peak memory 207544 kb
Host smart-aaebf3d7-1840-4a15-8c5e-2fdf407f01bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41894
85399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.4189485399
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.4231931057
Short name T2042
Test name
Test status
Simulation time 314086445 ps
CPU time 1.07 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:02 PM PDT 24
Peak memory 207532 kb
Host smart-dcac4898-6ca2-4dea-9441-ef7e11cedd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42319
31057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.4231931057
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2699058082
Short name T1741
Test name
Test status
Simulation time 145147744 ps
CPU time 0.89 seconds
Started Aug 13 06:34:02 PM PDT 24
Finished Aug 13 06:34:04 PM PDT 24
Peak memory 207476 kb
Host smart-b1ff47a7-2c4a-41ff-b0e2-069cac61137c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26990
58082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2699058082
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.645349650
Short name T646
Test name
Test status
Simulation time 184265041 ps
CPU time 0.9 seconds
Started Aug 13 06:34:02 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 207584 kb
Host smart-1a1d2187-e818-47e4-a1ea-3a526b957455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64534
9650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.645349650
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3398320242
Short name T3106
Test name
Test status
Simulation time 232560217 ps
CPU time 1.2 seconds
Started Aug 13 06:33:59 PM PDT 24
Finished Aug 13 06:34:01 PM PDT 24
Peak memory 207520 kb
Host smart-69890cd0-4cca-436c-805f-ceac62eec8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33983
20242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3398320242
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3422499164
Short name T85
Test name
Test status
Simulation time 2480575348 ps
CPU time 20.51 seconds
Started Aug 13 06:34:03 PM PDT 24
Finished Aug 13 06:34:23 PM PDT 24
Peak memory 224064 kb
Host smart-6763ae24-74e6-4522-8afa-608f866b8eda
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3422499164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3422499164
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.175228475
Short name T1433
Test name
Test status
Simulation time 196616318 ps
CPU time 0.92 seconds
Started Aug 13 06:34:03 PM PDT 24
Finished Aug 13 06:34:04 PM PDT 24
Peak memory 207492 kb
Host smart-60bce96b-d951-4469-9f27-357b48968400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17522
8475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.175228475
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1454402289
Short name T2935
Test name
Test status
Simulation time 162813604 ps
CPU time 0.94 seconds
Started Aug 13 06:34:01 PM PDT 24
Finished Aug 13 06:34:02 PM PDT 24
Peak memory 207408 kb
Host smart-eb988bcf-b294-4209-8e08-09a0bc819be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14544
02289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1454402289
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.389648303
Short name T3367
Test name
Test status
Simulation time 1033390300 ps
CPU time 2.48 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:11 PM PDT 24
Peak memory 207648 kb
Host smart-ca559c45-2afa-4177-ba3b-e7990b3c2443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38964
8303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.389648303
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.670839621
Short name T2872
Test name
Test status
Simulation time 2397865543 ps
CPU time 68.27 seconds
Started Aug 13 06:34:13 PM PDT 24
Finished Aug 13 06:35:21 PM PDT 24
Peak memory 217368 kb
Host smart-fd330321-1623-40f7-b99e-55e655f69a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67083
9621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.670839621
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2528233904
Short name T78
Test name
Test status
Simulation time 6771653587 ps
CPU time 95.59 seconds
Started Aug 13 06:34:06 PM PDT 24
Finished Aug 13 06:35:42 PM PDT 24
Peak memory 219776 kb
Host smart-5f896885-2cc0-4779-8f41-dad83dfba056
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528233904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2528233904
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.621702720
Short name T2469
Test name
Test status
Simulation time 4743307955 ps
CPU time 43.95 seconds
Started Aug 13 06:33:54 PM PDT 24
Finished Aug 13 06:34:38 PM PDT 24
Peak memory 207760 kb
Host smart-57fcc492-5f9a-4b63-873c-a8c470cdc36d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621702720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host_
handshake.621702720
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_tx_rx_disruption.1026967843
Short name T2228
Test name
Test status
Simulation time 434037313 ps
CPU time 1.4 seconds
Started Aug 13 06:34:11 PM PDT 24
Finished Aug 13 06:34:12 PM PDT 24
Peak memory 207604 kb
Host smart-a4dda0de-c81d-4165-9ce0-b77167a474e9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026967843 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.usbdev_tx_rx_disruption.1026967843
Directory /workspace/4.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3878698131
Short name T2294
Test name
Test status
Simulation time 33413153 ps
CPU time 0.65 seconds
Started Aug 13 06:39:45 PM PDT 24
Finished Aug 13 06:39:46 PM PDT 24
Peak memory 207436 kb
Host smart-8e196603-50a6-4803-ab15-c149c7f2feef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3878698131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3878698131
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1708485166
Short name T2747
Test name
Test status
Simulation time 5172314432 ps
CPU time 7.37 seconds
Started Aug 13 06:39:33 PM PDT 24
Finished Aug 13 06:39:40 PM PDT 24
Peak memory 215992 kb
Host smart-d6ad1f02-bcb6-4adb-95c6-5979442c4000
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708485166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.1708485166
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1421545066
Short name T1187
Test name
Test status
Simulation time 21163135805 ps
CPU time 25.55 seconds
Started Aug 13 06:39:19 PM PDT 24
Finished Aug 13 06:39:44 PM PDT 24
Peak memory 207724 kb
Host smart-9f37dec1-ec9a-4a69-bce2-414c7f1c4eb4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421545066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1421545066
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.1993956740
Short name T3554
Test name
Test status
Simulation time 25396462039 ps
CPU time 36.73 seconds
Started Aug 13 06:39:25 PM PDT 24
Finished Aug 13 06:40:02 PM PDT 24
Peak memory 216040 kb
Host smart-3c018c81-a7c2-452e-a3b5-2afd1d602de3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993956740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.1993956740
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.374741093
Short name T1303
Test name
Test status
Simulation time 189416532 ps
CPU time 0.96 seconds
Started Aug 13 06:39:17 PM PDT 24
Finished Aug 13 06:39:18 PM PDT 24
Peak memory 207488 kb
Host smart-c04a49db-4b32-4ff0-a283-4f0fd4a4e121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37474
1093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.374741093
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.4113227902
Short name T1530
Test name
Test status
Simulation time 151321412 ps
CPU time 0.86 seconds
Started Aug 13 06:39:37 PM PDT 24
Finished Aug 13 06:39:37 PM PDT 24
Peak memory 207472 kb
Host smart-11e3fa9d-a13d-4469-9cc8-55ab3d4f1879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41132
27902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.4113227902
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2190982960
Short name T865
Test name
Test status
Simulation time 218262068 ps
CPU time 0.99 seconds
Started Aug 13 06:39:40 PM PDT 24
Finished Aug 13 06:39:42 PM PDT 24
Peak memory 207572 kb
Host smart-7705ae5a-d884-434c-9672-384efc455260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21909
82960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2190982960
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.998176925
Short name T1801
Test name
Test status
Simulation time 953863206 ps
CPU time 2.7 seconds
Started Aug 13 06:39:37 PM PDT 24
Finished Aug 13 06:39:40 PM PDT 24
Peak memory 207692 kb
Host smart-a2c6315f-ac27-488d-b268-415896ba1f80
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=998176925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.998176925
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1052637216
Short name T3035
Test name
Test status
Simulation time 22668938039 ps
CPU time 36.25 seconds
Started Aug 13 06:39:45 PM PDT 24
Finished Aug 13 06:40:22 PM PDT 24
Peak memory 207848 kb
Host smart-4f996ae3-534b-472c-8457-21bdbb0702e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526
37216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1052637216
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.2206517872
Short name T3524
Test name
Test status
Simulation time 2450863365 ps
CPU time 21.07 seconds
Started Aug 13 06:39:44 PM PDT 24
Finished Aug 13 06:40:06 PM PDT 24
Peak memory 207836 kb
Host smart-5dd4a570-8308-4325-87b8-08e10924557e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206517872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.2206517872
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2715939794
Short name T2498
Test name
Test status
Simulation time 838353439 ps
CPU time 1.82 seconds
Started Aug 13 06:39:45 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 207464 kb
Host smart-20390fa5-0449-41f5-bca6-4106c2cd0959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27159
39794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2715939794
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1608376267
Short name T3503
Test name
Test status
Simulation time 140028980 ps
CPU time 0.85 seconds
Started Aug 13 06:39:49 PM PDT 24
Finished Aug 13 06:39:50 PM PDT 24
Peak memory 207536 kb
Host smart-18a0fb5d-8d6f-4978-bed9-6b4cd887e80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16083
76267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1608376267
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.950196223
Short name T1010
Test name
Test status
Simulation time 56615639 ps
CPU time 0.72 seconds
Started Aug 13 06:39:29 PM PDT 24
Finished Aug 13 06:39:30 PM PDT 24
Peak memory 207352 kb
Host smart-7ac46451-64c4-4437-9df2-41175adcc96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95019
6223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.950196223
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2821419633
Short name T2174
Test name
Test status
Simulation time 1008627300 ps
CPU time 2.6 seconds
Started Aug 13 06:39:45 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 207804 kb
Host smart-c1a8d219-c0ee-4ae5-8df1-6df494ec5faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28214
19633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2821419633
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_types.4280155639
Short name T498
Test name
Test status
Simulation time 287821429 ps
CPU time 1.19 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 207528 kb
Host smart-4b9dd484-b9ad-4efe-9778-08424db62adc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4280155639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.4280155639
Directory /workspace/40.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2666382426
Short name T2758
Test name
Test status
Simulation time 375602523 ps
CPU time 2.63 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:39:48 PM PDT 24
Peak memory 207600 kb
Host smart-00c12ba3-c1b6-4a17-83fa-1bced74aeff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26663
82426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2666382426
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3396356316
Short name T1417
Test name
Test status
Simulation time 229081326 ps
CPU time 1.16 seconds
Started Aug 13 06:39:36 PM PDT 24
Finished Aug 13 06:39:37 PM PDT 24
Peak memory 215864 kb
Host smart-eb634ec4-2cf5-4ac5-b0a0-3c9cbdf71dcf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3396356316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3396356316
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2745093471
Short name T3005
Test name
Test status
Simulation time 140531596 ps
CPU time 0.85 seconds
Started Aug 13 06:39:34 PM PDT 24
Finished Aug 13 06:39:35 PM PDT 24
Peak memory 207480 kb
Host smart-4b783659-fbc3-4f87-bb86-c5ed489a455d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27450
93471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2745093471
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.112988631
Short name T1363
Test name
Test status
Simulation time 182933129 ps
CPU time 0.96 seconds
Started Aug 13 06:39:37 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 207520 kb
Host smart-60897583-dc8d-4a14-b862-f782d7f8b16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11298
8631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.112988631
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2724494315
Short name T3590
Test name
Test status
Simulation time 2407142648 ps
CPU time 18.33 seconds
Started Aug 13 06:39:45 PM PDT 24
Finished Aug 13 06:40:04 PM PDT 24
Peak memory 218196 kb
Host smart-ba68f9c6-93e8-493f-8d57-a944d1246693
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2724494315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2724494315
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.2740519214
Short name T2945
Test name
Test status
Simulation time 11691683759 ps
CPU time 153.46 seconds
Started Aug 13 06:39:48 PM PDT 24
Finished Aug 13 06:42:22 PM PDT 24
Peak memory 207756 kb
Host smart-8974083c-f8f2-424b-8ea8-66924f0de151
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2740519214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.2740519214
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1240250333
Short name T1226
Test name
Test status
Simulation time 219363351 ps
CPU time 1.01 seconds
Started Aug 13 06:39:33 PM PDT 24
Finished Aug 13 06:39:34 PM PDT 24
Peak memory 207608 kb
Host smart-16d321ef-9a97-457d-8d10-0da2bfb8acdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12402
50333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1240250333
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3786988907
Short name T1217
Test name
Test status
Simulation time 25399006591 ps
CPU time 31.98 seconds
Started Aug 13 06:39:50 PM PDT 24
Finished Aug 13 06:40:23 PM PDT 24
Peak memory 215972 kb
Host smart-c76b4f3c-37c1-4993-a820-4013c126627d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37869
88907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3786988907
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.4171101908
Short name T2624
Test name
Test status
Simulation time 5228701466 ps
CPU time 7.33 seconds
Started Aug 13 06:39:51 PM PDT 24
Finished Aug 13 06:39:59 PM PDT 24
Peak memory 216888 kb
Host smart-e5964334-31b5-4272-aabb-e9da0de8b0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41711
01908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.4171101908
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1083557399
Short name T993
Test name
Test status
Simulation time 5740590726 ps
CPU time 61.48 seconds
Started Aug 13 06:39:45 PM PDT 24
Finished Aug 13 06:40:47 PM PDT 24
Peak memory 216000 kb
Host smart-1b1b4b66-1941-4640-a633-03c8bc6d81a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1083557399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1083557399
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2406894680
Short name T3552
Test name
Test status
Simulation time 1732750852 ps
CPU time 48.51 seconds
Started Aug 13 06:39:38 PM PDT 24
Finished Aug 13 06:40:27 PM PDT 24
Peak memory 217240 kb
Host smart-6b6ef22b-0556-4785-a66f-d97d00c21277
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2406894680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2406894680
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2763948594
Short name T2368
Test name
Test status
Simulation time 239974733 ps
CPU time 1.01 seconds
Started Aug 13 06:39:56 PM PDT 24
Finished Aug 13 06:39:57 PM PDT 24
Peak memory 207464 kb
Host smart-2c01e4f3-b534-4cb1-8ff9-f7312e81e0c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2763948594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2763948594
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3262109301
Short name T2560
Test name
Test status
Simulation time 197149412 ps
CPU time 0.94 seconds
Started Aug 13 06:39:33 PM PDT 24
Finished Aug 13 06:39:34 PM PDT 24
Peak memory 207452 kb
Host smart-831c553c-bb2b-40f0-88f8-9f4a3f42f201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32621
09301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3262109301
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.771647281
Short name T3037
Test name
Test status
Simulation time 1637638323 ps
CPU time 46.37 seconds
Started Aug 13 06:39:52 PM PDT 24
Finished Aug 13 06:40:38 PM PDT 24
Peak memory 215908 kb
Host smart-4f1c1f4e-6ab7-4e31-9357-f55a345816eb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=771647281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.771647281
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.99934790
Short name T3340
Test name
Test status
Simulation time 149944189 ps
CPU time 0.85 seconds
Started Aug 13 06:39:47 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 207464 kb
Host smart-143d994b-0512-4fe9-918e-91bd7fdfa866
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=99934790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.99934790
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1223273166
Short name T2020
Test name
Test status
Simulation time 143039234 ps
CPU time 0.84 seconds
Started Aug 13 06:39:30 PM PDT 24
Finished Aug 13 06:39:31 PM PDT 24
Peak memory 207508 kb
Host smart-2146d726-5fe8-4542-bd01-7c12b2a8a7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12232
73166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1223273166
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2396225634
Short name T1882
Test name
Test status
Simulation time 216315015 ps
CPU time 0.99 seconds
Started Aug 13 06:39:45 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 207544 kb
Host smart-0263ad98-1799-4711-a17d-d0e6e6942831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23962
25634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2396225634
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1459356405
Short name T3105
Test name
Test status
Simulation time 225871959 ps
CPU time 0.98 seconds
Started Aug 13 06:39:31 PM PDT 24
Finished Aug 13 06:39:32 PM PDT 24
Peak memory 207504 kb
Host smart-e704416e-9167-4836-b432-6c7bcb93e6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14593
56405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1459356405
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.4252924996
Short name T1788
Test name
Test status
Simulation time 172946318 ps
CPU time 0.89 seconds
Started Aug 13 06:39:37 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 207428 kb
Host smart-a56e305f-776d-4fa6-b09a-400b11d7cea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42529
24996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.4252924996
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.375225509
Short name T794
Test name
Test status
Simulation time 176217006 ps
CPU time 0.92 seconds
Started Aug 13 06:39:37 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 207492 kb
Host smart-0e8a8eeb-9f3c-4130-985e-d20032f11642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37522
5509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.375225509
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.109049979
Short name T1293
Test name
Test status
Simulation time 160125480 ps
CPU time 0.92 seconds
Started Aug 13 06:39:49 PM PDT 24
Finished Aug 13 06:39:50 PM PDT 24
Peak memory 207620 kb
Host smart-b183d839-5a32-4170-a657-2475cfc99622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10904
9979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.109049979
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.220864798
Short name T2041
Test name
Test status
Simulation time 257592832 ps
CPU time 1.02 seconds
Started Aug 13 06:39:49 PM PDT 24
Finished Aug 13 06:39:50 PM PDT 24
Peak memory 207612 kb
Host smart-3b38e7a1-0b29-4b52-84b0-2a60d84c2c13
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=220864798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.220864798
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1448963021
Short name T3048
Test name
Test status
Simulation time 144041765 ps
CPU time 0.86 seconds
Started Aug 13 06:39:38 PM PDT 24
Finished Aug 13 06:39:39 PM PDT 24
Peak memory 207468 kb
Host smart-5804a314-7a63-4e01-b3da-bb157c851871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14489
63021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1448963021
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1496413425
Short name T3149
Test name
Test status
Simulation time 33254211 ps
CPU time 0.72 seconds
Started Aug 13 06:39:35 PM PDT 24
Finished Aug 13 06:39:36 PM PDT 24
Peak memory 207496 kb
Host smart-9ba4dd51-23c9-4b93-bf31-30879eb5f64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14964
13425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1496413425
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1996611112
Short name T297
Test name
Test status
Simulation time 8751760371 ps
CPU time 22.04 seconds
Started Aug 13 06:39:51 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 215892 kb
Host smart-ab17e15f-e964-4454-85c1-b1e4ddf5884d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19966
11112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1996611112
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2856291066
Short name T2243
Test name
Test status
Simulation time 172855059 ps
CPU time 0.91 seconds
Started Aug 13 06:39:35 PM PDT 24
Finished Aug 13 06:39:36 PM PDT 24
Peak memory 207500 kb
Host smart-cd9e2a88-2318-4d97-b190-f32b30fc16c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28562
91066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2856291066
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3211694014
Short name T916
Test name
Test status
Simulation time 200361309 ps
CPU time 0.96 seconds
Started Aug 13 06:39:38 PM PDT 24
Finished Aug 13 06:39:39 PM PDT 24
Peak memory 207428 kb
Host smart-f31a808f-66b3-434b-8296-2229f3d42b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32116
94014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3211694014
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2495143064
Short name T1016
Test name
Test status
Simulation time 235541331 ps
CPU time 1.01 seconds
Started Aug 13 06:39:34 PM PDT 24
Finished Aug 13 06:39:36 PM PDT 24
Peak memory 207504 kb
Host smart-63e10c14-9f70-4c03-850b-db4029abf69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24951
43064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2495143064
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.3464057585
Short name T2542
Test name
Test status
Simulation time 230869359 ps
CPU time 0.98 seconds
Started Aug 13 06:39:48 PM PDT 24
Finished Aug 13 06:39:50 PM PDT 24
Peak memory 207548 kb
Host smart-e48c8f27-93aa-4fdb-b7f7-28046b2bb69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34640
57585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.3464057585
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3494238696
Short name T2904
Test name
Test status
Simulation time 192695239 ps
CPU time 0.86 seconds
Started Aug 13 06:39:37 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 207512 kb
Host smart-d032ebfa-ac59-40a6-828c-9a7a16cb8f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34942
38696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3494238696
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_rx_full.3158260642
Short name T3352
Test name
Test status
Simulation time 245290203 ps
CPU time 1.15 seconds
Started Aug 13 06:39:39 PM PDT 24
Finished Aug 13 06:39:41 PM PDT 24
Peak memory 207536 kb
Host smart-596fc7d6-a964-448a-bd33-6f5d0f7371c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582
60642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.3158260642
Directory /workspace/40.usbdev_rx_full/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.6144774
Short name T750
Test name
Test status
Simulation time 151056940 ps
CPU time 0.95 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:39:48 PM PDT 24
Peak memory 207492 kb
Host smart-355f2d8a-116f-49f8-a60b-cbf1fa21f608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61447
74 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.6144774
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.284354356
Short name T1859
Test name
Test status
Simulation time 198095182 ps
CPU time 0.91 seconds
Started Aug 13 06:39:53 PM PDT 24
Finished Aug 13 06:39:54 PM PDT 24
Peak memory 207600 kb
Host smart-d5b15518-f069-4d84-a533-1138e5d75ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28435
4356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.284354356
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.100094299
Short name T707
Test name
Test status
Simulation time 243513625 ps
CPU time 0.97 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:39:55 PM PDT 24
Peak memory 207524 kb
Host smart-4de173d5-0c07-4e6e-89cf-4b0908cc20f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10009
4299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.100094299
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.964936021
Short name T692
Test name
Test status
Simulation time 2612001741 ps
CPU time 74.06 seconds
Started Aug 13 06:39:42 PM PDT 24
Finished Aug 13 06:40:57 PM PDT 24
Peak memory 215944 kb
Host smart-2bd5fb9d-2f8f-42e6-9d6a-862bd501005d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=964936021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.964936021
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.294634357
Short name T2823
Test name
Test status
Simulation time 180557418 ps
CPU time 0.92 seconds
Started Aug 13 06:39:35 PM PDT 24
Finished Aug 13 06:39:36 PM PDT 24
Peak memory 207516 kb
Host smart-22aa6a18-2d58-4b1f-8dd4-f50cb44fa75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29463
4357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.294634357
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2915526023
Short name T1752
Test name
Test status
Simulation time 195544609 ps
CPU time 0.92 seconds
Started Aug 13 06:39:34 PM PDT 24
Finished Aug 13 06:39:35 PM PDT 24
Peak memory 207604 kb
Host smart-242bc4c9-013a-4303-a070-5017b5d73055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29155
26023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2915526023
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.485088421
Short name T1186
Test name
Test status
Simulation time 1051215663 ps
CPU time 2.56 seconds
Started Aug 13 06:39:36 PM PDT 24
Finished Aug 13 06:39:38 PM PDT 24
Peak memory 207752 kb
Host smart-96153a97-b033-4713-999b-1c27e286b936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48508
8421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.485088421
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.4129572439
Short name T3448
Test name
Test status
Simulation time 2248233586 ps
CPU time 62.22 seconds
Started Aug 13 06:39:39 PM PDT 24
Finished Aug 13 06:40:41 PM PDT 24
Peak memory 217408 kb
Host smart-61a0d607-42f9-44b8-908e-b65751bdb115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41295
72439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.4129572439
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.1847443442
Short name T3211
Test name
Test status
Simulation time 4342784645 ps
CPU time 27.99 seconds
Started Aug 13 06:39:35 PM PDT 24
Finished Aug 13 06:40:03 PM PDT 24
Peak memory 207628 kb
Host smart-9bb8e571-00ff-4493-ab7c-78e1f368fb09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847443442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.1847443442
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_tx_rx_disruption.3432028082
Short name T1255
Test name
Test status
Simulation time 639545415 ps
CPU time 1.75 seconds
Started Aug 13 06:39:58 PM PDT 24
Finished Aug 13 06:40:00 PM PDT 24
Peak memory 207596 kb
Host smart-c840ff3a-d761-47cf-b0c0-fe974736650b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432028082 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.usbdev_tx_rx_disruption.3432028082
Directory /workspace/40.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/400.usbdev_tx_rx_disruption.3472229228
Short name T1832
Test name
Test status
Simulation time 585028693 ps
CPU time 1.73 seconds
Started Aug 13 06:41:58 PM PDT 24
Finished Aug 13 06:42:00 PM PDT 24
Peak memory 207500 kb
Host smart-e97e4014-673d-4a17-828c-d29d0d3fcdaf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472229228 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 400.usbdev_tx_rx_disruption.3472229228
Directory /workspace/400.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/401.usbdev_tx_rx_disruption.1523481300
Short name T1957
Test name
Test status
Simulation time 583879500 ps
CPU time 1.57 seconds
Started Aug 13 06:42:11 PM PDT 24
Finished Aug 13 06:42:12 PM PDT 24
Peak memory 207596 kb
Host smart-055a29c7-52e2-455b-8efb-b80ef095de4b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523481300 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 401.usbdev_tx_rx_disruption.1523481300
Directory /workspace/401.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/402.usbdev_tx_rx_disruption.165494070
Short name T835
Test name
Test status
Simulation time 493245963 ps
CPU time 1.66 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207612 kb
Host smart-6a65f2ff-3b5e-4f87-a630-98b847626349
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165494070 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 402.usbdev_tx_rx_disruption.165494070
Directory /workspace/402.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/403.usbdev_tx_rx_disruption.2577123621
Short name T3633
Test name
Test status
Simulation time 546239490 ps
CPU time 1.67 seconds
Started Aug 13 06:41:54 PM PDT 24
Finished Aug 13 06:41:56 PM PDT 24
Peak memory 207588 kb
Host smart-70e023eb-6fb7-4294-93c0-17133e596cd9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577123621 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 403.usbdev_tx_rx_disruption.2577123621
Directory /workspace/403.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/404.usbdev_tx_rx_disruption.4280308761
Short name T743
Test name
Test status
Simulation time 526849112 ps
CPU time 1.6 seconds
Started Aug 13 06:42:00 PM PDT 24
Finished Aug 13 06:42:02 PM PDT 24
Peak memory 207504 kb
Host smart-5a7b04c1-29a7-4a9e-8078-83c2a63ad01f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280308761 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 404.usbdev_tx_rx_disruption.4280308761
Directory /workspace/404.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/405.usbdev_tx_rx_disruption.3841215537
Short name T2043
Test name
Test status
Simulation time 560812635 ps
CPU time 1.63 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 207568 kb
Host smart-0c442473-e694-4535-91b3-f7810139b8d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841215537 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 405.usbdev_tx_rx_disruption.3841215537
Directory /workspace/405.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/406.usbdev_tx_rx_disruption.3618316936
Short name T2031
Test name
Test status
Simulation time 437552506 ps
CPU time 1.39 seconds
Started Aug 13 06:42:11 PM PDT 24
Finished Aug 13 06:42:12 PM PDT 24
Peak memory 207612 kb
Host smart-638241f0-44f4-4805-9f90-5e857990d128
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618316936 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 406.usbdev_tx_rx_disruption.3618316936
Directory /workspace/406.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/407.usbdev_tx_rx_disruption.3310206229
Short name T2298
Test name
Test status
Simulation time 634173884 ps
CPU time 1.55 seconds
Started Aug 13 06:42:11 PM PDT 24
Finished Aug 13 06:42:13 PM PDT 24
Peak memory 207588 kb
Host smart-83b7ca61-6784-4de5-90b8-07f3d942c1c3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310206229 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 407.usbdev_tx_rx_disruption.3310206229
Directory /workspace/407.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/408.usbdev_tx_rx_disruption.758840228
Short name T2420
Test name
Test status
Simulation time 516453543 ps
CPU time 1.53 seconds
Started Aug 13 06:42:09 PM PDT 24
Finished Aug 13 06:42:11 PM PDT 24
Peak memory 207552 kb
Host smart-e2072e11-5e78-494c-97bb-675d0e97f625
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758840228 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 408.usbdev_tx_rx_disruption.758840228
Directory /workspace/408.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/409.usbdev_tx_rx_disruption.3191775805
Short name T2331
Test name
Test status
Simulation time 491941745 ps
CPU time 1.62 seconds
Started Aug 13 06:42:05 PM PDT 24
Finished Aug 13 06:42:07 PM PDT 24
Peak memory 207588 kb
Host smart-6874cfff-75ab-4b2e-8d0b-9224f9feeb23
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191775805 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 409.usbdev_tx_rx_disruption.3191775805
Directory /workspace/409.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.2606410066
Short name T3287
Test name
Test status
Simulation time 39830635 ps
CPU time 0.65 seconds
Started Aug 13 06:39:48 PM PDT 24
Finished Aug 13 06:39:49 PM PDT 24
Peak memory 207488 kb
Host smart-44c848ed-3a3c-4bb6-891b-a8ce68e1c403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2606410066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.2606410066
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1514542264
Short name T3050
Test name
Test status
Simulation time 4663292410 ps
CPU time 7.97 seconds
Started Aug 13 06:39:39 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 216016 kb
Host smart-8268f96a-c1f8-458b-8d27-77f4747888ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514542264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.1514542264
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.902809304
Short name T3614
Test name
Test status
Simulation time 14600342981 ps
CPU time 17.41 seconds
Started Aug 13 06:39:44 PM PDT 24
Finished Aug 13 06:40:02 PM PDT 24
Peak memory 216020 kb
Host smart-a5d44dc6-9fa6-4520-90ea-ebe4147ccdde
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=902809304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.902809304
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2198682258
Short name T610
Test name
Test status
Simulation time 26409929549 ps
CPU time 31.19 seconds
Started Aug 13 06:39:38 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 216012 kb
Host smart-1ef00602-3486-4daa-b88f-858e252f3a88
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198682258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.2198682258
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2940499240
Short name T2694
Test name
Test status
Simulation time 176919221 ps
CPU time 0.92 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 207540 kb
Host smart-d92355aa-57ab-4a20-a224-dd309c213ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29404
99240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2940499240
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3006784098
Short name T3231
Test name
Test status
Simulation time 180553104 ps
CPU time 0.92 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 207560 kb
Host smart-eb14d2e6-8ed3-41e6-8e97-d4efdfebc245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30067
84098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3006784098
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2838359810
Short name T1682
Test name
Test status
Simulation time 186599093 ps
CPU time 0.93 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:05 PM PDT 24
Peak memory 207604 kb
Host smart-aa3dddb4-fe15-45f6-9a39-d420e8ad0028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28383
59810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2838359810
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.799758623
Short name T3006
Test name
Test status
Simulation time 643335019 ps
CPU time 1.88 seconds
Started Aug 13 06:39:44 PM PDT 24
Finished Aug 13 06:39:46 PM PDT 24
Peak memory 207580 kb
Host smart-0239a76d-8f92-4315-ba26-21080d33ef92
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=799758623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.799758623
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.428007906
Short name T3631
Test name
Test status
Simulation time 26294981320 ps
CPU time 42.58 seconds
Started Aug 13 06:39:41 PM PDT 24
Finished Aug 13 06:40:24 PM PDT 24
Peak memory 207812 kb
Host smart-03abf89c-8b23-4851-b85f-d242fd4ddaa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42800
7906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.428007906
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.3020756127
Short name T1294
Test name
Test status
Simulation time 4978745890 ps
CPU time 35.94 seconds
Started Aug 13 06:39:34 PM PDT 24
Finished Aug 13 06:40:10 PM PDT 24
Peak memory 207828 kb
Host smart-c917f82f-d0c4-4a8b-9c56-d46dac3431cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020756127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.3020756127
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.1252166095
Short name T1044
Test name
Test status
Simulation time 788533310 ps
CPU time 1.96 seconds
Started Aug 13 06:39:47 PM PDT 24
Finished Aug 13 06:39:49 PM PDT 24
Peak memory 207504 kb
Host smart-af585ad1-e42b-43aa-bf2d-34ff252bd91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12521
66095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.1252166095
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.476543729
Short name T2282
Test name
Test status
Simulation time 138831689 ps
CPU time 0.77 seconds
Started Aug 13 06:39:44 PM PDT 24
Finished Aug 13 06:39:45 PM PDT 24
Peak memory 207452 kb
Host smart-0b792175-1fea-4d07-b09f-7751d6d8897b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47654
3729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.476543729
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2577552737
Short name T632
Test name
Test status
Simulation time 42193979 ps
CPU time 0.72 seconds
Started Aug 13 06:40:05 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207492 kb
Host smart-056ed2a9-5128-440e-8ca3-0ae7e992e7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25775
52737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2577552737
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2455596907
Short name T1985
Test name
Test status
Simulation time 725420423 ps
CPU time 2.09 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:39:56 PM PDT 24
Peak memory 207784 kb
Host smart-3b3b4b90-5179-43b1-8f2d-7eb07edf20b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24555
96907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2455596907
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_types.1612942403
Short name T2213
Test name
Test status
Simulation time 383384270 ps
CPU time 1.41 seconds
Started Aug 13 06:39:39 PM PDT 24
Finished Aug 13 06:39:41 PM PDT 24
Peak memory 207516 kb
Host smart-11e2ed4b-c732-41ce-8fe9-c63fa7618dd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1612942403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.1612942403
Directory /workspace/41.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.79498194
Short name T1775
Test name
Test status
Simulation time 224652471 ps
CPU time 1.46 seconds
Started Aug 13 06:39:47 PM PDT 24
Finished Aug 13 06:39:48 PM PDT 24
Peak memory 207668 kb
Host smart-89b093e0-9b03-4f4e-9e6e-97d7f5fbc740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79498
194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.79498194
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1855710486
Short name T1974
Test name
Test status
Simulation time 174873142 ps
CPU time 0.9 seconds
Started Aug 13 06:39:58 PM PDT 24
Finished Aug 13 06:39:59 PM PDT 24
Peak memory 207524 kb
Host smart-e24e985a-7a22-4f71-8f6c-ac8057109f98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1855710486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1855710486
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2799131327
Short name T519
Test name
Test status
Simulation time 152637516 ps
CPU time 0.81 seconds
Started Aug 13 06:39:59 PM PDT 24
Finished Aug 13 06:40:00 PM PDT 24
Peak memory 207496 kb
Host smart-5056195e-ee4e-4daf-be4e-166739cdb8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27991
31327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2799131327
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1306765754
Short name T2409
Test name
Test status
Simulation time 232306100 ps
CPU time 1 seconds
Started Aug 13 06:39:52 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 207528 kb
Host smart-21b6b7d3-c6f7-48bd-ac67-1a700f3a3adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13067
65754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1306765754
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.3874226574
Short name T2329
Test name
Test status
Simulation time 3452364403 ps
CPU time 103.48 seconds
Started Aug 13 06:39:36 PM PDT 24
Finished Aug 13 06:41:19 PM PDT 24
Peak memory 216028 kb
Host smart-fa78f75d-adac-4c7c-9f3b-a70216a62ead
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3874226574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.3874226574
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.319544226
Short name T1337
Test name
Test status
Simulation time 14072556341 ps
CPU time 109.97 seconds
Started Aug 13 06:39:50 PM PDT 24
Finished Aug 13 06:41:40 PM PDT 24
Peak memory 207688 kb
Host smart-75919fb3-fc72-41ae-b462-20c9d2bc6df6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=319544226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.319544226
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.115196239
Short name T1930
Test name
Test status
Simulation time 226008178 ps
CPU time 0.99 seconds
Started Aug 13 06:39:55 PM PDT 24
Finished Aug 13 06:39:56 PM PDT 24
Peak memory 207528 kb
Host smart-f58a843d-bf83-4411-8f2b-b2e096346286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11519
6239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.115196239
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.2746891054
Short name T1999
Test name
Test status
Simulation time 30929493315 ps
CPU time 46.96 seconds
Started Aug 13 06:39:39 PM PDT 24
Finished Aug 13 06:40:26 PM PDT 24
Peak memory 207848 kb
Host smart-6b356603-ebf5-4842-86e4-4aaacec2188d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27468
91054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.2746891054
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1173485032
Short name T3371
Test name
Test status
Simulation time 9860494360 ps
CPU time 13.51 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207828 kb
Host smart-cee4dc70-8283-43af-a113-bbc7fbf2fe85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11734
85032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1173485032
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2108460748
Short name T2337
Test name
Test status
Simulation time 4659521499 ps
CPU time 129.45 seconds
Started Aug 13 06:39:58 PM PDT 24
Finished Aug 13 06:42:07 PM PDT 24
Peak memory 224208 kb
Host smart-516e577a-88c5-4d90-91d6-1db8c5ce1ef9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2108460748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2108460748
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1903461981
Short name T3276
Test name
Test status
Simulation time 1999185704 ps
CPU time 15.23 seconds
Started Aug 13 06:39:53 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 224060 kb
Host smart-3fe763be-1589-4c19-bd15-b5a065440539
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1903461981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1903461981
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3770283009
Short name T549
Test name
Test status
Simulation time 237759361 ps
CPU time 1 seconds
Started Aug 13 06:40:01 PM PDT 24
Finished Aug 13 06:40:02 PM PDT 24
Peak memory 207520 kb
Host smart-447ff06c-c576-4736-9ae9-26b809accfb2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3770283009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3770283009
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1546758566
Short name T905
Test name
Test status
Simulation time 181473334 ps
CPU time 0.94 seconds
Started Aug 13 06:39:41 PM PDT 24
Finished Aug 13 06:39:42 PM PDT 24
Peak memory 207492 kb
Host smart-d1fcb931-cea5-407b-b819-f68aa777024c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15467
58566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1546758566
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.626115323
Short name T3405
Test name
Test status
Simulation time 2901137788 ps
CPU time 85.52 seconds
Started Aug 13 06:39:59 PM PDT 24
Finished Aug 13 06:41:25 PM PDT 24
Peak memory 217324 kb
Host smart-7642bd41-385e-4f64-b53a-aa1fdae3d82c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=626115323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.626115323
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3345253220
Short name T1142
Test name
Test status
Simulation time 148104286 ps
CPU time 0.85 seconds
Started Aug 13 06:39:36 PM PDT 24
Finished Aug 13 06:39:37 PM PDT 24
Peak memory 207552 kb
Host smart-1e04aa0e-ccd1-4c61-8162-c8569c4534cb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3345253220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3345253220
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3488008625
Short name T1987
Test name
Test status
Simulation time 144318175 ps
CPU time 0.81 seconds
Started Aug 13 06:39:44 PM PDT 24
Finished Aug 13 06:39:45 PM PDT 24
Peak memory 207492 kb
Host smart-0ef85822-92b5-4d59-bf3b-387f32f19adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34880
08625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3488008625
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3119586130
Short name T2947
Test name
Test status
Simulation time 218336740 ps
CPU time 0.95 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:22 PM PDT 24
Peak memory 207512 kb
Host smart-2d548c26-f1f0-4d5d-8add-c02713427930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31195
86130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3119586130
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1724251698
Short name T2824
Test name
Test status
Simulation time 151332157 ps
CPU time 0.87 seconds
Started Aug 13 06:39:36 PM PDT 24
Finished Aug 13 06:39:37 PM PDT 24
Peak memory 207488 kb
Host smart-e5f71002-65c1-4df5-8aea-40228e9f0de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17242
51698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1724251698
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2893954042
Short name T2299
Test name
Test status
Simulation time 191990957 ps
CPU time 0.91 seconds
Started Aug 13 06:39:53 PM PDT 24
Finished Aug 13 06:39:54 PM PDT 24
Peak memory 207500 kb
Host smart-d4ddd475-8e3a-4654-9d55-b6c2381f8078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28939
54042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2893954042
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3687244804
Short name T997
Test name
Test status
Simulation time 171598305 ps
CPU time 0.89 seconds
Started Aug 13 06:40:02 PM PDT 24
Finished Aug 13 06:40:03 PM PDT 24
Peak memory 207608 kb
Host smart-acd5a5e3-00b3-49b9-acda-e10b6c452b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36872
44804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3687244804
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.732142059
Short name T206
Test name
Test status
Simulation time 163285010 ps
CPU time 0.86 seconds
Started Aug 13 06:39:57 PM PDT 24
Finished Aug 13 06:39:58 PM PDT 24
Peak memory 207596 kb
Host smart-207c019d-e662-48a4-9719-c688fba018b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73214
2059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.732142059
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2800582615
Short name T3546
Test name
Test status
Simulation time 246599440 ps
CPU time 1.06 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:39:55 PM PDT 24
Peak memory 207596 kb
Host smart-319fe467-3343-476a-bdf6-34a133221ec0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2800582615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2800582615
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.4192480982
Short name T2159
Test name
Test status
Simulation time 146338849 ps
CPU time 0.89 seconds
Started Aug 13 06:39:41 PM PDT 24
Finished Aug 13 06:39:42 PM PDT 24
Peak memory 207420 kb
Host smart-19d1e434-c254-4728-808c-07ce5f77e8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41924
80982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.4192480982
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.495072152
Short name T30
Test name
Test status
Simulation time 44192983 ps
CPU time 0.67 seconds
Started Aug 13 06:39:46 PM PDT 24
Finished Aug 13 06:39:47 PM PDT 24
Peak memory 207536 kb
Host smart-8380e465-857f-43b2-b596-de58eec6b3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49507
2152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.495072152
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3873550822
Short name T91
Test name
Test status
Simulation time 22655983199 ps
CPU time 57.7 seconds
Started Aug 13 06:39:37 PM PDT 24
Finished Aug 13 06:40:35 PM PDT 24
Peak memory 220308 kb
Host smart-6ad1e30a-00b9-402e-b8a6-37e686304176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38735
50822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3873550822
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1408476077
Short name T2376
Test name
Test status
Simulation time 198782706 ps
CPU time 0.95 seconds
Started Aug 13 06:39:51 PM PDT 24
Finished Aug 13 06:39:52 PM PDT 24
Peak memory 207592 kb
Host smart-9ae24578-0d33-43cd-9fc4-b50daf060b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14084
76077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1408476077
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.373559665
Short name T3142
Test name
Test status
Simulation time 174087264 ps
CPU time 0.94 seconds
Started Aug 13 06:39:38 PM PDT 24
Finished Aug 13 06:39:39 PM PDT 24
Peak memory 207504 kb
Host smart-63362932-5fa3-49c7-a77a-e9b1be7fab4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37355
9665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.373559665
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.2163384751
Short name T560
Test name
Test status
Simulation time 178434770 ps
CPU time 0.91 seconds
Started Aug 13 06:39:41 PM PDT 24
Finished Aug 13 06:39:42 PM PDT 24
Peak memory 207500 kb
Host smart-7bb2164d-c631-49a3-a22f-b0417ef1dcbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21633
84751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.2163384751
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3545020400
Short name T939
Test name
Test status
Simulation time 191537716 ps
CPU time 0.96 seconds
Started Aug 13 06:39:50 PM PDT 24
Finished Aug 13 06:39:52 PM PDT 24
Peak memory 207504 kb
Host smart-cc11c635-1570-46b7-93f4-972dee5b4467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35450
20400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3545020400
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2756659409
Short name T2198
Test name
Test status
Simulation time 168240163 ps
CPU time 0.88 seconds
Started Aug 13 06:39:42 PM PDT 24
Finished Aug 13 06:39:43 PM PDT 24
Peak memory 207520 kb
Host smart-efcbf0a2-b234-46c2-90be-3a2fb41a594c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27566
59409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2756659409
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_rx_full.3624969115
Short name T3518
Test name
Test status
Simulation time 261362505 ps
CPU time 1.16 seconds
Started Aug 13 06:39:56 PM PDT 24
Finished Aug 13 06:39:58 PM PDT 24
Peak memory 207420 kb
Host smart-b1d270d8-bfe3-4fa2-a5c0-fc07f0fe90c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36249
69115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.3624969115
Directory /workspace/41.usbdev_rx_full/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3537313931
Short name T2069
Test name
Test status
Simulation time 152625623 ps
CPU time 0.85 seconds
Started Aug 13 06:40:02 PM PDT 24
Finished Aug 13 06:40:03 PM PDT 24
Peak memory 207544 kb
Host smart-d6a5236c-20d6-4848-800c-6fbd68c5da2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35373
13931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3537313931
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3403878745
Short name T2480
Test name
Test status
Simulation time 156625204 ps
CPU time 0.87 seconds
Started Aug 13 06:39:55 PM PDT 24
Finished Aug 13 06:39:56 PM PDT 24
Peak memory 207452 kb
Host smart-f0c1e360-ee50-4618-8eca-3b10d39b4046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34038
78745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3403878745
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1829939882
Short name T3151
Test name
Test status
Simulation time 243731100 ps
CPU time 1.07 seconds
Started Aug 13 06:40:02 PM PDT 24
Finished Aug 13 06:40:03 PM PDT 24
Peak memory 207528 kb
Host smart-d7731f9b-80e9-4191-b30b-ff525168380a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18299
39882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1829939882
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3366472853
Short name T596
Test name
Test status
Simulation time 3386335399 ps
CPU time 25.64 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:40:19 PM PDT 24
Peak memory 217936 kb
Host smart-8b093fe8-b239-438b-b840-692accf86265
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3366472853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3366472853
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3167474405
Short name T2908
Test name
Test status
Simulation time 187396895 ps
CPU time 0.89 seconds
Started Aug 13 06:39:39 PM PDT 24
Finished Aug 13 06:39:40 PM PDT 24
Peak memory 207464 kb
Host smart-8d8a6aa1-4e55-4190-9527-750a4b2becae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31674
74405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3167474405
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3042687726
Short name T834
Test name
Test status
Simulation time 171844986 ps
CPU time 0.91 seconds
Started Aug 13 06:39:41 PM PDT 24
Finished Aug 13 06:39:42 PM PDT 24
Peak memory 207520 kb
Host smart-d4422d16-9bd9-477f-81b4-467363f2b4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30426
87726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3042687726
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.934035580
Short name T2024
Test name
Test status
Simulation time 565622903 ps
CPU time 1.58 seconds
Started Aug 13 06:39:56 PM PDT 24
Finished Aug 13 06:39:58 PM PDT 24
Peak memory 207572 kb
Host smart-f5055b93-9262-4ce1-b02d-8b19388d836f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93403
5580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.934035580
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3015237334
Short name T3345
Test name
Test status
Simulation time 2612262042 ps
CPU time 72.43 seconds
Started Aug 13 06:39:45 PM PDT 24
Finished Aug 13 06:40:57 PM PDT 24
Peak memory 224192 kb
Host smart-f3433614-1084-45fd-a3ae-36f944ba3462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30152
37334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3015237334
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.3191522909
Short name T1605
Test name
Test status
Simulation time 1169790304 ps
CPU time 27.54 seconds
Started Aug 13 06:39:44 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207644 kb
Host smart-cb285a6f-a810-47e9-b076-e7a11709a9df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191522909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.3191522909
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_tx_rx_disruption.2819015609
Short name T2112
Test name
Test status
Simulation time 564592012 ps
CPU time 1.55 seconds
Started Aug 13 06:39:47 PM PDT 24
Finished Aug 13 06:39:48 PM PDT 24
Peak memory 207608 kb
Host smart-ac782859-4d90-4839-9a5c-10b95fa835c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819015609 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.usbdev_tx_rx_disruption.2819015609
Directory /workspace/41.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/410.usbdev_tx_rx_disruption.3131634960
Short name T3167
Test name
Test status
Simulation time 584728552 ps
CPU time 1.5 seconds
Started Aug 13 06:41:53 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207596 kb
Host smart-201421c8-e547-4930-80f2-f9c9281a0eec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131634960 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 410.usbdev_tx_rx_disruption.3131634960
Directory /workspace/410.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/411.usbdev_tx_rx_disruption.1788702436
Short name T2249
Test name
Test status
Simulation time 641049553 ps
CPU time 1.79 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207532 kb
Host smart-c47ddbc0-dc61-4560-a8f8-3696f077393b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788702436 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 411.usbdev_tx_rx_disruption.1788702436
Directory /workspace/411.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/412.usbdev_tx_rx_disruption.3027289756
Short name T852
Test name
Test status
Simulation time 630920537 ps
CPU time 1.59 seconds
Started Aug 13 06:42:10 PM PDT 24
Finished Aug 13 06:42:12 PM PDT 24
Peak memory 207532 kb
Host smart-bb361b66-130a-47ce-8440-75bef95c227f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027289756 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 412.usbdev_tx_rx_disruption.3027289756
Directory /workspace/412.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/413.usbdev_tx_rx_disruption.2217709724
Short name T3384
Test name
Test status
Simulation time 492527587 ps
CPU time 1.55 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207572 kb
Host smart-fdb389f8-50c9-429c-bbda-17dc8a82b9a6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217709724 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 413.usbdev_tx_rx_disruption.2217709724
Directory /workspace/413.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/414.usbdev_tx_rx_disruption.3892911171
Short name T2393
Test name
Test status
Simulation time 555511457 ps
CPU time 1.62 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 207572 kb
Host smart-056b8253-aad5-424b-8130-c6cc880eedc8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892911171 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 414.usbdev_tx_rx_disruption.3892911171
Directory /workspace/414.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/415.usbdev_tx_rx_disruption.1407982893
Short name T2061
Test name
Test status
Simulation time 521736215 ps
CPU time 1.58 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 207476 kb
Host smart-81929869-d588-451d-8f2e-bc3643b8fd78
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407982893 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 415.usbdev_tx_rx_disruption.1407982893
Directory /workspace/415.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/416.usbdev_tx_rx_disruption.2105343350
Short name T1690
Test name
Test status
Simulation time 525262364 ps
CPU time 1.48 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 207560 kb
Host smart-16c84c94-86e9-41c1-b0de-79452e7c8a3b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105343350 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 416.usbdev_tx_rx_disruption.2105343350
Directory /workspace/416.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/417.usbdev_tx_rx_disruption.1436357472
Short name T1630
Test name
Test status
Simulation time 512477320 ps
CPU time 1.65 seconds
Started Aug 13 06:42:17 PM PDT 24
Finished Aug 13 06:42:19 PM PDT 24
Peak memory 207536 kb
Host smart-7b72475e-8897-44ee-8c54-ec1a6586117a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436357472 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 417.usbdev_tx_rx_disruption.1436357472
Directory /workspace/417.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/418.usbdev_tx_rx_disruption.3442837070
Short name T2325
Test name
Test status
Simulation time 597556614 ps
CPU time 1.63 seconds
Started Aug 13 06:42:10 PM PDT 24
Finished Aug 13 06:42:12 PM PDT 24
Peak memory 207532 kb
Host smart-c1959f86-88c0-46ec-88a2-dfea5a070852
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442837070 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 418.usbdev_tx_rx_disruption.3442837070
Directory /workspace/418.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/419.usbdev_tx_rx_disruption.598663207
Short name T1703
Test name
Test status
Simulation time 524979633 ps
CPU time 1.49 seconds
Started Aug 13 06:42:11 PM PDT 24
Finished Aug 13 06:42:12 PM PDT 24
Peak memory 207556 kb
Host smart-c4ca6aa3-84d1-4cc4-8e2b-9096681e582e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598663207 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 419.usbdev_tx_rx_disruption.598663207
Directory /workspace/419.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.757298880
Short name T1094
Test name
Test status
Simulation time 36072903 ps
CPU time 0.68 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207488 kb
Host smart-10fb9a0b-6bd5-4ec6-a4d4-e156dc599c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=757298880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.757298880
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2890093583
Short name T672
Test name
Test status
Simulation time 3803169682 ps
CPU time 5.34 seconds
Started Aug 13 06:40:01 PM PDT 24
Finished Aug 13 06:40:06 PM PDT 24
Peak memory 216028 kb
Host smart-0315e5ca-6c43-47e1-87cc-cf0815e3f9ba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890093583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.2890093583
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3121530154
Short name T2171
Test name
Test status
Simulation time 14701511198 ps
CPU time 15.99 seconds
Started Aug 13 06:40:00 PM PDT 24
Finished Aug 13 06:40:16 PM PDT 24
Peak memory 214864 kb
Host smart-c2221fa8-b0a8-4be1-abdc-a0c7cbd1a27b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121530154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3121530154
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.4174817574
Short name T14
Test name
Test status
Simulation time 24514020374 ps
CPU time 30.66 seconds
Started Aug 13 06:39:44 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 215944 kb
Host smart-1aacedcc-69ba-427d-a3af-b6d035b80efb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174817574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.4174817574
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3201153282
Short name T1754
Test name
Test status
Simulation time 138244531 ps
CPU time 0.83 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207528 kb
Host smart-3096dc64-b707-4baf-a0b8-3b9548315266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32011
53282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3201153282
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3714568706
Short name T2618
Test name
Test status
Simulation time 145347489 ps
CPU time 0.83 seconds
Started Aug 13 06:39:47 PM PDT 24
Finished Aug 13 06:39:48 PM PDT 24
Peak memory 207504 kb
Host smart-3276f556-879b-4055-8305-b8f6d0ee923d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37145
68706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3714568706
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2323042141
Short name T762
Test name
Test status
Simulation time 478062295 ps
CPU time 1.75 seconds
Started Aug 13 06:39:53 PM PDT 24
Finished Aug 13 06:39:55 PM PDT 24
Peak memory 206448 kb
Host smart-2f5befbd-cceb-4ce5-832b-bb92a4309cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23230
42141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2323042141
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1183827456
Short name T108
Test name
Test status
Simulation time 1059200907 ps
CPU time 2.97 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:39:57 PM PDT 24
Peak memory 207720 kb
Host smart-b665e2bd-bfc2-4a7e-b6ed-98e860035303
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1183827456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1183827456
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.934060756
Short name T1864
Test name
Test status
Simulation time 28372748727 ps
CPU time 44.54 seconds
Started Aug 13 06:39:47 PM PDT 24
Finished Aug 13 06:40:32 PM PDT 24
Peak memory 207732 kb
Host smart-90aa8304-5426-4f9b-81df-1c1ce13db3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93406
0756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.934060756
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.3540491789
Short name T943
Test name
Test status
Simulation time 4388171824 ps
CPU time 29.9 seconds
Started Aug 13 06:39:58 PM PDT 24
Finished Aug 13 06:40:28 PM PDT 24
Peak memory 207724 kb
Host smart-5596934b-7049-4363-be5a-7baf7b3b8a90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540491789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.3540491789
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.153471790
Short name T2897
Test name
Test status
Simulation time 1035131117 ps
CPU time 2.28 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:39:57 PM PDT 24
Peak memory 207440 kb
Host smart-74e7140e-b711-4e26-a14f-57ac4587dc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347
1790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.153471790
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2134153325
Short name T2936
Test name
Test status
Simulation time 157684555 ps
CPU time 0.82 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:39:54 PM PDT 24
Peak memory 207556 kb
Host smart-6e1ad5df-0e08-4d9a-be6a-3a0a072c863c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21341
53325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2134153325
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2847075225
Short name T3280
Test name
Test status
Simulation time 43065410 ps
CPU time 0.71 seconds
Started Aug 13 06:39:51 PM PDT 24
Finished Aug 13 06:39:52 PM PDT 24
Peak memory 207460 kb
Host smart-e64f9bd5-6dac-4088-8f1a-c8ae5f8e31dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28470
75225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2847075225
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.447905599
Short name T898
Test name
Test status
Simulation time 848883517 ps
CPU time 2.3 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207800 kb
Host smart-8bf9bef8-0f3c-4261-9a92-9dd114583aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44790
5599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.447905599
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_types.2984651418
Short name T411
Test name
Test status
Simulation time 626798157 ps
CPU time 1.41 seconds
Started Aug 13 06:40:00 PM PDT 24
Finished Aug 13 06:40:01 PM PDT 24
Peak memory 207428 kb
Host smart-5a9dc2e6-77ac-40e0-b0b1-091611887f4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2984651418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.2984651418
Directory /workspace/42.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1344822118
Short name T222
Test name
Test status
Simulation time 363151516 ps
CPU time 2.46 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:39:56 PM PDT 24
Peak memory 207672 kb
Host smart-1a55067c-4a01-44a7-80fd-f4a5ba21b842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13448
22118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1344822118
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1728706216
Short name T3193
Test name
Test status
Simulation time 180960079 ps
CPU time 0.99 seconds
Started Aug 13 06:39:47 PM PDT 24
Finished Aug 13 06:39:48 PM PDT 24
Peak memory 215920 kb
Host smart-a8a26de0-9fe5-4ee2-9af7-9e4d2aa440cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1728706216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1728706216
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1191916882
Short name T2526
Test name
Test status
Simulation time 223223767 ps
CPU time 0.92 seconds
Started Aug 13 06:39:53 PM PDT 24
Finished Aug 13 06:39:54 PM PDT 24
Peak memory 207476 kb
Host smart-485937a4-9f52-4b57-84e0-a8e145dd1180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11919
16882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1191916882
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.683272415
Short name T2194
Test name
Test status
Simulation time 231658013 ps
CPU time 1 seconds
Started Aug 13 06:39:56 PM PDT 24
Finished Aug 13 06:39:57 PM PDT 24
Peak memory 207524 kb
Host smart-4e05beaa-f491-4d94-be9c-b280799d1cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68327
2415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.683272415
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.3564939286
Short name T193
Test name
Test status
Simulation time 4920063884 ps
CPU time 49.84 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:57 PM PDT 24
Peak memory 224140 kb
Host smart-3b9a8446-f211-4986-9203-e57cd95615b5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3564939286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.3564939286
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.3736138853
Short name T1737
Test name
Test status
Simulation time 6300396292 ps
CPU time 42.3 seconds
Started Aug 13 06:39:55 PM PDT 24
Finished Aug 13 06:40:37 PM PDT 24
Peak memory 207816 kb
Host smart-31b72637-859a-45f0-84be-8f8418d7a534
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3736138853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.3736138853
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3863171531
Short name T1759
Test name
Test status
Simulation time 248794024 ps
CPU time 0.96 seconds
Started Aug 13 06:40:00 PM PDT 24
Finished Aug 13 06:40:01 PM PDT 24
Peak memory 207620 kb
Host smart-1e7d3579-8bda-43e3-862e-37aa2dc30c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38631
71531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3863171531
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.3787916904
Short name T1621
Test name
Test status
Simulation time 28528577240 ps
CPU time 46.69 seconds
Started Aug 13 06:39:56 PM PDT 24
Finished Aug 13 06:40:43 PM PDT 24
Peak memory 207868 kb
Host smart-a30002b8-0ae2-462c-afd8-30097d52e021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37879
16904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3787916904
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2771585079
Short name T2753
Test name
Test status
Simulation time 4716206987 ps
CPU time 7.17 seconds
Started Aug 13 06:39:55 PM PDT 24
Finished Aug 13 06:40:02 PM PDT 24
Peak memory 207800 kb
Host smart-0363f69c-27b0-4407-9fe1-e13879a01d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715
85079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2771585079
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2730669036
Short name T1778
Test name
Test status
Simulation time 3079326737 ps
CPU time 22.86 seconds
Started Aug 13 06:39:53 PM PDT 24
Finished Aug 13 06:40:16 PM PDT 24
Peak memory 216848 kb
Host smart-43f393b8-1bb1-4aa3-bb8d-584b54e9a46a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2730669036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2730669036
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1780905541
Short name T3044
Test name
Test status
Simulation time 2724467826 ps
CPU time 78.2 seconds
Started Aug 13 06:40:13 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 215920 kb
Host smart-12a631e8-a7f2-49ba-9ec3-c4aad35f2ab3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1780905541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1780905541
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2584838472
Short name T2378
Test name
Test status
Simulation time 247372773 ps
CPU time 0.99 seconds
Started Aug 13 06:39:52 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 207532 kb
Host smart-499de0b8-bf52-4c8d-9035-2e64e8aa79ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2584838472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2584838472
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.4150347802
Short name T704
Test name
Test status
Simulation time 192031233 ps
CPU time 1.01 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207484 kb
Host smart-5ecdaddc-08d6-487d-9f31-bf349f21800a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41503
47802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.4150347802
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.2022835344
Short name T1591
Test name
Test status
Simulation time 4074825165 ps
CPU time 39.55 seconds
Started Aug 13 06:39:56 PM PDT 24
Finished Aug 13 06:40:36 PM PDT 24
Peak memory 217508 kb
Host smart-22a5577a-2725-460d-9cb6-7263723e5fed
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2022835344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.2022835344
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.4002629810
Short name T784
Test name
Test status
Simulation time 164957179 ps
CPU time 0.95 seconds
Started Aug 13 06:39:55 PM PDT 24
Finished Aug 13 06:39:56 PM PDT 24
Peak memory 207536 kb
Host smart-30ce84d2-9231-472c-83cb-d5cb9c1459f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4002629810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.4002629810
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.303598694
Short name T2681
Test name
Test status
Simulation time 149672799 ps
CPU time 0.85 seconds
Started Aug 13 06:40:03 PM PDT 24
Finished Aug 13 06:40:04 PM PDT 24
Peak memory 207488 kb
Host smart-06e0c45c-5160-4740-9fd2-dda428ccb31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30359
8694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.303598694
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.4091534992
Short name T133
Test name
Test status
Simulation time 255171337 ps
CPU time 1.07 seconds
Started Aug 13 06:39:58 PM PDT 24
Finished Aug 13 06:39:59 PM PDT 24
Peak memory 207492 kb
Host smart-4ee11201-5a00-40a2-b6e2-37befffcc2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40915
34992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.4091534992
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2390266260
Short name T2801
Test name
Test status
Simulation time 212913927 ps
CPU time 0.94 seconds
Started Aug 13 06:39:52 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 207488 kb
Host smart-96a49e05-ad34-409e-8eba-c07c41f1db0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23902
66260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2390266260
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2593176193
Short name T3471
Test name
Test status
Simulation time 170904326 ps
CPU time 0.86 seconds
Started Aug 13 06:39:51 PM PDT 24
Finished Aug 13 06:39:52 PM PDT 24
Peak memory 207496 kb
Host smart-1675c67f-052a-4cb9-9b24-23039ac7b573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25931
76193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2593176193
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1439443071
Short name T495
Test name
Test status
Simulation time 180172771 ps
CPU time 0.99 seconds
Started Aug 13 06:39:51 PM PDT 24
Finished Aug 13 06:39:52 PM PDT 24
Peak memory 207564 kb
Host smart-b3cbf2b3-5ccf-442f-a703-3357b8e5b3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14394
43071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1439443071
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2252888473
Short name T2520
Test name
Test status
Simulation time 149788786 ps
CPU time 0.84 seconds
Started Aug 13 06:39:55 PM PDT 24
Finished Aug 13 06:39:56 PM PDT 24
Peak memory 207588 kb
Host smart-cd329eea-2b07-4e93-b269-f132337b6d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22528
88473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2252888473
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.505070476
Short name T1983
Test name
Test status
Simulation time 259887381 ps
CPU time 1.06 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207596 kb
Host smart-0ef07959-2414-44f2-83e1-b526fd9459ea
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=505070476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.505070476
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.189646368
Short name T3073
Test name
Test status
Simulation time 148291281 ps
CPU time 0.79 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207496 kb
Host smart-0cd6f05e-c1ff-4efe-86a0-89ba2bebfe92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18964
6368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.189646368
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1595668905
Short name T2852
Test name
Test status
Simulation time 35421823 ps
CPU time 0.78 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207516 kb
Host smart-ea63a656-f124-41ce-98b0-7962b79c5f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15956
68905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1595668905
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4251202495
Short name T322
Test name
Test status
Simulation time 6056096423 ps
CPU time 16.22 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:24 PM PDT 24
Peak memory 215948 kb
Host smart-2046d46c-f27a-4151-bdc2-1fa10d1d85d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42512
02495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4251202495
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1851907631
Short name T804
Test name
Test status
Simulation time 193865206 ps
CPU time 0.88 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:12 PM PDT 24
Peak memory 207616 kb
Host smart-b4f4d81c-eed3-45ee-86f9-cc812b444bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18519
07631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1851907631
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3293631283
Short name T3094
Test name
Test status
Simulation time 180283550 ps
CPU time 0.93 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207448 kb
Host smart-fc5c1fb3-a723-4d2b-b98e-bc965c49fb98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
31283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3293631283
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2343669061
Short name T3282
Test name
Test status
Simulation time 279460703 ps
CPU time 1.07 seconds
Started Aug 13 06:39:57 PM PDT 24
Finished Aug 13 06:39:58 PM PDT 24
Peak memory 207460 kb
Host smart-0dd1c8bb-693c-4016-a1b9-c70e0415116a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23436
69061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2343669061
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1847527955
Short name T1940
Test name
Test status
Simulation time 189542072 ps
CPU time 0.91 seconds
Started Aug 13 06:39:52 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 207504 kb
Host smart-6f3cc68b-2557-4919-9028-cab322b1df49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18475
27955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1847527955
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2158961612
Short name T2766
Test name
Test status
Simulation time 144049826 ps
CPU time 0.82 seconds
Started Aug 13 06:40:00 PM PDT 24
Finished Aug 13 06:40:01 PM PDT 24
Peak memory 207432 kb
Host smart-c051a526-2afe-4aee-8a7b-01dee1301333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21589
61612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2158961612
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_rx_full.3382589900
Short name T45
Test name
Test status
Simulation time 336506417 ps
CPU time 1.24 seconds
Started Aug 13 06:39:52 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 207416 kb
Host smart-be12525b-bc97-4f6a-bd59-cca1b66fd46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33825
89900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.3382589900
Directory /workspace/42.usbdev_rx_full/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3899294766
Short name T2855
Test name
Test status
Simulation time 164728472 ps
CPU time 0.84 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:05 PM PDT 24
Peak memory 207572 kb
Host smart-bb5a1d36-ae80-4ccc-99ff-205f835a06a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38992
94766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3899294766
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1966850714
Short name T1104
Test name
Test status
Simulation time 209480356 ps
CPU time 0.88 seconds
Started Aug 13 06:39:59 PM PDT 24
Finished Aug 13 06:40:00 PM PDT 24
Peak memory 207544 kb
Host smart-49c6a622-1709-4cd0-8a9f-0228777f8fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19668
50714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1966850714
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.837908590
Short name T802
Test name
Test status
Simulation time 227834569 ps
CPU time 1.1 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:39:56 PM PDT 24
Peak memory 207520 kb
Host smart-56af329e-f3da-488d-8379-8c54d4402a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83790
8590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.837908590
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2101102258
Short name T1490
Test name
Test status
Simulation time 2296989428 ps
CPU time 22.87 seconds
Started Aug 13 06:39:56 PM PDT 24
Finished Aug 13 06:40:19 PM PDT 24
Peak memory 224072 kb
Host smart-dfaf28fa-b2f2-4036-bc7f-ac6019281ca1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2101102258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2101102258
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2011949169
Short name T2856
Test name
Test status
Simulation time 206666439 ps
CPU time 0.96 seconds
Started Aug 13 06:39:52 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 207508 kb
Host smart-59283be1-b787-4f22-990a-8ea2ac9c758f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20119
49169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2011949169
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2268441637
Short name T3442
Test name
Test status
Simulation time 186525121 ps
CPU time 0.87 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207572 kb
Host smart-9214c5c8-22ae-4309-8966-2d2fdab12588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22684
41637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2268441637
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.1861191192
Short name T2840
Test name
Test status
Simulation time 1323679375 ps
CPU time 2.83 seconds
Started Aug 13 06:39:53 PM PDT 24
Finished Aug 13 06:39:56 PM PDT 24
Peak memory 207756 kb
Host smart-59fe17e2-d20d-4eb5-96cb-d0abbbe4dc81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18611
91192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.1861191192
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.3224472970
Short name T2209
Test name
Test status
Simulation time 2209605130 ps
CPU time 21.73 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:28 PM PDT 24
Peak memory 217624 kb
Host smart-ae6381a9-aeb4-4e07-8faa-d9922f2dfecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32244
72970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3224472970
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.3025589496
Short name T971
Test name
Test status
Simulation time 901249215 ps
CPU time 18.14 seconds
Started Aug 13 06:39:56 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207704 kb
Host smart-9ab5c911-790f-4d6d-9c38-f9a13b415324
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025589496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.3025589496
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_tx_rx_disruption.2088662101
Short name T2352
Test name
Test status
Simulation time 424694654 ps
CPU time 1.5 seconds
Started Aug 13 06:39:59 PM PDT 24
Finished Aug 13 06:40:01 PM PDT 24
Peak memory 207620 kb
Host smart-db3028e2-4ae8-4caa-9bd9-8c661f4923c6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088662101 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.usbdev_tx_rx_disruption.2088662101
Directory /workspace/42.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/420.usbdev_tx_rx_disruption.2934935990
Short name T3562
Test name
Test status
Simulation time 589233260 ps
CPU time 1.63 seconds
Started Aug 13 06:42:13 PM PDT 24
Finished Aug 13 06:42:14 PM PDT 24
Peak memory 207624 kb
Host smart-e4061b60-f9f2-4aa2-8449-9b7fcf7e5928
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934935990 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 420.usbdev_tx_rx_disruption.2934935990
Directory /workspace/420.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/421.usbdev_tx_rx_disruption.1860853253
Short name T2915
Test name
Test status
Simulation time 497175938 ps
CPU time 1.62 seconds
Started Aug 13 06:42:06 PM PDT 24
Finished Aug 13 06:42:07 PM PDT 24
Peak memory 207536 kb
Host smart-9c32c240-3368-49b2-9e57-d1b8dfe959fc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860853253 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 421.usbdev_tx_rx_disruption.1860853253
Directory /workspace/421.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/422.usbdev_tx_rx_disruption.2784110756
Short name T3055
Test name
Test status
Simulation time 535909572 ps
CPU time 1.52 seconds
Started Aug 13 06:41:59 PM PDT 24
Finished Aug 13 06:42:01 PM PDT 24
Peak memory 207572 kb
Host smart-7c2997a2-902b-4c2c-938a-d4bfbfc41b73
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784110756 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 422.usbdev_tx_rx_disruption.2784110756
Directory /workspace/422.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/423.usbdev_tx_rx_disruption.4163128919
Short name T2497
Test name
Test status
Simulation time 611655256 ps
CPU time 1.67 seconds
Started Aug 13 06:42:08 PM PDT 24
Finished Aug 13 06:42:10 PM PDT 24
Peak memory 207612 kb
Host smart-cd7e62da-be8c-4bea-8762-a2ba3bffd856
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163128919 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 423.usbdev_tx_rx_disruption.4163128919
Directory /workspace/423.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/424.usbdev_tx_rx_disruption.168708836
Short name T845
Test name
Test status
Simulation time 584154548 ps
CPU time 1.63 seconds
Started Aug 13 06:42:25 PM PDT 24
Finished Aug 13 06:42:27 PM PDT 24
Peak memory 207592 kb
Host smart-18770580-04f8-4437-a8f5-75cbf3f51634
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168708836 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 424.usbdev_tx_rx_disruption.168708836
Directory /workspace/424.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/425.usbdev_tx_rx_disruption.3319691805
Short name T116
Test name
Test status
Simulation time 655544860 ps
CPU time 1.83 seconds
Started Aug 13 06:41:56 PM PDT 24
Finished Aug 13 06:41:58 PM PDT 24
Peak memory 207580 kb
Host smart-063a2cac-e2ee-48f1-9e8d-bd84ca89045e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319691805 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 425.usbdev_tx_rx_disruption.3319691805
Directory /workspace/425.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/426.usbdev_tx_rx_disruption.1451871679
Short name T2630
Test name
Test status
Simulation time 471668573 ps
CPU time 1.5 seconds
Started Aug 13 06:42:01 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 207572 kb
Host smart-191e52d1-4bc6-4c59-bb09-eaf9bef33bef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451871679 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 426.usbdev_tx_rx_disruption.1451871679
Directory /workspace/426.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/427.usbdev_tx_rx_disruption.2207403677
Short name T3132
Test name
Test status
Simulation time 494611314 ps
CPU time 1.71 seconds
Started Aug 13 06:42:30 PM PDT 24
Finished Aug 13 06:42:32 PM PDT 24
Peak memory 207600 kb
Host smart-6fee619f-0890-4a71-9f8f-c27c4fc35a0a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207403677 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 427.usbdev_tx_rx_disruption.2207403677
Directory /workspace/427.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/428.usbdev_tx_rx_disruption.2951924387
Short name T3317
Test name
Test status
Simulation time 495887427 ps
CPU time 1.48 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:23 PM PDT 24
Peak memory 207584 kb
Host smart-5811f11f-148f-439e-ac03-75c51127494a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951924387 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 428.usbdev_tx_rx_disruption.2951924387
Directory /workspace/428.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/429.usbdev_tx_rx_disruption.3109465056
Short name T3031
Test name
Test status
Simulation time 520744687 ps
CPU time 1.64 seconds
Started Aug 13 06:42:25 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207536 kb
Host smart-527cfbda-73c1-40f2-879b-a50d8b3c1613
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109465056 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 429.usbdev_tx_rx_disruption.3109465056
Directory /workspace/429.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.1710303317
Short name T1125
Test name
Test status
Simulation time 61633488 ps
CPU time 0.72 seconds
Started Aug 13 06:40:05 PM PDT 24
Finished Aug 13 06:40:06 PM PDT 24
Peak memory 207396 kb
Host smart-21eca470-79c0-43af-b793-9f0c806b5fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1710303317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1710303317
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2494752865
Short name T778
Test name
Test status
Simulation time 19721823161 ps
CPU time 22.82 seconds
Started Aug 13 06:39:57 PM PDT 24
Finished Aug 13 06:40:19 PM PDT 24
Peak memory 207796 kb
Host smart-e4a9cb61-5cff-4cd1-a7a8-b76b5fc84df5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494752865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2494752865
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1845034108
Short name T3135
Test name
Test status
Simulation time 25241786684 ps
CPU time 37.95 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:40:33 PM PDT 24
Peak memory 216016 kb
Host smart-4d66122a-100b-44af-9a48-d73c80c3e26e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845034108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.1845034108
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.568221574
Short name T1290
Test name
Test status
Simulation time 162111302 ps
CPU time 0.86 seconds
Started Aug 13 06:40:03 PM PDT 24
Finished Aug 13 06:40:04 PM PDT 24
Peak memory 207492 kb
Host smart-8e5bd67b-e09e-4e3f-8740-2dfa3e58a597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56822
1574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.568221574
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1314851057
Short name T3082
Test name
Test status
Simulation time 191243845 ps
CPU time 0.91 seconds
Started Aug 13 06:39:54 PM PDT 24
Finished Aug 13 06:39:55 PM PDT 24
Peak memory 207540 kb
Host smart-7557a939-332a-4072-ad06-67d9cdeee112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13148
51057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1314851057
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.642771385
Short name T965
Test name
Test status
Simulation time 384706840 ps
CPU time 1.44 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:12 PM PDT 24
Peak memory 207616 kb
Host smart-d8b9b42e-c305-4596-b0a1-8a912bafcd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64277
1385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.642771385
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3262971793
Short name T3234
Test name
Test status
Simulation time 395943012 ps
CPU time 1.34 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:06 PM PDT 24
Peak memory 207416 kb
Host smart-a62883b8-9d84-4928-8aa4-7f9fc58fbc06
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3262971793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3262971793
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.1428881009
Short name T525
Test name
Test status
Simulation time 36078018574 ps
CPU time 61.23 seconds
Started Aug 13 06:39:56 PM PDT 24
Finished Aug 13 06:40:57 PM PDT 24
Peak memory 207728 kb
Host smart-7f484a31-4f13-462b-822f-be14e5d8487e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14288
81009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.1428881009
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.2661556305
Short name T2599
Test name
Test status
Simulation time 2482138910 ps
CPU time 22.03 seconds
Started Aug 13 06:40:00 PM PDT 24
Finished Aug 13 06:40:23 PM PDT 24
Peak memory 207752 kb
Host smart-80a0af5b-7dbc-4a15-94fd-0b130a96ef1b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661556305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.2661556305
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1451360202
Short name T443
Test name
Test status
Simulation time 513247012 ps
CPU time 1.38 seconds
Started Aug 13 06:39:57 PM PDT 24
Finished Aug 13 06:39:59 PM PDT 24
Peak memory 207464 kb
Host smart-9c406d7c-4023-478e-aaf3-294293902995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14513
60202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1451360202
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.4256011323
Short name T1276
Test name
Test status
Simulation time 164682310 ps
CPU time 0.88 seconds
Started Aug 13 06:40:02 PM PDT 24
Finished Aug 13 06:40:03 PM PDT 24
Peak memory 207536 kb
Host smart-4d0854b7-87f4-4124-8eaf-a9bee90be54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42560
11323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.4256011323
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2350872492
Short name T2265
Test name
Test status
Simulation time 46268127 ps
CPU time 0.74 seconds
Started Aug 13 06:40:05 PM PDT 24
Finished Aug 13 06:40:06 PM PDT 24
Peak memory 207508 kb
Host smart-34ad2ad4-6579-4d3d-abb3-151bb7dc12cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23508
72492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2350872492
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.2023464058
Short name T1243
Test name
Test status
Simulation time 871199150 ps
CPU time 2.34 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:06 PM PDT 24
Peak memory 207724 kb
Host smart-16d12444-d692-465d-9fe6-719dcfb85516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20234
64058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2023464058
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_types.1862925383
Short name T3386
Test name
Test status
Simulation time 428828705 ps
CPU time 1.32 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:05 PM PDT 24
Peak memory 207572 kb
Host smart-7cb91761-6f6b-4d2b-ba88-7421b702ed06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1862925383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.1862925383
Directory /workspace/43.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.981888380
Short name T1601
Test name
Test status
Simulation time 266555794 ps
CPU time 2.26 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207712 kb
Host smart-3b75fab3-3e53-4b0b-8e5e-39cf80083fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98188
8380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.981888380
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3277277183
Short name T3598
Test name
Test status
Simulation time 228452851 ps
CPU time 1.17 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:06 PM PDT 24
Peak memory 223992 kb
Host smart-36620482-4ece-49d0-a156-2a97e93c0792
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3277277183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3277277183
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.103732738
Short name T2700
Test name
Test status
Simulation time 141655890 ps
CPU time 0.79 seconds
Started Aug 13 06:40:02 PM PDT 24
Finished Aug 13 06:40:03 PM PDT 24
Peak memory 207444 kb
Host smart-15d2a4ba-03e5-496d-8162-9985c72eab61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10373
2738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.103732738
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3308244409
Short name T878
Test name
Test status
Simulation time 225673042 ps
CPU time 1.02 seconds
Started Aug 13 06:40:02 PM PDT 24
Finished Aug 13 06:40:03 PM PDT 24
Peak memory 207440 kb
Host smart-7287b3a0-f4af-4cfc-9c90-451c2205cbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33082
44409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3308244409
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.2046532542
Short name T1861
Test name
Test status
Simulation time 4009615905 ps
CPU time 121.15 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:42:11 PM PDT 24
Peak memory 215952 kb
Host smart-581fe77c-fb4c-4fd9-b11a-1bd4de8c64d5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2046532542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.2046532542
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.1766501229
Short name T2657
Test name
Test status
Simulation time 7784984826 ps
CPU time 47.33 seconds
Started Aug 13 06:40:02 PM PDT 24
Finished Aug 13 06:40:49 PM PDT 24
Peak memory 207772 kb
Host smart-145ec3f2-4cc8-4318-9e66-f7ff349d3fea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1766501229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.1766501229
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.85278945
Short name T2832
Test name
Test status
Simulation time 218176772 ps
CPU time 0.94 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207512 kb
Host smart-298f5e8d-affd-4bc8-a317-8dcea5ebba19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85278
945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.85278945
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.62121918
Short name T2260
Test name
Test status
Simulation time 7263535978 ps
CPU time 14.56 seconds
Started Aug 13 06:39:58 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207716 kb
Host smart-88d46d71-7cfb-41ee-bdca-c61269b9b1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62121
918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.62121918
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1315280697
Short name T2984
Test name
Test status
Simulation time 10852135492 ps
CPU time 13.91 seconds
Started Aug 13 06:39:59 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207772 kb
Host smart-9d2ebfee-ecae-4b29-a66b-5e8e9aa1ee9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13152
80697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1315280697
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1490196588
Short name T1172
Test name
Test status
Simulation time 5386587981 ps
CPU time 43.74 seconds
Started Aug 13 06:40:05 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 219612 kb
Host smart-25434d5d-24c1-43fc-8dd2-35432e3c93e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1490196588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1490196588
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3155622356
Short name T889
Test name
Test status
Simulation time 2701373123 ps
CPU time 20.15 seconds
Started Aug 13 06:40:02 PM PDT 24
Finished Aug 13 06:40:22 PM PDT 24
Peak memory 224088 kb
Host smart-771a448f-85fc-43c0-ac27-ed79b5dc0678
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3155622356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3155622356
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2174774300
Short name T1846
Test name
Test status
Simulation time 235282957 ps
CPU time 0.96 seconds
Started Aug 13 06:39:53 PM PDT 24
Finished Aug 13 06:39:54 PM PDT 24
Peak memory 207532 kb
Host smart-cbd616cf-e289-41f5-ad50-506434753b6d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2174774300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2174774300
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.4294704162
Short name T1483
Test name
Test status
Simulation time 218300120 ps
CPU time 1.01 seconds
Started Aug 13 06:39:52 PM PDT 24
Finished Aug 13 06:39:53 PM PDT 24
Peak memory 207452 kb
Host smart-458deb81-c3eb-41c7-9ad2-5b630a5909ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42947
04162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.4294704162
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.989500024
Short name T1567
Test name
Test status
Simulation time 2739661675 ps
CPU time 25.77 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:37 PM PDT 24
Peak memory 217640 kb
Host smart-bde68491-3a8c-4028-ae65-b2f1c1b9f22b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=989500024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.989500024
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1431813659
Short name T3289
Test name
Test status
Simulation time 170519199 ps
CPU time 0.93 seconds
Started Aug 13 06:40:03 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207544 kb
Host smart-293fb915-e42d-49f5-9110-178605318dfb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1431813659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1431813659
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.906256300
Short name T2057
Test name
Test status
Simulation time 163179229 ps
CPU time 0.83 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207532 kb
Host smart-91b1a793-25a5-4bec-a24f-a9d07ededc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90625
6300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.906256300
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.4232475638
Short name T146
Test name
Test status
Simulation time 206822154 ps
CPU time 0.97 seconds
Started Aug 13 06:40:05 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207524 kb
Host smart-33b15cdb-1fe0-40f2-9eee-7e4ce48a0003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42324
75638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.4232475638
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.866232751
Short name T1620
Test name
Test status
Simulation time 193152950 ps
CPU time 0.95 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207428 kb
Host smart-e635c6ff-5fa9-4e76-8172-9bb67feeecf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86623
2751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.866232751
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3761138130
Short name T994
Test name
Test status
Simulation time 149247599 ps
CPU time 0.89 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207536 kb
Host smart-a93775b9-3108-4458-a2c1-8513a93d9b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37611
38130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3761138130
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.4198102297
Short name T3175
Test name
Test status
Simulation time 175014011 ps
CPU time 0.9 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207564 kb
Host smart-1a130695-10db-448e-859d-6508235e7619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41981
02297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.4198102297
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3898525996
Short name T2750
Test name
Test status
Simulation time 148651532 ps
CPU time 0.84 seconds
Started Aug 13 06:40:00 PM PDT 24
Finished Aug 13 06:40:01 PM PDT 24
Peak memory 207504 kb
Host smart-f7e3f2cc-5436-4191-a942-6e7728930115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38985
25996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3898525996
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2477799473
Short name T3086
Test name
Test status
Simulation time 224642333 ps
CPU time 1.06 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:10 PM PDT 24
Peak memory 207600 kb
Host smart-5e684ddc-8424-48f0-87b6-059005d561ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2477799473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2477799473
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2588328391
Short name T3358
Test name
Test status
Simulation time 143651375 ps
CPU time 0.8 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207460 kb
Host smart-d5c44290-e73d-4512-b95d-f5ad0a8e462a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883
28391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2588328391
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3712287760
Short name T2777
Test name
Test status
Simulation time 33566309 ps
CPU time 0.67 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207576 kb
Host smart-684ad01d-452b-4f80-9ad1-b3100940d761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37122
87760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3712287760
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2611077394
Short name T300
Test name
Test status
Simulation time 10748747796 ps
CPU time 29.12 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:35 PM PDT 24
Peak memory 216032 kb
Host smart-2f151f69-93b5-4837-8a61-b276c6ae0826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26110
77394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2611077394
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.793905738
Short name T3346
Test name
Test status
Simulation time 212144980 ps
CPU time 0.97 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207588 kb
Host smart-4787c2db-2384-4fcb-a8ab-416533057985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79390
5738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.793905738
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3485964703
Short name T3270
Test name
Test status
Simulation time 226624871 ps
CPU time 1.01 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207480 kb
Host smart-68f68a78-45ca-490b-9ef1-cdc40e771c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34859
64703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3485964703
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1268957788
Short name T281
Test name
Test status
Simulation time 213034146 ps
CPU time 1.04 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:05 PM PDT 24
Peak memory 207500 kb
Host smart-5171ac4d-730e-44fc-b4d9-39ea19932f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12689
57788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1268957788
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.1184915094
Short name T1881
Test name
Test status
Simulation time 184563502 ps
CPU time 0.91 seconds
Started Aug 13 06:40:14 PM PDT 24
Finished Aug 13 06:40:15 PM PDT 24
Peak memory 206372 kb
Host smart-21890644-a9bb-43be-b0e6-19ca155e335c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11849
15094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.1184915094
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2876424903
Short name T3586
Test name
Test status
Simulation time 144286283 ps
CPU time 0.85 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:17 PM PDT 24
Peak memory 207500 kb
Host smart-45a1c584-9dc7-4f20-aad8-7be5a64ef068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28764
24903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2876424903
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_rx_full.3028528493
Short name T1319
Test name
Test status
Simulation time 272072986 ps
CPU time 1.13 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207536 kb
Host smart-eac4a9d7-32c9-49bb-acc7-cf1a73cd503e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30285
28493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.3028528493
Directory /workspace/43.usbdev_rx_full/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2108347931
Short name T3148
Test name
Test status
Simulation time 169210469 ps
CPU time 0.85 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207496 kb
Host smart-63d76498-d1a3-4c8c-a3fa-ddb1cf29d82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21083
47931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2108347931
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2224014797
Short name T2012
Test name
Test status
Simulation time 157918215 ps
CPU time 0.89 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207540 kb
Host smart-3a5fc6a2-79cb-4ae7-9ba1-55a6ba4467f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
14797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2224014797
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3545916562
Short name T2686
Test name
Test status
Simulation time 224331372 ps
CPU time 1.1 seconds
Started Aug 13 06:40:01 PM PDT 24
Finished Aug 13 06:40:02 PM PDT 24
Peak memory 207448 kb
Host smart-a8050da4-7ed4-430b-8a5a-c0e6e36e5090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35459
16562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3545916562
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1961528940
Short name T1540
Test name
Test status
Simulation time 2193279128 ps
CPU time 60.27 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 224104 kb
Host smart-29e8de02-f18e-4d5d-8629-52ad53e01a9b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1961528940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1961528940
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1267572607
Short name T1822
Test name
Test status
Simulation time 149189728 ps
CPU time 0.89 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207512 kb
Host smart-d0f37e94-0fec-4c5e-bf0d-ebdb75fcdb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12675
72607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1267572607
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3964415228
Short name T1777
Test name
Test status
Simulation time 190160300 ps
CPU time 0.9 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207616 kb
Host smart-3bee4501-a0f6-45fb-9c57-810b13f1d488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39644
15228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3964415228
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.837557792
Short name T2567
Test name
Test status
Simulation time 1157140956 ps
CPU time 2.65 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:10 PM PDT 24
Peak memory 207780 kb
Host smart-0505e446-58ce-44f4-87b8-2d5f24858d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83755
7792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.837557792
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1351656259
Short name T3278
Test name
Test status
Simulation time 2248190164 ps
CPU time 22.14 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:34 PM PDT 24
Peak memory 215976 kb
Host smart-e83100a6-c047-43cd-9a94-e531b82e0926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13516
56259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1351656259
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.1949332271
Short name T1800
Test name
Test status
Simulation time 2897173278 ps
CPU time 18.39 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:25 PM PDT 24
Peak memory 207752 kb
Host smart-6b1f84c3-bf96-4d5f-9d90-6fe7f0cfa3af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949332271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.1949332271
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_tx_rx_disruption.2321212690
Short name T3535
Test name
Test status
Simulation time 488094905 ps
CPU time 1.58 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207556 kb
Host smart-57c75ede-60d6-4cc5-bfd8-252523f02d19
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321212690 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.usbdev_tx_rx_disruption.2321212690
Directory /workspace/43.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/430.usbdev_tx_rx_disruption.222898222
Short name T2767
Test name
Test status
Simulation time 465981248 ps
CPU time 1.66 seconds
Started Aug 13 06:42:18 PM PDT 24
Finished Aug 13 06:42:20 PM PDT 24
Peak memory 207632 kb
Host smart-05b3732c-15c7-485b-8ca6-09e472df5c3b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222898222 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 430.usbdev_tx_rx_disruption.222898222
Directory /workspace/430.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/431.usbdev_tx_rx_disruption.1124392612
Short name T2429
Test name
Test status
Simulation time 445854224 ps
CPU time 1.36 seconds
Started Aug 13 06:42:11 PM PDT 24
Finished Aug 13 06:42:13 PM PDT 24
Peak memory 207588 kb
Host smart-5f12f0d6-3575-4b81-b56e-857c601875fb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124392612 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 431.usbdev_tx_rx_disruption.1124392612
Directory /workspace/431.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/432.usbdev_tx_rx_disruption.553161683
Short name T2613
Test name
Test status
Simulation time 617876294 ps
CPU time 1.6 seconds
Started Aug 13 06:42:37 PM PDT 24
Finished Aug 13 06:42:38 PM PDT 24
Peak memory 207556 kb
Host smart-65d92331-0170-43a1-8aea-6ac8124afdbe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553161683 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 432.usbdev_tx_rx_disruption.553161683
Directory /workspace/432.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/433.usbdev_tx_rx_disruption.3404552405
Short name T823
Test name
Test status
Simulation time 538561281 ps
CPU time 1.66 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 207612 kb
Host smart-19c9964c-f8eb-4d92-b74c-21fb398dfd20
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404552405 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 433.usbdev_tx_rx_disruption.3404552405
Directory /workspace/433.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/434.usbdev_tx_rx_disruption.2437029584
Short name T1242
Test name
Test status
Simulation time 535162055 ps
CPU time 1.76 seconds
Started Aug 13 06:42:31 PM PDT 24
Finished Aug 13 06:42:33 PM PDT 24
Peak memory 207584 kb
Host smart-c7bb8360-8153-40d9-8c5f-c281a3527465
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437029584 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 434.usbdev_tx_rx_disruption.2437029584
Directory /workspace/434.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/435.usbdev_tx_rx_disruption.1368563650
Short name T2647
Test name
Test status
Simulation time 484475421 ps
CPU time 1.62 seconds
Started Aug 13 06:42:25 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 207532 kb
Host smart-f61fba74-895a-4221-9605-9b3cd45188ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368563650 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 435.usbdev_tx_rx_disruption.1368563650
Directory /workspace/435.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/436.usbdev_tx_rx_disruption.3749522768
Short name T2207
Test name
Test status
Simulation time 533245509 ps
CPU time 1.69 seconds
Started Aug 13 06:42:10 PM PDT 24
Finished Aug 13 06:42:11 PM PDT 24
Peak memory 207580 kb
Host smart-d41f2177-2ae6-43af-b9d1-0a1ba6f0aa67
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749522768 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 436.usbdev_tx_rx_disruption.3749522768
Directory /workspace/436.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/437.usbdev_tx_rx_disruption.3265455446
Short name T1662
Test name
Test status
Simulation time 560863192 ps
CPU time 1.6 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207608 kb
Host smart-dd7363fb-77c9-4eb0-9101-40839b52815e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265455446 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 437.usbdev_tx_rx_disruption.3265455446
Directory /workspace/437.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/438.usbdev_tx_rx_disruption.781105101
Short name T1299
Test name
Test status
Simulation time 584126365 ps
CPU time 1.65 seconds
Started Aug 13 06:42:30 PM PDT 24
Finished Aug 13 06:42:32 PM PDT 24
Peak memory 207488 kb
Host smart-731dd663-09b4-4a49-8130-e8aaf2b55ae4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781105101 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 438.usbdev_tx_rx_disruption.781105101
Directory /workspace/438.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/439.usbdev_tx_rx_disruption.1368525306
Short name T1152
Test name
Test status
Simulation time 494392967 ps
CPU time 1.46 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207572 kb
Host smart-3f1e8908-f28a-4f1b-96dc-b35f0c83df5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368525306 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 439.usbdev_tx_rx_disruption.1368525306
Directory /workspace/439.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.1650212131
Short name T744
Test name
Test status
Simulation time 48113739 ps
CPU time 0.68 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207464 kb
Host smart-51b2ed2b-dbd9-40fb-abdc-6c8520118b9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1650212131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.1650212131
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.665920858
Short name T2230
Test name
Test status
Simulation time 10493081827 ps
CPU time 15.03 seconds
Started Aug 13 06:39:57 PM PDT 24
Finished Aug 13 06:40:12 PM PDT 24
Peak memory 207760 kb
Host smart-0bea7676-44d3-4f70-93d9-60df5d946eef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665920858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_disconnect.665920858
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.566576792
Short name T1434
Test name
Test status
Simulation time 14256245419 ps
CPU time 16.69 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:25 PM PDT 24
Peak memory 216028 kb
Host smart-78f38120-7d5e-4350-8323-94c8e2257aa2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=566576792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.566576792
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2307344212
Short name T2905
Test name
Test status
Simulation time 25410291701 ps
CPU time 34.27 seconds
Started Aug 13 06:40:14 PM PDT 24
Finished Aug 13 06:40:49 PM PDT 24
Peak memory 215976 kb
Host smart-cacf883d-44c0-47bf-900b-82bc09606b9c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307344212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.2307344212
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3616189494
Short name T1966
Test name
Test status
Simulation time 150942735 ps
CPU time 0.85 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207420 kb
Host smart-08ff0f88-a6cb-4e9c-9665-a5d3504481f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36161
89494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3616189494
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1001352456
Short name T3147
Test name
Test status
Simulation time 188506680 ps
CPU time 0.91 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207536 kb
Host smart-1fa87a5b-39be-4730-a271-15e831cbf003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10013
52456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1001352456
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.3033872469
Short name T1606
Test name
Test status
Simulation time 368390064 ps
CPU time 1.38 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 206448 kb
Host smart-0024f4d1-cc28-4b41-bad8-9acc4113a51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30338
72469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.3033872469
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.466661079
Short name T3422
Test name
Test status
Simulation time 934019179 ps
CPU time 2.63 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207840 kb
Host smart-7e9edfb7-284b-412f-b4bb-2ff629be52b7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=466661079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.466661079
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1097831774
Short name T3607
Test name
Test status
Simulation time 26680946514 ps
CPU time 46.92 seconds
Started Aug 13 06:40:05 PM PDT 24
Finished Aug 13 06:40:53 PM PDT 24
Peak memory 207744 kb
Host smart-24a029f0-7596-4118-b573-e02bffd7ec4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10978
31774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1097831774
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.2213819729
Short name T2142
Test name
Test status
Simulation time 1473288077 ps
CPU time 33.79 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 207796 kb
Host smart-8de91680-e83d-4730-8da5-cc525c9eb9ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213819729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.2213819729
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2873988893
Short name T3079
Test name
Test status
Simulation time 713616551 ps
CPU time 1.79 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:06 PM PDT 24
Peak memory 207540 kb
Host smart-a209927f-afec-4082-9a33-a1acf3c3b1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28739
88893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2873988893
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.1975179315
Short name T55
Test name
Test status
Simulation time 151240423 ps
CPU time 0.8 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207552 kb
Host smart-5dc1c4eb-978b-4b9e-9fda-4b4142ad9801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
79315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1975179315
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1631722765
Short name T2113
Test name
Test status
Simulation time 37449403 ps
CPU time 0.7 seconds
Started Aug 13 06:40:02 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207404 kb
Host smart-8adfafea-5a78-4d8a-ba88-1a8ed1e86536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317
22765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1631722765
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2760811618
Short name T733
Test name
Test status
Simulation time 1015438469 ps
CPU time 2.49 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207796 kb
Host smart-0af24e1f-c6a7-4c43-9c44-ac448a97ba76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27608
11618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2760811618
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_types.197718554
Short name T212
Test name
Test status
Simulation time 212829791 ps
CPU time 0.98 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207560 kb
Host smart-83b27e2d-d441-4f82-b537-fc78483cd0c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=197718554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.197718554
Directory /workspace/44.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3985391014
Short name T714
Test name
Test status
Simulation time 219323101 ps
CPU time 2.54 seconds
Started Aug 13 06:40:05 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207656 kb
Host smart-3f661618-44c2-4db7-b787-b6e49a3354e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39853
91014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3985391014
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1166394108
Short name T720
Test name
Test status
Simulation time 208494755 ps
CPU time 0.99 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207508 kb
Host smart-057df2d5-872c-4d8f-a8ac-265cbfa3f345
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1166394108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1166394108
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.329975732
Short name T2270
Test name
Test status
Simulation time 139697407 ps
CPU time 0.82 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207480 kb
Host smart-a77eed34-6e83-49f5-8a9f-2a9303ce18d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32997
5732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.329975732
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1950549327
Short name T1295
Test name
Test status
Simulation time 212939168 ps
CPU time 0.99 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:10 PM PDT 24
Peak memory 207372 kb
Host smart-47933a82-f3a8-4f92-b78f-edb29dd80a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19505
49327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1950549327
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.3524125277
Short name T589
Test name
Test status
Simulation time 4631319090 ps
CPU time 139.29 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:42:23 PM PDT 24
Peak memory 218516 kb
Host smart-d27c140b-0064-40e7-b5e6-0ab9158359b4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3524125277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3524125277
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.2428573615
Short name T1230
Test name
Test status
Simulation time 12616818973 ps
CPU time 165.77 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:42:52 PM PDT 24
Peak memory 207688 kb
Host smart-8939b416-1a38-40cf-b6a3-58f1a560aa0f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2428573615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.2428573615
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.627994050
Short name T2554
Test name
Test status
Simulation time 233194424 ps
CPU time 1.06 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:05 PM PDT 24
Peak memory 207496 kb
Host smart-88708524-8811-4a2b-8705-6b3dc81d8cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62799
4050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.627994050
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3483354051
Short name T3275
Test name
Test status
Simulation time 32386473003 ps
CPU time 54.22 seconds
Started Aug 13 06:40:04 PM PDT 24
Finished Aug 13 06:40:58 PM PDT 24
Peak memory 207724 kb
Host smart-2d68fc52-5ddb-44ee-8f4d-41d859429e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34833
54051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3483354051
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2474075210
Short name T1720
Test name
Test status
Simulation time 8626966926 ps
CPU time 11 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:23 PM PDT 24
Peak memory 207788 kb
Host smart-c6df075b-650a-4a95-8e7f-7d7980e04286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24740
75210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2474075210
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.1288751309
Short name T3472
Test name
Test status
Simulation time 3313225911 ps
CPU time 24.7 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:34 PM PDT 24
Peak memory 218468 kb
Host smart-10275de1-32de-4789-adc3-62843f4fd488
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1288751309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1288751309
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.358368581
Short name T3404
Test name
Test status
Simulation time 2018276852 ps
CPU time 20.46 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:33 PM PDT 24
Peak memory 217524 kb
Host smart-b0f3b3b5-d0e1-4a4b-b696-34b57ec52640
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=358368581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.358368581
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.4035594484
Short name T2164
Test name
Test status
Simulation time 266040443 ps
CPU time 1.06 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207516 kb
Host smart-10e95a92-5a2e-4b32-81e8-4eef76a586b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4035594484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.4035594484
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.331022796
Short name T2643
Test name
Test status
Simulation time 194929536 ps
CPU time 0.97 seconds
Started Aug 13 06:39:58 PM PDT 24
Finished Aug 13 06:39:59 PM PDT 24
Peak memory 207492 kb
Host smart-fbc847a3-2e61-4866-b46e-801d710a463e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33102
2796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.331022796
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.4074763402
Short name T2246
Test name
Test status
Simulation time 3385481051 ps
CPU time 100.59 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:41:49 PM PDT 24
Peak memory 217160 kb
Host smart-f9304788-ea8a-4365-9d0f-4d7012caeb2d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4074763402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.4074763402
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.476984791
Short name T1766
Test name
Test status
Simulation time 150730985 ps
CPU time 0.87 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207396 kb
Host smart-f0c49b3c-2980-4249-bb59-2a43208f0e8c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=476984791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.476984791
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3069192199
Short name T1033
Test name
Test status
Simulation time 163076898 ps
CPU time 0.9 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207520 kb
Host smart-04cd5331-7621-4d16-80e0-ff468b0bc666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30691
92199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3069192199
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3458257472
Short name T3387
Test name
Test status
Simulation time 217017391 ps
CPU time 0.97 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:10 PM PDT 24
Peak memory 207524 kb
Host smart-c44cd768-0b49-4bab-a7d3-83aa02494a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
57472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3458257472
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2082224238
Short name T3328
Test name
Test status
Simulation time 150916803 ps
CPU time 0.86 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207524 kb
Host smart-a784f4f1-c781-4f35-94bc-c61d5d8ebaf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
24238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2082224238
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3564532029
Short name T869
Test name
Test status
Simulation time 197647187 ps
CPU time 0.92 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207524 kb
Host smart-03de6a2f-d661-4473-95c8-f35838886e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35645
32029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3564532029
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3768742274
Short name T833
Test name
Test status
Simulation time 186348923 ps
CPU time 0.9 seconds
Started Aug 13 06:40:21 PM PDT 24
Finished Aug 13 06:40:22 PM PDT 24
Peak memory 207608 kb
Host smart-555b2279-a60c-49fe-97ab-caa78c37c4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37687
42274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3768742274
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2395678600
Short name T1472
Test name
Test status
Simulation time 155091883 ps
CPU time 0.83 seconds
Started Aug 13 06:40:23 PM PDT 24
Finished Aug 13 06:40:24 PM PDT 24
Peak memory 207600 kb
Host smart-78c2ff89-57d4-4bc3-99bd-847ddcf4f8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23956
78600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2395678600
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3452165754
Short name T2692
Test name
Test status
Simulation time 205611806 ps
CPU time 0.95 seconds
Started Aug 13 06:40:13 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207604 kb
Host smart-9441d87d-3ad4-4957-97fe-2dcb5247d494
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3452165754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3452165754
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3390802258
Short name T753
Test name
Test status
Simulation time 137031019 ps
CPU time 0.84 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207356 kb
Host smart-1469aa3a-165a-4213-a819-2aaac331569b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33908
02258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3390802258
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.814453658
Short name T3627
Test name
Test status
Simulation time 83958377 ps
CPU time 0.76 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207540 kb
Host smart-7135eb3c-5a99-485e-bd85-bb63577b6cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81445
3658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.814453658
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2234927114
Short name T2983
Test name
Test status
Simulation time 15559536925 ps
CPU time 40.11 seconds
Started Aug 13 06:40:13 PM PDT 24
Finished Aug 13 06:40:53 PM PDT 24
Peak memory 224220 kb
Host smart-e2a1e848-5bf8-4178-9597-21d252a2d85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22349
27114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2234927114
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.105972891
Short name T1267
Test name
Test status
Simulation time 156234032 ps
CPU time 0.83 seconds
Started Aug 13 06:40:21 PM PDT 24
Finished Aug 13 06:40:22 PM PDT 24
Peak memory 207604 kb
Host smart-6a1ebf3e-bcb1-4ea0-a923-bb8be21fa7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10597
2891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.105972891
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.965755232
Short name T2889
Test name
Test status
Simulation time 205155311 ps
CPU time 0.96 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:10 PM PDT 24
Peak memory 207468 kb
Host smart-be366fc3-6fc5-4aee-a8f7-4b280cb6bcbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96575
5232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.965755232
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1994136661
Short name T697
Test name
Test status
Simulation time 262307263 ps
CPU time 1.03 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207508 kb
Host smart-6fdb18e2-c362-4150-b83d-3d79a269d7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19941
36661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1994136661
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.2452734024
Short name T1526
Test name
Test status
Simulation time 185864169 ps
CPU time 0.88 seconds
Started Aug 13 06:40:13 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207544 kb
Host smart-5407e935-3fef-474a-8346-81b8900d3022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24527
34024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.2452734024
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.257120640
Short name T3236
Test name
Test status
Simulation time 151401393 ps
CPU time 0.81 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:12 PM PDT 24
Peak memory 207496 kb
Host smart-a7e9046b-caf9-4f73-8550-2082108cea9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25712
0640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.257120640
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_rx_full.304699113
Short name T1131
Test name
Test status
Simulation time 263239493 ps
CPU time 1.12 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:12 PM PDT 24
Peak memory 207440 kb
Host smart-03c244d6-2875-4390-80ae-7c23663acf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30469
9113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.304699113
Directory /workspace/44.usbdev_rx_full/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.685342178
Short name T2048
Test name
Test status
Simulation time 158731602 ps
CPU time 0.86 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:12 PM PDT 24
Peak memory 207460 kb
Host smart-276c0fc3-873a-46db-b20f-bec642d26923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68534
2178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.685342178
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3975024379
Short name T2544
Test name
Test status
Simulation time 208330501 ps
CPU time 0.92 seconds
Started Aug 13 06:40:07 PM PDT 24
Finished Aug 13 06:40:08 PM PDT 24
Peak memory 207532 kb
Host smart-271896c6-aec5-4332-874e-6f19e0d88a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39750
24379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3975024379
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1840018097
Short name T2610
Test name
Test status
Simulation time 229879933 ps
CPU time 1.06 seconds
Started Aug 13 06:40:19 PM PDT 24
Finished Aug 13 06:40:21 PM PDT 24
Peak memory 207492 kb
Host smart-e96ebc57-b789-4117-9851-e53e256728a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18400
18097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1840018097
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2832555416
Short name T2590
Test name
Test status
Simulation time 3177675628 ps
CPU time 93.74 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:41:46 PM PDT 24
Peak memory 217596 kb
Host smart-97b96e46-b4ad-426d-9e89-2f91a82fffec
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2832555416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2832555416
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2224123755
Short name T1116
Test name
Test status
Simulation time 183294419 ps
CPU time 0.94 seconds
Started Aug 13 06:40:16 PM PDT 24
Finished Aug 13 06:40:17 PM PDT 24
Peak memory 207440 kb
Host smart-0cd77275-9ab3-4f21-9035-2436f0ca63f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22241
23755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2224123755
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1982162104
Short name T1685
Test name
Test status
Simulation time 203449316 ps
CPU time 0.93 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207552 kb
Host smart-cf17b3c5-04d2-4507-8303-7e1138ff7803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19821
62104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1982162104
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.3421186131
Short name T2973
Test name
Test status
Simulation time 619796194 ps
CPU time 1.72 seconds
Started Aug 13 06:40:19 PM PDT 24
Finished Aug 13 06:40:21 PM PDT 24
Peak memory 207512 kb
Host smart-24953b8f-3e6e-4c76-83d8-2b6dbaeea34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34211
86131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.3421186131
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.4260339211
Short name T1355
Test name
Test status
Simulation time 3175782098 ps
CPU time 23.4 seconds
Started Aug 13 06:40:13 PM PDT 24
Finished Aug 13 06:40:47 PM PDT 24
Peak memory 216268 kb
Host smart-70782ec0-c5f8-4d9b-a857-817768a13265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42603
39211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.4260339211
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.164009385
Short name T1484
Test name
Test status
Simulation time 785230123 ps
CPU time 5.16 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207588 kb
Host smart-06063115-c711-401e-81a2-35f29bbc93a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164009385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_host
_handshake.164009385
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_tx_rx_disruption.3498773526
Short name T3561
Test name
Test status
Simulation time 466354296 ps
CPU time 1.56 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207500 kb
Host smart-edeaa311-2e82-434d-ba17-09a4092a652a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498773526 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.usbdev_tx_rx_disruption.3498773526
Directory /workspace/44.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/440.usbdev_tx_rx_disruption.3809335963
Short name T265
Test name
Test status
Simulation time 619475611 ps
CPU time 1.76 seconds
Started Aug 13 06:42:18 PM PDT 24
Finished Aug 13 06:42:20 PM PDT 24
Peak memory 207572 kb
Host smart-b1186a5c-6fb5-4702-b39a-2b1ba43f682a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809335963 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 440.usbdev_tx_rx_disruption.3809335963
Directory /workspace/440.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/441.usbdev_tx_rx_disruption.1664337768
Short name T1307
Test name
Test status
Simulation time 572633990 ps
CPU time 1.68 seconds
Started Aug 13 06:42:29 PM PDT 24
Finished Aug 13 06:42:31 PM PDT 24
Peak memory 207592 kb
Host smart-0545dbe0-96b9-474c-b38f-9bedab2bb6ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664337768 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 441.usbdev_tx_rx_disruption.1664337768
Directory /workspace/441.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/442.usbdev_tx_rx_disruption.159722251
Short name T3228
Test name
Test status
Simulation time 469109866 ps
CPU time 1.44 seconds
Started Aug 13 06:42:35 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 207520 kb
Host smart-0dba1b3c-1bf7-4997-a297-e48ebd8ada26
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159722251 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 442.usbdev_tx_rx_disruption.159722251
Directory /workspace/442.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/443.usbdev_tx_rx_disruption.660178347
Short name T196
Test name
Test status
Simulation time 631795487 ps
CPU time 1.84 seconds
Started Aug 13 06:42:37 PM PDT 24
Finished Aug 13 06:42:38 PM PDT 24
Peak memory 207616 kb
Host smart-f661e263-e21d-419c-8b56-4a97827fc6c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660178347 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 443.usbdev_tx_rx_disruption.660178347
Directory /workspace/443.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/444.usbdev_tx_rx_disruption.3891132303
Short name T2653
Test name
Test status
Simulation time 487604584 ps
CPU time 1.6 seconds
Started Aug 13 06:42:14 PM PDT 24
Finished Aug 13 06:42:21 PM PDT 24
Peak memory 207592 kb
Host smart-21f4fd0e-f407-4623-8f28-8d34d848400f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891132303 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 444.usbdev_tx_rx_disruption.3891132303
Directory /workspace/444.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/445.usbdev_tx_rx_disruption.778088232
Short name T1350
Test name
Test status
Simulation time 530428294 ps
CPU time 1.62 seconds
Started Aug 13 06:42:09 PM PDT 24
Finished Aug 13 06:42:11 PM PDT 24
Peak memory 207544 kb
Host smart-12d262ca-6a3e-4b3d-a287-75f4f9737307
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778088232 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 445.usbdev_tx_rx_disruption.778088232
Directory /workspace/445.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/446.usbdev_tx_rx_disruption.452956596
Short name T1781
Test name
Test status
Simulation time 503816110 ps
CPU time 1.59 seconds
Started Aug 13 06:42:21 PM PDT 24
Finished Aug 13 06:42:23 PM PDT 24
Peak memory 207544 kb
Host smart-57e7bc24-f0ea-432d-92c3-b9dcf110e152
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452956596 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 446.usbdev_tx_rx_disruption.452956596
Directory /workspace/446.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/447.usbdev_tx_rx_disruption.765583162
Short name T1179
Test name
Test status
Simulation time 531501278 ps
CPU time 1.68 seconds
Started Aug 13 06:42:13 PM PDT 24
Finished Aug 13 06:42:15 PM PDT 24
Peak memory 207592 kb
Host smart-4a60c536-67c6-4f53-8a6e-a3176e46cf09
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765583162 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 447.usbdev_tx_rx_disruption.765583162
Directory /workspace/447.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/448.usbdev_tx_rx_disruption.206505324
Short name T1571
Test name
Test status
Simulation time 590329980 ps
CPU time 1.75 seconds
Started Aug 13 06:42:18 PM PDT 24
Finished Aug 13 06:42:19 PM PDT 24
Peak memory 207612 kb
Host smart-05fe76c9-c144-458f-a693-507c35fefe25
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206505324 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 448.usbdev_tx_rx_disruption.206505324
Directory /workspace/448.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/449.usbdev_tx_rx_disruption.1813913365
Short name T1308
Test name
Test status
Simulation time 458193565 ps
CPU time 1.37 seconds
Started Aug 13 06:42:28 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 207624 kb
Host smart-55e314ed-3fae-4335-b9a3-a362a3c372f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813913365 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 449.usbdev_tx_rx_disruption.1813913365
Directory /workspace/449.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.1385562922
Short name T2461
Test name
Test status
Simulation time 51728421 ps
CPU time 0.7 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207480 kb
Host smart-530f06a4-6815-4c83-92a4-25bef0ea0a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1385562922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.1385562922
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2406420419
Short name T3174
Test name
Test status
Simulation time 9390739676 ps
CPU time 12.23 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:25 PM PDT 24
Peak memory 207884 kb
Host smart-a44ee10b-7615-44ce-8272-7594225496ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406420419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.2406420419
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2428873739
Short name T2635
Test name
Test status
Simulation time 13761568211 ps
CPU time 16.42 seconds
Started Aug 13 06:40:13 PM PDT 24
Finished Aug 13 06:40:30 PM PDT 24
Peak memory 215952 kb
Host smart-9fef78a2-e393-430c-8fba-c5a99eb4ab20
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428873739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2428873739
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1506684030
Short name T2115
Test name
Test status
Simulation time 30382466337 ps
CPU time 38.79 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:45 PM PDT 24
Peak memory 207860 kb
Host smart-fbd121dd-8bc1-4023-b7e6-04ada93f9bdb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506684030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.1506684030
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1692050532
Short name T1885
Test name
Test status
Simulation time 151453238 ps
CPU time 0.92 seconds
Started Aug 13 06:40:14 PM PDT 24
Finished Aug 13 06:40:15 PM PDT 24
Peak memory 207492 kb
Host smart-dbb5e4e1-36fb-4a6e-937c-f718571bfee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16920
50532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1692050532
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.4084719062
Short name T2708
Test name
Test status
Simulation time 186741537 ps
CPU time 0.85 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:10 PM PDT 24
Peak memory 207552 kb
Host smart-cf868448-097a-4368-86f4-64b76c8ff64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40847
19062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.4084719062
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.4025285100
Short name T2401
Test name
Test status
Simulation time 390965812 ps
CPU time 1.35 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207616 kb
Host smart-bb81bdb0-c54c-4868-a1b4-b2ca0db37c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40252
85100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.4025285100
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1554662401
Short name T3496
Test name
Test status
Simulation time 266424775 ps
CPU time 1.02 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207444 kb
Host smart-15a6f2b0-6e4d-46b6-8b4b-b9ecd3807ea7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1554662401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1554662401
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.2583216274
Short name T527
Test name
Test status
Simulation time 38739292780 ps
CPU time 57.46 seconds
Started Aug 13 06:40:17 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207804 kb
Host smart-6a34eafe-52d6-4dfb-ab8a-da376033659f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25832
16274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2583216274
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.4053527598
Short name T1264
Test name
Test status
Simulation time 994089620 ps
CPU time 21.18 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:27 PM PDT 24
Peak memory 207828 kb
Host smart-ade964d3-ace4-43d4-abcb-9b04312e827e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053527598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.4053527598
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3411799734
Short name T2172
Test name
Test status
Simulation time 643934287 ps
CPU time 1.8 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:10 PM PDT 24
Peak memory 207480 kb
Host smart-ca044e46-c5f2-4792-91f6-4b3ae25f6b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34117
99734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3411799734
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.713789202
Short name T875
Test name
Test status
Simulation time 192571686 ps
CPU time 0.9 seconds
Started Aug 13 06:40:13 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207524 kb
Host smart-54d9ebef-2329-426f-b721-89f5cb4b4bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71378
9202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.713789202
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.788029042
Short name T1716
Test name
Test status
Simulation time 40708046 ps
CPU time 0.69 seconds
Started Aug 13 06:40:14 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207424 kb
Host smart-e41d0331-981c-4d15-a5da-fdb539752774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78802
9042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.788029042
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3068438002
Short name T3333
Test name
Test status
Simulation time 910059141 ps
CPU time 2.42 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 207792 kb
Host smart-20dc7b01-cb62-444f-9ea3-2e47486633ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30684
38002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3068438002
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3854446613
Short name T619
Test name
Test status
Simulation time 272050288 ps
CPU time 2.01 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207616 kb
Host smart-50e16207-08f1-4c73-8726-e38077bf6b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544
46613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3854446613
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3743810583
Short name T3356
Test name
Test status
Simulation time 236025098 ps
CPU time 1.2 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 215912 kb
Host smart-8d12a4cb-bc5c-4484-a413-e87ac68d9a48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3743810583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3743810583
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2693972830
Short name T2495
Test name
Test status
Simulation time 212253359 ps
CPU time 0.84 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:09 PM PDT 24
Peak memory 207476 kb
Host smart-e240c877-c987-485e-ac5b-ed7329bcba33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26939
72830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2693972830
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2410268934
Short name T1500
Test name
Test status
Simulation time 202314256 ps
CPU time 0.96 seconds
Started Aug 13 06:40:17 PM PDT 24
Finished Aug 13 06:40:18 PM PDT 24
Peak memory 207540 kb
Host smart-c38b56bd-c7d5-4415-ac3a-2f4612b47cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24102
68934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2410268934
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2136106624
Short name T2911
Test name
Test status
Simulation time 3742768070 ps
CPU time 28.76 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:41 PM PDT 24
Peak memory 218452 kb
Host smart-36d92a2e-5e21-4dfc-b879-df0f8149c0a0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2136106624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2136106624
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.2796718790
Short name T1816
Test name
Test status
Simulation time 12024666591 ps
CPU time 85.82 seconds
Started Aug 13 06:40:13 PM PDT 24
Finished Aug 13 06:41:39 PM PDT 24
Peak memory 207820 kb
Host smart-15b21420-03df-4b28-91a8-740a6d8226fc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2796718790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.2796718790
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2571364226
Short name T50
Test name
Test status
Simulation time 223153642 ps
CPU time 0.99 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207468 kb
Host smart-b1426166-5cde-4bf4-87d2-15f5cc61e033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25713
64226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2571364226
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.526433138
Short name T2084
Test name
Test status
Simulation time 12107549817 ps
CPU time 19.55 seconds
Started Aug 13 06:40:15 PM PDT 24
Finished Aug 13 06:40:34 PM PDT 24
Peak memory 207736 kb
Host smart-86a5f35a-64df-46df-9b10-2fc900ede287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52643
3138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.526433138
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2948054271
Short name T1409
Test name
Test status
Simulation time 8539097594 ps
CPU time 10.93 seconds
Started Aug 13 06:40:16 PM PDT 24
Finished Aug 13 06:40:27 PM PDT 24
Peak memory 207784 kb
Host smart-6281b44e-28cd-4acd-8e78-9146d470d9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29480
54271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2948054271
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.3677134694
Short name T1414
Test name
Test status
Simulation time 3354133735 ps
CPU time 92.4 seconds
Started Aug 13 06:40:05 PM PDT 24
Finished Aug 13 06:41:38 PM PDT 24
Peak memory 216020 kb
Host smart-3af265c0-ff16-4438-bedd-13200c687fe4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3677134694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.3677134694
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.102875098
Short name T1165
Test name
Test status
Simulation time 2822230406 ps
CPU time 22.62 seconds
Started Aug 13 06:40:18 PM PDT 24
Finished Aug 13 06:40:40 PM PDT 24
Peak memory 215956 kb
Host smart-ae1b22ce-99d8-4eba-91c1-ddc33ae3a7ab
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=102875098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.102875098
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.2143612444
Short name T1715
Test name
Test status
Simulation time 236881693 ps
CPU time 0.99 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207480 kb
Host smart-f74ee1f4-9ad3-4086-a45a-9cce31ecab02
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2143612444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.2143612444
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.211479834
Short name T1245
Test name
Test status
Simulation time 191138607 ps
CPU time 0.97 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207452 kb
Host smart-5641ac9d-03e0-43c9-aaaf-9231c09f9fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21147
9834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.211479834
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.131410361
Short name T170
Test name
Test status
Simulation time 3041029187 ps
CPU time 90.75 seconds
Started Aug 13 06:40:20 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 217444 kb
Host smart-30cb503d-b285-4e2b-8211-724bd099a130
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=131410361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.131410361
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3691992619
Short name T2384
Test name
Test status
Simulation time 149640675 ps
CPU time 0.85 seconds
Started Aug 13 06:40:14 PM PDT 24
Finished Aug 13 06:40:15 PM PDT 24
Peak memory 207552 kb
Host smart-bd1efff0-ce03-4790-9329-de9e8261948a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3691992619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3691992619
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1040321863
Short name T1443
Test name
Test status
Simulation time 170912679 ps
CPU time 0.89 seconds
Started Aug 13 06:40:24 PM PDT 24
Finished Aug 13 06:40:30 PM PDT 24
Peak memory 207528 kb
Host smart-7aeebdd7-2ff1-41e7-81fc-a6e76490c14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10403
21863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1040321863
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1309410205
Short name T135
Test name
Test status
Simulation time 199491683 ps
CPU time 0.95 seconds
Started Aug 13 06:40:16 PM PDT 24
Finished Aug 13 06:40:17 PM PDT 24
Peak memory 207500 kb
Host smart-f4f8340b-c90e-47c1-ba95-5262dd6c6584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13094
10205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1309410205
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2977050582
Short name T1177
Test name
Test status
Simulation time 159437296 ps
CPU time 0.86 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207504 kb
Host smart-81383a50-4779-4ae1-85db-6fdf7b0e5bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29770
50582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2977050582
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1821275504
Short name T219
Test name
Test status
Simulation time 164537751 ps
CPU time 0.87 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207416 kb
Host smart-680410b3-331c-452e-8c55-a8e37ce20086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18212
75504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1821275504
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2937968545
Short name T690
Test name
Test status
Simulation time 142348170 ps
CPU time 0.84 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:40:40 PM PDT 24
Peak memory 207600 kb
Host smart-f561668f-ae1c-48ea-ac98-b5d3d8d00d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29379
68545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2937968545
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2181381439
Short name T1198
Test name
Test status
Simulation time 173834282 ps
CPU time 0.85 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207588 kb
Host smart-ab4f1a73-6288-4d10-baa8-4bc00b900347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21813
81439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2181381439
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3010258514
Short name T2617
Test name
Test status
Simulation time 225281896 ps
CPU time 1.02 seconds
Started Aug 13 06:40:15 PM PDT 24
Finished Aug 13 06:40:16 PM PDT 24
Peak memory 207556 kb
Host smart-5432708b-5ea0-446a-8e45-01f9dfa40af2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3010258514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3010258514
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.125046419
Short name T1900
Test name
Test status
Simulation time 151858789 ps
CPU time 0.86 seconds
Started Aug 13 06:40:26 PM PDT 24
Finished Aug 13 06:40:27 PM PDT 24
Peak memory 207500 kb
Host smart-8d277db9-939b-437a-9999-74aebaa80b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12504
6419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.125046419
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2858208253
Short name T2525
Test name
Test status
Simulation time 68618812 ps
CPU time 0.73 seconds
Started Aug 13 06:40:45 PM PDT 24
Finished Aug 13 06:40:45 PM PDT 24
Peak memory 207564 kb
Host smart-fd4c8bc1-5ec6-4410-80dc-7df7a9d1de5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28582
08253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2858208253
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3526007889
Short name T1960
Test name
Test status
Simulation time 11025883914 ps
CPU time 26.97 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:38 PM PDT 24
Peak memory 215992 kb
Host smart-3963a333-51c0-4281-9dd4-72ed91e05aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35260
07889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3526007889
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3972511454
Short name T2176
Test name
Test status
Simulation time 177241807 ps
CPU time 0.87 seconds
Started Aug 13 06:40:20 PM PDT 24
Finished Aug 13 06:40:21 PM PDT 24
Peak memory 207608 kb
Host smart-f97c3861-996e-43e7-a916-0e3f461adffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
11454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3972511454
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.4015395928
Short name T2087
Test name
Test status
Simulation time 216744271 ps
CPU time 1.03 seconds
Started Aug 13 06:40:17 PM PDT 24
Finished Aug 13 06:40:18 PM PDT 24
Peak memory 207540 kb
Host smart-e7718558-4953-4c70-a429-a1e1eb10fe9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40153
95928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.4015395928
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.2183702193
Short name T668
Test name
Test status
Simulation time 207613025 ps
CPU time 0.93 seconds
Started Aug 13 06:40:22 PM PDT 24
Finished Aug 13 06:40:23 PM PDT 24
Peak memory 207536 kb
Host smart-ab08997a-cfd0-4659-9bd9-7fee3619f1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837
02193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2183702193
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.1447030671
Short name T1248
Test name
Test status
Simulation time 215841973 ps
CPU time 1.02 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207544 kb
Host smart-92cf906f-55a7-42cf-a9af-036a2d414097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14470
30671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.1447030671
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.3282225080
Short name T1553
Test name
Test status
Simulation time 180568358 ps
CPU time 0.88 seconds
Started Aug 13 06:40:17 PM PDT 24
Finished Aug 13 06:40:18 PM PDT 24
Peak memory 207488 kb
Host smart-7516db58-872f-4d2c-b351-6faad502a0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32822
25080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.3282225080
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_rx_full.2442226701
Short name T3029
Test name
Test status
Simulation time 259168415 ps
CPU time 1.11 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207528 kb
Host smart-6c7c2da2-f79d-4841-a7db-f07fcda9a359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24422
26701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.2442226701
Directory /workspace/45.usbdev_rx_full/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1337307139
Short name T3381
Test name
Test status
Simulation time 155478227 ps
CPU time 0.83 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207532 kb
Host smart-a7d8749b-1d02-4889-bb87-f7595f9ac80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13373
07139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1337307139
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3737549328
Short name T2798
Test name
Test status
Simulation time 167828708 ps
CPU time 0.85 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:12 PM PDT 24
Peak memory 207540 kb
Host smart-47dcb222-ff06-48c2-aadc-1cbd1041fe72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37375
49328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3737549328
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.4106485818
Short name T1402
Test name
Test status
Simulation time 239995051 ps
CPU time 1.03 seconds
Started Aug 13 06:40:32 PM PDT 24
Finished Aug 13 06:40:33 PM PDT 24
Peak memory 207520 kb
Host smart-dec2f006-74e0-46a1-85b4-a3476ab7e75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41064
85818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.4106485818
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3443742003
Short name T2552
Test name
Test status
Simulation time 3076723833 ps
CPU time 31.05 seconds
Started Aug 13 06:40:12 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 224132 kb
Host smart-b683be67-c507-4ad7-9163-d4f64d6ad1b4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3443742003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3443742003
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3147169174
Short name T1836
Test name
Test status
Simulation time 146276886 ps
CPU time 0.92 seconds
Started Aug 13 06:40:49 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 207488 kb
Host smart-f3048d6a-f65c-4518-b05a-9d3500557a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31471
69174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3147169174
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1587603059
Short name T1840
Test name
Test status
Simulation time 181049461 ps
CPU time 0.87 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:13 PM PDT 24
Peak memory 207500 kb
Host smart-2332ae1d-c4f3-4af8-8db6-bd29711c15bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15876
03059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1587603059
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.3064392777
Short name T3143
Test name
Test status
Simulation time 599803196 ps
CPU time 1.89 seconds
Started Aug 13 06:40:08 PM PDT 24
Finished Aug 13 06:40:10 PM PDT 24
Peak memory 207552 kb
Host smart-211253c9-c954-47f2-b2f8-501955d08b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30643
92777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.3064392777
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1949244640
Short name T1826
Test name
Test status
Simulation time 2548267000 ps
CPU time 19.03 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:31 PM PDT 24
Peak memory 217792 kb
Host smart-50a15dfa-b7f8-4455-952d-ddf691327d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19492
44640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1949244640
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.166145432
Short name T1642
Test name
Test status
Simulation time 174537827 ps
CPU time 0.91 seconds
Started Aug 13 06:40:06 PM PDT 24
Finished Aug 13 06:40:07 PM PDT 24
Peak memory 207480 kb
Host smart-3f65d0ea-5d14-4a08-9cdc-2d171757a45b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166145432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_host
_handshake.166145432
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_tx_rx_disruption.2012526370
Short name T1473
Test name
Test status
Simulation time 530364466 ps
CPU time 1.61 seconds
Started Aug 13 06:40:10 PM PDT 24
Finished Aug 13 06:40:12 PM PDT 24
Peak memory 207632 kb
Host smart-6181b6f6-e3ed-4aa4-8315-8ac3a04bc1c4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012526370 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.usbdev_tx_rx_disruption.2012526370
Directory /workspace/45.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/450.usbdev_tx_rx_disruption.1302887980
Short name T1817
Test name
Test status
Simulation time 551141478 ps
CPU time 1.81 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 207592 kb
Host smart-99a69927-ad92-4d8f-a857-5f28207c88ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302887980 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 450.usbdev_tx_rx_disruption.1302887980
Directory /workspace/450.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/451.usbdev_tx_rx_disruption.36192692
Short name T2381
Test name
Test status
Simulation time 567007066 ps
CPU time 1.72 seconds
Started Aug 13 06:42:32 PM PDT 24
Finished Aug 13 06:42:34 PM PDT 24
Peak memory 207620 kb
Host smart-f528b73a-f026-4d6c-9a1c-e44b96ac5e21
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36192692 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 451.usbdev_tx_rx_disruption.36192692
Directory /workspace/451.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/452.usbdev_tx_rx_disruption.2775231679
Short name T2551
Test name
Test status
Simulation time 574428505 ps
CPU time 1.7 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207608 kb
Host smart-3194d126-e6ac-4928-bddb-4386ed508016
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775231679 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 452.usbdev_tx_rx_disruption.2775231679
Directory /workspace/452.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/453.usbdev_tx_rx_disruption.214716478
Short name T2543
Test name
Test status
Simulation time 533140026 ps
CPU time 1.58 seconds
Started Aug 13 06:42:29 PM PDT 24
Finished Aug 13 06:42:30 PM PDT 24
Peak memory 207632 kb
Host smart-d89fd178-583d-45c7-95d2-2e308467f2a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214716478 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 453.usbdev_tx_rx_disruption.214716478
Directory /workspace/453.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/454.usbdev_tx_rx_disruption.3107046386
Short name T3355
Test name
Test status
Simulation time 476421273 ps
CPU time 1.47 seconds
Started Aug 13 06:42:13 PM PDT 24
Finished Aug 13 06:42:14 PM PDT 24
Peak memory 207496 kb
Host smart-4f81b74d-b8fb-4aca-90de-15c794a5216a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107046386 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 454.usbdev_tx_rx_disruption.3107046386
Directory /workspace/454.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/455.usbdev_tx_rx_disruption.3799195983
Short name T1537
Test name
Test status
Simulation time 415508048 ps
CPU time 1.41 seconds
Started Aug 13 06:42:25 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 207592 kb
Host smart-ee5ea33f-8301-4589-b0b0-bd2c2bdbb6e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799195983 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 455.usbdev_tx_rx_disruption.3799195983
Directory /workspace/455.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/456.usbdev_tx_rx_disruption.1641251442
Short name T2919
Test name
Test status
Simulation time 611674833 ps
CPU time 1.64 seconds
Started Aug 13 06:42:31 PM PDT 24
Finished Aug 13 06:42:32 PM PDT 24
Peak memory 207612 kb
Host smart-2c3b733c-ed2e-422f-8ea4-b0113fe72dfe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641251442 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 456.usbdev_tx_rx_disruption.1641251442
Directory /workspace/456.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/457.usbdev_tx_rx_disruption.703850187
Short name T2691
Test name
Test status
Simulation time 610352806 ps
CPU time 1.69 seconds
Started Aug 13 06:42:17 PM PDT 24
Finished Aug 13 06:42:19 PM PDT 24
Peak memory 207612 kb
Host smart-8c17df05-89e8-4536-9a5f-3a90b7b8f4f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703850187 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 457.usbdev_tx_rx_disruption.703850187
Directory /workspace/457.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/458.usbdev_tx_rx_disruption.453124928
Short name T2978
Test name
Test status
Simulation time 488991499 ps
CPU time 1.55 seconds
Started Aug 13 06:42:21 PM PDT 24
Finished Aug 13 06:42:22 PM PDT 24
Peak memory 207624 kb
Host smart-219a3bb1-cea8-4042-9964-797df75b347c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453124928 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 458.usbdev_tx_rx_disruption.453124928
Directory /workspace/458.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/459.usbdev_tx_rx_disruption.1780269908
Short name T1495
Test name
Test status
Simulation time 488287830 ps
CPU time 1.65 seconds
Started Aug 13 06:42:42 PM PDT 24
Finished Aug 13 06:42:44 PM PDT 24
Peak memory 207572 kb
Host smart-99b7c5fd-fe3d-4b86-b02f-d915752d42d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780269908 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 459.usbdev_tx_rx_disruption.1780269908
Directory /workspace/459.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1057919569
Short name T651
Test name
Test status
Simulation time 30846320 ps
CPU time 0.64 seconds
Started Aug 13 06:40:35 PM PDT 24
Finished Aug 13 06:40:36 PM PDT 24
Peak memory 207460 kb
Host smart-1a673af2-62f5-4a87-ac8f-a56f819528d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1057919569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1057919569
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3177648122
Short name T1051
Test name
Test status
Simulation time 11495212042 ps
CPU time 14.96 seconds
Started Aug 13 06:40:11 PM PDT 24
Finished Aug 13 06:40:26 PM PDT 24
Peak memory 207796 kb
Host smart-ad35c43b-da2b-43cb-8678-4f3afc945f6e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177648122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.3177648122
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.239789639
Short name T3112
Test name
Test status
Simulation time 19867332934 ps
CPU time 21.8 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:31 PM PDT 24
Peak memory 207824 kb
Host smart-46cb5a0b-9e8f-4650-957a-4b28dba126e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=239789639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.239789639
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2238202100
Short name T3397
Test name
Test status
Simulation time 23564858238 ps
CPU time 31.33 seconds
Started Aug 13 06:40:19 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 216040 kb
Host smart-8cfbe512-97d4-4f03-8c2c-57671f1e2105
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238202100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.2238202100
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2518783102
Short name T772
Test name
Test status
Simulation time 178274371 ps
CPU time 0.92 seconds
Started Aug 13 06:40:09 PM PDT 24
Finished Aug 13 06:40:11 PM PDT 24
Peak memory 207492 kb
Host smart-8d115db3-d541-4939-89ba-c3109a9b2c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25187
83102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2518783102
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.980365830
Short name T3206
Test name
Test status
Simulation time 150402014 ps
CPU time 0.8 seconds
Started Aug 13 06:40:19 PM PDT 24
Finished Aug 13 06:40:20 PM PDT 24
Peak memory 207568 kb
Host smart-af5cb579-b6ad-4aa4-9ae2-be41b4d896dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98036
5830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.980365830
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.1339249274
Short name T2311
Test name
Test status
Simulation time 534379274 ps
CPU time 1.71 seconds
Started Aug 13 06:40:31 PM PDT 24
Finished Aug 13 06:40:33 PM PDT 24
Peak memory 207564 kb
Host smart-990fd2ee-a073-4db3-911a-f8acde3e6622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13392
49274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1339249274
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.995400963
Short name T2317
Test name
Test status
Simulation time 736631978 ps
CPU time 1.97 seconds
Started Aug 13 06:40:13 PM PDT 24
Finished Aug 13 06:40:15 PM PDT 24
Peak memory 207560 kb
Host smart-eb19ad69-3f8b-4595-b431-f783f971ae14
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=995400963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.995400963
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2998059056
Short name T1183
Test name
Test status
Simulation time 14451818026 ps
CPU time 24.6 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207800 kb
Host smart-28bc64d7-9290-41b1-868b-2a6dc5aa3017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29980
59056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2998059056
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.436614908
Short name T2812
Test name
Test status
Simulation time 2558416788 ps
CPU time 18.26 seconds
Started Aug 13 06:40:33 PM PDT 24
Finished Aug 13 06:40:52 PM PDT 24
Peak memory 207800 kb
Host smart-f5fdbdc1-67e6-45fa-8971-3586c62f3f4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436614908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.436614908
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3202105
Short name T2616
Test name
Test status
Simulation time 861794310 ps
CPU time 1.98 seconds
Started Aug 13 06:40:35 PM PDT 24
Finished Aug 13 06:40:37 PM PDT 24
Peak memory 207552 kb
Host smart-491ca69e-79e6-44eb-b7e0-0725649ae667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32021
05 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3202105
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3596972109
Short name T2942
Test name
Test status
Simulation time 134788341 ps
CPU time 0.87 seconds
Started Aug 13 06:40:38 PM PDT 24
Finished Aug 13 06:40:39 PM PDT 24
Peak memory 207436 kb
Host smart-867ec1b2-7c19-41d7-a409-990451aca225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35969
72109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3596972109
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2530668591
Short name T3487
Test name
Test status
Simulation time 100483947 ps
CPU time 0.76 seconds
Started Aug 13 06:40:36 PM PDT 24
Finished Aug 13 06:40:37 PM PDT 24
Peak memory 207480 kb
Host smart-6c2b9259-748d-4f7e-9231-ea96e57d3191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25306
68591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2530668591
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.441866162
Short name T1265
Test name
Test status
Simulation time 779409346 ps
CPU time 2.06 seconds
Started Aug 13 06:40:22 PM PDT 24
Finished Aug 13 06:40:24 PM PDT 24
Peak memory 207700 kb
Host smart-c3569c48-37ce-454e-aaf6-87adea277b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44186
6162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.441866162
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2089020106
Short name T3068
Test name
Test status
Simulation time 294827248 ps
CPU time 2.1 seconds
Started Aug 13 06:40:33 PM PDT 24
Finished Aug 13 06:40:35 PM PDT 24
Peak memory 207552 kb
Host smart-85cf3a6e-79da-43b4-9a25-35e8236f785a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20890
20106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2089020106
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.570249841
Short name T2695
Test name
Test status
Simulation time 199343601 ps
CPU time 1.11 seconds
Started Aug 13 06:40:29 PM PDT 24
Finished Aug 13 06:40:30 PM PDT 24
Peak memory 215892 kb
Host smart-a4de03c3-144d-4b77-95c0-d6ccc33631c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=570249841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.570249841
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3198300909
Short name T2763
Test name
Test status
Simulation time 190044772 ps
CPU time 0.89 seconds
Started Aug 13 06:40:43 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 207404 kb
Host smart-ecdeb2aa-214e-45f9-88ef-cae38cb97806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31983
00909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3198300909
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.909607500
Short name T2828
Test name
Test status
Simulation time 218713263 ps
CPU time 1.01 seconds
Started Aug 13 06:40:21 PM PDT 24
Finished Aug 13 06:40:22 PM PDT 24
Peak memory 207452 kb
Host smart-c9f6bbe2-963e-48c2-9469-2168ac6de2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90960
7500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.909607500
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3154905914
Short name T2091
Test name
Test status
Simulation time 3124734611 ps
CPU time 24.25 seconds
Started Aug 13 06:40:35 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 218180 kb
Host smart-8e73b797-2ba7-4ba7-aea8-12d93baf9469
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3154905914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3154905914
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.1027066266
Short name T3049
Test name
Test status
Simulation time 5042193790 ps
CPU time 35.98 seconds
Started Aug 13 06:40:29 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207832 kb
Host smart-d2f49163-24ec-423a-bec0-d2849e6c0018
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1027066266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1027066266
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2927765297
Short name T2794
Test name
Test status
Simulation time 249540261 ps
CPU time 1.07 seconds
Started Aug 13 06:40:47 PM PDT 24
Finished Aug 13 06:40:48 PM PDT 24
Peak memory 207536 kb
Host smart-dc8b9d71-aa65-42ce-9d9c-327addb0edda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29277
65297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2927765297
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.4117001170
Short name T755
Test name
Test status
Simulation time 7170253659 ps
CPU time 11.37 seconds
Started Aug 13 06:40:29 PM PDT 24
Finished Aug 13 06:40:46 PM PDT 24
Peak memory 207832 kb
Host smart-2dae961e-7205-432b-a765-a206369e00b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41170
01170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.4117001170
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1334580465
Short name T1486
Test name
Test status
Simulation time 10329955485 ps
CPU time 13.62 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:40:53 PM PDT 24
Peak memory 207824 kb
Host smart-ebc0f552-49b6-4580-8d8c-47af7ae2ccae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13345
80465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1334580465
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1423504246
Short name T1569
Test name
Test status
Simulation time 4335939571 ps
CPU time 126.53 seconds
Started Aug 13 06:40:25 PM PDT 24
Finished Aug 13 06:42:32 PM PDT 24
Peak memory 218476 kb
Host smart-bb14b7c7-c0fc-448c-ab91-db0d18db25bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1423504246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1423504246
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2820518956
Short name T642
Test name
Test status
Simulation time 2416548713 ps
CPU time 64.82 seconds
Started Aug 13 06:40:33 PM PDT 24
Finished Aug 13 06:41:38 PM PDT 24
Peak memory 217332 kb
Host smart-b15a9cf2-86b4-4d39-abba-cf911311398d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2820518956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2820518956
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1924708623
Short name T582
Test name
Test status
Simulation time 265396465 ps
CPU time 1.04 seconds
Started Aug 13 06:40:33 PM PDT 24
Finished Aug 13 06:40:34 PM PDT 24
Peak memory 207448 kb
Host smart-390ae10c-da45-442d-a21c-dc162a122887
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1924708623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1924708623
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3593981153
Short name T734
Test name
Test status
Simulation time 192880567 ps
CPU time 1 seconds
Started Aug 13 06:40:36 PM PDT 24
Finished Aug 13 06:40:37 PM PDT 24
Peak memory 207424 kb
Host smart-a95df501-6735-4dca-90f8-f866698ba50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35939
81153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3593981153
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3436537411
Short name T3008
Test name
Test status
Simulation time 3803502366 ps
CPU time 108.81 seconds
Started Aug 13 06:40:36 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 217520 kb
Host smart-b085ebf4-8887-4aa6-acf3-49786a77c86e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3436537411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3436537411
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1261563484
Short name T1557
Test name
Test status
Simulation time 151322927 ps
CPU time 0.83 seconds
Started Aug 13 06:40:36 PM PDT 24
Finished Aug 13 06:40:37 PM PDT 24
Peak memory 207516 kb
Host smart-00e414ce-da7d-4951-a8a7-ee1024444f53
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1261563484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1261563484
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3244678502
Short name T1545
Test name
Test status
Simulation time 148755769 ps
CPU time 0.89 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:40:39 PM PDT 24
Peak memory 207432 kb
Host smart-6b5079b0-d360-421e-af3a-958018e6cb5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32446
78502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3244678502
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3326965001
Short name T139
Test name
Test status
Simulation time 222314122 ps
CPU time 0.98 seconds
Started Aug 13 06:40:28 PM PDT 24
Finished Aug 13 06:40:29 PM PDT 24
Peak memory 207508 kb
Host smart-a0bda999-4da1-4c78-8198-3bd2cf6df37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33269
65001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3326965001
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2545790467
Short name T1193
Test name
Test status
Simulation time 220087957 ps
CPU time 0.95 seconds
Started Aug 13 06:40:28 PM PDT 24
Finished Aug 13 06:40:29 PM PDT 24
Peak memory 207532 kb
Host smart-a6afc69f-98ae-4f63-9ca1-9d74f8548f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25457
90467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2545790467
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2957641673
Short name T2398
Test name
Test status
Simulation time 165734338 ps
CPU time 0.88 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:40:49 PM PDT 24
Peak memory 207528 kb
Host smart-04a37d48-3b22-4155-9314-cada5ef84489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29576
41673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2957641673
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2271514837
Short name T1926
Test name
Test status
Simulation time 161211522 ps
CPU time 0.85 seconds
Started Aug 13 06:40:31 PM PDT 24
Finished Aug 13 06:40:32 PM PDT 24
Peak memory 207524 kb
Host smart-e611b768-0d30-4317-b3bc-74ef025269f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22715
14837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2271514837
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3067014094
Short name T167
Test name
Test status
Simulation time 236860513 ps
CPU time 0.93 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:40:42 PM PDT 24
Peak memory 207500 kb
Host smart-19112f80-d95e-4ad9-8405-a9e02ec77986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30670
14094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3067014094
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3874051763
Short name T3383
Test name
Test status
Simulation time 221071995 ps
CPU time 1.03 seconds
Started Aug 13 06:40:24 PM PDT 24
Finished Aug 13 06:40:25 PM PDT 24
Peak memory 207544 kb
Host smart-23e899fa-f2f2-45de-b5e0-06dde20cafd6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3874051763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3874051763
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.669127820
Short name T817
Test name
Test status
Simulation time 140520804 ps
CPU time 0.86 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:40:42 PM PDT 24
Peak memory 207480 kb
Host smart-bd6fb970-157f-4495-ae3d-91c6829d6382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66912
7820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.669127820
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1665999765
Short name T2179
Test name
Test status
Simulation time 61659721 ps
CPU time 0.72 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:40:47 PM PDT 24
Peak memory 207556 kb
Host smart-808e56ba-24cd-4a25-a7ad-282a4fa23c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16659
99765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1665999765
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.228639318
Short name T1378
Test name
Test status
Simulation time 17315509149 ps
CPU time 41.46 seconds
Started Aug 13 06:40:34 PM PDT 24
Finished Aug 13 06:41:15 PM PDT 24
Peak memory 224180 kb
Host smart-846cdb96-9831-4a5f-a253-8c64fced4e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22863
9318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.228639318
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2730881920
Short name T3127
Test name
Test status
Simulation time 233939261 ps
CPU time 1.02 seconds
Started Aug 13 06:40:30 PM PDT 24
Finished Aug 13 06:40:31 PM PDT 24
Peak memory 207496 kb
Host smart-9a1ac55f-36e8-4d4a-b18d-ef02fba53221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27308
81920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2730881920
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2176642880
Short name T1516
Test name
Test status
Simulation time 253137956 ps
CPU time 1.02 seconds
Started Aug 13 06:40:34 PM PDT 24
Finished Aug 13 06:40:36 PM PDT 24
Peak memory 207500 kb
Host smart-f4ffa6c9-c675-4016-b52e-2a0abbf0cf2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21766
42880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2176642880
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.854996225
Short name T2423
Test name
Test status
Simulation time 226217400 ps
CPU time 0.99 seconds
Started Aug 13 06:40:38 PM PDT 24
Finished Aug 13 06:40:39 PM PDT 24
Peak memory 207480 kb
Host smart-b3dced71-7a8c-45fe-a43a-8a11fd780f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85499
6225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.854996225
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.681756566
Short name T2925
Test name
Test status
Simulation time 210512660 ps
CPU time 0.95 seconds
Started Aug 13 06:40:26 PM PDT 24
Finished Aug 13 06:40:27 PM PDT 24
Peak memory 207500 kb
Host smart-5c18de9b-e7d5-42c5-a12c-82c82a318730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68175
6566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.681756566
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1764707209
Short name T3458
Test name
Test status
Simulation time 138514998 ps
CPU time 0.82 seconds
Started Aug 13 06:40:24 PM PDT 24
Finished Aug 13 06:40:25 PM PDT 24
Peak memory 207464 kb
Host smart-2e8574ab-a3c5-4f1f-9fb0-60064431fc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17647
07209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1764707209
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_rx_full.1273742071
Short name T2511
Test name
Test status
Simulation time 359769418 ps
CPU time 1.22 seconds
Started Aug 13 06:40:29 PM PDT 24
Finished Aug 13 06:40:30 PM PDT 24
Peak memory 207516 kb
Host smart-c37144fd-3f02-46cc-a950-26b86676eaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12737
42071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.1273742071
Directory /workspace/46.usbdev_rx_full/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.4012547838
Short name T1219
Test name
Test status
Simulation time 154936941 ps
CPU time 0.86 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:40:42 PM PDT 24
Peak memory 207572 kb
Host smart-2e3bb6ab-d0ca-4c06-ac65-ba5d4bfe3f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40125
47838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.4012547838
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1297074221
Short name T3342
Test name
Test status
Simulation time 150225853 ps
CPU time 0.86 seconds
Started Aug 13 06:40:23 PM PDT 24
Finished Aug 13 06:40:24 PM PDT 24
Peak memory 207396 kb
Host smart-d2d09598-39ea-470d-90ec-ac9d1cbe362e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12970
74221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1297074221
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2001926188
Short name T1903
Test name
Test status
Simulation time 236227386 ps
CPU time 1.11 seconds
Started Aug 13 06:40:42 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 207500 kb
Host smart-71c626df-b858-48eb-b0c1-b4ea2b7de3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20019
26188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2001926188
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.299334983
Short name T3396
Test name
Test status
Simulation time 2775072143 ps
CPU time 29.35 seconds
Started Aug 13 06:40:35 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 217756 kb
Host smart-b10454c6-b1dd-4ecd-96ae-86f6cb07149c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=299334983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.299334983
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.796529780
Short name T1216
Test name
Test status
Simulation time 182696595 ps
CPU time 0.92 seconds
Started Aug 13 06:40:35 PM PDT 24
Finished Aug 13 06:40:36 PM PDT 24
Peak memory 207468 kb
Host smart-fc849e9c-a6ba-403f-905a-96cba05c3ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79652
9780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.796529780
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.288000909
Short name T661
Test name
Test status
Simulation time 156398054 ps
CPU time 0.83 seconds
Started Aug 13 06:40:29 PM PDT 24
Finished Aug 13 06:40:30 PM PDT 24
Peak memory 207472 kb
Host smart-80783e44-1577-485c-97b7-76efb19048b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28800
0909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.288000909
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3377741636
Short name T1273
Test name
Test status
Simulation time 451665639 ps
CPU time 1.36 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:40:41 PM PDT 24
Peak memory 207500 kb
Host smart-a9a202b2-5f67-4daf-b034-5e7e3ecaa23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33777
41636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3377741636
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1585984409
Short name T1991
Test name
Test status
Simulation time 2340678845 ps
CPU time 17.76 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207836 kb
Host smart-5f304f65-5f92-445d-867d-cf23ab3e23c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15859
84409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1585984409
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.1840675137
Short name T113
Test name
Test status
Simulation time 3907550740 ps
CPU time 37.28 seconds
Started Aug 13 06:40:29 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207712 kb
Host smart-e5668373-e9a3-40e4-8a64-34dbe6dded55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840675137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.1840675137
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_tx_rx_disruption.656564895
Short name T3150
Test name
Test status
Simulation time 552174223 ps
CPU time 1.55 seconds
Started Aug 13 06:40:42 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 207584 kb
Host smart-fc86ed1a-179c-4808-9811-c239c58646a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656564895 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.usbdev_tx_rx_disruption.656564895
Directory /workspace/46.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/460.usbdev_tx_rx_disruption.181389536
Short name T200
Test name
Test status
Simulation time 585925635 ps
CPU time 1.64 seconds
Started Aug 13 06:42:19 PM PDT 24
Finished Aug 13 06:42:21 PM PDT 24
Peak memory 207592 kb
Host smart-3e3fed15-e9f2-44ac-8dd1-517d7ff509d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181389536 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 460.usbdev_tx_rx_disruption.181389536
Directory /workspace/460.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/461.usbdev_tx_rx_disruption.3787438090
Short name T1914
Test name
Test status
Simulation time 503558304 ps
CPU time 1.57 seconds
Started Aug 13 06:42:19 PM PDT 24
Finished Aug 13 06:42:20 PM PDT 24
Peak memory 207572 kb
Host smart-0c5280bf-70f7-4c20-9077-4fcddc0d86bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787438090 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 461.usbdev_tx_rx_disruption.3787438090
Directory /workspace/461.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/462.usbdev_tx_rx_disruption.287235905
Short name T1452
Test name
Test status
Simulation time 464224325 ps
CPU time 1.5 seconds
Started Aug 13 06:42:40 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 207576 kb
Host smart-c7ce71e9-ba56-4142-88b4-b6306ec851d2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287235905 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 462.usbdev_tx_rx_disruption.287235905
Directory /workspace/462.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/463.usbdev_tx_rx_disruption.3398213776
Short name T630
Test name
Test status
Simulation time 526276718 ps
CPU time 1.54 seconds
Started Aug 13 06:42:28 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 207612 kb
Host smart-a07c1119-7c69-4325-ac21-ca0bc30a8b0a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398213776 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 463.usbdev_tx_rx_disruption.3398213776
Directory /workspace/463.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/464.usbdev_tx_rx_disruption.4150974563
Short name T3569
Test name
Test status
Simulation time 566972034 ps
CPU time 1.69 seconds
Started Aug 13 06:42:25 PM PDT 24
Finished Aug 13 06:42:27 PM PDT 24
Peak memory 207612 kb
Host smart-1dab84e0-3ee4-494b-bf9b-7a77425a5119
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150974563 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 464.usbdev_tx_rx_disruption.4150974563
Directory /workspace/464.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/465.usbdev_tx_rx_disruption.236982690
Short name T1868
Test name
Test status
Simulation time 466313754 ps
CPU time 1.44 seconds
Started Aug 13 06:42:14 PM PDT 24
Finished Aug 13 06:42:15 PM PDT 24
Peak memory 207592 kb
Host smart-ab4c778b-5d71-4316-9c7c-ffde59350748
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236982690 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 465.usbdev_tx_rx_disruption.236982690
Directory /workspace/465.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/466.usbdev_tx_rx_disruption.2492539453
Short name T1694
Test name
Test status
Simulation time 634881254 ps
CPU time 1.74 seconds
Started Aug 13 06:42:19 PM PDT 24
Finished Aug 13 06:42:21 PM PDT 24
Peak memory 207612 kb
Host smart-aef83f32-97ef-4d17-9a22-cad1e6d32895
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492539453 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 466.usbdev_tx_rx_disruption.2492539453
Directory /workspace/466.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/467.usbdev_tx_rx_disruption.3428379718
Short name T1672
Test name
Test status
Simulation time 446407413 ps
CPU time 1.49 seconds
Started Aug 13 06:42:33 PM PDT 24
Finished Aug 13 06:42:34 PM PDT 24
Peak memory 207592 kb
Host smart-4101dc04-343f-4473-a347-2bba25740381
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428379718 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 467.usbdev_tx_rx_disruption.3428379718
Directory /workspace/467.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/468.usbdev_tx_rx_disruption.3612352405
Short name T789
Test name
Test status
Simulation time 581903716 ps
CPU time 1.72 seconds
Started Aug 13 06:42:33 PM PDT 24
Finished Aug 13 06:42:35 PM PDT 24
Peak memory 207600 kb
Host smart-88867900-4b5e-40ad-98d2-4dc48d1ca4cd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612352405 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 468.usbdev_tx_rx_disruption.3612352405
Directory /workspace/468.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/469.usbdev_tx_rx_disruption.186506576
Short name T2418
Test name
Test status
Simulation time 470742056 ps
CPU time 1.54 seconds
Started Aug 13 06:42:25 PM PDT 24
Finished Aug 13 06:42:27 PM PDT 24
Peak memory 207572 kb
Host smart-0d5f1c83-f4d3-4b61-b22d-40b637babc3f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186506576 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 469.usbdev_tx_rx_disruption.186506576
Directory /workspace/469.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3890031543
Short name T2573
Test name
Test status
Simulation time 40616107 ps
CPU time 0.65 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:40:47 PM PDT 24
Peak memory 207508 kb
Host smart-8d9fe48d-0d1a-49ee-8db3-5310a9307942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3890031543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3890031543
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2624519267
Short name T3306
Test name
Test status
Simulation time 4249557353 ps
CPU time 6.21 seconds
Started Aug 13 06:40:26 PM PDT 24
Finished Aug 13 06:40:32 PM PDT 24
Peak memory 216012 kb
Host smart-9b0f2208-ca1b-4da1-a6c7-39bf421debb8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624519267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.2624519267
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.4031423692
Short name T1102
Test name
Test status
Simulation time 14002699943 ps
CPU time 17.67 seconds
Started Aug 13 06:40:26 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 215992 kb
Host smart-f1e53fee-3c53-40fa-b79a-1e31441f3c4b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031423692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.4031423692
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.312490975
Short name T2952
Test name
Test status
Simulation time 24115851195 ps
CPU time 28.47 seconds
Started Aug 13 06:40:37 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 216012 kb
Host smart-0033dd7a-8fa5-497d-8a1a-a3d50a078bfb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312490975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ao
n_wake_resume.312490975
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3523667664
Short name T998
Test name
Test status
Simulation time 151114677 ps
CPU time 0.86 seconds
Started Aug 13 06:40:37 PM PDT 24
Finished Aug 13 06:40:38 PM PDT 24
Peak memory 207504 kb
Host smart-5aae3f60-43e0-4cd4-b79a-7e328ce1e012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35236
67664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3523667664
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3010305692
Short name T2196
Test name
Test status
Simulation time 140188904 ps
CPU time 0.91 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:40:49 PM PDT 24
Peak memory 207532 kb
Host smart-e38f95fa-a34c-47a2-8b68-753e080dc22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30103
05692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3010305692
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.384298823
Short name T3515
Test name
Test status
Simulation time 368631460 ps
CPU time 1.35 seconds
Started Aug 13 06:40:40 PM PDT 24
Finished Aug 13 06:40:42 PM PDT 24
Peak memory 207580 kb
Host smart-a5271c23-dd42-454a-8538-aff77dc19195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38429
8823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.384298823
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.476609455
Short name T123
Test name
Test status
Simulation time 311110778 ps
CPU time 1.01 seconds
Started Aug 13 06:40:36 PM PDT 24
Finished Aug 13 06:40:37 PM PDT 24
Peak memory 207520 kb
Host smart-29a1ad71-560d-4308-8588-ec06321ebfc2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=476609455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.476609455
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.193803509
Short name T2787
Test name
Test status
Simulation time 28675386537 ps
CPU time 46.29 seconds
Started Aug 13 06:40:50 PM PDT 24
Finished Aug 13 06:41:37 PM PDT 24
Peak memory 207868 kb
Host smart-1b4589ed-1fe0-4f89-b85c-6cb4152f93f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19380
3509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.193803509
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.1678971047
Short name T2961
Test name
Test status
Simulation time 2550977393 ps
CPU time 17.33 seconds
Started Aug 13 06:40:45 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207844 kb
Host smart-15d578fc-afe1-4fea-b0d5-4042678a79be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678971047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.1678971047
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1636589045
Short name T1037
Test name
Test status
Simulation time 404782647 ps
CPU time 1.35 seconds
Started Aug 13 06:40:30 PM PDT 24
Finished Aug 13 06:40:32 PM PDT 24
Peak memory 207500 kb
Host smart-ff404470-0855-449b-9139-68afbc6632fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16365
89045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1636589045
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.205878422
Short name T1227
Test name
Test status
Simulation time 138464651 ps
CPU time 0.83 seconds
Started Aug 13 06:40:38 PM PDT 24
Finished Aug 13 06:40:39 PM PDT 24
Peak memory 207548 kb
Host smart-0121daa3-806d-463d-a6d5-ade46300291b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20587
8422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.205878422
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1625629588
Short name T910
Test name
Test status
Simulation time 45453592 ps
CPU time 0.71 seconds
Started Aug 13 06:40:31 PM PDT 24
Finished Aug 13 06:40:32 PM PDT 24
Peak memory 207404 kb
Host smart-b84a78bb-0497-423a-be69-c946953b3bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
29588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1625629588
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2427832180
Short name T565
Test name
Test status
Simulation time 894093439 ps
CPU time 2.41 seconds
Started Aug 13 06:40:36 PM PDT 24
Finished Aug 13 06:40:39 PM PDT 24
Peak memory 207784 kb
Host smart-76305746-5b3d-45ae-8c91-d987b09edc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24278
32180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2427832180
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1923849405
Short name T2580
Test name
Test status
Simulation time 180346695 ps
CPU time 2.51 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:40:49 PM PDT 24
Peak memory 207676 kb
Host smart-8a65765a-021e-450d-a864-14424cbbb344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19238
49405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1923849405
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2067274758
Short name T2278
Test name
Test status
Simulation time 244629907 ps
CPU time 1.14 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:40:42 PM PDT 24
Peak memory 216904 kb
Host smart-f7685d40-63fb-4cf0-86a1-8ae627614945
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2067274758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2067274758
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3311407436
Short name T859
Test name
Test status
Simulation time 141950131 ps
CPU time 0.82 seconds
Started Aug 13 06:40:45 PM PDT 24
Finished Aug 13 06:40:46 PM PDT 24
Peak memory 207464 kb
Host smart-37a8605f-62fd-467b-8f73-63a37813c6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33114
07436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3311407436
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2187008066
Short name T3139
Test name
Test status
Simulation time 191726557 ps
CPU time 0.91 seconds
Started Aug 13 06:40:43 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 207488 kb
Host smart-df9c53df-37cd-4ce7-a69c-242d2a821e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21870
08066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2187008066
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.464741701
Short name T2181
Test name
Test status
Simulation time 2792308995 ps
CPU time 20.1 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 224140 kb
Host smart-59924b5e-1664-474b-801f-cbcb1d195905
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=464741701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.464741701
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.807471469
Short name T3330
Test name
Test status
Simulation time 7173194339 ps
CPU time 84.91 seconds
Started Aug 13 06:40:34 PM PDT 24
Finished Aug 13 06:41:59 PM PDT 24
Peak memory 207744 kb
Host smart-7cecfdfa-8a65-47f6-bb95-50db17595724
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=807471469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.807471469
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.193168041
Short name T598
Test name
Test status
Simulation time 191424733 ps
CPU time 0.95 seconds
Started Aug 13 06:40:45 PM PDT 24
Finished Aug 13 06:40:46 PM PDT 24
Peak memory 207476 kb
Host smart-623fd3dd-6b9c-41b9-8641-4fd0c030be24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19316
8041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.193168041
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3270281409
Short name T958
Test name
Test status
Simulation time 9117576680 ps
CPU time 12.01 seconds
Started Aug 13 06:40:44 PM PDT 24
Finished Aug 13 06:40:56 PM PDT 24
Peak memory 207836 kb
Host smart-fe43e16d-7aed-4677-b822-647da90fc40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702
81409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3270281409
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.646093437
Short name T1599
Test name
Test status
Simulation time 3838124347 ps
CPU time 109.07 seconds
Started Aug 13 06:40:43 PM PDT 24
Finished Aug 13 06:42:32 PM PDT 24
Peak memory 216036 kb
Host smart-a2beaf17-15e5-4d49-8bb2-90bf9554c2c7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=646093437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.646093437
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3056463808
Short name T1032
Test name
Test status
Simulation time 255410999 ps
CPU time 1.06 seconds
Started Aug 13 06:40:45 PM PDT 24
Finished Aug 13 06:40:46 PM PDT 24
Peak memory 207488 kb
Host smart-49de37ff-10b1-4449-be2a-fe4f348372d5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3056463808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3056463808
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.538483349
Short name T3295
Test name
Test status
Simulation time 203961110 ps
CPU time 1.01 seconds
Started Aug 13 06:40:35 PM PDT 24
Finished Aug 13 06:40:36 PM PDT 24
Peak memory 207460 kb
Host smart-b5365a41-f60a-48a5-af64-e88a58967c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53848
3349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.538483349
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.4003793923
Short name T1728
Test name
Test status
Simulation time 1577716860 ps
CPU time 15.59 seconds
Started Aug 13 06:40:47 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 224040 kb
Host smart-24b7ffce-b4ba-4269-a46a-3f261ff97db7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4003793923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.4003793923
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2688690868
Short name T2093
Test name
Test status
Simulation time 155865054 ps
CPU time 0.87 seconds
Started Aug 13 06:40:37 PM PDT 24
Finished Aug 13 06:40:38 PM PDT 24
Peak memory 207516 kb
Host smart-646c88a1-72a0-4503-b767-9eba0e02af74
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2688690868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2688690868
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1532695343
Short name T3334
Test name
Test status
Simulation time 150657422 ps
CPU time 0.86 seconds
Started Aug 13 06:40:50 PM PDT 24
Finished Aug 13 06:40:51 PM PDT 24
Peak memory 207524 kb
Host smart-4e8dd949-ff33-4a34-a4b6-6791057b9513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15326
95343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1532695343
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4021037857
Short name T132
Test name
Test status
Simulation time 186674092 ps
CPU time 0.95 seconds
Started Aug 13 06:40:50 PM PDT 24
Finished Aug 13 06:40:51 PM PDT 24
Peak memory 207440 kb
Host smart-aa8d49f2-cf66-4e44-8f3b-27f2ca798467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40210
37857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4021037857
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1971917451
Short name T2685
Test name
Test status
Simulation time 175525581 ps
CPU time 0.9 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:40:47 PM PDT 24
Peak memory 207528 kb
Host smart-dbabb9b8-38b5-483b-aa13-c837536bc3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19719
17451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1971917451
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.869043034
Short name T2345
Test name
Test status
Simulation time 186153980 ps
CPU time 0.93 seconds
Started Aug 13 06:40:42 PM PDT 24
Finished Aug 13 06:40:43 PM PDT 24
Peak memory 207424 kb
Host smart-f7488ce4-547c-43ef-95cb-8242c29d8952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86904
3034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.869043034
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1533640926
Short name T587
Test name
Test status
Simulation time 170487643 ps
CPU time 0.92 seconds
Started Aug 13 06:40:51 PM PDT 24
Finished Aug 13 06:40:52 PM PDT 24
Peak memory 207612 kb
Host smart-28893ab8-8d86-4b5b-87c0-03d204d73c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15336
40926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1533640926
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.4086541911
Short name T2688
Test name
Test status
Simulation time 151154414 ps
CPU time 0.89 seconds
Started Aug 13 06:40:42 PM PDT 24
Finished Aug 13 06:40:43 PM PDT 24
Peak memory 207524 kb
Host smart-3221e9d4-b2ca-4082-842e-800b584e3033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40865
41911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.4086541911
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2851034744
Short name T223
Test name
Test status
Simulation time 181029422 ps
CPU time 0.92 seconds
Started Aug 13 06:40:30 PM PDT 24
Finished Aug 13 06:40:31 PM PDT 24
Peak memory 207600 kb
Host smart-449c4097-16a1-4e46-94a1-7bf45788d87b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2851034744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2851034744
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1062699582
Short name T3307
Test name
Test status
Simulation time 146274314 ps
CPU time 0.85 seconds
Started Aug 13 06:40:43 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 207492 kb
Host smart-98d12056-9f8c-4947-b28f-7efe1fa9fb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10626
99582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1062699582
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2684770764
Short name T1479
Test name
Test status
Simulation time 66119097 ps
CPU time 0.77 seconds
Started Aug 13 06:40:42 PM PDT 24
Finished Aug 13 06:40:43 PM PDT 24
Peak memory 207564 kb
Host smart-c9212bfd-3ce8-4008-9008-298b9c2325a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26847
70764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2684770764
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3084882305
Short name T1425
Test name
Test status
Simulation time 19884377196 ps
CPU time 48.71 seconds
Started Aug 13 06:40:25 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 215952 kb
Host smart-375cb3b6-048b-49ae-b032-3bbc6fe0634e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30848
82305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3084882305
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2686417510
Short name T1287
Test name
Test status
Simulation time 165601127 ps
CPU time 0.87 seconds
Started Aug 13 06:40:32 PM PDT 24
Finished Aug 13 06:40:33 PM PDT 24
Peak memory 207592 kb
Host smart-6fc05968-e471-4b54-a29f-a113640ac784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26864
17510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2686417510
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3670687431
Short name T3249
Test name
Test status
Simulation time 205990380 ps
CPU time 0.96 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:40:49 PM PDT 24
Peak memory 207504 kb
Host smart-04443166-0dd8-4f49-99a1-27d5428dc697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36706
87431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3670687431
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.3187756624
Short name T677
Test name
Test status
Simulation time 215999294 ps
CPU time 0.97 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:40:42 PM PDT 24
Peak memory 207516 kb
Host smart-fe145bd3-71ce-45ac-bb8e-d838e5963aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31877
56624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.3187756624
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.2859804422
Short name T2129
Test name
Test status
Simulation time 158384456 ps
CPU time 0.9 seconds
Started Aug 13 06:40:50 PM PDT 24
Finished Aug 13 06:40:51 PM PDT 24
Peak memory 207492 kb
Host smart-ebbf7ee0-1186-4758-b026-5cdcbaa7f34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28598
04422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.2859804422
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1637478104
Short name T3327
Test name
Test status
Simulation time 143540536 ps
CPU time 0.85 seconds
Started Aug 13 06:40:53 PM PDT 24
Finished Aug 13 06:40:54 PM PDT 24
Peak memory 207460 kb
Host smart-4bda41f9-9814-40cc-aada-8c76fbb16ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16374
78104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1637478104
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_rx_full.3735307686
Short name T1491
Test name
Test status
Simulation time 367865058 ps
CPU time 1.35 seconds
Started Aug 13 06:40:42 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 207512 kb
Host smart-fc09819e-7b44-4aef-98be-848532257115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37353
07686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.3735307686
Directory /workspace/47.usbdev_rx_full/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1100607200
Short name T2634
Test name
Test status
Simulation time 163454364 ps
CPU time 0.92 seconds
Started Aug 13 06:40:31 PM PDT 24
Finished Aug 13 06:40:32 PM PDT 24
Peak memory 207524 kb
Host smart-ac71c657-9b59-475a-ae87-0b2721ce5098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11006
07200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1100607200
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2707911540
Short name T334
Test name
Test status
Simulation time 168840208 ps
CPU time 0.85 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:40:40 PM PDT 24
Peak memory 207504 kb
Host smart-bc0bc0da-48bc-477d-babd-be953178c791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27079
11540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2707911540
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3948903083
Short name T1494
Test name
Test status
Simulation time 229151986 ps
CPU time 1.05 seconds
Started Aug 13 06:40:31 PM PDT 24
Finished Aug 13 06:40:32 PM PDT 24
Peak memory 207388 kb
Host smart-61f823ad-b045-4a56-8029-8133a2824555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39489
03083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3948903083
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.39075306
Short name T1304
Test name
Test status
Simulation time 1940566809 ps
CPU time 19.34 seconds
Started Aug 13 06:40:54 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 224016 kb
Host smart-be41cc5b-6e3d-4b22-a0d0-02dafaf138e1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=39075306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.39075306
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1270649239
Short name T776
Test name
Test status
Simulation time 157849604 ps
CPU time 0.88 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207420 kb
Host smart-ddc1d51b-c472-45c3-8895-a9ba35ac66f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12706
49239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1270649239
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3925728248
Short name T735
Test name
Test status
Simulation time 182987122 ps
CPU time 0.92 seconds
Started Aug 13 06:40:30 PM PDT 24
Finished Aug 13 06:40:31 PM PDT 24
Peak memory 207584 kb
Host smart-d5c73d9e-4ac5-4dba-9584-bee9d9f53fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39257
28248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3925728248
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1405023834
Short name T1202
Test name
Test status
Simulation time 335166420 ps
CPU time 1.2 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:40:41 PM PDT 24
Peak memory 207540 kb
Host smart-33486585-19e9-41a8-9559-a98f25c8335f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14050
23834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1405023834
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.156145382
Short name T2633
Test name
Test status
Simulation time 1822197550 ps
CPU time 49.06 seconds
Started Aug 13 06:40:49 PM PDT 24
Finished Aug 13 06:41:38 PM PDT 24
Peak memory 224080 kb
Host smart-8228537d-276f-49af-aad8-df4dba37d9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15614
5382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.156145382
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.962531752
Short name T2402
Test name
Test status
Simulation time 3640445449 ps
CPU time 23.98 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:41:10 PM PDT 24
Peak memory 207688 kb
Host smart-7d605af4-0b8c-47a1-9a99-c09b32bfec96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962531752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_host
_handshake.962531752
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_tx_rx_disruption.1510065708
Short name T2492
Test name
Test status
Simulation time 623637675 ps
CPU time 1.66 seconds
Started Aug 13 06:40:53 PM PDT 24
Finished Aug 13 06:40:54 PM PDT 24
Peak memory 207472 kb
Host smart-9708e8a3-cd8b-4506-a966-8aeb318d69d6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510065708 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.usbdev_tx_rx_disruption.1510065708
Directory /workspace/47.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/470.usbdev_tx_rx_disruption.416486275
Short name T3558
Test name
Test status
Simulation time 487567929 ps
CPU time 1.48 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:27 PM PDT 24
Peak memory 207576 kb
Host smart-95bb15df-379b-42fe-80cb-9611a5165c86
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416486275 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 470.usbdev_tx_rx_disruption.416486275
Directory /workspace/470.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/471.usbdev_tx_rx_disruption.1266957965
Short name T266
Test name
Test status
Simulation time 605570641 ps
CPU time 1.6 seconds
Started Aug 13 06:42:25 PM PDT 24
Finished Aug 13 06:42:27 PM PDT 24
Peak memory 207592 kb
Host smart-f41ce5eb-c8d0-4d69-a0f9-9aeae046c5cf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266957965 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 471.usbdev_tx_rx_disruption.1266957965
Directory /workspace/471.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/472.usbdev_tx_rx_disruption.3206866433
Short name T1797
Test name
Test status
Simulation time 517219736 ps
CPU time 1.5 seconds
Started Aug 13 06:42:28 PM PDT 24
Finished Aug 13 06:42:30 PM PDT 24
Peak memory 207476 kb
Host smart-f16bc49d-e4a9-45c9-a485-dbac68e1650c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206866433 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 472.usbdev_tx_rx_disruption.3206866433
Directory /workspace/472.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/473.usbdev_tx_rx_disruption.2750192381
Short name T674
Test name
Test status
Simulation time 558040494 ps
CPU time 1.62 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:27 PM PDT 24
Peak memory 207536 kb
Host smart-0d9a0517-adf9-4c06-9c7f-8c0c45b9a972
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750192381 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 473.usbdev_tx_rx_disruption.2750192381
Directory /workspace/473.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/474.usbdev_tx_rx_disruption.2447881642
Short name T3136
Test name
Test status
Simulation time 492009349 ps
CPU time 1.56 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 207628 kb
Host smart-e43a533a-ef82-4729-b2d7-a03ba06cc48b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447881642 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 474.usbdev_tx_rx_disruption.2447881642
Directory /workspace/474.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/475.usbdev_tx_rx_disruption.2668184977
Short name T1798
Test name
Test status
Simulation time 512709310 ps
CPU time 1.62 seconds
Started Aug 13 06:42:38 PM PDT 24
Finished Aug 13 06:42:39 PM PDT 24
Peak memory 207608 kb
Host smart-c049230c-fcbc-419f-9e3d-0ecccc004974
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668184977 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 475.usbdev_tx_rx_disruption.2668184977
Directory /workspace/475.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/476.usbdev_tx_rx_disruption.484970135
Short name T1012
Test name
Test status
Simulation time 507484154 ps
CPU time 1.59 seconds
Started Aug 13 06:42:30 PM PDT 24
Finished Aug 13 06:42:31 PM PDT 24
Peak memory 207612 kb
Host smart-9e1e1436-7550-4bb1-bd27-1c2fd7db020d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484970135 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 476.usbdev_tx_rx_disruption.484970135
Directory /workspace/476.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/477.usbdev_tx_rx_disruption.873863988
Short name T925
Test name
Test status
Simulation time 419176186 ps
CPU time 1.4 seconds
Started Aug 13 06:42:25 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 207548 kb
Host smart-a28cf2ff-3f41-4461-a1d8-9651b8e845c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873863988 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 477.usbdev_tx_rx_disruption.873863988
Directory /workspace/477.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/478.usbdev_tx_rx_disruption.405758355
Short name T566
Test name
Test status
Simulation time 653735290 ps
CPU time 1.8 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 207616 kb
Host smart-c402774a-4fb3-442e-93e1-c47237597d2e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405758355 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 478.usbdev_tx_rx_disruption.405758355
Directory /workspace/478.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/479.usbdev_tx_rx_disruption.102345449
Short name T2300
Test name
Test status
Simulation time 537641898 ps
CPU time 1.46 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207628 kb
Host smart-b46161b8-89f2-48db-93be-7e5fe7e48be2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102345449 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 479.usbdev_tx_rx_disruption.102345449
Directory /workspace/479.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2879943531
Short name T1118
Test name
Test status
Simulation time 56881637 ps
CPU time 0.69 seconds
Started Aug 13 06:40:47 PM PDT 24
Finished Aug 13 06:40:47 PM PDT 24
Peak memory 207456 kb
Host smart-3a1af1a9-bc0b-4547-bcd4-81b272faba8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2879943531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2879943531
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.684378086
Short name T2579
Test name
Test status
Simulation time 11475266208 ps
CPU time 15.58 seconds
Started Aug 13 06:40:47 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207836 kb
Host smart-d399d9eb-778a-4bf9-830c-0ff85d138c89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684378086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_disconnect.684378086
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.234847644
Short name T2600
Test name
Test status
Simulation time 13983848575 ps
CPU time 18.17 seconds
Started Aug 13 06:40:43 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 215980 kb
Host smart-d1776da7-bc34-492f-a992-0460f1191a36
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=234847644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.234847644
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.2858088027
Short name T2873
Test name
Test status
Simulation time 31125736234 ps
CPU time 42.91 seconds
Started Aug 13 06:40:42 PM PDT 24
Finished Aug 13 06:41:25 PM PDT 24
Peak memory 207840 kb
Host smart-ee253ea8-ebea-4f8a-801c-51614177bcfc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858088027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.2858088027
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.997940587
Short name T2621
Test name
Test status
Simulation time 155351163 ps
CPU time 0.86 seconds
Started Aug 13 06:40:33 PM PDT 24
Finished Aug 13 06:40:34 PM PDT 24
Peak memory 207508 kb
Host smart-9eed4bc8-1dc1-4440-92d2-f3f7e8e419c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99794
0587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.997940587
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.1350116496
Short name T3467
Test name
Test status
Simulation time 164279831 ps
CPU time 0.85 seconds
Started Aug 13 06:40:50 PM PDT 24
Finished Aug 13 06:40:51 PM PDT 24
Peak memory 207516 kb
Host smart-192ca51f-1e55-4218-870c-6b3e44d96ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13501
16496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.1350116496
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2621413045
Short name T669
Test name
Test status
Simulation time 625464129 ps
CPU time 1.95 seconds
Started Aug 13 06:40:42 PM PDT 24
Finished Aug 13 06:40:44 PM PDT 24
Peak memory 207784 kb
Host smart-24373ef7-85a8-4840-b3d8-5942eb0c108f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26214
13045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2621413045
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3326990808
Short name T1858
Test name
Test status
Simulation time 713725836 ps
CPU time 1.88 seconds
Started Aug 13 06:40:38 PM PDT 24
Finished Aug 13 06:40:40 PM PDT 24
Peak memory 207528 kb
Host smart-1f26e6f5-ccdb-49eb-aa14-bcac7073b845
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3326990808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3326990808
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.246897595
Short name T2182
Test name
Test status
Simulation time 43182207553 ps
CPU time 71.17 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 207836 kb
Host smart-58bf7663-09be-442a-acae-8212c1ea4407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24689
7595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.246897595
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.3047401341
Short name T2508
Test name
Test status
Simulation time 894506359 ps
CPU time 18.84 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207816 kb
Host smart-f13d2b34-eba7-4570-926a-355287a339e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047401341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.3047401341
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1682955759
Short name T2218
Test name
Test status
Simulation time 1106557781 ps
CPU time 2.41 seconds
Started Aug 13 06:40:31 PM PDT 24
Finished Aug 13 06:40:33 PM PDT 24
Peak memory 207548 kb
Host smart-8cfeb338-32ba-4eb8-8aa7-5f9bed3a0ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16829
55759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1682955759
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.4207366384
Short name T2349
Test name
Test status
Simulation time 159213954 ps
CPU time 0.83 seconds
Started Aug 13 06:40:33 PM PDT 24
Finished Aug 13 06:40:34 PM PDT 24
Peak memory 207544 kb
Host smart-825dcc90-19bb-4747-af13-20f82f7616ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42073
66384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.4207366384
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2815495229
Short name T1907
Test name
Test status
Simulation time 35476080 ps
CPU time 0.68 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:40:40 PM PDT 24
Peak memory 207456 kb
Host smart-19f397f7-4f44-42ff-b2a3-cf40364deda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28154
95229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2815495229
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2732685622
Short name T626
Test name
Test status
Simulation time 936367693 ps
CPU time 2.6 seconds
Started Aug 13 06:40:53 PM PDT 24
Finished Aug 13 06:40:56 PM PDT 24
Peak memory 207804 kb
Host smart-d93cafb4-092a-4f56-b70b-9473508612c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27326
85622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2732685622
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_types.2273506591
Short name T3316
Test name
Test status
Simulation time 550013033 ps
CPU time 1.52 seconds
Started Aug 13 06:40:44 PM PDT 24
Finished Aug 13 06:40:46 PM PDT 24
Peak memory 207552 kb
Host smart-38c27789-40df-418e-aebf-82a6c5e75e11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2273506591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.2273506591
Directory /workspace/48.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1581426320
Short name T1364
Test name
Test status
Simulation time 230388912 ps
CPU time 1.71 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 207684 kb
Host smart-9e70ef44-2635-4717-8e1c-583134907e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15814
26320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1581426320
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.888944882
Short name T1318
Test name
Test status
Simulation time 221036786 ps
CPU time 1.19 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 215888 kb
Host smart-818ab135-5cdb-4d4b-a543-94ecef27177d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=888944882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.888944882
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.33858517
Short name T3225
Test name
Test status
Simulation time 150643270 ps
CPU time 0.86 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:40:49 PM PDT 24
Peak memory 207480 kb
Host smart-7f3c5ce7-5e7c-4c8b-b56c-035f273ba0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33858
517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.33858517
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.864424984
Short name T977
Test name
Test status
Simulation time 202351358 ps
CPU time 0.93 seconds
Started Aug 13 06:40:54 PM PDT 24
Finished Aug 13 06:40:55 PM PDT 24
Peak memory 207544 kb
Host smart-5757e788-778a-4b28-a2e5-c76b88df084d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86442
4984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.864424984
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1926692864
Short name T3221
Test name
Test status
Simulation time 3655489208 ps
CPU time 102.51 seconds
Started Aug 13 06:40:43 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 218312 kb
Host smart-2f73f092-a842-47f1-9ab7-40156b4c8c11
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1926692864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1926692864
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.3020209551
Short name T3475
Test name
Test status
Simulation time 9843070148 ps
CPU time 62.57 seconds
Started Aug 13 06:40:52 PM PDT 24
Finished Aug 13 06:41:55 PM PDT 24
Peak memory 207828 kb
Host smart-fd5f9841-d863-4cb2-a170-93bbbb9f4f04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3020209551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.3020209551
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3480212503
Short name T2479
Test name
Test status
Simulation time 208680773 ps
CPU time 0.92 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:40:47 PM PDT 24
Peak memory 207584 kb
Host smart-0be01120-d616-4696-b683-ce398fd7d312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
12503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3480212503
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2863304370
Short name T2414
Test name
Test status
Simulation time 27880201175 ps
CPU time 43.64 seconds
Started Aug 13 06:40:53 PM PDT 24
Finished Aug 13 06:41:36 PM PDT 24
Peak memory 207852 kb
Host smart-b70fd16b-28d3-4dc6-8dae-e202a5a59bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28633
04370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2863304370
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1301476965
Short name T592
Test name
Test status
Simulation time 6102054771 ps
CPU time 9.06 seconds
Started Aug 13 06:40:56 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 216232 kb
Host smart-e11148db-63da-4bbc-89d4-fe84a511b6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13014
76965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1301476965
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1953497964
Short name T1020
Test name
Test status
Simulation time 2981416728 ps
CPU time 28.62 seconds
Started Aug 13 06:40:53 PM PDT 24
Finished Aug 13 06:41:22 PM PDT 24
Peak memory 216020 kb
Host smart-6c9a1732-1f17-4a13-9d96-575187fbde0a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1953497964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1953497964
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2960548706
Short name T3000
Test name
Test status
Simulation time 2345029361 ps
CPU time 17.62 seconds
Started Aug 13 06:40:51 PM PDT 24
Finished Aug 13 06:41:08 PM PDT 24
Peak memory 217536 kb
Host smart-ae3747b5-512b-4790-a25f-cb64ea308ee6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2960548706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2960548706
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1936410993
Short name T1579
Test name
Test status
Simulation time 295736007 ps
CPU time 1.07 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207520 kb
Host smart-2e016171-2b02-47b5-9920-2452308e4df3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1936410993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1936410993
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2748241172
Short name T2998
Test name
Test status
Simulation time 187955268 ps
CPU time 0.92 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:40:41 PM PDT 24
Peak memory 207492 kb
Host smart-26d23227-8b76-44c7-be1f-c7617816c2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27482
41172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2748241172
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.4166135120
Short name T2638
Test name
Test status
Simulation time 1593526348 ps
CPU time 11.55 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:40:57 PM PDT 24
Peak memory 217400 kb
Host smart-dd9db989-8526-4a3d-b463-0194bb7b6848
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4166135120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.4166135120
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2947277862
Short name T552
Test name
Test status
Simulation time 147303826 ps
CPU time 0.85 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:40:47 PM PDT 24
Peak memory 207468 kb
Host smart-47052ea2-f217-4505-a744-7ff716a0a074
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2947277862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2947277862
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3986747831
Short name T1897
Test name
Test status
Simulation time 199374982 ps
CPU time 0.95 seconds
Started Aug 13 06:40:55 PM PDT 24
Finished Aug 13 06:40:56 PM PDT 24
Peak memory 207536 kb
Host smart-413d7210-5c5c-45de-aa02-4a1cbc68ed25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39867
47831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3986747831
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3600179461
Short name T976
Test name
Test status
Simulation time 183364100 ps
CPU time 0.92 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:40:59 PM PDT 24
Peak memory 207496 kb
Host smart-c492d5e0-24f8-477a-b0e5-d4dd33ea93d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36001
79461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3600179461
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2222905229
Short name T542
Test name
Test status
Simulation time 200449625 ps
CPU time 0.9 seconds
Started Aug 13 06:40:42 PM PDT 24
Finished Aug 13 06:40:43 PM PDT 24
Peak memory 207504 kb
Host smart-4bd1ae74-aa6f-4677-abbe-f43465b0bf5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22229
05229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2222905229
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1863243035
Short name T1581
Test name
Test status
Simulation time 227618279 ps
CPU time 0.97 seconds
Started Aug 13 06:40:44 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 207496 kb
Host smart-02ec9bd0-7961-4e27-b803-b762d7b486fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18632
43035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1863243035
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.806009212
Short name T3469
Test name
Test status
Simulation time 179359910 ps
CPU time 0.9 seconds
Started Aug 13 06:40:44 PM PDT 24
Finished Aug 13 06:40:45 PM PDT 24
Peak memory 207452 kb
Host smart-4cbdfcb9-da0e-4a3b-826d-50cc6cfa6026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80600
9212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.806009212
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1882977411
Short name T198
Test name
Test status
Simulation time 159171569 ps
CPU time 0.9 seconds
Started Aug 13 06:40:49 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 207584 kb
Host smart-9c229f2a-c16f-402d-9cd8-fb4fad764d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18829
77411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1882977411
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3684478300
Short name T1093
Test name
Test status
Simulation time 226102264 ps
CPU time 1.09 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:40:43 PM PDT 24
Peak memory 207532 kb
Host smart-1dc1d905-1962-4c68-958e-1f8587a1eb19
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3684478300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3684478300
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2390908531
Short name T2746
Test name
Test status
Simulation time 187966784 ps
CPU time 0.84 seconds
Started Aug 13 06:40:54 PM PDT 24
Finished Aug 13 06:40:55 PM PDT 24
Peak memory 207436 kb
Host smart-ff58d7f2-15f4-49df-8434-1054137606a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
08531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2390908531
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2302858442
Short name T684
Test name
Test status
Simulation time 39677235 ps
CPU time 0.7 seconds
Started Aug 13 06:40:39 PM PDT 24
Finished Aug 13 06:40:40 PM PDT 24
Peak memory 207536 kb
Host smart-3103186d-19cd-4fcb-aa78-8bfad811910d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23028
58442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2302858442
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1015776644
Short name T296
Test name
Test status
Simulation time 22252617733 ps
CPU time 60.97 seconds
Started Aug 13 06:40:56 PM PDT 24
Finished Aug 13 06:42:02 PM PDT 24
Peak memory 224148 kb
Host smart-ea3d18b9-e6ec-44bd-8338-3377524c549b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157
76644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1015776644
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2600149344
Short name T1636
Test name
Test status
Simulation time 153843739 ps
CPU time 0.84 seconds
Started Aug 13 06:40:56 PM PDT 24
Finished Aug 13 06:40:57 PM PDT 24
Peak memory 207620 kb
Host smart-1eec5d4d-2bd4-4c9f-b680-9b1fed452d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26001
49344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2600149344
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.614107782
Short name T3402
Test name
Test status
Simulation time 223158429 ps
CPU time 0.98 seconds
Started Aug 13 06:40:44 PM PDT 24
Finished Aug 13 06:40:45 PM PDT 24
Peak memory 207504 kb
Host smart-80c83810-c558-4826-82ef-fbf679b2a363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61410
7782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.614107782
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.3590165269
Short name T3130
Test name
Test status
Simulation time 221408970 ps
CPU time 0.99 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:40:59 PM PDT 24
Peak memory 207536 kb
Host smart-69742120-9860-409e-92f7-30d89e8e0092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35901
65269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.3590165269
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.569190381
Short name T836
Test name
Test status
Simulation time 180082230 ps
CPU time 0.94 seconds
Started Aug 13 06:40:44 PM PDT 24
Finished Aug 13 06:40:45 PM PDT 24
Peak memory 207432 kb
Host smart-ebddca3f-3657-4e63-aea9-1132a6dc511e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56919
0381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.569190381
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3703192432
Short name T1223
Test name
Test status
Simulation time 187126795 ps
CPU time 0.97 seconds
Started Aug 13 06:40:45 PM PDT 24
Finished Aug 13 06:40:46 PM PDT 24
Peak memory 207516 kb
Host smart-7b2a6309-7e44-48c8-a185-70d16a793c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37031
92432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3703192432
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_rx_full.788866513
Short name T2570
Test name
Test status
Simulation time 256733125 ps
CPU time 1.15 seconds
Started Aug 13 06:40:44 PM PDT 24
Finished Aug 13 06:40:45 PM PDT 24
Peak memory 207448 kb
Host smart-254695ac-cc23-4a97-bc51-5f959c7df488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78886
6513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.788866513
Directory /workspace/48.usbdev_rx_full/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1647068214
Short name T544
Test name
Test status
Simulation time 152154416 ps
CPU time 0.85 seconds
Started Aug 13 06:40:54 PM PDT 24
Finished Aug 13 06:40:55 PM PDT 24
Peak memory 207572 kb
Host smart-0b5174a9-a59a-4fa9-ba48-e8c8b5fcb785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16470
68214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1647068214
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3155212050
Short name T819
Test name
Test status
Simulation time 214253940 ps
CPU time 0.91 seconds
Started Aug 13 06:40:51 PM PDT 24
Finished Aug 13 06:40:52 PM PDT 24
Peak memory 207524 kb
Host smart-f864f160-8f87-46dc-87a9-95c7dd11ef54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31552
12050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3155212050
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2538131639
Short name T1651
Test name
Test status
Simulation time 219589511 ps
CPU time 1 seconds
Started Aug 13 06:40:51 PM PDT 24
Finished Aug 13 06:40:52 PM PDT 24
Peak memory 207524 kb
Host smart-27644213-af98-4334-886b-2659a57f437e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25381
31639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2538131639
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.3241615816
Short name T3081
Test name
Test status
Simulation time 1760909709 ps
CPU time 49.31 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 224080 kb
Host smart-90e4b999-6a73-43b6-a3b0-30688e46dd8b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3241615816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.3241615816
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.4019853994
Short name T2434
Test name
Test status
Simulation time 203245202 ps
CPU time 0.99 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207512 kb
Host smart-2dfa0336-f808-49c3-be3a-08e791ccf255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40198
53994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.4019853994
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2033679867
Short name T2046
Test name
Test status
Simulation time 182092038 ps
CPU time 0.91 seconds
Started Aug 13 06:40:52 PM PDT 24
Finished Aug 13 06:40:53 PM PDT 24
Peak memory 207576 kb
Host smart-8f390bb4-fd7e-4a59-a3f5-b9a5bf300576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20336
79867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2033679867
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.2319666891
Short name T2948
Test name
Test status
Simulation time 939694801 ps
CPU time 2.45 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:40:43 PM PDT 24
Peak memory 207752 kb
Host smart-1eb9ea9b-ff30-4193-8563-c1bec1e3efdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23196
66891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2319666891
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1327972787
Short name T3534
Test name
Test status
Simulation time 2588551587 ps
CPU time 25.23 seconds
Started Aug 13 06:40:52 PM PDT 24
Finished Aug 13 06:41:17 PM PDT 24
Peak memory 217592 kb
Host smart-3d807a17-ec00-4046-92dc-20086f977b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13279
72787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1327972787
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.3296769886
Short name T49
Test name
Test status
Simulation time 2909999917 ps
CPU time 19.79 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:41:08 PM PDT 24
Peak memory 207768 kb
Host smart-98f0e7cd-6e3b-47b4-bab1-60d89f3ad1d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296769886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.3296769886
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_tx_rx_disruption.1556062733
Short name T2188
Test name
Test status
Simulation time 489541741 ps
CPU time 1.45 seconds
Started Aug 13 06:40:52 PM PDT 24
Finished Aug 13 06:40:54 PM PDT 24
Peak memory 207608 kb
Host smart-5a108248-2355-4b00-a657-c679884cc498
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556062733 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.usbdev_tx_rx_disruption.1556062733
Directory /workspace/48.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/480.usbdev_tx_rx_disruption.1483562855
Short name T524
Test name
Test status
Simulation time 569051551 ps
CPU time 1.55 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207608 kb
Host smart-98b70994-fddf-49b7-8630-ff0a29652403
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483562855 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 480.usbdev_tx_rx_disruption.1483562855
Directory /workspace/480.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/481.usbdev_tx_rx_disruption.387647554
Short name T781
Test name
Test status
Simulation time 497020588 ps
CPU time 1.64 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 207616 kb
Host smart-27c95dac-53e2-4af1-8151-400f17399b72
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387647554 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 481.usbdev_tx_rx_disruption.387647554
Directory /workspace/481.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/482.usbdev_tx_rx_disruption.3585095634
Short name T1528
Test name
Test status
Simulation time 559421176 ps
CPU time 1.63 seconds
Started Aug 13 06:42:42 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 207560 kb
Host smart-1c69c18b-4401-4501-b32a-bd463c110277
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585095634 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 482.usbdev_tx_rx_disruption.3585095634
Directory /workspace/482.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/483.usbdev_tx_rx_disruption.2301787591
Short name T1109
Test name
Test status
Simulation time 493200545 ps
CPU time 1.48 seconds
Started Aug 13 06:42:16 PM PDT 24
Finished Aug 13 06:42:18 PM PDT 24
Peak memory 207608 kb
Host smart-1f04377d-67be-422e-93c3-6de4866fdb20
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301787591 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 483.usbdev_tx_rx_disruption.2301787591
Directory /workspace/483.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/485.usbdev_tx_rx_disruption.3791154223
Short name T594
Test name
Test status
Simulation time 528274679 ps
CPU time 1.74 seconds
Started Aug 13 06:42:37 PM PDT 24
Finished Aug 13 06:42:39 PM PDT 24
Peak memory 207608 kb
Host smart-0a3ee295-54b0-4b27-9bf4-e0ea54dd3c1a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791154223 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 485.usbdev_tx_rx_disruption.3791154223
Directory /workspace/485.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/486.usbdev_tx_rx_disruption.1195212313
Short name T1604
Test name
Test status
Simulation time 644671302 ps
CPU time 1.69 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 207608 kb
Host smart-9039f1f5-f916-484f-93e5-24037ec46a05
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195212313 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 486.usbdev_tx_rx_disruption.1195212313
Directory /workspace/486.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/487.usbdev_tx_rx_disruption.3935890679
Short name T1338
Test name
Test status
Simulation time 497069311 ps
CPU time 1.58 seconds
Started Aug 13 06:42:37 PM PDT 24
Finished Aug 13 06:42:39 PM PDT 24
Peak memory 207608 kb
Host smart-7e23bf51-a744-4193-8836-950b3aeca859
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935890679 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 487.usbdev_tx_rx_disruption.3935890679
Directory /workspace/487.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/488.usbdev_tx_rx_disruption.3136532174
Short name T2247
Test name
Test status
Simulation time 445019273 ps
CPU time 1.45 seconds
Started Aug 13 06:42:08 PM PDT 24
Finished Aug 13 06:42:10 PM PDT 24
Peak memory 207468 kb
Host smart-b51182b0-28af-4f1e-8b8e-a581b39e40af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136532174 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 488.usbdev_tx_rx_disruption.3136532174
Directory /workspace/488.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/489.usbdev_tx_rx_disruption.4277157536
Short name T2611
Test name
Test status
Simulation time 518694466 ps
CPU time 1.52 seconds
Started Aug 13 06:42:44 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 207560 kb
Host smart-345fac58-8c77-4d3a-8b8e-9f125618e19c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277157536 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 489.usbdev_tx_rx_disruption.4277157536
Directory /workspace/489.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3487247944
Short name T1045
Test name
Test status
Simulation time 61928202 ps
CPU time 0.73 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 207496 kb
Host smart-a34c4145-3254-4457-8709-a60eb89b03e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3487247944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3487247944
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2482670996
Short name T3118
Test name
Test status
Simulation time 9766590031 ps
CPU time 12.37 seconds
Started Aug 13 06:40:45 PM PDT 24
Finished Aug 13 06:40:58 PM PDT 24
Peak memory 207856 kb
Host smart-2df201a3-4468-4694-ad97-2e07ac642717
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482670996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.2482670996
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2376650314
Short name T1742
Test name
Test status
Simulation time 15793958211 ps
CPU time 17.81 seconds
Started Aug 13 06:40:44 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 215992 kb
Host smart-2598ee1c-8b5c-4f03-9049-5f8f59a0b734
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376650314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2376650314
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.2626518127
Short name T1035
Test name
Test status
Simulation time 30601600957 ps
CPU time 39.18 seconds
Started Aug 13 06:40:35 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207708 kb
Host smart-b79d05ea-4a54-4886-9a10-588fadce88cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626518127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.2626518127
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3012050233
Short name T949
Test name
Test status
Simulation time 156873485 ps
CPU time 0.82 seconds
Started Aug 13 06:40:49 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 207528 kb
Host smart-c4b04ee0-6bf6-4021-bda4-a8073d141d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30120
50233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3012050233
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.562725361
Short name T3445
Test name
Test status
Simulation time 152738376 ps
CPU time 0.87 seconds
Started Aug 13 06:40:47 PM PDT 24
Finished Aug 13 06:40:48 PM PDT 24
Peak memory 207536 kb
Host smart-a95ba5e5-5a9d-452f-8735-5591d79c3345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56272
5361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.562725361
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.4070930938
Short name T3016
Test name
Test status
Simulation time 660834737 ps
CPU time 2 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 207500 kb
Host smart-5f78b902-49e3-4fc0-ac19-c47e7a5cad4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40709
30938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.4070930938
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3502280240
Short name T109
Test name
Test status
Simulation time 1041380469 ps
CPU time 2.55 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207708 kb
Host smart-4dba2d95-9705-4bf9-93e3-dc3bf4b1ee56
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3502280240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3502280240
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2531011047
Short name T516
Test name
Test status
Simulation time 29278315269 ps
CPU time 45.83 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:47 PM PDT 24
Peak memory 207868 kb
Host smart-20015d30-efeb-4c82-a182-c28689764653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25310
11047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2531011047
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.2174906209
Short name T2462
Test name
Test status
Simulation time 1595113725 ps
CPU time 13.66 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 207816 kb
Host smart-9685d60a-148a-4b34-9651-abf0457c9b73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174906209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.2174906209
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1095270426
Short name T787
Test name
Test status
Simulation time 466358887 ps
CPU time 1.49 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:40:43 PM PDT 24
Peak memory 207500 kb
Host smart-56a6f78a-9a2a-4a9e-abe9-002113898b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10952
70426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1095270426
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.15366783
Short name T2308
Test name
Test status
Simulation time 150822755 ps
CPU time 0.81 seconds
Started Aug 13 06:40:49 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 207412 kb
Host smart-d954beb7-922f-4e58-8779-eee3a7e08451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15366
783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.15366783
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.4101985610
Short name T1718
Test name
Test status
Simulation time 39794199 ps
CPU time 0.74 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207460 kb
Host smart-f88630b8-1b7a-466d-93dc-3641b8e36bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41019
85610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.4101985610
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1870244078
Short name T2284
Test name
Test status
Simulation time 900764255 ps
CPU time 2.35 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:40:51 PM PDT 24
Peak memory 207820 kb
Host smart-e2ad1283-436f-4adf-894b-0a6f48ccd904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702
44078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1870244078
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_types.3046553050
Short name T398
Test name
Test status
Simulation time 627425247 ps
CPU time 1.57 seconds
Started Aug 13 06:40:54 PM PDT 24
Finished Aug 13 06:40:55 PM PDT 24
Peak memory 207576 kb
Host smart-c7f6d887-83d1-4ec3-849c-aeacdb66ecd2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3046553050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.3046553050
Directory /workspace/49.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1294542987
Short name T2306
Test name
Test status
Simulation time 181361264 ps
CPU time 2.24 seconds
Started Aug 13 06:40:55 PM PDT 24
Finished Aug 13 06:40:57 PM PDT 24
Peak memory 207708 kb
Host smart-764aa261-e337-4873-86f0-ae94f90125bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12945
42987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1294542987
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3805435547
Short name T585
Test name
Test status
Simulation time 217878927 ps
CPU time 1.07 seconds
Started Aug 13 06:40:57 PM PDT 24
Finished Aug 13 06:40:58 PM PDT 24
Peak memory 215892 kb
Host smart-4a081d26-1e3c-42ef-8333-0a9649318046
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3805435547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3805435547
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1081916376
Short name T913
Test name
Test status
Simulation time 195994870 ps
CPU time 0.87 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207468 kb
Host smart-ebb0a56b-937f-47c5-81c9-8b5cf5b935f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10819
16376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1081916376
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1239612131
Short name T2145
Test name
Test status
Simulation time 161689413 ps
CPU time 0.91 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207388 kb
Host smart-b0e0de1f-978c-44c5-a33c-6b0a34bc855d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12396
12131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1239612131
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1840429425
Short name T857
Test name
Test status
Simulation time 4311779225 ps
CPU time 122.55 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 215984 kb
Host smart-d8ec2e7b-93db-443e-8bb0-5a57873f50a0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1840429425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1840429425
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.3864679464
Short name T1453
Test name
Test status
Simulation time 7342088330 ps
CPU time 98.61 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:42:40 PM PDT 24
Peak memory 207796 kb
Host smart-face4e5e-f4c6-406b-be83-a6e5f80df910
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3864679464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.3864679464
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.455016056
Short name T2026
Test name
Test status
Simulation time 190395227 ps
CPU time 0.92 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207496 kb
Host smart-b494181a-a041-455b-9c55-88cee7f580b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45501
6056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.455016056
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1718764208
Short name T2491
Test name
Test status
Simulation time 32904748646 ps
CPU time 49.43 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:52 PM PDT 24
Peak memory 207860 kb
Host smart-8851b54b-62e6-47fa-9d7a-bff88ec01f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17187
64208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1718764208
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1256158104
Short name T3505
Test name
Test status
Simulation time 3270616485 ps
CPU time 6.32 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:08 PM PDT 24
Peak memory 207736 kb
Host smart-1d31a547-426c-496b-9a54-4cecf32669a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12561
58104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1256158104
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1011100171
Short name T960
Test name
Test status
Simulation time 5111777323 ps
CPU time 52.44 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:53 PM PDT 24
Peak memory 215988 kb
Host smart-2d0da4c8-305a-435a-bafc-2e5226b89da6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1011100171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1011100171
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3455156402
Short name T3098
Test name
Test status
Simulation time 2503524970 ps
CPU time 72.95 seconds
Started Aug 13 06:40:47 PM PDT 24
Finished Aug 13 06:42:00 PM PDT 24
Peak memory 215892 kb
Host smart-7586e4a2-0e5b-4e8d-83c8-7962a395fe48
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3455156402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3455156402
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1198949561
Short name T2044
Test name
Test status
Simulation time 236446297 ps
CPU time 1.02 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207448 kb
Host smart-9d1de312-8eb3-49c2-bf13-91f665a58c0a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1198949561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1198949561
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.197759755
Short name T1144
Test name
Test status
Simulation time 219615124 ps
CPU time 0.96 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207528 kb
Host smart-71d06ec3-a34e-4432-b393-e6f558a4cdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19775
9755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.197759755
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.4245117291
Short name T779
Test name
Test status
Simulation time 2721499591 ps
CPU time 27.48 seconds
Started Aug 13 06:40:51 PM PDT 24
Finished Aug 13 06:41:19 PM PDT 24
Peak memory 217672 kb
Host smart-25df2721-482a-41d1-8074-6b8b5f4333fa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4245117291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.4245117291
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.2719017829
Short name T1747
Test name
Test status
Simulation time 189406343 ps
CPU time 0.91 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:40:47 PM PDT 24
Peak memory 207412 kb
Host smart-fadf1e82-d839-47f9-8066-efad53a3bd50
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2719017829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.2719017829
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.4094405682
Short name T3440
Test name
Test status
Simulation time 150212587 ps
CPU time 0.82 seconds
Started Aug 13 06:40:52 PM PDT 24
Finished Aug 13 06:40:53 PM PDT 24
Peak memory 207512 kb
Host smart-1703dc77-2305-497f-ad58-7499261a8367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
05682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.4094405682
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2719394431
Short name T125
Test name
Test status
Simulation time 174305521 ps
CPU time 0.85 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207516 kb
Host smart-09cee6e1-1b35-48ea-bd36-432b430eec01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27193
94431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2719394431
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.955010477
Short name T822
Test name
Test status
Simulation time 149028500 ps
CPU time 0.85 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207532 kb
Host smart-eda003f3-09c1-48d7-adbe-8b8f8fabdaf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95501
0477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.955010477
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3462485791
Short name T1358
Test name
Test status
Simulation time 181868947 ps
CPU time 0.95 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:40:49 PM PDT 24
Peak memory 207412 kb
Host smart-f37e11bb-f2a0-4040-969c-2977e746bb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34624
85791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3462485791
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2353168609
Short name T855
Test name
Test status
Simulation time 168846843 ps
CPU time 0.89 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207584 kb
Host smart-d509a4e1-4f06-4be3-ab01-1812b9583bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23531
68609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2353168609
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3955510938
Short name T1212
Test name
Test status
Simulation time 186171911 ps
CPU time 0.91 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 207552 kb
Host smart-d8149755-1f38-47a4-ad34-ea72a57dd37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39555
10938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3955510938
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.4090466969
Short name T3618
Test name
Test status
Simulation time 237085669 ps
CPU time 0.97 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207600 kb
Host smart-b4ee58c0-f690-4224-84fa-723199977469
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4090466969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.4090466969
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2249742198
Short name T1678
Test name
Test status
Simulation time 193793238 ps
CPU time 0.91 seconds
Started Aug 13 06:41:19 PM PDT 24
Finished Aug 13 06:41:20 PM PDT 24
Peak memory 207420 kb
Host smart-1ed95f1e-07e5-40f3-9d29-7199c9a74ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
42198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2249742198
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3662173259
Short name T1658
Test name
Test status
Simulation time 53114512 ps
CPU time 0.71 seconds
Started Aug 13 06:40:47 PM PDT 24
Finished Aug 13 06:40:48 PM PDT 24
Peak memory 207564 kb
Host smart-6c17466b-6dc3-4a2f-aea7-c7587a589893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36621
73259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3662173259
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2512614577
Short name T3168
Test name
Test status
Simulation time 8223579981 ps
CPU time 23.44 seconds
Started Aug 13 06:40:48 PM PDT 24
Finished Aug 13 06:41:12 PM PDT 24
Peak memory 220716 kb
Host smart-8f40b48b-dd96-426d-acef-39051e2d901f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25126
14577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2512614577
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1307657689
Short name T3235
Test name
Test status
Simulation time 180836481 ps
CPU time 0.93 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207600 kb
Host smart-318eb63e-4641-4bef-9c8d-00aa88100ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13076
57689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1307657689
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1598082833
Short name T1101
Test name
Test status
Simulation time 175258972 ps
CPU time 0.86 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207520 kb
Host smart-ae0bb1c1-e3b0-4c66-a01b-99b3fc685685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15980
82833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1598082833
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.2088749590
Short name T3380
Test name
Test status
Simulation time 258295993 ps
CPU time 1 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207548 kb
Host smart-a5e0d0ae-5f89-4782-9f5f-04018ba2f2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20887
49590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.2088749590
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3346614316
Short name T765
Test name
Test status
Simulation time 151432930 ps
CPU time 0.85 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207396 kb
Host smart-e190bae6-10c0-4dc5-996f-302488e3d8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33466
14316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3346614316
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.137488420
Short name T3298
Test name
Test status
Simulation time 224448870 ps
CPU time 0.95 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207476 kb
Host smart-d0a74d18-4e32-43b2-adb1-d514e4d9af0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13748
8420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.137488420
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_rx_full.3947449275
Short name T3620
Test name
Test status
Simulation time 409466083 ps
CPU time 1.44 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207488 kb
Host smart-e256471e-4ed7-41cb-8a72-cfe3d2afd52e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39474
49275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.3947449275
Directory /workspace/49.usbdev_rx_full/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.802931988
Short name T1866
Test name
Test status
Simulation time 157537632 ps
CPU time 0.85 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207500 kb
Host smart-868df1b0-2e86-4359-a0dd-a8926f348c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80293
1988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.802931988
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1788707492
Short name T2990
Test name
Test status
Simulation time 148109036 ps
CPU time 0.87 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207392 kb
Host smart-7737e9a4-c1b9-4775-9dd5-dc1931114291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17887
07492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1788707492
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1357649662
Short name T1675
Test name
Test status
Simulation time 212483695 ps
CPU time 1.02 seconds
Started Aug 13 06:40:51 PM PDT 24
Finished Aug 13 06:40:52 PM PDT 24
Peak memory 207488 kb
Host smart-e9be0e57-c1d8-44bd-8b8b-dd908fc31d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13576
49662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1357649662
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.2584855303
Short name T2755
Test name
Test status
Simulation time 2268626861 ps
CPU time 21.84 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:41:19 PM PDT 24
Peak memory 224068 kb
Host smart-e5e76260-3f57-4646-b8c3-a1046707ff1b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2584855303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.2584855303
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.992490417
Short name T799
Test name
Test status
Simulation time 181317800 ps
CPU time 0.88 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 207524 kb
Host smart-6798923e-d2a3-48a5-8807-439c3d56c554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99249
0417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.992490417
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2453179156
Short name T3229
Test name
Test status
Simulation time 204845007 ps
CPU time 1.01 seconds
Started Aug 13 06:40:49 PM PDT 24
Finished Aug 13 06:40:50 PM PDT 24
Peak memory 207600 kb
Host smart-da2b6b4a-7aa8-4d84-ae5e-5f44cbdf920d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24531
79156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2453179156
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.163991225
Short name T1309
Test name
Test status
Simulation time 1098759487 ps
CPU time 2.73 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207692 kb
Host smart-97fe25e1-00ba-4b1f-8b98-315fc8480843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16399
1225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.163991225
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1248805788
Short name T161
Test name
Test status
Simulation time 1418188924 ps
CPU time 40.34 seconds
Started Aug 13 06:40:56 PM PDT 24
Finished Aug 13 06:41:37 PM PDT 24
Peak memory 215972 kb
Host smart-52fb7214-1748-460c-bef9-c35c5ef689a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12488
05788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1248805788
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.473189432
Short name T3476
Test name
Test status
Simulation time 4333556725 ps
CPU time 29.76 seconds
Started Aug 13 06:40:41 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207648 kb
Host smart-20c2032c-dae1-42ea-b274-eff8fb72b41b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473189432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_host
_handshake.473189432
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_tx_rx_disruption.2894373417
Short name T3265
Test name
Test status
Simulation time 549364011 ps
CPU time 1.66 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207464 kb
Host smart-041641df-fa35-4a34-ba1e-40271bdabdf1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894373417 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.usbdev_tx_rx_disruption.2894373417
Directory /workspace/49.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/490.usbdev_tx_rx_disruption.406713482
Short name T3323
Test name
Test status
Simulation time 500802238 ps
CPU time 1.56 seconds
Started Aug 13 06:42:34 PM PDT 24
Finished Aug 13 06:42:35 PM PDT 24
Peak memory 207560 kb
Host smart-5513dee1-a5dd-414b-8e03-bf6aea8d15a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406713482 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 490.usbdev_tx_rx_disruption.406713482
Directory /workspace/490.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/491.usbdev_tx_rx_disruption.36323747
Short name T824
Test name
Test status
Simulation time 674781023 ps
CPU time 1.81 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 207624 kb
Host smart-2235aba1-bea6-490f-9251-4a5b485389a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36323747 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 491.usbdev_tx_rx_disruption.36323747
Directory /workspace/491.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/492.usbdev_tx_rx_disruption.810511519
Short name T1071
Test name
Test status
Simulation time 591061713 ps
CPU time 1.72 seconds
Started Aug 13 06:42:35 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 207560 kb
Host smart-bc80479e-f73b-4cde-b046-28d53af5c1b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810511519 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 492.usbdev_tx_rx_disruption.810511519
Directory /workspace/492.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/493.usbdev_tx_rx_disruption.4160556257
Short name T1192
Test name
Test status
Simulation time 552770316 ps
CPU time 1.48 seconds
Started Aug 13 06:42:37 PM PDT 24
Finished Aug 13 06:42:39 PM PDT 24
Peak memory 206456 kb
Host smart-bdf1c7b8-54db-4b32-a8cb-dceaa750e6e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160556257 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 493.usbdev_tx_rx_disruption.4160556257
Directory /workspace/493.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/494.usbdev_tx_rx_disruption.4034277227
Short name T194
Test name
Test status
Simulation time 474290218 ps
CPU time 1.49 seconds
Started Aug 13 06:42:34 PM PDT 24
Finished Aug 13 06:42:36 PM PDT 24
Peak memory 206456 kb
Host smart-2f238e84-d00b-402e-a79c-63bc29f69937
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034277227 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 494.usbdev_tx_rx_disruption.4034277227
Directory /workspace/494.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/495.usbdev_tx_rx_disruption.1673139381
Short name T3095
Test name
Test status
Simulation time 538279969 ps
CPU time 1.54 seconds
Started Aug 13 06:42:38 PM PDT 24
Finished Aug 13 06:42:40 PM PDT 24
Peak memory 206456 kb
Host smart-8c551daa-bec9-441f-97bd-65f6a243b58c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673139381 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 495.usbdev_tx_rx_disruption.1673139381
Directory /workspace/495.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/496.usbdev_tx_rx_disruption.3741643890
Short name T264
Test name
Test status
Simulation time 502649122 ps
CPU time 1.54 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 207608 kb
Host smart-6bfc5179-1acb-48cb-a84f-caad60ebdb63
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741643890 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 496.usbdev_tx_rx_disruption.3741643890
Directory /workspace/496.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/497.usbdev_tx_rx_disruption.3872174177
Short name T1519
Test name
Test status
Simulation time 440382577 ps
CPU time 1.41 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 206456 kb
Host smart-67b3c238-c142-4285-b823-d6ab2c5d9f35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872174177 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 497.usbdev_tx_rx_disruption.3872174177
Directory /workspace/497.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/498.usbdev_tx_rx_disruption.1042016826
Short name T3002
Test name
Test status
Simulation time 593540740 ps
CPU time 1.63 seconds
Started Aug 13 06:42:13 PM PDT 24
Finished Aug 13 06:42:14 PM PDT 24
Peak memory 207532 kb
Host smart-84b5b246-6629-4912-9b11-f2814c3e2fcf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042016826 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 498.usbdev_tx_rx_disruption.1042016826
Directory /workspace/498.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/499.usbdev_tx_rx_disruption.3941056839
Short name T801
Test name
Test status
Simulation time 532153459 ps
CPU time 1.62 seconds
Started Aug 13 06:42:15 PM PDT 24
Finished Aug 13 06:42:16 PM PDT 24
Peak memory 207608 kb
Host smart-9609bb13-1f48-4783-b36c-472c91d22a80
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941056839 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 499.usbdev_tx_rx_disruption.3941056839
Directory /workspace/499.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2845963990
Short name T2759
Test name
Test status
Simulation time 38616518 ps
CPU time 0.67 seconds
Started Aug 13 06:34:18 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 207460 kb
Host smart-4fd063d4-24ef-4e70-a646-9a51335b12f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2845963990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2845963990
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1012242343
Short name T1023
Test name
Test status
Simulation time 11845543606 ps
CPU time 16.3 seconds
Started Aug 13 06:34:13 PM PDT 24
Finished Aug 13 06:34:29 PM PDT 24
Peak memory 207764 kb
Host smart-a05b7049-2082-4cf2-8da4-a9717da1d4d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012242343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.1012242343
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3416086227
Short name T712
Test name
Test status
Simulation time 16376754191 ps
CPU time 19.21 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:28 PM PDT 24
Peak memory 215944 kb
Host smart-3e59af15-fcc3-4b2f-9da4-1b2d40cce575
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416086227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3416086227
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1855453411
Short name T93
Test name
Test status
Simulation time 25676512597 ps
CPU time 38.99 seconds
Started Aug 13 06:34:06 PM PDT 24
Finished Aug 13 06:34:46 PM PDT 24
Peak memory 215988 kb
Host smart-d7c35027-6ed8-4024-8995-6c707c3f1fe0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855453411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.1855453411
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1425808484
Short name T2149
Test name
Test status
Simulation time 176217264 ps
CPU time 0.89 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:09 PM PDT 24
Peak memory 207456 kb
Host smart-98695e9f-4121-48bd-8521-8c620da6aa1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14258
08484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1425808484
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.1206451776
Short name T1652
Test name
Test status
Simulation time 181243818 ps
CPU time 0.92 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:09 PM PDT 24
Peak memory 207568 kb
Host smart-ea3cab5b-e357-4692-86d9-f59928863a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12064
51776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.1206451776
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.999512500
Short name T1614
Test name
Test status
Simulation time 316099246 ps
CPU time 1.35 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:09 PM PDT 24
Peak memory 207584 kb
Host smart-26b91206-432c-4763-96a3-ec7feb1b2518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99951
2500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.999512500
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.146562591
Short name T346
Test name
Test status
Simulation time 1255935334 ps
CPU time 3.66 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:13 PM PDT 24
Peak memory 207724 kb
Host smart-c4b5191a-1509-4610-be9a-c26322fa4c3c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=146562591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.146562591
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3048871082
Short name T1792
Test name
Test status
Simulation time 21279750012 ps
CPU time 33.8 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 207820 kb
Host smart-99372438-941a-4511-9e45-810baa065498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
71082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3048871082
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.3675487020
Short name T1312
Test name
Test status
Simulation time 3400097900 ps
CPU time 30.23 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:38 PM PDT 24
Peak memory 207836 kb
Host smart-8dd4d93f-1bc5-4c77-8f42-82abc2980166
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675487020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3675487020
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3103668242
Short name T969
Test name
Test status
Simulation time 504155694 ps
CPU time 1.55 seconds
Started Aug 13 06:34:10 PM PDT 24
Finished Aug 13 06:34:12 PM PDT 24
Peak memory 207404 kb
Host smart-1d144195-f943-40ad-ab2a-3e97ea7cf62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31036
68242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3103668242
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3969481663
Short name T1475
Test name
Test status
Simulation time 144370428 ps
CPU time 0.81 seconds
Started Aug 13 06:34:10 PM PDT 24
Finished Aug 13 06:34:11 PM PDT 24
Peak memory 207664 kb
Host smart-3387c32f-e059-434f-af8e-6c7a9c7b2916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39694
81663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3969481663
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.3746731536
Short name T1092
Test name
Test status
Simulation time 48924568 ps
CPU time 0.75 seconds
Started Aug 13 06:34:13 PM PDT 24
Finished Aug 13 06:34:14 PM PDT 24
Peak memory 207420 kb
Host smart-2ce42ace-3278-4ce2-8655-e418a75aa013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37467
31536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3746731536
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.908135052
Short name T1078
Test name
Test status
Simulation time 916754143 ps
CPU time 2.37 seconds
Started Aug 13 06:34:10 PM PDT 24
Finished Aug 13 06:34:12 PM PDT 24
Peak memory 207820 kb
Host smart-ea2fd9be-967a-461b-805d-f51bf1734082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90813
5052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.908135052
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_types.962022757
Short name T483
Test name
Test status
Simulation time 202023486 ps
CPU time 0.91 seconds
Started Aug 13 06:34:10 PM PDT 24
Finished Aug 13 06:34:11 PM PDT 24
Peak memory 207560 kb
Host smart-3ecf2899-3eda-4a0a-a8cc-8b129d176176
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=962022757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.962022757
Directory /workspace/5.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.873679601
Short name T800
Test name
Test status
Simulation time 272455912 ps
CPU time 2.26 seconds
Started Aug 13 06:34:13 PM PDT 24
Finished Aug 13 06:34:16 PM PDT 24
Peak memory 207612 kb
Host smart-9dab0396-37d2-44f1-8b6a-1b703f20eb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87367
9601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.873679601
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3243575525
Short name T1163
Test name
Test status
Simulation time 239299016 ps
CPU time 1.23 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 215828 kb
Host smart-de8dbee7-6846-4c5e-84ca-c6a83e7b01bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3243575525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3243575525
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1071300015
Short name T121
Test name
Test status
Simulation time 136607153 ps
CPU time 0.82 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 207496 kb
Host smart-bc3a625b-42b0-4da9-a608-9f2bd282778e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10713
00015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1071300015
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1096452671
Short name T1575
Test name
Test status
Simulation time 268213775 ps
CPU time 1.01 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:09 PM PDT 24
Peak memory 207488 kb
Host smart-e8c33d02-0c8e-4644-8453-e303e0fa6ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10964
52671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1096452671
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.846156405
Short name T777
Test name
Test status
Simulation time 3760821382 ps
CPU time 31.37 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:40 PM PDT 24
Peak memory 218104 kb
Host smart-9bcf2829-0240-4ead-b17d-51a0a20b8b11
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=846156405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.846156405
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1370153137
Short name T3497
Test name
Test status
Simulation time 9138260875 ps
CPU time 71.83 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:35:20 PM PDT 24
Peak memory 207812 kb
Host smart-c4dd2857-7ce5-4b24-9612-f28320d6d984
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1370153137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1370153137
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1519519192
Short name T2850
Test name
Test status
Simulation time 222081623 ps
CPU time 0.96 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 207444 kb
Host smart-24f75278-b83c-4ba9-ad8b-87fff43b34ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15195
19192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1519519192
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2847417427
Short name T1725
Test name
Test status
Simulation time 29900767428 ps
CPU time 53.5 seconds
Started Aug 13 06:34:11 PM PDT 24
Finished Aug 13 06:35:05 PM PDT 24
Peak memory 207876 kb
Host smart-169ce2ef-3e04-4e1c-b29b-0b2429984d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28474
17427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2847417427
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.782699489
Short name T3012
Test name
Test status
Simulation time 5954229216 ps
CPU time 9 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:17 PM PDT 24
Peak memory 216048 kb
Host smart-d23e4baf-1be8-4158-87c7-dcd56c769ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78269
9489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.782699489
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1685021552
Short name T1896
Test name
Test status
Simulation time 2955479454 ps
CPU time 24.91 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:34 PM PDT 24
Peak memory 216068 kb
Host smart-92b90eb7-b08b-443b-8e2c-d038195001ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1685021552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1685021552
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.954522495
Short name T1431
Test name
Test status
Simulation time 2250075829 ps
CPU time 23.41 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 217380 kb
Host smart-c6ac310f-d564-41b2-97d6-5907470863b8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=954522495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.954522495
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3542739751
Short name T2804
Test name
Test status
Simulation time 302395198 ps
CPU time 1.13 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:09 PM PDT 24
Peak memory 207444 kb
Host smart-2a837f01-6c94-488a-8c43-7f668edfe0e9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3542739751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3542739751
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.106901733
Short name T2672
Test name
Test status
Simulation time 193170115 ps
CPU time 0.98 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 207420 kb
Host smart-90d17d09-c97a-44aa-aee1-ee04bbc5ab36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10690
1733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.106901733
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.3683229794
Short name T759
Test name
Test status
Simulation time 2503424787 ps
CPU time 24.56 seconds
Started Aug 13 06:34:12 PM PDT 24
Finished Aug 13 06:34:37 PM PDT 24
Peak memory 217892 kb
Host smart-81efed14-5075-4079-84a4-4859b55f557e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36832
29794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.3683229794
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.2607101678
Short name T1370
Test name
Test status
Simulation time 3176804476 ps
CPU time 29.53 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:38 PM PDT 24
Peak memory 216028 kb
Host smart-121a7674-9300-472d-bdba-8c06ada0d91a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2607101678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.2607101678
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.786346137
Short name T2357
Test name
Test status
Simulation time 1550949268 ps
CPU time 12.03 seconds
Started Aug 13 06:34:07 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 207748 kb
Host smart-d88483f2-4cd4-401c-83b6-5ade75188778
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=786346137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.786346137
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2135723522
Short name T2522
Test name
Test status
Simulation time 155450709 ps
CPU time 0.89 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:09 PM PDT 24
Peak memory 207452 kb
Host smart-7baa5573-366f-4b23-af41-d7d12b3859f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2135723522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2135723522
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1979428874
Short name T3202
Test name
Test status
Simulation time 159405244 ps
CPU time 0.86 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 207528 kb
Host smart-f2359040-990f-4bfb-97e1-0e46089df30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
28874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1979428874
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.339957579
Short name T136
Test name
Test status
Simulation time 207271330 ps
CPU time 0.96 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 207528 kb
Host smart-750df5b3-1289-4155-a16a-0555b5bb9a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33995
7579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.339957579
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3842016679
Short name T550
Test name
Test status
Simulation time 196304492 ps
CPU time 0.92 seconds
Started Aug 13 06:34:13 PM PDT 24
Finished Aug 13 06:34:14 PM PDT 24
Peak memory 207452 kb
Host smart-c48c0734-3b2d-435c-93ee-dc0cca7f2d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38420
16679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3842016679
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.809447610
Short name T2487
Test name
Test status
Simulation time 161383402 ps
CPU time 0.87 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 207424 kb
Host smart-5652f37e-cefb-42e2-ba9c-b418147be9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80944
7610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.809447610
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.505403493
Short name T970
Test name
Test status
Simulation time 167739361 ps
CPU time 0.87 seconds
Started Aug 13 06:34:12 PM PDT 24
Finished Aug 13 06:34:13 PM PDT 24
Peak memory 207712 kb
Host smart-d3a2ae12-8fe2-4f18-8616-455c3b365c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50540
3493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.505403493
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3642306036
Short name T2901
Test name
Test status
Simulation time 157332879 ps
CPU time 0.81 seconds
Started Aug 13 06:34:11 PM PDT 24
Finished Aug 13 06:34:12 PM PDT 24
Peak memory 207716 kb
Host smart-5b862c3d-8d7e-4ea4-a773-71397c55a701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
06036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3642306036
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.3385557458
Short name T2582
Test name
Test status
Simulation time 271489414 ps
CPU time 1.17 seconds
Started Aug 13 06:34:10 PM PDT 24
Finished Aug 13 06:34:11 PM PDT 24
Peak memory 207508 kb
Host smart-7c90ad9a-5f84-4df8-b6f5-790cc1c77479
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3385557458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.3385557458
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.814743177
Short name T1314
Test name
Test status
Simulation time 145055353 ps
CPU time 0.83 seconds
Started Aug 13 06:34:06 PM PDT 24
Finished Aug 13 06:34:07 PM PDT 24
Peak memory 207480 kb
Host smart-2fc7d172-e7b7-45ed-8907-42af98e065d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81474
3177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.814743177
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3024242598
Short name T2242
Test name
Test status
Simulation time 56248723 ps
CPU time 0.71 seconds
Started Aug 13 06:34:08 PM PDT 24
Finished Aug 13 06:34:09 PM PDT 24
Peak memory 207548 kb
Host smart-3c658ace-88c0-4451-a824-356cc427c0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30242
42598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3024242598
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.44702342
Short name T3284
Test name
Test status
Simulation time 18270068898 ps
CPU time 49.37 seconds
Started Aug 13 06:34:06 PM PDT 24
Finished Aug 13 06:34:56 PM PDT 24
Peak memory 215972 kb
Host smart-e3b0a1f5-618a-44ce-8c4b-68ebb31d7c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44702
342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.44702342
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.4017065035
Short name T3344
Test name
Test status
Simulation time 191247347 ps
CPU time 0.96 seconds
Started Aug 13 06:34:07 PM PDT 24
Finished Aug 13 06:34:08 PM PDT 24
Peak memory 207548 kb
Host smart-a92670e5-adf9-4a53-942f-d9eb7de99c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40170
65035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.4017065035
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1235417233
Short name T1901
Test name
Test status
Simulation time 274742690 ps
CPU time 1.11 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 207412 kb
Host smart-d9cc90b5-8a77-4af3-b28a-4c42432502b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12354
17233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1235417233
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1817790717
Short name T3134
Test name
Test status
Simulation time 2917700088 ps
CPU time 56.87 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:35:14 PM PDT 24
Peak memory 224116 kb
Host smart-9e9b7627-7bcd-4af2-9dbe-38832243c862
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1817790717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1817790717
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.4106915288
Short name T3312
Test name
Test status
Simulation time 6091818462 ps
CPU time 22.53 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 219216 kb
Host smart-41b38870-8249-4714-9824-dd96551e0a0d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106915288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.4106915288
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3368290780
Short name T3573
Test name
Test status
Simulation time 230725262 ps
CPU time 1.08 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 207448 kb
Host smart-36ab0336-64f1-4c2d-b197-dd50c8f799c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33682
90780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3368290780
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2566670487
Short name T974
Test name
Test status
Simulation time 172273989 ps
CPU time 0.96 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:11 PM PDT 24
Peak memory 207512 kb
Host smart-376aab39-46a2-4337-930c-c6260274de2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25666
70487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2566670487
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_resume_link_active.338439353
Short name T2918
Test name
Test status
Simulation time 20180917437 ps
CPU time 28.33 seconds
Started Aug 13 06:34:16 PM PDT 24
Finished Aug 13 06:34:45 PM PDT 24
Peak memory 207588 kb
Host smart-6ce5f8ff-a367-41e0-bc5e-c1995f7965dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33843
9353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.338439353
Directory /workspace/5.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1442028060
Short name T209
Test name
Test status
Simulation time 179876000 ps
CPU time 0.96 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 207456 kb
Host smart-f89fbc06-e691-467b-bbdc-b1294e01a4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14420
28060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1442028060
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_rx_full.425805168
Short name T329
Test name
Test status
Simulation time 244266269 ps
CPU time 1.14 seconds
Started Aug 13 06:34:15 PM PDT 24
Finished Aug 13 06:34:16 PM PDT 24
Peak memory 207532 kb
Host smart-8af16a49-2b19-4661-b645-e44d43716979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42580
5168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.425805168
Directory /workspace/5.usbdev_rx_full/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1277936572
Short name T1886
Test name
Test status
Simulation time 144582029 ps
CPU time 0.83 seconds
Started Aug 13 06:34:18 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 207516 kb
Host smart-4996a230-6312-4ef9-a583-dc74ae46c280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12779
36572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1277936572
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1384033326
Short name T1510
Test name
Test status
Simulation time 143614195 ps
CPU time 0.86 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 207572 kb
Host smart-c25864a3-7e69-467b-8e62-4dd588682515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13840
33326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1384033326
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3060952442
Short name T1150
Test name
Test status
Simulation time 225725843 ps
CPU time 1.08 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 207456 kb
Host smart-7eabee27-b1a0-4191-aad2-a70f53424d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
52442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3060952442
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1991461798
Short name T1401
Test name
Test status
Simulation time 3270022205 ps
CPU time 96.12 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:35:55 PM PDT 24
Peak memory 217728 kb
Host smart-c57a94cc-2c8b-4530-99dd-f8bbc49be5a5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1991461798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1991461798
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1347461875
Short name T581
Test name
Test status
Simulation time 178225605 ps
CPU time 0.95 seconds
Started Aug 13 06:34:18 PM PDT 24
Finished Aug 13 06:34:20 PM PDT 24
Peak memory 207524 kb
Host smart-f4984c26-0f59-4e18-a131-62fa110f18ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13474
61875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1347461875
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2617216994
Short name T887
Test name
Test status
Simulation time 206782496 ps
CPU time 0.95 seconds
Started Aug 13 06:34:15 PM PDT 24
Finished Aug 13 06:34:16 PM PDT 24
Peak memory 207392 kb
Host smart-41a28428-8ce2-4b1a-a65a-0401748137fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26172
16994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2617216994
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.3537836379
Short name T695
Test name
Test status
Simulation time 974351085 ps
CPU time 2.53 seconds
Started Aug 13 06:34:15 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 207760 kb
Host smart-063e0b66-7bc9-4e3e-b9ef-684203e7df04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35378
36379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.3537836379
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3184922894
Short name T2162
Test name
Test status
Simulation time 3995236055 ps
CPU time 31.28 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:34:50 PM PDT 24
Peak memory 217796 kb
Host smart-345ba707-7aaa-4de8-8cd1-95454ae66958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31849
22894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3184922894
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.1673874592
Short name T1090
Test name
Test status
Simulation time 1285712992 ps
CPU time 31.11 seconds
Started Aug 13 06:34:09 PM PDT 24
Finished Aug 13 06:34:40 PM PDT 24
Peak memory 207724 kb
Host smart-8fd6d574-964d-4531-a63c-41f8c5a8084d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673874592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.1673874592
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_tx_rx_disruption.3448857674
Short name T3232
Test name
Test status
Simulation time 570303133 ps
CPU time 1.55 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:34:21 PM PDT 24
Peak memory 207532 kb
Host smart-51548474-5dab-4d79-a8f3-e8cc476ee6bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448857674 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.usbdev_tx_rx_disruption.3448857674
Directory /workspace/5.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/50.usbdev_endpoint_types.3806281605
Short name T417
Test name
Test status
Simulation time 799288700 ps
CPU time 1.71 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207552 kb
Host smart-b198d9be-6ca7-40df-8f75-9d45fc46d220
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3806281605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.3806281605
Directory /workspace/50.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/50.usbdev_tx_rx_disruption.2358194004
Short name T2037
Test name
Test status
Simulation time 558580385 ps
CPU time 1.68 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207540 kb
Host smart-26bd356f-bbac-4ac4-b66e-d56bc1764047
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358194004 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.usbdev_tx_rx_disruption.2358194004
Directory /workspace/50.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/51.usbdev_endpoint_types.426764859
Short name T2666
Test name
Test status
Simulation time 151845795 ps
CPU time 0.87 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:40:59 PM PDT 24
Peak memory 207508 kb
Host smart-6aa3ca86-ff38-4d33-84fb-55246a11ed7a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=426764859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.426764859
Directory /workspace/51.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/51.usbdev_tx_rx_disruption.394489009
Short name T28
Test name
Test status
Simulation time 504708707 ps
CPU time 1.49 seconds
Started Aug 13 06:40:46 PM PDT 24
Finished Aug 13 06:40:48 PM PDT 24
Peak memory 207588 kb
Host smart-67a14220-bc48-4b9d-b4ed-1ec93589a51a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394489009 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 51.usbdev_tx_rx_disruption.394489009
Directory /workspace/51.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/52.usbdev_endpoint_types.729824267
Short name T416
Test name
Test status
Simulation time 430115438 ps
CPU time 1.39 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207524 kb
Host smart-b5766585-fdef-42f9-b9b8-33ffea0d3f08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=729824267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.729824267
Directory /workspace/52.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/52.usbdev_tx_rx_disruption.583172602
Short name T3625
Test name
Test status
Simulation time 457117510 ps
CPU time 1.43 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207612 kb
Host smart-069725a2-9110-472a-b1b2-d0d3a3de2afa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583172602 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 52.usbdev_tx_rx_disruption.583172602
Directory /workspace/52.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/53.usbdev_endpoint_types.3009813029
Short name T986
Test name
Test status
Simulation time 166254186 ps
CPU time 0.89 seconds
Started Aug 13 06:40:54 PM PDT 24
Finished Aug 13 06:40:55 PM PDT 24
Peak memory 207552 kb
Host smart-f545e5ef-adb0-46d1-9c27-ec40ba26436b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3009813029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.3009813029
Directory /workspace/53.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/53.usbdev_tx_rx_disruption.2296820882
Short name T2032
Test name
Test status
Simulation time 560427288 ps
CPU time 1.7 seconds
Started Aug 13 06:40:56 PM PDT 24
Finished Aug 13 06:40:58 PM PDT 24
Peak memory 207592 kb
Host smart-12a7692d-9107-4adf-8263-74dad52a4c7e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296820882 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.usbdev_tx_rx_disruption.2296820882
Directory /workspace/53.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/54.usbdev_endpoint_types.4237793384
Short name T391
Test name
Test status
Simulation time 360353090 ps
CPU time 1.11 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207564 kb
Host smart-604a9cff-3239-4e2d-ae3a-7c0cc591468c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4237793384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.4237793384
Directory /workspace/54.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/54.usbdev_tx_rx_disruption.529156033
Short name T2811
Test name
Test status
Simulation time 496529221 ps
CPU time 1.46 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207612 kb
Host smart-8b834d22-400b-45fd-a253-5a307477b09f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529156033 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 54.usbdev_tx_rx_disruption.529156033
Directory /workspace/54.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/55.usbdev_endpoint_types.2075438333
Short name T3066
Test name
Test status
Simulation time 194109115 ps
CPU time 0.91 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207556 kb
Host smart-e84c5eec-12e9-4c0c-8123-bdf35d85a673
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2075438333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.2075438333
Directory /workspace/55.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/55.usbdev_tx_rx_disruption.142055742
Short name T2838
Test name
Test status
Simulation time 487705179 ps
CPU time 1.6 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207612 kb
Host smart-064e33bb-5f98-4687-9f2f-2946f195ad6e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142055742 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 55.usbdev_tx_rx_disruption.142055742
Directory /workspace/55.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/56.usbdev_endpoint_types.3231875249
Short name T3411
Test name
Test status
Simulation time 599429552 ps
CPU time 1.49 seconds
Started Aug 13 06:40:57 PM PDT 24
Finished Aug 13 06:40:58 PM PDT 24
Peak memory 207508 kb
Host smart-bb9ccbd4-bdf2-478b-8edd-d89c5e356a2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3231875249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.3231875249
Directory /workspace/56.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/56.usbdev_tx_rx_disruption.1913777136
Short name T3268
Test name
Test status
Simulation time 702490612 ps
CPU time 1.88 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207604 kb
Host smart-648629b4-5ba8-4193-b770-8ec4b8700509
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913777136 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.usbdev_tx_rx_disruption.1913777136
Directory /workspace/56.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/57.usbdev_endpoint_types.1655503272
Short name T2885
Test name
Test status
Simulation time 591844656 ps
CPU time 1.53 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207560 kb
Host smart-a0ab3f66-4f5e-4f6a-b6f7-5ae3f74d43e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1655503272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.1655503272
Directory /workspace/57.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/57.usbdev_tx_rx_disruption.2079103435
Short name T2932
Test name
Test status
Simulation time 481542939 ps
CPU time 1.44 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 207604 kb
Host smart-945f50a3-ef38-42a0-9ad3-caf907001556
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079103435 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.usbdev_tx_rx_disruption.2079103435
Directory /workspace/57.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/58.usbdev_tx_rx_disruption.4199838005
Short name T808
Test name
Test status
Simulation time 501727357 ps
CPU time 1.56 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207592 kb
Host smart-de259e93-2023-402a-8539-35916bd1d771
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199838005 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.usbdev_tx_rx_disruption.4199838005
Directory /workspace/58.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/59.usbdev_tx_rx_disruption.3034727609
Short name T2615
Test name
Test status
Simulation time 484739817 ps
CPU time 1.42 seconds
Started Aug 13 06:41:08 PM PDT 24
Finished Aug 13 06:41:09 PM PDT 24
Peak memory 207568 kb
Host smart-0e92d1d4-6d14-4733-9e8b-990bbe3a96da
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034727609 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.usbdev_tx_rx_disruption.3034727609
Directory /workspace/59.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.2238164481
Short name T2881
Test name
Test status
Simulation time 33473946 ps
CPU time 0.66 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:34:25 PM PDT 24
Peak memory 207476 kb
Host smart-b9e7149e-b0a4-4144-a7d3-90092d93ad3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2238164481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.2238164481
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.301679178
Short name T1082
Test name
Test status
Simulation time 10745749066 ps
CPU time 13.78 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:34:31 PM PDT 24
Peak memory 207868 kb
Host smart-84873629-ae4f-43c1-b641-f661e21e85fb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301679178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon
_wake_disconnect.301679178
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.740316467
Short name T538
Test name
Test status
Simulation time 19629580904 ps
CPU time 22.62 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:34:41 PM PDT 24
Peak memory 207840 kb
Host smart-dc53649d-8ee4-4bd6-a382-03d82e9f08bc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=740316467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.740316467
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1061851651
Short name T3042
Test name
Test status
Simulation time 29145804013 ps
CPU time 41.97 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 207824 kb
Host smart-68d0a674-5b24-4713-b7e2-b1ea450bc340
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061851651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.1061851651
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2512962188
Short name T867
Test name
Test status
Simulation time 196764579 ps
CPU time 0.95 seconds
Started Aug 13 06:34:18 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 207492 kb
Host smart-ce02f5ce-8577-4623-ad6b-f9d10387e7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25129
62188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2512962188
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.785422630
Short name T2118
Test name
Test status
Simulation time 147201800 ps
CPU time 0.83 seconds
Started Aug 13 06:34:15 PM PDT 24
Finished Aug 13 06:34:16 PM PDT 24
Peak memory 207492 kb
Host smart-ff3f3738-3203-46d2-9783-ba0fb361cc5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78542
2630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.785422630
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.1321916519
Short name T2442
Test name
Test status
Simulation time 445357995 ps
CPU time 1.49 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:34:21 PM PDT 24
Peak memory 207512 kb
Host smart-ee6e6c71-6762-4ddb-935d-0eb756a4e0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13219
16519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.1321916519
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.4079794588
Short name T343
Test name
Test status
Simulation time 750092307 ps
CPU time 2.13 seconds
Started Aug 13 06:34:15 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 207580 kb
Host smart-4c918787-6b56-41ee-a2f4-223b2b6ecbb0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4079794588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.4079794588
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.28848800
Short name T2370
Test name
Test status
Simulation time 35201178897 ps
CPU time 56.37 seconds
Started Aug 13 06:34:16 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207864 kb
Host smart-905210be-01fd-432d-bc37-34be0c6e2398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28848
800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.28848800
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.2942419809
Short name T1506
Test name
Test status
Simulation time 3358995900 ps
CPU time 31 seconds
Started Aug 13 06:34:18 PM PDT 24
Finished Aug 13 06:34:50 PM PDT 24
Peak memory 207836 kb
Host smart-dbcb8657-fe8e-4a61-8df6-31e9e05d6e46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942419809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.2942419809
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.769572896
Short name T1924
Test name
Test status
Simulation time 1015125765 ps
CPU time 2.32 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 207580 kb
Host smart-557adb8f-bffe-454d-8607-1e312ff8fb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76957
2896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.769572896
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2491624342
Short name T2095
Test name
Test status
Simulation time 133510094 ps
CPU time 0.87 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 206912 kb
Host smart-abce8638-c052-484b-a8ae-c478a889770f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24916
24342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2491624342
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.730702550
Short name T2658
Test name
Test status
Simulation time 33077732 ps
CPU time 0.71 seconds
Started Aug 13 06:34:16 PM PDT 24
Finished Aug 13 06:34:17 PM PDT 24
Peak memory 207488 kb
Host smart-4f1edb3c-38e1-4eec-b106-1309a62f8043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73070
2550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.730702550
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1984481660
Short name T670
Test name
Test status
Simulation time 828871806 ps
CPU time 2.33 seconds
Started Aug 13 06:34:15 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 207728 kb
Host smart-728ff1c8-65de-49d4-a027-8532458ab898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19844
81660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1984481660
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_types.3022463001
Short name T3565
Test name
Test status
Simulation time 451322578 ps
CPU time 1.43 seconds
Started Aug 13 06:34:16 PM PDT 24
Finished Aug 13 06:34:17 PM PDT 24
Peak memory 207560 kb
Host smart-384fd34e-730b-4561-a699-8e1adc5da4d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3022463001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.3022463001
Directory /workspace/6.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2727521135
Short name T220
Test name
Test status
Simulation time 194489980 ps
CPU time 1.48 seconds
Started Aug 13 06:34:20 PM PDT 24
Finished Aug 13 06:34:22 PM PDT 24
Peak memory 207648 kb
Host smart-7ce46943-44c2-456d-b346-811c90d289d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27275
21135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2727521135
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1831524045
Short name T1004
Test name
Test status
Simulation time 169810786 ps
CPU time 0.92 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:34:18 PM PDT 24
Peak memory 207540 kb
Host smart-4bd5cceb-25ce-45a2-bfc8-13b72872302c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1831524045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1831524045
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3926697639
Short name T1039
Test name
Test status
Simulation time 150212133 ps
CPU time 0.88 seconds
Started Aug 13 06:34:16 PM PDT 24
Finished Aug 13 06:34:17 PM PDT 24
Peak memory 207424 kb
Host smart-043d8d55-2cab-49d1-b14c-87d01359c6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39266
97639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3926697639
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.684779202
Short name T1872
Test name
Test status
Simulation time 216581568 ps
CPU time 0.94 seconds
Started Aug 13 06:34:15 PM PDT 24
Finished Aug 13 06:34:16 PM PDT 24
Peak memory 207412 kb
Host smart-7457cfba-ff7b-4e92-95ba-0d56ab2bdce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68477
9202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.684779202
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.3985770777
Short name T972
Test name
Test status
Simulation time 2459196313 ps
CPU time 18.91 seconds
Started Aug 13 06:34:16 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 218104 kb
Host smart-c7148610-91fb-4dad-98e4-d894ca46441e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3985770777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3985770777
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.3516402042
Short name T2348
Test name
Test status
Simulation time 13058658045 ps
CPU time 84.62 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 207824 kb
Host smart-cf34b027-b506-444e-a0b8-830e9ec31901
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3516402042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.3516402042
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3426590619
Short name T107
Test name
Test status
Simulation time 282101778 ps
CPU time 1.02 seconds
Started Aug 13 06:34:18 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 207512 kb
Host smart-827eb31d-2e8f-4862-9c6c-7feb63f5720d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34265
90619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3426590619
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2019574295
Short name T854
Test name
Test status
Simulation time 32228894026 ps
CPU time 49.24 seconds
Started Aug 13 06:34:17 PM PDT 24
Finished Aug 13 06:35:07 PM PDT 24
Peak memory 207776 kb
Host smart-1317da7f-fec3-47ef-b0f4-d644fd33643f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20195
74295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2019574295
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3927556472
Short name T1031
Test name
Test status
Simulation time 5753398402 ps
CPU time 8.03 seconds
Started Aug 13 06:34:15 PM PDT 24
Finished Aug 13 06:34:23 PM PDT 24
Peak memory 215996 kb
Host smart-3f985eb1-69cf-4fab-ba7c-cbe673bd7af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
56472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3927556472
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1511647248
Short name T176
Test name
Test status
Simulation time 5568737082 ps
CPU time 59.73 seconds
Started Aug 13 06:34:16 PM PDT 24
Finished Aug 13 06:35:16 PM PDT 24
Peak memory 219668 kb
Host smart-52d291d8-4933-43d4-a8d1-009c4b1e14e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1511647248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1511647248
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3031693315
Short name T2769
Test name
Test status
Simulation time 1687204416 ps
CPU time 45.36 seconds
Started Aug 13 06:34:15 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 215956 kb
Host smart-0fccd1bc-1ea6-42ca-9010-42614c12dbe8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3031693315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3031693315
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.4116124227
Short name T766
Test name
Test status
Simulation time 239275516 ps
CPU time 1.03 seconds
Started Aug 13 06:34:18 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 207516 kb
Host smart-e75b7e99-9499-43b1-81d8-85eaf8e593cc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4116124227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.4116124227
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1887165142
Short name T3389
Test name
Test status
Simulation time 216232548 ps
CPU time 1 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:34:20 PM PDT 24
Peak memory 207488 kb
Host smart-c4dd3bca-96cd-4c3a-a4ac-4eee9e7342c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18871
65142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1887165142
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.1509886780
Short name T1615
Test name
Test status
Simulation time 2872502950 ps
CPU time 84 seconds
Started Aug 13 06:34:19 PM PDT 24
Finished Aug 13 06:35:43 PM PDT 24
Peak memory 217708 kb
Host smart-86773c63-8433-4eba-b0ad-b6390c1f423a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15098
86780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.1509886780
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.179388964
Short name T2114
Test name
Test status
Simulation time 2427155621 ps
CPU time 20.06 seconds
Started Aug 13 06:34:26 PM PDT 24
Finished Aug 13 06:34:47 PM PDT 24
Peak memory 224108 kb
Host smart-44faab3a-2b82-4c65-8d64-cde3d72b7d76
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=179388964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.179388964
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.1926622407
Short name T2456
Test name
Test status
Simulation time 3011449726 ps
CPU time 23.3 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:34:48 PM PDT 24
Peak memory 224120 kb
Host smart-09de894a-eaa2-42ea-b8a7-c941079e5d99
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1926622407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.1926622407
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2950201183
Short name T1449
Test name
Test status
Simulation time 162015914 ps
CPU time 0.9 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207500 kb
Host smart-c62345fc-6840-4547-a2b3-920cc6eaf565
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2950201183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2950201183
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3614289569
Short name T1368
Test name
Test status
Simulation time 150453443 ps
CPU time 0.88 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207540 kb
Host smart-a2329f6d-b80a-4082-96f0-b692a1ddef9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36142
89569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3614289569
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3324406825
Short name T138
Test name
Test status
Simulation time 214577984 ps
CPU time 1.01 seconds
Started Aug 13 06:34:23 PM PDT 24
Finished Aug 13 06:34:24 PM PDT 24
Peak memory 207392 kb
Host smart-bae4d6f6-9225-4ec5-8144-127780db7dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33244
06825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3324406825
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.911933071
Short name T924
Test name
Test status
Simulation time 157922652 ps
CPU time 0.97 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:34:25 PM PDT 24
Peak memory 207492 kb
Host smart-0209d26d-e190-40f1-b888-cdd03ee470a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91193
3071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.911933071
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.885279559
Short name T3488
Test name
Test status
Simulation time 165905230 ps
CPU time 0.97 seconds
Started Aug 13 06:34:28 PM PDT 24
Finished Aug 13 06:34:29 PM PDT 24
Peak memory 207456 kb
Host smart-bf5777bc-c20a-4af8-a607-fc4cab11a7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88527
9559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.885279559
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1917673046
Short name T1705
Test name
Test status
Simulation time 156027680 ps
CPU time 0.89 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207576 kb
Host smart-42717888-d24f-4a43-bc47-f07961e0aaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19176
73046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1917673046
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.990853464
Short name T946
Test name
Test status
Simulation time 158775740 ps
CPU time 0.88 seconds
Started Aug 13 06:34:22 PM PDT 24
Finished Aug 13 06:34:23 PM PDT 24
Peak memory 207512 kb
Host smart-e859b033-bb39-49f4-8969-132e4d69a76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99085
3464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.990853464
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1413488765
Short name T1834
Test name
Test status
Simulation time 210558000 ps
CPU time 1.07 seconds
Started Aug 13 06:34:26 PM PDT 24
Finished Aug 13 06:34:27 PM PDT 24
Peak memory 207520 kb
Host smart-c3eddf1b-b2a7-418d-94a7-1a9bb39314f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1413488765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1413488765
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.1738023838
Short name T1211
Test name
Test status
Simulation time 149377825 ps
CPU time 0.89 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207464 kb
Host smart-a2b36655-7116-433d-9c82-3dad858e6c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17380
23838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1738023838
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1401896845
Short name T2505
Test name
Test status
Simulation time 59815677 ps
CPU time 0.71 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207552 kb
Host smart-ebb3e4b1-b7a5-4651-944f-170e697d0ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14018
96845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1401896845
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1462882497
Short name T1552
Test name
Test status
Simulation time 16215116432 ps
CPU time 46.09 seconds
Started Aug 13 06:34:29 PM PDT 24
Finished Aug 13 06:35:15 PM PDT 24
Peak memory 215904 kb
Host smart-f6e0a33d-91d9-4ffb-870d-335ca88787f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14628
82497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1462882497
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1337956241
Short name T590
Test name
Test status
Simulation time 158342420 ps
CPU time 0.94 seconds
Started Aug 13 06:34:27 PM PDT 24
Finished Aug 13 06:34:28 PM PDT 24
Peak memory 207600 kb
Host smart-abc66ef2-445c-4d89-9158-a81a59405425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13379
56241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1337956241
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2702744771
Short name T3495
Test name
Test status
Simulation time 241947965 ps
CPU time 1.01 seconds
Started Aug 13 06:34:29 PM PDT 24
Finished Aug 13 06:34:30 PM PDT 24
Peak memory 207432 kb
Host smart-678cabcd-f14d-416a-bab3-f5cfaf8e7935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27027
44771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2702744771
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.123614464
Short name T604
Test name
Test status
Simulation time 1864933653 ps
CPU time 18.54 seconds
Started Aug 13 06:34:23 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 217840 kb
Host smart-7726cf25-4e31-4573-bbec-ffd299e5866a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=123614464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.123614464
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2573476738
Short name T1444
Test name
Test status
Simulation time 8907199964 ps
CPU time 46.99 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 216004 kb
Host smart-7d22488d-8dec-4b9a-818e-5fabb2c87097
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573476738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2573476738
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2913752699
Short name T2946
Test name
Test status
Simulation time 259975848 ps
CPU time 1.09 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207504 kb
Host smart-f00e8f56-0bd9-43cf-8283-05a481035140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29137
52699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2913752699
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3129832084
Short name T3560
Test name
Test status
Simulation time 186792199 ps
CPU time 0.94 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:34:25 PM PDT 24
Peak memory 207444 kb
Host smart-b0f28b1c-0d6a-460b-b55c-442580bb75a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31298
32084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3129832084
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_resume_link_active.1539509389
Short name T102
Test name
Test status
Simulation time 20161994811 ps
CPU time 28.36 seconds
Started Aug 13 06:34:21 PM PDT 24
Finished Aug 13 06:34:50 PM PDT 24
Peak memory 207616 kb
Host smart-b404de6b-6860-44a2-b16f-08bd6bd729ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15395
09389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.1539509389
Directory /workspace/6.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2173225892
Short name T1856
Test name
Test status
Simulation time 147100838 ps
CPU time 0.86 seconds
Started Aug 13 06:34:26 PM PDT 24
Finished Aug 13 06:34:27 PM PDT 24
Peak memory 207492 kb
Host smart-7bdc119c-f3e9-448c-a443-b3afd689f0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21732
25892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2173225892
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_rx_full.1326622944
Short name T3549
Test name
Test status
Simulation time 265452822 ps
CPU time 1.19 seconds
Started Aug 13 06:34:26 PM PDT 24
Finished Aug 13 06:34:27 PM PDT 24
Peak memory 207420 kb
Host smart-9c10b55b-d70b-45eb-bae4-06f7c777f92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13266
22944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.1326622944
Directory /workspace/6.usbdev_rx_full/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4154021653
Short name T2225
Test name
Test status
Simulation time 151784943 ps
CPU time 0.91 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:34:25 PM PDT 24
Peak memory 207500 kb
Host smart-1fb937bd-f611-4735-aeaf-1bf3c5174f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41540
21653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4154021653
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2379091112
Short name T2482
Test name
Test status
Simulation time 157915830 ps
CPU time 1.01 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207600 kb
Host smart-8b724e4c-6e4c-4511-b038-05466547fd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
91112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2379091112
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2580150335
Short name T3242
Test name
Test status
Simulation time 237831362 ps
CPU time 1.1 seconds
Started Aug 13 06:34:26 PM PDT 24
Finished Aug 13 06:34:27 PM PDT 24
Peak memory 207456 kb
Host smart-1dfb4519-990b-4b62-af7d-1b97ce8a7c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25801
50335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2580150335
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2258285703
Short name T2534
Test name
Test status
Simulation time 3092085310 ps
CPU time 93.86 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:35:58 PM PDT 24
Peak memory 217628 kb
Host smart-8279493f-6ae0-4343-a0a0-78fe5241605b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2258285703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2258285703
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.317079623
Short name T3241
Test name
Test status
Simulation time 189076970 ps
CPU time 0.95 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:27 PM PDT 24
Peak memory 207536 kb
Host smart-59026d6f-db4a-4347-b712-dbf81af8783a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31707
9623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.317079623
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1005141569
Short name T1398
Test name
Test status
Simulation time 185909421 ps
CPU time 0.88 seconds
Started Aug 13 06:34:29 PM PDT 24
Finished Aug 13 06:34:30 PM PDT 24
Peak memory 207468 kb
Host smart-ca7c2142-0803-412e-bbe3-760509191c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10051
41569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1005141569
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.113953448
Short name T539
Test name
Test status
Simulation time 889982193 ps
CPU time 2.3 seconds
Started Aug 13 06:34:23 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207756 kb
Host smart-651c750d-6527-41b3-871d-884be1d31e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11395
3448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.113953448
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3971336179
Short name T1684
Test name
Test status
Simulation time 2935022404 ps
CPU time 85.03 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:35:50 PM PDT 24
Peak memory 217652 kb
Host smart-247f4369-7ee9-46dd-9348-e3068fb7b151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
36179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3971336179
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.3960113413
Short name T985
Test name
Test status
Simulation time 3459167604 ps
CPU time 31.71 seconds
Started Aug 13 06:34:18 PM PDT 24
Finished Aug 13 06:34:50 PM PDT 24
Peak memory 207720 kb
Host smart-8eb34f06-cdab-4376-8b4c-473f619c3efa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960113413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.3960113413
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_tx_rx_disruption.1694004455
Short name T3608
Test name
Test status
Simulation time 515022847 ps
CPU time 1.62 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:27 PM PDT 24
Peak memory 207600 kb
Host smart-27f511ac-cd13-439b-85c9-94b15ba24b17
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694004455 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.usbdev_tx_rx_disruption.1694004455
Directory /workspace/6.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/60.usbdev_endpoint_types.4255458095
Short name T433
Test name
Test status
Simulation time 663596652 ps
CPU time 1.69 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207544 kb
Host smart-78d979ab-97bf-43f7-b8f2-226637c7288d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4255458095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.4255458095
Directory /workspace/60.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/60.usbdev_tx_rx_disruption.855330243
Short name T3533
Test name
Test status
Simulation time 598781864 ps
CPU time 1.72 seconds
Started Aug 13 06:41:13 PM PDT 24
Finished Aug 13 06:41:15 PM PDT 24
Peak memory 207588 kb
Host smart-5d7a0698-ec49-41c7-a898-243ddea5d672
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855330243 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 60.usbdev_tx_rx_disruption.855330243
Directory /workspace/60.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/61.usbdev_endpoint_types.490120413
Short name T422
Test name
Test status
Simulation time 529524693 ps
CPU time 1.43 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:40:59 PM PDT 24
Peak memory 207532 kb
Host smart-a46415e7-3739-4b62-b0e7-febc874356d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=490120413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.490120413
Directory /workspace/61.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/61.usbdev_tx_rx_disruption.3299989940
Short name T3532
Test name
Test status
Simulation time 586038830 ps
CPU time 1.72 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207592 kb
Host smart-8dea752d-ab68-41a6-af7a-94b0b3c8d690
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299989940 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.usbdev_tx_rx_disruption.3299989940
Directory /workspace/61.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/63.usbdev_endpoint_types.3716892418
Short name T459
Test name
Test status
Simulation time 511269672 ps
CPU time 1.5 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207576 kb
Host smart-4ba3868f-07aa-4242-887e-6b4a797f4b3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3716892418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.3716892418
Directory /workspace/63.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/63.usbdev_tx_rx_disruption.3450288526
Short name T3318
Test name
Test status
Simulation time 495772626 ps
CPU time 1.62 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207584 kb
Host smart-c848857c-d771-4de6-8cf6-c91c74aca855
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450288526 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.usbdev_tx_rx_disruption.3450288526
Directory /workspace/63.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/64.usbdev_endpoint_types.1337669345
Short name T435
Test name
Test status
Simulation time 284500225 ps
CPU time 1.11 seconds
Started Aug 13 06:41:17 PM PDT 24
Finished Aug 13 06:41:18 PM PDT 24
Peak memory 207564 kb
Host smart-831da475-bc7c-42d5-8ce5-105aae756e9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1337669345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.1337669345
Directory /workspace/64.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/64.usbdev_tx_rx_disruption.4117044406
Short name T515
Test name
Test status
Simulation time 601278874 ps
CPU time 1.74 seconds
Started Aug 13 06:41:01 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207608 kb
Host smart-a3f9bc17-514b-428d-b443-2827eb434571
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117044406 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.usbdev_tx_rx_disruption.4117044406
Directory /workspace/64.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/65.usbdev_endpoint_types.1702885161
Short name T401
Test name
Test status
Simulation time 628307037 ps
CPU time 1.62 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207424 kb
Host smart-7debedc0-9365-4543-b4c5-80a11ec6c12e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1702885161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.1702885161
Directory /workspace/65.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/65.usbdev_tx_rx_disruption.647447061
Short name T2529
Test name
Test status
Simulation time 621751534 ps
CPU time 1.6 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 207600 kb
Host smart-fc3150e4-d534-47d0-8838-b811ac7fa10e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647447061 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 65.usbdev_tx_rx_disruption.647447061
Directory /workspace/65.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/66.usbdev_tx_rx_disruption.2846120829
Short name T3514
Test name
Test status
Simulation time 521266721 ps
CPU time 1.64 seconds
Started Aug 13 06:41:06 PM PDT 24
Finished Aug 13 06:41:08 PM PDT 24
Peak memory 207592 kb
Host smart-8212ee3c-0a6a-4de7-8035-7c6977137954
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846120829 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.usbdev_tx_rx_disruption.2846120829
Directory /workspace/66.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/67.usbdev_endpoint_types.3686693715
Short name T2493
Test name
Test status
Simulation time 411580254 ps
CPU time 1.45 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207500 kb
Host smart-e6ab0418-de33-46f1-894c-ce87f9fdcd23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3686693715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.3686693715
Directory /workspace/67.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/67.usbdev_tx_rx_disruption.412473329
Short name T1301
Test name
Test status
Simulation time 567944227 ps
CPU time 1.82 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207600 kb
Host smart-66cd258b-f11a-42d7-a48e-56122688f7ee
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412473329 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 67.usbdev_tx_rx_disruption.412473329
Directory /workspace/67.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/68.usbdev_endpoint_types.2718868734
Short name T448
Test name
Test status
Simulation time 447673496 ps
CPU time 1.22 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 207524 kb
Host smart-9587f5b4-3ab4-4345-81e7-298f2dafbfec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2718868734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.2718868734
Directory /workspace/68.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/68.usbdev_tx_rx_disruption.2662898803
Short name T3527
Test name
Test status
Simulation time 626657723 ps
CPU time 1.88 seconds
Started Aug 13 06:41:21 PM PDT 24
Finished Aug 13 06:41:23 PM PDT 24
Peak memory 207612 kb
Host smart-24e06e9d-2fed-45b6-90c9-f3f03c410c99
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662898803 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.usbdev_tx_rx_disruption.2662898803
Directory /workspace/68.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/69.usbdev_endpoint_types.2424266337
Short name T438
Test name
Test status
Simulation time 489256792 ps
CPU time 1.38 seconds
Started Aug 13 06:41:12 PM PDT 24
Finished Aug 13 06:41:13 PM PDT 24
Peak memory 207556 kb
Host smart-657e4920-f894-43b4-bc83-b8d89c5f0a80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2424266337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.2424266337
Directory /workspace/69.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/69.usbdev_tx_rx_disruption.4127269376
Short name T2860
Test name
Test status
Simulation time 543550919 ps
CPU time 1.51 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207604 kb
Host smart-43299eaa-6fce-48ee-b32d-d3ec3cb68a00
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127269376 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.usbdev_tx_rx_disruption.4127269376
Directory /workspace/69.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.3805922875
Short name T726
Test name
Test status
Simulation time 33848272 ps
CPU time 0.67 seconds
Started Aug 13 06:34:35 PM PDT 24
Finished Aug 13 06:34:36 PM PDT 24
Peak memory 207424 kb
Host smart-c99784fa-129a-4c32-b467-62749b2f4ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3805922875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.3805922875
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1604657703
Short name T103
Test name
Test status
Simulation time 4033873538 ps
CPU time 6.69 seconds
Started Aug 13 06:34:21 PM PDT 24
Finished Aug 13 06:34:28 PM PDT 24
Peak memory 216028 kb
Host smart-567ba91d-5de4-4f01-a00f-0e17588e230d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604657703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.1604657703
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3749212716
Short name T241
Test name
Test status
Simulation time 15542533179 ps
CPU time 19.06 seconds
Started Aug 13 06:34:23 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 215984 kb
Host smart-6630ff3b-0e42-482c-ade0-f2ceb4a58fd6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749212716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3749212716
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3733266348
Short name T2255
Test name
Test status
Simulation time 26261853117 ps
CPU time 36.09 seconds
Started Aug 13 06:34:26 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 215888 kb
Host smart-0cee72ab-68a9-4cf0-86a9-833dd83c3569
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733266348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.3733266348
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2396653914
Short name T2324
Test name
Test status
Simulation time 150817079 ps
CPU time 0.87 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:34:25 PM PDT 24
Peak memory 207516 kb
Host smart-481cac9b-933a-4f38-afa8-4eb244bbc4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23966
53914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2396653914
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3182727826
Short name T3054
Test name
Test status
Simulation time 145420209 ps
CPU time 0.88 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207632 kb
Host smart-8f30ec90-4ee1-4555-a887-7c0d915296a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31827
27826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3182727826
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.1603190682
Short name T2097
Test name
Test status
Simulation time 153775637 ps
CPU time 0.84 seconds
Started Aug 13 06:34:25 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207580 kb
Host smart-6ab81d27-d2f5-4b67-adbc-b2a8acc19f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
90682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1603190682
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.919386363
Short name T1740
Test name
Test status
Simulation time 294760833 ps
CPU time 1.09 seconds
Started Aug 13 06:34:26 PM PDT 24
Finished Aug 13 06:34:27 PM PDT 24
Peak memory 207556 kb
Host smart-994aa097-63c3-402c-9a93-6017c168336d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=919386363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.919386363
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.1440624093
Short name T3632
Test name
Test status
Simulation time 15448965123 ps
CPU time 24.39 seconds
Started Aug 13 06:34:29 PM PDT 24
Finished Aug 13 06:34:53 PM PDT 24
Peak memory 207756 kb
Host smart-656b4384-f925-44fc-9e99-3abe7c2a9899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14406
24093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1440624093
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.2129768293
Short name T631
Test name
Test status
Simulation time 2333823510 ps
CPU time 61.19 seconds
Started Aug 13 06:34:27 PM PDT 24
Finished Aug 13 06:35:28 PM PDT 24
Peak memory 207836 kb
Host smart-26d4c51a-1ddc-4310-97a1-54f17c885626
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129768293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2129768293
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3966676077
Short name T945
Test name
Test status
Simulation time 498529167 ps
CPU time 1.5 seconds
Started Aug 13 06:34:24 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 207504 kb
Host smart-dd4f4389-bdf7-407f-9ec5-e709b54b7b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39666
76077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3966676077
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2692202576
Short name T1918
Test name
Test status
Simulation time 148651128 ps
CPU time 0.81 seconds
Started Aug 13 06:34:21 PM PDT 24
Finished Aug 13 06:34:22 PM PDT 24
Peak memory 207576 kb
Host smart-db1bdc30-1ec9-433d-9a83-0193e36b0c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26922
02576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2692202576
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3538074307
Short name T1122
Test name
Test status
Simulation time 34611329 ps
CPU time 0.72 seconds
Started Aug 13 06:34:26 PM PDT 24
Finished Aug 13 06:34:27 PM PDT 24
Peak memory 207484 kb
Host smart-31352d21-7de1-4999-82a7-de7d792999f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35380
74307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3538074307
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2690545870
Short name T791
Test name
Test status
Simulation time 855990104 ps
CPU time 2.45 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:34:36 PM PDT 24
Peak memory 207728 kb
Host smart-6d328ce3-fb8f-4731-b10d-2b4fea238e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26905
45870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2690545870
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_types.2271391078
Short name T399
Test name
Test status
Simulation time 403137573 ps
CPU time 1.27 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207572 kb
Host smart-b8be1cb2-cc1f-49bd-a5d0-49c028a78449
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2271391078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.2271391078
Directory /workspace/7.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2274495397
Short name T1711
Test name
Test status
Simulation time 188521821 ps
CPU time 1.96 seconds
Started Aug 13 06:34:31 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 207608 kb
Host smart-f9249350-ddd0-4036-8d82-ec6acf559d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22744
95397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2274495397
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2593783156
Short name T1343
Test name
Test status
Simulation time 216347727 ps
CPU time 1.09 seconds
Started Aug 13 06:34:32 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 215816 kb
Host smart-27b037af-545e-4bc4-9755-9e0bcde0066d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2593783156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2593783156
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1885984952
Short name T2245
Test name
Test status
Simulation time 155930233 ps
CPU time 0.84 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207412 kb
Host smart-f2d7deeb-efb5-42c2-89de-130f98fc48a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18859
84952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1885984952
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3860348217
Short name T1724
Test name
Test status
Simulation time 229577400 ps
CPU time 1.02 seconds
Started Aug 13 06:34:31 PM PDT 24
Finished Aug 13 06:34:32 PM PDT 24
Peak memory 207508 kb
Host smart-e640a970-2fd0-4012-b977-52015ebcd2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38603
48217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3860348217
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.2099308631
Short name T1220
Test name
Test status
Simulation time 4603183385 ps
CPU time 137.79 seconds
Started Aug 13 06:34:32 PM PDT 24
Finished Aug 13 06:36:50 PM PDT 24
Peak memory 217640 kb
Host smart-607b1c9c-72fb-46c7-abac-b7d9de96a24e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2099308631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.2099308631
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.2531170052
Short name T2674
Test name
Test status
Simulation time 4234643288 ps
CPU time 28.07 seconds
Started Aug 13 06:34:32 PM PDT 24
Finished Aug 13 06:35:00 PM PDT 24
Peak memory 207828 kb
Host smart-1edfebf3-0d18-49e2-8998-edc3484cac7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2531170052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2531170052
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2871512993
Short name T1549
Test name
Test status
Simulation time 274179925 ps
CPU time 1 seconds
Started Aug 13 06:34:35 PM PDT 24
Finished Aug 13 06:34:36 PM PDT 24
Peak memory 207452 kb
Host smart-3b9029dd-b2f5-4f86-ae35-58c13d697cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28715
12993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2871512993
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.5029830
Short name T3455
Test name
Test status
Simulation time 29587799064 ps
CPU time 45.98 seconds
Started Aug 13 06:34:30 PM PDT 24
Finished Aug 13 06:35:16 PM PDT 24
Peak memory 207764 kb
Host smart-4331feb9-269a-465c-ac25-c6acec6329c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50298
30 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.5029830
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2213983271
Short name T2726
Test name
Test status
Simulation time 9259819658 ps
CPU time 14.55 seconds
Started Aug 13 06:34:32 PM PDT 24
Finished Aug 13 06:34:47 PM PDT 24
Peak memory 207868 kb
Host smart-223545c3-ea49-47dc-8247-d0f06d518a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22139
83271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2213983271
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3847906460
Short name T2711
Test name
Test status
Simulation time 2041455722 ps
CPU time 16.07 seconds
Started Aug 13 06:34:35 PM PDT 24
Finished Aug 13 06:34:51 PM PDT 24
Peak memory 224048 kb
Host smart-b4ad685c-44d5-471b-a3b3-9858d075d0f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3847906460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3847906460
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2274134278
Short name T2013
Test name
Test status
Simulation time 247292570 ps
CPU time 1 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207516 kb
Host smart-d0de972a-155e-4450-937e-fa5364acd4b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2274134278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2274134278
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.401130990
Short name T3097
Test name
Test status
Simulation time 196278717 ps
CPU time 0.94 seconds
Started Aug 13 06:34:32 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 207496 kb
Host smart-2591c624-bbcb-4eab-99f2-987ae2b348bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40113
0990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.401130990
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.2013737112
Short name T3184
Test name
Test status
Simulation time 2977347347 ps
CPU time 23.63 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:34:57 PM PDT 24
Peak memory 215948 kb
Host smart-33aa4e47-2ad2-485e-939e-af73e898381c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20137
37112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.2013737112
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2407197743
Short name T1461
Test name
Test status
Simulation time 1820231054 ps
CPU time 19.06 seconds
Started Aug 13 06:34:35 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 217932 kb
Host smart-826d2ed6-411b-4525-b153-d2e598633aea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2407197743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2407197743
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1762649448
Short name T770
Test name
Test status
Simulation time 1836150322 ps
CPU time 14.46 seconds
Started Aug 13 06:34:36 PM PDT 24
Finished Aug 13 06:34:51 PM PDT 24
Peak memory 215968 kb
Host smart-a1b53e88-9182-4d13-a813-990363cb6286
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1762649448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1762649448
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3077095854
Short name T1691
Test name
Test status
Simulation time 161778809 ps
CPU time 0.91 seconds
Started Aug 13 06:34:31 PM PDT 24
Finished Aug 13 06:34:32 PM PDT 24
Peak memory 207516 kb
Host smart-7c00128f-c46a-4509-bd34-8f459a8b5fbd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3077095854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3077095854
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2762095540
Short name T3240
Test name
Test status
Simulation time 168376493 ps
CPU time 0.9 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:34:34 PM PDT 24
Peak memory 207388 kb
Host smart-2fa8bbd2-5b07-4dc6-b02e-a542eb64b792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27620
95540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2762095540
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1738740309
Short name T155
Test name
Test status
Simulation time 227108436 ps
CPU time 0.96 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207476 kb
Host smart-5d572c9e-7cef-484c-98df-eafcb1775a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17387
40309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1738740309
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.146235257
Short name T922
Test name
Test status
Simulation time 188136239 ps
CPU time 0.95 seconds
Started Aug 13 06:34:32 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 207452 kb
Host smart-1d53f587-762c-4f17-bb42-97bd60ef00ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14623
5257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.146235257
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2633831475
Short name T2156
Test name
Test status
Simulation time 170694189 ps
CPU time 0.87 seconds
Started Aug 13 06:34:32 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 207528 kb
Host smart-0dbb9041-78f7-4e0f-b599-afd47f28c561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26338
31475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2633831475
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3297683971
Short name T1206
Test name
Test status
Simulation time 201704746 ps
CPU time 0.93 seconds
Started Aug 13 06:34:31 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 207500 kb
Host smart-97dc51ca-93f3-4e83-aaad-9b4a6f715b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32976
83971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3297683971
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1032466893
Short name T2972
Test name
Test status
Simulation time 148489204 ps
CPU time 0.86 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207588 kb
Host smart-313bacea-89b4-4302-a796-fb8b32212d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10324
66893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1032466893
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.580005928
Short name T612
Test name
Test status
Simulation time 227874287 ps
CPU time 1.11 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:34:34 PM PDT 24
Peak memory 207532 kb
Host smart-f1efbb66-9323-440e-844e-41c41532a631
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=580005928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.580005928
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3700200093
Short name T1001
Test name
Test status
Simulation time 172427448 ps
CPU time 0.88 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:34:34 PM PDT 24
Peak memory 207456 kb
Host smart-62193567-6d27-49a3-b4c9-6468cfdbbd46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37002
00093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3700200093
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.711946489
Short name T29
Test name
Test status
Simulation time 76917704 ps
CPU time 0.74 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207516 kb
Host smart-7a6c2402-082a-4193-ad14-c00f1390a9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71194
6489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.711946489
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2750112949
Short name T864
Test name
Test status
Simulation time 17304853737 ps
CPU time 49.22 seconds
Started Aug 13 06:34:35 PM PDT 24
Finished Aug 13 06:35:24 PM PDT 24
Peak memory 224132 kb
Host smart-faa96bc6-e4c8-4af1-a807-cc6d09e92412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27501
12949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2750112949
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3973628019
Short name T1050
Test name
Test status
Simulation time 178380326 ps
CPU time 0.92 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207608 kb
Host smart-ddbc7453-bcf9-47f2-aa9e-5e344096b17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39736
28019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3973628019
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.194432663
Short name T3379
Test name
Test status
Simulation time 202059927 ps
CPU time 1.02 seconds
Started Aug 13 06:34:36 PM PDT 24
Finished Aug 13 06:34:37 PM PDT 24
Peak memory 207456 kb
Host smart-bd37ac99-5739-4a50-9b08-9b11ff5d1fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19443
2663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.194432663
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3655943498
Short name T3092
Test name
Test status
Simulation time 3831099717 ps
CPU time 91.04 seconds
Started Aug 13 06:34:32 PM PDT 24
Finished Aug 13 06:36:03 PM PDT 24
Peak memory 218564 kb
Host smart-c0943046-0e6d-4a5e-bad5-cc650ad2d87c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655943498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3655943498
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1893610681
Short name T189
Test name
Test status
Simulation time 3000184499 ps
CPU time 30.93 seconds
Started Aug 13 06:34:31 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 217284 kb
Host smart-8f0455ad-3594-4303-ab63-6bc684100145
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1893610681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1893610681
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.3458272046
Short name T1829
Test name
Test status
Simulation time 6114510426 ps
CPU time 32.37 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:35:05 PM PDT 24
Peak memory 224060 kb
Host smart-5ba72968-f0da-414a-b9b1-ed79e42c5085
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458272046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.3458272046
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.186969416
Short name T2201
Test name
Test status
Simulation time 258792655 ps
CPU time 1 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:41 PM PDT 24
Peak memory 207496 kb
Host smart-a1ffc13d-a8ef-4685-9b18-a61d33c65801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18696
9416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.186969416
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3225782571
Short name T1874
Test name
Test status
Simulation time 191384614 ps
CPU time 0.96 seconds
Started Aug 13 06:34:32 PM PDT 24
Finished Aug 13 06:34:33 PM PDT 24
Peak memory 207544 kb
Host smart-b2f4c208-4a34-4c19-9032-459afe6ee087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32257
82571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3225782571
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_resume_link_active.4000765228
Short name T2593
Test name
Test status
Simulation time 20150352362 ps
CPU time 23.94 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:34:57 PM PDT 24
Peak memory 207576 kb
Host smart-a4c14912-ff9e-4173-aa15-d2b187f12b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40007
65228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.4000765228
Directory /workspace/7.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3489495119
Short name T1722
Test name
Test status
Simulation time 172337864 ps
CPU time 0.92 seconds
Started Aug 13 06:34:35 PM PDT 24
Finished Aug 13 06:34:36 PM PDT 24
Peak memory 207452 kb
Host smart-25a9159c-b513-4628-9ef1-be07462d18b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34894
95119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3489495119
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_rx_full.1103901214
Short name T330
Test name
Test status
Simulation time 272484769 ps
CPU time 1.14 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:34:34 PM PDT 24
Peak memory 207532 kb
Host smart-34e5b156-dd7b-49a6-bd1b-722b5ab3aada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11039
01214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.1103901214
Directory /workspace/7.usbdev_rx_full/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2992468269
Short name T2371
Test name
Test status
Simulation time 154413053 ps
CPU time 0.87 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207484 kb
Host smart-e47acb46-1742-4fd1-8387-64e93bff3c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29924
68269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2992468269
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2349433204
Short name T1972
Test name
Test status
Simulation time 170323293 ps
CPU time 0.96 seconds
Started Aug 13 06:34:36 PM PDT 24
Finished Aug 13 06:34:37 PM PDT 24
Peak memory 207576 kb
Host smart-a09b36b5-d229-4b1c-a02f-0f84a4f57d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494
33204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2349433204
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1616654658
Short name T911
Test name
Test status
Simulation time 247629968 ps
CPU time 1 seconds
Started Aug 13 06:34:31 PM PDT 24
Finished Aug 13 06:34:32 PM PDT 24
Peak memory 207484 kb
Host smart-21c90384-78bf-4364-bb21-f8be4d640452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16166
54658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1616654658
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.4159263484
Short name T1799
Test name
Test status
Simulation time 1925455711 ps
CPU time 55.22 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:35:29 PM PDT 24
Peak memory 217468 kb
Host smart-4420c2ce-46f6-4432-9ff1-92656ee93c09
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4159263484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.4159263484
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.684541218
Short name T3087
Test name
Test status
Simulation time 183661092 ps
CPU time 0.89 seconds
Started Aug 13 06:34:33 PM PDT 24
Finished Aug 13 06:34:34 PM PDT 24
Peak memory 207468 kb
Host smart-8caab997-31c7-451e-97a7-aa268a75d2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68454
1218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.684541218
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3099510476
Short name T572
Test name
Test status
Simulation time 184781540 ps
CPU time 0.85 seconds
Started Aug 13 06:34:37 PM PDT 24
Finished Aug 13 06:34:38 PM PDT 24
Peak memory 207480 kb
Host smart-5154a2e1-ff8f-4bec-b311-bc53b749d673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30995
10476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3099510476
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.653439606
Short name T1802
Test name
Test status
Simulation time 387027920 ps
CPU time 1.33 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:35 PM PDT 24
Peak memory 207392 kb
Host smart-83669a13-0b35-4950-9e76-a200c7668654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65343
9606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.653439606
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3945672932
Short name T2512
Test name
Test status
Simulation time 1954078371 ps
CPU time 56.01 seconds
Started Aug 13 06:34:36 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 215932 kb
Host smart-f4b93d7b-764f-4328-9417-24864d564102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39456
72932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3945672932
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.1153703760
Short name T897
Test name
Test status
Simulation time 6154149719 ps
CPU time 42.77 seconds
Started Aug 13 06:34:29 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 207656 kb
Host smart-0002f154-1d90-4c6c-b1a1-392532848bb1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153703760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.1153703760
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_tx_rx_disruption.3432449320
Short name T2603
Test name
Test status
Simulation time 703134383 ps
CPU time 1.9 seconds
Started Aug 13 06:34:34 PM PDT 24
Finished Aug 13 06:34:36 PM PDT 24
Peak memory 207396 kb
Host smart-fc7cbef6-ee40-46c2-8ec1-b0ec86e4d073
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432449320 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.usbdev_tx_rx_disruption.3432449320
Directory /workspace/7.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/70.usbdev_endpoint_types.2870605765
Short name T491
Test name
Test status
Simulation time 300372534 ps
CPU time 1.08 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207532 kb
Host smart-0044bb0d-f2ff-4462-8174-d0846d6adac1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2870605765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.2870605765
Directory /workspace/70.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/70.usbdev_tx_rx_disruption.3086741435
Short name T1462
Test name
Test status
Simulation time 552098733 ps
CPU time 2.05 seconds
Started Aug 13 06:41:31 PM PDT 24
Finished Aug 13 06:41:33 PM PDT 24
Peak memory 207608 kb
Host smart-33de16bd-e833-4873-bb81-6d548b93e07d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086741435 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.usbdev_tx_rx_disruption.3086741435
Directory /workspace/70.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/71.usbdev_endpoint_types.2914048027
Short name T3615
Test name
Test status
Simulation time 243301546 ps
CPU time 1.01 seconds
Started Aug 13 06:41:24 PM PDT 24
Finished Aug 13 06:41:25 PM PDT 24
Peak memory 207576 kb
Host smart-c31709cd-f203-4e36-951a-4c473847ab2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2914048027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.2914048027
Directory /workspace/71.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/71.usbdev_tx_rx_disruption.2155946920
Short name T931
Test name
Test status
Simulation time 535631833 ps
CPU time 1.58 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207136 kb
Host smart-c800e6e9-15ad-43b9-972f-382fd513c445
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155946920 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 71.usbdev_tx_rx_disruption.2155946920
Directory /workspace/71.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/72.usbdev_endpoint_types.1331444632
Short name T3169
Test name
Test status
Simulation time 246069487 ps
CPU time 1.03 seconds
Started Aug 13 06:41:37 PM PDT 24
Finished Aug 13 06:41:38 PM PDT 24
Peak memory 207564 kb
Host smart-692fe19b-fd64-4f3b-bce9-42ae27e77f29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1331444632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.1331444632
Directory /workspace/72.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/72.usbdev_tx_rx_disruption.67515520
Short name T3575
Test name
Test status
Simulation time 478942063 ps
CPU time 1.51 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207520 kb
Host smart-46790801-f446-4ccc-bf03-ca475c07e953
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67515520 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 72.usbdev_tx_rx_disruption.67515520
Directory /workspace/72.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/73.usbdev_endpoint_types.3174041845
Short name T446
Test name
Test status
Simulation time 208323288 ps
CPU time 0.92 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207556 kb
Host smart-3125404e-b4b9-422e-b126-5e6670700467
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3174041845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.3174041845
Directory /workspace/73.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/73.usbdev_tx_rx_disruption.1792644698
Short name T861
Test name
Test status
Simulation time 630391241 ps
CPU time 1.88 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207620 kb
Host smart-85c9e3de-f785-41f0-8832-dcbf31814150
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792644698 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.usbdev_tx_rx_disruption.1792644698
Directory /workspace/73.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/74.usbdev_endpoint_types.3665368562
Short name T477
Test name
Test status
Simulation time 211270275 ps
CPU time 1.01 seconds
Started Aug 13 06:41:08 PM PDT 24
Finished Aug 13 06:41:09 PM PDT 24
Peak memory 207472 kb
Host smart-829e0fa6-7e61-429c-a88a-ad277e0df7f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3665368562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.3665368562
Directory /workspace/74.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/74.usbdev_tx_rx_disruption.2145078967
Short name T3609
Test name
Test status
Simulation time 486148503 ps
CPU time 1.59 seconds
Started Aug 13 06:41:09 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207600 kb
Host smart-f7f8909b-5b6e-46f7-b72f-911cf6711b01
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145078967 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.usbdev_tx_rx_disruption.2145078967
Directory /workspace/74.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/75.usbdev_tx_rx_disruption.929202094
Short name T3606
Test name
Test status
Simulation time 463583226 ps
CPU time 1.49 seconds
Started Aug 13 06:40:58 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207548 kb
Host smart-bf49f8a6-7c21-49d5-bbf5-8cff30d7b6cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929202094 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 75.usbdev_tx_rx_disruption.929202094
Directory /workspace/75.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/76.usbdev_endpoint_types.3520170252
Short name T2017
Test name
Test status
Simulation time 251407524 ps
CPU time 1.05 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207472 kb
Host smart-27211cc8-60bf-4855-94bf-7e11fe76e2de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3520170252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.3520170252
Directory /workspace/76.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/76.usbdev_tx_rx_disruption.1855273331
Short name T837
Test name
Test status
Simulation time 633840496 ps
CPU time 1.72 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207588 kb
Host smart-4eec7eab-8630-43fa-ac4d-5ca6271082f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855273331 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.usbdev_tx_rx_disruption.1855273331
Directory /workspace/76.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/77.usbdev_endpoint_types.89579847
Short name T496
Test name
Test status
Simulation time 330529928 ps
CPU time 1.23 seconds
Started Aug 13 06:41:08 PM PDT 24
Finished Aug 13 06:41:09 PM PDT 24
Peak memory 207560 kb
Host smart-c3a9c452-e688-4ed3-8890-e77bdf30bf45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=89579847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.89579847
Directory /workspace/77.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/77.usbdev_tx_rx_disruption.711817335
Short name T3279
Test name
Test status
Simulation time 518434259 ps
CPU time 1.62 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:00 PM PDT 24
Peak memory 207484 kb
Host smart-71eb01f9-8071-4610-b0be-4efee6795021
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711817335 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 77.usbdev_tx_rx_disruption.711817335
Directory /workspace/77.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/78.usbdev_endpoint_types.3162703808
Short name T478
Test name
Test status
Simulation time 318656291 ps
CPU time 1.19 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207472 kb
Host smart-03520a19-a887-4425-929e-7c96bc41ec08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3162703808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.3162703808
Directory /workspace/78.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/78.usbdev_tx_rx_disruption.2686379130
Short name T2819
Test name
Test status
Simulation time 531246278 ps
CPU time 1.55 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207608 kb
Host smart-f9652f65-4e9d-4ab4-8280-bec3efd587d4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686379130 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.usbdev_tx_rx_disruption.2686379130
Directory /workspace/78.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/79.usbdev_endpoint_types.79063570
Short name T444
Test name
Test status
Simulation time 287498780 ps
CPU time 1.09 seconds
Started Aug 13 06:41:09 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207508 kb
Host smart-d447b73a-8a1b-4d4c-becf-fcfdee9b411c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=79063570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.79063570
Directory /workspace/79.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/79.usbdev_tx_rx_disruption.2980422069
Short name T2135
Test name
Test status
Simulation time 667604108 ps
CPU time 1.56 seconds
Started Aug 13 06:41:17 PM PDT 24
Finished Aug 13 06:41:18 PM PDT 24
Peak memory 207580 kb
Host smart-3ba64226-5d21-4720-b3d7-7c7cb62c54d0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980422069 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.usbdev_tx_rx_disruption.2980422069
Directory /workspace/79.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1088905713
Short name T2178
Test name
Test status
Simulation time 65129552 ps
CPU time 0.72 seconds
Started Aug 13 06:34:51 PM PDT 24
Finished Aug 13 06:34:52 PM PDT 24
Peak memory 207496 kb
Host smart-f9578f62-b8cd-4c28-a1c0-62bf5eaef819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1088905713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1088905713
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.4167666631
Short name T1405
Test name
Test status
Simulation time 11513847576 ps
CPU time 14.57 seconds
Started Aug 13 06:34:37 PM PDT 24
Finished Aug 13 06:34:52 PM PDT 24
Peak memory 207768 kb
Host smart-e0925af6-dc60-4fd2-a90c-1a0e3654c0ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167666631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.4167666631
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3710395893
Short name T228
Test name
Test status
Simulation time 20831056668 ps
CPU time 25.22 seconds
Started Aug 13 06:34:37 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 207764 kb
Host smart-f54e42e0-f0ac-4e8c-979f-ff951850b286
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710395893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3710395893
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.734874834
Short name T2073
Test name
Test status
Simulation time 29316230048 ps
CPU time 33.73 seconds
Started Aug 13 06:34:39 PM PDT 24
Finished Aug 13 06:35:13 PM PDT 24
Peak memory 207888 kb
Host smart-afeb3888-7b2f-4ed3-8a2c-ccd511ef738c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734874834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon
_wake_resume.734874834
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.728577551
Short name T3599
Test name
Test status
Simulation time 149228724 ps
CPU time 0.88 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 207472 kb
Host smart-05f32fbe-ad5a-4cfc-be4d-8d87b4c17c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72857
7551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.728577551
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3329150785
Short name T2161
Test name
Test status
Simulation time 173600285 ps
CPU time 0.87 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:34:41 PM PDT 24
Peak memory 207540 kb
Host smart-87708067-2b7d-4248-8429-6a7e003126fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33291
50785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3329150785
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.287752816
Short name T3329
Test name
Test status
Simulation time 477578855 ps
CPU time 1.8 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 207508 kb
Host smart-ac9e12c9-8e0f-44b4-82df-52d2b4d3afb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28775
2816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.287752816
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3408879076
Short name T2204
Test name
Test status
Simulation time 729327348 ps
CPU time 2.08 seconds
Started Aug 13 06:34:46 PM PDT 24
Finished Aug 13 06:34:49 PM PDT 24
Peak memory 207796 kb
Host smart-c8d94a5b-f64c-4870-b044-c42744d6666f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3408879076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3408879076
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.3234478849
Short name T180
Test name
Test status
Simulation time 44906681202 ps
CPU time 75.33 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:35:56 PM PDT 24
Peak memory 207828 kb
Host smart-ec37276c-58c8-4877-8d17-7ba69d9e7961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32344
78849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3234478849
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.4271447902
Short name T748
Test name
Test status
Simulation time 4358079762 ps
CPU time 37.52 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:35:18 PM PDT 24
Peak memory 207788 kb
Host smart-ceecf6e6-fc0a-4677-9509-2d9ff65833d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271447902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.4271447902
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.25219681
Short name T2199
Test name
Test status
Simulation time 956579687 ps
CPU time 2.27 seconds
Started Aug 13 06:34:42 PM PDT 24
Finished Aug 13 06:34:45 PM PDT 24
Peak memory 207544 kb
Host smart-3a96999a-88cf-4528-a714-c2d1c66f98cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25219
681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.25219681
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.4142932985
Short name T3391
Test name
Test status
Simulation time 151590941 ps
CPU time 0.88 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 207516 kb
Host smart-047dbb08-09b8-44bd-9fdc-795936c2ce39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41429
32985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.4142932985
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3040551153
Short name T1568
Test name
Test status
Simulation time 44779775 ps
CPU time 0.77 seconds
Started Aug 13 06:34:39 PM PDT 24
Finished Aug 13 06:34:40 PM PDT 24
Peak memory 207492 kb
Host smart-9e497344-e71d-4112-8be5-e164d01568ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30405
51153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3040551153
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.23002224
Short name T2928
Test name
Test status
Simulation time 906607889 ps
CPU time 2.4 seconds
Started Aug 13 06:34:39 PM PDT 24
Finished Aug 13 06:34:41 PM PDT 24
Peak memory 207700 kb
Host smart-e60f7e03-054a-4481-be67-bfc5ed7a72e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23002
224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.23002224
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_types.1382139003
Short name T376
Test name
Test status
Simulation time 553945136 ps
CPU time 1.66 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:34:43 PM PDT 24
Peak memory 207492 kb
Host smart-2a7f4c51-ab51-4ae4-ad5f-df2c63ced740
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1382139003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.1382139003
Directory /workspace/8.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.4128089047
Short name T1768
Test name
Test status
Simulation time 241155565 ps
CPU time 1.62 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:34:43 PM PDT 24
Peak memory 207688 kb
Host smart-41b05e89-e15d-45da-905a-af66470130ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41280
89047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.4128089047
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1554696024
Short name T2066
Test name
Test status
Simulation time 213695059 ps
CPU time 1.06 seconds
Started Aug 13 06:34:45 PM PDT 24
Finished Aug 13 06:34:47 PM PDT 24
Peak memory 215928 kb
Host smart-c4d3a53a-87e2-4bde-b4bc-2fa827825d45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1554696024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1554696024
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.727234163
Short name T2514
Test name
Test status
Simulation time 133619629 ps
CPU time 0.8 seconds
Started Aug 13 06:34:37 PM PDT 24
Finished Aug 13 06:34:38 PM PDT 24
Peak memory 207380 kb
Host smart-e51ae5cc-c2f7-4779-b331-da839fc74138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72723
4163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.727234163
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2687063694
Short name T2338
Test name
Test status
Simulation time 156446247 ps
CPU time 0.85 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 207512 kb
Host smart-e950862a-2205-4e70-92a1-bbb164f07243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26870
63694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2687063694
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.999325210
Short name T881
Test name
Test status
Simulation time 3842517712 ps
CPU time 40.83 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:35:21 PM PDT 24
Peak memory 217732 kb
Host smart-1d1316b0-c3be-4d33-b2be-8657f1b838a4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=999325210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.999325210
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.3148044908
Short name T2639
Test name
Test status
Simulation time 12525910995 ps
CPU time 156.24 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:37:17 PM PDT 24
Peak memory 207820 kb
Host smart-aff9cc26-fc1f-4ab2-a6e4-c0539c5522d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3148044908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.3148044908
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1688887857
Short name T2894
Test name
Test status
Simulation time 196508218 ps
CPU time 1.01 seconds
Started Aug 13 06:34:38 PM PDT 24
Finished Aug 13 06:34:39 PM PDT 24
Peak memory 207512 kb
Host smart-8c417345-c89f-4a97-90ae-ec50e1390cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16888
87857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1688887857
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2741787819
Short name T2779
Test name
Test status
Simulation time 28293681402 ps
CPU time 39.35 seconds
Started Aug 13 06:34:42 PM PDT 24
Finished Aug 13 06:35:21 PM PDT 24
Peak memory 215964 kb
Host smart-ba435a90-5421-4d12-b447-2182b6456bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27417
87819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2741787819
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2074249832
Short name T1079
Test name
Test status
Simulation time 3785862883 ps
CPU time 5.75 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:34:46 PM PDT 24
Peak memory 207796 kb
Host smart-ecd95c1f-890c-43be-9f6d-55462a444222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20742
49832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2074249832
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.1127554643
Short name T1244
Test name
Test status
Simulation time 4450088966 ps
CPU time 129.73 seconds
Started Aug 13 06:34:43 PM PDT 24
Finished Aug 13 06:36:53 PM PDT 24
Peak memory 216036 kb
Host smart-22d43df5-804d-47a5-81fd-3990450ad5d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1127554643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.1127554643
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.1928039025
Short name T1887
Test name
Test status
Simulation time 4137704818 ps
CPU time 121.3 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:36:42 PM PDT 24
Peak memory 217456 kb
Host smart-f324bf49-6bb7-445d-9225-97c9049d958d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1928039025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.1928039025
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3904378371
Short name T3578
Test name
Test status
Simulation time 236887723 ps
CPU time 0.98 seconds
Started Aug 13 06:34:38 PM PDT 24
Finished Aug 13 06:34:39 PM PDT 24
Peak memory 207480 kb
Host smart-e34a135d-b89e-4f1c-bfd4-005269df0ba1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3904378371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3904378371
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.4234666490
Short name T2537
Test name
Test status
Simulation time 190745661 ps
CPU time 0.92 seconds
Started Aug 13 06:34:45 PM PDT 24
Finished Aug 13 06:34:46 PM PDT 24
Peak memory 207532 kb
Host smart-bdd00647-5b8a-404e-8693-4805bef125bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42346
66490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.4234666490
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.685647041
Short name T2100
Test name
Test status
Simulation time 2972047376 ps
CPU time 82.38 seconds
Started Aug 13 06:34:43 PM PDT 24
Finished Aug 13 06:36:05 PM PDT 24
Peak memory 217592 kb
Host smart-83a82003-a953-4389-a726-d0c7dc64ab25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68564
7041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.685647041
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1175003038
Short name T964
Test name
Test status
Simulation time 2792683676 ps
CPU time 30.99 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 224168 kb
Host smart-dfee1230-0c14-4f35-9a06-1484ca84f8bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1175003038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1175003038
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.678336334
Short name T2088
Test name
Test status
Simulation time 2846853258 ps
CPU time 82.81 seconds
Started Aug 13 06:34:43 PM PDT 24
Finished Aug 13 06:36:06 PM PDT 24
Peak memory 217552 kb
Host smart-7db31ea7-0f84-419c-819c-631c193f2426
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=678336334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.678336334
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3591341187
Short name T1266
Test name
Test status
Simulation time 177736154 ps
CPU time 0.91 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:34:43 PM PDT 24
Peak memory 207452 kb
Host smart-d86969e5-dedb-4153-b6bf-9cb75fd4c6b0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3591341187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3591341187
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1735567714
Short name T2266
Test name
Test status
Simulation time 153801355 ps
CPU time 0.9 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:34:41 PM PDT 24
Peak memory 207508 kb
Host smart-d186cae9-15c9-40c9-ac9f-efd30b1553ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17355
67714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1735567714
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.329141669
Short name T143
Test name
Test status
Simulation time 246016773 ps
CPU time 1 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 207400 kb
Host smart-24ac1958-758f-4700-91ac-dce57323e3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914
1669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.329141669
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1707146925
Short name T2440
Test name
Test status
Simulation time 167114215 ps
CPU time 0.9 seconds
Started Aug 13 06:34:38 PM PDT 24
Finished Aug 13 06:34:39 PM PDT 24
Peak memory 207440 kb
Host smart-831642de-7646-42eb-b2d5-970787fd9860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17071
46925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1707146925
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.151687891
Short name T1970
Test name
Test status
Simulation time 194923229 ps
CPU time 1 seconds
Started Aug 13 06:34:39 PM PDT 24
Finished Aug 13 06:34:40 PM PDT 24
Peak memory 207540 kb
Host smart-999763ff-370e-43b1-992d-7d82bbecbb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15168
7891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.151687891
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3327017368
Short name T790
Test name
Test status
Simulation time 194638991 ps
CPU time 0.97 seconds
Started Aug 13 06:34:38 PM PDT 24
Finished Aug 13 06:34:39 PM PDT 24
Peak memory 207616 kb
Host smart-124a9b49-e475-46af-a051-21607d118c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33270
17368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3327017368
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.243402353
Short name T3296
Test name
Test status
Simulation time 148500631 ps
CPU time 0.86 seconds
Started Aug 13 06:34:43 PM PDT 24
Finished Aug 13 06:34:44 PM PDT 24
Peak memory 207584 kb
Host smart-35975702-2717-411d-bc39-e0be93c5ea1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24340
2353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.243402353
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3116141932
Short name T2808
Test name
Test status
Simulation time 224280777 ps
CPU time 1.01 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 207588 kb
Host smart-9bccd174-7bd4-4d9e-9150-16a881f1d72b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3116141932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3116141932
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3581028264
Short name T812
Test name
Test status
Simulation time 174668750 ps
CPU time 0.86 seconds
Started Aug 13 06:34:46 PM PDT 24
Finished Aug 13 06:34:47 PM PDT 24
Peak memory 207500 kb
Host smart-1d43567e-03a9-4edd-9c5f-76be319775cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35810
28264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3581028264
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.884390718
Short name T26
Test name
Test status
Simulation time 50793247 ps
CPU time 0.71 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:34:40 PM PDT 24
Peak memory 207540 kb
Host smart-2bbc0b12-575e-49a1-9a3f-f15989c5825f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88439
0718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.884390718
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.4209665499
Short name T1820
Test name
Test status
Simulation time 19344403689 ps
CPU time 51.47 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 224008 kb
Host smart-f2e7562e-5232-4a9b-947b-0bf76a66cd2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096
65499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.4209665499
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.293481257
Short name T2604
Test name
Test status
Simulation time 174250737 ps
CPU time 0.95 seconds
Started Aug 13 06:34:39 PM PDT 24
Finished Aug 13 06:34:40 PM PDT 24
Peak memory 207448 kb
Host smart-1a5c4e3c-b379-490c-8ac6-43f2e28ebc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29348
1257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.293481257
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2572147483
Short name T2056
Test name
Test status
Simulation time 243713035 ps
CPU time 1.08 seconds
Started Aug 13 06:34:40 PM PDT 24
Finished Aug 13 06:34:42 PM PDT 24
Peak memory 207528 kb
Host smart-66a89217-ac61-4a1e-9879-99d16ec9a9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25721
47483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2572147483
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.421430514
Short name T3023
Test name
Test status
Simulation time 6640516773 ps
CPU time 47.66 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:35:29 PM PDT 24
Peak memory 218728 kb
Host smart-13052e5c-bf86-41fb-83e9-189904a94ddb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=421430514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.421430514
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.4011843180
Short name T1873
Test name
Test status
Simulation time 3509786671 ps
CPU time 82.24 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:36:03 PM PDT 24
Peak memory 215960 kb
Host smart-17049152-de0e-42aa-a48c-2cb0458f1ca6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4011843180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.4011843180
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1900157733
Short name T1333
Test name
Test status
Simulation time 10628173150 ps
CPU time 205.3 seconds
Started Aug 13 06:34:42 PM PDT 24
Finished Aug 13 06:38:08 PM PDT 24
Peak memory 218348 kb
Host smart-6bd806fd-7324-4b44-8347-af212279bab5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900157733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1900157733
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.3263584105
Short name T1992
Test name
Test status
Simulation time 260635144 ps
CPU time 0.99 seconds
Started Aug 13 06:34:38 PM PDT 24
Finished Aug 13 06:34:39 PM PDT 24
Peak memory 207520 kb
Host smart-51670b3c-e1f6-4553-b1c3-04e4351816e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32635
84105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.3263584105
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.765846754
Short name T3378
Test name
Test status
Simulation time 187976601 ps
CPU time 0.96 seconds
Started Aug 13 06:34:36 PM PDT 24
Finished Aug 13 06:34:37 PM PDT 24
Peak memory 207544 kb
Host smart-da6a6359-7a90-4447-902f-18390d448832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76584
6754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.765846754
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_resume_link_active.3547217648
Short name T1619
Test name
Test status
Simulation time 20190565212 ps
CPU time 22.75 seconds
Started Aug 13 06:34:43 PM PDT 24
Finished Aug 13 06:35:05 PM PDT 24
Peak memory 207624 kb
Host smart-56f580ad-14cf-4c23-a618-96fca1ffdad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35472
17648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.3547217648
Directory /workspace/8.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2589458548
Short name T3099
Test name
Test status
Simulation time 141083239 ps
CPU time 0.85 seconds
Started Aug 13 06:34:43 PM PDT 24
Finished Aug 13 06:34:44 PM PDT 24
Peak memory 207472 kb
Host smart-40250a91-7a74-48b9-b3d6-de2645e15cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25894
58548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2589458548
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_rx_full.1448184132
Short name T1387
Test name
Test status
Simulation time 361070809 ps
CPU time 1.27 seconds
Started Aug 13 06:34:42 PM PDT 24
Finished Aug 13 06:34:44 PM PDT 24
Peak memory 207536 kb
Host smart-329018f9-48a5-43ab-9423-43642a897ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14481
84132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.1448184132
Directory /workspace/8.usbdev_rx_full/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2755977106
Short name T1702
Test name
Test status
Simulation time 152097393 ps
CPU time 0.88 seconds
Started Aug 13 06:34:45 PM PDT 24
Finished Aug 13 06:34:46 PM PDT 24
Peak memory 207412 kb
Host smart-b383346d-9bf8-4855-960e-8a372ed67aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27559
77106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2755977106
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.744226456
Short name T2203
Test name
Test status
Simulation time 152935828 ps
CPU time 0.82 seconds
Started Aug 13 06:34:48 PM PDT 24
Finished Aug 13 06:34:49 PM PDT 24
Peak memory 207608 kb
Host smart-37793b16-785d-4182-bc11-e5833796885f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74422
6456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.744226456
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1929304992
Short name T2051
Test name
Test status
Simulation time 226038100 ps
CPU time 1.12 seconds
Started Aug 13 06:34:47 PM PDT 24
Finished Aug 13 06:34:48 PM PDT 24
Peak memory 207492 kb
Host smart-a94a221e-7baf-4234-850f-965f96b984c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19293
04992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1929304992
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3918354738
Short name T1346
Test name
Test status
Simulation time 2230395661 ps
CPU time 22.2 seconds
Started Aug 13 06:34:46 PM PDT 24
Finished Aug 13 06:35:08 PM PDT 24
Peak memory 224148 kb
Host smart-391fc3b7-af80-4e06-927f-0871668037e7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3918354738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3918354738
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2548979124
Short name T2288
Test name
Test status
Simulation time 189692579 ps
CPU time 0.89 seconds
Started Aug 13 06:34:45 PM PDT 24
Finished Aug 13 06:34:46 PM PDT 24
Peak memory 207524 kb
Host smart-7c2ceb8f-b959-4e84-865a-57b43b88c0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25489
79124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2548979124
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3536166049
Short name T613
Test name
Test status
Simulation time 156783495 ps
CPU time 0.85 seconds
Started Aug 13 06:34:46 PM PDT 24
Finished Aug 13 06:34:47 PM PDT 24
Peak memory 207408 kb
Host smart-b9d0f388-79b0-4f75-a246-6fc491a306c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35361
66049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3536166049
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.3046489761
Short name T1420
Test name
Test status
Simulation time 1262543660 ps
CPU time 2.76 seconds
Started Aug 13 06:34:45 PM PDT 24
Finished Aug 13 06:34:48 PM PDT 24
Peak memory 207768 kb
Host smart-0d8ca79e-ad42-4bf2-8dcd-39387253836a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30464
89761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3046489761
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2354921478
Short name T814
Test name
Test status
Simulation time 2095355807 ps
CPU time 61.58 seconds
Started Aug 13 06:34:47 PM PDT 24
Finished Aug 13 06:35:49 PM PDT 24
Peak memory 217348 kb
Host smart-98694343-512e-4709-b812-eb8ec5c9773c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23549
21478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2354921478
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.1992795746
Short name T601
Test name
Test status
Simulation time 7711482849 ps
CPU time 50.72 seconds
Started Aug 13 06:34:41 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 207784 kb
Host smart-0b7ad661-ed43-46e0-96dd-016dd534d5a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992795746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.1992795746
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_tx_rx_disruption.3098390442
Short name T1201
Test name
Test status
Simulation time 586632456 ps
CPU time 1.68 seconds
Started Aug 13 06:34:50 PM PDT 24
Finished Aug 13 06:34:52 PM PDT 24
Peak memory 207552 kb
Host smart-8c650968-dd01-41db-aa75-2a5aeff53821
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098390442 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.usbdev_tx_rx_disruption.3098390442
Directory /workspace/8.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/80.usbdev_endpoint_types.3330374251
Short name T110
Test name
Test status
Simulation time 323523815 ps
CPU time 1.16 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207584 kb
Host smart-d59ea23f-b700-479c-954c-1752b6a10fa3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3330374251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.3330374251
Directory /workspace/80.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/80.usbdev_tx_rx_disruption.1928189615
Short name T2822
Test name
Test status
Simulation time 491120220 ps
CPU time 1.72 seconds
Started Aug 13 06:40:59 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 207504 kb
Host smart-d447228c-a1d8-4ac3-ae39-8b84ddbfafb6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928189615 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.usbdev_tx_rx_disruption.1928189615
Directory /workspace/80.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/81.usbdev_endpoint_types.1882036223
Short name T3322
Test name
Test status
Simulation time 303345151 ps
CPU time 1.09 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:01 PM PDT 24
Peak memory 207564 kb
Host smart-af664f31-3802-4931-8e51-0e5c3c367dfe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1882036223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.1882036223
Directory /workspace/81.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/81.usbdev_tx_rx_disruption.2189988741
Short name T2774
Test name
Test status
Simulation time 573195907 ps
CPU time 1.5 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207472 kb
Host smart-81ad1cf0-6ff3-46d0-8484-978c2af30264
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189988741 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.usbdev_tx_rx_disruption.2189988741
Directory /workspace/81.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/82.usbdev_endpoint_types.2637296591
Short name T3628
Test name
Test status
Simulation time 264020207 ps
CPU time 1.09 seconds
Started Aug 13 06:41:27 PM PDT 24
Finished Aug 13 06:41:28 PM PDT 24
Peak memory 207532 kb
Host smart-55cddb5d-5986-411b-aa76-cb3e9f05f88e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2637296591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.2637296591
Directory /workspace/82.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/82.usbdev_tx_rx_disruption.131996644
Short name T1024
Test name
Test status
Simulation time 575541465 ps
CPU time 1.56 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207592 kb
Host smart-742f488f-07d3-4192-a075-2d9bd8ca50b7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131996644 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 82.usbdev_tx_rx_disruption.131996644
Directory /workspace/82.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/83.usbdev_endpoint_types.1275301289
Short name T3022
Test name
Test status
Simulation time 389361624 ps
CPU time 1.21 seconds
Started Aug 13 06:41:06 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207496 kb
Host smart-9005e010-9efc-405e-84f5-912b8792b59c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1275301289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.1275301289
Directory /workspace/83.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/83.usbdev_tx_rx_disruption.446392454
Short name T1922
Test name
Test status
Simulation time 457523559 ps
CPU time 1.47 seconds
Started Aug 13 06:41:00 PM PDT 24
Finished Aug 13 06:41:02 PM PDT 24
Peak memory 207536 kb
Host smart-0da97015-0a01-41e8-8091-b7f9df328d6f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446392454 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 83.usbdev_tx_rx_disruption.446392454
Directory /workspace/83.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/84.usbdev_endpoint_types.319640201
Short name T2614
Test name
Test status
Simulation time 263820482 ps
CPU time 1.12 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207476 kb
Host smart-a13a3d0d-c726-450b-857a-b893fc5287c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=319640201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.319640201
Directory /workspace/84.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/84.usbdev_tx_rx_disruption.3228203973
Short name T1254
Test name
Test status
Simulation time 633243092 ps
CPU time 1.81 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:04 PM PDT 24
Peak memory 207532 kb
Host smart-32d7a76c-ebcb-4256-a1e4-00ef3a2bbaa6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228203973 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.usbdev_tx_rx_disruption.3228203973
Directory /workspace/84.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/85.usbdev_endpoint_types.2233755644
Short name T480
Test name
Test status
Simulation time 410935369 ps
CPU time 1.29 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207532 kb
Host smart-f364a32f-23f3-436e-a703-2c578b45fc82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2233755644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.2233755644
Directory /workspace/85.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/85.usbdev_tx_rx_disruption.1529686542
Short name T2895
Test name
Test status
Simulation time 594507221 ps
CPU time 1.63 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207624 kb
Host smart-b27a7090-8817-4c6f-8eeb-8e1322af5e7c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529686542 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.usbdev_tx_rx_disruption.1529686542
Directory /workspace/85.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/86.usbdev_endpoint_types.1159506007
Short name T1279
Test name
Test status
Simulation time 168842579 ps
CPU time 0.92 seconds
Started Aug 13 06:41:08 PM PDT 24
Finished Aug 13 06:41:09 PM PDT 24
Peak memory 207552 kb
Host smart-9bf5f9ef-759d-42fe-93b3-605c00229e97
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1159506007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.1159506007
Directory /workspace/86.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/86.usbdev_tx_rx_disruption.251646856
Short name T1631
Test name
Test status
Simulation time 436442129 ps
CPU time 1.49 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207528 kb
Host smart-91675d6f-017b-4673-8e1e-24c2d65a00ba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251646856 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 86.usbdev_tx_rx_disruption.251646856
Directory /workspace/86.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/87.usbdev_tx_rx_disruption.1371606746
Short name T987
Test name
Test status
Simulation time 403829801 ps
CPU time 1.3 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207592 kb
Host smart-2d0ccefe-6d5a-4e1d-85bd-de140dd6e39b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371606746 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.usbdev_tx_rx_disruption.1371606746
Directory /workspace/87.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/88.usbdev_endpoint_types.2577978950
Short name T375
Test name
Test status
Simulation time 573648896 ps
CPU time 1.63 seconds
Started Aug 13 06:41:16 PM PDT 24
Finished Aug 13 06:41:18 PM PDT 24
Peak memory 207560 kb
Host smart-40151280-6034-4b08-afe3-4357c1ee0a10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2577978950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.2577978950
Directory /workspace/88.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/88.usbdev_tx_rx_disruption.1634246630
Short name T1190
Test name
Test status
Simulation time 469915346 ps
CPU time 1.5 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207608 kb
Host smart-28422ca2-a951-4b0b-af40-431f1811c063
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634246630 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.usbdev_tx_rx_disruption.1634246630
Directory /workspace/88.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/89.usbdev_endpoint_types.1364980578
Short name T439
Test name
Test status
Simulation time 522485624 ps
CPU time 1.54 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207480 kb
Host smart-32572d1e-08ac-4b73-926e-c8219c7940f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1364980578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.1364980578
Directory /workspace/89.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/89.usbdev_tx_rx_disruption.3866248359
Short name T760
Test name
Test status
Simulation time 563638916 ps
CPU time 1.44 seconds
Started Aug 13 06:41:07 PM PDT 24
Finished Aug 13 06:41:09 PM PDT 24
Peak memory 207560 kb
Host smart-d6f9d9ac-6499-41b6-bd58-906cf1d87ebc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866248359 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.usbdev_tx_rx_disruption.3866248359
Directory /workspace/89.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.287401613
Short name T1282
Test name
Test status
Simulation time 36074803 ps
CPU time 0.66 seconds
Started Aug 13 06:34:59 PM PDT 24
Finished Aug 13 06:34:59 PM PDT 24
Peak memory 207468 kb
Host smart-10f4e249-447d-497d-ab4d-d1fef472d210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=287401613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.287401613
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.99982835
Short name T96
Test name
Test status
Simulation time 12004760236 ps
CPU time 16.97 seconds
Started Aug 13 06:34:50 PM PDT 24
Finished Aug 13 06:35:07 PM PDT 24
Peak memory 207784 kb
Host smart-dc099d61-03e5-4b66-9535-e73b4d6593f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99982835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_
wake_disconnect.99982835
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3857159392
Short name T2890
Test name
Test status
Simulation time 15556453047 ps
CPU time 17.7 seconds
Started Aug 13 06:34:44 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 215988 kb
Host smart-fdc469db-522c-4a01-81ce-547e91e385b8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857159392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3857159392
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.869273222
Short name T1586
Test name
Test status
Simulation time 29424500591 ps
CPU time 41.76 seconds
Started Aug 13 06:34:52 PM PDT 24
Finished Aug 13 06:35:34 PM PDT 24
Peak memory 207820 kb
Host smart-c48b1210-01ee-4b12-a775-75e21e27d0b0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869273222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon
_wake_resume.869273222
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2286110864
Short name T21
Test name
Test status
Simulation time 170334579 ps
CPU time 0.92 seconds
Started Aug 13 06:34:51 PM PDT 24
Finished Aug 13 06:34:52 PM PDT 24
Peak memory 207476 kb
Host smart-f3491635-78de-48e1-b01b-5d25cf402715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22861
10864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2286110864
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1999092388
Short name T2035
Test name
Test status
Simulation time 184502212 ps
CPU time 0.85 seconds
Started Aug 13 06:34:51 PM PDT 24
Finished Aug 13 06:34:51 PM PDT 24
Peak memory 207696 kb
Host smart-99b27b51-3af5-45b9-aa4e-e25a0589df77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19990
92388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1999092388
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2567289154
Short name T2791
Test name
Test status
Simulation time 287613874 ps
CPU time 1.17 seconds
Started Aug 13 06:34:51 PM PDT 24
Finished Aug 13 06:34:52 PM PDT 24
Peak memory 207552 kb
Host smart-167bb749-6dc5-4875-becf-12b84ce143f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25672
89154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2567289154
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.4016586361
Short name T1753
Test name
Test status
Simulation time 889229828 ps
CPU time 2.36 seconds
Started Aug 13 06:34:51 PM PDT 24
Finished Aug 13 06:34:53 PM PDT 24
Peak memory 207776 kb
Host smart-245dec20-9617-468c-9bb7-0864f89485fc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4016586361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.4016586361
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.4072033149
Short name T185
Test name
Test status
Simulation time 40776009845 ps
CPU time 68.87 seconds
Started Aug 13 06:34:47 PM PDT 24
Finished Aug 13 06:35:56 PM PDT 24
Peak memory 207800 kb
Host smart-da0d6e2d-3423-444f-aa4d-9b523687e40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40720
33149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.4072033149
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.1249549962
Short name T3522
Test name
Test status
Simulation time 3838434822 ps
CPU time 33.75 seconds
Started Aug 13 06:34:45 PM PDT 24
Finished Aug 13 06:35:19 PM PDT 24
Peak memory 207852 kb
Host smart-636907b9-5f61-4082-b70d-1794329068cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249549962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.1249549962
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3329978109
Short name T1825
Test name
Test status
Simulation time 619545725 ps
CPU time 1.73 seconds
Started Aug 13 06:34:46 PM PDT 24
Finished Aug 13 06:34:48 PM PDT 24
Peak memory 207508 kb
Host smart-13f259e5-91f7-401b-b37a-cfd4633430dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33299
78109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3329978109
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1623948845
Short name T1905
Test name
Test status
Simulation time 147726001 ps
CPU time 0.86 seconds
Started Aug 13 06:34:47 PM PDT 24
Finished Aug 13 06:34:48 PM PDT 24
Peak memory 207536 kb
Host smart-6f487ea9-3f37-4caa-9f86-e3528fb226db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16239
48845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1623948845
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3417889194
Short name T1448
Test name
Test status
Simulation time 41073812 ps
CPU time 0.7 seconds
Started Aug 13 06:34:45 PM PDT 24
Finished Aug 13 06:34:46 PM PDT 24
Peak memory 207472 kb
Host smart-32f52cee-602e-42b7-a0d5-fde1d6a4d8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34178
89194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3417889194
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3417499243
Short name T2773
Test name
Test status
Simulation time 821643012 ps
CPU time 2.21 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:34:55 PM PDT 24
Peak memory 207784 kb
Host smart-8225dc6d-637f-481d-b028-88f37cc5b05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34174
99243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3417499243
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_types.2318978868
Short name T493
Test name
Test status
Simulation time 334265692 ps
CPU time 1.18 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 207428 kb
Host smart-3a50f696-12a2-40bf-b143-f15701f733db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2318978868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.2318978868
Directory /workspace/9.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1222310027
Short name T2417
Test name
Test status
Simulation time 296025171 ps
CPU time 2.48 seconds
Started Aug 13 06:34:55 PM PDT 24
Finished Aug 13 06:34:58 PM PDT 24
Peak memory 207532 kb
Host smart-39831043-b67a-40ae-92d8-6109f85eda5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12223
10027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1222310027
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.634122599
Short name T2733
Test name
Test status
Simulation time 202555322 ps
CPU time 1.09 seconds
Started Aug 13 06:34:51 PM PDT 24
Finished Aug 13 06:34:52 PM PDT 24
Peak memory 215924 kb
Host smart-73f18417-31e7-4f8c-9873-3b38491a1896
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=634122599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.634122599
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3189039808
Short name T2436
Test name
Test status
Simulation time 151047364 ps
CPU time 0.85 seconds
Started Aug 13 06:34:46 PM PDT 24
Finished Aug 13 06:34:47 PM PDT 24
Peak memory 207480 kb
Host smart-38dac9ec-af84-4fc9-b2aa-ded33d23dca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31890
39808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3189039808
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.601931052
Short name T2550
Test name
Test status
Simulation time 242903429 ps
CPU time 1.03 seconds
Started Aug 13 06:34:51 PM PDT 24
Finished Aug 13 06:34:52 PM PDT 24
Peak memory 207476 kb
Host smart-a122b01d-32f6-4a41-929d-93694696b536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60193
1052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.601931052
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.19929141
Short name T2933
Test name
Test status
Simulation time 4940651645 ps
CPU time 142.12 seconds
Started Aug 13 06:34:49 PM PDT 24
Finished Aug 13 06:37:11 PM PDT 24
Peak memory 215960 kb
Host smart-217cd6e8-4b50-4296-a5c7-744bf4d4133e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=19929141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.19929141
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.1471754329
Short name T806
Test name
Test status
Simulation time 5988339278 ps
CPU time 43.34 seconds
Started Aug 13 06:34:49 PM PDT 24
Finished Aug 13 06:35:33 PM PDT 24
Peak memory 207708 kb
Host smart-b86ffcbf-68e8-4147-9edb-695052a06a00
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1471754329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.1471754329
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3878133024
Short name T2055
Test name
Test status
Simulation time 253862985 ps
CPU time 0.98 seconds
Started Aug 13 06:34:46 PM PDT 24
Finished Aug 13 06:34:47 PM PDT 24
Peak memory 207424 kb
Host smart-f9bf32bf-6285-4e44-b0c9-af98d2a1c287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38781
33024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3878133024
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.859137728
Short name T2724
Test name
Test status
Simulation time 32437831442 ps
CPU time 49.28 seconds
Started Aug 13 06:34:56 PM PDT 24
Finished Aug 13 06:35:46 PM PDT 24
Peak memory 207772 kb
Host smart-45fc8aa2-2754-45c9-8028-fd19dbbfa2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85913
7728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.859137728
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3085669575
Short name T3010
Test name
Test status
Simulation time 4540693827 ps
CPU time 7.83 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 216912 kb
Host smart-fcbe1c28-fb2a-49b1-853b-304c120d0876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30856
69575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3085669575
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.4119972090
Short name T2177
Test name
Test status
Simulation time 3546862406 ps
CPU time 100.02 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:36:34 PM PDT 24
Peak memory 224148 kb
Host smart-19014a5e-2c50-42c5-973d-4cc063b9ee42
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4119972090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.4119972090
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.62257350
Short name T2866
Test name
Test status
Simulation time 2459368126 ps
CPU time 18.66 seconds
Started Aug 13 06:34:52 PM PDT 24
Finished Aug 13 06:35:11 PM PDT 24
Peak memory 217776 kb
Host smart-7e2ac75a-95db-444f-a847-2f6cb241096d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=62257350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.62257350
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3377108311
Short name T554
Test name
Test status
Simulation time 239665006 ps
CPU time 1.13 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:34:55 PM PDT 24
Peak memory 207552 kb
Host smart-9303d5c9-1756-4d63-9a6f-07341f429be6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3377108311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3377108311
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3548220736
Short name T633
Test name
Test status
Simulation time 201603899 ps
CPU time 0.93 seconds
Started Aug 13 06:34:55 PM PDT 24
Finished Aug 13 06:34:56 PM PDT 24
Peak memory 207524 kb
Host smart-9743abef-cedd-43c4-a38e-63cf5161cfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35482
20736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3548220736
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.3202082196
Short name T815
Test name
Test status
Simulation time 2109823420 ps
CPU time 20.36 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:35:14 PM PDT 24
Peak memory 217384 kb
Host smart-4fd1a5b8-e1b4-4524-8f2f-bb8cb531a363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32020
82196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.3202082196
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3167303665
Short name T2468
Test name
Test status
Simulation time 3169244384 ps
CPU time 34.72 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:35:28 PM PDT 24
Peak memory 218496 kb
Host smart-33671c0e-c4b6-4058-9ea6-80ba89bdbc14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3167303665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3167303665
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.692266788
Short name T842
Test name
Test status
Simulation time 3656610661 ps
CPU time 29.3 seconds
Started Aug 13 06:34:55 PM PDT 24
Finished Aug 13 06:35:24 PM PDT 24
Peak memory 217744 kb
Host smart-449794b6-6e46-4d88-9dbe-12b8f7e3f6dc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=692266788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.692266788
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.1497740574
Short name T1136
Test name
Test status
Simulation time 151853609 ps
CPU time 0.87 seconds
Started Aug 13 06:34:56 PM PDT 24
Finished Aug 13 06:34:57 PM PDT 24
Peak memory 207536 kb
Host smart-d2edb66e-6690-4cec-b246-eede2a4355fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1497740574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.1497740574
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.736804278
Short name T2902
Test name
Test status
Simulation time 141275761 ps
CPU time 0.83 seconds
Started Aug 13 06:34:58 PM PDT 24
Finished Aug 13 06:34:59 PM PDT 24
Peak memory 207492 kb
Host smart-b15dc31e-4ef7-40e7-829d-e254481ef2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73680
4278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.736804278
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.4168081669
Short name T130
Test name
Test status
Simulation time 197684809 ps
CPU time 0.98 seconds
Started Aug 13 06:34:56 PM PDT 24
Finished Aug 13 06:34:57 PM PDT 24
Peak memory 207512 kb
Host smart-c27c6ed0-f3d3-4356-bd30-94798234daba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41680
81669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.4168081669
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2733011097
Short name T1783
Test name
Test status
Simulation time 162713440 ps
CPU time 0.89 seconds
Started Aug 13 06:34:55 PM PDT 24
Finished Aug 13 06:34:56 PM PDT 24
Peak memory 207528 kb
Host smart-4c9fef87-deb4-4f31-828d-873eb7cd2a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27330
11097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2733011097
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2000678469
Short name T2553
Test name
Test status
Simulation time 182413368 ps
CPU time 0.92 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:03 PM PDT 24
Peak memory 207528 kb
Host smart-bc184215-3538-44e9-92da-6061fae9771c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20006
78469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2000678469
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2072012930
Short name T1961
Test name
Test status
Simulation time 163581507 ps
CPU time 0.86 seconds
Started Aug 13 06:34:55 PM PDT 24
Finished Aug 13 06:34:56 PM PDT 24
Peak memory 207548 kb
Host smart-d15832b7-6739-4d0f-9d77-a5af5a5320b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20720
12930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2072012930
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.551545516
Short name T3138
Test name
Test status
Simulation time 193579436 ps
CPU time 0.9 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 207604 kb
Host smart-a10c5f3e-deb2-4dcd-8708-5c5d46ae0a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55154
5516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.551545516
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1219945679
Short name T2256
Test name
Test status
Simulation time 179725552 ps
CPU time 0.97 seconds
Started Aug 13 06:35:04 PM PDT 24
Finished Aug 13 06:35:06 PM PDT 24
Peak memory 207600 kb
Host smart-ed7af108-8143-4999-a36f-502f5e08848a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1219945679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1219945679
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2324944441
Short name T3272
Test name
Test status
Simulation time 153773618 ps
CPU time 0.89 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:34:55 PM PDT 24
Peak memory 207496 kb
Host smart-d60304be-100a-4041-96c9-567b5c84b821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23249
44441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2324944441
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1010436588
Short name T2049
Test name
Test status
Simulation time 53511756 ps
CPU time 0.74 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:34:53 PM PDT 24
Peak memory 207496 kb
Host smart-c1109b60-c286-40db-8b9e-e78b94c5364d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
36588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1010436588
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.4158753566
Short name T1595
Test name
Test status
Simulation time 21978763914 ps
CPU time 58.18 seconds
Started Aug 13 06:34:57 PM PDT 24
Finished Aug 13 06:35:56 PM PDT 24
Peak memory 215948 kb
Host smart-38093540-ecce-4ed0-83ac-8638552c0c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41587
53566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.4158753566
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.976839967
Short name T2232
Test name
Test status
Simulation time 178544429 ps
CPU time 0.96 seconds
Started Aug 13 06:35:00 PM PDT 24
Finished Aug 13 06:35:01 PM PDT 24
Peak memory 207480 kb
Host smart-16a8ff2c-a1a8-4b8a-927e-9e70167ef758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97683
9967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.976839967
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1893775376
Short name T2710
Test name
Test status
Simulation time 175410128 ps
CPU time 1.03 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 207488 kb
Host smart-d21d4211-a329-49b6-a8fb-93d83b1e2029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18937
75376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1893775376
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2376556487
Short name T1438
Test name
Test status
Simulation time 5857771104 ps
CPU time 22.05 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:35:15 PM PDT 24
Peak memory 224036 kb
Host smart-faba4356-13ae-4343-bf7b-58221ec4c521
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376556487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2376556487
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3705631377
Short name T2446
Test name
Test status
Simulation time 5860459615 ps
CPU time 26.34 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:35:20 PM PDT 24
Peak memory 218928 kb
Host smart-6c9a4b3c-aaf4-45c6-8f4e-6a6dfe9f636d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3705631377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3705631377
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.3153367000
Short name T739
Test name
Test status
Simulation time 6842872431 ps
CPU time 37.89 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:35:32 PM PDT 24
Peak memory 219452 kb
Host smart-9a0e305e-57bb-4eee-a50f-c2bf1aa1c3de
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153367000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.3153367000
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2102106670
Short name T1002
Test name
Test status
Simulation time 228042283 ps
CPU time 1.01 seconds
Started Aug 13 06:34:55 PM PDT 24
Finished Aug 13 06:34:56 PM PDT 24
Peak memory 207436 kb
Host smart-4bb6bddf-380f-4e9d-a31f-2600b80d54b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21021
06670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2102106670
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1262197964
Short name T3413
Test name
Test status
Simulation time 194528176 ps
CPU time 1.09 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 207464 kb
Host smart-2f6d9c1a-f7be-4414-8006-1ef0910cbf46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
97964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1262197964
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_resume_link_active.4178288508
Short name T2817
Test name
Test status
Simulation time 20212162666 ps
CPU time 25 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:27 PM PDT 24
Peak memory 207628 kb
Host smart-fafa40c8-1bee-458a-9cd8-6e60aa3f55d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41782
88508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.4178288508
Directory /workspace/9.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.926303612
Short name T2735
Test name
Test status
Simulation time 145656958 ps
CPU time 0.84 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:34:55 PM PDT 24
Peak memory 207336 kb
Host smart-a0a65fed-ecaa-49b3-bf83-77e74d3e279a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92630
3612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.926303612
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_rx_full.536070895
Short name T1815
Test name
Test status
Simulation time 380241711 ps
CPU time 1.37 seconds
Started Aug 13 06:34:58 PM PDT 24
Finished Aug 13 06:34:59 PM PDT 24
Peak memory 207516 kb
Host smart-7e56e549-2061-46ef-af79-7d9833a3d020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53607
0895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.536070895
Directory /workspace/9.usbdev_rx_full/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2271470853
Short name T1210
Test name
Test status
Simulation time 161466239 ps
CPU time 0.83 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 207492 kb
Host smart-fe6b1842-abb2-40a5-a865-f802accedfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22714
70853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2271470853
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2042127051
Short name T3418
Test name
Test status
Simulation time 146056431 ps
CPU time 0.87 seconds
Started Aug 13 06:34:56 PM PDT 24
Finished Aug 13 06:34:57 PM PDT 24
Peak memory 207544 kb
Host smart-420d0014-1fec-42e4-958a-1a8427b980ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20421
27051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2042127051
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.943447636
Short name T2496
Test name
Test status
Simulation time 217304372 ps
CPU time 1.07 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:34:55 PM PDT 24
Peak memory 207484 kb
Host smart-856964fc-eb68-43ca-89cc-07964ec35026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94344
7636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.943447636
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.64670871
Short name T1738
Test name
Test status
Simulation time 2416851073 ps
CPU time 18.86 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 217948 kb
Host smart-2f81e144-2a97-4ba5-8a37-db03be7e7e68
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=64670871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.64670871
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3177738857
Short name T2081
Test name
Test status
Simulation time 159726489 ps
CPU time 0.9 seconds
Started Aug 13 06:34:53 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 207476 kb
Host smart-96ff70af-b096-45d9-861c-72a1c79967db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31777
38857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3177738857
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.56892717
Short name T2868
Test name
Test status
Simulation time 151920828 ps
CPU time 0.9 seconds
Started Aug 13 06:34:55 PM PDT 24
Finished Aug 13 06:34:56 PM PDT 24
Peak memory 207508 kb
Host smart-97e44658-ce21-46d6-a933-f20b041d491f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56892
717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.56892717
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3040819656
Short name T1686
Test name
Test status
Simulation time 1268386955 ps
CPU time 2.99 seconds
Started Aug 13 06:34:54 PM PDT 24
Finished Aug 13 06:34:57 PM PDT 24
Peak memory 207704 kb
Host smart-2bead58d-e817-4043-aa2a-58e994af2036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30408
19656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3040819656
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2645904559
Short name T571
Test name
Test status
Simulation time 3360633635 ps
CPU time 27.6 seconds
Started Aug 13 06:34:55 PM PDT 24
Finished Aug 13 06:35:23 PM PDT 24
Peak memory 217700 kb
Host smart-806465f9-8bb2-4896-bb8b-a22a9540ea8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26459
04559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2645904559
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.566564829
Short name T3365
Test name
Test status
Simulation time 704072986 ps
CPU time 16.3 seconds
Started Aug 13 06:34:47 PM PDT 24
Finished Aug 13 06:35:04 PM PDT 24
Peak memory 207676 kb
Host smart-8919d10b-2ff7-4b57-a1d6-a784f07fdfc5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566564829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host_
handshake.566564829
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_tx_rx_disruption.1742425218
Short name T3210
Test name
Test status
Simulation time 561639622 ps
CPU time 1.84 seconds
Started Aug 13 06:35:02 PM PDT 24
Finished Aug 13 06:35:04 PM PDT 24
Peak memory 207604 kb
Host smart-27af26be-2c34-4544-9662-27771dbd4d76
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742425218 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.usbdev_tx_rx_disruption.1742425218
Directory /workspace/9.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/90.usbdev_endpoint_types.2615902142
Short name T361
Test name
Test status
Simulation time 499735688 ps
CPU time 1.4 seconds
Started Aug 13 06:41:13 PM PDT 24
Finished Aug 13 06:41:15 PM PDT 24
Peak memory 207528 kb
Host smart-986505bb-2da5-4022-bcf0-04b119829f80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2615902142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.2615902142
Directory /workspace/90.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/90.usbdev_tx_rx_disruption.1868331133
Short name T607
Test name
Test status
Simulation time 450026741 ps
CPU time 1.46 seconds
Started Aug 13 06:41:14 PM PDT 24
Finished Aug 13 06:41:16 PM PDT 24
Peak memory 207604 kb
Host smart-6c594cb5-b1de-4849-a388-aff864919b75
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868331133 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.usbdev_tx_rx_disruption.1868331133
Directory /workspace/90.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/91.usbdev_tx_rx_disruption.4011869380
Short name T3376
Test name
Test status
Simulation time 600529748 ps
CPU time 1.6 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207524 kb
Host smart-589cd81e-30da-41ca-8de4-807803fb7be2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011869380 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.usbdev_tx_rx_disruption.4011869380
Directory /workspace/91.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/92.usbdev_endpoint_types.1570713457
Short name T380
Test name
Test status
Simulation time 441188244 ps
CPU time 1.27 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207520 kb
Host smart-ceeb3ff7-728a-413d-a3da-40155b8f6c10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1570713457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.1570713457
Directory /workspace/92.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/92.usbdev_tx_rx_disruption.1413715287
Short name T3446
Test name
Test status
Simulation time 535276913 ps
CPU time 1.55 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207572 kb
Host smart-d0918cd9-9b80-4dab-8677-2f7330660a4b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413715287 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.usbdev_tx_rx_disruption.1413715287
Directory /workspace/92.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/93.usbdev_endpoint_types.2665102711
Short name T362
Test name
Test status
Simulation time 539510428 ps
CPU time 1.47 seconds
Started Aug 13 06:41:05 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 207560 kb
Host smart-a517a016-8de2-42bb-8864-f6809178bae4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2665102711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.2665102711
Directory /workspace/93.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/93.usbdev_tx_rx_disruption.2711121594
Short name T3394
Test name
Test status
Simulation time 543898861 ps
CPU time 1.58 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207556 kb
Host smart-297e7c0c-46d1-4f82-9a98-c92c9aa11626
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711121594 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.usbdev_tx_rx_disruption.2711121594
Directory /workspace/93.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/94.usbdev_endpoint_types.2175513902
Short name T217
Test name
Test status
Simulation time 450034392 ps
CPU time 1.39 seconds
Started Aug 13 06:41:07 PM PDT 24
Finished Aug 13 06:41:09 PM PDT 24
Peak memory 207516 kb
Host smart-c4514ddb-00df-4dfc-8cb2-45673ae5619e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2175513902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.2175513902
Directory /workspace/94.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/94.usbdev_tx_rx_disruption.1222331270
Short name T2183
Test name
Test status
Simulation time 661530042 ps
CPU time 1.73 seconds
Started Aug 13 06:41:08 PM PDT 24
Finished Aug 13 06:41:10 PM PDT 24
Peak memory 207556 kb
Host smart-a32a4211-41a1-4de5-9933-767720bf26b2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222331270 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.usbdev_tx_rx_disruption.1222331270
Directory /workspace/94.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/95.usbdev_endpoint_types.2039681388
Short name T405
Test name
Test status
Simulation time 528632744 ps
CPU time 1.47 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207560 kb
Host smart-c1fd0a0e-dd78-4510-b69c-da0fd5076bf0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2039681388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.2039681388
Directory /workspace/95.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/95.usbdev_tx_rx_disruption.1571793988
Short name T3179
Test name
Test status
Simulation time 537710881 ps
CPU time 1.53 seconds
Started Aug 13 06:41:04 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 207608 kb
Host smart-958be5f0-a571-4d67-80f9-cf2b08ffc887
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571793988 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.usbdev_tx_rx_disruption.1571793988
Directory /workspace/95.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/96.usbdev_endpoint_types.376369405
Short name T394
Test name
Test status
Simulation time 587530849 ps
CPU time 1.68 seconds
Started Aug 13 06:41:03 PM PDT 24
Finished Aug 13 06:41:05 PM PDT 24
Peak memory 207556 kb
Host smart-a3095560-bf2c-42e8-b5d3-6fcf6f84b373
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=376369405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.376369405
Directory /workspace/96.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/96.usbdev_tx_rx_disruption.4119143031
Short name T70
Test name
Test status
Simulation time 485120865 ps
CPU time 1.52 seconds
Started Aug 13 06:41:10 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 207608 kb
Host smart-c0f5177c-5dcf-488d-b150-94e970510223
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119143031 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.usbdev_tx_rx_disruption.4119143031
Directory /workspace/96.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/97.usbdev_endpoint_types.2973711927
Short name T83
Test name
Test status
Simulation time 523863877 ps
CPU time 1.38 seconds
Started Aug 13 06:41:11 PM PDT 24
Finished Aug 13 06:41:12 PM PDT 24
Peak memory 207568 kb
Host smart-1937b2ec-6c66-4b4d-bb79-745ca9a841c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2973711927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.2973711927
Directory /workspace/97.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/97.usbdev_tx_rx_disruption.517009994
Short name T2205
Test name
Test status
Simulation time 536181625 ps
CPU time 1.61 seconds
Started Aug 13 06:41:12 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207628 kb
Host smart-94bd17c7-3ff3-41fa-a00a-2ba2cd84a991
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517009994 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 97.usbdev_tx_rx_disruption.517009994
Directory /workspace/97.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/98.usbdev_endpoint_types.3164777661
Short name T2673
Test name
Test status
Simulation time 637330093 ps
CPU time 1.63 seconds
Started Aug 13 06:41:34 PM PDT 24
Finished Aug 13 06:41:36 PM PDT 24
Peak memory 207564 kb
Host smart-06ced13d-78bc-434e-b83b-b26fe8b9f8f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3164777661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.3164777661
Directory /workspace/98.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/98.usbdev_tx_rx_disruption.1005377721
Short name T1860
Test name
Test status
Simulation time 460987208 ps
CPU time 1.42 seconds
Started Aug 13 06:41:12 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207632 kb
Host smart-7dc624a9-df18-4061-a920-99cc844c47d0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005377721 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.usbdev_tx_rx_disruption.1005377721
Directory /workspace/98.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/99.usbdev_endpoint_types.328538889
Short name T2190
Test name
Test status
Simulation time 155565134 ps
CPU time 0.87 seconds
Started Aug 13 06:41:02 PM PDT 24
Finished Aug 13 06:41:03 PM PDT 24
Peak memory 207588 kb
Host smart-9a4abaa3-2645-4826-90d7-75b303ed4920
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=328538889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.328538889
Directory /workspace/99.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/99.usbdev_tx_rx_disruption.3163484081
Short name T120
Test name
Test status
Simulation time 520122936 ps
CPU time 1.61 seconds
Started Aug 13 06:41:12 PM PDT 24
Finished Aug 13 06:41:14 PM PDT 24
Peak memory 207632 kb
Host smart-ec0726fc-27a2-4f63-a814-0c385d60a4b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163484081 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.usbdev_tx_rx_disruption.3163484081
Directory /workspace/99.usbdev_tx_rx_disruption/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%