Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	81705	1			T1	3		T2	2		T3	2
all_values[1]	81705	1			T1	3		T2	2		T3	2
all_values[2]	81705	1			T1	3		T2	2		T3	2
all_values[3]	81705	1			T1	3		T2	2		T3	2
all_values[4]	81705	1			T1	3		T2	2		T3	2
all_values[5]	81705	1			T1	3		T2	2		T3	2
all_values[6]	81705	1			T1	3		T2	2		T3	2
all_values[7]	81705	1			T1	3		T2	2		T3	2
all_values[8]	81705	1			T1	3		T2	2		T3	2
all_values[9]	81705	1			T1	3		T2	2		T3	2
all_values[10]	81705	1			T1	3		T2	2		T3	2
all_values[11]	81705	1			T1	3		T2	2		T3	2
all_values[12]	81705	1			T1	3		T2	2		T3	2
all_values[13]	81705	1			T1	3		T2	2		T3	2
all_values[14]	81705	1			T1	3		T2	2		T3	2
all_values[15]	81705	1			T1	3		T2	2		T3	2
all_values[16]	81705	1			T1	3		T2	2		T3	2
all_values[17]	81705	1			T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2604818

1

T1

94

T2

64

T3

64

auto[1]

9742

1

T1

2

T26

2

T30

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2168802

1

T1

85

T2

61

T3

55

auto[1]

445758

1

T1

11

T2

3

T3

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	53035	1			T1	3		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	25346	1			T27	1		T34	6		T90	1
all_values[0]	auto[1]	auto[0]	3220	1			T32	5		T33	5		T44	5
all_values[0]	auto[1]	auto[1]	104	1			T358	1		T359	1		T360	1
all_values[1]	auto[0]	auto[0]	77227	1			T1	3		T2	2		T26	2
all_values[1]	auto[0]	auto[1]	3080	1			T3	2		T28	2		T29	2
all_values[1]	auto[1]	auto[0]	524	1			T26	1		T30	2		T45	2
all_values[1]	auto[1]	auto[1]	874	1			T26	1		T30	12		T45	12
all_values[2]	auto[0]	auto[0]	4242	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	77214	1			T1	2		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	136	1			T36	1		T42	1		T43	1
all_values[2]	auto[1]	auto[1]	113	1			T36	1		T42	1		T43	1
all_values[3]	auto[0]	auto[0]	79763	1			T1	3		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	298	1			T3	1		T29	1		T65	1
all_values[3]	auto[1]	auto[0]	1575	1			T66	1483		T233	2		T230	1
all_values[3]	auto[1]	auto[1]	69	1			T66	1		T233	3		T230	3
all_values[4]	auto[0]	auto[0]	4218	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	77331	1			T1	2		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	86	1			T67	1		T233	1		T230	1
all_values[4]	auto[1]	auto[1]	70	1			T67	1		T230	1		T234	2
all_values[5]	auto[0]	auto[0]	81205	1			T1	3		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	353	1			T3	1		T26	1		T6	1
all_values[5]	auto[1]	auto[0]	91	1			T230	3		T231	2		T232	1
all_values[5]	auto[1]	auto[1]	56	1			T230	1		T231	4		T232	4
all_values[6]	auto[0]	auto[0]	81296	1			T1	3		T2	2		T3	1
all_values[6]	auto[0]	auto[1]	208	1			T3	1		T26	1		T68	1
all_values[6]	auto[1]	auto[0]	103	1			T233	1		T230	4		T234	1
all_values[6]	auto[1]	auto[1]	98	1			T69	1		T70	1		T71	1
all_values[7]	auto[0]	auto[0]	24897	1			T1	3		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	56630	1			T26	2		T27	4		T28	2
all_values[7]	auto[1]	auto[0]	119	1			T46	1		T230	1		T234	1
all_values[7]	auto[1]	auto[1]	59	1			T46	1		T233	2		T234	1
all_values[8]	auto[0]	auto[0]	80963	1			T1	3		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	51	1			T233	2		T234	2		T231	2
all_values[8]	auto[1]	auto[0]	601	1			T50	10		T51	10		T52	10
all_values[8]	auto[1]	auto[1]	90	1			T47	1		T48	1		T49	1
all_values[9]	auto[0]	auto[0]	81460	1			T1	3		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	52	1			T233	3		T230	1		T234	1
all_values[9]	auto[1]	auto[0]	119	1			T62	3		T63	3		T64	3
all_values[9]	auto[1]	auto[1]	74	1			T62	2		T63	2		T64	2
all_values[10]	auto[0]	auto[0]	81172	1			T1	3		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	365	1			T59	3		T60	1		T61	1
all_values[10]	auto[1]	auto[0]	106	1			T233	2		T230	1		T234	5
all_values[10]	auto[1]	auto[1]	62	1			T231	5		T331	1		T354	1
all_values[11]	auto[0]	auto[0]	80666	1			T1	2		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	755	1			T1	1		T33	3		T44	3
all_values[11]	auto[1]	auto[0]	164	1			T75	1		T76	1		T77	1
all_values[11]	auto[1]	auto[1]	120	1			T75	1		T76	1		T77	1
all_values[12]	auto[0]	auto[0]	81328	1			T1	3		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	215	1			T78	3		T80	3		T83	3
all_values[12]	auto[1]	auto[0]	95	1			T79	2		T81	2		T82	2
all_values[12]	auto[1]	auto[1]	67	1			T79	1		T81	1		T82	1
all_values[13]	auto[0]	auto[0]	81381	1			T1	1		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	73	1			T86	1		T87	1		T88	1
all_values[13]	auto[1]	auto[0]	140	1			T1	1		T84	1		T85	1
all_values[13]	auto[1]	auto[1]	111	1			T1	1		T84	1		T85	1
all_values[14]	auto[0]	auto[0]	15758	1			T1	3		T2	2		T3	1
all_values[14]	auto[0]	auto[1]	65771	1			T3	1		T26	2		T29	1
all_values[14]	auto[1]	auto[0]	107	1			T233	1		T230	3		T234	1
all_values[14]	auto[1]	auto[1]	69	1			T233	2		T234	3		T231	1
all_values[15]	auto[0]	auto[0]	4278	1			T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	77275	1			T1	2		T2	1		T3	1
all_values[15]	auto[1]	auto[0]	99	1			T234	3		T231	2		T232	4
all_values[15]	auto[1]	auto[1]	53	1			T230	1		T231	1		T353	1
all_values[16]	auto[0]	auto[0]	80687	1			T1	3		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	821	1			T29	1		T31	1		T44	3
all_values[16]	auto[1]	auto[0]	117	1			T72	4		T73	4		T74	4
all_values[16]	auto[1]	auto[1]	80	1			T72	4		T73	4		T74	4
all_values[17]	auto[0]	auto[0]	23840	1			T2	2		T3	2		T26	2
all_values[17]	auto[0]	auto[1]	57694	1			T1	3		T26	2		T27	4
all_values[17]	auto[1]	auto[0]	114	1			T56	1		T57	1		T58	1
all_values[17]	auto[1]	auto[1]	57	1			T56	1		T57	1		T58	1