Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1161	1			T29	3		T257	1		T361	1
range_16_to_126	148691	1			T2	7		T3	65		T26	2
fifteen	1703	1			T29	3		T395	1		T403	1
range_2_to_14	20797	1			T29	46		T352	24		T288	370
seven	1922	1			T29	3		T162	117		T263	1
one	609	1			T29	9		T436	1		T424	1
zero	421	1			T1	1		T29	6		T84	1

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

12205

1

T29

74

T30

2

T45

2

three

11851

1

T3

13

T28

3

T29

76

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	13	1			T172	1		T520	1		T414	1
range_127	three	19	1			T521	1		T115	1		T522	3
range_16_to_126	seven	10825	1			T29	68		T30	2		T45	2
range_16_to_126	three	10261	1			T3	13		T28	3		T29	71
fifteen	seven	112	1			T29	1		T523	31		T253	1
fifteen	three	121	1			T29	1		T115	1		T181	1
range_2_to_14	seven	1194	1			T29	5		T352	2		T288	32
range_2_to_14	three	1391	1			T29	3		T352	2		T288	37
seven	seven	142	1			T162	13		T297	75		T502	2
seven	three	172	1			T524	77		T115	1		T297	62
one	seven	36	1			T114	1		T379	1		T253	1
one	three	29	1			T29	1		T114	2		T525	1
zero	seven	25	1			T253	1		T526	1		T503	1
zero	three	30	1			T192	2		T526	1		T502	2