Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107801

1

T1

1

T2

4

T3

30

auto[1]

44662

1

T3

30

T26

1

T28

2

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29312	1			T27	1		T4	2		T34	6
max_len_m1	834	1			T30	2		T32	1		T35	1
max_len_m2	835	1			T3	4		T4	6		T5	2
max_len_m3	800	1			T3	2		T4	2		T32	1
five	1079	1			T116	2		T288	10		T193	2
four	1197	1			T4	2		T91	1		T288	7
three	754	1			T26	2		T30	2		T35	1
one	822	1			T352	2		T16	1		T288	8
zero	11688	1			T1	1		T28	2		T30	2

---

Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24270	1			T27	1		T4	1		T34	6
max_len	auto[1]	5042	1			T4	1		T45	1		T116	1
max_len_m1	auto[0]	577	1			T30	1		T32	1		T35	1
max_len_m1	auto[1]	257	1			T30	1		T45	1		T116	1
max_len_m2	auto[0]	562	1			T3	2		T4	3		T5	1
max_len_m2	auto[1]	273	1			T3	2		T4	3		T5	1
max_len_m3	auto[0]	549	1			T3	1		T4	1		T32	1
max_len_m3	auto[1]	251	1			T3	1		T4	1		T5	1
five	auto[0]	579	1			T116	1		T288	6		T193	1
five	auto[1]	500	1			T116	1		T288	4		T193	1
four	auto[0]	614	1			T4	1		T91	1		T288	4
four	auto[1]	583	1			T4	1		T288	3		T198	1
three	auto[0]	383	1			T26	1		T30	1		T35	1
three	auto[1]	371	1			T26	1		T30	1		T288	2
one	auto[0]	350	1			T352	1		T288	3		T320	3
one	auto[1]	472	1			T352	1		T16	1		T288	5
zero	auto[0]	535	1			T1	1		T30	1		T91	1
zero	auto[1]	11153	1			T28	2		T30	1		T35	8