Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69613

1

T3

30

T26

1

T27

1

auto[1]

76641

1

T3

60

T26

2

T28

4

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	11529	1			T29	20		T30	3		T31	1
endpoints[0x1]	11963	1			T26	3		T27	1		T29	10
endpoints[0x2]	14121	1			T29	21		T30	3		T32	8
endpoints[0x3]	11034	1			T3	18		T28	5		T29	32
endpoints[0x4]	12610	1			T3	18		T29	17		T30	3
endpoints[0x5]	13238	1			T30	3		T34	6		T44	4
endpoints[0x6]	14350	1			T3	18		T30	3		T90	1
endpoints[0x7]	11363	1			T29	47		T30	3		T45	3
endpoints[0x8]	13641	1			T3	18		T29	17		T30	3
endpoints[0x9]	11966	1			T3	18		T30	3		T45	3
endpoints[0xa]	10048	1			T30	3		T4	156		T45	3
endpoints[0xb]	10391	1			T29	13		T30	3		T33	4

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	183	1			T61	5		T111	5		T112	7
ack	37756	1			T3	30		T26	1		T28	2
data1	50361	1			T3	29		T28	2		T29	50
data0	57888	1			T3	31		T26	2		T27	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	12	1			T342	1		T343	1		T344	1
nak	auto[1]	endpoints[0x1]	15	1			T61	2		T345	1		T346	1
nak	auto[1]	endpoints[0x2]	14	1			T111	1		T112	1		T346	3
nak	auto[1]	endpoints[0x3]	16	1			T111	1		T112	1		T347	1
nak	auto[1]	endpoints[0x4]	8	1			T348	2		T349	1		T350	1
nak	auto[1]	endpoints[0x5]	15	1			T61	1		T345	1		T346	1
nak	auto[1]	endpoints[0x6]	18	1			T61	1		T345	1		T351	2
nak	auto[1]	endpoints[0x7]	21	1			T111	1		T112	3		T343	1
nak	auto[1]	endpoints[0x8]	15	1			T61	1		T345	2		T346	1
nak	auto[1]	endpoints[0x9]	19	1			T112	1		T345	1		T346	1
nak	auto[1]	endpoints[0xa]	19	1			T111	1		T345	1		T343	1
nak	auto[1]	endpoints[0xb]	11	1			T111	1		T112	1		T345	1
ack	auto[1]	endpoints[0x0]	2969	1			T29	10		T30	1		T33	2
ack	auto[1]	endpoints[0x1]	3012	1			T26	1		T29	5		T30	1
ack	auto[1]	endpoints[0x2]	3001	1			T30	1		T32	2		T35	8
ack	auto[1]	endpoints[0x3]	3028	1			T3	6		T28	2		T29	7
ack	auto[1]	endpoints[0x4]	3218	1			T3	6		T30	1		T45	1
ack	auto[1]	endpoints[0x5]	3338	1			T30	1		T44	1		T45	1
ack	auto[1]	endpoints[0x6]	3325	1			T3	6		T30	1		T44	2
ack	auto[1]	endpoints[0x7]	2947	1			T29	13		T30	1		T45	1
ack	auto[1]	endpoints[0x8]	3262	1			T3	6		T30	1		T45	1
ack	auto[1]	endpoints[0x9]	3395	1			T3	6		T30	1		T45	1
ack	auto[1]	endpoints[0xa]	3053	1			T30	1		T4	52		T45	1
ack	auto[1]	endpoints[0xb]	3208	1			T30	1		T33	1		T45	1
data1	auto[0]	endpoints[0x0]	2316	1			T33	2		T91	1		T107	2
data1	auto[0]	endpoints[0x1]	2507	1			T32	1		T91	2		T5	2
data1	auto[0]	endpoints[0x2]	3581	1			T29	11		T32	2		T35	2
data1	auto[0]	endpoints[0x3]	1972	1			T3	3		T28	1		T29	2
data1	auto[0]	endpoints[0x4]	2612	1			T3	2		T29	6		T116	25
data1	auto[0]	endpoints[0x5]	2794	1			T34	3		T44	1		T89	1
data1	auto[0]	endpoints[0x6]	3389	1			T3	3		T44	2		T5	2
data1	auto[0]	endpoints[0x7]	2305	1			T29	10		T19	4		T288	6
data1	auto[0]	endpoints[0x8]	3080	1			T3	3		T5	2		T50	3
data1	auto[0]	endpoints[0x9]	2080	1			T3	3		T5	2		T197	25
data1	auto[0]	endpoints[0xa]	1563	1			T4	26		T5	2		T16	2
data1	auto[0]	endpoints[0xb]	1493	1			T33	1		T5	2		T107	1
data1	auto[1]	endpoints[0x0]	1641	1			T29	5		T33	2		T91	1
data1	auto[1]	endpoints[0x1]	1646	1			T29	4		T32	1		T91	2
data1	auto[1]	endpoints[0x2]	1663	1			T32	2		T35	3		T288	6
data1	auto[1]	endpoints[0x3]	1671	1			T3	3		T28	1		T29	3
data1	auto[1]	endpoints[0x4]	1759	1			T3	3		T116	25		T19	4
data1	auto[1]	endpoints[0x5]	1845	1			T44	1		T89	1		T19	5
data1	auto[1]	endpoints[0x6]	1814	1			T3	3		T44	2		T5	2
data1	auto[1]	endpoints[0x7]	1600	1			T29	9		T5	5		T19	4
data1	auto[1]	endpoints[0x8]	1782	1			T3	3		T5	2		T288	8
data1	auto[1]	endpoints[0x9]	1868	1			T3	3		T5	3		T197	25
data1	auto[1]	endpoints[0xa]	1643	1			T4	26		T5	3		T16	2
data1	auto[1]	endpoints[0xb]	1737	1			T33	1		T5	2		T107	1
data0	auto[0]	endpoints[0x0]	3176	1			T30	1		T31	1		T33	2
data0	auto[0]	endpoints[0x1]	3329	1			T26	1		T27	1		T30	1
data0	auto[0]	endpoints[0x2]	4456	1			T29	10		T30	1		T32	2
data0	auto[0]	endpoints[0x3]	2923	1			T3	3		T29	16		T30	1
data0	auto[0]	endpoints[0x4]	3468	1			T3	4		T29	11		T30	1
data0	auto[0]	endpoints[0x5]	3671	1			T30	1		T34	3		T44	1
data0	auto[0]	endpoints[0x6]	4226	1			T3	3		T30	1		T90	1
data0	auto[0]	endpoints[0x7]	3083	1			T29	11		T30	1		T45	1
data0	auto[0]	endpoints[0x8]	3937	1			T3	3		T29	17		T30	1
data0	auto[0]	endpoints[0x9]	2987	1			T3	3		T30	1		T45	1
data0	auto[0]	endpoints[0xa]	2269	1			T30	1		T4	26		T45	1
data0	auto[0]	endpoints[0xb]	2380	1			T29	13		T30	1		T33	1
data0	auto[1]	endpoints[0x0]	1411	1			T29	5		T30	1		T45	1
data0	auto[1]	endpoints[0x1]	1449	1			T26	1		T29	1		T30	1
data0	auto[1]	endpoints[0x2]	1398	1			T30	1		T35	5		T45	1
data0	auto[1]	endpoints[0x3]	1419	1			T3	3		T28	1		T29	4
data0	auto[1]	endpoints[0x4]	1536	1			T3	3		T30	1		T45	1
data0	auto[1]	endpoints[0x5]	1573	1			T30	1		T45	1		T352	1
data0	auto[1]	endpoints[0x6]	1570	1			T3	3		T30	1		T45	1
data0	auto[1]	endpoints[0x7]	1403	1			T29	4		T30	1		T45	1
data0	auto[1]	endpoints[0x8]	1562	1			T3	3		T30	1		T45	1
data0	auto[1]	endpoints[0x9]	1613	1			T3	3		T30	1		T45	1
data0	auto[1]	endpoints[0xa]	1495	1			T30	1		T4	26		T45	1
data0	auto[1]	endpoints[0xb]	1554	1			T30	1		T45	1		T5	3