Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	0	16	100.00	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8158

1

T2

1

T29

145

T263

3

auto[1]

52167

1

T2

2

T3

35

T26

1

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53159

1

T2

3

T3

35

T26

1

auto[1]

7166

1

T65

94

T18

1

T94

65

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54809

1

T3

35

T26

1

T28

2

auto[1]

5516

1

T2

3

T29

117

T123

1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

4303

1

T2

1

T29

71

T436

1

pkt_types[PidTypeInToken]

56022

1

T2

2

T3

35

T26

1

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

1342

1

T29

21

T257

4

T361

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

737

1

T29

17

T406

1

T114

22

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

92

1

T257

2

T258

1

T406

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

18

1

T436

1

T424

1

T422

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

1360

1

T29

21

T258

2

T114

16

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

637

1

T2

1

T29

12

T424

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

97

1

T442

1

T258

2

T262

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

20

1

T251

1

T442

1

T248

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3756

1

T29

50

T395

2

T442

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2108

1

T2

1

T29

57

T263

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

50

1

T249

2

T403

1

T251

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

55

1

T263

2

T249

1

T436

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

41328

1

T3

35

T26

1

T28

2

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

1891

1

T2

1

T29

31

T123

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

6784

1

T65

94

T18

1

T94

65

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

50

1

T249

2

T395

1

T403

1