Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.46	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	1	10	90.91
Crosses	54	39	15	27.78

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	1	2	66.67	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	39	15	27.78	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19601	1			T3	30		T4	52		T5	40
solo	73190	1			T1	1		T2	2		T26	1
empty	3945	1			T2	1		T29	12		T32	3

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19649	1			T3	30		T4	52		T5	40
solo	30667	1			T2	3		T29	551		T32	3
empty	46464	1			T1	1		T26	1		T27	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

75283

1

T1

1

T2

1

T3

29

setup

21650

1

T2

2

T3

1

T29

304

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_rx

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
full	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

solo

42

1

T47

1

T48

1

T49

1

empty

82424

1

T1

1

T2

3

T3

30

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	39	15	27.78	39

Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[full]	[full]	[full , solo]	*	--	--	4
[full]	[solo]	*	*	--	--	6
[full]	[empty]	[full]	*	--	--	2
[solo]	[full]	[full , solo]	*	--	--	4
[solo]	[solo]	[full]	*	--	--	2
[solo]	[empty]	[full]	*	--	--	2
[empty]	[full , solo]	[full , solo]	*	--	--	8
[empty]	[empty]	[full , solo]	*	--	--	4

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[full]	[empty]	[solo , empty]	[out]	--	--	2
[solo]	[full]	[empty]	[setup]	0	1	1
[solo]	[empty]	[solo , empty]	[out]	--	--	2
[empty]	[full , solo]	[empty]	[setup]	--	--	2

Covered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	full	empty	out	15592	1			T3	29		T4	52		T5	32
full	full	empty	setup	3994	1			T3	1		T5	8		T19	11
full	empty	solo	setup	6	1			T47	1		T334	1		T335	1
full	empty	empty	setup	10	1			T336	1		T337	1		T338	1
solo	full	empty	out	5	1			T53	1		T54	1		T55	1
solo	solo	solo	out	5	1			T53	1		T54	1		T55	1
solo	solo	solo	setup	5	1			T53	1		T54	1		T55	1
solo	solo	empty	out	7923	1			T2	1		T29	134		T263	2
solo	solo	empty	setup	8122	1			T2	1		T29	151		T79	1
solo	empty	solo	setup	2	1			T339	1		T340	1		-	-
solo	empty	empty	setup	2076	1			T2	1		T29	5		T32	3
empty	full	empty	out	1	1			T341	1		-	-		-	-
empty	solo	empty	out	44225	1			T1	1		T26	1		T27	1
empty	empty	empty	out	271	1			T33	1		T91	1		T268	1
empty	empty	empty	setup	167	1			T44	1		T89	1		T107	1