Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	81705	1			T1	3		T2	2		T3	2
all_pins[1]	81705	1			T1	3		T2	2		T3	2
all_pins[2]	81705	1			T1	3		T2	2		T3	2
all_pins[3]	81705	1			T1	3		T2	2		T3	2
all_pins[4]	81705	1			T1	3		T2	2		T3	2
all_pins[5]	81705	1			T1	3		T2	2		T3	2
all_pins[6]	81705	1			T1	3		T2	2		T3	2
all_pins[7]	81705	1			T1	3		T2	2		T3	2
all_pins[8]	81705	1			T1	3		T2	2		T3	2
all_pins[9]	81705	1			T1	3		T2	2		T3	2
all_pins[10]	81705	1			T1	3		T2	2		T3	2
all_pins[11]	81705	1			T1	3		T2	2		T3	2
all_pins[12]	81705	1			T1	3		T2	2		T3	2
all_pins[13]	81705	1			T1	3		T2	2		T3	2
all_pins[14]	81705	1			T1	3		T2	2		T3	2
all_pins[15]	81705	1			T1	3		T2	2		T3	2
all_pins[16]	81705	1			T1	3		T2	2		T3	2
all_pins[17]	81705	1			T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2612334	1			T1	95		T2	64		T3	64
values[0x1]	2226	1			T1	1		T26	1		T30	12
transitions[0x0=>0x1]	1972	1			T1	1		T26	1		T30	12
transitions[0x1=>0x0]	1972	1			T1	1		T26	1		T30	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	81601	1			T1	3		T2	2		T3	2
all_pins[0]	values[0x1]	104	1			T358	1		T359	1		T360	1
all_pins[0]	transitions[0x0=>0x1]	87	1			T358	1		T359	1		T360	1
all_pins[0]	transitions[0x1=>0x0]	857	1			T26	1		T30	12		T45	12
all_pins[1]	values[0x0]	80831	1			T1	3		T2	2		T3	2
all_pins[1]	values[0x1]	874	1			T26	1		T30	12		T45	12
all_pins[1]	transitions[0x0=>0x1]	858	1			T26	1		T30	12		T45	12
all_pins[1]	transitions[0x1=>0x0]	97	1			T36	1		T42	1		T43	1
all_pins[2]	values[0x0]	81592	1			T1	3		T2	2		T3	2
all_pins[2]	values[0x1]	113	1			T36	1		T42	1		T43	1
all_pins[2]	transitions[0x0=>0x1]	91	1			T36	1		T42	1		T43	1
all_pins[2]	transitions[0x1=>0x0]	47	1			T66	1		T233	3		T230	3
all_pins[3]	values[0x0]	81636	1			T1	3		T2	2		T3	2
all_pins[3]	values[0x1]	69	1			T66	1		T233	3		T230	3
all_pins[3]	transitions[0x0=>0x1]	52	1			T66	1		T233	3		T230	2
all_pins[3]	transitions[0x1=>0x0]	53	1			T67	1		T231	2		T354	2
all_pins[4]	values[0x0]	81635	1			T1	3		T2	2		T3	2
all_pins[4]	values[0x1]	70	1			T67	1		T230	1		T234	2
all_pins[4]	transitions[0x0=>0x1]	56	1			T67	1		T234	2		T332	1
all_pins[4]	transitions[0x1=>0x0]	42	1			T231	2		T232	4		T331	1
all_pins[5]	values[0x0]	81649	1			T1	3		T2	2		T3	2
all_pins[5]	values[0x1]	56	1			T230	1		T231	4		T232	4
all_pins[5]	transitions[0x0=>0x1]	48	1			T230	1		T231	3		T232	4
all_pins[5]	transitions[0x1=>0x0]	90	1			T69	1		T70	1		T71	1
all_pins[6]	values[0x0]	81607	1			T1	3		T2	2		T3	2
all_pins[6]	values[0x1]	98	1			T69	1		T70	1		T71	1
all_pins[6]	transitions[0x0=>0x1]	88	1			T69	1		T70	1		T71	1
all_pins[6]	transitions[0x1=>0x0]	49	1			T46	1		T233	2		T234	1
all_pins[7]	values[0x0]	81646	1			T1	3		T2	2		T3	2
all_pins[7]	values[0x1]	59	1			T46	1		T233	2		T234	1
all_pins[7]	transitions[0x0=>0x1]	40	1			T46	1		T233	1		T234	1
all_pins[7]	transitions[0x1=>0x0]	71	1			T47	1		T48	1		T49	1
all_pins[8]	values[0x0]	81615	1			T1	3		T2	2		T3	2
all_pins[8]	values[0x1]	90	1			T47	1		T48	1		T49	1
all_pins[8]	transitions[0x0=>0x1]	79	1			T47	1		T48	1		T49	1
all_pins[8]	transitions[0x1=>0x0]	63	1			T62	2		T63	2		T64	2
all_pins[9]	values[0x0]	81631	1			T1	3		T2	2		T3	2
all_pins[9]	values[0x1]	74	1			T62	2		T63	2		T64	2
all_pins[9]	transitions[0x0=>0x1]	57	1			T62	2		T63	2		T64	2
all_pins[9]	transitions[0x1=>0x0]	45	1			T231	4		T331	1		T356	1
all_pins[10]	values[0x0]	81643	1			T1	3		T2	2		T3	2
all_pins[10]	values[0x1]	62	1			T231	5		T331	1		T354	1
all_pins[10]	transitions[0x0=>0x1]	50	1			T231	5		T331	1		T354	1
all_pins[10]	transitions[0x1=>0x0]	108	1			T75	1		T76	1		T77	1
all_pins[11]	values[0x0]	81585	1			T1	3		T2	2		T3	2
all_pins[11]	values[0x1]	120	1			T75	1		T76	1		T77	1
all_pins[11]	transitions[0x0=>0x1]	102	1			T75	1		T76	1		T77	1
all_pins[11]	transitions[0x1=>0x0]	49	1			T79	1		T81	1		T82	1
all_pins[12]	values[0x0]	81638	1			T1	3		T2	2		T3	2
all_pins[12]	values[0x1]	67	1			T79	1		T81	1		T82	1
all_pins[12]	transitions[0x0=>0x1]	54	1			T79	1		T81	1		T82	1
all_pins[12]	transitions[0x1=>0x0]	98	1			T1	1		T84	1		T85	1
all_pins[13]	values[0x0]	81594	1			T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	111	1			T1	1		T84	1		T85	1
all_pins[13]	transitions[0x0=>0x1]	94	1			T1	1		T84	1		T85	1
all_pins[13]	transitions[0x1=>0x0]	52	1			T233	2		T234	3		T232	1
all_pins[14]	values[0x0]	81636	1			T1	3		T2	2		T3	2
all_pins[14]	values[0x1]	69	1			T233	2		T234	3		T231	1
all_pins[14]	transitions[0x0=>0x1]	54	1			T233	2		T234	3		T231	1
all_pins[14]	transitions[0x1=>0x0]	38	1			T230	1		T231	1		T353	1
all_pins[15]	values[0x0]	81652	1			T1	3		T2	2		T3	2
all_pins[15]	values[0x1]	53	1			T230	1		T231	1		T353	1
all_pins[15]	transitions[0x0=>0x1]	38	1			T231	1		T353	1		T354	3
all_pins[15]	transitions[0x1=>0x0]	65	1			T72	4		T73	4		T74	4
all_pins[16]	values[0x0]	81625	1			T1	3		T2	2		T3	2
all_pins[16]	values[0x1]	80	1			T72	4		T73	4		T74	4
all_pins[16]	transitions[0x0=>0x1]	67	1			T72	4		T73	4		T74	4
all_pins[16]	transitions[0x1=>0x0]	44	1			T56	1		T57	1		T58	1
all_pins[17]	values[0x0]	81648	1			T1	3		T2	2		T3	2
all_pins[17]	values[0x1]	57	1			T56	1		T57	1		T58	1
all_pins[17]	transitions[0x0=>0x1]	57	1			T56	1		T57	1		T58	1