Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4360	1			T29	66		T19	13		T263	3
invalid_ep[0xd]	4291	1			T2	1		T29	81		T19	10
invalid_ep[0xe]	4356	1			T29	67		T19	9		T174	10
invalid_ep[0xf]	4368	1			T29	83		T19	14		T174	7
endpoints[0x0]	12427	1			T1	1		T2	2		T29	66
endpoints[0x1]	12907	1			T26	2		T27	1		T29	66
endpoints[0x2]	14906	1			T29	82		T30	2		T32	6
endpoints[0x3]	11851	1			T3	13		T28	3		T29	76
endpoints[0x4]	13484	1			T3	13		T29	66		T30	2
endpoints[0x5]	13350	1			T2	1		T29	83		T30	2
endpoints[0x6]	15204	1			T2	1		T3	13		T29	68
endpoints[0x7]	12205	1			T29	74		T30	2		T45	2
endpoints[0x8]	14092	1			T3	13		T29	72		T30	2
endpoints[0x9]	12497	1			T2	1		T3	13		T29	55
endpoints[0xa]	11530	1			T2	1		T29	95		T30	2
endpoints[0xb]	11554	1			T29	56		T30	2		T33	3

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	21650	1			T2	2		T3	1		T29	304
pkt_types[PidTypeOutToken]	75283	1			T1	1		T2	1		T3	29
pkt_types[PidTypeInToken]	59836	1			T2	2		T3	35		T26	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	947	1			T29	18		T263	1		T424	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	941	1			T2	1		T29	20		T113	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	945	1			T29	17		T114	12		T115	6
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	943	1			T29	27		T250	1		T418	1
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1520	1			T29	9		T33	2		T91	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1454	1			T29	19		T32	1		T91	2
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1536	1			T29	21		T32	2		T17	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1507	1			T29	18		T19	5		T157	2
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1419	1			T3	1		T29	20		T20	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1541	1			T29	20		T44	1		T89	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1456	1			T29	22		T44	3		T89	3
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1349	1			T29	20		T5	5		T117	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1532	1			T29	18		T159	2		T120	1
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1560	1			T29	18		T5	2		T16	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1546	1			T2	1		T29	20		T5	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1454	1			T29	17		T33	1		T107	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1515	1			T29	12		T19	13		T263	1
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1468	1			T29	13		T19	10		T174	11
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1472	1			T29	17		T19	9		T174	10
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1534	1			T29	18		T19	14		T174	7
pkt_types[PidTypeOutToken]	endpoints[0x0]	5408	1			T1	1		T29	24		T30	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	5853	1			T26	1		T27	1		T29	17
pkt_types[PidTypeOutToken]	endpoints[0x2]	7885	1			T29	19		T30	1		T32	2
pkt_types[PidTypeOutToken]	endpoints[0x3]	5010	1			T3	6		T28	1		T29	19
pkt_types[PidTypeOutToken]	endpoints[0x4]	6127	1			T3	5		T29	14		T30	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	6372	1			T29	29		T30	1		T34	6
pkt_types[PidTypeOutToken]	endpoints[0x6]	7585	1			T2	1		T3	6		T29	18
pkt_types[PidTypeOutToken]	endpoints[0x7]	5498	1			T29	19		T30	1		T45	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	6896	1			T3	6		T29	14		T30	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	4921	1			T3	6		T29	9		T30	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	3843	1			T29	21		T30	1		T4	52
pkt_types[PidTypeOutToken]	endpoints[0xb]	3896	1			T29	10		T30	1		T33	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	997	1			T29	19		T395	1		T250	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	891	1			T29	21		T263	1		T403	2
pkt_types[PidTypeInToken]	invalid_ep[0xe]	977	1			T29	15		T406	2		T114	10
pkt_types[PidTypeInToken]	invalid_ep[0xf]	949	1			T29	19		T424	1		T114	17
pkt_types[PidTypeInToken]	endpoints[0x0]	4436	1			T2	1		T29	21		T30	1
pkt_types[PidTypeInToken]	endpoints[0x1]	4563	1			T26	1		T29	14		T30	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4305	1			T29	23		T30	1		T32	2
pkt_types[PidTypeInToken]	endpoints[0x3]	4220	1			T3	7		T28	2		T29	16
pkt_types[PidTypeInToken]	endpoints[0x4]	4887	1			T3	7		T29	13		T30	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4405	1			T2	1		T29	14		T30	1
pkt_types[PidTypeInToken]	endpoints[0x6]	5099	1			T3	7		T29	15		T30	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4294	1			T29	19		T30	1		T45	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4630	1			T3	7		T29	17		T30	1
pkt_types[PidTypeInToken]	endpoints[0x9]	5014	1			T3	7		T29	9		T30	1
pkt_types[PidTypeInToken]	endpoints[0xa]	5050	1			T29	32		T30	1		T4	53
pkt_types[PidTypeInToken]	endpoints[0xb]	5119	1			T29	15		T30	1		T33	1