Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	93988	1			T1	36		T2	2		T3	2
all_values[1]	93988	1			T1	36		T2	2		T3	2
all_values[2]	93988	1			T1	36		T2	2		T3	2
all_values[3]	93988	1			T1	36		T2	2		T3	2
all_values[4]	93988	1			T1	36		T2	2		T3	2
all_values[5]	93988	1			T1	36		T2	2		T3	2
all_values[6]	93988	1			T1	36		T2	2		T3	2
all_values[7]	93988	1			T1	36		T2	2		T3	2
all_values[8]	93988	1			T1	36		T2	2		T3	2
all_values[9]	93988	1			T1	36		T2	2		T3	2
all_values[10]	93988	1			T1	36		T2	2		T3	2
all_values[11]	93988	1			T1	36		T2	2		T3	2
all_values[12]	93988	1			T1	36		T2	2		T3	2
all_values[13]	93988	1			T1	36		T2	2		T3	2
all_values[14]	93988	1			T1	36		T2	2		T3	2
all_values[15]	93988	1			T1	36		T2	2		T3	2
all_values[16]	93988	1			T1	36		T2	2		T3	2
all_values[17]	93988	1			T1	36		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2997957

1

T1

1152

T2

64

T3

64

auto[1]

9659

1

T28

3

T18

3

T19

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2511054

1

T1

957

T2

58

T3

61

auto[1]

496562

1

T1

195

T2

6

T3

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	64430	1			T1	19		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	26210	1			T1	17		T30	7		T22	3
all_values[0]	auto[1]	auto[0]	3236	1			T18	3		T39	3		T40	5
all_values[0]	auto[1]	auto[1]	112	1			T505	1		T506	1		T507	1
all_values[1]	auto[0]	auto[0]	89539	1			T1	36		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	3075	1			T27	2		T4	2		T18	1
all_values[1]	auto[1]	auto[0]	510	1			T28	1		T20	1		T21	2
all_values[1]	auto[1]	auto[1]	864	1			T28	1		T20	1		T21	1
all_values[2]	auto[0]	auto[0]	4226	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	89491	1			T1	35		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	145	1			T38	1		T58	1		T59	1
all_values[2]	auto[1]	auto[1]	126	1			T38	1		T58	1		T59	1
all_values[3]	auto[0]	auto[0]	92152	1			T1	36		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	293	1			T27	1		T60	1		T61	1
all_values[3]	auto[1]	auto[0]	1482	1			T62	1392		T230	1		T231	2
all_values[3]	auto[1]	auto[1]	61	1			T62	1		T231	3		T233	2
all_values[4]	auto[0]	auto[0]	4214	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	89609	1			T1	35		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	93	1			T63	1		T230	1		T231	1
all_values[4]	auto[1]	auto[1]	72	1			T63	1		T230	3		T231	1
all_values[5]	auto[0]	auto[0]	93488	1			T1	36		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	335	1			T28	1		T7	1		T8	1
all_values[5]	auto[1]	auto[0]	109	1			T230	2		T231	2		T235	1
all_values[5]	auto[1]	auto[1]	56	1			T233	1		T232	3		T321	4
all_values[6]	auto[0]	auto[0]	93563	1			T1	36		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	203	1			T8	1		T9	1		T10	1
all_values[6]	auto[1]	auto[0]	114	1			T230	2		T231	2		T233	2
all_values[6]	auto[1]	auto[1]	108	1			T28	1		T20	1		T64	1
all_values[7]	auto[0]	auto[0]	35607	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	58189	1			T1	34		T27	2		T28	3
all_values[7]	auto[1]	auto[0]	127	1			T41	1		T42	1		T43	1
all_values[7]	auto[1]	auto[1]	65	1			T41	1		T42	1		T43	1
all_values[8]	auto[0]	auto[0]	93246	1			T1	36		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	54	1			T231	3		T232	1		T341	2
all_values[8]	auto[1]	auto[0]	609	1			T47	10		T48	10		T44	10
all_values[8]	auto[1]	auto[1]	79	1			T44	1		T45	1		T51	1
all_values[9]	auto[0]	auto[0]	93748	1			T1	36		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	69	1			T230	3		T231	4		T233	1
all_values[9]	auto[1]	auto[0]	110	1			T55	3		T56	3		T57	3
all_values[9]	auto[1]	auto[1]	61	1			T55	2		T56	2		T57	2
all_values[10]	auto[0]	auto[0]	93458	1			T1	36		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	385	1			T29	1		T53	2		T54	1
all_values[10]	auto[1]	auto[0]	86	1			T231	2		T233	1		T234	1
all_values[10]	auto[1]	auto[1]	59	1			T231	2		T233	4		T234	1
all_values[11]	auto[0]	auto[0]	92991	1			T1	36		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	735	1			T68	1		T69	3		T70	3
all_values[11]	auto[1]	auto[0]	157	1			T71	1		T72	1		T73	1
all_values[11]	auto[1]	auto[1]	105	1			T71	1		T72	1		T73	1
all_values[12]	auto[0]	auto[0]	93591	1			T1	36		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	214	1			T74	3		T75	3		T78	3
all_values[12]	auto[1]	auto[0]	117	1			T19	2		T76	2		T77	2
all_values[12]	auto[1]	auto[1]	66	1			T19	1		T76	1		T77	1
all_values[13]	auto[0]	auto[0]	93649	1			T1	36		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	73	1			T81	1		T82	1		T83	1
all_values[13]	auto[1]	auto[0]	145	1			T68	1		T79	1		T80	1
all_values[13]	auto[1]	auto[1]	121	1			T68	1		T79	1		T80	1
all_values[14]	auto[0]	auto[0]	18159	1			T1	33		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	75664	1			T1	3		T27	1		T28	3
all_values[14]	auto[1]	auto[0]	96	1			T230	2		T231	2		T233	1
all_values[14]	auto[1]	auto[1]	69	1			T230	2		T235	3		T340	1
all_values[15]	auto[0]	auto[0]	4261	1			T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	89576	1			T1	35		T2	1		T3	1
all_values[15]	auto[1]	auto[0]	99	1			T230	1		T231	1		T234	3
all_values[15]	auto[1]	auto[1]	52	1			T231	2		T232	1		T340	3
all_values[16]	auto[0]	auto[0]	93033	1			T1	36		T2	1		T3	2
all_values[16]	auto[0]	auto[1]	768	1			T2	1		T29	1		T17	1
all_values[16]	auto[1]	auto[0]	122	1			T65	4		T66	4		T67	4
all_values[16]	auto[1]	auto[1]	65	1			T65	4		T66	4		T67	4
all_values[17]	auto[0]	auto[0]	34408	1			T3	2		T31	2		T28	2
all_values[17]	auto[0]	auto[1]	59419	1			T1	36		T2	2		T27	2
all_values[17]	auto[1]	auto[0]	102	1			T52	1		T231	1		T234	4
all_values[17]	auto[1]	auto[1]	59	1			T52	1		T230	1		T231	1