Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	3642	1			T69	10		T167	1		T109	4
range_16_to_126	154715	1			T1	17		T2	1		T3	16
fifteen	1668	1			T23	1		T109	2		T416	1
range_2_to_14	18795	1			T3	3		T31	1		T22	2
seven	401	1			T105	1		T109	3		T251	1
one	858	1			T39	3		T109	6		T356	1
zero	580	1			T167	1		T13	2		T109	8

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

14983

1

T3

1

T31

1

T27

31

three

12380

1

T2

1

T3

1

T31

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	1258	1			T146	2		T509	1070		T510	2
range_127	three	281	1			T167	1		T110	1		T182	2
range_16_to_126	seven	12346	1			T3	1		T31	1		T27	31
range_16_to_126	three	10733	1			T2	1		T3	1		T31	2
fifteen	seven	112	1			T416	1		T110	1		T511	1
fifteen	three	92	1			T357	1		T172	1		T413	1
range_2_to_14	seven	1182	1			T61	23		T109	4		T162	15
range_2_to_14	three	1108	1			T6	11		T68	1		T156	13
seven	seven	13	1			T109	1		T251	1		T196	1
seven	three	33	1			T196	1		T512	1		T414	1
one	seven	62	1			T110	1		T78	6		T182	1
one	three	35	1			T513	2		T213	1		T514	1
zero	seven	23	1			T109	1		T214	1		T515	1
zero	three	131	1			T213	1		T516	113		T414	2