Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::crc5_cg

Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_crc5	3	0	3	100.00	100	1	1	0
cp_dir	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_crc5_X_dir	6	0	6	100.00	100	1	1	0

Summary for Variable cp_crc5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_crc5

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	5286	1			T5	13		T54	4		T167	1
leading_zero	5122	1			T27	52		T105	2		T112	2
trailing_zero	5983	1			T3	1		T27	43		T22	2

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Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112756

1

T1

17

T2

1

T3

15

auto[1]

67502

1

T3

4

T31

4

T27

233

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Summary for Cross cr_crc5_X_dir

Samples crossed: cp_crc5 cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for cr_crc5_X_dir

Bins

cp_crc5	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	auto[0]	3649	1			T5	6		T54	3		T167	1
all_ones	auto[1]	1637	1			T5	7		T54	1		T61	13
leading_zero	auto[0]	2846	1			T27	24		T105	1		T112	1
leading_zero	auto[1]	2276	1			T27	28		T105	1		T112	1
trailing_zero	auto[0]	3810	1			T3	1		T27	21		T22	1
trailing_zero	auto[1]	2173	1			T27	22		T22	1		T112	1