Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112605

1

T1

17

T2

1

T3

15

auto[1]

44963

1

T27

233

T28

1

T29

2

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	30625	1			T1	17		T27	3		T30	7
max_len_m1	874	1			T27	4		T6	2		T111	2
max_len_m2	837	1			T27	5		T112	2		T272	2
max_len_m3	832	1			T27	2		T4	2		T40	1
five	1164	1			T27	9		T54	1		T272	4
four	1118	1			T27	4		T21	2		T5	2
three	720	1			T27	9		T61	1		T161	1
one	823	1			T27	4		T47	1		T61	4
zero	11467	1			T27	132		T29	1		T54	5

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	25147	1			T1	17		T27	3		T30	7
max_len	auto[1]	5478	1			T61	1		T93	115		T108	99
max_len_m1	auto[0]	584	1			T27	4		T6	1		T111	1
max_len_m1	auto[1]	290	1			T6	1		T111	1		T112	1
max_len_m2	auto[0]	569	1			T27	5		T112	1		T272	1
max_len_m2	auto[1]	268	1			T112	1		T272	1		T209	1
max_len_m3	auto[0]	583	1			T27	2		T4	1		T40	1
max_len_m3	auto[1]	249	1			T4	1		T111	1		T205	3
five	auto[0]	592	1			T27	4		T54	1		T272	2
five	auto[1]	572	1			T27	5		T272	2		T85	2
four	auto[0]	599	1			T27	2		T21	1		T5	1
four	auto[1]	519	1			T27	2		T21	1		T5	1
three	auto[0]	344	1			T27	2		T61	1		T161	1
three	auto[1]	376	1			T27	7		T525	1		T91	6
one	auto[0]	350	1			T27	1		T47	1		T61	4
one	auto[1]	473	1			T27	3		T163	1		T526	1
zero	auto[0]	522	1			T27	6		T527	1		T68	1
zero	auto[1]	10945	1			T27	126		T29	1		T54	5