Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70909

1

T1

17

T2

1

T27

260

auto[1]

76555

1

T27

466

T28

2

T29

3

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	10691	1			T27	72		T5	18		T6	15
endpoints[0x1]	12726	1			T27	53		T20	3		T5	18
endpoints[0x2]	11742	1			T27	65		T29	2		T4	36
endpoints[0x3]	11351	1			T2	1		T27	66		T157	3
endpoints[0x4]	12991	1			T27	69		T17	1		T5	18
endpoints[0x5]	14175	1			T1	17		T27	49		T4	36
endpoints[0x6]	13527	1			T27	61		T29	1		T30	7
endpoints[0x7]	13687	1			T27	43		T4	36		T5	18
endpoints[0x8]	13313	1			T27	80		T29	2		T6	15
endpoints[0x9]	11806	1			T27	55		T28	3		T21	3
endpoints[0xa]	10856	1			T27	54		T6	15		T54	2
endpoints[0xb]	10599	1			T27	59		T4	36		T5	18

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	191	1			T29	1		T54	3		T103	7
ack	37681	1			T27	233		T28	1		T4	48
data1	50984	1			T1	8		T27	240		T4	47
data0	58550	1			T1	9		T2	1		T27	253

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	14	1			T103	2		T331	1		T332	1
nak	auto[1]	endpoints[0x1]	18	1			T103	1		T333	1		T331	1
nak	auto[1]	endpoints[0x2]	21	1			T29	1		T54	1		T331	1
nak	auto[1]	endpoints[0x3]	19	1			T103	2		T331	1		T334	1
nak	auto[1]	endpoints[0x4]	14	1			T103	1		T335	1		T333	1
nak	auto[1]	endpoints[0x5]	17	1			T333	1		T336	1		T337	1
nak	auto[1]	endpoints[0x6]	17	1			T336	1		T337	1		T334	2
nak	auto[1]	endpoints[0x7]	12	1			T54	1		T333	1		T334	1
nak	auto[1]	endpoints[0x8]	13	1			T103	1		T336	2		T337	1
nak	auto[1]	endpoints[0x9]	14	1			T331	1		T336	1		T337	2
nak	auto[1]	endpoints[0xa]	16	1			T338	1		T332	1		T339	1
nak	auto[1]	endpoints[0xb]	16	1			T54	1		T333	1		T331	1
ack	auto[1]	endpoints[0x0]	3292	1			T27	19		T5	6		T6	5
ack	auto[1]	endpoints[0x1]	3036	1			T27	16		T20	1		T5	6
ack	auto[1]	endpoints[0x2]	3248	1			T27	22		T4	12		T22	1
ack	auto[1]	endpoints[0x3]	3109	1			T27	19		T157	1		T5	6
ack	auto[1]	endpoints[0x4]	3089	1			T27	22		T5	6		T54	1
ack	auto[1]	endpoints[0x5]	3111	1			T27	17		T4	12		T9	1
ack	auto[1]	endpoints[0x6]	3258	1			T27	19		T18	1		T5	6
ack	auto[1]	endpoints[0x7]	3049	1			T27	12		T4	12		T5	6
ack	auto[1]	endpoints[0x8]	2892	1			T27	28		T6	5		T112	1
ack	auto[1]	endpoints[0x9]	2988	1			T27	20		T28	1		T21	1
ack	auto[1]	endpoints[0xa]	3368	1			T27	16		T6	5		T156	6
ack	auto[1]	endpoints[0xb]	3241	1			T27	23		T4	12		T5	6
data1	auto[0]	endpoints[0x0]	1539	1			T27	17		T5	2		T6	2
data1	auto[0]	endpoints[0x1]	2841	1			T27	10		T5	3		T156	1
data1	auto[0]	endpoints[0x2]	2150	1			T27	10		T4	4		T6	2
data1	auto[0]	endpoints[0x3]	2100	1			T27	14		T5	1		T6	1
data1	auto[0]	endpoints[0x4]	2894	1			T27	12		T5	2		T61	5
data1	auto[0]	endpoints[0x5]	3447	1			T1	8		T27	7		T4	6
data1	auto[0]	endpoints[0x6]	3020	1			T27	11		T30	3		T18	1
data1	auto[0]	endpoints[0x7]	3370	1			T27	9		T4	6		T5	3
data1	auto[0]	endpoints[0x8]	3236	1			T27	12		T6	2		T103	1
data1	auto[0]	endpoints[0x9]	2404	1			T27	7		T47	3		T74	1
data1	auto[0]	endpoints[0xa]	1578	1			T27	11		T54	1		T156	2
data1	auto[0]	endpoints[0xb]	1551	1			T27	6		T4	3		T5	1
data1	auto[1]	endpoints[0x0]	1832	1			T27	9		T5	4		T6	3
data1	auto[1]	endpoints[0x1]	1709	1			T27	8		T5	3		T156	5
data1	auto[1]	endpoints[0x2]	1810	1			T27	11		T4	8		T6	2
data1	auto[1]	endpoints[0x3]	1684	1			T27	9		T5	4		T6	4
data1	auto[1]	endpoints[0x4]	1713	1			T27	11		T5	4		T54	2
data1	auto[1]	endpoints[0x5]	1725	1			T27	8		T4	6		T5	4
data1	auto[1]	endpoints[0x6]	1825	1			T27	9		T18	1		T5	3
data1	auto[1]	endpoints[0x7]	1673	1			T27	6		T4	6		T5	3
data1	auto[1]	endpoints[0x8]	1583	1			T27	14		T6	3		T103	2
data1	auto[1]	endpoints[0x9]	1626	1			T27	10		T6	5		T74	1
data1	auto[1]	endpoints[0xa]	1880	1			T27	8		T6	4		T156	4
data1	auto[1]	endpoints[0xb]	1794	1			T27	11		T4	8		T5	5
data0	auto[0]	endpoints[0x0]	2424	1			T27	17		T5	4		T6	3
data0	auto[0]	endpoints[0x1]	3733	1			T27	11		T20	1		T5	3
data0	auto[0]	endpoints[0x2]	2995	1			T27	11		T4	8		T22	1
data0	auto[0]	endpoints[0x3]	2955	1			T2	1		T27	14		T157	1
data0	auto[0]	endpoints[0x4]	3816	1			T27	13		T17	1		T5	4
data0	auto[0]	endpoints[0x5]	4391	1			T1	9		T27	8		T4	6
data0	auto[0]	endpoints[0x6]	3845	1			T27	12		T29	1		T30	4
data0	auto[0]	endpoints[0x7]	4145	1			T27	10		T4	6		T5	3
data0	auto[0]	endpoints[0x8]	4191	1			T27	12		T29	1		T6	3
data0	auto[0]	endpoints[0x9]	3352	1			T27	8		T28	1		T21	1
data0	auto[0]	endpoints[0xa]	2461	1			T27	11		T6	5		T54	1
data0	auto[0]	endpoints[0xb]	2463	1			T27	7		T4	9		T5	5
data0	auto[1]	endpoints[0x0]	1584	1			T27	10		T5	2		T6	2
data0	auto[1]	endpoints[0x1]	1386	1			T27	8		T20	1		T5	3
data0	auto[1]	endpoints[0x2]	1514	1			T27	11		T29	1		T4	4
data0	auto[1]	endpoints[0x3]	1480	1			T27	10		T157	1		T5	2
data0	auto[1]	endpoints[0x4]	1460	1			T27	11		T5	2		T54	1
data0	auto[1]	endpoints[0x5]	1479	1			T27	9		T4	6		T9	1
data0	auto[1]	endpoints[0x6]	1559	1			T27	10		T5	3		T6	3
data0	auto[1]	endpoints[0x7]	1432	1			T27	6		T4	6		T5	3
data0	auto[1]	endpoints[0x8]	1395	1			T27	14		T29	1		T6	2
data0	auto[1]	endpoints[0x9]	1415	1			T27	10		T28	1		T21	1
data0	auto[1]	endpoints[0xa]	1546	1			T27	8		T6	1		T156	2
data0	auto[1]	endpoints[0xb]	1529	1			T27	12		T4	4		T5	1