Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	0	16	100.00	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9123

1

T3

3

T31

2

T167

9

auto[1]

52883

1

T3

1

T31

2

T27

233

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54471

1

T3

2

T31

2

T27

233

auto[1]

7535

1

T3

2

T31

2

T105

2

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55627

1

T31

2

T27

233

T28

1

auto[1]

6379

1

T3

4

T31

2

T167

7

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

4557

1

T3

1

T167

1

T105

1

pkt_types[PidTypeInToken]

57449

1

T3

3

T31

4

T27

233

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

1502

1

T61

2

T109

12

T173

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

769

1

T167

1

T109

21

T379

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

106

1

T105

1

T61

2

T106

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

16

1

T365

1

T358

1

T406

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

1355

1

T109

12

T173

3

T355

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

687

1

T3

1

T109

19

T379

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

89

1

T173

1

T416

1

T448

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

33

1

T528

1

T248

1

T363

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

4052

1

T31

1

T167

2

T109

37

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2574

1

T3

1

T167

6

T109

75

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

52

1

T31

1

T105

1

T106

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

52

1

T3

2

T416

1

T248

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

41341

1

T27

233

T28

1

T29

2

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2191

1

T31

1

T105

3

T109

68

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

7130

1

T61

12

T119

1

T93

116

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

57

1

T31

1

T258

1

T416

1