Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	93988	1			T1	36		T2	2		T3	2
all_pins[1]	93988	1			T1	36		T2	2		T3	2
all_pins[2]	93988	1			T1	36		T2	2		T3	2
all_pins[3]	93988	1			T1	36		T2	2		T3	2
all_pins[4]	93988	1			T1	36		T2	2		T3	2
all_pins[5]	93988	1			T1	36		T2	2		T3	2
all_pins[6]	93988	1			T1	36		T2	2		T3	2
all_pins[7]	93988	1			T1	36		T2	2		T3	2
all_pins[8]	93988	1			T1	36		T2	2		T3	2
all_pins[9]	93988	1			T1	36		T2	2		T3	2
all_pins[10]	93988	1			T1	36		T2	2		T3	2
all_pins[11]	93988	1			T1	36		T2	2		T3	2
all_pins[12]	93988	1			T1	36		T2	2		T3	2
all_pins[13]	93988	1			T1	36		T2	2		T3	2
all_pins[14]	93988	1			T1	36		T2	2		T3	2
all_pins[15]	93988	1			T1	36		T2	2		T3	2
all_pins[16]	93988	1			T1	36		T2	2		T3	2
all_pins[17]	93988	1			T1	36		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3005416	1			T1	1152		T2	64		T3	64
values[0x1]	2200	1			T28	2		T19	1		T20	2
transitions[0x0=>0x1]	1950	1			T28	2		T19	1		T20	2
transitions[0x1=>0x0]	1950	1			T28	2		T19	1		T20	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93876	1			T1	36		T2	2		T3	2
all_pins[0]	values[0x1]	112	1			T505	1		T506	1		T507	1
all_pins[0]	transitions[0x0=>0x1]	98	1			T505	1		T506	1		T507	1
all_pins[0]	transitions[0x1=>0x0]	850	1			T28	1		T20	1		T21	1
all_pins[1]	values[0x0]	93124	1			T1	36		T2	2		T3	2
all_pins[1]	values[0x1]	864	1			T28	1		T20	1		T21	1
all_pins[1]	transitions[0x0=>0x1]	850	1			T28	1		T20	1		T21	1
all_pins[1]	transitions[0x1=>0x0]	112	1			T38	1		T58	1		T59	1
all_pins[2]	values[0x0]	93862	1			T1	36		T2	2		T3	2
all_pins[2]	values[0x1]	126	1			T38	1		T58	1		T59	1
all_pins[2]	transitions[0x0=>0x1]	107	1			T38	1		T58	1		T59	1
all_pins[2]	transitions[0x1=>0x0]	42	1			T62	1		T231	3		T233	2
all_pins[3]	values[0x0]	93927	1			T1	36		T2	2		T3	2
all_pins[3]	values[0x1]	61	1			T62	1		T231	3		T233	2
all_pins[3]	transitions[0x0=>0x1]	47	1			T62	1		T231	3		T233	2
all_pins[3]	transitions[0x1=>0x0]	58	1			T63	1		T230	3		T231	1
all_pins[4]	values[0x0]	93916	1			T1	36		T2	2		T3	2
all_pins[4]	values[0x1]	72	1			T63	1		T230	3		T231	1
all_pins[4]	transitions[0x0=>0x1]	57	1			T63	1		T230	3		T231	1
all_pins[4]	transitions[0x1=>0x0]	41	1			T233	1		T232	1		T321	4
all_pins[5]	values[0x0]	93932	1			T1	36		T2	2		T3	2
all_pins[5]	values[0x1]	56	1			T233	1		T232	3		T321	4
all_pins[5]	transitions[0x0=>0x1]	50	1			T233	1		T232	3		T321	4
all_pins[5]	transitions[0x1=>0x0]	102	1			T28	1		T20	1		T64	1
all_pins[6]	values[0x0]	93880	1			T1	36		T2	2		T3	2
all_pins[6]	values[0x1]	108	1			T28	1		T20	1		T64	1
all_pins[6]	transitions[0x0=>0x1]	95	1			T28	1		T20	1		T64	1
all_pins[6]	transitions[0x1=>0x0]	52	1			T41	1		T42	1		T43	1
all_pins[7]	values[0x0]	93923	1			T1	36		T2	2		T3	2
all_pins[7]	values[0x1]	65	1			T41	1		T42	1		T43	1
all_pins[7]	transitions[0x0=>0x1]	50	1			T41	1		T42	1		T43	1
all_pins[7]	transitions[0x1=>0x0]	64	1			T44	1		T45	1		T51	1
all_pins[8]	values[0x0]	93909	1			T1	36		T2	2		T3	2
all_pins[8]	values[0x1]	79	1			T44	1		T45	1		T51	1
all_pins[8]	transitions[0x0=>0x1]	65	1			T44	1		T45	1		T51	1
all_pins[8]	transitions[0x1=>0x0]	47	1			T55	2		T56	2		T57	2
all_pins[9]	values[0x0]	93927	1			T1	36		T2	2		T3	2
all_pins[9]	values[0x1]	61	1			T55	2		T56	2		T57	2
all_pins[9]	transitions[0x0=>0x1]	48	1			T55	2		T56	2		T57	2
all_pins[9]	transitions[0x1=>0x0]	46	1			T231	1		T233	3		T234	1
all_pins[10]	values[0x0]	93929	1			T1	36		T2	2		T3	2
all_pins[10]	values[0x1]	59	1			T231	2		T233	4		T234	1
all_pins[10]	transitions[0x0=>0x1]	44	1			T231	1		T233	3		T234	1
all_pins[10]	transitions[0x1=>0x0]	90	1			T71	1		T72	1		T73	1
all_pins[11]	values[0x0]	93883	1			T1	36		T2	2		T3	2
all_pins[11]	values[0x1]	105	1			T71	1		T72	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	91	1			T71	1		T72	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	52	1			T19	1		T76	1		T77	1
all_pins[12]	values[0x0]	93922	1			T1	36		T2	2		T3	2
all_pins[12]	values[0x1]	66	1			T19	1		T76	1		T77	1
all_pins[12]	transitions[0x0=>0x1]	45	1			T19	1		T76	1		T77	1
all_pins[12]	transitions[0x1=>0x0]	100	1			T68	1		T79	1		T80	1
all_pins[13]	values[0x0]	93867	1			T1	36		T2	2		T3	2
all_pins[13]	values[0x1]	121	1			T68	1		T79	1		T80	1
all_pins[13]	transitions[0x0=>0x1]	100	1			T68	1		T79	1		T80	1
all_pins[13]	transitions[0x1=>0x0]	48	1			T235	3		T340	1		T341	3
all_pins[14]	values[0x0]	93919	1			T1	36		T2	2		T3	2
all_pins[14]	values[0x1]	69	1			T230	2		T235	3		T340	1
all_pins[14]	transitions[0x0=>0x1]	57	1			T230	2		T235	3		T340	1
all_pins[14]	transitions[0x1=>0x0]	40	1			T231	2		T232	1		T340	3
all_pins[15]	values[0x0]	93936	1			T1	36		T2	2		T3	2
all_pins[15]	values[0x1]	52	1			T231	2		T232	1		T340	3
all_pins[15]	transitions[0x0=>0x1]	36	1			T231	1		T340	3		T341	1
all_pins[15]	transitions[0x1=>0x0]	49	1			T65	4		T66	4		T67	4
all_pins[16]	values[0x0]	93923	1			T1	36		T2	2		T3	2
all_pins[16]	values[0x1]	65	1			T65	4		T66	4		T67	4
all_pins[16]	transitions[0x0=>0x1]	51	1			T65	4		T66	4		T67	4
all_pins[16]	transitions[0x1=>0x0]	45	1			T52	1		T231	1		T233	1
all_pins[17]	values[0x0]	93929	1			T1	36		T2	2		T3	2
all_pins[17]	values[0x1]	59	1			T52	1		T230	1		T231	1
all_pins[17]	transitions[0x0=>0x1]	59	1			T52	1		T230	1		T231	1