Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4602	1			T3	2		T105	1		T109	82
invalid_ep[0xd]	4785	1			T257	1		T105	1		T109	67
invalid_ep[0xe]	4741	1			T105	1		T109	72		T106	1
invalid_ep[0xf]	4668	1			T105	2		T109	80		T106	1
endpoints[0x0]	11510	1			T3	2		T27	53		T5	13
endpoints[0x1]	14104	1			T3	2		T27	37		T20	2
endpoints[0x2]	13431	1			T3	1		T31	1		T27	43
endpoints[0x3]	12380	1			T2	1		T3	1		T31	2
endpoints[0x4]	13885	1			T31	1		T27	47		T17	1
endpoints[0x5]	14973	1			T1	17		T3	3		T27	32
endpoints[0x6]	14226	1			T3	2		T27	42		T29	1
endpoints[0x7]	14983	1			T3	1		T31	1		T27	31
endpoints[0x8]	14962	1			T3	1		T27	52		T29	2
endpoints[0x9]	13095	1			T3	2		T27	35		T28	2
endpoints[0xa]	11826	1			T3	1		T31	3		T27	38
endpoints[0xb]	12087	1			T3	1		T31	2		T27	36

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	23687	1			T3	8		T31	3		T4	12
pkt_types[PidTypeOutToken]	77342	1			T1	17		T2	1		T3	3
pkt_types[PidTypeInToken]	61490	1			T3	3		T31	4		T27	233

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1036	1			T105	1		T109	19		T248	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1075	1			T109	13		T418	1		T110	26
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1061	1			T109	13		T110	26		T538	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1047	1			T105	1		T109	18		T106	1
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1615	1			T5	3		T6	2		T160	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1659	1			T3	1		T156	5		T109	22
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1733	1			T4	4		T40	1		T167	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1513	1			T3	1		T31	1		T5	4
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1615	1			T5	3		T114	1		T109	20
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1571	1			T3	1		T4	2		T5	3
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1614	1			T3	1		T18	1		T5	3
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1582	1			T3	1		T61	5		T109	14
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1525	1			T3	1		T6	2		T109	16
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1661	1			T3	1		T6	5		T257	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1711	1			T31	1		T6	4		T156	3
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1669	1			T3	1		T31	1		T4	6
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1580	1			T109	17		T472	1		T107	2
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1625	1			T109	16		T107	5		T200	10
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1636	1			T109	25		T107	18		T200	10
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1530	1			T105	1		T109	31		T107	12
pkt_types[PidTypeOutToken]	endpoints[0x0]	4072	1			T27	34		T5	3		T6	3
pkt_types[PidTypeOutToken]	endpoints[0x1]	6445	1			T27	21		T20	1		T5	6
pkt_types[PidTypeOutToken]	endpoints[0x2]	5243	1			T3	1		T27	21		T4	8
pkt_types[PidTypeOutToken]	endpoints[0x3]	5110	1			T2	1		T27	28		T157	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	6649	1			T31	1		T27	25		T17	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	7696	1			T1	17		T3	1		T27	15
pkt_types[PidTypeOutToken]	endpoints[0x6]	6857	1			T3	1		T27	23		T29	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	7669	1			T31	1		T27	19		T4	12
pkt_types[PidTypeOutToken]	endpoints[0x8]	7432	1			T27	24		T29	1		T6	3
pkt_types[PidTypeOutToken]	endpoints[0x9]	5802	1			T27	15		T28	1		T21	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	3982	1			T27	22		T6	1		T54	2
pkt_types[PidTypeOutToken]	endpoints[0xb]	4014	1			T27	13		T4	6		T5	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	989	1			T109	25		T248	1		T110	28
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1017	1			T109	22		T472	1		T110	27
pkt_types[PidTypeInToken]	invalid_ep[0xe]	988	1			T109	13		T106	1		T110	29
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1047	1			T109	19		T110	25		T182	10
pkt_types[PidTypeInToken]	endpoints[0x0]	4740	1			T3	2		T27	19		T5	7
pkt_types[PidTypeInToken]	endpoints[0x1]	4856	1			T3	1		T27	16		T20	1
pkt_types[PidTypeInToken]	endpoints[0x2]	5314	1			T31	1		T27	22		T29	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4641	1			T31	1		T27	19		T157	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4466	1			T27	22		T5	7		T54	3
pkt_types[PidTypeInToken]	endpoints[0x5]	4595	1			T27	17		T4	13		T9	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4595	1			T27	19		T18	1		T5	7
pkt_types[PidTypeInToken]	endpoints[0x7]	4657	1			T27	12		T4	13		T5	7
pkt_types[PidTypeInToken]	endpoints[0x8]	4882	1			T27	28		T29	1		T6	6
pkt_types[PidTypeInToken]	endpoints[0x9]	4505	1			T27	20		T28	1		T21	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4991	1			T31	1		T27	16		T6	6
pkt_types[PidTypeInToken]	endpoints[0xb]	5207	1			T31	1		T27	23		T4	13