Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T230	4		T231	7		T233	4
all_values[1]	275	1			T230	4		T231	7		T233	4
all_values[2]	275	1			T230	4		T231	7		T233	4
all_values[3]	275	1			T230	4		T231	7		T233	4
all_values[4]	275	1			T230	4		T231	7		T233	4
all_values[5]	275	1			T230	4		T231	7		T233	4
all_values[6]	275	1			T230	4		T231	7		T233	4
all_values[7]	275	1			T230	4		T231	7		T233	4
all_values[8]	275	1			T230	4		T231	7		T233	4
all_values[9]	275	1			T230	4		T231	7		T233	4
all_values[10]	275	1			T230	4		T231	7		T233	4
all_values[11]	275	1			T230	4		T231	7		T233	4
all_values[12]	275	1			T230	4		T231	7		T233	4
all_values[13]	275	1			T230	4		T231	7		T233	4
all_values[14]	275	1			T230	4		T231	7		T233	4
all_values[15]	275	1			T230	4		T231	7		T233	4
all_values[16]	275	1			T230	4		T231	7		T233	4
all_values[17]	275	1			T230	4		T231	7		T233	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6598

1

T230

90

T231

150

T233

95

auto[1]

2202

1

T230

38

T231

74

T233

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6081

1

T230

88

T231

153

T233

77

auto[1]

2719

1

T230

40

T231

71

T233

51

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5235

1

T230

84

T231

137

T233

68

auto[1]

3565

1

T230

44

T231

87

T233

60

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	74	1			T231	1		T233	1		T234	1
all_values[0]	auto[0]	auto[1]	auto[0]	72	1			T230	4		T231	3		T233	1
all_values[0]	auto[1]	auto[0]	auto[1]	75	1			T231	1		T233	1		T234	1
all_values[0]	auto[1]	auto[1]	auto[1]	54	1			T231	2		T233	1		T234	2
all_values[1]	auto[0]	auto[0]	auto[0]	86	1			T230	1		T234	2		T235	2
all_values[1]	auto[0]	auto[1]	auto[0]	75	1			T230	1		T231	4		T233	2
all_values[1]	auto[1]	auto[0]	auto[1]	64	1			T235	1		T232	1		T340	3
all_values[1]	auto[1]	auto[1]	auto[1]	50	1			T230	2		T231	3		T233	2
all_values[2]	auto[0]	auto[0]	auto[0]	37	1			T233	3		T232	2		T322	1
all_values[2]	auto[0]	auto[0]	auto[1]	43	1			T230	1		T231	1		T234	1
all_values[2]	auto[0]	auto[1]	auto[0]	41	1			T231	1		T235	1		T232	1
all_values[2]	auto[0]	auto[1]	auto[1]	37	1			T230	1		T231	2		T233	1
all_values[2]	auto[1]	auto[0]	auto[1]	65	1			T230	2		T234	2		T235	1
all_values[2]	auto[1]	auto[1]	auto[1]	52	1			T231	3		T235	1		T340	3
all_values[3]	auto[0]	auto[0]	auto[0]	71	1			T234	2		T235	1		T232	1
all_values[3]	auto[0]	auto[0]	auto[1]	32	1			T230	1		T231	2		T233	1
all_values[3]	auto[0]	auto[1]	auto[0]	43	1			T230	2		T231	2		T235	2
all_values[3]	auto[0]	auto[1]	auto[1]	25	1			T231	1		T233	1		T234	1
all_values[3]	auto[1]	auto[0]	auto[1]	61	1			T230	1		T233	1		T234	1
all_values[3]	auto[1]	auto[1]	auto[1]	43	1			T231	2		T233	1		T340	5
all_values[4]	auto[0]	auto[0]	auto[0]	65	1			T231	1		T233	1		T234	1
all_values[4]	auto[0]	auto[0]	auto[1]	30	1			T231	1		T233	1		T234	1
all_values[4]	auto[0]	auto[1]	auto[0]	46	1			T231	1		T235	2		T341	2
all_values[4]	auto[0]	auto[1]	auto[1]	29	1			T230	2		T232	2		T340	2
all_values[4]	auto[1]	auto[0]	auto[1]	56	1			T230	2		T231	3		T233	1
all_values[4]	auto[1]	auto[1]	auto[1]	49	1			T231	1		T233	1		T232	1
all_values[5]	auto[0]	auto[0]	auto[0]	67	1			T231	3		T234	2		T340	2
all_values[5]	auto[0]	auto[0]	auto[1]	17	1			T230	1		T233	1		T235	2
all_values[5]	auto[0]	auto[1]	auto[0]	56	1			T230	2		T231	2		T340	4
all_values[5]	auto[0]	auto[1]	auto[1]	20	1			T232	1		T321	2		T342	1
all_values[5]	auto[1]	auto[0]	auto[1]	67	1			T231	1		T233	2		T234	2
all_values[5]	auto[1]	auto[1]	auto[1]	48	1			T230	1		T231	1		T233	1
all_values[6]	auto[0]	auto[0]	auto[0]	66	1			T231	4		T232	2		T340	3
all_values[6]	auto[0]	auto[0]	auto[1]	24	1			T230	1		T235	2		T341	2
all_values[6]	auto[0]	auto[1]	auto[0]	62	1			T230	1		T231	2		T233	1
all_values[6]	auto[0]	auto[1]	auto[1]	19	1			T233	1		T234	1		T321	1
all_values[6]	auto[1]	auto[0]	auto[1]	62	1			T233	1		T234	3		T235	2
all_values[6]	auto[1]	auto[1]	auto[1]	42	1			T230	2		T231	1		T233	1
all_values[7]	auto[0]	auto[0]	auto[0]	79	1			T230	2		T233	1		T234	2
all_values[7]	auto[0]	auto[1]	auto[0]	82	1			T231	5		T233	1		T232	1
all_values[7]	auto[1]	auto[0]	auto[1]	58	1			T230	2		T231	2		T233	1
all_values[7]	auto[1]	auto[1]	auto[1]	56	1			T233	1		T232	1		T340	1
all_values[8]	auto[0]	auto[0]	auto[0]	86	1			T230	1		T233	2		T234	2
all_values[8]	auto[0]	auto[1]	auto[0]	77	1			T230	2		T231	2		T233	1
all_values[8]	auto[1]	auto[0]	auto[1]	62	1			T230	1		T231	3		T235	1
all_values[8]	auto[1]	auto[1]	auto[1]	50	1			T231	2		T233	1		T322	1
all_values[9]	auto[0]	auto[0]	auto[0]	67	1			T234	3		T232	1		T340	2
all_values[9]	auto[0]	auto[0]	auto[1]	29	1			T230	1		T231	1		T232	1
all_values[9]	auto[0]	auto[1]	auto[0]	56	1			T233	1		T234	1		T235	2
all_values[9]	auto[0]	auto[1]	auto[1]	23	1			T231	1		T233	1		T321	1
all_values[9]	auto[1]	auto[0]	auto[1]	66	1			T230	2		T231	3		T233	1
all_values[9]	auto[1]	auto[1]	auto[1]	34	1			T230	1		T231	2		T233	1
all_values[10]	auto[0]	auto[0]	auto[0]	67	1			T230	4		T231	1		T234	1
all_values[10]	auto[0]	auto[0]	auto[1]	26	1			T235	1		T232	1		T340	1
all_values[10]	auto[0]	auto[1]	auto[0]	44	1			T231	1		T234	2		T340	2
all_values[10]	auto[0]	auto[1]	auto[1]	22	1			T233	1		T341	1		T322	1
all_values[10]	auto[1]	auto[0]	auto[1]	76	1			T231	2		T234	1		T235	2
all_values[10]	auto[1]	auto[1]	auto[1]	40	1			T231	3		T233	3		T232	1
all_values[11]	auto[0]	auto[0]	auto[0]	59	1			T230	3		T233	1		T234	1
all_values[11]	auto[0]	auto[0]	auto[1]	31	1			T231	1		T233	1		T321	2
all_values[11]	auto[0]	auto[1]	auto[0]	52	1			T230	1		T231	3		T235	1
all_values[11]	auto[0]	auto[1]	auto[1]	21	1			T231	1		T235	1		T232	1
all_values[11]	auto[1]	auto[0]	auto[1]	77	1			T233	1		T234	1		T340	4
all_values[11]	auto[1]	auto[1]	auto[1]	35	1			T231	2		T233	1		T234	2
all_values[12]	auto[0]	auto[0]	auto[0]	63	1			T233	2		T234	1		T235	1
all_values[12]	auto[0]	auto[0]	auto[1]	23	1			T231	1		T234	1		T235	1
all_values[12]	auto[0]	auto[1]	auto[0]	53	1			T230	2		T231	2		T233	1
all_values[12]	auto[0]	auto[1]	auto[1]	26	1			T230	1		T231	3		T235	1
all_values[12]	auto[1]	auto[0]	auto[1]	62	1			T230	1		T234	2		T235	1
all_values[12]	auto[1]	auto[1]	auto[1]	48	1			T231	1		T233	1		T232	1
all_values[13]	auto[0]	auto[0]	auto[0]	52	1			T231	1		T234	1		T235	1
all_values[13]	auto[0]	auto[0]	auto[1]	31	1			T231	1		T233	2		T322	1
all_values[13]	auto[0]	auto[1]	auto[0]	43	1			T230	1		T235	2		T340	1
all_values[13]	auto[0]	auto[1]	auto[1]	35	1			T230	1		T231	1		T234	2
all_values[13]	auto[1]	auto[0]	auto[1]	61	1			T231	3		T234	1		T235	1
all_values[13]	auto[1]	auto[1]	auto[1]	53	1			T230	2		T231	1		T233	2
all_values[14]	auto[0]	auto[0]	auto[0]	69	1			T230	2		T231	4		T234	1
all_values[14]	auto[0]	auto[0]	auto[1]	28	1			T233	1		T234	1		T232	2
all_values[14]	auto[0]	auto[1]	auto[0]	37	1			T233	1		T340	1		T341	1
all_values[14]	auto[0]	auto[1]	auto[1]	32	1			T230	1		T231	1		T235	1
all_values[14]	auto[1]	auto[0]	auto[1]	64	1			T231	2		T233	2		T234	2
all_values[14]	auto[1]	auto[1]	auto[1]	45	1			T230	1		T341	1		T321	3
all_values[15]	auto[0]	auto[0]	auto[0]	56	1			T231	2		T235	3		T340	2
all_values[15]	auto[0]	auto[0]	auto[1]	32	1			T230	1		T233	1		T234	1
all_values[15]	auto[0]	auto[1]	auto[0]	58	1			T234	1		T235	1		T340	1
all_values[15]	auto[0]	auto[1]	auto[1]	16	1			T232	1		T340	1		T343	1
all_values[15]	auto[1]	auto[0]	auto[1]	71	1			T230	2		T231	2		T233	3
all_values[15]	auto[1]	auto[1]	auto[1]	42	1			T230	1		T231	3		T340	1
all_values[16]	auto[0]	auto[0]	auto[0]	57	1			T231	1		T234	1		T235	1
all_values[16]	auto[0]	auto[0]	auto[1]	32	1			T233	2		T234	1		T235	1
all_values[16]	auto[0]	auto[1]	auto[0]	57	1			T231	4		T235	1		T340	2
all_values[16]	auto[0]	auto[1]	auto[1]	21	1			T230	2		T341	1		T343	1
all_values[16]	auto[1]	auto[0]	auto[1]	58	1			T233	1		T234	2		T340	2
all_values[16]	auto[1]	auto[1]	auto[1]	50	1			T230	2		T231	2		T233	1
all_values[17]	auto[0]	auto[0]	auto[0]	78	1			T230	2		T231	3		T233	1
all_values[17]	auto[0]	auto[1]	auto[0]	78	1			T230	1		T231	2		T234	1
all_values[17]	auto[1]	auto[0]	auto[1]	66	1			T231	1		T233	2		T234	1
all_values[17]	auto[1]	auto[1]	auto[1]	53	1			T230	1		T231	1		T233	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal