Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	171061	1			T1	3		T2	3		T3	2
all_values[1]	171061	1			T1	3		T2	3		T3	2
all_values[2]	171061	1			T1	3		T2	3		T3	2
all_values[3]	171061	1			T1	3		T2	3		T3	2
all_values[4]	171061	1			T1	3		T2	3		T3	2
all_values[5]	171061	1			T1	3		T2	3		T3	2
all_values[6]	171061	1			T1	3		T2	3		T3	2
all_values[7]	171061	1			T1	3		T2	3		T3	2
all_values[8]	171061	1			T1	3		T2	3		T3	2
all_values[9]	171061	1			T1	3		T2	3		T3	2
all_values[10]	171061	1			T1	3		T2	3		T3	2
all_values[11]	171061	1			T1	3		T2	3		T3	2
all_values[12]	171061	1			T1	3		T2	3		T3	2
all_values[13]	171061	1			T1	3		T2	3		T3	2
all_values[14]	171061	1			T1	3		T2	3		T3	2
all_values[15]	171061	1			T1	3		T2	3		T3	2
all_values[16]	171061	1			T1	3		T2	3		T3	2
all_values[17]	171061	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5464023

1

T1

96

T2

96

T3

64

auto[1]

9929

1

T68

2

T29

10

T34

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4692356

1

T1

85

T2

86

T3

60

auto[1]

781596

1

T1

11

T2

10

T3

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142764	1			T1	3		T2	3		T3	2
all_values[0]	auto[0]	auto[1]	24964	1			T22	3		T24	2		T25	9
all_values[0]	auto[1]	auto[0]	3225	1			T34	5		T40	5		T41	3
all_values[0]	auto[1]	auto[1]	108	1			T85	1		T366	1		T367	1
all_values[1]	auto[0]	auto[0]	166563	1			T1	3		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	3067	1			T5	2		T22	1		T23	2
all_values[1]	auto[1]	auto[0]	544	1			T35	1		T36	1		T42	2
all_values[1]	auto[1]	auto[1]	887	1			T35	1		T36	1		T42	1
all_values[2]	auto[0]	auto[0]	4251	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	166544	1			T1	2		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	131	1			T37	1		T39	1		T59	1
all_values[2]	auto[1]	auto[1]	135	1			T37	1		T39	1		T59	1
all_values[3]	auto[0]	auto[0]	169117	1			T1	3		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	297	1			T5	1		T27	1		T60	1
all_values[3]	auto[1]	auto[0]	1576	1			T61	1484		T233	2		T238	1
all_values[3]	auto[1]	auto[1]	71	1			T61	1		T234	2		T237	1
all_values[4]	auto[0]	auto[0]	4212	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	166668	1			T1	2		T2	2		T3	1
all_values[4]	auto[1]	auto[0]	111	1			T62	1		T233	4		T234	1
all_values[4]	auto[1]	auto[1]	70	1			T62	1		T233	1		T234	3
all_values[5]	auto[0]	auto[0]	170544	1			T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	347	1			T1	1		T2	1		T6	1
all_values[5]	auto[1]	auto[0]	111	1			T234	3		T235	5		T238	3
all_values[5]	auto[1]	auto[1]	59	1			T234	2		T237	2		T356	2
all_values[6]	auto[0]	auto[0]	170630	1			T1	3		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	213	1			T2	1		T5	1		T35	1
all_values[6]	auto[1]	auto[0]	102	1			T233	4		T235	4		T237	1
all_values[6]	auto[1]	auto[1]	116	1			T38	1		T63	1		T64	1
all_values[7]	auto[0]	auto[0]	115023	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	55844	1			T1	1		T2	1		T6	1
all_values[7]	auto[1]	auto[0]	127	1			T43	1		T233	5		T234	4
all_values[7]	auto[1]	auto[1]	67	1			T43	1		T233	2		T235	1
all_values[8]	auto[0]	auto[0]	170337	1			T1	3		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	64	1			T233	1		T234	1		T235	1
all_values[8]	auto[1]	auto[0]	585	1			T29	10		T47	10		T48	10
all_values[8]	auto[1]	auto[1]	75	1			T46	1		T50	1		T51	1
all_values[9]	auto[0]	auto[0]	170817	1			T1	3		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	65	1			T235	3		T237	3		T356	3
all_values[9]	auto[1]	auto[0]	106	1			T56	3		T57	3		T58	3
all_values[9]	auto[1]	auto[1]	73	1			T56	2		T57	2		T58	2
all_values[10]	auto[0]	auto[0]	170461	1			T1	3		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	421	1			T23	1		T28	1		T55	1
all_values[10]	auto[1]	auto[0]	113	1			T233	4		T234	1		T238	2
all_values[10]	auto[1]	auto[1]	66	1			T233	1		T238	2		T237	3
all_values[11]	auto[0]	auto[0]	170104	1			T1	3		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	681	1			T68	1		T69	3		T70	3
all_values[11]	auto[1]	auto[0]	147	1			T71	1		T72	1		T73	1
all_values[11]	auto[1]	auto[1]	129	1			T71	1		T72	1		T73	1
all_values[12]	auto[0]	auto[0]	170679	1			T1	3		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	200	1			T74	3		T75	3		T76	3
all_values[12]	auto[1]	auto[0]	114	1			T77	2		T78	2		T79	2
all_values[12]	auto[1]	auto[1]	68	1			T77	1		T78	1		T79	1
all_values[13]	auto[0]	auto[0]	170724	1			T1	3		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	61	1			T82	1		T83	1		T84	1
all_values[13]	auto[1]	auto[0]	155	1			T68	1		T80	1		T81	1
all_values[13]	auto[1]	auto[1]	121	1			T68	1		T80	1		T81	1
all_values[14]	auto[0]	auto[0]	35419	1			T1	1		T2	3		T3	1
all_values[14]	auto[0]	auto[1]	135465	1			T1	2		T3	1		T4	1
all_values[14]	auto[1]	auto[0]	110	1			T233	2		T234	1		T235	4
all_values[14]	auto[1]	auto[1]	67	1			T233	4		T238	2		T237	1
all_values[15]	auto[0]	auto[0]	4264	1			T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	166627	1			T1	2		T2	2		T3	1
all_values[15]	auto[1]	auto[0]	100	1			T233	1		T234	1		T235	1
all_values[15]	auto[1]	auto[1]	70	1			T233	3		T238	2		T237	1
all_values[16]	auto[0]	auto[0]	170115	1			T1	3		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	722	1			T16	1		T17	1		T21	1
all_values[16]	auto[1]	auto[0]	123	1			T65	4		T66	4		T67	4
all_values[16]	auto[1]	auto[1]	101	1			T65	4		T66	4		T67	4
all_values[17]	auto[0]	auto[0]	113894	1			T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	57001	1			T1	1		T2	1		T16	2
all_values[17]	auto[1]	auto[0]	104	1			T52	1		T53	1		T54	1
all_values[17]	auto[1]	auto[1]	62	1			T52	1		T53	1		T54	1