Summary for Variable cp_crc5
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_crc5
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_ones |
4444 |
1 |
|
|
T3 |
11 |
|
T4 |
11 |
|
T27 |
47 |
leading_zero |
7400 |
1 |
|
|
T15 |
1 |
|
T27 |
10 |
|
T29 |
7 |
trailing_zero |
4211 |
1 |
|
|
T27 |
9 |
|
T112 |
29 |
|
T128 |
2 |
Summary for Variable cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_dir
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
110733 |
1 |
|
|
T3 |
40 |
|
T14 |
2 |
|
T15 |
7 |
auto[1] |
68540 |
1 |
|
|
T3 |
48 |
|
T14 |
1 |
|
T15 |
6 |
Summary for Cross cr_crc5_X_dir
Samples crossed: cp_crc5 cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for cr_crc5_X_dir
Bins
cp_crc5 | cp_dir | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_ones |
auto[0] |
2650 |
1 |
|
|
T3 |
5 |
|
T4 |
5 |
|
T27 |
31 |
all_ones |
auto[1] |
1794 |
1 |
|
|
T3 |
6 |
|
T4 |
6 |
|
T27 |
16 |
leading_zero |
auto[0] |
5458 |
1 |
|
|
T27 |
6 |
|
T29 |
7 |
|
T112 |
30 |
leading_zero |
auto[1] |
1942 |
1 |
|
|
T15 |
1 |
|
T27 |
4 |
|
T112 |
3 |
trailing_zero |
auto[0] |
2473 |
1 |
|
|
T27 |
5 |
|
T112 |
24 |
|
T128 |
1 |
trailing_zero |
auto[1] |
1738 |
1 |
|
|
T27 |
4 |
|
T112 |
5 |
|
T128 |
1 |