Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg
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Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_crc5 3 0 3 100.00 100 1 1 0
cp_dir 2 0 2 100.00 100 1 1 2


Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_crc5_X_dir 6 0 6 100.00 100 1 1 0


Summary for Variable cp_crc5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_crc5

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_ones 4444 1 T3 11 T4 11 T27 47
leading_zero 7400 1 T15 1 T27 10 T29 7
trailing_zero 4211 1 T27 9 T112 29 T128 2



Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 110733 1 T3 40 T14 2 T15 7
auto[1] 68540 1 T3 48 T14 1 T15 6



Summary for Cross cr_crc5_X_dir

Samples crossed: cp_crc5 cp_dir
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for cr_crc5_X_dir

Bins
cp_crc5cp_dirCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_ones auto[0] 2650 1 T3 5 T4 5 T27 31
all_ones auto[1] 1794 1 T3 6 T4 6 T27 16
leading_zero auto[0] 5458 1 T27 6 T29 7 T112 30
leading_zero auto[1] 1942 1 T15 1 T27 4 T112 3
trailing_zero auto[0] 2473 1 T27 5 T112 24 T128 1
trailing_zero auto[1] 1738 1 T27 4 T112 5 T128 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%