Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110587

1

T3

40

T14

2

T15

7

auto[1]

46587

1

T3

40

T4

35

T5

42

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29594	1			T25	9		T114	2		T41	1
max_len_m1	835	1			T3	2		T118	6		T97	4
max_len_m2	886	1			T5	2		T114	2		T186	4
max_len_m3	819	1			T40	1		T88	1		T97	1
five	1189	1			T3	2		T23	2		T114	4
four	1177	1			T5	4		T23	1		T34	1
three	788	1			T23	2		T333	1		T97	5
one	889	1			T378	1		T379	1		T97	8
zero	12176	1			T68	1		T23	6		T26	12

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23899	1			T25	9		T114	1		T41	1
max_len	auto[1]	5695	1			T114	1		T60	70		T115	1
max_len_m1	auto[0]	566	1			T3	1		T118	3		T97	4
max_len_m1	auto[1]	269	1			T3	1		T118	3		T109	1
max_len_m2	auto[0]	588	1			T5	1		T114	1		T186	2
max_len_m2	auto[1]	298	1			T5	1		T114	1		T186	2
max_len_m3	auto[0]	560	1			T40	1		T97	1		T186	1
max_len_m3	auto[1]	259	1			T88	1		T186	1		T129	3
five	auto[0]	617	1			T3	1		T23	1		T114	2
five	auto[1]	572	1			T3	1		T23	1		T114	2
four	auto[0]	621	1			T5	2		T23	1		T74	1
four	auto[1]	556	1			T5	2		T34	1		T118	2
three	auto[0]	374	1			T23	1		T333	1		T97	2
three	auto[1]	414	1			T23	1		T97	3		T265	3
one	auto[0]	396	1			T378	1		T379	1		T97	7
one	auto[1]	493	1			T97	1		T380	1		T265	9
zero	auto[0]	582	1			T68	1		T97	7		T308	1
zero	auto[1]	11594	1			T23	6		T26	12		T28	9