Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69703

1

T3

40

T4

35

T16

1

auto[1]

79291

1

T3

80

T4

70

T5

84

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	14642	1			T4	15		T17	1		T23	1
endpoints[0x1]	11364	1			T3	15		T23	5		T27	26
endpoints[0x2]	12914	1			T3	15		T23	5		T27	8
endpoints[0x3]	11591	1			T3	15		T4	15		T23	4
endpoints[0x4]	9562	1			T21	1		T23	3		T27	15
endpoints[0x5]	12397	1			T4	15		T28	13		T41	4
endpoints[0x6]	13668	1			T3	15		T4	15		T23	4
endpoints[0x7]	12246	1			T3	15		T4	15		T23	3
endpoints[0x8]	11255	1			T3	15		T4	15		T5	42
endpoints[0x9]	14178	1			T3	15		T5	42		T23	4
endpoints[0xa]	12577	1			T3	15		T4	15		T22	1
endpoints[0xb]	12600	1			T16	1		T5	42		T23	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	179	1			T23	3		T109	6		T110	6
ack	39040	1			T3	40		T4	35		T5	42
data1	51300	1			T3	37		T4	31		T5	41
data0	58411	1			T3	43		T4	39		T16	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	17	1			T110	2		T334	1		T335	1
nak	auto[1]	endpoints[0x1]	16	1			T23	1		T110	1		T336	1
nak	auto[1]	endpoints[0x2]	18	1			T23	1		T109	1		T337	1
nak	auto[1]	endpoints[0x3]	17	1			T109	2		T338	2		T339	1
nak	auto[1]	endpoints[0x4]	9	1			T338	1		T340	1		T341	1
nak	auto[1]	endpoints[0x5]	16	1			T109	1		T337	1		T342	2
nak	auto[1]	endpoints[0x6]	16	1			T23	1		T109	1		T110	1
nak	auto[1]	endpoints[0x7]	13	1			T337	1		T343	1		T344	1
nak	auto[1]	endpoints[0x8]	14	1			T109	1		T110	1		T336	1
nak	auto[1]	endpoints[0x9]	17	1			T338	1		T337	1		T345	1
nak	auto[1]	endpoints[0xa]	17	1			T110	1		T338	2		T334	1
nak	auto[1]	endpoints[0xb]	9	1			T339	1		T345	1		T343	1
ack	auto[1]	endpoints[0x0]	3473	1			T4	5		T35	1		T70	2
ack	auto[1]	endpoints[0x1]	3153	1			T3	5		T23	1		T27	8
ack	auto[1]	endpoints[0x2]	3189	1			T3	5		T23	1		T40	1
ack	auto[1]	endpoints[0x3]	3325	1			T3	5		T4	5		T27	7
ack	auto[1]	endpoints[0x4]	2915	1			T34	2		T114	48		T86	3
ack	auto[1]	endpoints[0x5]	3311	1			T4	5		T28	4		T41	1
ack	auto[1]	endpoints[0x6]	3292	1			T3	5		T4	5		T23	1
ack	auto[1]	endpoints[0x7]	3138	1			T3	5		T4	5		T23	1
ack	auto[1]	endpoints[0x8]	3204	1			T3	5		T4	5		T5	14
ack	auto[1]	endpoints[0x9]	3642	1			T3	5		T5	14		T23	1
ack	auto[1]	endpoints[0xa]	3353	1			T3	5		T4	5		T23	1
ack	auto[1]	endpoints[0xb]	3045	1			T5	14		T70	1		T112	4
data1	auto[0]	endpoints[0x0]	3402	1			T4	2		T23	1		T27	4
data1	auto[0]	endpoints[0x1]	2026	1			T3	2		T27	5		T87	1
data1	auto[0]	endpoints[0x2]	2758	1			T3	1		T23	1		T27	3
data1	auto[0]	endpoints[0x3]	1925	1			T3	1		T23	3		T25	4
data1	auto[0]	endpoints[0x4]	1431	1			T23	2		T34	2		T114	24
data1	auto[0]	endpoints[0x5]	2423	1			T4	1		T41	1		T123	2
data1	auto[0]	endpoints[0x6]	3057	1			T3	2		T4	2		T27	3
data1	auto[0]	endpoints[0x7]	2573	1			T3	1		T4	1		T27	2
data1	auto[0]	endpoints[0x8]	2017	1			T3	1		T4	1		T5	7
data1	auto[0]	endpoints[0x9]	2949	1			T3	2		T5	5		T27	7
data1	auto[0]	endpoints[0xa]	2463	1			T3	1		T4	2		T23	1
data1	auto[0]	endpoints[0xb]	2763	1			T5	7		T23	1		T27	3
data1	auto[1]	endpoints[0x0]	1951	1			T4	2		T70	2		T175	5
data1	auto[1]	endpoints[0x1]	1733	1			T3	3		T23	1		T27	5
data1	auto[1]	endpoints[0x2]	1732	1			T3	3		T40	1		T97	6
data1	auto[1]	endpoints[0x3]	1847	1			T3	4		T4	5		T23	1
data1	auto[1]	endpoints[0x4]	1580	1			T23	1		T34	2		T114	24
data1	auto[1]	endpoints[0x5]	1806	1			T4	4		T28	4		T41	1
data1	auto[1]	endpoints[0x6]	1847	1			T3	2		T4	2		T23	1
data1	auto[1]	endpoints[0x7]	1723	1			T3	4		T4	4		T27	5
data1	auto[1]	endpoints[0x8]	1750	1			T3	4		T4	3		T5	7
data1	auto[1]	endpoints[0x9]	2032	1			T3	2		T5	8		T27	4
data1	auto[1]	endpoints[0xa]	1847	1			T3	4		T4	2		T26	4
data1	auto[1]	endpoints[0xb]	1665	1			T5	7		T70	1		T112	3
data0	auto[0]	endpoints[0x0]	4155	1			T4	3		T17	1		T27	5
data0	auto[0]	endpoints[0x1]	2937	1			T3	3		T27	5		T112	4
data0	auto[0]	endpoints[0x2]	3678	1			T3	4		T27	5		T29	4
data0	auto[0]	endpoints[0x3]	2922	1			T3	4		T4	5		T25	5
data0	auto[0]	endpoints[0x4]	2203	1			T21	1		T27	15		T34	2
data0	auto[0]	endpoints[0x5]	3249	1			T4	4		T41	1		T112	9
data0	auto[0]	endpoints[0x6]	3893	1			T3	3		T4	3		T92	1
data0	auto[0]	endpoints[0x7]	3310	1			T3	4		T4	4		T23	1
data0	auto[0]	endpoints[0x8]	2747	1			T3	4		T4	4		T5	7
data0	auto[0]	endpoints[0x9]	3854	1			T3	3		T5	9		T23	2
data0	auto[0]	endpoints[0xa]	3304	1			T3	4		T4	3		T22	1
data0	auto[0]	endpoints[0xb]	3650	1			T16	1		T5	7		T27	9
data0	auto[1]	endpoints[0x0]	1640	1			T4	3		T35	1		T175	6
data0	auto[1]	endpoints[0x1]	1492	1			T3	2		T23	2		T27	3
data0	auto[1]	endpoints[0x2]	1537	1			T3	2		T23	2		T97	6
data0	auto[1]	endpoints[0x3]	1549	1			T3	1		T27	3		T36	1
data0	auto[1]	endpoints[0x4]	1420	1			T114	24		T86	2		T97	6
data0	auto[1]	endpoints[0x5]	1588	1			T4	1		T28	5		T123	2
data0	auto[1]	endpoints[0x6]	1556	1			T3	3		T4	3		T23	1
data0	auto[1]	endpoints[0x7]	1485	1			T3	1		T4	1		T23	1
data0	auto[1]	endpoints[0x8]	1517	1			T3	1		T4	2		T5	7
data0	auto[1]	endpoints[0x9]	1677	1			T3	3		T5	6		T23	1
data0	auto[1]	endpoints[0xa]	1586	1			T3	1		T4	3		T23	1
data0	auto[1]	endpoints[0xb]	1462	1			T5	7		T112	1		T346	1