Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8352 1 T15 5 T27 91 T112 51
auto[1] 54748 1 T3 48 T14 1 T4 42


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55155 1 T3 48 T15 3 T4 42
auto[1] 7945 1 T14 1 T15 2 T22 1


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 57279 1 T3 48 T14 1 T15 4
auto[1] 5821 1 T15 1 T27 39 T112 61


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4392 1 T15 1 T27 48 T112 22
pkt_types[PidTypeInToken] 58708 1 T3 48 T14 1 T15 4


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1404 1 T15 1 T27 14 T112 7
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 668 1 T27 7 T381 1 T113 14
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 92 1 T382 1 T179 5 T383 3
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 7 1 T384 1 T385 1 T386 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1358 1 T27 27 T112 7 T128 2
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 733 1 T112 8 T387 2 T132 52
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 117 1 T129 1 T127 1 T179 3
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 13 1 T388 1 T389 1 T390 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 4064 1 T15 1 T27 43 T112 40
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2022 1 T15 1 T27 27 T112 4
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 42 1 T15 2 T391 1 T144 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 53 1 T369 1 T382 1 T391 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 42624 1 T3 48 T4 42 T5 45
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2282 1 T27 5 T112 49 T128 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7578 1 T14 1 T22 1 T60 72
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 43 1 T369 1 T388 2 T392 1

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