Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
36.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	1	10	90.91
Crosses	54	40	14	25.93

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	1	2	66.67	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	40	14	25.93	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19850	1			T3	40		T4	35		T5	42
solo	75155	1			T14	1		T15	6		T16	1
empty	3826	1			T14	1		T24	1		T27	34

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19874	1			T3	40		T4	35		T5	42
solo	32289	1			T14	2		T15	3		T24	1
empty	46754	1			T15	3		T16	1		T17	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

76305

1

T3

21

T14

1

T15

4

setup

22736

1

T3

19

T14

1

T15

2

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_rx

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
full	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

solo

37

1

T44

2

T45

2

T46

1

empty

83447

1

T3

40

T14

2

T15

6

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	40	14	25.93	40

Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[full]	[full]	[full , solo]	*	--	--	4
[full]	[solo]	*	*	--	--	6
[full]	[empty]	[full]	*	--	--	2
[solo]	[full]	[full , solo]	*	--	--	4
[solo]	[solo]	[full]	*	--	--	2
[solo]	[empty]	[full , solo]	*	--	--	4
[empty]	[full , solo]	[full , solo]	*	--	--	8
[empty]	[empty]	[full , solo]	*	--	--	4

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[full]	[empty]	[solo , empty]	[out]	--	--	2
[solo]	[full]	[empty]	[setup]	0	1	1
[solo]	[empty]	[empty]	[out]	0	1	1
[empty]	[full , solo]	[empty]	[setup]	--	--	2

Covered bins

cp_avsetup

cp_avout

cp_rx

cp_pid

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

full

full

empty

out

15462

1

T3

21

T4

20

T5

36

full

full

empty

setup

4351

1

T3

19

T4

15

T5

6

full

empty

solo

setup

11

1

T50

1

T327

1

T328

1

full

empty

empty

setup

8

1

T50

1

T329

1

T330

1

solo

full

empty

out

5

1

T44

1

T45

1

T49

1

solo

solo

solo

out

5

1

T44

1

T45

1

T49

1

solo

solo

solo

setup

5

1

T44

1

T45

1

T49

1

solo

solo

empty

out

8363

1

T14

1

T15

1

T27

103

solo

solo

empty

setup

8418

1

T15

2

T27

94

T95

2

solo

empty

empty

setup

2024

1

T14

1

T24

1

T27

8

empty

full

empty

out

6

1

T47

1

T331

1

T332

1

empty

solo

empty

out

44356

1

T15

3

T16

1

T17

1

empty

empty

empty

out

244

1

T70

1

T106

1

T333

1

empty

empty

empty

setup

169

1

T124

1

T116

1

T166

1