Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	171061	1			T1	3		T2	3		T3	2
all_pins[1]	171061	1			T1	3		T2	3		T3	2
all_pins[2]	171061	1			T1	3		T2	3		T3	2
all_pins[3]	171061	1			T1	3		T2	3		T3	2
all_pins[4]	171061	1			T1	3		T2	3		T3	2
all_pins[5]	171061	1			T1	3		T2	3		T3	2
all_pins[6]	171061	1			T1	3		T2	3		T3	2
all_pins[7]	171061	1			T1	3		T2	3		T3	2
all_pins[8]	171061	1			T1	3		T2	3		T3	2
all_pins[9]	171061	1			T1	3		T2	3		T3	2
all_pins[10]	171061	1			T1	3		T2	3		T3	2
all_pins[11]	171061	1			T1	3		T2	3		T3	2
all_pins[12]	171061	1			T1	3		T2	3		T3	2
all_pins[13]	171061	1			T1	3		T2	3		T3	2
all_pins[14]	171061	1			T1	3		T2	3		T3	2
all_pins[15]	171061	1			T1	3		T2	3		T3	2
all_pins[16]	171061	1			T1	3		T2	3		T3	2
all_pins[17]	171061	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5471607	1			T1	96		T2	96		T3	64
values[0x1]	2345	1			T68	1		T35	1		T36	1
transitions[0x0=>0x1]	2067	1			T68	1		T35	1		T36	1
transitions[0x1=>0x0]	2067	1			T68	1		T35	1		T36	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	170953	1			T1	3		T2	3		T3	2
all_pins[0]	values[0x1]	108	1			T85	1		T366	1		T367	1
all_pins[0]	transitions[0x0=>0x1]	89	1			T85	1		T366	1		T367	1
all_pins[0]	transitions[0x1=>0x0]	868	1			T35	1		T36	1		T42	1
all_pins[1]	values[0x0]	170174	1			T1	3		T2	3		T3	2
all_pins[1]	values[0x1]	887	1			T35	1		T36	1		T42	1
all_pins[1]	transitions[0x0=>0x1]	872	1			T35	1		T36	1		T42	1
all_pins[1]	transitions[0x1=>0x0]	120	1			T37	1		T39	1		T59	1
all_pins[2]	values[0x0]	170926	1			T1	3		T2	3		T3	2
all_pins[2]	values[0x1]	135	1			T37	1		T39	1		T59	1
all_pins[2]	transitions[0x0=>0x1]	113	1			T37	1		T39	1		T59	1
all_pins[2]	transitions[0x1=>0x0]	49	1			T61	1		T237	1		T356	2
all_pins[3]	values[0x0]	170990	1			T1	3		T2	3		T3	2
all_pins[3]	values[0x1]	71	1			T61	1		T234	2		T237	1
all_pins[3]	transitions[0x0=>0x1]	58	1			T61	1		T234	1		T237	1
all_pins[3]	transitions[0x1=>0x0]	57	1			T62	1		T233	1		T234	2
all_pins[4]	values[0x0]	170991	1			T1	3		T2	3		T3	2
all_pins[4]	values[0x1]	70	1			T62	1		T233	1		T234	3
all_pins[4]	transitions[0x0=>0x1]	53	1			T62	1		T233	1		T234	1
all_pins[4]	transitions[0x1=>0x0]	42	1			T356	2		T323	2		T325	3
all_pins[5]	values[0x0]	171002	1			T1	3		T2	3		T3	2
all_pins[5]	values[0x1]	59	1			T234	2		T237	2		T356	2
all_pins[5]	transitions[0x0=>0x1]	48	1			T234	2		T237	2		T356	2
all_pins[5]	transitions[0x1=>0x0]	105	1			T38	1		T63	1		T64	1
all_pins[6]	values[0x0]	170945	1			T1	3		T2	3		T3	2
all_pins[6]	values[0x1]	116	1			T38	1		T63	1		T64	1
all_pins[6]	transitions[0x0=>0x1]	96	1			T38	1		T63	1		T64	1
all_pins[6]	transitions[0x1=>0x0]	47	1			T43	1		T233	2		T235	1
all_pins[7]	values[0x0]	170994	1			T1	3		T2	3		T3	2
all_pins[7]	values[0x1]	67	1			T43	1		T233	2		T235	1
all_pins[7]	transitions[0x0=>0x1]	56	1			T43	1		T233	1		T235	1
all_pins[7]	transitions[0x1=>0x0]	64	1			T46	1		T50	1		T51	1
all_pins[8]	values[0x0]	170986	1			T1	3		T2	3		T3	2
all_pins[8]	values[0x1]	75	1			T46	1		T50	1		T51	1
all_pins[8]	transitions[0x0=>0x1]	65	1			T46	1		T50	1		T51	1
all_pins[8]	transitions[0x1=>0x0]	63	1			T56	2		T57	2		T58	2
all_pins[9]	values[0x0]	170988	1			T1	3		T2	3		T3	2
all_pins[9]	values[0x1]	73	1			T56	2		T57	2		T58	2
all_pins[9]	transitions[0x0=>0x1]	58	1			T56	2		T57	2		T58	2
all_pins[9]	transitions[0x1=>0x0]	51	1			T233	1		T238	2		T237	1
all_pins[10]	values[0x0]	170995	1			T1	3		T2	3		T3	2
all_pins[10]	values[0x1]	66	1			T233	1		T238	2		T237	3
all_pins[10]	transitions[0x0=>0x1]	50	1			T233	1		T238	2		T237	3
all_pins[10]	transitions[0x1=>0x0]	113	1			T71	1		T72	1		T73	1
all_pins[11]	values[0x0]	170932	1			T1	3		T2	3		T3	2
all_pins[11]	values[0x1]	129	1			T71	1		T72	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	115	1			T71	1		T72	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	54	1			T77	1		T78	1		T79	1
all_pins[12]	values[0x0]	170993	1			T1	3		T2	3		T3	2
all_pins[12]	values[0x1]	68	1			T77	1		T78	1		T79	1
all_pins[12]	transitions[0x0=>0x1]	53	1			T77	1		T78	1		T79	1
all_pins[12]	transitions[0x1=>0x0]	106	1			T68	1		T80	1		T81	1
all_pins[13]	values[0x0]	170940	1			T1	3		T2	3		T3	2
all_pins[13]	values[0x1]	121	1			T68	1		T80	1		T81	1
all_pins[13]	transitions[0x0=>0x1]	103	1			T68	1		T80	1		T81	1
all_pins[13]	transitions[0x1=>0x0]	49	1			T233	4		T237	1		T356	2
all_pins[14]	values[0x0]	170994	1			T1	3		T2	3		T3	2
all_pins[14]	values[0x1]	67	1			T233	4		T238	2		T237	1
all_pins[14]	transitions[0x0=>0x1]	44	1			T233	3		T237	1		T356	2
all_pins[14]	transitions[0x1=>0x0]	47	1			T233	2		T237	1		T356	2
all_pins[15]	values[0x0]	170991	1			T1	3		T2	3		T3	2
all_pins[15]	values[0x1]	70	1			T233	3		T238	2		T237	1
all_pins[15]	transitions[0x0=>0x1]	49	1			T233	3		T237	1		T356	1
all_pins[15]	transitions[0x1=>0x0]	80	1			T65	4		T66	4		T67	4
all_pins[16]	values[0x0]	170960	1			T1	3		T2	3		T3	2
all_pins[16]	values[0x1]	101	1			T65	4		T66	4		T67	4
all_pins[16]	transitions[0x0=>0x1]	83	1			T65	4		T66	4		T67	4
all_pins[16]	transitions[0x1=>0x0]	44	1			T52	1		T53	1		T54	1
all_pins[17]	values[0x0]	170999	1			T1	3		T2	3		T3	2
all_pins[17]	values[0x1]	62	1			T52	1		T53	1		T54	1
all_pins[17]	transitions[0x0=>0x1]	62	1			T52	1		T53	1		T54	1