Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4589	1			T15	1		T27	46		T95	1
invalid_ep[0xd]	4537	1			T14	1		T27	45		T112	38
invalid_ep[0xe]	4474	1			T27	52		T95	1		T112	49
invalid_ep[0xf]	4555	1			T15	1		T27	50		T95	1
endpoints[0x0]	15657	1			T15	2		T4	11		T17	1
endpoints[0x1]	12456	1			T3	11		T23	3		T27	46
endpoints[0x2]	13851	1			T3	11		T15	1		T23	3
endpoints[0x3]	12531	1			T3	11		T15	1		T4	11
endpoints[0x4]	11355	1			T15	3		T21	1		T23	3
endpoints[0x5]	12910	1			T14	1		T15	1		T4	11
endpoints[0x6]	14598	1			T3	11		T15	3		T4	11
endpoints[0x7]	13823	1			T3	11		T4	11		T23	2
endpoints[0x8]	12370	1			T3	11		T4	11		T5	29
endpoints[0x9]	14769	1			T3	11		T5	29		T23	3
endpoints[0xa]	13011	1			T3	11		T14	1		T4	11
endpoints[0xb]	13787	1			T16	1		T5	29		T23	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	22736	1			T3	19		T14	1		T15	2
pkt_types[PidTypeOutToken]	76305	1			T3	21		T14	1		T15	4
pkt_types[PidTypeInToken]	62775	1			T3	48		T14	1		T15	5

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	941	1			T27	15		T112	5		T111	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	996	1			T14	1		T27	11		T112	15
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	993	1			T27	9		T112	12		T113	19
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1008	1			T27	13		T112	12		T369	2
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1624	1			T27	7		T70	2		T112	10
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1546	1			T3	2		T27	12		T112	8
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1584	1			T3	2		T27	3		T170	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1756	1			T3	4		T15	1		T4	5
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1427	1			T15	1		T27	17		T34	2
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1502	1			T4	4		T27	12		T41	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1646	1			T27	16		T112	8		T118	5
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1538	1			T3	3		T4	4		T27	12
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1483	1			T3	4		T4	2		T27	10
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1661	1			T5	6		T24	1		T27	11
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1539	1			T3	4		T27	7		T95	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1492	1			T27	8		T70	1		T112	10
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1538	1			T27	15		T112	10		T113	34
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1511	1			T27	9		T112	6		T113	23
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1483	1			T27	14		T112	11		T113	28
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1551	1			T15	1		T27	12		T95	1
pkt_types[PidTypeOutToken]	endpoints[0x0]	7676	1			T4	5		T17	1		T68	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	4988	1			T3	3		T27	8		T95	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	6569	1			T3	3		T23	1		T27	11
pkt_types[PidTypeOutToken]	endpoints[0x3]	4791	1			T3	1		T23	3		T25	9
pkt_types[PidTypeOutToken]	endpoints[0x4]	3720	1			T15	2		T21	1		T23	2
pkt_types[PidTypeOutToken]	endpoints[0x5]	5763	1			T14	1		T15	1		T4	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	6922	1			T3	5		T4	5		T92	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	6024	1			T3	2		T4	1		T23	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	4935	1			T3	1		T4	3		T5	14
pkt_types[PidTypeOutToken]	endpoints[0x9]	6785	1			T3	5		T5	8		T23	2
pkt_types[PidTypeOutToken]	endpoints[0xa]	5703	1			T3	1		T4	5		T22	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	6346	1			T16	1		T5	14		T23	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1089	1			T15	1		T27	9		T112	9
pkt_types[PidTypeInToken]	invalid_ep[0xd]	984	1			T27	11		T112	7		T113	20
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1007	1			T27	13		T95	1		T112	14
pkt_types[PidTypeInToken]	invalid_ep[0xf]	987	1			T27	8		T112	11		T393	1
pkt_types[PidTypeInToken]	endpoints[0x0]	5221	1			T15	1		T4	6		T27	7
pkt_types[PidTypeInToken]	endpoints[0x1]	4797	1			T3	6		T23	3		T27	17
pkt_types[PidTypeInToken]	endpoints[0x2]	4589	1			T3	6		T15	1		T23	2
pkt_types[PidTypeInToken]	endpoints[0x3]	4853	1			T3	6		T4	6		T23	1
pkt_types[PidTypeInToken]	endpoints[0x4]	5098	1			T23	1		T27	10		T34	2
pkt_types[PidTypeInToken]	endpoints[0x5]	4510	1			T4	6		T27	9		T28	9
pkt_types[PidTypeInToken]	endpoints[0x6]	4935	1			T3	6		T15	2		T4	6
pkt_types[PidTypeInToken]	endpoints[0x7]	5128	1			T3	6		T4	6		T23	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4820	1			T3	6		T4	6		T5	15
pkt_types[PidTypeInToken]	endpoints[0x9]	5225	1			T3	6		T5	15		T23	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4692	1			T3	6		T14	1		T4	6
pkt_types[PidTypeInToken]	endpoints[0xb]	4840	1			T5	15		T27	12		T60	72