Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T233	7		T234	4		T235	4
all_values[1]	281	1			T233	7		T234	4		T235	4
all_values[2]	281	1			T233	7		T234	4		T235	4
all_values[3]	281	1			T233	7		T234	4		T235	4
all_values[4]	281	1			T233	7		T234	4		T235	4
all_values[5]	281	1			T233	7		T234	4		T235	4
all_values[6]	281	1			T233	7		T234	4		T235	4
all_values[7]	281	1			T233	7		T234	4		T235	4
all_values[8]	281	1			T233	7		T234	4		T235	4
all_values[9]	281	1			T233	7		T234	4		T235	4
all_values[10]	281	1			T233	7		T234	4		T235	4
all_values[11]	281	1			T233	7		T234	4		T235	4
all_values[12]	281	1			T233	7		T234	4		T235	4
all_values[13]	281	1			T233	7		T234	4		T235	4
all_values[14]	281	1			T233	7		T234	4		T235	4
all_values[15]	281	1			T233	7		T234	4		T235	4
all_values[16]	281	1			T233	7		T234	4		T235	4
all_values[17]	281	1			T233	7		T234	4		T235	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6605

1

T233

158

T234

91

T235

102

auto[1]

2387

1

T233

66

T234

37

T235

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6135

1

T233

149

T234

83

T235

91

auto[1]

2857

1

T233

75

T234

45

T235

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5259

1

T233

121

T234

78

T235

83

auto[1]

3733

1

T233

103

T234

50

T235

45

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	80	1			T233	2		T238	2		T237	2
all_values[0]	auto[0]	auto[1]	auto[0]	78	1			T233	2		T234	1		T235	1
all_values[0]	auto[1]	auto[0]	auto[1]	72	1			T233	2		T234	3		T235	2
all_values[0]	auto[1]	auto[1]	auto[1]	51	1			T233	1		T235	1		T356	1
all_values[1]	auto[0]	auto[0]	auto[0]	77	1			T233	1		T234	1		T235	3
all_values[1]	auto[0]	auto[1]	auto[0]	91	1			T233	1		T234	2		T238	1
all_values[1]	auto[1]	auto[0]	auto[1]	54	1			T233	3		T235	1		T356	1
all_values[1]	auto[1]	auto[1]	auto[1]	59	1			T233	2		T234	1		T237	2
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T234	1		T235	1		T237	1
all_values[2]	auto[0]	auto[0]	auto[1]	35	1			T233	1		T237	1		T356	1
all_values[2]	auto[0]	auto[1]	auto[0]	38	1			T234	1		T235	2		T238	1
all_values[2]	auto[0]	auto[1]	auto[1]	42	1			T233	2		T234	1		T238	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1			T233	1		T235	1		T238	2
all_values[2]	auto[1]	auto[1]	auto[1]	55	1			T233	3		T234	1		T237	2
all_values[3]	auto[0]	auto[0]	auto[0]	54	1			T233	1		T235	2		T238	3
all_values[3]	auto[0]	auto[0]	auto[1]	28	1			T233	1		T234	1		T235	1
all_values[3]	auto[0]	auto[1]	auto[0]	47	1			T233	1		T238	1		T237	4
all_values[3]	auto[0]	auto[1]	auto[1]	27	1			T234	1		T237	1		T356	2
all_values[3]	auto[1]	auto[0]	auto[1]	65	1			T233	3		T235	1		T237	1
all_values[3]	auto[1]	auto[1]	auto[1]	60	1			T233	1		T234	2		T237	1
all_values[4]	auto[0]	auto[0]	auto[0]	57	1			T233	2		T234	1		T356	2
all_values[4]	auto[0]	auto[0]	auto[1]	21	1			T238	1		T237	1		T357	1
all_values[4]	auto[0]	auto[1]	auto[0]	51	1			T233	3		T235	1		T238	1
all_values[4]	auto[0]	auto[1]	auto[1]	34	1			T234	1		T235	1		T237	2
all_values[4]	auto[1]	auto[0]	auto[1]	71	1			T233	2		T235	1		T238	1
all_values[4]	auto[1]	auto[1]	auto[1]	47	1			T234	2		T235	1		T238	1
all_values[5]	auto[0]	auto[0]	auto[0]	66	1			T233	6		T235	1		T238	2
all_values[5]	auto[0]	auto[0]	auto[1]	22	1			T237	1		T356	1		T358	2
all_values[5]	auto[0]	auto[1]	auto[0]	59	1			T234	2		T235	3		T238	1
all_values[5]	auto[0]	auto[1]	auto[1]	27	1			T234	1		T237	1		T323	1
all_values[5]	auto[1]	auto[0]	auto[1]	62	1			T233	1		T238	1		T237	2
all_values[5]	auto[1]	auto[1]	auto[1]	45	1			T234	1		T237	2		T356	2
all_values[6]	auto[0]	auto[0]	auto[0]	59	1			T238	1		T237	2		T356	2
all_values[6]	auto[0]	auto[0]	auto[1]	25	1			T233	1		T234	1		T357	1
all_values[6]	auto[0]	auto[1]	auto[0]	48	1			T233	2		T235	2		T238	1
all_values[6]	auto[0]	auto[1]	auto[1]	26	1			T234	1		T356	1		T359	1
all_values[6]	auto[1]	auto[0]	auto[1]	70	1			T233	3		T234	1		T235	2
all_values[6]	auto[1]	auto[1]	auto[1]	53	1			T233	1		T234	1		T237	2
all_values[7]	auto[0]	auto[0]	auto[0]	70	1			T233	1		T234	2		T235	1
all_values[7]	auto[0]	auto[1]	auto[0]	88	1			T233	4		T234	2		T235	1
all_values[7]	auto[1]	auto[0]	auto[1]	64	1			T235	2		T238	3		T237	1
all_values[7]	auto[1]	auto[1]	auto[1]	59	1			T233	2		T237	1		T356	1
all_values[8]	auto[0]	auto[0]	auto[0]	111	1			T233	2		T234	2		T235	2
all_values[8]	auto[0]	auto[1]	auto[0]	55	1			T233	2		T235	1		T237	1
all_values[8]	auto[1]	auto[0]	auto[1]	67	1			T233	1		T234	1		T238	1
all_values[8]	auto[1]	auto[1]	auto[1]	48	1			T233	2		T234	1		T235	1
all_values[9]	auto[0]	auto[0]	auto[0]	66	1			T233	1		T234	3		T235	1
all_values[9]	auto[0]	auto[0]	auto[1]	31	1			T235	1		T237	1		T356	1
all_values[9]	auto[0]	auto[1]	auto[0]	43	1			T233	3		T234	1		T238	1
all_values[9]	auto[0]	auto[1]	auto[1]	29	1			T237	3		T357	1		T323	2
all_values[9]	auto[1]	auto[0]	auto[1]	63	1			T235	1		T238	1		T237	1
all_values[9]	auto[1]	auto[1]	auto[1]	49	1			T233	3		T235	1		T237	2
all_values[10]	auto[0]	auto[0]	auto[0]	56	1			T235	2		T238	1		T356	1
all_values[10]	auto[0]	auto[0]	auto[1]	22	1			T233	1		T234	1		T237	1
all_values[10]	auto[0]	auto[1]	auto[0]	60	1			T233	3		T234	1		T238	1
all_values[10]	auto[0]	auto[1]	auto[1]	27	1			T233	1		T238	1		T237	1
all_values[10]	auto[1]	auto[0]	auto[1]	68	1			T233	1		T234	2		T235	2
all_values[10]	auto[1]	auto[1]	auto[1]	48	1			T233	1		T237	4		T356	1
all_values[11]	auto[0]	auto[0]	auto[0]	50	1			T233	1		T238	1		T357	4
all_values[11]	auto[0]	auto[0]	auto[1]	30	1			T234	1		T235	1		T238	1
all_values[11]	auto[0]	auto[1]	auto[0]	44	1			T233	1		T234	1		T237	5
all_values[11]	auto[0]	auto[1]	auto[1]	36	1			T233	2		T234	1		T235	1
all_values[11]	auto[1]	auto[0]	auto[1]	61	1			T233	2		T235	1		T238	1
all_values[11]	auto[1]	auto[1]	auto[1]	60	1			T233	1		T234	1		T235	1
all_values[12]	auto[0]	auto[0]	auto[0]	69	1			T235	2		T238	2		T237	1
all_values[12]	auto[0]	auto[0]	auto[1]	17	1			T233	1		T234	1		T238	1
all_values[12]	auto[0]	auto[1]	auto[0]	58	1			T237	1		T356	2		T357	1
all_values[12]	auto[0]	auto[1]	auto[1]	24	1			T234	1		T237	1		T359	1
all_values[12]	auto[1]	auto[0]	auto[1]	57	1			T233	2		T234	1		T235	1
all_values[12]	auto[1]	auto[1]	auto[1]	56	1			T233	4		T234	1		T235	1
all_values[13]	auto[0]	auto[0]	auto[0]	65	1			T233	1		T234	2		T238	2
all_values[13]	auto[0]	auto[0]	auto[1]	21	1			T233	1		T356	1		T323	1
all_values[13]	auto[0]	auto[1]	auto[0]	50	1			T233	2		T235	1		T237	1
all_values[13]	auto[0]	auto[1]	auto[1]	28	1			T235	1		T238	1		T237	1
all_values[13]	auto[1]	auto[0]	auto[1]	71	1			T233	2		T234	1		T235	1
all_values[13]	auto[1]	auto[1]	auto[1]	46	1			T233	1		T234	1		T235	1
all_values[14]	auto[0]	auto[0]	auto[0]	61	1			T233	1		T235	1		T356	2
all_values[14]	auto[0]	auto[0]	auto[1]	21	1			T234	1		T237	1		T360	1
all_values[14]	auto[0]	auto[1]	auto[0]	46	1			T234	1		T235	1		T237	3
all_values[14]	auto[0]	auto[1]	auto[1]	30	1			T233	1		T238	1		T356	1
all_values[14]	auto[1]	auto[0]	auto[1]	59	1			T233	2		T234	2		T235	1
all_values[14]	auto[1]	auto[1]	auto[1]	64	1			T233	3		T235	1		T238	1
all_values[15]	auto[0]	auto[0]	auto[0]	56	1			T235	3		T237	1		T357	1
all_values[15]	auto[0]	auto[0]	auto[1]	25	1			T233	1		T234	1		T238	1
all_values[15]	auto[0]	auto[1]	auto[0]	42	1			T234	1		T237	2		T357	1
all_values[15]	auto[0]	auto[1]	auto[1]	31	1			T233	1		T238	1		T323	1
all_values[15]	auto[1]	auto[0]	auto[1]	65	1			T233	2		T234	1		T238	1
all_values[15]	auto[1]	auto[1]	auto[1]	62	1			T233	3		T234	1		T235	1
all_values[16]	auto[0]	auto[0]	auto[0]	51	1			T233	1		T235	1		T238	1
all_values[16]	auto[0]	auto[0]	auto[1]	23	1			T234	1		T235	1		T356	2
all_values[16]	auto[0]	auto[1]	auto[0]	57	1			T233	4		T237	1		T357	1
all_values[16]	auto[0]	auto[1]	auto[1]	28	1			T233	1		T238	1		T323	1
all_values[16]	auto[1]	auto[0]	auto[1]	47	1			T234	3		T235	2		T238	1
all_values[16]	auto[1]	auto[1]	auto[1]	75	1			T233	1		T238	1		T356	1
all_values[17]	auto[0]	auto[0]	auto[0]	92	1			T233	2		T235	1		T238	2
all_values[17]	auto[0]	auto[1]	auto[0]	61	1			T233	1		T234	2		T235	1
all_values[17]	auto[1]	auto[0]	auto[1]	83	1			T233	4		T235	2		T238	1
all_values[17]	auto[1]	auto[1]	auto[1]	45	1			T234	2		T237	2		T356	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal