Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.28 98.11 95.94 97.44 93.22 98.30 98.17 92.76


Total test records in report: 3739
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html | tests63.html | tests64.html | tests65.html | tests66.html | tests67.html | tests68.html | tests69.html | tests70.html | tests71.html | tests72.html | tests73.html | tests74.html | tests75.html | tests76.html | tests77.html | tests78.html | tests79.html
T3577 /workspace/coverage/default/24.usbdev_phy_pins_sense.3365746159 Aug 17 06:07:24 PM PDT 24 Aug 17 06:07:24 PM PDT 24 50345529 ps
T3578 /workspace/coverage/default/48.usbdev_tx_rx_disruption.930179131 Aug 17 06:11:07 PM PDT 24 Aug 17 06:11:08 PM PDT 24 500718172 ps
T3579 /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.4057238278 Aug 17 06:05:18 PM PDT 24 Aug 17 06:05:44 PM PDT 24 2519519525 ps
T3580 /workspace/coverage/default/287.usbdev_tx_rx_disruption.342080087 Aug 17 06:12:35 PM PDT 24 Aug 17 06:12:36 PM PDT 24 600664239 ps
T3581 /workspace/coverage/default/33.usbdev_out_trans_nak.2188218361 Aug 17 06:08:43 PM PDT 24 Aug 17 06:08:44 PM PDT 24 184085914 ps
T3582 /workspace/coverage/default/15.usbdev_rx_crc_err.4103951245 Aug 17 06:05:49 PM PDT 24 Aug 17 06:05:50 PM PDT 24 147740444 ps
T419 /workspace/coverage/default/49.usbdev_endpoint_types.1296496674 Aug 17 06:11:01 PM PDT 24 Aug 17 06:11:03 PM PDT 24 318384831 ps
T3583 /workspace/coverage/default/44.usbdev_min_length_in_transaction.1256150884 Aug 17 06:10:26 PM PDT 24 Aug 17 06:10:27 PM PDT 24 159436578 ps
T3584 /workspace/coverage/default/5.usbdev_fifo_rst.52180036 Aug 17 06:03:37 PM PDT 24 Aug 17 06:03:40 PM PDT 24 178397599 ps
T3585 /workspace/coverage/default/18.usbdev_device_address.2485165850 Aug 17 06:06:24 PM PDT 24 Aug 17 06:07:02 PM PDT 24 24882482238 ps
T3586 /workspace/coverage/default/16.usbdev_pkt_buffer.873108738 Aug 17 06:06:08 PM PDT 24 Aug 17 06:06:50 PM PDT 24 15124465391 ps
T3587 /workspace/coverage/default/22.usbdev_alert_test.1754456917 Aug 17 06:07:11 PM PDT 24 Aug 17 06:07:12 PM PDT 24 54220746 ps
T3588 /workspace/coverage/default/12.usbdev_phy_config_pinflip.3254493071 Aug 17 06:05:19 PM PDT 24 Aug 17 06:05:20 PM PDT 24 200940839 ps
T3589 /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.1193567466 Aug 17 06:05:58 PM PDT 24 Aug 17 06:06:16 PM PDT 24 2135640057 ps
T3590 /workspace/coverage/default/158.usbdev_tx_rx_disruption.2194709221 Aug 17 06:11:59 PM PDT 24 Aug 17 06:12:02 PM PDT 24 629659510 ps
T3591 /workspace/coverage/default/9.usbdev_pkt_received.4242310731 Aug 17 06:04:51 PM PDT 24 Aug 17 06:04:52 PM PDT 24 164821940 ps
T3592 /workspace/coverage/default/482.usbdev_tx_rx_disruption.384279266 Aug 17 06:12:30 PM PDT 24 Aug 17 06:12:32 PM PDT 24 538484436 ps
T3593 /workspace/coverage/default/31.usbdev_max_length_out_transaction.145976910 Aug 17 06:08:24 PM PDT 24 Aug 17 06:08:25 PM PDT 24 194988170 ps
T3594 /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3521670148 Aug 17 06:10:00 PM PDT 24 Aug 17 06:10:01 PM PDT 24 225293316 ps
T3595 /workspace/coverage/default/99.usbdev_tx_rx_disruption.1055252124 Aug 17 06:11:48 PM PDT 24 Aug 17 06:11:50 PM PDT 24 519843946 ps
T3596 /workspace/coverage/default/44.usbdev_phy_config_pinflip.3113739042 Aug 17 06:10:28 PM PDT 24 Aug 17 06:10:29 PM PDT 24 208878249 ps
T3597 /workspace/coverage/default/40.usbdev_setup_stage.2362990626 Aug 17 06:09:53 PM PDT 24 Aug 17 06:09:54 PM PDT 24 177648806 ps
T3598 /workspace/coverage/default/19.usbdev_link_in_err.2040709774 Aug 17 06:06:32 PM PDT 24 Aug 17 06:06:33 PM PDT 24 202999045 ps
T3599 /workspace/coverage/default/75.usbdev_tx_rx_disruption.965077571 Aug 17 06:11:12 PM PDT 24 Aug 17 06:11:14 PM PDT 24 535063679 ps
T3600 /workspace/coverage/default/40.usbdev_setup_trans_ignored.1211344060 Aug 17 06:09:54 PM PDT 24 Aug 17 06:09:55 PM PDT 24 148133239 ps
T3601 /workspace/coverage/default/17.usbdev_smoke.3061869687 Aug 17 06:06:18 PM PDT 24 Aug 17 06:06:19 PM PDT 24 236179600 ps
T3602 /workspace/coverage/default/22.usbdev_link_resume.483859610 Aug 17 06:07:04 PM PDT 24 Aug 17 06:07:22 PM PDT 24 12421935341 ps
T3603 /workspace/coverage/default/28.usbdev_disconnected.670056745 Aug 17 06:07:54 PM PDT 24 Aug 17 06:07:55 PM PDT 24 162128968 ps
T3604 /workspace/coverage/default/46.usbdev_aon_wake_reset.646736619 Aug 17 06:10:28 PM PDT 24 Aug 17 06:10:46 PM PDT 24 14834884224 ps
T3605 /workspace/coverage/default/34.usbdev_device_timeout.237493988 Aug 17 06:08:49 PM PDT 24 Aug 17 06:08:50 PM PDT 24 155396246 ps
T3606 /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.1273348359 Aug 17 06:07:34 PM PDT 24 Aug 17 06:07:54 PM PDT 24 876926915 ps
T3607 /workspace/coverage/default/49.usbdev_out_stall.2843467647 Aug 17 06:11:01 PM PDT 24 Aug 17 06:11:02 PM PDT 24 213379995 ps
T3608 /workspace/coverage/default/25.usbdev_av_buffer.2870371427 Aug 17 06:07:26 PM PDT 24 Aug 17 06:07:27 PM PDT 24 145067479 ps
T3609 /workspace/coverage/default/3.usbdev_spurious_pids_ignored.591380175 Aug 17 06:03:17 PM PDT 24 Aug 17 06:04:23 PM PDT 24 2130807549 ps
T3610 /workspace/coverage/default/11.usbdev_min_length_out_transaction.2297394968 Aug 17 06:05:06 PM PDT 24 Aug 17 06:05:07 PM PDT 24 161898241 ps
T3611 /workspace/coverage/default/114.usbdev_tx_rx_disruption.3824281815 Aug 17 06:11:37 PM PDT 24 Aug 17 06:11:39 PM PDT 24 532594824 ps
T3612 /workspace/coverage/default/195.usbdev_tx_rx_disruption.3113138632 Aug 17 06:11:51 PM PDT 24 Aug 17 06:11:52 PM PDT 24 425081548 ps
T3613 /workspace/coverage/default/47.usbdev_link_resume.1861030050 Aug 17 06:10:49 PM PDT 24 Aug 17 06:11:45 PM PDT 24 34692335204 ps
T3614 /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.3001282726 Aug 17 06:04:51 PM PDT 24 Aug 17 06:05:02 PM PDT 24 1108900346 ps
T3615 /workspace/coverage/default/32.usbdev_out_iso.820282683 Aug 17 06:08:37 PM PDT 24 Aug 17 06:08:38 PM PDT 24 175477802 ps
T3616 /workspace/coverage/default/32.usbdev_enable.193304525 Aug 17 06:08:48 PM PDT 24 Aug 17 06:08:49 PM PDT 24 37857618 ps
T3617 /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4276067054 Aug 17 06:06:17 PM PDT 24 Aug 17 06:06:18 PM PDT 24 181374363 ps
T3618 /workspace/coverage/default/2.usbdev_stall_trans.332883295 Aug 17 06:03:01 PM PDT 24 Aug 17 06:03:02 PM PDT 24 211394137 ps
T430 /workspace/coverage/default/193.usbdev_endpoint_types.3958782333 Aug 17 06:11:59 PM PDT 24 Aug 17 06:12:00 PM PDT 24 762862859 ps
T3619 /workspace/coverage/default/4.usbdev_freq_loclk.107530500 Aug 17 06:03:22 PM PDT 24 Aug 17 06:06:32 PM PDT 24 111124910568 ps
T3620 /workspace/coverage/default/498.usbdev_tx_rx_disruption.3918605288 Aug 17 06:12:29 PM PDT 24 Aug 17 06:12:31 PM PDT 24 531290855 ps
T3621 /workspace/coverage/default/18.usbdev_disconnected.1202806222 Aug 17 06:06:33 PM PDT 24 Aug 17 06:06:34 PM PDT 24 154576560 ps
T3622 /workspace/coverage/default/37.usbdev_device_address.3232027559 Aug 17 06:09:10 PM PDT 24 Aug 17 06:09:42 PM PDT 24 16585980567 ps
T3623 /workspace/coverage/default/45.usbdev_in_stall.2014680472 Aug 17 06:10:28 PM PDT 24 Aug 17 06:10:29 PM PDT 24 144730119 ps
T3624 /workspace/coverage/default/49.usbdev_tx_rx_disruption.3558716380 Aug 17 06:10:59 PM PDT 24 Aug 17 06:11:01 PM PDT 24 632924919 ps
T3625 /workspace/coverage/default/9.usbdev_disconnected.3000952 Aug 17 06:04:35 PM PDT 24 Aug 17 06:04:36 PM PDT 24 170101418 ps
T3626 /workspace/coverage/default/76.usbdev_tx_rx_disruption.4093261492 Aug 17 06:11:21 PM PDT 24 Aug 17 06:11:23 PM PDT 24 405437568 ps
T3627 /workspace/coverage/default/82.usbdev_tx_rx_disruption.3668759593 Aug 17 06:11:22 PM PDT 24 Aug 17 06:11:24 PM PDT 24 486614359 ps
T3628 /workspace/coverage/default/35.usbdev_min_length_out_transaction.2405789491 Aug 17 06:09:02 PM PDT 24 Aug 17 06:09:03 PM PDT 24 161828531 ps
T3629 /workspace/coverage/default/77.usbdev_endpoint_types.1454388788 Aug 17 06:11:23 PM PDT 24 Aug 17 06:11:25 PM PDT 24 206014829 ps
T3630 /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.4135867320 Aug 17 06:03:36 PM PDT 24 Aug 17 06:03:37 PM PDT 24 246457060 ps
T3631 /workspace/coverage/default/45.usbdev_min_length_out_transaction.1865628995 Aug 17 06:10:29 PM PDT 24 Aug 17 06:10:30 PM PDT 24 144988365 ps
T3632 /workspace/coverage/default/12.usbdev_aon_wake_reset.2474217047 Aug 17 06:05:13 PM PDT 24 Aug 17 06:05:30 PM PDT 24 15155223501 ps
T3633 /workspace/coverage/default/50.usbdev_tx_rx_disruption.3267821217 Aug 17 06:11:05 PM PDT 24 Aug 17 06:11:07 PM PDT 24 544074644 ps
T3634 /workspace/coverage/default/7.usbdev_random_length_out_transaction.2080009346 Aug 17 06:04:19 PM PDT 24 Aug 17 06:04:20 PM PDT 24 184354267 ps
T3635 /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.621061932 Aug 17 06:11:02 PM PDT 24 Aug 17 06:11:28 PM PDT 24 3271200748 ps
T3636 /workspace/coverage/default/174.usbdev_tx_rx_disruption.4113116434 Aug 17 06:11:57 PM PDT 24 Aug 17 06:11:58 PM PDT 24 487655486 ps
T3637 /workspace/coverage/default/23.usbdev_link_in_err.1504140938 Aug 17 06:07:10 PM PDT 24 Aug 17 06:07:12 PM PDT 24 231455521 ps
T3638 /workspace/coverage/default/28.usbdev_aon_wake_resume.2378359391 Aug 17 06:07:53 PM PDT 24 Aug 17 06:08:30 PM PDT 24 28588753544 ps
T229 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3246131403 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:13 PM PDT 24 565846607 ps
T248 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2490048122 Aug 17 06:34:17 PM PDT 24 Aug 17 06:34:19 PM PDT 24 102547641 ps
T230 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1968585030 Aug 17 06:34:24 PM PDT 24 Aug 17 06:34:29 PM PDT 24 763558179 ps
T231 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1060241797 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:13 PM PDT 24 176944552 ps
T299 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3139751470 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:10 PM PDT 24 263065478 ps
T300 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4001138413 Aug 17 06:34:46 PM PDT 24 Aug 17 06:34:48 PM PDT 24 170931434 ps
T246 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2652813002 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:14 PM PDT 24 218915220 ps
T233 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1472074758 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:10 PM PDT 24 47989674 ps
T247 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1379580214 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:11 PM PDT 24 141052911 ps
T263 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.663075997 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:10 PM PDT 24 102343353 ps
T301 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1389181161 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:15 PM PDT 24 204095209 ps
T302 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1356033230 Aug 17 06:34:26 PM PDT 24 Aug 17 06:34:27 PM PDT 24 173155846 ps
T234 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1831128473 Aug 17 06:34:18 PM PDT 24 Aug 17 06:34:24 PM PDT 24 32241035 ps
T235 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1571907751 Aug 17 06:34:36 PM PDT 24 Aug 17 06:34:37 PM PDT 24 38895940 ps
T238 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.548446518 Aug 17 06:34:17 PM PDT 24 Aug 17 06:34:18 PM PDT 24 44091986 ps
T254 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3062702770 Aug 17 06:34:33 PM PDT 24 Aug 17 06:34:36 PM PDT 24 578865439 ps
T236 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2383969791 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:11 PM PDT 24 117242656 ps
T237 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.625909097 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:14 PM PDT 24 48149053 ps
T303 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4075934457 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:09 PM PDT 24 320859325 ps
T255 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2305819561 Aug 17 06:34:16 PM PDT 24 Aug 17 06:34:18 PM PDT 24 87531723 ps
T3639 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2652058912 Aug 17 06:34:14 PM PDT 24 Aug 17 06:34:15 PM PDT 24 99402483 ps
T316 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1403974864 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:14 PM PDT 24 1475429301 ps
T252 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1791750563 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:12 PM PDT 24 67514421 ps
T304 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3346416358 Aug 17 06:34:12 PM PDT 24 Aug 17 06:34:14 PM PDT 24 119153950 ps
T256 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1634643901 Aug 17 06:34:18 PM PDT 24 Aug 17 06:34:20 PM PDT 24 143324679 ps
T305 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3636372617 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:07 PM PDT 24 126159528 ps
T264 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2861199072 Aug 17 06:34:40 PM PDT 24 Aug 17 06:34:41 PM PDT 24 78383802 ps
T259 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1717347402 Aug 17 06:34:32 PM PDT 24 Aug 17 06:34:34 PM PDT 24 72017352 ps
T257 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1051486349 Aug 17 06:34:16 PM PDT 24 Aug 17 06:34:23 PM PDT 24 188132116 ps
T356 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2320859735 Aug 17 06:34:36 PM PDT 24 Aug 17 06:34:37 PM PDT 24 40039710 ps
T280 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1518667411 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:12 PM PDT 24 193440372 ps
T260 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2119128831 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 54287569 ps
T361 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.740853069 Aug 17 06:34:23 PM PDT 24 Aug 17 06:34:26 PM PDT 24 451038315 ps
T306 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1937621208 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:44 PM PDT 24 161442037 ps
T357 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4108463993 Aug 17 06:34:27 PM PDT 24 Aug 17 06:34:27 PM PDT 24 34800692 ps
T323 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1978571195 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:11 PM PDT 24 101195004 ps
T307 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2956849633 Aug 17 06:34:19 PM PDT 24 Aug 17 06:34:21 PM PDT 24 110172925 ps
T324 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1995533708 Aug 17 06:34:12 PM PDT 24 Aug 17 06:34:13 PM PDT 24 85568970 ps
T281 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3566215026 Aug 17 06:34:27 PM PDT 24 Aug 17 06:34:28 PM PDT 24 78918802 ps
T3640 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3730821070 Aug 17 06:34:34 PM PDT 24 Aug 17 06:34:36 PM PDT 24 70236069 ps
T3641 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2382234353 Aug 17 06:34:12 PM PDT 24 Aug 17 06:34:14 PM PDT 24 194367890 ps
T359 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.110674125 Aug 17 06:34:28 PM PDT 24 Aug 17 06:34:29 PM PDT 24 55869695 ps
T258 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3841623993 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 97897980 ps
T282 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1079643646 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:12 PM PDT 24 84536943 ps
T3642 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2247746356 Aug 17 06:34:46 PM PDT 24 Aug 17 06:34:46 PM PDT 24 38417265 ps
T360 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2646846518 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:21 PM PDT 24 35049829 ps
T325 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.235875840 Aug 17 06:34:46 PM PDT 24 Aug 17 06:34:46 PM PDT 24 52532083 ps
T3643 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1488053398 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:14 PM PDT 24 480955980 ps
T317 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3125613814 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:10 PM PDT 24 506516057 ps
T321 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1610331101 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:19 PM PDT 24 111903086 ps
T3644 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1714815366 Aug 17 06:34:54 PM PDT 24 Aug 17 06:34:55 PM PDT 24 65079351 ps
T3645 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2297121184 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:14 PM PDT 24 41606155 ps
T358 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1631645966 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:50 PM PDT 24 40918318 ps
T3646 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2672358272 Aug 17 06:34:47 PM PDT 24 Aug 17 06:34:48 PM PDT 24 48162469 ps
T3647 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2543803105 Aug 17 06:34:48 PM PDT 24 Aug 17 06:34:49 PM PDT 24 45837765 ps
T3648 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2302118492 Aug 17 06:34:40 PM PDT 24 Aug 17 06:34:42 PM PDT 24 186507587 ps
T283 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3084512998 Aug 17 06:34:16 PM PDT 24 Aug 17 06:34:17 PM PDT 24 72876986 ps
T284 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1912143174 Aug 17 06:34:19 PM PDT 24 Aug 17 06:34:20 PM PDT 24 56386030 ps
T3649 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1953738294 Aug 17 06:34:47 PM PDT 24 Aug 17 06:34:48 PM PDT 24 73342627 ps
T318 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3384271986 Aug 17 06:34:45 PM PDT 24 Aug 17 06:34:47 PM PDT 24 170113145 ps
T3650 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3162940608 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:11 PM PDT 24 214597132 ps
T3651 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3727425245 Aug 17 06:34:46 PM PDT 24 Aug 17 06:34:47 PM PDT 24 37060030 ps
T262 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1760630924 Aug 17 06:34:22 PM PDT 24 Aug 17 06:34:25 PM PDT 24 100333763 ps
T261 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2312589936 Aug 17 06:34:20 PM PDT 24 Aug 17 06:34:22 PM PDT 24 144996151 ps
T3652 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2774981966 Aug 17 06:34:15 PM PDT 24 Aug 17 06:34:16 PM PDT 24 137837641 ps
T3653 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3790681407 Aug 17 06:34:26 PM PDT 24 Aug 17 06:34:27 PM PDT 24 94641247 ps
T319 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2660347477 Aug 17 06:34:16 PM PDT 24 Aug 17 06:34:22 PM PDT 24 1154033678 ps
T3654 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2530418983 Aug 17 06:34:18 PM PDT 24 Aug 17 06:34:19 PM PDT 24 39199240 ps
T326 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4188815042 Aug 17 06:34:31 PM PDT 24 Aug 17 06:34:33 PM PDT 24 118567684 ps
T3655 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.937264983 Aug 17 06:34:22 PM PDT 24 Aug 17 06:34:23 PM PDT 24 88720179 ps
T322 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2383442929 Aug 17 06:34:36 PM PDT 24 Aug 17 06:34:37 PM PDT 24 94406464 ps
T3656 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.977291366 Aug 17 06:34:44 PM PDT 24 Aug 17 06:34:45 PM PDT 24 107140943 ps
T3657 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1963386312 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:45 PM PDT 24 712763051 ps
T3658 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2659866581 Aug 17 06:34:33 PM PDT 24 Aug 17 06:34:36 PM PDT 24 259656240 ps
T285 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1247819634 Aug 17 06:34:18 PM PDT 24 Aug 17 06:34:19 PM PDT 24 54381629 ps
T3659 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1354020566 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:08 PM PDT 24 348444134 ps
T3660 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.229068661 Aug 17 06:34:40 PM PDT 24 Aug 17 06:34:40 PM PDT 24 91011551 ps
T3661 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4073943850 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 160559813 ps
T3662 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2535960768 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:14 PM PDT 24 168441435 ps
T3663 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.743511718 Aug 17 06:34:17 PM PDT 24 Aug 17 06:34:19 PM PDT 24 94995033 ps
T3664 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3402652028 Aug 17 06:34:27 PM PDT 24 Aug 17 06:34:28 PM PDT 24 55109939 ps
T3665 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1776296661 Aug 17 06:34:18 PM PDT 24 Aug 17 06:34:18 PM PDT 24 42828584 ps
T320 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3501352283 Aug 17 06:34:14 PM PDT 24 Aug 17 06:34:16 PM PDT 24 205550052 ps
T286 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4090807106 Aug 17 06:34:29 PM PDT 24 Aug 17 06:34:30 PM PDT 24 67700225 ps
T3666 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2274756670 Aug 17 06:34:02 PM PDT 24 Aug 17 06:34:03 PM PDT 24 57979018 ps
T3667 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1291489339 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:14 PM PDT 24 123090193 ps
T3668 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.573130005 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:13 PM PDT 24 422272629 ps
T364 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1614284052 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:14 PM PDT 24 549445836 ps
T3669 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3495583748 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:12 PM PDT 24 43179492 ps
T3670 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.733985407 Aug 17 06:34:22 PM PDT 24 Aug 17 06:34:23 PM PDT 24 44010425 ps
T287 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.383434850 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:11 PM PDT 24 171198477 ps
T3671 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.747940316 Aug 17 06:34:22 PM PDT 24 Aug 17 06:34:23 PM PDT 24 73821422 ps
T3672 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2601208768 Aug 17 06:34:40 PM PDT 24 Aug 17 06:34:42 PM PDT 24 77182230 ps
T288 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1434725703 Aug 17 06:34:12 PM PDT 24 Aug 17 06:34:22 PM PDT 24 984026634 ps
T289 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4231538561 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:11 PM PDT 24 403266976 ps
T3673 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4281751629 Aug 17 06:34:48 PM PDT 24 Aug 17 06:34:48 PM PDT 24 47798332 ps
T3674 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.581201425 Aug 17 06:34:17 PM PDT 24 Aug 17 06:34:18 PM PDT 24 52728021 ps
T3675 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2424874800 Aug 17 06:34:37 PM PDT 24 Aug 17 06:34:40 PM PDT 24 87643516 ps
T290 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2871848347 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:51 PM PDT 24 60795861 ps
T3676 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1427299136 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:14 PM PDT 24 109592282 ps
T365 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3163549988 Aug 17 06:34:18 PM PDT 24 Aug 17 06:34:21 PM PDT 24 424382789 ps
T3677 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1042199564 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:16 PM PDT 24 228879889 ps
T3678 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3715275798 Aug 17 06:34:19 PM PDT 24 Aug 17 06:34:20 PM PDT 24 60316491 ps
T3679 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.87564216 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 193797004 ps
T3680 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4199451554 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:43 PM PDT 24 48421111 ps
T3681 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3577427489 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:14 PM PDT 24 1005233216 ps
T3682 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.315388476 Aug 17 06:34:45 PM PDT 24 Aug 17 06:34:46 PM PDT 24 39752741 ps
T3683 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2181642874 Aug 17 06:34:19 PM PDT 24 Aug 17 06:34:19 PM PDT 24 96453059 ps
T3684 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.851167023 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:43 PM PDT 24 74211517 ps
T3685 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2516261872 Aug 17 06:34:15 PM PDT 24 Aug 17 06:34:16 PM PDT 24 74689910 ps
T3686 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3755850673 Aug 17 06:34:32 PM PDT 24 Aug 17 06:34:33 PM PDT 24 55985019 ps
T3687 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3401699206 Aug 17 06:34:18 PM PDT 24 Aug 17 06:34:23 PM PDT 24 1134561201 ps
T3688 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1223195828 Aug 17 06:34:16 PM PDT 24 Aug 17 06:34:19 PM PDT 24 149332612 ps
T3689 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2203970585 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:14 PM PDT 24 328140331 ps
T3690 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2843210599 Aug 17 06:34:53 PM PDT 24 Aug 17 06:34:54 PM PDT 24 136229747 ps
T3691 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.729823571 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:12 PM PDT 24 1327903681 ps
T3692 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.737958660 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:13 PM PDT 24 516205404 ps
T3693 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.378930930 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 144100703 ps
T291 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1646414740 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 115255582 ps
T3694 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3194175363 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:12 PM PDT 24 164563260 ps
T3695 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.928994168 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:10 PM PDT 24 117085362 ps
T296 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.326928234 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:14 PM PDT 24 55722310 ps
T368 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.412842010 Aug 17 06:34:36 PM PDT 24 Aug 17 06:34:41 PM PDT 24 1815571060 ps
T3696 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2980675853 Aug 17 06:34:34 PM PDT 24 Aug 17 06:34:36 PM PDT 24 94269967 ps
T3697 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2730825016 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:10 PM PDT 24 294532237 ps
T3698 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1462582387 Aug 17 06:34:25 PM PDT 24 Aug 17 06:34:26 PM PDT 24 65416568 ps
T3699 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3576072017 Aug 17 06:34:49 PM PDT 24 Aug 17 06:34:49 PM PDT 24 45506907 ps
T3700 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4021928113 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:11 PM PDT 24 91532967 ps
T3701 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3972967041 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:56 PM PDT 24 43963822 ps
T3702 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4037209366 Aug 17 06:34:17 PM PDT 24 Aug 17 06:34:18 PM PDT 24 54611925 ps
T3703 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.706967871 Aug 17 06:34:34 PM PDT 24 Aug 17 06:34:37 PM PDT 24 496547448 ps
T3704 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1477278412 Aug 17 06:34:32 PM PDT 24 Aug 17 06:34:35 PM PDT 24 495934767 ps
T3705 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.527896108 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:21 PM PDT 24 367368099 ps
T3706 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.910828245 Aug 17 06:34:14 PM PDT 24 Aug 17 06:34:21 PM PDT 24 94269096 ps
T292 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1388168593 Aug 17 06:34:28 PM PDT 24 Aug 17 06:34:29 PM PDT 24 85978703 ps
T3707 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.179719988 Aug 17 06:34:27 PM PDT 24 Aug 17 06:34:28 PM PDT 24 101162401 ps
T293 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1377125044 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:12 PM PDT 24 201834832 ps
T297 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2699685604 Aug 17 06:34:17 PM PDT 24 Aug 17 06:34:18 PM PDT 24 94148880 ps
T3708 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.560075456 Aug 17 06:34:17 PM PDT 24 Aug 17 06:34:18 PM PDT 24 59585902 ps
T3709 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4116386235 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:15 PM PDT 24 739088140 ps
T3710 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3395454505 Aug 17 06:34:15 PM PDT 24 Aug 17 06:34:16 PM PDT 24 40088891 ps
T3711 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.254905348 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:12 PM PDT 24 61964815 ps
T3712 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1920690540 Aug 17 06:34:36 PM PDT 24 Aug 17 06:34:41 PM PDT 24 758365007 ps
T298 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.438719322 Aug 17 06:34:20 PM PDT 24 Aug 17 06:34:21 PM PDT 24 61057516 ps
T3713 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1509485879 Aug 17 06:34:39 PM PDT 24 Aug 17 06:34:40 PM PDT 24 96520236 ps
T294 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.932951795 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:10 PM PDT 24 75377208 ps
T3714 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.361527121 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:08 PM PDT 24 87407391 ps
T3715 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3522773535 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:18 PM PDT 24 698045188 ps
T3716 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1176346165 Aug 17 06:34:47 PM PDT 24 Aug 17 06:34:49 PM PDT 24 170100968 ps
T3717 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3396480608 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 193499543 ps
T3718 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1729876489 Aug 17 06:34:24 PM PDT 24 Aug 17 06:34:29 PM PDT 24 625960795 ps
T3719 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3696251676 Aug 17 06:34:26 PM PDT 24 Aug 17 06:34:28 PM PDT 24 398948556 ps
T3720 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1754405238 Aug 17 06:34:14 PM PDT 24 Aug 17 06:34:15 PM PDT 24 74120441 ps
T3721 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2688000396 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:10 PM PDT 24 61253120 ps
T362 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.73862914 Aug 17 06:34:16 PM PDT 24 Aug 17 06:34:20 PM PDT 24 1048613898 ps
T295 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3159941267 Aug 17 06:34:20 PM PDT 24 Aug 17 06:34:21 PM PDT 24 51429592 ps
T3722 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.805605749 Aug 17 06:34:43 PM PDT 24 Aug 17 06:34:44 PM PDT 24 67517265 ps
T3723 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.47329045 Aug 17 06:34:19 PM PDT 24 Aug 17 06:34:21 PM PDT 24 104230111 ps
T3724 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1325654431 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:15 PM PDT 24 105454634 ps
T3725 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2861636656 Aug 17 06:34:17 PM PDT 24 Aug 17 06:34:18 PM PDT 24 49293635 ps
T363 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3218253812 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:18 PM PDT 24 513301001 ps
T3726 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1210228270 Aug 17 06:34:31 PM PDT 24 Aug 17 06:34:33 PM PDT 24 89072235 ps
T3727 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1548491979 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:10 PM PDT 24 292451217 ps
T3728 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1945059548 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:45 PM PDT 24 94676979 ps
T3729 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3932707860 Aug 17 06:34:25 PM PDT 24 Aug 17 06:34:26 PM PDT 24 197295789 ps
T3730 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3396419519 Aug 17 06:34:14 PM PDT 24 Aug 17 06:34:15 PM PDT 24 69897213 ps
T3731 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.623112182 Aug 17 06:34:17 PM PDT 24 Aug 17 06:34:18 PM PDT 24 44173550 ps
T3732 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2669354183 Aug 17 06:34:47 PM PDT 24 Aug 17 06:34:48 PM PDT 24 68636782 ps
T3733 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2091969245 Aug 17 06:34:15 PM PDT 24 Aug 17 06:34:17 PM PDT 24 152795811 ps
T3734 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.153576742 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:10 PM PDT 24 101145524 ps
T3735 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1516836631 Aug 17 06:34:15 PM PDT 24 Aug 17 06:34:18 PM PDT 24 284122560 ps
T3736 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2371422901 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:15 PM PDT 24 362656898 ps
T3737 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2532030130 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:15 PM PDT 24 69696442 ps
T3738 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2376681684 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:11 PM PDT 24 71782161 ps
T3739 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4123574814 Aug 17 06:34:38 PM PDT 24 Aug 17 06:34:39 PM PDT 24 68587845 ps

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1363992562
Short name T5
Test name
Test status
Simulation time 5852513250 ps
CPU time 24.6 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:30 PM PDT 24
Peak memory 224084 kb
Host smart-e48593e8-a3f4-4ea4-b74c-8df7f175c862
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363992562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1363992562
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2367654565
Short name T27
Test name
Test status
Simulation time 19043723219 ps
CPU time 37.27 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207800 kb
Host smart-f9f1c36f-0f2d-464e-97a2-f60dd1ac3305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23676
54565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2367654565
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.705996902
Short name T1
Test name
Test status
Simulation time 15069160621 ps
CPU time 19.4 seconds
Started Aug 17 06:08:34 PM PDT 24
Finished Aug 17 06:08:53 PM PDT 24
Peak memory 216172 kb
Host smart-e6ff7ebc-d6c3-4b1f-9f8b-d27e42ddde17
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=705996902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.705996902
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.625909097
Short name T237
Test name
Test status
Simulation time 48149053 ps
CPU time 0.73 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 206912 kb
Host smart-6b791bdb-42c8-4cb8-865e-a6451cc4d98a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=625909097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.625909097
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3062702770
Short name T254
Test name
Test status
Simulation time 578865439 ps
CPU time 3.05 seconds
Started Aug 17 06:34:33 PM PDT 24
Finished Aug 17 06:34:36 PM PDT 24
Peak memory 207216 kb
Host smart-f4ee8c55-2555-442f-9219-d947d2f918bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3062702770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3062702770
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.726192150
Short name T118
Test name
Test status
Simulation time 3572811610 ps
CPU time 111.9 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:05:00 PM PDT 24
Peak memory 224040 kb
Host smart-30d9d547-8a30-4731-b398-e15d7f9bfa8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=726192150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.726192150
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.1556428575
Short name T23
Test name
Test status
Simulation time 833119559 ps
CPU time 2.71 seconds
Started Aug 17 06:02:49 PM PDT 24
Finished Aug 17 06:02:52 PM PDT 24
Peak memory 207764 kb
Host smart-72f0cac6-8ce8-4aaa-8a2e-84de259fa284
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1556428575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1556428575
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.1210791578
Short name T38
Test name
Test status
Simulation time 30831545126 ps
CPU time 51.66 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207876 kb
Host smart-b7d623ed-4883-4b15-b22e-45d286f0b6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
91578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.1210791578
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.2698963759
Short name T101
Test name
Test status
Simulation time 7592333522 ps
CPU time 9.66 seconds
Started Aug 17 06:06:52 PM PDT 24
Finished Aug 17 06:07:02 PM PDT 24
Peak memory 215940 kb
Host smart-aa36ba9d-d4a9-466c-84d7-e8318d359018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26989
63759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.2698963759
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.696826307
Short name T215
Test name
Test status
Simulation time 345273882 ps
CPU time 1.1 seconds
Started Aug 17 06:02:22 PM PDT 24
Finished Aug 17 06:02:23 PM PDT 24
Peak memory 207444 kb
Host smart-4f7cc148-1404-4936-aa3b-12301dffdb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69682
6307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.696826307
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2718211238
Short name T239
Test name
Test status
Simulation time 269230723 ps
CPU time 1.13 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:38 PM PDT 24
Peak memory 223292 kb
Host smart-71c7244d-b2c7-4427-8c70-fdfc69d751d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2718211238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2718211238
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1472074758
Short name T233
Test name
Test status
Simulation time 47989674 ps
CPU time 0.72 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 206872 kb
Host smart-d24f949d-6c46-4d0d-b732-45885f433533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1472074758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1472074758
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/default/143.usbdev_tx_rx_disruption.2935294639
Short name T119
Test name
Test status
Simulation time 439544171 ps
CPU time 1.54 seconds
Started Aug 17 06:11:50 PM PDT 24
Finished Aug 17 06:11:51 PM PDT 24
Peak memory 207500 kb
Host smart-a9210c87-53ab-4db7-b4cb-df44240d49cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935294639 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.usbdev_tx_rx_disruption.2935294639
Directory /workspace/143.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2652813002
Short name T246
Test name
Test status
Simulation time 218915220 ps
CPU time 2.61 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 219924 kb
Host smart-ad915f2e-b1ce-4f87-a66e-0db72c2123c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2652813002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2652813002
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1320721656
Short name T33
Test name
Test status
Simulation time 38001114 ps
CPU time 0.71 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 207524 kb
Host smart-1bb384a8-4d78-48b7-9db9-564cb162ba01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13207
21656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1320721656
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/168.usbdev_tx_rx_disruption.1122804548
Short name T216
Test name
Test status
Simulation time 571401586 ps
CPU time 1.56 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207508 kb
Host smart-ccdfa2e9-18e5-42c3-8933-6393b2534dab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122804548 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.usbdev_tx_rx_disruption.1122804548
Directory /workspace/168.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2900658442
Short name T592
Test name
Test status
Simulation time 183950974 ps
CPU time 0.94 seconds
Started Aug 17 06:06:08 PM PDT 24
Finished Aug 17 06:06:09 PM PDT 24
Peak memory 207516 kb
Host smart-ca9bfb48-e068-48be-8970-b92b16d5d1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
58442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2900658442
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1488062829
Short name T104
Test name
Test status
Simulation time 5338528709 ps
CPU time 8.39 seconds
Started Aug 17 06:04:47 PM PDT 24
Finished Aug 17 06:04:56 PM PDT 24
Peak memory 215888 kb
Host smart-cee59aab-188d-4df6-9c6c-126ad13b06a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488062829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.1488062829
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1300964903
Short name T36
Test name
Test status
Simulation time 10490942721 ps
CPU time 14.72 seconds
Started Aug 17 06:09:55 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207804 kb
Host smart-2bbcffad-3460-4db6-a58b-856f4a9732bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13009
64903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1300964903
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2201336491
Short name T113
Test name
Test status
Simulation time 39975827228 ps
CPU time 76.16 seconds
Started Aug 17 06:06:31 PM PDT 24
Finished Aug 17 06:07:48 PM PDT 24
Peak memory 207764 kb
Host smart-8604ca70-2b5c-4669-80df-e87e4dd78a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22013
36491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2201336491
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1416107544
Short name T97
Test name
Test status
Simulation time 9022972398 ps
CPU time 23.73 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:27 PM PDT 24
Peak memory 224112 kb
Host smart-416e26fb-1d54-4faf-a374-2b4076159620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14161
07544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1416107544
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.789418192
Short name T68
Test name
Test status
Simulation time 162047629 ps
CPU time 0.82 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207512 kb
Host smart-49555397-8128-403d-8b4f-17e474e6d481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78941
8192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.789418192
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.383434850
Short name T287
Test name
Test status
Simulation time 171198477 ps
CPU time 2.48 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 215412 kb
Host smart-5246bc59-f1c5-49ed-9ed1-76f1accfbae5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=383434850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.383434850
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/default/34.usbdev_rx_full.2235183369
Short name T50
Test name
Test status
Simulation time 305460526 ps
CPU time 1.25 seconds
Started Aug 17 06:09:00 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207484 kb
Host smart-fc1c6991-c8c1-4d16-82a1-3091462f2d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22351
83369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.2235183369
Directory /workspace/34.usbdev_rx_full/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_types.1615890026
Short name T382
Test name
Test status
Simulation time 767227503 ps
CPU time 1.82 seconds
Started Aug 17 06:08:48 PM PDT 24
Finished Aug 17 06:08:50 PM PDT 24
Peak memory 207524 kb
Host smart-aad0b6e2-dae7-4919-b069-28a3628bd5c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1615890026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.1615890026
Directory /workspace/34.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/196.usbdev_endpoint_types.3035271789
Short name T456
Test name
Test status
Simulation time 664296846 ps
CPU time 1.73 seconds
Started Aug 17 06:11:45 PM PDT 24
Finished Aug 17 06:11:47 PM PDT 24
Peak memory 207508 kb
Host smart-452fd4ea-3ff3-47f4-ad3c-293fff6258c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3035271789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.3035271789
Directory /workspace/196.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.4180208461
Short name T617
Test name
Test status
Simulation time 178157827 ps
CPU time 0.93 seconds
Started Aug 17 06:05:21 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 207436 kb
Host smart-3bc06bba-b132-44b4-ae8b-a9ca053d69ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41802
08461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.4180208461
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_device_address.4252077446
Short name T371
Test name
Test status
Simulation time 33050938429 ps
CPU time 53.9 seconds
Started Aug 17 06:08:28 PM PDT 24
Finished Aug 17 06:09:22 PM PDT 24
Peak memory 207688 kb
Host smart-3151930f-e031-44de-bb27-78acb37a057a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42520
77446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.4252077446
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/124.usbdev_endpoint_types.2157733829
Short name T402
Test name
Test status
Simulation time 1120576559 ps
CPU time 2.44 seconds
Started Aug 17 06:11:24 PM PDT 24
Finished Aug 17 06:11:26 PM PDT 24
Peak memory 207500 kb
Host smart-f05efe68-f0a8-443c-b204-40602365a337
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2157733829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.2157733829
Directory /workspace/124.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/138.usbdev_endpoint_types.332622307
Short name T388
Test name
Test status
Simulation time 445588492 ps
CPU time 1.33 seconds
Started Aug 17 06:11:27 PM PDT 24
Finished Aug 17 06:11:28 PM PDT 24
Peak memory 207532 kb
Host smart-48af3d9b-2ab3-4752-adc7-6200178aaa46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=332622307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.332622307
Directory /workspace/138.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_types.477664276
Short name T463
Test name
Test status
Simulation time 633555561 ps
CPU time 1.55 seconds
Started Aug 17 06:03:41 PM PDT 24
Finished Aug 17 06:03:42 PM PDT 24
Peak memory 207472 kb
Host smart-2f32acd0-5bc2-4180-b8a1-a9891e64271b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=477664276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.477664276
Directory /workspace/5.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_types.604279891
Short name T436
Test name
Test status
Simulation time 585974357 ps
CPU time 1.64 seconds
Started Aug 17 06:04:10 PM PDT 24
Finished Aug 17 06:04:11 PM PDT 24
Peak memory 207452 kb
Host smart-eb785a94-4ee5-4f04-8a93-afc23bdc942d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=604279891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.604279891
Directory /workspace/7.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/74.usbdev_endpoint_types.3560947276
Short name T395
Test name
Test status
Simulation time 918008722 ps
CPU time 2.05 seconds
Started Aug 17 06:11:13 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207576 kb
Host smart-e79f1635-1651-4a73-a3c4-7010632898b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3560947276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.3560947276
Directory /workspace/74.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/86.usbdev_tx_rx_disruption.46251033
Short name T74
Test name
Test status
Simulation time 575188082 ps
CPU time 1.54 seconds
Started Aug 17 06:11:19 PM PDT 24
Finished Aug 17 06:11:20 PM PDT 24
Peak memory 207568 kb
Host smart-1a3dc4d8-74c8-4ffe-837b-dad9d77f231a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46251033 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 86.usbdev_tx_rx_disruption.46251033
Directory /workspace/86.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/106.usbdev_endpoint_types.1443742094
Short name T424
Test name
Test status
Simulation time 564999169 ps
CPU time 1.61 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:44 PM PDT 24
Peak memory 207536 kb
Host smart-fcbfd585-e23f-4a43-a664-48038166f158
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1443742094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.1443742094
Directory /workspace/106.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_types.4132740092
Short name T450
Test name
Test status
Simulation time 533409923 ps
CPU time 1.5 seconds
Started Aug 17 06:05:28 PM PDT 24
Finished Aug 17 06:05:30 PM PDT 24
Peak memory 207520 kb
Host smart-34da52f1-1b1e-43d4-b0f3-450b2971c8b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4132740092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.4132740092
Directory /workspace/13.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2320859735
Short name T356
Test name
Test status
Simulation time 40039710 ps
CPU time 0.71 seconds
Started Aug 17 06:34:36 PM PDT 24
Finished Aug 17 06:34:37 PM PDT 24
Peak memory 206848 kb
Host smart-b1f12cd3-2d98-454a-934e-f211b92ee401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2320859735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2320859735
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/default/80.usbdev_endpoint_types.1418621784
Short name T127
Test name
Test status
Simulation time 842546562 ps
CPU time 2.03 seconds
Started Aug 17 06:11:19 PM PDT 24
Finished Aug 17 06:11:21 PM PDT 24
Peak memory 207520 kb
Host smart-0d390399-9d47-40cd-a17f-858ae2f6a3a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1418621784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.1418621784
Directory /workspace/80.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/101.usbdev_endpoint_types.3476232010
Short name T433
Test name
Test status
Simulation time 484730266 ps
CPU time 1.32 seconds
Started Aug 17 06:11:25 PM PDT 24
Finished Aug 17 06:11:27 PM PDT 24
Peak memory 207520 kb
Host smart-eab16d6f-b987-4e3c-802e-8fdf4d68880e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3476232010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.3476232010
Directory /workspace/101.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/140.usbdev_endpoint_types.3957555245
Short name T472
Test name
Test status
Simulation time 232111804 ps
CPU time 1.11 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:00 PM PDT 24
Peak memory 207516 kb
Host smart-ac2cd08f-4cdb-4c78-a728-7443ef31de09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3957555245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.3957555245
Directory /workspace/140.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.621653745
Short name T2202
Test name
Test status
Simulation time 1332607539 ps
CPU time 3.74 seconds
Started Aug 17 06:06:00 PM PDT 24
Finished Aug 17 06:06:04 PM PDT 24
Peak memory 207764 kb
Host smart-9497c302-b904-4d1b-9efd-c380984098fb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=621653745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.621653745
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/198.usbdev_endpoint_types.4283763667
Short name T417
Test name
Test status
Simulation time 607688617 ps
CPU time 1.62 seconds
Started Aug 17 06:12:00 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207388 kb
Host smart-71f0efe0-91a8-4f0f-89f7-710af551ecf9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4283763667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.4283763667
Directory /workspace/198.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_types.1928674298
Short name T117
Test name
Test status
Simulation time 599990742 ps
CPU time 1.49 seconds
Started Aug 17 06:10:45 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 207488 kb
Host smart-b2b9f539-3fcd-46fe-8ef3-8b7dc1e1bd02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1928674298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.1928674298
Directory /workspace/48.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.4057136729
Short name T49
Test name
Test status
Simulation time 418910355 ps
CPU time 1.48 seconds
Started Aug 17 06:02:36 PM PDT 24
Finished Aug 17 06:02:38 PM PDT 24
Peak memory 207516 kb
Host smart-a2a3d051-65cf-4cc2-afb8-06bf6781d9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40571
36729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.4057136729
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1968585030
Short name T230
Test name
Test status
Simulation time 763558179 ps
CPU time 4.9 seconds
Started Aug 17 06:34:24 PM PDT 24
Finished Aug 17 06:34:29 PM PDT 24
Peak memory 207240 kb
Host smart-3e2b4811-8f6e-4453-ae49-3556076e4bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1968585030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1968585030
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/147.usbdev_endpoint_types.173705705
Short name T408
Test name
Test status
Simulation time 690426850 ps
CPU time 1.57 seconds
Started Aug 17 06:11:52 PM PDT 24
Finished Aug 17 06:11:54 PM PDT 24
Peak memory 207520 kb
Host smart-4813303d-4082-407a-8baa-7b62a8834fec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=173705705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.173705705
Directory /workspace/147.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/116.usbdev_endpoint_types.1238466324
Short name T144
Test name
Test status
Simulation time 582773365 ps
CPU time 1.66 seconds
Started Aug 17 06:11:25 PM PDT 24
Finished Aug 17 06:11:32 PM PDT 24
Peak memory 207500 kb
Host smart-c8d93398-0a74-4014-afe1-c2900c7327c1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1238466324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.1238466324
Directory /workspace/116.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.4043476206
Short name T1002
Test name
Test status
Simulation time 29037768 ps
CPU time 0.67 seconds
Started Aug 17 06:05:09 PM PDT 24
Finished Aug 17 06:05:10 PM PDT 24
Peak memory 207412 kb
Host smart-373c6424-bd18-4d59-a153-6e1d5c6e4c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4043476206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.4043476206
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2627161059
Short name T177
Test name
Test status
Simulation time 7394024739 ps
CPU time 201.76 seconds
Started Aug 17 06:03:18 PM PDT 24
Finished Aug 17 06:06:40 PM PDT 24
Peak memory 215952 kb
Host smart-41da46ea-18f9-4874-98ed-1c95253f32a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2627161059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2627161059
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2390994106
Short name T129
Test name
Test status
Simulation time 3469191497 ps
CPU time 91.27 seconds
Started Aug 17 06:08:51 PM PDT 24
Finished Aug 17 06:10:22 PM PDT 24
Peak memory 224152 kb
Host smart-b0557117-76bd-450b-b33a-a33ca673de2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2390994106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2390994106
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/107.usbdev_endpoint_types.2016866733
Short name T503
Test name
Test status
Simulation time 684579885 ps
CPU time 1.75 seconds
Started Aug 17 06:11:43 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 207512 kb
Host smart-a59a0aa2-67f6-4cff-88a1-154ff27d65c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2016866733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.2016866733
Directory /workspace/107.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1272892065
Short name T710
Test name
Test status
Simulation time 168600739 ps
CPU time 0.91 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207536 kb
Host smart-e90b82fa-f496-4194-8c36-829588a9f849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
92065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1272892065
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/132.usbdev_endpoint_types.4122653001
Short name T473
Test name
Test status
Simulation time 333860952 ps
CPU time 1.19 seconds
Started Aug 17 06:11:34 PM PDT 24
Finished Aug 17 06:11:35 PM PDT 24
Peak memory 207528 kb
Host smart-bd294490-b929-458e-949e-d8399c56d7ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4122653001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.4122653001
Directory /workspace/132.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/150.usbdev_endpoint_types.3668718561
Short name T476
Test name
Test status
Simulation time 351354882 ps
CPU time 1.25 seconds
Started Aug 17 06:11:29 PM PDT 24
Finished Aug 17 06:11:30 PM PDT 24
Peak memory 207520 kb
Host smart-f0836ed4-3de7-4977-a22a-dee2a2f310ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3668718561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.3668718561
Directory /workspace/150.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/190.usbdev_endpoint_types.3222024266
Short name T413
Test name
Test status
Simulation time 584822133 ps
CPU time 1.53 seconds
Started Aug 17 06:12:05 PM PDT 24
Finished Aug 17 06:12:06 PM PDT 24
Peak memory 207504 kb
Host smart-139d385e-a209-4a73-9bb0-11ca809c15df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3222024266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.3222024266
Directory /workspace/190.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.1954753663
Short name T338
Test name
Test status
Simulation time 1035675105 ps
CPU time 2.65 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:42 PM PDT 24
Peak memory 207648 kb
Host smart-a2cead10-aac4-44c8-8f88-f65538940804
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1954753663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.1954753663
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2659866581
Short name T3658
Test name
Test status
Simulation time 259656240 ps
CPU time 3.46 seconds
Started Aug 17 06:34:33 PM PDT 24
Finished Aug 17 06:34:36 PM PDT 24
Peak memory 215388 kb
Host smart-af56b7fd-9871-4c23-9399-9168a99db19d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2659866581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2659866581
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/307.usbdev_tx_rx_disruption.3791815772
Short name T244
Test name
Test status
Simulation time 486901302 ps
CPU time 1.52 seconds
Started Aug 17 06:12:20 PM PDT 24
Finished Aug 17 06:12:21 PM PDT 24
Peak memory 207508 kb
Host smart-4634cbfc-af43-43a5-942a-2c91bc99ac43
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791815772 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 307.usbdev_tx_rx_disruption.3791815772
Directory /workspace/307.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1112062706
Short name T84
Test name
Test status
Simulation time 4345857235 ps
CPU time 31.26 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:04:09 PM PDT 24
Peak memory 218376 kb
Host smart-ebfcf5d7-0246-4f28-b982-7b74823e4913
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112062706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1112062706
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1290666981
Short name T163
Test name
Test status
Simulation time 228574078 ps
CPU time 1.03 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207472 kb
Host smart-c1428153-dc0a-4b56-bff2-b2757f57a81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12906
66981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1290666981
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4075934457
Short name T303
Test name
Test status
Simulation time 320859325 ps
CPU time 1.92 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:09 PM PDT 24
Peak memory 207156 kb
Host smart-6088601c-2691-47ba-85be-0e3c59861f03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4075934457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.4075934457
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3819930894
Short name T277
Test name
Test status
Simulation time 20668278849 ps
CPU time 53.62 seconds
Started Aug 17 06:06:31 PM PDT 24
Finished Aug 17 06:07:25 PM PDT 24
Peak memory 224124 kb
Host smart-919925c5-f5f2-4e52-b50e-5bf3019d5331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38199
30894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3819930894
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/170.usbdev_tx_rx_disruption.3340123988
Short name T166
Test name
Test status
Simulation time 551978421 ps
CPU time 1.75 seconds
Started Aug 17 06:11:40 PM PDT 24
Finished Aug 17 06:11:42 PM PDT 24
Peak memory 207496 kb
Host smart-d3bacf6b-e75f-42d8-9014-0684dfa97343
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340123988 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.usbdev_tx_rx_disruption.3340123988
Directory /workspace/170.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3339110009
Short name T96
Test name
Test status
Simulation time 139441284 ps
CPU time 0.84 seconds
Started Aug 17 06:02:15 PM PDT 24
Finished Aug 17 06:02:15 PM PDT 24
Peak memory 207452 kb
Host smart-516c42b2-ba68-48d1-b7af-71124cbf3ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33391
10009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3339110009
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.4068074740
Short name T351
Test name
Test status
Simulation time 5113753333 ps
CPU time 155.34 seconds
Started Aug 17 06:02:17 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 215996 kb
Host smart-d36a5529-d2eb-4a3f-8360-7c16ffe8ca9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40680
74740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.4068074740
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/1.usbdev_device_address.549884564
Short name T373
Test name
Test status
Simulation time 14968405349 ps
CPU time 22.82 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:03:06 PM PDT 24
Peak memory 207820 kb
Host smart-70ee0199-a7e1-4808-9258-348a06f830a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54988
4564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.549884564
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/112.usbdev_endpoint_types.2933812593
Short name T486
Test name
Test status
Simulation time 586759960 ps
CPU time 1.58 seconds
Started Aug 17 06:11:32 PM PDT 24
Finished Aug 17 06:11:34 PM PDT 24
Peak memory 207520 kb
Host smart-86e37698-a6cc-41f0-ae9d-c3b4246c8992
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2933812593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.2933812593
Directory /workspace/112.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/133.usbdev_endpoint_types.2073725467
Short name T444
Test name
Test status
Simulation time 592747142 ps
CPU time 1.68 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:44 PM PDT 24
Peak memory 207500 kb
Host smart-4ccdcdd7-4a39-4fd1-be85-2bb9b6c68847
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2073725467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.2073725467
Directory /workspace/133.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/148.usbdev_endpoint_types.2203674072
Short name T427
Test name
Test status
Simulation time 387850876 ps
CPU time 1.32 seconds
Started Aug 17 06:11:32 PM PDT 24
Finished Aug 17 06:11:34 PM PDT 24
Peak memory 207520 kb
Host smart-5b1555af-21aa-4b2d-9e17-d7e1e687c00b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2203674072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.2203674072
Directory /workspace/148.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/149.usbdev_endpoint_types.2848792337
Short name T524
Test name
Test status
Simulation time 329505016 ps
CPU time 1.18 seconds
Started Aug 17 06:11:36 PM PDT 24
Finished Aug 17 06:11:37 PM PDT 24
Peak memory 207532 kb
Host smart-71214b81-4cc6-4300-aa99-0bb6c69af68f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2848792337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.2848792337
Directory /workspace/149.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/160.usbdev_endpoint_types.782147771
Short name T475
Test name
Test status
Simulation time 541489681 ps
CPU time 1.54 seconds
Started Aug 17 06:11:58 PM PDT 24
Finished Aug 17 06:12:00 PM PDT 24
Peak memory 207436 kb
Host smart-77d8cdde-cb12-460a-911f-c5c75518a550
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=782147771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.782147771
Directory /workspace/160.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/182.usbdev_endpoint_types.1336235956
Short name T410
Test name
Test status
Simulation time 397093718 ps
CPU time 1.27 seconds
Started Aug 17 06:11:43 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 207532 kb
Host smart-190482a5-ea3f-4b77-88f3-ba51688a5b5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1336235956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.1336235956
Directory /workspace/182.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2478554691
Short name T132
Test name
Test status
Simulation time 45156959184 ps
CPU time 70.49 seconds
Started Aug 17 06:07:06 PM PDT 24
Finished Aug 17 06:08:16 PM PDT 24
Peak memory 207680 kb
Host smart-09deeb2d-0f9f-444c-849e-4451cc8a7a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24785
54691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2478554691
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/59.usbdev_endpoint_types.3106348867
Short name T440
Test name
Test status
Simulation time 330668093 ps
CPU time 1.14 seconds
Started Aug 17 06:11:09 PM PDT 24
Finished Aug 17 06:11:11 PM PDT 24
Peak memory 207384 kb
Host smart-e16d967e-950a-4564-ad34-e795de9985ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3106348867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.3106348867
Directory /workspace/59.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/87.usbdev_endpoint_types.748562463
Short name T3525
Test name
Test status
Simulation time 318561441 ps
CPU time 1.13 seconds
Started Aug 17 06:11:14 PM PDT 24
Finished Aug 17 06:11:16 PM PDT 24
Peak memory 207448 kb
Host smart-397eecfb-002c-4590-b49e-dbf9a1693372
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=748562463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.748562463
Directory /workspace/87.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.665640515
Short name T4
Test name
Test status
Simulation time 1779561364 ps
CPU time 53.3 seconds
Started Aug 17 06:02:36 PM PDT 24
Finished Aug 17 06:03:29 PM PDT 24
Peak memory 215840 kb
Host smart-0d95ad68-5748-4f43-a140-3cf44ada84a0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=665640515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.665640515
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3246131403
Short name T229
Test name
Test status
Simulation time 565846607 ps
CPU time 2.72 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 207240 kb
Host smart-0c3610ea-2897-4e61-9456-c328ab764e83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3246131403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3246131403
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1614284052
Short name T364
Test name
Test status
Simulation time 549445836 ps
CPU time 4.05 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 207224 kb
Host smart-7f58670a-51be-4c86-a2f7-1a1086be281d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1614284052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1614284052
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2297121184
Short name T3645
Test name
Test status
Simulation time 41606155 ps
CPU time 0.69 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 206876 kb
Host smart-9b5a4644-f129-41da-a2d5-f128ffc35d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2297121184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2297121184
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.73862914
Short name T362
Test name
Test status
Simulation time 1048613898 ps
CPU time 4.31 seconds
Started Aug 17 06:34:16 PM PDT 24
Finished Aug 17 06:34:20 PM PDT 24
Peak memory 207300 kb
Host smart-c5696cf4-a74b-4075-9a51-597acf52f2a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=73862914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.73862914
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3580499559
Short name T394
Test name
Test status
Simulation time 2757439650 ps
CPU time 30.11 seconds
Started Aug 17 06:02:22 PM PDT 24
Finished Aug 17 06:02:52 PM PDT 24
Peak memory 218756 kb
Host smart-2185f55f-f777-47df-962e-1eb8e36813a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3580499559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3580499559
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.915909768
Short name T2489
Test name
Test status
Simulation time 356376978 ps
CPU time 1.29 seconds
Started Aug 17 06:02:31 PM PDT 24
Finished Aug 17 06:02:32 PM PDT 24
Peak memory 207472 kb
Host smart-2950a3aa-1f52-4720-9f32-8b5c414c41cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91590
9768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.915909768
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2855000428
Short name T345
Test name
Test status
Simulation time 1218373455 ps
CPU time 3.35 seconds
Started Aug 17 06:02:35 PM PDT 24
Finished Aug 17 06:02:38 PM PDT 24
Peak memory 207744 kb
Host smart-c90f8deb-a66f-4c23-b1da-cabde1006fb4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2855000428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2855000428
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3787562132
Short name T24
Test name
Test status
Simulation time 150505938 ps
CPU time 0.87 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:44 PM PDT 24
Peak memory 207540 kb
Host smart-b9e1a1b3-8659-4f60-8860-d24b487872c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37875
62132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3787562132
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_types.4188325989
Short name T406
Test name
Test status
Simulation time 320431920 ps
CPU time 1.11 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:04:53 PM PDT 24
Peak memory 207472 kb
Host smart-13d64c93-585f-4c6b-9a34-82243bf1610a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4188325989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.4188325989
Directory /workspace/10.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3358106683
Short name T644
Test name
Test status
Simulation time 196765117 ps
CPU time 0.99 seconds
Started Aug 17 06:04:55 PM PDT 24
Finished Aug 17 06:04:56 PM PDT 24
Peak memory 207484 kb
Host smart-5e731a49-6b76-427e-af27-a0a96f9ddea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33581
06683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3358106683
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2513966286
Short name T16
Test name
Test status
Simulation time 165457571 ps
CPU time 0.89 seconds
Started Aug 17 06:05:19 PM PDT 24
Finished Aug 17 06:05:20 PM PDT 24
Peak memory 207500 kb
Host smart-db5de28d-b3fa-4f23-a5dc-56428105c957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25139
66286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2513966286
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/128.usbdev_endpoint_types.618916010
Short name T390
Test name
Test status
Simulation time 393073390 ps
CPU time 1.28 seconds
Started Aug 17 06:11:28 PM PDT 24
Finished Aug 17 06:11:29 PM PDT 24
Peak memory 207508 kb
Host smart-97f68af0-f607-4696-8a98-87c29cbf8a56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=618916010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.618916010
Directory /workspace/128.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/135.usbdev_endpoint_types.1436760402
Short name T392
Test name
Test status
Simulation time 491645002 ps
CPU time 1.41 seconds
Started Aug 17 06:11:48 PM PDT 24
Finished Aug 17 06:11:49 PM PDT 24
Peak memory 207448 kb
Host smart-99bbe45a-89f8-4d5f-bb42-99de7296fa47
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1436760402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.1436760402
Directory /workspace/135.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_endpoint_types.1979676126
Short name T404
Test name
Test status
Simulation time 496031013 ps
CPU time 1.49 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207448 kb
Host smart-cd5e04b5-ef38-442a-9ef3-7d536eb3f2d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1979676126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.1979676126
Directory /workspace/144.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/145.usbdev_endpoint_types.2872680217
Short name T95
Test name
Test status
Simulation time 422813907 ps
CPU time 1.29 seconds
Started Aug 17 06:11:36 PM PDT 24
Finished Aug 17 06:11:37 PM PDT 24
Peak memory 207520 kb
Host smart-f3442caf-e6ca-4ce7-ae9c-cfd846ad63a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2872680217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.2872680217
Directory /workspace/145.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_endpoint_types.742968692
Short name T439
Test name
Test status
Simulation time 272977146 ps
CPU time 1.1 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:43 PM PDT 24
Peak memory 207436 kb
Host smart-b6579b8d-1e46-4e39-910f-a29afabefcb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=742968692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.742968692
Directory /workspace/156.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2228315145
Short name T2376
Test name
Test status
Simulation time 14679283984 ps
CPU time 37.99 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 215872 kb
Host smart-911a1fd1-09be-4143-bfd3-3f6a48810ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283
15145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2228315145
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_types.2163356178
Short name T397
Test name
Test status
Simulation time 400019439 ps
CPU time 1.24 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:05 PM PDT 24
Peak memory 207536 kb
Host smart-4b5f414c-0ff7-452e-98ec-2926f919a8f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2163356178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.2163356178
Directory /workspace/28.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3419410491
Short name T349
Test name
Test status
Simulation time 110190590349 ps
CPU time 173.95 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:06:02 PM PDT 24
Peak memory 207784 kb
Host smart-a2957b5b-6d5c-40ff-8eb6-824b490d963a
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3419410491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3419410491
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_types.3400252694
Short name T490
Test name
Test status
Simulation time 384383396 ps
CPU time 1.23 seconds
Started Aug 17 06:04:22 PM PDT 24
Finished Aug 17 06:04:23 PM PDT 24
Peak memory 207540 kb
Host smart-92e0fb29-5b9f-46fd-9e2f-8cb42a3da28c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3400252694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.3400252694
Directory /workspace/8.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.327957108
Short name T605
Test name
Test status
Simulation time 140597922 ps
CPU time 0.82 seconds
Started Aug 17 06:02:25 PM PDT 24
Finished Aug 17 06:02:26 PM PDT 24
Peak memory 207340 kb
Host smart-c121bfa4-33ce-4ff7-b95a-e364b3f1ea6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32795
7108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.327957108
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1738140674
Short name T223
Test name
Test status
Simulation time 6425139593 ps
CPU time 8.95 seconds
Started Aug 17 06:02:15 PM PDT 24
Finished Aug 17 06:02:24 PM PDT 24
Peak memory 215968 kb
Host smart-f1bfcef3-25be-4e22-84e4-b771e805ea1e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738140674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.1738140674
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.233228151
Short name T94
Test name
Test status
Simulation time 199850008 ps
CPU time 0.9 seconds
Started Aug 17 06:02:34 PM PDT 24
Finished Aug 17 06:02:35 PM PDT 24
Peak memory 207436 kb
Host smart-087174d7-5985-46f3-8389-6593958b4f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23322
8151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.233228151
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1887755301
Short name T253
Test name
Test status
Simulation time 145477951 ps
CPU time 0.85 seconds
Started Aug 17 06:06:10 PM PDT 24
Finished Aug 17 06:06:11 PM PDT 24
Peak memory 207384 kb
Host smart-210a69c5-2bd8-44dc-9ab0-6d287ddd4f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18877
55301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1887755301
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1240746833
Short name T32
Test name
Test status
Simulation time 43776556 ps
CPU time 0.71 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207520 kb
Host smart-17a07d6a-b98f-4a77-85e4-c79438480c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12407
46833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1240746833
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.1213058099
Short name T3475
Test name
Test status
Simulation time 156945999 ps
CPU time 0.85 seconds
Started Aug 17 06:02:22 PM PDT 24
Finished Aug 17 06:02:23 PM PDT 24
Peak memory 207476 kb
Host smart-b0c151df-21f6-45f1-8482-7af05d9f7121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12130
58099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1213058099
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1123596812
Short name T61
Test name
Test status
Simulation time 4165376826 ps
CPU time 11.23 seconds
Started Aug 17 06:02:16 PM PDT 24
Finished Aug 17 06:02:27 PM PDT 24
Peak memory 207780 kb
Host smart-0b9b7697-f592-4757-8a2f-5c572aef5823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
96812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1123596812
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2672190880
Short name T67
Test name
Test status
Simulation time 516782897 ps
CPU time 1.67 seconds
Started Aug 17 06:02:15 PM PDT 24
Finished Aug 17 06:02:17 PM PDT 24
Peak memory 207500 kb
Host smart-2ef6913f-0349-4a6b-849b-e9dabd4508e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26721
90880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2672190880
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.3950844548
Short name T62
Test name
Test status
Simulation time 191790845 ps
CPU time 0.87 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:22 PM PDT 24
Peak memory 207400 kb
Host smart-9f833e53-aa50-4268-812b-14588d03bd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39508
44548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3950844548
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.354415368
Short name T2249
Test name
Test status
Simulation time 200236535 ps
CPU time 0.91 seconds
Started Aug 17 06:02:31 PM PDT 24
Finished Aug 17 06:02:32 PM PDT 24
Peak memory 207460 kb
Host smart-8f57fda8-1c43-4f63-b631-7b78676cad72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35441
5368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.354415368
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1722045766
Short name T43
Test name
Test status
Simulation time 194894862 ps
CPU time 0.91 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:02:52 PM PDT 24
Peak memory 207484 kb
Host smart-02ea757d-4840-4df5-9daa-e39eeb246950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17220
45766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1722045766
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.961083376
Short name T185
Test name
Test status
Simulation time 6239746036 ps
CPU time 34.94 seconds
Started Aug 17 06:03:15 PM PDT 24
Finished Aug 17 06:03:50 PM PDT 24
Peak memory 219944 kb
Host smart-c66fc34f-5ec0-493f-9f6a-ff70020b655d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=961083376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.961083376
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.470362408
Short name T1280
Test name
Test status
Simulation time 208108107 ps
CPU time 0.92 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:22 PM PDT 24
Peak memory 207468 kb
Host smart-2fc56807-1786-4735-b655-f3d6650cdf87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47036
2408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.470362408
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2114499961
Short name T82
Test name
Test status
Simulation time 7600815604 ps
CPU time 49.78 seconds
Started Aug 17 06:02:29 PM PDT 24
Finished Aug 17 06:03:18 PM PDT 24
Peak memory 219140 kb
Host smart-0bc6c339-6501-429d-aa94-00afaf531505
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114499961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2114499961
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1617673313
Short name T151
Test name
Test status
Simulation time 212708790 ps
CPU time 1 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:45 PM PDT 24
Peak memory 207460 kb
Host smart-a04cd4bd-d28d-420e-8a3f-9ec9d5a7c677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16176
73313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1617673313
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.1121527817
Short name T584
Test name
Test status
Simulation time 2106246871 ps
CPU time 60.76 seconds
Started Aug 17 06:04:49 PM PDT 24
Finished Aug 17 06:05:50 PM PDT 24
Peak memory 223992 kb
Host smart-22cb668f-504e-4e94-a5ec-82f1e63e46f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215
27817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.1121527817
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1660927067
Short name T159
Test name
Test status
Simulation time 176938738 ps
CPU time 1.02 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:04:58 PM PDT 24
Peak memory 207392 kb
Host smart-feedf09f-5749-46b8-b01b-c39aac37816f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16609
27067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1660927067
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1088584010
Short name T3127
Test name
Test status
Simulation time 195550443 ps
CPU time 0.9 seconds
Started Aug 17 06:05:12 PM PDT 24
Finished Aug 17 06:05:13 PM PDT 24
Peak memory 207464 kb
Host smart-9807f890-b169-4499-b5e4-206630fc83d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10885
84010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1088584010
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1117950379
Short name T91
Test name
Test status
Simulation time 435503785 ps
CPU time 3.07 seconds
Started Aug 17 06:05:14 PM PDT 24
Finished Aug 17 06:05:17 PM PDT 24
Peak memory 207636 kb
Host smart-3e13369e-fbdf-4010-9ca0-6ce41d264617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11179
50379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1117950379
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1408857517
Short name T148
Test name
Test status
Simulation time 173699272 ps
CPU time 0.92 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:14 PM PDT 24
Peak memory 207492 kb
Host smart-1f7d6858-84fb-4a84-bea4-5e62acece90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14088
57517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1408857517
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3366497700
Short name T137
Test name
Test status
Simulation time 207401471 ps
CPU time 0.96 seconds
Started Aug 17 06:06:26 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207408 kb
Host smart-046871be-24ac-49ba-b938-fd61c3faae40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33664
97700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3366497700
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/224.usbdev_tx_rx_disruption.2292631762
Short name T2799
Test name
Test status
Simulation time 480605973 ps
CPU time 1.44 seconds
Started Aug 17 06:11:54 PM PDT 24
Finished Aug 17 06:11:56 PM PDT 24
Peak memory 207544 kb
Host smart-3f70a0bf-3fbe-48ca-ae84-8da89df15149
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292631762 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.usbdev_tx_rx_disruption.2292631762
Directory /workspace/224.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2243822955
Short name T3490
Test name
Test status
Simulation time 259103982 ps
CPU time 1.02 seconds
Started Aug 17 06:07:21 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 207412 kb
Host smart-41f3da8c-7791-4168-9734-14a27b844fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22438
22955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2243822955
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1172774976
Short name T155
Test name
Test status
Simulation time 154902302 ps
CPU time 0.9 seconds
Started Aug 17 06:07:40 PM PDT 24
Finished Aug 17 06:07:41 PM PDT 24
Peak memory 207468 kb
Host smart-26d8527e-c050-4d95-b9c7-301ddd5bcc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11727
74976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1172774976
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1707874624
Short name T140
Test name
Test status
Simulation time 190946072 ps
CPU time 0.93 seconds
Started Aug 17 06:08:57 PM PDT 24
Finished Aug 17 06:08:58 PM PDT 24
Peak memory 207464 kb
Host smart-c055a112-c10e-478b-a56b-b1fcf040e906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17078
74624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1707874624
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3265296639
Short name T141
Test name
Test status
Simulation time 189782943 ps
CPU time 0.89 seconds
Started Aug 17 06:09:10 PM PDT 24
Finished Aug 17 06:09:11 PM PDT 24
Peak memory 207444 kb
Host smart-669787f5-340e-4726-827c-bec34d13e750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32652
96639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3265296639
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4231538561
Short name T289
Test name
Test status
Simulation time 403266976 ps
CPU time 3.68 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 207040 kb
Host smart-fd5d8af5-ea3b-4d12-890b-ea71cda4886b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4231538561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.4231538561
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1403974864
Short name T316
Test name
Test status
Simulation time 1475429301 ps
CPU time 5.25 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 207228 kb
Host smart-be367d9d-6a1e-4bad-ba4b-67eed8cda313
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1403974864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1403974864
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2383969791
Short name T236
Test name
Test status
Simulation time 117242656 ps
CPU time 0.91 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 206988 kb
Host smart-1a5a0ab5-5725-4b73-873f-237d0e2a2ae4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2383969791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2383969791
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3162940608
Short name T3650
Test name
Test status
Simulation time 214597132 ps
CPU time 1.89 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 218368 kb
Host smart-83bb7fb1-215b-4feb-8239-60f20b4311e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162940608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3162940608
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1325654431
Short name T3724
Test name
Test status
Simulation time 105454634 ps
CPU time 0.98 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 207036 kb
Host smart-e39e49e1-4dc5-401d-bc9d-04586be0ed49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1325654431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1325654431
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3395454505
Short name T3710
Test name
Test status
Simulation time 40088891 ps
CPU time 0.73 seconds
Started Aug 17 06:34:15 PM PDT 24
Finished Aug 17 06:34:16 PM PDT 24
Peak memory 206924 kb
Host smart-356c174b-4e0b-4aac-aa3b-edcf253abdb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3395454505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3395454505
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1354020566
Short name T3659
Test name
Test status
Simulation time 348444134 ps
CPU time 2.39 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 207096 kb
Host smart-7644e50f-415c-452e-b853-649bdd747445
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1354020566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1354020566
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3125613814
Short name T317
Test name
Test status
Simulation time 506516057 ps
CPU time 2.99 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 207288 kb
Host smart-9071175d-5a90-4c79-a48a-facdb9b3e5c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3125613814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3125613814
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.87564216
Short name T3679
Test name
Test status
Simulation time 193797004 ps
CPU time 2.08 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 207164 kb
Host smart-b4a57733-57f9-41b9-b98b-af683e0ce13e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=87564216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.87564216
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3522773535
Short name T3715
Test name
Test status
Simulation time 698045188 ps
CPU time 8.38 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 207208 kb
Host smart-6615e114-755e-4f88-bc85-69f00f026183
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3522773535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3522773535
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.326928234
Short name T296
Test name
Test status
Simulation time 55722310 ps
CPU time 0.77 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 206812 kb
Host smart-6a82608c-89d9-49b8-8c97-4b607eb87e40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=326928234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.326928234
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2305819561
Short name T255
Test name
Test status
Simulation time 87531723 ps
CPU time 2.13 seconds
Started Aug 17 06:34:16 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 215532 kb
Host smart-05ae9588-436b-4e91-b6c2-d10589de50d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305819561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2305819561
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4021928113
Short name T3700
Test name
Test status
Simulation time 91532967 ps
CPU time 1.05 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 206852 kb
Host smart-78caeb6f-1581-41fb-8a38-90a8cb8fd0e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4021928113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4021928113
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2376681684
Short name T3738
Test name
Test status
Simulation time 71782161 ps
CPU time 0.79 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 206948 kb
Host smart-e7ed017c-dee0-4dfe-a3bf-f6e157782251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2376681684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2376681684
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1646414740
Short name T291
Test name
Test status
Simulation time 115255582 ps
CPU time 1.48 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 207168 kb
Host smart-88c238f1-3891-43c5-9ada-6b40076bb774
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1646414740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1646414740
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2535960768
Short name T3662
Test name
Test status
Simulation time 168441435 ps
CPU time 4.01 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 207016 kb
Host smart-3e59e7cb-9172-4459-9ace-b40c9434e8e4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2535960768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2535960768
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4001138413
Short name T300
Test name
Test status
Simulation time 170931434 ps
CPU time 1.25 seconds
Started Aug 17 06:34:46 PM PDT 24
Finished Aug 17 06:34:48 PM PDT 24
Peak memory 207040 kb
Host smart-509f115f-3190-4ffd-894d-88ae5c233e90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4001138413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.4001138413
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1548491979
Short name T3727
Test name
Test status
Simulation time 292451217 ps
CPU time 3.11 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 223360 kb
Host smart-effefbf9-37f2-4aa7-8d25-7a589eeea03f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1548491979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1548491979
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1427299136
Short name T3676
Test name
Test status
Simulation time 109592282 ps
CPU time 1.2 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 217408 kb
Host smart-69824a19-5d34-4d74-83bb-ceea6484c463
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427299136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1427299136
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3730821070
Short name T3640
Test name
Test status
Simulation time 70236069 ps
CPU time 1.05 seconds
Started Aug 17 06:34:34 PM PDT 24
Finished Aug 17 06:34:36 PM PDT 24
Peak memory 206964 kb
Host smart-cf3d6ba5-32dc-4226-a46e-607edc20eb96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3730821070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3730821070
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2774981966
Short name T3652
Test name
Test status
Simulation time 137837641 ps
CPU time 1.59 seconds
Started Aug 17 06:34:15 PM PDT 24
Finished Aug 17 06:34:16 PM PDT 24
Peak memory 207272 kb
Host smart-902bfdba-1483-4467-972b-3e7618ffb5cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2774981966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2774981966
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1042199564
Short name T3677
Test name
Test status
Simulation time 228879889 ps
CPU time 2.85 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:16 PM PDT 24
Peak memory 207168 kb
Host smart-c9b8450e-5c95-4c39-b57f-f79955d4af4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1042199564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1042199564
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1477278412
Short name T3704
Test name
Test status
Simulation time 495934767 ps
CPU time 2.64 seconds
Started Aug 17 06:34:32 PM PDT 24
Finished Aug 17 06:34:35 PM PDT 24
Peak memory 207292 kb
Host smart-d03b0f3d-677a-4833-8643-2371b24730c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1477278412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1477278412
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2601208768
Short name T3672
Test name
Test status
Simulation time 77182230 ps
CPU time 1.35 seconds
Started Aug 17 06:34:40 PM PDT 24
Finished Aug 17 06:34:42 PM PDT 24
Peak memory 215564 kb
Host smart-f7a51bca-7616-4dd8-a785-1d7b189c5b4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601208768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2601208768
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3790681407
Short name T3653
Test name
Test status
Simulation time 94641247 ps
CPU time 0.87 seconds
Started Aug 17 06:34:26 PM PDT 24
Finished Aug 17 06:34:27 PM PDT 24
Peak memory 206876 kb
Host smart-f6181ac2-0099-41c1-bf93-04e3ab6647f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3790681407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3790681407
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1356033230
Short name T302
Test name
Test status
Simulation time 173155846 ps
CPU time 1.64 seconds
Started Aug 17 06:34:26 PM PDT 24
Finished Aug 17 06:34:27 PM PDT 24
Peak memory 207240 kb
Host smart-232474b8-8404-4590-a8ab-d681b1e73473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1356033230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1356033230
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3841623993
Short name T258
Test name
Test status
Simulation time 97897980 ps
CPU time 1.44 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 207280 kb
Host smart-553c882a-8c8e-431a-a7dc-2dd8dc76f240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3841623993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3841623993
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3401699206
Short name T3687
Test name
Test status
Simulation time 1134561201 ps
CPU time 4.83 seconds
Started Aug 17 06:34:18 PM PDT 24
Finished Aug 17 06:34:23 PM PDT 24
Peak memory 207208 kb
Host smart-3992c20b-3124-4fea-afa4-61d460952f55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3401699206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3401699206
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4073943850
Short name T3661
Test name
Test status
Simulation time 160559813 ps
CPU time 1.97 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215540 kb
Host smart-8037694a-cd9c-4393-97ab-0b2534bd39b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073943850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.4073943850
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3566215026
Short name T281
Test name
Test status
Simulation time 78918802 ps
CPU time 0.89 seconds
Started Aug 17 06:34:27 PM PDT 24
Finished Aug 17 06:34:28 PM PDT 24
Peak memory 206980 kb
Host smart-be9d8165-a022-4914-bb50-974fead2b50c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3566215026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3566215026
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3402652028
Short name T3664
Test name
Test status
Simulation time 55109939 ps
CPU time 0.74 seconds
Started Aug 17 06:34:27 PM PDT 24
Finished Aug 17 06:34:28 PM PDT 24
Peak memory 206784 kb
Host smart-7a7c9d5c-bff0-4784-822d-8deaaa7205a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3402652028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3402652028
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3932707860
Short name T3729
Test name
Test status
Simulation time 197295789 ps
CPU time 1.55 seconds
Started Aug 17 06:34:25 PM PDT 24
Finished Aug 17 06:34:26 PM PDT 24
Peak memory 207176 kb
Host smart-bdea3f64-1867-411e-b2ee-7c29955f5de9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3932707860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3932707860
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1760630924
Short name T262
Test name
Test status
Simulation time 100333763 ps
CPU time 2.41 seconds
Started Aug 17 06:34:22 PM PDT 24
Finished Aug 17 06:34:25 PM PDT 24
Peak memory 223288 kb
Host smart-d8ea88a4-b3ff-4ba1-93f8-d562b1ccfb5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1760630924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1760630924
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3577427489
Short name T3681
Test name
Test status
Simulation time 1005233216 ps
CPU time 5.24 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 207228 kb
Host smart-3da5f2b2-e0e7-43d4-9a8d-9f1ea9d1dd09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3577427489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3577427489
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2861199072
Short name T264
Test name
Test status
Simulation time 78383802 ps
CPU time 1.27 seconds
Started Aug 17 06:34:40 PM PDT 24
Finished Aug 17 06:34:41 PM PDT 24
Peak memory 215452 kb
Host smart-bf3aa185-35e2-45ae-b6f3-f869fcf08614
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861199072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2861199072
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3159941267
Short name T295
Test name
Test status
Simulation time 51429592 ps
CPU time 0.99 seconds
Started Aug 17 06:34:20 PM PDT 24
Finished Aug 17 06:34:21 PM PDT 24
Peak memory 206976 kb
Host smart-1d96273d-4518-47d3-8747-f4a7102e5825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3159941267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3159941267
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2516261872
Short name T3685
Test name
Test status
Simulation time 74689910 ps
CPU time 0.74 seconds
Started Aug 17 06:34:15 PM PDT 24
Finished Aug 17 06:34:16 PM PDT 24
Peak memory 206904 kb
Host smart-33732900-e11a-416f-8241-e42f35e1bac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2516261872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2516261872
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2490048122
Short name T248
Test name
Test status
Simulation time 102547641 ps
CPU time 1.01 seconds
Started Aug 17 06:34:17 PM PDT 24
Finished Aug 17 06:34:19 PM PDT 24
Peak memory 207036 kb
Host smart-9e4ccf13-25b4-4a1c-a485-be6f423a0ac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2490048122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2490048122
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3194175363
Short name T3694
Test name
Test status
Simulation time 164563260 ps
CPU time 2.04 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215356 kb
Host smart-1f4d8909-d1dd-4da2-8b69-f58f967514b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3194175363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3194175363
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.573130005
Short name T3668
Test name
Test status
Simulation time 422272629 ps
CPU time 2.77 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 207292 kb
Host smart-25c54716-1454-4980-a2e0-9d43e6bb353f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=573130005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.573130005
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2383442929
Short name T322
Test name
Test status
Simulation time 94406464 ps
CPU time 1.36 seconds
Started Aug 17 06:34:36 PM PDT 24
Finished Aug 17 06:34:37 PM PDT 24
Peak memory 215528 kb
Host smart-73e866c8-383b-4481-9bd7-a3c0e2ef097b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383442929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2383442929
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3396419519
Short name T3730
Test name
Test status
Simulation time 69897213 ps
CPU time 1.05 seconds
Started Aug 17 06:34:14 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 207008 kb
Host smart-2d9bc4f6-259e-4c60-896f-b3d3d6106c29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3396419519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3396419519
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2646846518
Short name T360
Test name
Test status
Simulation time 35049829 ps
CPU time 0.72 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:21 PM PDT 24
Peak memory 206908 kb
Host smart-2f222add-1642-4a2f-8229-421a0d6b2d48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2646846518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2646846518
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.928994168
Short name T3695
Test name
Test status
Simulation time 117085362 ps
CPU time 1.04 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 207236 kb
Host smart-0f56a10a-3e64-45de-8948-88df49360c53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=928994168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.928994168
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1717347402
Short name T259
Test name
Test status
Simulation time 72017352 ps
CPU time 2.09 seconds
Started Aug 17 06:34:32 PM PDT 24
Finished Aug 17 06:34:34 PM PDT 24
Peak memory 215388 kb
Host smart-2e26be1f-04d9-43fc-964a-fd42223a4cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1717347402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1717347402
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2980675853
Short name T3696
Test name
Test status
Simulation time 94269967 ps
CPU time 1.19 seconds
Started Aug 17 06:34:34 PM PDT 24
Finished Aug 17 06:34:36 PM PDT 24
Peak memory 215236 kb
Host smart-9bfc6b90-fe51-4f40-bef9-ce841719e0ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980675853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2980675853
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2871848347
Short name T290
Test name
Test status
Simulation time 60795861 ps
CPU time 0.94 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:51 PM PDT 24
Peak memory 206856 kb
Host smart-c057bfbf-67b3-4836-bdbf-c50a7542cd67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2871848347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2871848347
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1389181161
Short name T301
Test name
Test status
Simulation time 204095209 ps
CPU time 1.56 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 207200 kb
Host smart-ac44c94f-4354-42de-b3a1-9807d05e5ada
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1389181161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1389181161
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2371422901
Short name T3736
Test name
Test status
Simulation time 362656898 ps
CPU time 4.06 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 221144 kb
Host smart-0031dfbd-002c-428f-9e9a-4f57566a34b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2371422901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2371422901
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.737958660
Short name T3692
Test name
Test status
Simulation time 516205404 ps
CPU time 2.75 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 207272 kb
Host smart-7a3cb90a-3d01-4ff6-b16b-9a6dbb81dc57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=737958660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.737958660
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.47329045
Short name T3723
Test name
Test status
Simulation time 104230111 ps
CPU time 2.61 seconds
Started Aug 17 06:34:19 PM PDT 24
Finished Aug 17 06:34:21 PM PDT 24
Peak memory 215448 kb
Host smart-7e07b860-26f8-4dcc-aee8-a432e5c4e7ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47329045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev
_csr_mem_rw_with_rand_reset.47329045
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.438719322
Short name T298
Test name
Test status
Simulation time 61057516 ps
CPU time 1.02 seconds
Started Aug 17 06:34:20 PM PDT 24
Finished Aug 17 06:34:21 PM PDT 24
Peak memory 206972 kb
Host smart-1431f104-acbd-41b3-872c-ebbd750ea9fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=438719322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.438719322
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1831128473
Short name T234
Test name
Test status
Simulation time 32241035 ps
CPU time 0.67 seconds
Started Aug 17 06:34:18 PM PDT 24
Finished Aug 17 06:34:24 PM PDT 24
Peak memory 206840 kb
Host smart-7dee4fda-9563-4313-ac4b-c9f8abdd78ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1831128473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1831128473
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3715275798
Short name T3678
Test name
Test status
Simulation time 60316491 ps
CPU time 1.08 seconds
Started Aug 17 06:34:19 PM PDT 24
Finished Aug 17 06:34:20 PM PDT 24
Peak memory 207236 kb
Host smart-9ea226bd-651f-4f01-92ce-ea5d07669571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3715275798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3715275798
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1223195828
Short name T3688
Test name
Test status
Simulation time 149332612 ps
CPU time 2.92 seconds
Started Aug 17 06:34:16 PM PDT 24
Finished Aug 17 06:34:19 PM PDT 24
Peak memory 220948 kb
Host smart-7870f961-0886-4967-9784-53ea3b850e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1223195828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1223195828
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.412842010
Short name T368
Test name
Test status
Simulation time 1815571060 ps
CPU time 4.84 seconds
Started Aug 17 06:34:36 PM PDT 24
Finished Aug 17 06:34:41 PM PDT 24
Peak memory 207236 kb
Host smart-bcf4e47d-8045-47ef-b3a5-4b62b9eb965b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=412842010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.412842010
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1210228270
Short name T3726
Test name
Test status
Simulation time 89072235 ps
CPU time 1.31 seconds
Started Aug 17 06:34:31 PM PDT 24
Finished Aug 17 06:34:33 PM PDT 24
Peak memory 215524 kb
Host smart-6a8ecfef-ef61-46c3-98a9-ba328cf65ecf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210228270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1210228270
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1247819634
Short name T285
Test name
Test status
Simulation time 54381629 ps
CPU time 0.92 seconds
Started Aug 17 06:34:18 PM PDT 24
Finished Aug 17 06:34:19 PM PDT 24
Peak memory 206968 kb
Host smart-4932f336-d353-4a40-83a8-01da3eb265af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1247819634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1247819634
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4037209366
Short name T3702
Test name
Test status
Simulation time 54611925 ps
CPU time 0.71 seconds
Started Aug 17 06:34:17 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 206888 kb
Host smart-0be8d8f9-a8b0-4772-842a-c331751f3323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4037209366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.4037209366
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2091969245
Short name T3733
Test name
Test status
Simulation time 152795811 ps
CPU time 1.48 seconds
Started Aug 17 06:34:15 PM PDT 24
Finished Aug 17 06:34:17 PM PDT 24
Peak memory 207252 kb
Host smart-9457a4d7-d030-463a-8bc3-62077a2a7c54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2091969245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2091969245
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.743511718
Short name T3663
Test name
Test status
Simulation time 94995033 ps
CPU time 2.41 seconds
Started Aug 17 06:34:17 PM PDT 24
Finished Aug 17 06:34:19 PM PDT 24
Peak memory 222992 kb
Host smart-3f9ee9b2-4ecb-4189-9ebb-bd04742541d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=743511718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.743511718
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1963386312
Short name T3657
Test name
Test status
Simulation time 712763051 ps
CPU time 2.95 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:45 PM PDT 24
Peak memory 207120 kb
Host smart-0342ef3a-ece4-4b2f-ac04-d42373db53dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1963386312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1963386312
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2424874800
Short name T3675
Test name
Test status
Simulation time 87643516 ps
CPU time 2.53 seconds
Started Aug 17 06:34:37 PM PDT 24
Finished Aug 17 06:34:40 PM PDT 24
Peak memory 215420 kb
Host smart-a63ea8df-0e60-42f0-b819-15ab65bf5cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424874800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2424874800
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1388168593
Short name T292
Test name
Test status
Simulation time 85978703 ps
CPU time 1.03 seconds
Started Aug 17 06:34:28 PM PDT 24
Finished Aug 17 06:34:29 PM PDT 24
Peak memory 207004 kb
Host smart-8928afaf-71ef-44bc-9271-0f4dc6030b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1388168593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1388168593
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1571907751
Short name T235
Test name
Test status
Simulation time 38895940 ps
CPU time 0.71 seconds
Started Aug 17 06:34:36 PM PDT 24
Finished Aug 17 06:34:37 PM PDT 24
Peak memory 206788 kb
Host smart-341ca01b-db8d-40fe-b410-59eb5f194544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1571907751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1571907751
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3384271986
Short name T318
Test name
Test status
Simulation time 170113145 ps
CPU time 1.35 seconds
Started Aug 17 06:34:45 PM PDT 24
Finished Aug 17 06:34:47 PM PDT 24
Peak memory 207176 kb
Host smart-98c74283-ba9d-4df2-9bb1-5b274607a05a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3384271986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3384271986
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1509485879
Short name T3713
Test name
Test status
Simulation time 96520236 ps
CPU time 1.25 seconds
Started Aug 17 06:34:39 PM PDT 24
Finished Aug 17 06:34:40 PM PDT 24
Peak memory 215268 kb
Host smart-ce9a19ef-aa88-443d-b596-8fcc7cd88fbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509485879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1509485879
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1912143174
Short name T284
Test name
Test status
Simulation time 56386030 ps
CPU time 0.97 seconds
Started Aug 17 06:34:19 PM PDT 24
Finished Aug 17 06:34:20 PM PDT 24
Peak memory 206900 kb
Host smart-75579cd9-85ce-4633-b649-c3c7a3f04d01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1912143174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1912143174
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.805605749
Short name T3722
Test name
Test status
Simulation time 67517265 ps
CPU time 0.72 seconds
Started Aug 17 06:34:43 PM PDT 24
Finished Aug 17 06:34:44 PM PDT 24
Peak memory 206920 kb
Host smart-008b3e3c-61cf-42de-90cb-c6f0e038e090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=805605749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.805605749
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2302118492
Short name T3648
Test name
Test status
Simulation time 186507587 ps
CPU time 1.61 seconds
Started Aug 17 06:34:40 PM PDT 24
Finished Aug 17 06:34:42 PM PDT 24
Peak memory 207204 kb
Host smart-2f25020c-78cf-47fe-8564-18f2446fb933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2302118492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2302118492
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2312589936
Short name T261
Test name
Test status
Simulation time 144996151 ps
CPU time 1.91 seconds
Started Aug 17 06:34:20 PM PDT 24
Finished Aug 17 06:34:22 PM PDT 24
Peak memory 207272 kb
Host smart-d1c1ea03-ba84-4952-8bec-c7addbee87e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2312589936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2312589936
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3163549988
Short name T365
Test name
Test status
Simulation time 424382789 ps
CPU time 3.01 seconds
Started Aug 17 06:34:18 PM PDT 24
Finished Aug 17 06:34:21 PM PDT 24
Peak memory 207172 kb
Host smart-06ee1ea3-a829-4636-8168-b95a0427865a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3163549988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3163549988
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2730825016
Short name T3697
Test name
Test status
Simulation time 294532237 ps
CPU time 3.89 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 207116 kb
Host smart-910f01a7-7292-41ad-ac4d-66ab257f2398
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2730825016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2730825016
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.729823571
Short name T3691
Test name
Test status
Simulation time 1327903681 ps
CPU time 5.49 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 207168 kb
Host smart-1d68c3f1-96a6-4033-adb8-bf8a9ae4b296
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=729823571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.729823571
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1610331101
Short name T321
Test name
Test status
Simulation time 111903086 ps
CPU time 0.97 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:19 PM PDT 24
Peak memory 207012 kb
Host smart-dda53835-f68e-4165-b0ee-8a19c86bc4e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1610331101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1610331101
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2532030130
Short name T3737
Test name
Test status
Simulation time 69696442 ps
CPU time 1.61 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 215420 kb
Host smart-b5fba0fb-0a1d-4e34-811c-04787b3fc443
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532030130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2532030130
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3084512998
Short name T283
Test name
Test status
Simulation time 72876986 ps
CPU time 0.95 seconds
Started Aug 17 06:34:16 PM PDT 24
Finished Aug 17 06:34:17 PM PDT 24
Peak memory 206928 kb
Host smart-997b7673-431e-4ccf-a2f4-259d925c588d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3084512998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3084512998
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3495583748
Short name T3669
Test name
Test status
Simulation time 43179492 ps
CPU time 0.71 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 206864 kb
Host smart-49bd9127-1e2e-44bf-bb64-7f0dffb14cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3495583748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3495583748
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.932951795
Short name T294
Test name
Test status
Simulation time 75377208 ps
CPU time 2.09 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215408 kb
Host smart-80e016b3-2fac-4ade-a6f2-4dc0967e681d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=932951795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.932951795
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1488053398
Short name T3643
Test name
Test status
Simulation time 480955980 ps
CPU time 4.07 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 207052 kb
Host smart-ede73183-5ca3-4c56-8605-e111217d595c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1488053398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1488053398
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2956849633
Short name T307
Test name
Test status
Simulation time 110172925 ps
CPU time 1.55 seconds
Started Aug 17 06:34:19 PM PDT 24
Finished Aug 17 06:34:21 PM PDT 24
Peak memory 207272 kb
Host smart-616d272b-d408-479e-ae68-f4d3fbf66f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2956849633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2956849633
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1379580214
Short name T247
Test name
Test status
Simulation time 141052911 ps
CPU time 1.66 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 207260 kb
Host smart-bec4bb6f-33f9-4bc8-bfff-275e0908e4a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1379580214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1379580214
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3218253812
Short name T363
Test name
Test status
Simulation time 513301001 ps
CPU time 4.39 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 207296 kb
Host smart-4c770e4f-d783-4e3b-9426-e885cd18888d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3218253812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3218253812
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1631645966
Short name T358
Test name
Test status
Simulation time 40918318 ps
CPU time 0.75 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:50 PM PDT 24
Peak memory 206852 kb
Host smart-03c4a721-eb0b-4ed0-b506-4c7447315645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1631645966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1631645966
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2181642874
Short name T3683
Test name
Test status
Simulation time 96453059 ps
CPU time 0.78 seconds
Started Aug 17 06:34:19 PM PDT 24
Finished Aug 17 06:34:19 PM PDT 24
Peak memory 206844 kb
Host smart-8fe1858d-d93f-434b-878d-7918216f967a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2181642874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2181642874
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.548446518
Short name T238
Test name
Test status
Simulation time 44091986 ps
CPU time 0.69 seconds
Started Aug 17 06:34:17 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 206872 kb
Host smart-0b98f533-ce66-49ff-aae0-c15cc7e6471e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=548446518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.548446518
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1776296661
Short name T3665
Test name
Test status
Simulation time 42828584 ps
CPU time 0.75 seconds
Started Aug 17 06:34:18 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 206896 kb
Host smart-df87d9d9-806c-4737-a46f-7cb9eeefd4e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1776296661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1776296661
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3755850673
Short name T3686
Test name
Test status
Simulation time 55985019 ps
CPU time 0.75 seconds
Started Aug 17 06:34:32 PM PDT 24
Finished Aug 17 06:34:33 PM PDT 24
Peak memory 206884 kb
Host smart-686f857c-e516-4019-a5d9-1b70e51c4b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3755850673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3755850673
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4108463993
Short name T357
Test name
Test status
Simulation time 34800692 ps
CPU time 0.71 seconds
Started Aug 17 06:34:27 PM PDT 24
Finished Aug 17 06:34:27 PM PDT 24
Peak memory 206884 kb
Host smart-1dbfb9fe-c452-4e29-9d2e-525238405450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4108463993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4108463993
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.229068661
Short name T3660
Test name
Test status
Simulation time 91011551 ps
CPU time 0.76 seconds
Started Aug 17 06:34:40 PM PDT 24
Finished Aug 17 06:34:40 PM PDT 24
Peak memory 206780 kb
Host smart-de64b478-f002-4851-b5a8-aeee9322de20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=229068661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.229068661
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.110674125
Short name T359
Test name
Test status
Simulation time 55869695 ps
CPU time 0.7 seconds
Started Aug 17 06:34:28 PM PDT 24
Finished Aug 17 06:34:29 PM PDT 24
Peak memory 206928 kb
Host smart-66cc86e8-ceed-481e-9e84-1b11dbcdd961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=110674125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.110674125
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3727425245
Short name T3651
Test name
Test status
Simulation time 37060030 ps
CPU time 0.74 seconds
Started Aug 17 06:34:46 PM PDT 24
Finished Aug 17 06:34:47 PM PDT 24
Peak memory 206908 kb
Host smart-99e705b7-2ba8-4b84-a123-624fb71f5011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3727425245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3727425245
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.733985407
Short name T3670
Test name
Test status
Simulation time 44010425 ps
CPU time 0.7 seconds
Started Aug 17 06:34:22 PM PDT 24
Finished Aug 17 06:34:23 PM PDT 24
Peak memory 206876 kb
Host smart-8ac63b88-170b-4a66-a7ea-78a8e8cb8ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=733985407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.733985407
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.527896108
Short name T3705
Test name
Test status
Simulation time 367368099 ps
CPU time 3.44 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:21 PM PDT 24
Peak memory 207108 kb
Host smart-f68f11ad-e410-4321-9743-3eda7b93c3a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=527896108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.527896108
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1434725703
Short name T288
Test name
Test status
Simulation time 984026634 ps
CPU time 9.13 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:22 PM PDT 24
Peak memory 207228 kb
Host smart-9c9fcecb-d788-4117-bc22-4b74ca63d354
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1434725703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1434725703
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2652058912
Short name T3639
Test name
Test status
Simulation time 99402483 ps
CPU time 0.92 seconds
Started Aug 17 06:34:14 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 206812 kb
Host smart-e839478e-538a-4628-a1a4-fc5bebee2efb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2652058912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2652058912
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2382234353
Short name T3641
Test name
Test status
Simulation time 194367890 ps
CPU time 1.85 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 223648 kb
Host smart-ba7ca802-fc9a-4e33-91eb-952236581ca4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382234353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2382234353
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.623112182
Short name T3731
Test name
Test status
Simulation time 44173550 ps
CPU time 0.96 seconds
Started Aug 17 06:34:17 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 206896 kb
Host smart-54999da7-b254-4039-8569-d3f518fcbf08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=623112182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.623112182
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1079643646
Short name T282
Test name
Test status
Simulation time 84536943 ps
CPU time 2.16 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215404 kb
Host smart-f1cfd584-8a2b-4515-b04d-0fe59991f516
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1079643646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1079643646
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1729876489
Short name T3718
Test name
Test status
Simulation time 625960795 ps
CPU time 4.37 seconds
Started Aug 17 06:34:24 PM PDT 24
Finished Aug 17 06:34:29 PM PDT 24
Peak memory 207068 kb
Host smart-32fa0191-75d7-4dc1-8732-5d7ca3c4a31b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1729876489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1729876489
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1937621208
Short name T306
Test name
Test status
Simulation time 161442037 ps
CPU time 1.49 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:44 PM PDT 24
Peak memory 207220 kb
Host smart-d9166d33-ff71-4ad9-806f-f294a2b96aed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1937621208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1937621208
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1945059548
Short name T3728
Test name
Test status
Simulation time 94676979 ps
CPU time 2.77 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:45 PM PDT 24
Peak memory 223284 kb
Host smart-37912b12-0995-483a-aced-d21fd253a33a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1945059548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1945059548
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1920690540
Short name T3712
Test name
Test status
Simulation time 758365007 ps
CPU time 4.81 seconds
Started Aug 17 06:34:36 PM PDT 24
Finished Aug 17 06:34:41 PM PDT 24
Peak memory 207232 kb
Host smart-0ab048d5-9e61-46bb-bba9-1c71c959e780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1920690540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1920690540
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1462582387
Short name T3698
Test name
Test status
Simulation time 65416568 ps
CPU time 0.75 seconds
Started Aug 17 06:34:25 PM PDT 24
Finished Aug 17 06:34:26 PM PDT 24
Peak memory 206920 kb
Host smart-8cbb409e-ad37-43ae-bb2c-f76e4ce6f070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1462582387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1462582387
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.937264983
Short name T3655
Test name
Test status
Simulation time 88720179 ps
CPU time 0.79 seconds
Started Aug 17 06:34:22 PM PDT 24
Finished Aug 17 06:34:23 PM PDT 24
Peak memory 206924 kb
Host smart-766c8413-1aef-472c-87c1-3ae3fefe69af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=937264983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.937264983
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3576072017
Short name T3699
Test name
Test status
Simulation time 45506907 ps
CPU time 0.78 seconds
Started Aug 17 06:34:49 PM PDT 24
Finished Aug 17 06:34:49 PM PDT 24
Peak memory 206928 kb
Host smart-bdb8e6cd-9bfa-4f73-be5d-cdf9790c3bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3576072017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3576072017
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.235875840
Short name T325
Test name
Test status
Simulation time 52532083 ps
CPU time 0.74 seconds
Started Aug 17 06:34:46 PM PDT 24
Finished Aug 17 06:34:46 PM PDT 24
Peak memory 206872 kb
Host smart-6b207fa7-c3d8-4594-8dac-2bb884fbd650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=235875840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.235875840
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1953738294
Short name T3649
Test name
Test status
Simulation time 73342627 ps
CPU time 0.71 seconds
Started Aug 17 06:34:47 PM PDT 24
Finished Aug 17 06:34:48 PM PDT 24
Peak memory 206888 kb
Host smart-bb860aa2-e68c-4c4e-97ad-363fe63c8545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1953738294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1953738294
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2543803105
Short name T3647
Test name
Test status
Simulation time 45837765 ps
CPU time 0.71 seconds
Started Aug 17 06:34:48 PM PDT 24
Finished Aug 17 06:34:49 PM PDT 24
Peak memory 206892 kb
Host smart-069d17e1-1a6d-4b6a-99fc-d5c335bb3f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2543803105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2543803105
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2669354183
Short name T3732
Test name
Test status
Simulation time 68636782 ps
CPU time 0.74 seconds
Started Aug 17 06:34:47 PM PDT 24
Finished Aug 17 06:34:48 PM PDT 24
Peak memory 206780 kb
Host smart-88e9b813-ef02-4c82-8004-1194669e3b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2669354183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2669354183
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4281751629
Short name T3673
Test name
Test status
Simulation time 47798332 ps
CPU time 0.72 seconds
Started Aug 17 06:34:48 PM PDT 24
Finished Aug 17 06:34:48 PM PDT 24
Peak memory 206876 kb
Host smart-bd135879-f077-42b7-88ec-d7807ce3cf3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4281751629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.4281751629
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4123574814
Short name T3739
Test name
Test status
Simulation time 68587845 ps
CPU time 0.72 seconds
Started Aug 17 06:34:38 PM PDT 24
Finished Aug 17 06:34:39 PM PDT 24
Peak memory 206884 kb
Host smart-d4904a05-34a5-42b0-ac0f-1690ef178709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4123574814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4123574814
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.851167023
Short name T3684
Test name
Test status
Simulation time 74211517 ps
CPU time 0.78 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:43 PM PDT 24
Peak memory 206908 kb
Host smart-63c219e6-53da-4805-99ac-bb225e548a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=851167023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.851167023
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1518667411
Short name T280
Test name
Test status
Simulation time 193440372 ps
CPU time 3.35 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 207136 kb
Host smart-2c2cc629-40c4-4cea-a549-2a445a395216
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1518667411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1518667411
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4116386235
Short name T3709
Test name
Test status
Simulation time 739088140 ps
CPU time 7 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 206120 kb
Host smart-1fdd33d8-fea0-4639-b112-f224e949c8db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4116386235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.4116386235
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1754405238
Short name T3720
Test name
Test status
Simulation time 74120441 ps
CPU time 0.88 seconds
Started Aug 17 06:34:14 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 206856 kb
Host smart-3dfd4963-e87e-4fdd-ab8d-efeb4bcf1044
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1754405238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1754405238
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2688000396
Short name T3721
Test name
Test status
Simulation time 61253120 ps
CPU time 1.52 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215432 kb
Host smart-d66db007-f9cd-4a07-a8c1-21fc0698ca26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688000396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2688000396
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2274756670
Short name T3666
Test name
Test status
Simulation time 57979018 ps
CPU time 0.84 seconds
Started Aug 17 06:34:02 PM PDT 24
Finished Aug 17 06:34:03 PM PDT 24
Peak memory 206972 kb
Host smart-269c94e5-c527-4f2c-a440-cfd060fe574a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2274756670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2274756670
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.560075456
Short name T3708
Test name
Test status
Simulation time 59585902 ps
CPU time 0.75 seconds
Started Aug 17 06:34:17 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 206896 kb
Host smart-4eb50d66-6d98-4d36-8faa-2c4913f14480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=560075456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.560075456
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1377125044
Short name T293
Test name
Test status
Simulation time 201834832 ps
CPU time 2.38 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215392 kb
Host smart-00cec721-0e08-4b5c-b2b3-29cc963d0413
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1377125044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1377125044
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.153576742
Short name T3734
Test name
Test status
Simulation time 101145524 ps
CPU time 2.43 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 206968 kb
Host smart-c8c69f8b-b648-4017-a3bc-d7a3b1ff66c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=153576742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.153576742
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3139751470
Short name T299
Test name
Test status
Simulation time 263065478 ps
CPU time 1.91 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 207300 kb
Host smart-5c0640d5-a395-436c-b037-deaf6c5022a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3139751470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3139751470
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1051486349
Short name T257
Test name
Test status
Simulation time 188132116 ps
CPU time 2.23 seconds
Started Aug 17 06:34:16 PM PDT 24
Finished Aug 17 06:34:23 PM PDT 24
Peak memory 207188 kb
Host smart-2eedf568-67f4-4323-85cf-c536225c1d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1051486349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1051486349
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2247746356
Short name T3642
Test name
Test status
Simulation time 38417265 ps
CPU time 0.71 seconds
Started Aug 17 06:34:46 PM PDT 24
Finished Aug 17 06:34:46 PM PDT 24
Peak memory 206884 kb
Host smart-2de08757-0f12-421f-ab1b-560f60807191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2247746356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2247746356
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4199451554
Short name T3680
Test name
Test status
Simulation time 48421111 ps
CPU time 0.74 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:43 PM PDT 24
Peak memory 206948 kb
Host smart-b0145fe5-57bb-4b91-a051-59ec8d209885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4199451554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.4199451554
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1714815366
Short name T3644
Test name
Test status
Simulation time 65079351 ps
CPU time 0.74 seconds
Started Aug 17 06:34:54 PM PDT 24
Finished Aug 17 06:34:55 PM PDT 24
Peak memory 206916 kb
Host smart-46929d63-46d3-4632-8c9a-a11d196f4dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1714815366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1714815366
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.315388476
Short name T3682
Test name
Test status
Simulation time 39752741 ps
CPU time 0.78 seconds
Started Aug 17 06:34:45 PM PDT 24
Finished Aug 17 06:34:46 PM PDT 24
Peak memory 206836 kb
Host smart-ab1ff8ac-c2c8-432c-a972-6159b583868f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=315388476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.315388476
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3972967041
Short name T3701
Test name
Test status
Simulation time 43963822 ps
CPU time 0.69 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 206896 kb
Host smart-787bf573-2a79-44ab-b7c8-81e752a3df39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3972967041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3972967041
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.179719988
Short name T3707
Test name
Test status
Simulation time 101162401 ps
CPU time 0.82 seconds
Started Aug 17 06:34:27 PM PDT 24
Finished Aug 17 06:34:28 PM PDT 24
Peak memory 206908 kb
Host smart-1fb1dbd1-a9b1-480b-8038-f0aee1fa8765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=179719988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.179719988
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.747940316
Short name T3671
Test name
Test status
Simulation time 73821422 ps
CPU time 0.81 seconds
Started Aug 17 06:34:22 PM PDT 24
Finished Aug 17 06:34:23 PM PDT 24
Peak memory 206876 kb
Host smart-ae9cea04-ebdd-4fba-8391-d8e89b28929f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=747940316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.747940316
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2843210599
Short name T3690
Test name
Test status
Simulation time 136229747 ps
CPU time 0.81 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 206896 kb
Host smart-7b4d231b-8d63-4246-9795-73e21cbfc1af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2843210599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2843210599
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.977291366
Short name T3656
Test name
Test status
Simulation time 107140943 ps
CPU time 0.8 seconds
Started Aug 17 06:34:44 PM PDT 24
Finished Aug 17 06:34:45 PM PDT 24
Peak memory 206852 kb
Host smart-61c2b89f-69c1-4f08-8595-15ce3c9d7e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=977291366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.977291366
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2672358272
Short name T3646
Test name
Test status
Simulation time 48162469 ps
CPU time 0.73 seconds
Started Aug 17 06:34:47 PM PDT 24
Finished Aug 17 06:34:48 PM PDT 24
Peak memory 206876 kb
Host smart-bdc2f754-efdc-4444-a557-a10c25d5e1e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2672358272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2672358272
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.663075997
Short name T263
Test name
Test status
Simulation time 102343353 ps
CPU time 1.72 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215508 kb
Host smart-04abfb04-4ad1-4911-85bb-9d545e8f252d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663075997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.663075997
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3636372617
Short name T305
Test name
Test status
Simulation time 126159528 ps
CPU time 0.92 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 206944 kb
Host smart-0f36d9b2-15c3-41eb-bd97-96442f917ba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3636372617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3636372617
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1978571195
Short name T323
Test name
Test status
Simulation time 101195004 ps
CPU time 0.76 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 206872 kb
Host smart-b72afaa1-c886-4567-bd19-0a6e9b0517f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1978571195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1978571195
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3501352283
Short name T320
Test name
Test status
Simulation time 205550052 ps
CPU time 1.6 seconds
Started Aug 17 06:34:14 PM PDT 24
Finished Aug 17 06:34:16 PM PDT 24
Peak memory 207264 kb
Host smart-6dd7ba24-5dda-4cbe-ba3d-88a6049a68ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3501352283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3501352283
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.361527121
Short name T3714
Test name
Test status
Simulation time 87407391 ps
CPU time 2.03 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 207256 kb
Host smart-79b10b86-6c44-449a-a1f5-d611d6327d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=361527121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.361527121
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2203970585
Short name T3689
Test name
Test status
Simulation time 328140331 ps
CPU time 2.33 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 207296 kb
Host smart-94f03b7d-6c14-496b-88c0-215be1938778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2203970585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2203970585
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1176346165
Short name T3716
Test name
Test status
Simulation time 170100968 ps
CPU time 1.7 seconds
Started Aug 17 06:34:47 PM PDT 24
Finished Aug 17 06:34:49 PM PDT 24
Peak memory 217796 kb
Host smart-6e57df51-d93d-4a82-85cc-1408836aff32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176346165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1176346165
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4090807106
Short name T286
Test name
Test status
Simulation time 67700225 ps
CPU time 0.84 seconds
Started Aug 17 06:34:29 PM PDT 24
Finished Aug 17 06:34:30 PM PDT 24
Peak memory 206876 kb
Host smart-08dc51cb-af36-42d0-ac2c-a7b9757d30b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4090807106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4090807106
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2861636656
Short name T3725
Test name
Test status
Simulation time 49293635 ps
CPU time 0.69 seconds
Started Aug 17 06:34:17 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 206884 kb
Host smart-d1a8cf4d-cd86-4461-af1e-aae162a133ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2861636656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2861636656
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.254905348
Short name T3711
Test name
Test status
Simulation time 61964815 ps
CPU time 1.02 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 207068 kb
Host smart-7e419b41-7234-4979-833a-dadddf8ea957
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=254905348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.254905348
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1791750563
Short name T252
Test name
Test status
Simulation time 67514421 ps
CPU time 2.01 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 207268 kb
Host smart-8fa71dde-8bba-4f32-8b88-43a2002915be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1791750563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1791750563
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.706967871
Short name T3703
Test name
Test status
Simulation time 496547448 ps
CPU time 3 seconds
Started Aug 17 06:34:34 PM PDT 24
Finished Aug 17 06:34:37 PM PDT 24
Peak memory 207240 kb
Host smart-b97aeaae-e383-4da7-97b8-6e5a00b4635a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=706967871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.706967871
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1060241797
Short name T231
Test name
Test status
Simulation time 176944552 ps
CPU time 1.84 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 215552 kb
Host smart-edb88fae-293c-4d38-8c16-2d0d678bc7fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060241797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1060241797
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2530418983
Short name T3654
Test name
Test status
Simulation time 39199240 ps
CPU time 0.83 seconds
Started Aug 17 06:34:18 PM PDT 24
Finished Aug 17 06:34:19 PM PDT 24
Peak memory 206920 kb
Host smart-fe1f9f35-2982-4fc0-8479-2b9bc58100e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2530418983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2530418983
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1291489339
Short name T3667
Test name
Test status
Simulation time 123090193 ps
CPU time 0.8 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 206852 kb
Host smart-4090b4e5-f97e-4bff-ae1a-2930dc62ce96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1291489339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1291489339
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3396480608
Short name T3717
Test name
Test status
Simulation time 193499543 ps
CPU time 1.62 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 207256 kb
Host smart-eae9733c-e13a-4059-930c-69ca3b308f34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3396480608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3396480608
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4188815042
Short name T326
Test name
Test status
Simulation time 118567684 ps
CPU time 1.51 seconds
Started Aug 17 06:34:31 PM PDT 24
Finished Aug 17 06:34:33 PM PDT 24
Peak memory 207252 kb
Host smart-8571b769-3fd4-4c72-baf1-aac7ecd200df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4188815042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.4188815042
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2660347477
Short name T319
Test name
Test status
Simulation time 1154033678 ps
CPU time 5.53 seconds
Started Aug 17 06:34:16 PM PDT 24
Finished Aug 17 06:34:22 PM PDT 24
Peak memory 207244 kb
Host smart-22506f65-c573-499d-a5c2-4ec92861cd63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2660347477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2660347477
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.910828245
Short name T3706
Test name
Test status
Simulation time 94269096 ps
CPU time 1.36 seconds
Started Aug 17 06:34:14 PM PDT 24
Finished Aug 17 06:34:21 PM PDT 24
Peak memory 215488 kb
Host smart-c9a45291-e491-4f15-ab7c-57b33ccf7fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910828245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.910828245
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2699685604
Short name T297
Test name
Test status
Simulation time 94148880 ps
CPU time 1 seconds
Started Aug 17 06:34:17 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 206924 kb
Host smart-16304752-b124-4b65-8896-5be940af364c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2699685604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2699685604
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.581201425
Short name T3674
Test name
Test status
Simulation time 52728021 ps
CPU time 0.72 seconds
Started Aug 17 06:34:17 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 206872 kb
Host smart-dfcf7412-4d66-4583-b0a4-78f1a79bbf62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=581201425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.581201425
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3696251676
Short name T3719
Test name
Test status
Simulation time 398948556 ps
CPU time 1.74 seconds
Started Aug 17 06:34:26 PM PDT 24
Finished Aug 17 06:34:28 PM PDT 24
Peak memory 207320 kb
Host smart-f898dd1a-87be-471b-9539-bfb632d68188
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3696251676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3696251676
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1634643901
Short name T256
Test name
Test status
Simulation time 143324679 ps
CPU time 1.88 seconds
Started Aug 17 06:34:18 PM PDT 24
Finished Aug 17 06:34:20 PM PDT 24
Peak memory 207216 kb
Host smart-9431cba8-89d3-454f-8b83-419a4c5a93f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1634643901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1634643901
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2119128831
Short name T260
Test name
Test status
Simulation time 54287569 ps
CPU time 1.18 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215564 kb
Host smart-8b78cb12-0959-4680-97d1-25b57764bae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119128831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2119128831
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.378930930
Short name T3693
Test name
Test status
Simulation time 144100703 ps
CPU time 0.91 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 206984 kb
Host smart-8e3a64c5-f7af-4e54-871f-f80ae086b024
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=378930930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.378930930
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1995533708
Short name T324
Test name
Test status
Simulation time 85568970 ps
CPU time 0.78 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 206864 kb
Host smart-41089ff9-18fe-4443-bf08-0004610852b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1995533708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1995533708
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3346416358
Short name T304
Test name
Test status
Simulation time 119153950 ps
CPU time 1.51 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 207236 kb
Host smart-da58f0b1-0896-4948-8710-1d115b32ecb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3346416358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3346416358
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1516836631
Short name T3735
Test name
Test status
Simulation time 284122560 ps
CPU time 2.49 seconds
Started Aug 17 06:34:15 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 223552 kb
Host smart-4425c439-cc7f-4376-ada4-b954deb1dcef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1516836631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1516836631
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.740853069
Short name T361
Test name
Test status
Simulation time 451038315 ps
CPU time 3.22 seconds
Started Aug 17 06:34:23 PM PDT 24
Finished Aug 17 06:34:26 PM PDT 24
Peak memory 207276 kb
Host smart-9edecd15-2809-4153-be75-06977c23442d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=740853069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.740853069
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1738014036
Short name T1136
Test name
Test status
Simulation time 54468606 ps
CPU time 0.7 seconds
Started Aug 17 06:02:38 PM PDT 24
Finished Aug 17 06:02:39 PM PDT 24
Peak memory 207460 kb
Host smart-9ffc8d77-d1f9-4eb4-8f8d-e7ad2ae12398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1738014036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1738014036
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.347909830
Short name T2879
Test name
Test status
Simulation time 20860955661 ps
CPU time 27.32 seconds
Started Aug 17 06:02:17 PM PDT 24
Finished Aug 17 06:02:44 PM PDT 24
Peak memory 207768 kb
Host smart-5ca4e94a-67b7-44f8-af32-44d99b42ed51
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=347909830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.347909830
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2975301542
Short name T1726
Test name
Test status
Simulation time 25937733022 ps
CPU time 33.25 seconds
Started Aug 17 06:02:14 PM PDT 24
Finished Aug 17 06:02:48 PM PDT 24
Peak memory 215964 kb
Host smart-08445ee4-f450-45c4-ba6c-00c9389fe945
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975301542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.2975301542
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4261726815
Short name T890
Test name
Test status
Simulation time 164801023 ps
CPU time 0.85 seconds
Started Aug 17 06:02:14 PM PDT 24
Finished Aug 17 06:02:15 PM PDT 24
Peak memory 207432 kb
Host smart-f44ed4ae-6162-4054-a2fc-d1bae0c7a166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42617
26815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4261726815
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1325238125
Short name T661
Test name
Test status
Simulation time 158348475 ps
CPU time 0.84 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:02:24 PM PDT 24
Peak memory 207560 kb
Host smart-6657e184-672c-48e1-9b04-75b8f69d35a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13252
38125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1325238125
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.346468904
Short name T570
Test name
Test status
Simulation time 435610917 ps
CPU time 1.51 seconds
Started Aug 17 06:02:24 PM PDT 24
Finished Aug 17 06:02:25 PM PDT 24
Peak memory 207552 kb
Host smart-11b6564f-757d-499c-bb5c-bcea8798881f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34646
8904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.346468904
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2102194243
Short name T2291
Test name
Test status
Simulation time 678114863 ps
CPU time 1.83 seconds
Started Aug 17 06:02:27 PM PDT 24
Finished Aug 17 06:02:29 PM PDT 24
Peak memory 207744 kb
Host smart-ad57073b-357a-4db7-8000-61038f3bb450
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2102194243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2102194243
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.1405942492
Short name T370
Test name
Test status
Simulation time 40035364360 ps
CPU time 83.12 seconds
Started Aug 17 06:02:15 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207796 kb
Host smart-32383b44-ffba-4014-b964-5b28aac6bf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14059
42492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1405942492
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.3365600331
Short name T1848
Test name
Test status
Simulation time 981425495 ps
CPU time 22.74 seconds
Started Aug 17 06:02:13 PM PDT 24
Finished Aug 17 06:02:36 PM PDT 24
Peak memory 207704 kb
Host smart-18c585d3-7b53-4aae-8639-d2fa3851017b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365600331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.3365600331
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3198287052
Short name T1986
Test name
Test status
Simulation time 854624245 ps
CPU time 1.99 seconds
Started Aug 17 06:02:24 PM PDT 24
Finished Aug 17 06:02:26 PM PDT 24
Peak memory 207528 kb
Host smart-2fe06581-f4a5-4991-9e07-cbbc089b6ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31982
87052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3198287052
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1651774162
Short name T2932
Test name
Test status
Simulation time 214988340 ps
CPU time 0.92 seconds
Started Aug 17 06:02:14 PM PDT 24
Finished Aug 17 06:02:15 PM PDT 24
Peak memory 207508 kb
Host smart-c8d6cd4a-ed71-4537-ac08-2350472ea754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16517
74162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1651774162
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.2620658362
Short name T2205
Test name
Test status
Simulation time 52033542 ps
CPU time 0.7 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:02:24 PM PDT 24
Peak memory 207448 kb
Host smart-627750a9-7206-4fe7-a6ec-47febfc361d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26206
58362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2620658362
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.585240401
Short name T3365
Test name
Test status
Simulation time 908368657 ps
CPU time 2.74 seconds
Started Aug 17 06:02:14 PM PDT 24
Finished Aug 17 06:02:17 PM PDT 24
Peak memory 207692 kb
Host smart-016b6fbb-d7bd-4d7c-acde-68d9384f1d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58524
0401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.585240401
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_types.2961685798
Short name T391
Test name
Test status
Simulation time 518924028 ps
CPU time 1.64 seconds
Started Aug 17 06:02:15 PM PDT 24
Finished Aug 17 06:02:17 PM PDT 24
Peak memory 207528 kb
Host smart-f1587347-af4d-44d1-907c-f6d7508ea516
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2961685798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.2961685798
Directory /workspace/0.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1593074141
Short name T1660
Test name
Test status
Simulation time 214614465 ps
CPU time 1.96 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:02:25 PM PDT 24
Peak memory 207684 kb
Host smart-4f75a86a-3355-48e6-918c-be52e544e884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15930
74141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1593074141
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.1884345764
Short name T975
Test name
Test status
Simulation time 116179125935 ps
CPU time 199.86 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:05:43 PM PDT 24
Peak memory 207696 kb
Host smart-a360664d-5c90-4bee-81c4-5d83f63a5394
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1884345764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.1884345764
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.1235540413
Short name T1769
Test name
Test status
Simulation time 99346367330 ps
CPU time 192.13 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:05:35 PM PDT 24
Peak memory 207784 kb
Host smart-5493375e-3c1a-43da-9af7-e5aea2f07bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235540413 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.1235540413
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.3241541383
Short name T1922
Test name
Test status
Simulation time 113104078217 ps
CPU time 217.2 seconds
Started Aug 17 06:02:16 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207716 kb
Host smart-5abe9bcd-484b-46e3-a2c8-4aa296676331
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3241541383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3241541383
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3804938351
Short name T3470
Test name
Test status
Simulation time 81073939792 ps
CPU time 130.87 seconds
Started Aug 17 06:02:20 PM PDT 24
Finished Aug 17 06:04:31 PM PDT 24
Peak memory 207832 kb
Host smart-e4a92dfb-1b04-42bf-9e0d-aaf3c7282a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804938351 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3804938351
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3495021819
Short name T3209
Test name
Test status
Simulation time 97155615083 ps
CPU time 163.72 seconds
Started Aug 17 06:02:15 PM PDT 24
Finished Aug 17 06:04:59 PM PDT 24
Peak memory 207740 kb
Host smart-a11e1e9b-e19f-450c-a160-0de00a9ce1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34950
21819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3495021819
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1344077598
Short name T830
Test name
Test status
Simulation time 225483198 ps
CPU time 1.07 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:02:24 PM PDT 24
Peak memory 215880 kb
Host smart-eea7d270-35a0-4234-ad85-8a8a63fd532c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1344077598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1344077598
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2049346825
Short name T994
Test name
Test status
Simulation time 166844555 ps
CPU time 0.87 seconds
Started Aug 17 06:02:15 PM PDT 24
Finished Aug 17 06:02:17 PM PDT 24
Peak memory 207424 kb
Host smart-5af86864-67a0-4b36-b952-706d9e3211a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20493
46825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2049346825
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1743143604
Short name T1088
Test name
Test status
Simulation time 204763344 ps
CPU time 0.93 seconds
Started Aug 17 06:02:22 PM PDT 24
Finished Aug 17 06:02:23 PM PDT 24
Peak memory 207476 kb
Host smart-9fc4d526-4a72-43b7-bb2e-93c6b11ec745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17431
43604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1743143604
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1217063822
Short name T3067
Test name
Test status
Simulation time 5206210957 ps
CPU time 55.25 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:03:18 PM PDT 24
Peak memory 218096 kb
Host smart-878ffe1b-ec35-4b1b-8e6f-4d5937314d15
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1217063822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1217063822
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.2674379124
Short name T553
Test name
Test status
Simulation time 12379099883 ps
CPU time 154.16 seconds
Started Aug 17 06:02:13 PM PDT 24
Finished Aug 17 06:04:47 PM PDT 24
Peak memory 207776 kb
Host smart-107c9e43-662f-4597-8c4f-656c03466832
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2674379124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.2674379124
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.4020428292
Short name T2146
Test name
Test status
Simulation time 175918797 ps
CPU time 0.9 seconds
Started Aug 17 06:02:22 PM PDT 24
Finished Aug 17 06:02:23 PM PDT 24
Peak memory 207476 kb
Host smart-98a4c795-1f2e-43d8-a019-f77e219735c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40204
28292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.4020428292
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1982297992
Short name T66
Test name
Test status
Simulation time 489853804 ps
CPU time 1.59 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:23 PM PDT 24
Peak memory 207576 kb
Host smart-c6f81c48-9ca8-4fcb-a500-47fe90c19f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
97992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1982297992
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2248608530
Short name T902
Test name
Test status
Simulation time 14793384615 ps
CPU time 24.49 seconds
Started Aug 17 06:02:24 PM PDT 24
Finished Aug 17 06:02:49 PM PDT 24
Peak memory 207744 kb
Host smart-25fa6ad1-a9aa-4919-9015-0d85e7753e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22486
08530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2248608530
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.4175007619
Short name T2584
Test name
Test status
Simulation time 10940670466 ps
CPU time 16.26 seconds
Started Aug 17 06:02:22 PM PDT 24
Finished Aug 17 06:02:38 PM PDT 24
Peak memory 207824 kb
Host smart-fcfae00a-4696-4e84-9ddd-570b5fe58e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41750
07619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.4175007619
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3314753643
Short name T2793
Test name
Test status
Simulation time 2017108007 ps
CPU time 15.94 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:37 PM PDT 24
Peak memory 224068 kb
Host smart-5d85dbde-40ad-4026-9cec-5b6d275a7da5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3314753643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3314753643
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2192260040
Short name T3405
Test name
Test status
Simulation time 238623795 ps
CPU time 0.99 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:22 PM PDT 24
Peak memory 207408 kb
Host smart-3019e3d0-f91e-46bc-8eb2-481152f2f8b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2192260040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2192260040
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3495557858
Short name T598
Test name
Test status
Simulation time 216831368 ps
CPU time 0.96 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:22 PM PDT 24
Peak memory 207432 kb
Host smart-98a663da-5674-4a86-83e5-7526a0e8e029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34955
57858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3495557858
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.2434691862
Short name T1978
Test name
Test status
Simulation time 1724603987 ps
CPU time 13.9 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:02:37 PM PDT 24
Peak memory 217712 kb
Host smart-25ac2c9f-919a-40ba-9907-c2039d88977e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24346
91862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.2434691862
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.1480301073
Short name T776
Test name
Test status
Simulation time 2639914437 ps
CPU time 22.76 seconds
Started Aug 17 06:02:19 PM PDT 24
Finished Aug 17 06:02:42 PM PDT 24
Peak memory 224108 kb
Host smart-c2b1f00a-40c9-44c3-aed3-228bf8848762
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1480301073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.1480301073
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.553298856
Short name T745
Test name
Test status
Simulation time 2673902433 ps
CPU time 20.44 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:02:43 PM PDT 24
Peak memory 217608 kb
Host smart-1eb1b299-1476-4c7d-b61f-7df51fb22c18
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=553298856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.553298856
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.69066296
Short name T1456
Test name
Test status
Simulation time 147096582 ps
CPU time 0.87 seconds
Started Aug 17 06:02:23 PM PDT 24
Finished Aug 17 06:02:24 PM PDT 24
Peak memory 207472 kb
Host smart-04e12d6f-0e1d-4925-ace5-0372be97a45b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=69066296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.69066296
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.239978123
Short name T612
Test name
Test status
Simulation time 172569103 ps
CPU time 0.92 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:22 PM PDT 24
Peak memory 207436 kb
Host smart-9615a436-ed2b-42ef-a963-7bcbf227b939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23997
8123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.239978123
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2384106549
Short name T65
Test name
Test status
Simulation time 419624883 ps
CPU time 1.45 seconds
Started Aug 17 06:02:20 PM PDT 24
Finished Aug 17 06:02:21 PM PDT 24
Peak memory 207488 kb
Host smart-5e0d890d-cda4-4f53-b7a4-8c1a72e3c560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23841
06549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2384106549
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.414424102
Short name T1213
Test name
Test status
Simulation time 187932222 ps
CPU time 1.01 seconds
Started Aug 17 06:02:25 PM PDT 24
Finished Aug 17 06:02:26 PM PDT 24
Peak memory 207368 kb
Host smart-e74918e2-cb9b-489e-bf6b-9d2825438eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41442
4102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.414424102
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2792180564
Short name T2081
Test name
Test status
Simulation time 173910529 ps
CPU time 0.91 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:22 PM PDT 24
Peak memory 207468 kb
Host smart-35f8fbdd-41a7-49de-82a1-af47bed59259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27921
80564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2792180564
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.664304316
Short name T2079
Test name
Test status
Simulation time 187539743 ps
CPU time 0.92 seconds
Started Aug 17 06:02:25 PM PDT 24
Finished Aug 17 06:02:26 PM PDT 24
Peak memory 207536 kb
Host smart-f905b44e-7bb1-43b8-8fd8-72e62d7851af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66430
4316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.664304316
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1527287323
Short name T2699
Test name
Test status
Simulation time 168485030 ps
CPU time 0.87 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:22 PM PDT 24
Peak memory 207568 kb
Host smart-97fd1e78-d448-44f6-bb20-b66541c1d2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15272
87323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1527287323
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2375745512
Short name T2734
Test name
Test status
Simulation time 231632182 ps
CPU time 0.98 seconds
Started Aug 17 06:02:22 PM PDT 24
Finished Aug 17 06:02:23 PM PDT 24
Peak memory 207484 kb
Host smart-671d5aea-ccdc-434d-bd0d-4c00159592fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23757
45512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2375745512
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.4169995135
Short name T2017
Test name
Test status
Simulation time 307748958 ps
CPU time 1.29 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:02:23 PM PDT 24
Peak memory 207532 kb
Host smart-c766eeed-fb6b-4a3a-99d3-a595c5ad6c25
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4169995135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.4169995135
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3654375827
Short name T2875
Test name
Test status
Simulation time 219829783 ps
CPU time 1.04 seconds
Started Aug 17 06:02:20 PM PDT 24
Finished Aug 17 06:02:21 PM PDT 24
Peak memory 207408 kb
Host smart-5724c120-b703-4494-a95e-ecfa29196bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36543
75827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3654375827
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.151170650
Short name T3153
Test name
Test status
Simulation time 236913073 ps
CPU time 1.07 seconds
Started Aug 17 06:02:22 PM PDT 24
Finished Aug 17 06:02:23 PM PDT 24
Peak memory 207572 kb
Host smart-808921f6-5cbf-4a2d-8b73-5cb6c8fbe7d1
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=151170650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.151170650
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.3318103358
Short name T3447
Test name
Test status
Simulation time 230412890 ps
CPU time 0.99 seconds
Started Aug 17 06:02:22 PM PDT 24
Finished Aug 17 06:02:23 PM PDT 24
Peak memory 207484 kb
Host smart-92161ad0-9a45-4374-96d6-ddfab493cccf
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3318103358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.3318103358
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3622840451
Short name T2941
Test name
Test status
Simulation time 37871153 ps
CPU time 0.7 seconds
Started Aug 17 06:02:26 PM PDT 24
Finished Aug 17 06:02:27 PM PDT 24
Peak memory 207416 kb
Host smart-8807be40-f216-4bf6-b457-dcaa6f618504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36228
40451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3622840451
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2017474502
Short name T3289
Test name
Test status
Simulation time 19211833719 ps
CPU time 63.78 seconds
Started Aug 17 06:02:21 PM PDT 24
Finished Aug 17 06:03:25 PM PDT 24
Peak memory 215952 kb
Host smart-4e72735e-f5b6-4f75-97fb-f973ff21ec50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20174
74502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2017474502
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2131683837
Short name T1757
Test name
Test status
Simulation time 224398169 ps
CPU time 0.99 seconds
Started Aug 17 06:02:28 PM PDT 24
Finished Aug 17 06:02:29 PM PDT 24
Peak memory 207592 kb
Host smart-a8094e01-3f68-4699-aa5f-4fd9d266df4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21316
83837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2131683837
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.638591980
Short name T714
Test name
Test status
Simulation time 210415012 ps
CPU time 0.96 seconds
Started Aug 17 06:02:30 PM PDT 24
Finished Aug 17 06:02:31 PM PDT 24
Peak memory 207456 kb
Host smart-44c17a0d-59c8-4ce5-b27b-0e7d7bccfde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63859
1980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.638591980
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1163888985
Short name T1620
Test name
Test status
Simulation time 6547579828 ps
CPU time 48.66 seconds
Started Aug 17 06:02:30 PM PDT 24
Finished Aug 17 06:03:19 PM PDT 24
Peak memory 218372 kb
Host smart-9615592e-816a-4377-be3f-d48ef52cbf5b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163888985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1163888985
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2450944754
Short name T1950
Test name
Test status
Simulation time 6887009299 ps
CPU time 37.6 seconds
Started Aug 17 06:02:27 PM PDT 24
Finished Aug 17 06:03:04 PM PDT 24
Peak memory 219428 kb
Host smart-5a495bf3-ee7d-4591-a992-3fd8a2e41beb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2450944754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2450944754
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.950227554
Short name T1807
Test name
Test status
Simulation time 5882251145 ps
CPU time 24.39 seconds
Started Aug 17 06:02:28 PM PDT 24
Finished Aug 17 06:02:52 PM PDT 24
Peak memory 219388 kb
Host smart-9bc04033-eced-4d41-a149-a1c7301143d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=950227554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.950227554
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1689086227
Short name T2646
Test name
Test status
Simulation time 225185514 ps
CPU time 1.04 seconds
Started Aug 17 06:02:39 PM PDT 24
Finished Aug 17 06:02:40 PM PDT 24
Peak memory 207464 kb
Host smart-4110a0b0-5f4b-4882-9b9d-1834604019c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16890
86227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1689086227
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.2962185571
Short name T1328
Test name
Test status
Simulation time 266113061 ps
CPU time 1.02 seconds
Started Aug 17 06:02:31 PM PDT 24
Finished Aug 17 06:02:32 PM PDT 24
Peak memory 207460 kb
Host smart-296c5219-c601-4443-93be-d5f40c2598b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29621
85571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.2962185571
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.4259177267
Short name T102
Test name
Test status
Simulation time 20166636859 ps
CPU time 30.45 seconds
Started Aug 17 06:02:28 PM PDT 24
Finished Aug 17 06:02:58 PM PDT 24
Peak memory 207576 kb
Host smart-febef932-a145-42a7-a543-f899c0f1ef3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42591
77267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.4259177267
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.922194939
Short name T1479
Test name
Test status
Simulation time 172144762 ps
CPU time 0.9 seconds
Started Aug 17 06:02:31 PM PDT 24
Finished Aug 17 06:02:32 PM PDT 24
Peak memory 207388 kb
Host smart-8554f66a-0679-40a8-9af7-d1031266091c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92219
4939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.922194939
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2887095275
Short name T242
Test name
Test status
Simulation time 317972831 ps
CPU time 1.13 seconds
Started Aug 17 06:02:30 PM PDT 24
Finished Aug 17 06:02:32 PM PDT 24
Peak memory 223316 kb
Host smart-f64667e9-4836-46a1-8032-fce698505103
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2887095275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2887095275
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2293352132
Short name T2159
Test name
Test status
Simulation time 209016210 ps
CPU time 0.95 seconds
Started Aug 17 06:02:36 PM PDT 24
Finished Aug 17 06:02:37 PM PDT 24
Peak memory 207488 kb
Host smart-daa36d4e-090a-486b-a03e-5025dcf8b0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22933
52132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2293352132
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.994386376
Short name T2550
Test name
Test status
Simulation time 160051141 ps
CPU time 0.88 seconds
Started Aug 17 06:02:38 PM PDT 24
Finished Aug 17 06:02:39 PM PDT 24
Peak memory 207400 kb
Host smart-54cb14d2-c7dd-4522-b7e2-731dfe859685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99438
6376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.994386376
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1164334377
Short name T1203
Test name
Test status
Simulation time 164642347 ps
CPU time 0.87 seconds
Started Aug 17 06:02:28 PM PDT 24
Finished Aug 17 06:02:29 PM PDT 24
Peak memory 207552 kb
Host smart-a0328219-f107-428f-b9ba-6a20221373c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11643
34377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1164334377
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.68434491
Short name T3241
Test name
Test status
Simulation time 241052144 ps
CPU time 1.06 seconds
Started Aug 17 06:02:30 PM PDT 24
Finished Aug 17 06:02:31 PM PDT 24
Peak memory 207468 kb
Host smart-ffb0d322-74fc-48af-bd2d-97c485a88fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68434
491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.68434491
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3008504330
Short name T2996
Test name
Test status
Simulation time 157593758 ps
CPU time 0.84 seconds
Started Aug 17 06:02:30 PM PDT 24
Finished Aug 17 06:02:31 PM PDT 24
Peak memory 207484 kb
Host smart-e6f92ad2-eed4-446e-bf1c-efa272b1b387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30085
04330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3008504330
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2978122155
Short name T851
Test name
Test status
Simulation time 160845982 ps
CPU time 0.84 seconds
Started Aug 17 06:02:35 PM PDT 24
Finished Aug 17 06:02:36 PM PDT 24
Peak memory 207484 kb
Host smart-7e8c5d27-7ed3-47a3-94f7-f74060381b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29781
22155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2978122155
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.837769195
Short name T1069
Test name
Test status
Simulation time 503387597 ps
CPU time 1.63 seconds
Started Aug 17 06:02:31 PM PDT 24
Finished Aug 17 06:02:33 PM PDT 24
Peak memory 207500 kb
Host smart-f8e03134-f181-4ad5-b539-d87d1e30291a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83776
9195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.837769195
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3722997720
Short name T3055
Test name
Test status
Simulation time 2424804342 ps
CPU time 24.18 seconds
Started Aug 17 06:02:31 PM PDT 24
Finished Aug 17 06:02:55 PM PDT 24
Peak memory 217592 kb
Host smart-07bd6b74-0a67-411b-a72c-dce71cb89637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37229
97720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3722997720
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.506323449
Short name T2596
Test name
Test status
Simulation time 2068242669 ps
CPU time 18.78 seconds
Started Aug 17 06:02:15 PM PDT 24
Finished Aug 17 06:02:35 PM PDT 24
Peak memory 207592 kb
Host smart-87f1635e-3f71-41b0-a696-0417c2d5ca4c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506323449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host_
handshake.506323449
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/0.usbdev_tx_rx_disruption.166663125
Short name T1695
Test name
Test status
Simulation time 503931619 ps
CPU time 1.56 seconds
Started Aug 17 06:02:30 PM PDT 24
Finished Aug 17 06:02:32 PM PDT 24
Peak memory 207468 kb
Host smart-48021cc3-e3c4-4f1c-8d01-9cbfe3a02010
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166663125 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.usbdev_tx_rx_disruption.166663125
Directory /workspace/0.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.2781316648
Short name T1851
Test name
Test status
Simulation time 51384470 ps
CPU time 0.68 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:02:51 PM PDT 24
Peak memory 207428 kb
Host smart-5153444b-1857-4349-a3eb-384be41967e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2781316648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2781316648
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3356845979
Short name T2789
Test name
Test status
Simulation time 5556849116 ps
CPU time 8.27 seconds
Started Aug 17 06:02:29 PM PDT 24
Finished Aug 17 06:02:37 PM PDT 24
Peak memory 215940 kb
Host smart-758cc854-f08c-4168-841c-6c5de1365673
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356845979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.3356845979
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1859338939
Short name T2115
Test name
Test status
Simulation time 15361000870 ps
CPU time 18.58 seconds
Started Aug 17 06:02:29 PM PDT 24
Finished Aug 17 06:02:48 PM PDT 24
Peak memory 215956 kb
Host smart-e61a7e2f-bf38-432a-8310-f54537dd5fe8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859338939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1859338939
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1628032342
Short name T1891
Test name
Test status
Simulation time 31359223857 ps
CPU time 46.84 seconds
Started Aug 17 06:02:37 PM PDT 24
Finished Aug 17 06:03:24 PM PDT 24
Peak memory 207800 kb
Host smart-385b0531-9292-423e-94bd-4cb8c9412677
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628032342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.1628032342
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.50985145
Short name T3045
Test name
Test status
Simulation time 178560695 ps
CPU time 0.86 seconds
Started Aug 17 06:02:36 PM PDT 24
Finished Aug 17 06:02:36 PM PDT 24
Peak memory 207468 kb
Host smart-f41f929e-6879-4055-8972-e352cafe4585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50985
145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.50985145
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1822700982
Short name T54
Test name
Test status
Simulation time 201622956 ps
CPU time 0.94 seconds
Started Aug 17 06:02:36 PM PDT 24
Finished Aug 17 06:02:37 PM PDT 24
Peak memory 207464 kb
Host smart-32be46dc-1210-4076-b159-2c068e0ca58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18227
00982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1822700982
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2024661195
Short name T849
Test name
Test status
Simulation time 179109393 ps
CPU time 0.88 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:44 PM PDT 24
Peak memory 207560 kb
Host smart-a3ce10df-04dc-4f4e-8864-c47705ee9849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20246
61195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2024661195
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.484180787
Short name T2307
Test name
Test status
Simulation time 401911069 ps
CPU time 1.44 seconds
Started Aug 17 06:02:35 PM PDT 24
Finished Aug 17 06:02:36 PM PDT 24
Peak memory 207564 kb
Host smart-36ddc463-f465-4b32-aca5-e6e3b19860d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48418
0787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.484180787
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.1910848544
Short name T2736
Test name
Test status
Simulation time 4355025760 ps
CPU time 28.2 seconds
Started Aug 17 06:02:44 PM PDT 24
Finished Aug 17 06:03:12 PM PDT 24
Peak memory 207688 kb
Host smart-e3104c5e-b12b-41db-bfa4-aa94a1600529
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910848544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.1910848544
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1912539956
Short name T3311
Test name
Test status
Simulation time 888665710 ps
CPU time 2.03 seconds
Started Aug 17 06:02:34 PM PDT 24
Finished Aug 17 06:02:37 PM PDT 24
Peak memory 207540 kb
Host smart-53ef07d2-66c8-4aba-bb64-f63eb0f7d7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19125
39956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1912539956
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3653941692
Short name T685
Test name
Test status
Simulation time 142175612 ps
CPU time 0.82 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:44 PM PDT 24
Peak memory 207528 kb
Host smart-c3f7dd3f-6fa6-4345-878e-8552bddd37af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36539
41692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3653941692
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.378397613
Short name T3262
Test name
Test status
Simulation time 39112411 ps
CPU time 0.69 seconds
Started Aug 17 06:02:35 PM PDT 24
Finished Aug 17 06:02:36 PM PDT 24
Peak memory 207436 kb
Host smart-83033b18-5030-479a-96c2-d937632244b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37839
7613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.378397613
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1687056077
Short name T2492
Test name
Test status
Simulation time 978327688 ps
CPU time 2.64 seconds
Started Aug 17 06:02:35 PM PDT 24
Finished Aug 17 06:02:38 PM PDT 24
Peak memory 207792 kb
Host smart-25debd52-2128-43d6-bf9f-f779d32b38fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16870
56077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1687056077
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_types.2141940312
Short name T466
Test name
Test status
Simulation time 286870614 ps
CPU time 1.1 seconds
Started Aug 17 06:02:33 PM PDT 24
Finished Aug 17 06:02:34 PM PDT 24
Peak memory 207508 kb
Host smart-5d4a61be-e8c3-4667-ac11-4210a31ca787
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2141940312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.2141940312
Directory /workspace/1.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2797598243
Short name T1779
Test name
Test status
Simulation time 236856389 ps
CPU time 1.8 seconds
Started Aug 17 06:02:36 PM PDT 24
Finished Aug 17 06:02:38 PM PDT 24
Peak memory 207668 kb
Host smart-fe53ea98-4128-43e2-96e4-ce2a561013d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27975
98243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2797598243
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1750028185
Short name T2190
Test name
Test status
Simulation time 109181376672 ps
CPU time 161.05 seconds
Started Aug 17 06:02:37 PM PDT 24
Finished Aug 17 06:05:18 PM PDT 24
Peak memory 207716 kb
Host smart-4ece4ed6-8eb9-4afe-bc12-0f742e25267f
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1750028185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1750028185
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.3297574338
Short name T347
Test name
Test status
Simulation time 112399163936 ps
CPU time 187.52 seconds
Started Aug 17 06:02:36 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 207780 kb
Host smart-ec301443-09ad-4f07-a736-c02ae8c6ae47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297574338 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.3297574338
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2437472187
Short name T2392
Test name
Test status
Simulation time 97106915643 ps
CPU time 175.29 seconds
Started Aug 17 06:02:35 PM PDT 24
Finished Aug 17 06:05:31 PM PDT 24
Peak memory 207692 kb
Host smart-3b0436e5-cc58-480b-bf1b-4630c33d8001
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2437472187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2437472187
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.35961225
Short name T2666
Test name
Test status
Simulation time 88948125602 ps
CPU time 173.85 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207752 kb
Host smart-7d56571a-8980-45fa-8c85-efb43a4b9e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961225 -assert nop
ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.35961225
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3283385412
Short name T3496
Test name
Test status
Simulation time 92133380927 ps
CPU time 142.38 seconds
Started Aug 17 06:02:37 PM PDT 24
Finished Aug 17 06:04:59 PM PDT 24
Peak memory 207712 kb
Host smart-c60c9740-939e-4e5b-8194-fd4fe6b658c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32833
85412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3283385412
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.734703828
Short name T3120
Test name
Test status
Simulation time 191564658 ps
CPU time 1.01 seconds
Started Aug 17 06:02:34 PM PDT 24
Finished Aug 17 06:02:35 PM PDT 24
Peak memory 215812 kb
Host smart-3e9034df-da33-4c1f-a260-be8e33156618
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=734703828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.734703828
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.424620984
Short name T3229
Test name
Test status
Simulation time 148364961 ps
CPU time 0.82 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:44 PM PDT 24
Peak memory 207448 kb
Host smart-a2ba2f29-9ea3-4ddb-a1f1-50df86c72926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
0984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.424620984
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1553522024
Short name T715
Test name
Test status
Simulation time 203839991 ps
CPU time 0.93 seconds
Started Aug 17 06:02:35 PM PDT 24
Finished Aug 17 06:02:36 PM PDT 24
Peak memory 207420 kb
Host smart-9e970d75-ac8e-417c-9865-46f312235bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15535
22024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1553522024
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2006528737
Short name T1857
Test name
Test status
Simulation time 4467469022 ps
CPU time 42.21 seconds
Started Aug 17 06:02:42 PM PDT 24
Finished Aug 17 06:03:25 PM PDT 24
Peak memory 215988 kb
Host smart-897ab6b7-d25c-4061-bc69-35a4ae749bcd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2006528737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2006528737
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.2287364221
Short name T1584
Test name
Test status
Simulation time 4534449102 ps
CPU time 29.38 seconds
Started Aug 17 06:02:36 PM PDT 24
Finished Aug 17 06:03:05 PM PDT 24
Peak memory 207804 kb
Host smart-eb90d84a-07cb-469a-a587-3d19946faa84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2287364221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.2287364221
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.312098498
Short name T2508
Test name
Test status
Simulation time 229866251 ps
CPU time 0.99 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:45 PM PDT 24
Peak memory 207476 kb
Host smart-509de8fb-89bd-4c4b-9469-9d30d15ea62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31209
8498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.312098498
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.3143503247
Short name T3463
Test name
Test status
Simulation time 26816248270 ps
CPU time 49.97 seconds
Started Aug 17 06:02:42 PM PDT 24
Finished Aug 17 06:03:32 PM PDT 24
Peak memory 207576 kb
Host smart-7e702cf5-e3cb-4311-832d-e51dec62eece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31435
03247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.3143503247
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.406037163
Short name T2432
Test name
Test status
Simulation time 9876979757 ps
CPU time 12.39 seconds
Started Aug 17 06:02:44 PM PDT 24
Finished Aug 17 06:02:57 PM PDT 24
Peak memory 207680 kb
Host smart-eb638d8e-bb6f-4bc7-b0f6-f0d1a0f1170b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40603
7163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.406037163
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2262423783
Short name T1416
Test name
Test status
Simulation time 3686447615 ps
CPU time 31.23 seconds
Started Aug 17 06:02:42 PM PDT 24
Finished Aug 17 06:03:14 PM PDT 24
Peak memory 219212 kb
Host smart-a812d4f1-21d4-4e26-8b61-de2738c97626
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2262423783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2262423783
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.3252284390
Short name T2700
Test name
Test status
Simulation time 3315298443 ps
CPU time 27.7 seconds
Started Aug 17 06:02:44 PM PDT 24
Finished Aug 17 06:03:12 PM PDT 24
Peak memory 215976 kb
Host smart-576ba3d2-a3df-452c-a2a4-4d7fc904df68
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3252284390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.3252284390
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.2183558251
Short name T759
Test name
Test status
Simulation time 296282096 ps
CPU time 1.13 seconds
Started Aug 17 06:02:46 PM PDT 24
Finished Aug 17 06:02:47 PM PDT 24
Peak memory 207448 kb
Host smart-cb566e41-0ead-4bc4-8e78-b8ab97012c0a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2183558251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.2183558251
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3215524898
Short name T637
Test name
Test status
Simulation time 212423590 ps
CPU time 0.98 seconds
Started Aug 17 06:02:45 PM PDT 24
Finished Aug 17 06:02:46 PM PDT 24
Peak memory 207480 kb
Host smart-59d2ea28-0a15-4f50-845b-0f64c01780c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32155
24898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3215524898
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.2914767520
Short name T2326
Test name
Test status
Simulation time 2689951237 ps
CPU time 81.56 seconds
Started Aug 17 06:02:44 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 217836 kb
Host smart-a855f456-5491-4a65-9527-92fa1b261530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29147
67520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.2914767520
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2767931815
Short name T2674
Test name
Test status
Simulation time 3237789184 ps
CPU time 103.41 seconds
Started Aug 17 06:02:42 PM PDT 24
Finished Aug 17 06:04:26 PM PDT 24
Peak memory 218396 kb
Host smart-1985ed6f-f3ff-4289-8060-808f19384cfe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2767931815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2767931815
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2558208814
Short name T1971
Test name
Test status
Simulation time 2675503549 ps
CPU time 79.78 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:04:03 PM PDT 24
Peak memory 217408 kb
Host smart-410dee00-fd94-4d07-8586-a28a8dc14e47
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2558208814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2558208814
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.984805902
Short name T1218
Test name
Test status
Simulation time 208469454 ps
CPU time 0.96 seconds
Started Aug 17 06:02:45 PM PDT 24
Finished Aug 17 06:02:46 PM PDT 24
Peak memory 207456 kb
Host smart-68d57ee6-cca6-4dc0-be48-333bfc2d97ef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=984805902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.984805902
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.736970390
Short name T3013
Test name
Test status
Simulation time 148034909 ps
CPU time 0.91 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:44 PM PDT 24
Peak memory 207484 kb
Host smart-90f77683-8bfc-4d8e-8e0b-d4fd87009b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73697
0390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.736970390
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.360042997
Short name T2582
Test name
Test status
Simulation time 149158106 ps
CPU time 0.87 seconds
Started Aug 17 06:02:45 PM PDT 24
Finished Aug 17 06:02:46 PM PDT 24
Peak memory 207452 kb
Host smart-9e4a7c52-7a92-429d-b58f-c74b664a43a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36004
2997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.360042997
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3494656270
Short name T1442
Test name
Test status
Simulation time 206592141 ps
CPU time 0.92 seconds
Started Aug 17 06:02:42 PM PDT 24
Finished Aug 17 06:02:43 PM PDT 24
Peak memory 207684 kb
Host smart-02d3b2a6-b93c-4e5b-b003-7bf3d4f5ca13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34946
56270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3494656270
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3063421303
Short name T1592
Test name
Test status
Simulation time 219055112 ps
CPU time 1.03 seconds
Started Aug 17 06:02:44 PM PDT 24
Finished Aug 17 06:02:45 PM PDT 24
Peak memory 207612 kb
Host smart-0f5bc12b-d98e-41e7-b4d2-1b5e4c211d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30634
21303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3063421303
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2827532085
Short name T1487
Test name
Test status
Simulation time 249534901 ps
CPU time 1.08 seconds
Started Aug 17 06:02:44 PM PDT 24
Finished Aug 17 06:02:46 PM PDT 24
Peak memory 207556 kb
Host smart-646f65dd-dd43-4e28-b569-31fc2ffce166
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2827532085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2827532085
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3545916825
Short name T1090
Test name
Test status
Simulation time 250363539 ps
CPU time 1.1 seconds
Started Aug 17 06:02:46 PM PDT 24
Finished Aug 17 06:02:47 PM PDT 24
Peak memory 207368 kb
Host smart-a08b8484-5375-49cc-bd38-f45b1fbfec03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35459
16825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3545916825
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.408602410
Short name T872
Test name
Test status
Simulation time 145234021 ps
CPU time 1 seconds
Started Aug 17 06:02:42 PM PDT 24
Finished Aug 17 06:02:43 PM PDT 24
Peak memory 207432 kb
Host smart-f4f44822-5703-4556-8a79-c7327572d952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40860
2410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.408602410
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.982734568
Short name T2292
Test name
Test status
Simulation time 49566952 ps
CPU time 0.71 seconds
Started Aug 17 06:02:45 PM PDT 24
Finished Aug 17 06:02:45 PM PDT 24
Peak memory 207460 kb
Host smart-74511962-45b2-455d-bebe-9dc482d5c5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98273
4568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.982734568
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3837515202
Short name T2033
Test name
Test status
Simulation time 16580655489 ps
CPU time 40.65 seconds
Started Aug 17 06:02:44 PM PDT 24
Finished Aug 17 06:03:24 PM PDT 24
Peak memory 215988 kb
Host smart-e1eaee4e-32f7-441c-bc42-624129b887cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38375
15202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3837515202
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.393357796
Short name T2195
Test name
Test status
Simulation time 153253922 ps
CPU time 0.87 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:44 PM PDT 24
Peak memory 207424 kb
Host smart-79f50e38-668d-413f-ba86-ed023a2efaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39335
7796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.393357796
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1881198421
Short name T2644
Test name
Test status
Simulation time 206186048 ps
CPU time 0.94 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:44 PM PDT 24
Peak memory 207452 kb
Host smart-8e9cc44c-8b6b-43c0-b353-8d641e642542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
98421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1881198421
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.4082179386
Short name T2775
Test name
Test status
Simulation time 6395863834 ps
CPU time 34.2 seconds
Started Aug 17 06:02:45 PM PDT 24
Finished Aug 17 06:03:19 PM PDT 24
Peak memory 223964 kb
Host smart-d0a533b0-0bfd-415f-93d1-7f55a559f6cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082179386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.4082179386
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.1588775126
Short name T1881
Test name
Test status
Simulation time 6887665968 ps
CPU time 40.37 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 224344 kb
Host smart-5a6ac0c3-c104-41f7-96be-781eff6ef0cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1588775126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.1588775126
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.475483375
Short name T1334
Test name
Test status
Simulation time 5459072246 ps
CPU time 26.11 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 219040 kb
Host smart-0700fbdf-26d7-4bb1-a5dd-6dec4ced7003
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=475483375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.475483375
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3826333505
Short name T3460
Test name
Test status
Simulation time 180629802 ps
CPU time 0.96 seconds
Started Aug 17 06:02:46 PM PDT 24
Finished Aug 17 06:02:47 PM PDT 24
Peak memory 207400 kb
Host smart-3686f33d-0d1c-49c8-aa56-9bffb61b6d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38263
33505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3826333505
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.3818020621
Short name T3082
Test name
Test status
Simulation time 187841360 ps
CPU time 0.92 seconds
Started Aug 17 06:02:46 PM PDT 24
Finished Aug 17 06:02:47 PM PDT 24
Peak memory 207396 kb
Host smart-aa13538e-4ff2-4161-a92c-c4bdcee96607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38180
20621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.3818020621
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_resume_link_active.2944956065
Short name T1182
Test name
Test status
Simulation time 20200908525 ps
CPU time 25.41 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:03:08 PM PDT 24
Peak memory 207564 kb
Host smart-db132ceb-16b6-4888-8054-c891f7d94dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29449
56065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.2944956065
Directory /workspace/1.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.497527935
Short name T2373
Test name
Test status
Simulation time 154487090 ps
CPU time 0.88 seconds
Started Aug 17 06:02:43 PM PDT 24
Finished Aug 17 06:02:44 PM PDT 24
Peak memory 207400 kb
Host smart-49cbfe18-d44d-44df-931f-b977107759e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49752
7935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.497527935
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_full.3543496108
Short name T2836
Test name
Test status
Simulation time 248303474 ps
CPU time 1.19 seconds
Started Aug 17 06:02:41 PM PDT 24
Finished Aug 17 06:02:43 PM PDT 24
Peak memory 207444 kb
Host smart-bcbc0295-f7ba-43c6-b11a-6774b943b832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35434
96108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.3543496108
Directory /workspace/1.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2623680328
Short name T2864
Test name
Test status
Simulation time 185140615 ps
CPU time 0.89 seconds
Started Aug 17 06:02:49 PM PDT 24
Finished Aug 17 06:02:50 PM PDT 24
Peak memory 207452 kb
Host smart-02601d9e-c76d-473d-8e68-f3bd7dd6b7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26236
80328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2623680328
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1078114145
Short name T240
Test name
Test status
Simulation time 239528280 ps
CPU time 1.11 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 223288 kb
Host smart-5fae097f-2b73-484f-bc02-b021358312f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1078114145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1078114145
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.553666112
Short name T2464
Test name
Test status
Simulation time 492162678 ps
CPU time 1.7 seconds
Started Aug 17 06:02:55 PM PDT 24
Finished Aug 17 06:02:57 PM PDT 24
Peak memory 207472 kb
Host smart-879ffd1a-6c7f-43da-af85-e0b141f38b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55366
6112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.553666112
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1390087287
Short name T879
Test name
Test status
Simulation time 203784489 ps
CPU time 0.96 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 207484 kb
Host smart-e4e3f76b-4e39-44aa-b344-d383234cb678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13900
87287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1390087287
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3127302471
Short name T2656
Test name
Test status
Simulation time 150712704 ps
CPU time 0.88 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:02:52 PM PDT 24
Peak memory 207404 kb
Host smart-2895bc41-7f97-48ba-ad83-69ec5f478aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273
02471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3127302471
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.225758532
Short name T3244
Test name
Test status
Simulation time 177097172 ps
CPU time 0.88 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:02:52 PM PDT 24
Peak memory 207560 kb
Host smart-6a9c0f68-86cd-42ac-b0d0-b89da7dc5f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22575
8532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.225758532
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.4105338252
Short name T1500
Test name
Test status
Simulation time 218741685 ps
CPU time 1.07 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 207468 kb
Host smart-cbd90eb1-66ed-4d85-8897-94748b0e1209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41053
38252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.4105338252
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.87315305
Short name T1265
Test name
Test status
Simulation time 3136586756 ps
CPU time 105.87 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:04:37 PM PDT 24
Peak memory 217816 kb
Host smart-31734570-63ec-415f-8ace-509f6860003e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=87315305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.87315305
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.766099837
Short name T1743
Test name
Test status
Simulation time 188278097 ps
CPU time 0.87 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 207428 kb
Host smart-7ab39d7a-87bf-4e87-811a-54d99d26f076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76609
9837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.766099837
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.4193082168
Short name T3036
Test name
Test status
Simulation time 185721047 ps
CPU time 0.92 seconds
Started Aug 17 06:02:50 PM PDT 24
Finished Aug 17 06:02:51 PM PDT 24
Peak memory 207452 kb
Host smart-0a351ef2-69c7-4028-96ba-77b3acf0c397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41930
82168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.4193082168
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.872724010
Short name T1939
Test name
Test status
Simulation time 512442291 ps
CPU time 1.52 seconds
Started Aug 17 06:02:50 PM PDT 24
Finished Aug 17 06:02:51 PM PDT 24
Peak memory 207512 kb
Host smart-f322c54b-dff6-4a23-be62-6c4ef4dab34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87272
4010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.872724010
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.270357233
Short name T876
Test name
Test status
Simulation time 2866148482 ps
CPU time 30.18 seconds
Started Aug 17 06:02:50 PM PDT 24
Finished Aug 17 06:03:21 PM PDT 24
Peak memory 215936 kb
Host smart-60b54c56-d7cf-4701-a32b-d6f5257d4b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27035
7233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.270357233
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3940249639
Short name T107
Test name
Test status
Simulation time 3648161860 ps
CPU time 33.8 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:03:25 PM PDT 24
Peak memory 217596 kb
Host smart-345c56f7-7163-4cb1-8ab0-b3ed1b404d2b
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940249639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.3940249639
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.2082793940
Short name T1108
Test name
Test status
Simulation time 1573546615 ps
CPU time 37.5 seconds
Started Aug 17 06:02:44 PM PDT 24
Finished Aug 17 06:03:21 PM PDT 24
Peak memory 207588 kb
Host smart-ab2abc08-140c-46c3-a68f-58f6472c4f45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082793940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.2082793940
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_tx_rx_disruption.1360113805
Short name T3399
Test name
Test status
Simulation time 523972363 ps
CPU time 1.58 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:02:54 PM PDT 24
Peak memory 207476 kb
Host smart-c02b16bb-fa0d-4223-9fae-0d25c824a891
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360113805 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.usbdev_tx_rx_disruption.1360113805
Directory /workspace/1.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.4049026506
Short name T1694
Test name
Test status
Simulation time 62120221 ps
CPU time 0.71 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:04:56 PM PDT 24
Peak memory 207436 kb
Host smart-4e373346-90b6-434a-b966-4c740ed4c5d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4049026506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.4049026506
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.199522892
Short name T960
Test name
Test status
Simulation time 15556835520 ps
CPU time 22.06 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:05:12 PM PDT 24
Peak memory 215976 kb
Host smart-deebe5bb-6f32-4bc5-8332-31c4f208ba51
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=199522892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.199522892
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1074725035
Short name T1336
Test name
Test status
Simulation time 30817435653 ps
CPU time 38.16 seconds
Started Aug 17 06:04:48 PM PDT 24
Finished Aug 17 06:05:26 PM PDT 24
Peak memory 207808 kb
Host smart-09d54214-76df-4e11-abe4-655a4b173abc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074725035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.1074725035
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.4065557426
Short name T541
Test name
Test status
Simulation time 181046279 ps
CPU time 0.94 seconds
Started Aug 17 06:04:48 PM PDT 24
Finished Aug 17 06:04:49 PM PDT 24
Peak memory 207436 kb
Host smart-d322390a-d091-4373-8484-99048ab5f873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40655
57426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.4065557426
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.756212154
Short name T1524
Test name
Test status
Simulation time 167060252 ps
CPU time 0.94 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:04:51 PM PDT 24
Peak memory 207500 kb
Host smart-f2b76255-57fe-449b-ad62-676b12542c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75621
2154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.756212154
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3620542237
Short name T3363
Test name
Test status
Simulation time 489760530 ps
CPU time 1.65 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:04:51 PM PDT 24
Peak memory 207536 kb
Host smart-1b2e6fb7-de2a-4e58-8658-8fbab729b17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36205
42237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3620542237
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2846133431
Short name T1266
Test name
Test status
Simulation time 755125960 ps
CPU time 2.11 seconds
Started Aug 17 06:04:48 PM PDT 24
Finished Aug 17 06:04:51 PM PDT 24
Peak memory 207412 kb
Host smart-35049e17-b13b-4265-bbb4-9760217109f5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2846133431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2846133431
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1552489467
Short name T3151
Test name
Test status
Simulation time 31923867600 ps
CPU time 54.65 seconds
Started Aug 17 06:04:52 PM PDT 24
Finished Aug 17 06:05:47 PM PDT 24
Peak memory 207768 kb
Host smart-c1de1370-43ea-4413-b051-47a59b869e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15524
89467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1552489467
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.3040622584
Short name T1365
Test name
Test status
Simulation time 627841137 ps
CPU time 11.84 seconds
Started Aug 17 06:04:48 PM PDT 24
Finished Aug 17 06:05:00 PM PDT 24
Peak memory 207756 kb
Host smart-116bb803-99cd-465f-9382-d1d2de192696
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040622584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.3040622584
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1544075605
Short name T2245
Test name
Test status
Simulation time 635025804 ps
CPU time 1.93 seconds
Started Aug 17 06:04:52 PM PDT 24
Finished Aug 17 06:04:54 PM PDT 24
Peak memory 207508 kb
Host smart-6b40db29-ba70-48ab-a479-f1fae28c0747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15440
75605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1544075605
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.799547
Short name T1153
Test name
Test status
Simulation time 157728416 ps
CPU time 0.86 seconds
Started Aug 17 06:04:49 PM PDT 24
Finished Aug 17 06:04:50 PM PDT 24
Peak memory 207460 kb
Host smart-5c0f014c-75b9-4a6c-870d-4fcea689d01a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79954
7 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.799547
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.640590778
Short name T2041
Test name
Test status
Simulation time 64301613 ps
CPU time 0.73 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 207376 kb
Host smart-1b85bb6e-d3a5-4fb8-9213-4ef4438da808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64059
0778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.640590778
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3484708049
Short name T747
Test name
Test status
Simulation time 895470617 ps
CPU time 2.44 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:04:53 PM PDT 24
Peak memory 207784 kb
Host smart-4cf57d1c-6763-4a43-b833-9a59000a9749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34847
08049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3484708049
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.4147779541
Short name T2258
Test name
Test status
Simulation time 337979087 ps
CPU time 2.69 seconds
Started Aug 17 06:04:48 PM PDT 24
Finished Aug 17 06:04:51 PM PDT 24
Peak memory 207680 kb
Host smart-cae6730b-cbc8-4f21-a04d-ba33fe4453fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41477
79541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.4147779541
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2833576336
Short name T2008
Test name
Test status
Simulation time 241447362 ps
CPU time 1.3 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 215824 kb
Host smart-1af0aa4a-4d12-408e-b7e1-c820eeb58d10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2833576336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2833576336
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.452611135
Short name T1001
Test name
Test status
Simulation time 139970349 ps
CPU time 0.86 seconds
Started Aug 17 06:04:52 PM PDT 24
Finished Aug 17 06:04:53 PM PDT 24
Peak memory 207396 kb
Host smart-50df6590-6801-4ea8-bea9-4e499a988fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45261
1135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.452611135
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2525806946
Short name T1469
Test name
Test status
Simulation time 238889546 ps
CPU time 1.06 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 207472 kb
Host smart-04225271-af50-4ff2-b4db-e483ab2dad18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25258
06946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2525806946
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.3593075207
Short name T897
Test name
Test status
Simulation time 3930903082 ps
CPU time 44.33 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:05:35 PM PDT 24
Peak memory 224128 kb
Host smart-3bf3da69-ca87-44c6-9f03-fa3eb5ce32ca
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3593075207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.3593075207
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.697292424
Short name T2678
Test name
Test status
Simulation time 3727945951 ps
CPU time 46.03 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:05:36 PM PDT 24
Peak memory 207796 kb
Host smart-670190ac-e3c2-481e-8239-2104a52c5ef9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=697292424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.697292424
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.2727980086
Short name T623
Test name
Test status
Simulation time 201291629 ps
CPU time 0.99 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:04:51 PM PDT 24
Peak memory 207548 kb
Host smart-90b7914a-b068-4f34-bd4a-ea6fbd5c75ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27279
80086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.2727980086
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3907288261
Short name T3175
Test name
Test status
Simulation time 11439439955 ps
CPU time 14.24 seconds
Started Aug 17 06:04:52 PM PDT 24
Finished Aug 17 06:05:06 PM PDT 24
Peak memory 207764 kb
Host smart-b38f6f28-5eeb-45be-a618-8bd8336e33d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072
88261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3907288261
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1279843171
Short name T1177
Test name
Test status
Simulation time 10735184634 ps
CPU time 13.15 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:05:04 PM PDT 24
Peak memory 207752 kb
Host smart-50951a91-bc44-4beb-a2ec-4a5fc2e5c15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12798
43171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1279843171
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.276214395
Short name T1436
Test name
Test status
Simulation time 3694275417 ps
CPU time 36.8 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:05:28 PM PDT 24
Peak memory 224080 kb
Host smart-b65fa8f8-475f-4ef4-8e1c-aa10d2375625
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=276214395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.276214395
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.693846606
Short name T2773
Test name
Test status
Simulation time 3470940400 ps
CPU time 107.2 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:06:38 PM PDT 24
Peak memory 215908 kb
Host smart-ef38193a-2281-484b-ad6a-65ff3a55a793
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=693846606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.693846606
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.899107536
Short name T1357
Test name
Test status
Simulation time 281125116 ps
CPU time 1.02 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 207500 kb
Host smart-e3353e05-dfdc-4b3d-b0bc-94556f387345
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=899107536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.899107536
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.4126553202
Short name T3136
Test name
Test status
Simulation time 200542546 ps
CPU time 0.96 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:04:51 PM PDT 24
Peak memory 207464 kb
Host smart-53897b2c-0ebb-4d2f-acfc-53e02add07f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41265
53202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.4126553202
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3669330203
Short name T1812
Test name
Test status
Simulation time 3268681397 ps
CPU time 35.11 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:05:25 PM PDT 24
Peak memory 218524 kb
Host smart-dc618be7-8203-414e-a50c-63ddd5f1cf64
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3669330203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3669330203
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2608021927
Short name T1703
Test name
Test status
Simulation time 3104685405 ps
CPU time 30.74 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 215880 kb
Host smart-83bba6f0-7a88-4be7-998b-a6789848ead5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2608021927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2608021927
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.777311526
Short name T1834
Test name
Test status
Simulation time 171166717 ps
CPU time 0.98 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:04:51 PM PDT 24
Peak memory 207468 kb
Host smart-be5beae7-24c8-45c9-85dc-658bd7c21a77
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=777311526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.777311526
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.343359655
Short name T999
Test name
Test status
Simulation time 157912201 ps
CPU time 0.86 seconds
Started Aug 17 06:04:49 PM PDT 24
Finished Aug 17 06:04:50 PM PDT 24
Peak memory 207452 kb
Host smart-16f9e6f0-34e0-4a43-a6a7-9ab699915f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34335
9655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.343359655
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1221515103
Short name T2118
Test name
Test status
Simulation time 171665004 ps
CPU time 0.91 seconds
Started Aug 17 06:04:58 PM PDT 24
Finished Aug 17 06:04:59 PM PDT 24
Peak memory 207460 kb
Host smart-55e022a7-75cd-4d50-978c-efd1c93460aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12215
15103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1221515103
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3806859273
Short name T3423
Test name
Test status
Simulation time 179510917 ps
CPU time 0.89 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:04:57 PM PDT 24
Peak memory 207540 kb
Host smart-a8f0cc80-92ac-4ff5-a049-c4aed7cd8f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38068
59273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3806859273
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3830883048
Short name T935
Test name
Test status
Simulation time 177569814 ps
CPU time 0.92 seconds
Started Aug 17 06:04:57 PM PDT 24
Finished Aug 17 06:04:58 PM PDT 24
Peak memory 207424 kb
Host smart-a6aaf3f9-7bce-4efc-a8cf-6a4b46ac6a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38308
83048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3830883048
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3379732036
Short name T3099
Test name
Test status
Simulation time 182974959 ps
CPU time 0.87 seconds
Started Aug 17 06:05:01 PM PDT 24
Finished Aug 17 06:05:02 PM PDT 24
Peak memory 207532 kb
Host smart-23010483-3de2-4f6f-b695-a573f8ff61fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33797
32036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3379732036
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.405303613
Short name T2265
Test name
Test status
Simulation time 213171973 ps
CPU time 1.02 seconds
Started Aug 17 06:04:59 PM PDT 24
Finished Aug 17 06:05:00 PM PDT 24
Peak memory 207552 kb
Host smart-442e1fa3-42e2-437d-a3cc-bf58b862cafa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=405303613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.405303613
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3582586879
Short name T1026
Test name
Test status
Simulation time 150330215 ps
CPU time 0.85 seconds
Started Aug 17 06:05:00 PM PDT 24
Finished Aug 17 06:05:00 PM PDT 24
Peak memory 207456 kb
Host smart-2b179388-af51-498e-a555-4705847458a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35825
86879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3582586879
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1700417751
Short name T2872
Test name
Test status
Simulation time 77582587 ps
CPU time 0.75 seconds
Started Aug 17 06:04:57 PM PDT 24
Finished Aug 17 06:04:58 PM PDT 24
Peak memory 207520 kb
Host smart-b92ececb-c1de-43de-8166-89ed099fd28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17004
17751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1700417751
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3300056953
Short name T3249
Test name
Test status
Simulation time 22884705206 ps
CPU time 58.82 seconds
Started Aug 17 06:05:00 PM PDT 24
Finished Aug 17 06:05:59 PM PDT 24
Peak memory 215960 kb
Host smart-7c29480f-d022-4781-bb31-d180c4522a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33000
56953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3300056953
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1669608077
Short name T1241
Test name
Test status
Simulation time 175741124 ps
CPU time 0.9 seconds
Started Aug 17 06:04:59 PM PDT 24
Finished Aug 17 06:05:00 PM PDT 24
Peak memory 207548 kb
Host smart-52428d6c-e612-40d9-ab33-b43f0e59343f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16696
08077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1669608077
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.395026216
Short name T42
Test name
Test status
Simulation time 177502226 ps
CPU time 0.87 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:04:57 PM PDT 24
Peak memory 207468 kb
Host smart-7097198e-0efd-4df5-b11c-86ff63c6bf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39502
6216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.395026216
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3507922356
Short name T3277
Test name
Test status
Simulation time 188028760 ps
CPU time 0.94 seconds
Started Aug 17 06:04:57 PM PDT 24
Finished Aug 17 06:04:58 PM PDT 24
Peak memory 207352 kb
Host smart-d9f92bdb-8eec-4a79-bc7a-e4e8d1ffeed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35079
22356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3507922356
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1882604596
Short name T2995
Test name
Test status
Simulation time 159146821 ps
CPU time 0.87 seconds
Started Aug 17 06:04:57 PM PDT 24
Finished Aug 17 06:04:58 PM PDT 24
Peak memory 207476 kb
Host smart-469435ab-608c-4b45-a594-5817d2b7b4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18826
04596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1882604596
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_resume_link_active.3066703388
Short name T1846
Test name
Test status
Simulation time 20187746916 ps
CPU time 27.39 seconds
Started Aug 17 06:04:59 PM PDT 24
Finished Aug 17 06:05:26 PM PDT 24
Peak memory 207592 kb
Host smart-49cd8b26-1977-4601-8ba9-2ab54cbfedce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30667
03388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.3066703388
Directory /workspace/10.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.420985341
Short name T719
Test name
Test status
Simulation time 186615576 ps
CPU time 0.91 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:04:57 PM PDT 24
Peak memory 207384 kb
Host smart-232a4ab3-34ef-4d94-853c-f9780ee38e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42098
5341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.420985341
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_rx_full.3909866216
Short name T3542
Test name
Test status
Simulation time 399113155 ps
CPU time 1.33 seconds
Started Aug 17 06:04:59 PM PDT 24
Finished Aug 17 06:05:00 PM PDT 24
Peak memory 207464 kb
Host smart-099c8c79-630b-417f-b2c2-596fa6d4d278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39098
66216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.3909866216
Directory /workspace/10.usbdev_rx_full/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2073190944
Short name T1089
Test name
Test status
Simulation time 142126025 ps
CPU time 0.84 seconds
Started Aug 17 06:04:57 PM PDT 24
Finished Aug 17 06:04:58 PM PDT 24
Peak memory 207520 kb
Host smart-e83faa9a-9912-47a1-8348-d4d758822f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20731
90944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2073190944
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1321053173
Short name T667
Test name
Test status
Simulation time 152554023 ps
CPU time 0.89 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:04:57 PM PDT 24
Peak memory 207488 kb
Host smart-fdda9fa1-5e4d-4e4c-a1a5-4c0778645526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13210
53173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1321053173
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2218673393
Short name T3226
Test name
Test status
Simulation time 210716234 ps
CPU time 0.98 seconds
Started Aug 17 06:04:59 PM PDT 24
Finished Aug 17 06:05:00 PM PDT 24
Peak memory 207480 kb
Host smart-fdaeec41-78e2-43aa-a355-11361e162713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22186
73393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2218673393
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.1580039767
Short name T193
Test name
Test status
Simulation time 3296707648 ps
CPU time 34.85 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:05:31 PM PDT 24
Peak memory 215832 kb
Host smart-b15741f7-be89-40de-878b-abc718369cd0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1580039767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.1580039767
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1678474977
Short name T1405
Test name
Test status
Simulation time 190569761 ps
CPU time 0.88 seconds
Started Aug 17 06:05:02 PM PDT 24
Finished Aug 17 06:05:03 PM PDT 24
Peak memory 207532 kb
Host smart-abd844be-6985-485b-889d-58c6bc9f352f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16784
74977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1678474977
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.4270531613
Short name T1527
Test name
Test status
Simulation time 661214866 ps
CPU time 1.97 seconds
Started Aug 17 06:04:58 PM PDT 24
Finished Aug 17 06:05:01 PM PDT 24
Peak memory 207536 kb
Host smart-19606dce-745c-405d-9e06-5c59299ea599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42705
31613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.4270531613
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1045850232
Short name T988
Test name
Test status
Simulation time 3401093307 ps
CPU time 40.25 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 217700 kb
Host smart-16c963fe-bce8-4c12-bf5a-7f7f231bde4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458
50232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1045850232
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.3001282726
Short name T3614
Test name
Test status
Simulation time 1108900346 ps
CPU time 9.86 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:05:02 PM PDT 24
Peak memory 207592 kb
Host smart-3ed1428f-971e-4df6-b94a-e27a9a5223e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001282726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.3001282726
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_tx_rx_disruption.1128616931
Short name T1453
Test name
Test status
Simulation time 537701283 ps
CPU time 1.68 seconds
Started Aug 17 06:04:59 PM PDT 24
Finished Aug 17 06:05:01 PM PDT 24
Peak memory 207564 kb
Host smart-eba4ac48-c057-4131-8c2c-11c61b9dfbe1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128616931 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.usbdev_tx_rx_disruption.1128616931
Directory /workspace/10.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/100.usbdev_endpoint_types.1598811645
Short name T494
Test name
Test status
Simulation time 158494657 ps
CPU time 0.88 seconds
Started Aug 17 06:11:40 PM PDT 24
Finished Aug 17 06:11:41 PM PDT 24
Peak memory 207528 kb
Host smart-785b3af6-f7a6-4b46-b9e7-ae2678f56b17
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1598811645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.1598811645
Directory /workspace/100.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/100.usbdev_tx_rx_disruption.3388119195
Short name T1024
Test name
Test status
Simulation time 449372197 ps
CPU time 1.38 seconds
Started Aug 17 06:11:48 PM PDT 24
Finished Aug 17 06:11:49 PM PDT 24
Peak memory 207496 kb
Host smart-750d949a-a5b0-46df-a280-98471eb45295
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388119195 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.usbdev_tx_rx_disruption.3388119195
Directory /workspace/100.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/101.usbdev_tx_rx_disruption.2404375495
Short name T3473
Test name
Test status
Simulation time 480522382 ps
CPU time 1.58 seconds
Started Aug 17 06:11:36 PM PDT 24
Finished Aug 17 06:11:38 PM PDT 24
Peak memory 207568 kb
Host smart-4db37103-1596-4435-afd1-a9369897d832
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404375495 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.usbdev_tx_rx_disruption.2404375495
Directory /workspace/101.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/102.usbdev_endpoint_types.106573905
Short name T461
Test name
Test status
Simulation time 477749556 ps
CPU time 1.3 seconds
Started Aug 17 06:11:29 PM PDT 24
Finished Aug 17 06:11:30 PM PDT 24
Peak memory 207452 kb
Host smart-4543d53a-9d6a-430c-bd63-daf9408c68d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=106573905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.106573905
Directory /workspace/102.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/102.usbdev_tx_rx_disruption.3024197121
Short name T3353
Test name
Test status
Simulation time 779711170 ps
CPU time 1.86 seconds
Started Aug 17 06:11:22 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207444 kb
Host smart-83d05011-a725-4e16-b398-0957155fff60
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024197121 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.usbdev_tx_rx_disruption.3024197121
Directory /workspace/102.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/103.usbdev_endpoint_types.3066861968
Short name T479
Test name
Test status
Simulation time 604296961 ps
CPU time 1.69 seconds
Started Aug 17 06:11:29 PM PDT 24
Finished Aug 17 06:11:31 PM PDT 24
Peak memory 207528 kb
Host smart-ff462a55-4af7-467c-aff7-34688cfa5795
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3066861968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.3066861968
Directory /workspace/103.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/103.usbdev_tx_rx_disruption.1610957781
Short name T124
Test name
Test status
Simulation time 469498109 ps
CPU time 1.41 seconds
Started Aug 17 06:11:21 PM PDT 24
Finished Aug 17 06:11:23 PM PDT 24
Peak memory 207540 kb
Host smart-d040551f-db0e-463e-92d9-ec9c8dcc441d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610957781 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.usbdev_tx_rx_disruption.1610957781
Directory /workspace/103.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/104.usbdev_endpoint_types.1717070856
Short name T510
Test name
Test status
Simulation time 183761632 ps
CPU time 0.97 seconds
Started Aug 17 06:11:33 PM PDT 24
Finished Aug 17 06:11:34 PM PDT 24
Peak memory 207512 kb
Host smart-275df192-acc7-4264-a341-8ed13d17b2bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1717070856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.1717070856
Directory /workspace/104.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/104.usbdev_tx_rx_disruption.1722789695
Short name T1158
Test name
Test status
Simulation time 559379283 ps
CPU time 1.78 seconds
Started Aug 17 06:11:28 PM PDT 24
Finished Aug 17 06:11:30 PM PDT 24
Peak memory 207564 kb
Host smart-6656f830-334e-497b-9862-9124c6f8560b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722789695 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.usbdev_tx_rx_disruption.1722789695
Directory /workspace/104.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/105.usbdev_endpoint_types.1640571813
Short name T369
Test name
Test status
Simulation time 185601112 ps
CPU time 0.94 seconds
Started Aug 17 06:11:48 PM PDT 24
Finished Aug 17 06:11:49 PM PDT 24
Peak memory 207524 kb
Host smart-f6c22cc3-0f8b-461d-9524-f747bd4c443f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1640571813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.1640571813
Directory /workspace/105.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/105.usbdev_tx_rx_disruption.623590635
Short name T2441
Test name
Test status
Simulation time 601375206 ps
CPU time 1.6 seconds
Started Aug 17 06:11:28 PM PDT 24
Finished Aug 17 06:11:29 PM PDT 24
Peak memory 207580 kb
Host smart-9c8c3e78-777f-426f-83dc-e59ab143aabe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623590635 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 105.usbdev_tx_rx_disruption.623590635
Directory /workspace/105.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/106.usbdev_tx_rx_disruption.2813170121
Short name T1686
Test name
Test status
Simulation time 600968093 ps
CPU time 1.62 seconds
Started Aug 17 06:11:31 PM PDT 24
Finished Aug 17 06:11:32 PM PDT 24
Peak memory 207540 kb
Host smart-fa20b41c-c3ba-48c0-a8f8-1e3a16f406f0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813170121 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.usbdev_tx_rx_disruption.2813170121
Directory /workspace/106.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/107.usbdev_tx_rx_disruption.1085906758
Short name T2757
Test name
Test status
Simulation time 632866961 ps
CPU time 1.65 seconds
Started Aug 17 06:11:28 PM PDT 24
Finished Aug 17 06:11:29 PM PDT 24
Peak memory 207560 kb
Host smart-83573ae8-4e36-4a1e-853d-bc7a4125c97a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085906758 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.usbdev_tx_rx_disruption.1085906758
Directory /workspace/107.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/108.usbdev_endpoint_types.3253100096
Short name T434
Test name
Test status
Simulation time 708735067 ps
CPU time 1.68 seconds
Started Aug 17 06:11:28 PM PDT 24
Finished Aug 17 06:11:29 PM PDT 24
Peak memory 207568 kb
Host smart-8a67b0d7-473d-4fd9-9a64-4f91e2dd47fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3253100096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.3253100096
Directory /workspace/108.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/108.usbdev_tx_rx_disruption.618644692
Short name T2841
Test name
Test status
Simulation time 478126530 ps
CPU time 1.6 seconds
Started Aug 17 06:11:30 PM PDT 24
Finished Aug 17 06:11:32 PM PDT 24
Peak memory 207512 kb
Host smart-62d37ed5-a8ea-4c9c-81b6-ac4ecc0776fe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618644692 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 108.usbdev_tx_rx_disruption.618644692
Directory /workspace/108.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/109.usbdev_endpoint_types.3979951166
Short name T420
Test name
Test status
Simulation time 351426375 ps
CPU time 1.16 seconds
Started Aug 17 06:11:31 PM PDT 24
Finished Aug 17 06:11:32 PM PDT 24
Peak memory 207528 kb
Host smart-7756d356-20ae-404e-a882-78c0d9ed23f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3979951166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.3979951166
Directory /workspace/109.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/109.usbdev_tx_rx_disruption.3591214368
Short name T1472
Test name
Test status
Simulation time 488390906 ps
CPU time 1.51 seconds
Started Aug 17 06:11:41 PM PDT 24
Finished Aug 17 06:11:43 PM PDT 24
Peak memory 207548 kb
Host smart-e5762d2b-6dfc-4e02-bb97-29ceff234cd4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591214368 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.usbdev_tx_rx_disruption.3591214368
Directory /workspace/109.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3034957966
Short name T1190
Test name
Test status
Simulation time 6735171926 ps
CPU time 10.81 seconds
Started Aug 17 06:04:55 PM PDT 24
Finished Aug 17 06:05:06 PM PDT 24
Peak memory 216000 kb
Host smart-c4946874-6175-457a-ad8a-33122a4387c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034957966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.3034957966
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.4267613621
Short name T3221
Test name
Test status
Simulation time 19302831305 ps
CPU time 22.32 seconds
Started Aug 17 06:04:58 PM PDT 24
Finished Aug 17 06:05:20 PM PDT 24
Peak memory 207800 kb
Host smart-40db62d8-6f54-4ad0-afbe-413630b08b16
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267613621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.4267613621
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3265928460
Short name T1973
Test name
Test status
Simulation time 24192235940 ps
CPU time 33.18 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:05:29 PM PDT 24
Peak memory 215992 kb
Host smart-33facbca-4a6d-4f6a-9445-0ba3c10c0169
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265928460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.3265928460
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2701664632
Short name T3293
Test name
Test status
Simulation time 204507066 ps
CPU time 0.98 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:04:57 PM PDT 24
Peak memory 207480 kb
Host smart-1f17592b-956d-4a8c-8cc9-e217dfb35465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27016
64632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2701664632
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2253028537
Short name T801
Test name
Test status
Simulation time 144036678 ps
CPU time 0.89 seconds
Started Aug 17 06:05:00 PM PDT 24
Finished Aug 17 06:05:01 PM PDT 24
Peak memory 207544 kb
Host smart-d04620f3-c30a-402c-895d-6955928a191e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22530
28537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2253028537
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.340942549
Short name T3410
Test name
Test status
Simulation time 406563325 ps
CPU time 1.62 seconds
Started Aug 17 06:05:02 PM PDT 24
Finished Aug 17 06:05:03 PM PDT 24
Peak memory 207532 kb
Host smart-ff234079-836c-4727-b9e8-4f012a96faf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34094
2549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.340942549
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1452739582
Short name T334
Test name
Test status
Simulation time 626558979 ps
CPU time 1.9 seconds
Started Aug 17 06:05:02 PM PDT 24
Finished Aug 17 06:05:04 PM PDT 24
Peak memory 207448 kb
Host smart-9f3ea7ea-2e98-4831-afe1-fa3ac54e0462
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1452739582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1452739582
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1795700040
Short name T1904
Test name
Test status
Simulation time 13163227650 ps
CPU time 22.93 seconds
Started Aug 17 06:05:00 PM PDT 24
Finished Aug 17 06:05:23 PM PDT 24
Peak memory 207772 kb
Host smart-764e12b0-9c0a-42b3-a2db-436f87581424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17957
00040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1795700040
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.723605670
Short name T1544
Test name
Test status
Simulation time 1217568404 ps
CPU time 27.92 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:05:24 PM PDT 24
Peak memory 207724 kb
Host smart-671dba07-65dd-46b4-93cf-a5d5bb6803b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723605670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.723605670
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.155014037
Short name T2795
Test name
Test status
Simulation time 587176359 ps
CPU time 1.56 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:05:09 PM PDT 24
Peak memory 207504 kb
Host smart-7e68c998-85f9-434a-8a42-42ff9bd451a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15501
4037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.155014037
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1756371269
Short name T3486
Test name
Test status
Simulation time 201005454 ps
CPU time 0.91 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207464 kb
Host smart-db5091f8-3ea4-429a-80c1-9f7b3a3bd44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17563
71269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1756371269
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2258754241
Short name T1561
Test name
Test status
Simulation time 61844600 ps
CPU time 0.71 seconds
Started Aug 17 06:05:08 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207456 kb
Host smart-8714b6d8-fd32-4e8b-98a8-f5f4b977d359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22587
54241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2258754241
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3616894679
Short name T660
Test name
Test status
Simulation time 902189166 ps
CPU time 2.19 seconds
Started Aug 17 06:05:05 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207684 kb
Host smart-2239c881-24df-4aa9-b92f-c9004d52c94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36168
94679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3616894679
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_types.1114749044
Short name T499
Test name
Test status
Simulation time 491204269 ps
CPU time 1.32 seconds
Started Aug 17 06:05:04 PM PDT 24
Finished Aug 17 06:05:06 PM PDT 24
Peak memory 207472 kb
Host smart-27b1e370-72d6-45f0-9ffe-65454eab6b72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1114749044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.1114749044
Directory /workspace/11.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3460558079
Short name T1046
Test name
Test status
Simulation time 202660940 ps
CPU time 1.65 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207600 kb
Host smart-a044d321-63f0-4857-bc4a-d1c329432c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34605
58079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3460558079
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1371165163
Short name T915
Test name
Test status
Simulation time 241610714 ps
CPU time 1.11 seconds
Started Aug 17 06:05:12 PM PDT 24
Finished Aug 17 06:05:13 PM PDT 24
Peak memory 215852 kb
Host smart-58b4c798-9ba7-4e38-8e41-23f81debebd3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1371165163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1371165163
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2182764525
Short name T122
Test name
Test status
Simulation time 210921327 ps
CPU time 1 seconds
Started Aug 17 06:05:04 PM PDT 24
Finished Aug 17 06:05:05 PM PDT 24
Peak memory 207420 kb
Host smart-c2e793b9-1dc2-4952-bafc-e957bd46b2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21827
64525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2182764525
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3391947912
Short name T843
Test name
Test status
Simulation time 233808590 ps
CPU time 1.05 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207456 kb
Host smart-d9666bd2-a8b8-4ed3-a997-bbb9cb3937de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33919
47912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3391947912
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1551609751
Short name T2369
Test name
Test status
Simulation time 4314301314 ps
CPU time 126.81 seconds
Started Aug 17 06:05:04 PM PDT 24
Finished Aug 17 06:07:11 PM PDT 24
Peak memory 218304 kb
Host smart-fa71908d-4e78-4e0c-8b7d-dc520fced26e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1551609751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1551609751
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.963323214
Short name T1534
Test name
Test status
Simulation time 11669175997 ps
CPU time 152.22 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:07:39 PM PDT 24
Peak memory 207748 kb
Host smart-bcef46df-4813-4138-80c2-c86333e11032
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=963323214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.963323214
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1150498082
Short name T1889
Test name
Test status
Simulation time 226802122 ps
CPU time 0.97 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207496 kb
Host smart-260bebb1-ac19-483d-b225-b7419f4a146c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
98082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1150498082
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3138145192
Short name T2913
Test name
Test status
Simulation time 7612778114 ps
CPU time 11.72 seconds
Started Aug 17 06:05:04 PM PDT 24
Finished Aug 17 06:05:16 PM PDT 24
Peak memory 207784 kb
Host smart-68a36c3c-3a25-4801-90d8-ff0d3e193000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31381
45192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3138145192
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1020609850
Short name T3089
Test name
Test status
Simulation time 5442155743 ps
CPU time 8.17 seconds
Started Aug 17 06:05:04 PM PDT 24
Finished Aug 17 06:05:12 PM PDT 24
Peak memory 215972 kb
Host smart-5548ea8d-dd9d-4217-9e2a-0ec0060e6042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10206
09850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1020609850
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2193645967
Short name T3115
Test name
Test status
Simulation time 4611503165 ps
CPU time 43.01 seconds
Started Aug 17 06:05:05 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 224068 kb
Host smart-697aa7d1-be00-4fde-a63d-4962e3fdcee2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2193645967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2193645967
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.4230574274
Short name T2039
Test name
Test status
Simulation time 2904571638 ps
CPU time 81.52 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:06:33 PM PDT 24
Peak memory 217256 kb
Host smart-1d728855-9833-49a3-8d6a-42684fefa9a2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4230574274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.4230574274
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.3271718540
Short name T1803
Test name
Test status
Simulation time 274021810 ps
CPU time 1.05 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207340 kb
Host smart-18e65978-4c0d-4985-8d6b-3e88cb8c6e8f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3271718540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.3271718540
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1635829346
Short name T962
Test name
Test status
Simulation time 190207777 ps
CPU time 0.91 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:05:09 PM PDT 24
Peak memory 207424 kb
Host smart-02bca396-1f62-485f-bc8c-7724d7d1c1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16358
29346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1635829346
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.3711199346
Short name T973
Test name
Test status
Simulation time 3468224283 ps
CPU time 101.45 seconds
Started Aug 17 06:05:05 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 217672 kb
Host smart-e61f25b9-5610-45a7-8f0e-c575df96a8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37111
99346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.3711199346
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1337653782
Short name T1375
Test name
Test status
Simulation time 2972538004 ps
CPU time 33.72 seconds
Started Aug 17 06:05:03 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 224136 kb
Host smart-57990c38-94ae-4df8-828c-a862ea410557
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1337653782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1337653782
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3621191122
Short name T2141
Test name
Test status
Simulation time 2669582702 ps
CPU time 29.75 seconds
Started Aug 17 06:05:10 PM PDT 24
Finished Aug 17 06:05:40 PM PDT 24
Peak memory 216792 kb
Host smart-e50e1a15-0749-4d62-8e02-f7afafa87c51
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3621191122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3621191122
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.271529647
Short name T1313
Test name
Test status
Simulation time 182682791 ps
CPU time 0.89 seconds
Started Aug 17 06:05:04 PM PDT 24
Finished Aug 17 06:05:05 PM PDT 24
Peak memory 207456 kb
Host smart-3e667ff2-214c-4366-aeb3-3b316cad9393
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=271529647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.271529647
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2297394968
Short name T3610
Test name
Test status
Simulation time 161898241 ps
CPU time 0.86 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207484 kb
Host smart-e9ed27c9-60b2-4638-9403-34f7add6628f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22973
94968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2297394968
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.357044909
Short name T3314
Test name
Test status
Simulation time 181502887 ps
CPU time 0.92 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207352 kb
Host smart-3987be40-0b00-4b68-bf6e-3cd0fb94bb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35704
4909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.357044909
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2882518759
Short name T1795
Test name
Test status
Simulation time 200646971 ps
CPU time 1 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207400 kb
Host smart-d970c890-30ff-4cb5-ad28-79efcc9f17a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28825
18759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2882518759
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4135230612
Short name T2777
Test name
Test status
Simulation time 162026200 ps
CPU time 0.92 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207504 kb
Host smart-a7981383-4bca-4252-8158-e7393279e9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41352
30612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4135230612
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2161069944
Short name T2985
Test name
Test status
Simulation time 178404173 ps
CPU time 0.95 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207540 kb
Host smart-4a1adc49-f2ca-48fd-95d5-68c973a22a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21610
69944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2161069944
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.786584078
Short name T3426
Test name
Test status
Simulation time 234040105 ps
CPU time 1.03 seconds
Started Aug 17 06:05:05 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207500 kb
Host smart-7c050566-204e-46ee-9256-abb8b9b8c3a7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=786584078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.786584078
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2217678583
Short name T3083
Test name
Test status
Simulation time 164992450 ps
CPU time 0.85 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207444 kb
Host smart-0c2bf094-9d29-4371-a801-fd781f344e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22176
78583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2217678583
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1770450507
Short name T3407
Test name
Test status
Simulation time 64755947 ps
CPU time 0.74 seconds
Started Aug 17 06:05:04 PM PDT 24
Finished Aug 17 06:05:04 PM PDT 24
Peak memory 207500 kb
Host smart-70331332-d55c-4754-b375-6c1a0db3b996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17704
50507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1770450507
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2510595749
Short name T1924
Test name
Test status
Simulation time 10670669320 ps
CPU time 26.63 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:33 PM PDT 24
Peak memory 215944 kb
Host smart-d0e7069e-5739-49ef-94b1-21f1d8a13bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25105
95749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2510595749
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.311351234
Short name T3469
Test name
Test status
Simulation time 222010470 ps
CPU time 0.99 seconds
Started Aug 17 06:05:03 PM PDT 24
Finished Aug 17 06:05:04 PM PDT 24
Peak memory 207440 kb
Host smart-f7e6f3d8-3bc7-4f78-87c9-991ef7f78e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31135
1234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.311351234
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.385625418
Short name T3041
Test name
Test status
Simulation time 162114123 ps
CPU time 0.87 seconds
Started Aug 17 06:05:04 PM PDT 24
Finished Aug 17 06:05:05 PM PDT 24
Peak memory 207472 kb
Host smart-c7d3dad9-0150-4c57-8565-0a1dd89f3a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38562
5418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.385625418
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2036477967
Short name T3097
Test name
Test status
Simulation time 185039159 ps
CPU time 0.99 seconds
Started Aug 17 06:05:04 PM PDT 24
Finished Aug 17 06:05:05 PM PDT 24
Peak memory 207472 kb
Host smart-33242a73-c266-4956-b16c-19c5ae14b1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20364
77967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2036477967
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_resume_link_active.709278143
Short name T1054
Test name
Test status
Simulation time 20165383819 ps
CPU time 26.54 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:32 PM PDT 24
Peak memory 207508 kb
Host smart-66d9e910-330a-4d5d-823a-153a8ad01468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70927
8143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.709278143
Directory /workspace/11.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3771232644
Short name T1113
Test name
Test status
Simulation time 181955007 ps
CPU time 0.89 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207488 kb
Host smart-87f65b18-d325-4edf-9381-f4af334054e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37712
32644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3771232644
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_rx_full.1909269669
Short name T1071
Test name
Test status
Simulation time 342032499 ps
CPU time 1.25 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207396 kb
Host smart-1e4ba3d7-a8c9-4c81-bbce-aed23cb266d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19092
69669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.1909269669
Directory /workspace/11.usbdev_rx_full/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3961917753
Short name T1872
Test name
Test status
Simulation time 155158500 ps
CPU time 0.89 seconds
Started Aug 17 06:05:08 PM PDT 24
Finished Aug 17 06:05:09 PM PDT 24
Peak memory 207532 kb
Host smart-5e7c00f2-a23b-4fa9-9dfe-f08a47c634b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39619
17753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3961917753
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3259359562
Short name T586
Test name
Test status
Simulation time 148372596 ps
CPU time 0.87 seconds
Started Aug 17 06:05:08 PM PDT 24
Finished Aug 17 06:05:09 PM PDT 24
Peak memory 207476 kb
Host smart-c376f002-a1c3-4fe0-95c9-bbdf714c793c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32593
59562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3259359562
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.842340303
Short name T2627
Test name
Test status
Simulation time 224826997 ps
CPU time 1 seconds
Started Aug 17 06:05:12 PM PDT 24
Finished Aug 17 06:05:13 PM PDT 24
Peak memory 207464 kb
Host smart-7a85cfaa-9bee-495f-ae06-7db019d7fe4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84234
0303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.842340303
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.543987986
Short name T1314
Test name
Test status
Simulation time 3361755830 ps
CPU time 100.18 seconds
Started Aug 17 06:05:07 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 223956 kb
Host smart-c0244eff-8ba8-430e-92ae-02d0db3f5693
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=543987986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.543987986
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3585501076
Short name T3520
Test name
Test status
Simulation time 176329329 ps
CPU time 0.99 seconds
Started Aug 17 06:05:06 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207488 kb
Host smart-59c83696-2b6a-4f49-a71e-6af0661d4f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35855
01076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3585501076
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3223730250
Short name T948
Test name
Test status
Simulation time 198514316 ps
CPU time 0.98 seconds
Started Aug 17 06:05:20 PM PDT 24
Finished Aug 17 06:05:21 PM PDT 24
Peak memory 207552 kb
Host smart-f8f22259-a30b-42b9-b319-7d5de3b6faea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32237
30250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3223730250
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.4075719003
Short name T1687
Test name
Test status
Simulation time 1120490428 ps
CPU time 2.78 seconds
Started Aug 17 06:05:16 PM PDT 24
Finished Aug 17 06:05:19 PM PDT 24
Peak memory 207728 kb
Host smart-093c3e22-b336-4a2b-8bd7-d2fbeb1b4726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40757
19003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.4075719003
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.344975084
Short name T1029
Test name
Test status
Simulation time 2877381597 ps
CPU time 82.22 seconds
Started Aug 17 06:05:15 PM PDT 24
Finished Aug 17 06:06:37 PM PDT 24
Peak memory 215908 kb
Host smart-d6c796a5-4ca5-4497-b48f-a81266397c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34497
5084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.344975084
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.3519477439
Short name T2517
Test name
Test status
Simulation time 431528469 ps
CPU time 8.19 seconds
Started Aug 17 06:04:56 PM PDT 24
Finished Aug 17 06:05:05 PM PDT 24
Peak memory 207568 kb
Host smart-7657dbff-46fc-4b8a-82ef-86e822fb7ed3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519477439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.3519477439
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_tx_rx_disruption.2379021373
Short name T1838
Test name
Test status
Simulation time 678249805 ps
CPU time 1.81 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:15 PM PDT 24
Peak memory 207552 kb
Host smart-823932b5-22dc-4ed2-9ea3-7f302ec52a4f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379021373 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.usbdev_tx_rx_disruption.2379021373
Directory /workspace/11.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/110.usbdev_endpoint_types.1017032649
Short name T2569
Test name
Test status
Simulation time 232334838 ps
CPU time 1.09 seconds
Started Aug 17 06:11:30 PM PDT 24
Finished Aug 17 06:11:31 PM PDT 24
Peak memory 207564 kb
Host smart-928ecc4f-e2b4-4dcb-a7fb-ae6fb07f46a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1017032649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.1017032649
Directory /workspace/110.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/110.usbdev_tx_rx_disruption.1153539212
Short name T1087
Test name
Test status
Simulation time 434491428 ps
CPU time 1.41 seconds
Started Aug 17 06:11:25 PM PDT 24
Finished Aug 17 06:11:27 PM PDT 24
Peak memory 207508 kb
Host smart-ec19e68d-dbab-4762-a186-be5b4abfb0b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153539212 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.usbdev_tx_rx_disruption.1153539212
Directory /workspace/110.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/111.usbdev_endpoint_types.1942361834
Short name T432
Test name
Test status
Simulation time 674229392 ps
CPU time 1.68 seconds
Started Aug 17 06:11:29 PM PDT 24
Finished Aug 17 06:11:31 PM PDT 24
Peak memory 207528 kb
Host smart-fc0ccb75-4339-47c5-83fc-955ff84260c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1942361834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.1942361834
Directory /workspace/111.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/111.usbdev_tx_rx_disruption.2226323943
Short name T2120
Test name
Test status
Simulation time 493085302 ps
CPU time 1.55 seconds
Started Aug 17 06:11:36 PM PDT 24
Finished Aug 17 06:11:38 PM PDT 24
Peak memory 207580 kb
Host smart-f8f23eb4-966d-4794-ad72-a5f6d7b6d954
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226323943 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.usbdev_tx_rx_disruption.2226323943
Directory /workspace/111.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/112.usbdev_tx_rx_disruption.1058785887
Short name T729
Test name
Test status
Simulation time 603909208 ps
CPU time 1.91 seconds
Started Aug 17 06:11:45 PM PDT 24
Finished Aug 17 06:11:47 PM PDT 24
Peak memory 207568 kb
Host smart-43d5550b-260e-4fa3-9786-df5a123beda4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058785887 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.usbdev_tx_rx_disruption.1058785887
Directory /workspace/112.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/113.usbdev_endpoint_types.421786843
Short name T457
Test name
Test status
Simulation time 277010447 ps
CPU time 1.03 seconds
Started Aug 17 06:11:34 PM PDT 24
Finished Aug 17 06:11:35 PM PDT 24
Peak memory 207524 kb
Host smart-9a1601e3-17f7-4f54-89d1-e4c4f22860ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=421786843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.421786843
Directory /workspace/113.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/113.usbdev_tx_rx_disruption.3494498749
Short name T2029
Test name
Test status
Simulation time 488517187 ps
CPU time 1.66 seconds
Started Aug 17 06:11:41 PM PDT 24
Finished Aug 17 06:11:42 PM PDT 24
Peak memory 207484 kb
Host smart-6a9d89d9-db14-4a9b-8299-fdc9dfe5482c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494498749 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.usbdev_tx_rx_disruption.3494498749
Directory /workspace/113.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/114.usbdev_endpoint_types.1345689621
Short name T3478
Test name
Test status
Simulation time 477281229 ps
CPU time 1.46 seconds
Started Aug 17 06:11:31 PM PDT 24
Finished Aug 17 06:11:33 PM PDT 24
Peak memory 207500 kb
Host smart-c6365946-0c82-4d70-ade4-2da886211d70
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1345689621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.1345689621
Directory /workspace/114.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/114.usbdev_tx_rx_disruption.3824281815
Short name T3611
Test name
Test status
Simulation time 532594824 ps
CPU time 1.61 seconds
Started Aug 17 06:11:37 PM PDT 24
Finished Aug 17 06:11:39 PM PDT 24
Peak memory 207484 kb
Host smart-a9143430-3216-45d1-a903-95aab0ed798d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824281815 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.usbdev_tx_rx_disruption.3824281815
Directory /workspace/114.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/115.usbdev_endpoint_types.1961432617
Short name T426
Test name
Test status
Simulation time 415235306 ps
CPU time 1.29 seconds
Started Aug 17 06:11:28 PM PDT 24
Finished Aug 17 06:11:34 PM PDT 24
Peak memory 206444 kb
Host smart-cfa75a09-8197-49b1-92cd-8983e36834c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1961432617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.1961432617
Directory /workspace/115.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/115.usbdev_tx_rx_disruption.1263009306
Short name T796
Test name
Test status
Simulation time 483704645 ps
CPU time 1.55 seconds
Started Aug 17 06:11:29 PM PDT 24
Finished Aug 17 06:11:30 PM PDT 24
Peak memory 207544 kb
Host smart-40a80981-e88d-4487-b4be-dea474239150
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263009306 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.usbdev_tx_rx_disruption.1263009306
Directory /workspace/115.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/116.usbdev_tx_rx_disruption.4148941200
Short name T2140
Test name
Test status
Simulation time 592760536 ps
CPU time 1.74 seconds
Started Aug 17 06:11:58 PM PDT 24
Finished Aug 17 06:12:00 PM PDT 24
Peak memory 207548 kb
Host smart-d91b11ea-3fc5-44f6-93a9-1e394218b1d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148941200 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.usbdev_tx_rx_disruption.4148941200
Directory /workspace/116.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/117.usbdev_endpoint_types.2303737876
Short name T2974
Test name
Test status
Simulation time 144807154 ps
CPU time 0.86 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:43 PM PDT 24
Peak memory 207496 kb
Host smart-1933740d-a999-46d2-97b6-1793f52e60b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2303737876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.2303737876
Directory /workspace/117.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/117.usbdev_tx_rx_disruption.247527189
Short name T2200
Test name
Test status
Simulation time 605596018 ps
CPU time 1.64 seconds
Started Aug 17 06:11:21 PM PDT 24
Finished Aug 17 06:11:22 PM PDT 24
Peak memory 207540 kb
Host smart-991c3c4a-931b-42fb-a806-d25d4306e85f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247527189 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 117.usbdev_tx_rx_disruption.247527189
Directory /workspace/117.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/118.usbdev_endpoint_types.945753681
Short name T3231
Test name
Test status
Simulation time 360791323 ps
CPU time 1.18 seconds
Started Aug 17 06:11:37 PM PDT 24
Finished Aug 17 06:11:38 PM PDT 24
Peak memory 207456 kb
Host smart-6f47d330-420d-427a-a25b-c5cda3bf054a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=945753681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.945753681
Directory /workspace/118.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/118.usbdev_tx_rx_disruption.4289334109
Short name T1224
Test name
Test status
Simulation time 498732843 ps
CPU time 1.57 seconds
Started Aug 17 06:11:31 PM PDT 24
Finished Aug 17 06:11:33 PM PDT 24
Peak memory 207488 kb
Host smart-fd58d240-47c5-48ef-b38f-dc4dc71f5666
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289334109 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.usbdev_tx_rx_disruption.4289334109
Directory /workspace/118.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/119.usbdev_endpoint_types.3423433738
Short name T3352
Test name
Test status
Simulation time 251506508 ps
CPU time 0.95 seconds
Started Aug 17 06:11:31 PM PDT 24
Finished Aug 17 06:11:32 PM PDT 24
Peak memory 207520 kb
Host smart-b91365aa-a132-47d8-a2d2-cd903db1191d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3423433738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.3423433738
Directory /workspace/119.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/119.usbdev_tx_rx_disruption.4212807215
Short name T206
Test name
Test status
Simulation time 473416250 ps
CPU time 1.54 seconds
Started Aug 17 06:11:50 PM PDT 24
Finished Aug 17 06:11:52 PM PDT 24
Peak memory 207504 kb
Host smart-7b4c2349-de20-4c6e-ab7e-632f5ea47fdf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212807215 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.usbdev_tx_rx_disruption.4212807215
Directory /workspace/119.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.3277056986
Short name T1432
Test name
Test status
Simulation time 42482313 ps
CPU time 0.71 seconds
Started Aug 17 06:05:21 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 207452 kb
Host smart-7cf753df-05b2-4761-bb4b-99305bd904ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3277056986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.3277056986
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.905588487
Short name T3223
Test name
Test status
Simulation time 11842771619 ps
CPU time 16.78 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:30 PM PDT 24
Peak memory 207756 kb
Host smart-1a002b78-929d-4bb8-8afe-8c6518167454
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905588487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_disconnect.905588487
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2474217047
Short name T3632
Test name
Test status
Simulation time 15155223501 ps
CPU time 17.06 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:30 PM PDT 24
Peak memory 215968 kb
Host smart-a78214b4-7a25-4997-a153-f2a151412b90
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474217047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2474217047
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.3066250547
Short name T3432
Test name
Test status
Simulation time 24076467339 ps
CPU time 32.36 seconds
Started Aug 17 06:05:16 PM PDT 24
Finished Aug 17 06:05:48 PM PDT 24
Peak memory 216000 kb
Host smart-92e8879c-00ae-4600-9000-846740aa63e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066250547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.3066250547
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2583246446
Short name T619
Test name
Test status
Simulation time 153705938 ps
CPU time 0.88 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:14 PM PDT 24
Peak memory 207460 kb
Host smart-f0605150-fcdf-4b23-ae34-7b0041e800c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25832
46446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2583246446
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1323382690
Short name T1197
Test name
Test status
Simulation time 192761554 ps
CPU time 0.9 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:14 PM PDT 24
Peak memory 207540 kb
Host smart-d2a07fe3-e682-4124-965b-ddbbd2943b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13233
82690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1323382690
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.4118565594
Short name T2139
Test name
Test status
Simulation time 230248473 ps
CPU time 1.03 seconds
Started Aug 17 06:05:18 PM PDT 24
Finished Aug 17 06:05:19 PM PDT 24
Peak memory 207552 kb
Host smart-0c312cb4-547c-407e-a3a8-9d3d05810d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41185
65594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.4118565594
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2324394673
Short name T3392
Test name
Test status
Simulation time 991863904 ps
CPU time 2.76 seconds
Started Aug 17 06:05:12 PM PDT 24
Finished Aug 17 06:05:15 PM PDT 24
Peak memory 207612 kb
Host smart-dd22e71d-e1bf-4a82-89cc-744e9d6fb7fa
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2324394673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2324394673
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.473281574
Short name T1657
Test name
Test status
Simulation time 34291061784 ps
CPU time 59.66 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:06:10 PM PDT 24
Peak memory 207764 kb
Host smart-ea53b2cf-e584-43a3-9179-aa178f7c3f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47328
1574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.473281574
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.3822960570
Short name T557
Test name
Test status
Simulation time 1544535742 ps
CPU time 13.8 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:05:25 PM PDT 24
Peak memory 207608 kb
Host smart-1b05ed48-a20b-4d00-ac5e-10d46b8e37b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822960570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.3822960570
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3955156344
Short name T1342
Test name
Test status
Simulation time 545184287 ps
CPU time 1.48 seconds
Started Aug 17 06:05:19 PM PDT 24
Finished Aug 17 06:05:21 PM PDT 24
Peak memory 207520 kb
Host smart-db4e8ed9-4bc1-45f5-ad35-dacbe7b043ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39551
56344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3955156344
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3997707865
Short name T3521
Test name
Test status
Simulation time 156284538 ps
CPU time 0.86 seconds
Started Aug 17 06:05:15 PM PDT 24
Finished Aug 17 06:05:16 PM PDT 24
Peak memory 207500 kb
Host smart-3fa091f3-f6a3-436d-8cef-5a2fbff39552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39977
07865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3997707865
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3705393633
Short name T533
Test name
Test status
Simulation time 45054163 ps
CPU time 0.76 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:05:12 PM PDT 24
Peak memory 207332 kb
Host smart-7630db81-f338-4431-ad9d-eade3d43c88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37053
93633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3705393633
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2274378491
Short name T1513
Test name
Test status
Simulation time 903796477 ps
CPU time 2.39 seconds
Started Aug 17 06:05:18 PM PDT 24
Finished Aug 17 06:05:21 PM PDT 24
Peak memory 207788 kb
Host smart-400a1a2f-effd-483e-bf24-281f1ce7092f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22743
78491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2274378491
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_types.3213945835
Short name T389
Test name
Test status
Simulation time 612108641 ps
CPU time 1.56 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:05:13 PM PDT 24
Peak memory 207512 kb
Host smart-87d91f36-ba56-4987-8bdd-915c5b46cd73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3213945835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.3213945835
Directory /workspace/12.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3344636165
Short name T1414
Test name
Test status
Simulation time 166924090 ps
CPU time 0.94 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:05:12 PM PDT 24
Peak memory 206400 kb
Host smart-2b37e7fe-a702-4974-8fe4-ef908aee4598
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3344636165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3344636165
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1896345470
Short name T1198
Test name
Test status
Simulation time 149700801 ps
CPU time 0.9 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:14 PM PDT 24
Peak memory 207464 kb
Host smart-09779daa-787b-4de0-bb9e-bed8bb10a621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18963
45470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1896345470
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3128162953
Short name T2818
Test name
Test status
Simulation time 210227862 ps
CPU time 0.97 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:05:12 PM PDT 24
Peak memory 207464 kb
Host smart-ed8aed50-7aa2-475e-b0f4-99bdb51005b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31281
62953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3128162953
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1471401288
Short name T2091
Test name
Test status
Simulation time 2349107996 ps
CPU time 27.02 seconds
Started Aug 17 06:05:18 PM PDT 24
Finished Aug 17 06:05:45 PM PDT 24
Peak memory 218500 kb
Host smart-7e718871-c951-4f85-b782-fcf65969e328
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1471401288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1471401288
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.3056788743
Short name T2143
Test name
Test status
Simulation time 13430741984 ps
CPU time 102.58 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:06:54 PM PDT 24
Peak memory 207780 kb
Host smart-b0585d38-05fd-424a-9829-183b15d35969
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3056788743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.3056788743
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3380883070
Short name T3449
Test name
Test status
Simulation time 256688805 ps
CPU time 1.16 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:05:12 PM PDT 24
Peak memory 207492 kb
Host smart-7c0254e9-5e01-4b86-8d56-6741ddee8637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33808
83070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3380883070
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.856885079
Short name T1608
Test name
Test status
Simulation time 30992561538 ps
CPU time 51.27 seconds
Started Aug 17 06:05:12 PM PDT 24
Finished Aug 17 06:06:03 PM PDT 24
Peak memory 207776 kb
Host smart-93c2d720-20d2-4455-b0f6-33ea97e943be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85688
5079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.856885079
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3871264878
Short name T1586
Test name
Test status
Simulation time 4411480631 ps
CPU time 6.69 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:19 PM PDT 24
Peak memory 207768 kb
Host smart-03cf8792-af18-4ca5-9693-6aa7f0fac59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
64878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3871264878
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2144762778
Short name T1823
Test name
Test status
Simulation time 3621351632 ps
CPU time 32.66 seconds
Started Aug 17 06:05:17 PM PDT 24
Finished Aug 17 06:05:50 PM PDT 24
Peak memory 224132 kb
Host smart-bf150e08-9bba-4dd7-8c4c-3e0bae8285b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2144762778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2144762778
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.4057238278
Short name T3579
Test name
Test status
Simulation time 2519519525 ps
CPU time 25.56 seconds
Started Aug 17 06:05:18 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 217548 kb
Host smart-3014dc17-d072-4841-b7aa-d93a6b24ecfa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4057238278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.4057238278
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.190779512
Short name T2208
Test name
Test status
Simulation time 240757285 ps
CPU time 0.99 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:14 PM PDT 24
Peak memory 207492 kb
Host smart-6d0535bf-789f-4b78-8722-bfb980958c4a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=190779512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.190779512
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1775206432
Short name T556
Test name
Test status
Simulation time 213332444 ps
CPU time 1.02 seconds
Started Aug 17 06:05:15 PM PDT 24
Finished Aug 17 06:05:16 PM PDT 24
Peak memory 207412 kb
Host smart-e49cc9e5-418d-4146-8be4-b4eb1361d183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17752
06432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1775206432
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.2108875230
Short name T1208
Test name
Test status
Simulation time 2789535478 ps
CPU time 24.36 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:05:36 PM PDT 24
Peak memory 217828 kb
Host smart-d0aded71-43ab-45d9-8e4c-528f1003db35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21088
75230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.2108875230
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2955404213
Short name T1672
Test name
Test status
Simulation time 1957865629 ps
CPU time 22.1 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:05:33 PM PDT 24
Peak memory 224084 kb
Host smart-d6ad3f21-3ce9-4a29-8e1c-935208c8f1dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2955404213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2955404213
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1719342209
Short name T618
Test name
Test status
Simulation time 1951617807 ps
CPU time 56.6 seconds
Started Aug 17 06:05:12 PM PDT 24
Finished Aug 17 06:06:08 PM PDT 24
Peak memory 217240 kb
Host smart-3f07e5ef-7460-4edc-ab9e-5d268d963a5b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1719342209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1719342209
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.1250796276
Short name T1540
Test name
Test status
Simulation time 205112663 ps
CPU time 0.92 seconds
Started Aug 17 06:05:11 PM PDT 24
Finished Aug 17 06:05:12 PM PDT 24
Peak memory 207424 kb
Host smart-ade0160b-33fd-4837-a247-a0ece6e50197
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1250796276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.1250796276
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.628834460
Short name T1556
Test name
Test status
Simulation time 165305546 ps
CPU time 0.9 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:14 PM PDT 24
Peak memory 207468 kb
Host smart-824c6272-732f-4f50-abe4-a37c5a83a064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62883
4460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.628834460
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.1825038364
Short name T2591
Test name
Test status
Simulation time 183259726 ps
CPU time 0.92 seconds
Started Aug 17 06:05:20 PM PDT 24
Finished Aug 17 06:05:21 PM PDT 24
Peak memory 207460 kb
Host smart-85c3e37f-e297-4113-9e77-d57e5d868fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18250
38364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.1825038364
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2669653447
Short name T1480
Test name
Test status
Simulation time 194162422 ps
CPU time 0.99 seconds
Started Aug 17 06:05:21 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 207412 kb
Host smart-e20dd332-554a-4369-8553-415937ccbc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
53447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2669653447
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.829183967
Short name T1940
Test name
Test status
Simulation time 194610668 ps
CPU time 0.97 seconds
Started Aug 17 06:05:21 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 207544 kb
Host smart-62db64fe-0d11-4705-8d25-b29449967698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82918
3967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.829183967
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1105447748
Short name T1212
Test name
Test status
Simulation time 148646086 ps
CPU time 0.9 seconds
Started Aug 17 06:05:22 PM PDT 24
Finished Aug 17 06:05:23 PM PDT 24
Peak memory 207548 kb
Host smart-af08bda2-4a0b-42a5-958b-3848ce31573d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11054
47748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1105447748
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3254493071
Short name T3588
Test name
Test status
Simulation time 200940839 ps
CPU time 0.96 seconds
Started Aug 17 06:05:19 PM PDT 24
Finished Aug 17 06:05:20 PM PDT 24
Peak memory 207556 kb
Host smart-6a380435-8650-49be-9b52-bf110a4af891
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3254493071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3254493071
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1462694622
Short name T1528
Test name
Test status
Simulation time 157185691 ps
CPU time 0.87 seconds
Started Aug 17 06:05:22 PM PDT 24
Finished Aug 17 06:05:23 PM PDT 24
Peak memory 207424 kb
Host smart-dfa97fc6-487f-49d5-9c19-261e2d4d76bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14626
94622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1462694622
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.130871498
Short name T2158
Test name
Test status
Simulation time 47052868 ps
CPU time 0.72 seconds
Started Aug 17 06:05:21 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 207516 kb
Host smart-3e6205db-41e6-46e6-aea2-9b79de7e2709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13087
1498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.130871498
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3469847414
Short name T2490
Test name
Test status
Simulation time 10773121677 ps
CPU time 28.45 seconds
Started Aug 17 06:05:22 PM PDT 24
Finished Aug 17 06:05:50 PM PDT 24
Peak memory 215880 kb
Host smart-f94517de-e92b-45cc-a26f-a140af1a9fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34698
47414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3469847414
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1820224379
Short name T1184
Test name
Test status
Simulation time 227428149 ps
CPU time 0.98 seconds
Started Aug 17 06:05:20 PM PDT 24
Finished Aug 17 06:05:21 PM PDT 24
Peak memory 207592 kb
Host smart-46ead570-fb9d-4d6f-8508-694b7192a7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18202
24379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1820224379
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3918881103
Short name T3571
Test name
Test status
Simulation time 184474309 ps
CPU time 0.91 seconds
Started Aug 17 06:05:17 PM PDT 24
Finished Aug 17 06:05:18 PM PDT 24
Peak memory 207432 kb
Host smart-3f41bbcc-ab2c-42d9-99ff-a47c113c7383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39188
81103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3918881103
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.2619264929
Short name T1780
Test name
Test status
Simulation time 171973773 ps
CPU time 0.89 seconds
Started Aug 17 06:05:21 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 207456 kb
Host smart-b30a9e11-8491-44f6-8278-6061388efee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26192
64929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2619264929
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2222802878
Short name T1568
Test name
Test status
Simulation time 173790270 ps
CPU time 0.89 seconds
Started Aug 17 06:05:21 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 207440 kb
Host smart-d6b020e7-c9e3-45c0-b6ba-bffad02956a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22228
02878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2222802878
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_resume_link_active.2587298261
Short name T3218
Test name
Test status
Simulation time 20160695844 ps
CPU time 25.27 seconds
Started Aug 17 06:05:19 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 207600 kb
Host smart-6a07cf0a-6ba7-4a56-9aad-1bb395ae9770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25872
98261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.2587298261
Directory /workspace/12.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/12.usbdev_rx_full.1458340443
Short name T327
Test name
Test status
Simulation time 301589866 ps
CPU time 1.12 seconds
Started Aug 17 06:05:20 PM PDT 24
Finished Aug 17 06:05:21 PM PDT 24
Peak memory 207452 kb
Host smart-196eb20b-f2ea-470b-9ce7-71b05728f59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14583
40443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.1458340443
Directory /workspace/12.usbdev_rx_full/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.304308241
Short name T3567
Test name
Test status
Simulation time 146733160 ps
CPU time 0.84 seconds
Started Aug 17 06:05:23 PM PDT 24
Finished Aug 17 06:05:24 PM PDT 24
Peak memory 207444 kb
Host smart-adef2390-3a9c-47eb-9456-9bd39bb5da9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30430
8241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.304308241
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2841857909
Short name T2346
Test name
Test status
Simulation time 148352037 ps
CPU time 0.87 seconds
Started Aug 17 06:05:19 PM PDT 24
Finished Aug 17 06:05:20 PM PDT 24
Peak memory 207460 kb
Host smart-2dc6feaf-7580-4572-a950-e64d86aba5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28418
57909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2841857909
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2918084381
Short name T1696
Test name
Test status
Simulation time 243384643 ps
CPU time 1.1 seconds
Started Aug 17 06:05:21 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 207392 kb
Host smart-e61b2697-25e4-4ad9-b514-6f0621d8abe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29180
84381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2918084381
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.17271513
Short name T2456
Test name
Test status
Simulation time 1651876380 ps
CPU time 12.08 seconds
Started Aug 17 06:05:19 PM PDT 24
Finished Aug 17 06:05:31 PM PDT 24
Peak memory 217592 kb
Host smart-1bb1b206-914d-41d3-b20f-c965def0dcd4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=17271513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.17271513
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3034581181
Short name T1231
Test name
Test status
Simulation time 177488156 ps
CPU time 0.91 seconds
Started Aug 17 06:05:20 PM PDT 24
Finished Aug 17 06:05:21 PM PDT 24
Peak memory 207500 kb
Host smart-2d0d4822-541e-47e2-862f-d82ee31bc597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30345
81181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3034581181
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3536937194
Short name T1776
Test name
Test status
Simulation time 522445434 ps
CPU time 1.59 seconds
Started Aug 17 06:05:22 PM PDT 24
Finished Aug 17 06:05:24 PM PDT 24
Peak memory 207456 kb
Host smart-11cc0908-a1b0-40dd-a858-20dc603ac373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35369
37194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3536937194
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3768845154
Short name T1381
Test name
Test status
Simulation time 3071344771 ps
CPU time 30.19 seconds
Started Aug 17 06:05:22 PM PDT 24
Finished Aug 17 06:05:52 PM PDT 24
Peak memory 217284 kb
Host smart-55a238e4-c68b-4914-8d1e-3b325fa6bf04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37688
45154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3768845154
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.2012832072
Short name T2949
Test name
Test status
Simulation time 1445987421 ps
CPU time 33.98 seconds
Started Aug 17 06:05:13 PM PDT 24
Finished Aug 17 06:05:47 PM PDT 24
Peak memory 207644 kb
Host smart-4a2b0245-a78a-4f14-8698-2b2cb8ec52e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012832072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.2012832072
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_tx_rx_disruption.4122408657
Short name T977
Test name
Test status
Simulation time 467739577 ps
CPU time 1.61 seconds
Started Aug 17 06:05:19 PM PDT 24
Finished Aug 17 06:05:20 PM PDT 24
Peak memory 207560 kb
Host smart-5904ec10-fe3c-4b04-a36e-53b4f9916b8f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122408657 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.usbdev_tx_rx_disruption.4122408657
Directory /workspace/12.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/120.usbdev_endpoint_types.3986447457
Short name T817
Test name
Test status
Simulation time 217592368 ps
CPU time 0.95 seconds
Started Aug 17 06:11:30 PM PDT 24
Finished Aug 17 06:11:31 PM PDT 24
Peak memory 207512 kb
Host smart-c17d1a34-2bce-4bfd-869c-5c39c04261af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3986447457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.3986447457
Directory /workspace/120.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/120.usbdev_tx_rx_disruption.3731416312
Short name T1580
Test name
Test status
Simulation time 467692194 ps
CPU time 1.51 seconds
Started Aug 17 06:11:27 PM PDT 24
Finished Aug 17 06:11:29 PM PDT 24
Peak memory 207556 kb
Host smart-791a2f2e-41bb-4b66-bf2c-cab9e11b5a36
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731416312 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.usbdev_tx_rx_disruption.3731416312
Directory /workspace/120.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/121.usbdev_endpoint_types.3815164938
Short name T416
Test name
Test status
Simulation time 756344916 ps
CPU time 1.9 seconds
Started Aug 17 06:11:46 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207444 kb
Host smart-2d12d5a8-5511-45ba-ad07-2863be7062e1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3815164938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.3815164938
Directory /workspace/121.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/121.usbdev_tx_rx_disruption.2302044940
Short name T2487
Test name
Test status
Simulation time 619755993 ps
CPU time 1.66 seconds
Started Aug 17 06:11:34 PM PDT 24
Finished Aug 17 06:11:36 PM PDT 24
Peak memory 207544 kb
Host smart-a45e7647-f55a-43c9-828e-726f6916ae0a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302044940 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.usbdev_tx_rx_disruption.2302044940
Directory /workspace/121.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/122.usbdev_endpoint_types.2171988856
Short name T3232
Test name
Test status
Simulation time 219227112 ps
CPU time 0.93 seconds
Started Aug 17 06:11:26 PM PDT 24
Finished Aug 17 06:11:27 PM PDT 24
Peak memory 207496 kb
Host smart-de948bf2-544e-4222-bc03-12bed0398996
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2171988856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.2171988856
Directory /workspace/122.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/122.usbdev_tx_rx_disruption.1046539692
Short name T2534
Test name
Test status
Simulation time 520990119 ps
CPU time 1.57 seconds
Started Aug 17 06:11:23 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207516 kb
Host smart-7a366da8-e0ab-4468-b51b-51aadaf36322
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046539692 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.usbdev_tx_rx_disruption.1046539692
Directory /workspace/122.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/123.usbdev_endpoint_types.961695260
Short name T452
Test name
Test status
Simulation time 372804106 ps
CPU time 1.18 seconds
Started Aug 17 06:11:23 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 207468 kb
Host smart-9bfedb09-34ce-4d57-9b7d-67bf45ff1d25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=961695260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.961695260
Directory /workspace/123.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/123.usbdev_tx_rx_disruption.3340789628
Short name T742
Test name
Test status
Simulation time 639033160 ps
CPU time 1.71 seconds
Started Aug 17 06:11:31 PM PDT 24
Finished Aug 17 06:11:33 PM PDT 24
Peak memory 207536 kb
Host smart-9fbd048b-b688-45fc-8b89-a811bad87634
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340789628 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.usbdev_tx_rx_disruption.3340789628
Directory /workspace/123.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/124.usbdev_tx_rx_disruption.856426144
Short name T200
Test name
Test status
Simulation time 465428081 ps
CPU time 1.53 seconds
Started Aug 17 06:11:22 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207552 kb
Host smart-ae9b839b-920c-4165-991e-ebb1bd39887c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856426144 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 124.usbdev_tx_rx_disruption.856426144
Directory /workspace/124.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/125.usbdev_endpoint_types.2934298194
Short name T3532
Test name
Test status
Simulation time 196505586 ps
CPU time 0.93 seconds
Started Aug 17 06:11:32 PM PDT 24
Finished Aug 17 06:11:33 PM PDT 24
Peak memory 207492 kb
Host smart-91e97204-02f5-4d95-bd0e-d5b86de39be4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2934298194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.2934298194
Directory /workspace/125.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/125.usbdev_tx_rx_disruption.3167888528
Short name T1589
Test name
Test status
Simulation time 442729598 ps
CPU time 1.41 seconds
Started Aug 17 06:11:26 PM PDT 24
Finished Aug 17 06:11:27 PM PDT 24
Peak memory 207556 kb
Host smart-3bc971b9-e762-4796-9430-cac72f6c132a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167888528 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.usbdev_tx_rx_disruption.3167888528
Directory /workspace/125.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/126.usbdev_endpoint_types.2314239034
Short name T2090
Test name
Test status
Simulation time 257646155 ps
CPU time 1.1 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 207504 kb
Host smart-85644d52-245e-4020-a552-683d3a6278e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2314239034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.2314239034
Directory /workspace/126.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/126.usbdev_tx_rx_disruption.1959719153
Short name T3084
Test name
Test status
Simulation time 536328578 ps
CPU time 1.71 seconds
Started Aug 17 06:11:30 PM PDT 24
Finished Aug 17 06:11:32 PM PDT 24
Peak memory 207540 kb
Host smart-05f63555-8bd1-4b7c-942e-656dcf4b354f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959719153 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.usbdev_tx_rx_disruption.1959719153
Directory /workspace/126.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/127.usbdev_endpoint_types.780895231
Short name T2062
Test name
Test status
Simulation time 256464985 ps
CPU time 0.97 seconds
Started Aug 17 06:11:53 PM PDT 24
Finished Aug 17 06:11:54 PM PDT 24
Peak memory 207512 kb
Host smart-7174cda2-78c7-47bb-8e6a-74eb7e5d8dbc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=780895231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.780895231
Directory /workspace/127.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/127.usbdev_tx_rx_disruption.461152508
Short name T1765
Test name
Test status
Simulation time 539451432 ps
CPU time 1.66 seconds
Started Aug 17 06:11:30 PM PDT 24
Finished Aug 17 06:11:32 PM PDT 24
Peak memory 207560 kb
Host smart-afbaa260-f998-4859-9aa3-6bde957a9e14
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461152508 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 127.usbdev_tx_rx_disruption.461152508
Directory /workspace/127.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/128.usbdev_tx_rx_disruption.3339187180
Short name T2338
Test name
Test status
Simulation time 544237323 ps
CPU time 1.61 seconds
Started Aug 17 06:11:33 PM PDT 24
Finished Aug 17 06:11:34 PM PDT 24
Peak memory 207536 kb
Host smart-02a8a833-00fb-4145-8043-f36e81bff0bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339187180 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.usbdev_tx_rx_disruption.3339187180
Directory /workspace/128.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/129.usbdev_endpoint_types.1919370548
Short name T2513
Test name
Test status
Simulation time 185689549 ps
CPU time 0.9 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207464 kb
Host smart-89139765-7452-444e-88e6-d26bb31f2db4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1919370548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.1919370548
Directory /workspace/129.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/129.usbdev_tx_rx_disruption.4164252259
Short name T1887
Test name
Test status
Simulation time 441312715 ps
CPU time 1.49 seconds
Started Aug 17 06:11:58 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207520 kb
Host smart-db705425-5db5-459e-9590-9b1da37dec0f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164252259 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.usbdev_tx_rx_disruption.4164252259
Directory /workspace/129.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.208024621
Short name T2555
Test name
Test status
Simulation time 39584707 ps
CPU time 0.68 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207420 kb
Host smart-a7e276ea-9b8a-4ea7-96fa-e9f9125c0223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=208024621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.208024621
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3196355290
Short name T2074
Test name
Test status
Simulation time 5660903389 ps
CPU time 8.73 seconds
Started Aug 17 06:05:22 PM PDT 24
Finished Aug 17 06:05:31 PM PDT 24
Peak memory 215976 kb
Host smart-fcd98343-6063-4b45-9fa2-aa9521b589dd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196355290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.3196355290
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3888816357
Short name T761
Test name
Test status
Simulation time 13628232241 ps
CPU time 17.62 seconds
Started Aug 17 06:05:22 PM PDT 24
Finished Aug 17 06:05:39 PM PDT 24
Peak memory 215980 kb
Host smart-ffb77376-6adb-41fc-8ea7-1adc9cfebf91
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888816357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3888816357
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.326418857
Short name T1043
Test name
Test status
Simulation time 24320205894 ps
CPU time 30.78 seconds
Started Aug 17 06:05:19 PM PDT 24
Finished Aug 17 06:05:50 PM PDT 24
Peak memory 215996 kb
Host smart-e79c2d7d-f1f8-4849-80b1-eaa170552ed1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326418857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ao
n_wake_resume.326418857
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3623272642
Short name T2021
Test name
Test status
Simulation time 214904598 ps
CPU time 1.01 seconds
Started Aug 17 06:05:20 PM PDT 24
Finished Aug 17 06:05:21 PM PDT 24
Peak memory 207484 kb
Host smart-7d789ae8-7b9c-4c42-b303-5df1f17b6c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36232
72642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3623272642
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.676936658
Short name T3333
Test name
Test status
Simulation time 191071113 ps
CPU time 0.92 seconds
Started Aug 17 06:05:22 PM PDT 24
Finished Aug 17 06:05:23 PM PDT 24
Peak memory 207532 kb
Host smart-2052a5ec-2092-443a-b6f5-50ae268ba145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67693
6658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.676936658
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.1551363934
Short name T1341
Test name
Test status
Simulation time 408491340 ps
CPU time 1.47 seconds
Started Aug 17 06:05:18 PM PDT 24
Finished Aug 17 06:05:19 PM PDT 24
Peak memory 207532 kb
Host smart-cd360819-63e5-4ca5-957c-9356a46b7224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15513
63934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.1551363934
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3859704864
Short name T2738
Test name
Test status
Simulation time 892806647 ps
CPU time 2.57 seconds
Started Aug 17 06:05:21 PM PDT 24
Finished Aug 17 06:05:23 PM PDT 24
Peak memory 207600 kb
Host smart-9f81e11d-5689-43b4-b9dd-e2421b79cdbb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3859704864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3859704864
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.2828175410
Short name T3370
Test name
Test status
Simulation time 43638202430 ps
CPU time 67.22 seconds
Started Aug 17 06:05:23 PM PDT 24
Finished Aug 17 06:06:30 PM PDT 24
Peak memory 207760 kb
Host smart-844ecf9e-85b8-4739-90e4-3c0fea1f29ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28281
75410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.2828175410
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.4081859928
Short name T2976
Test name
Test status
Simulation time 3862717011 ps
CPU time 36.53 seconds
Started Aug 17 06:05:19 PM PDT 24
Finished Aug 17 06:05:56 PM PDT 24
Peak memory 207780 kb
Host smart-1929196c-fe9b-4fdf-b879-02680534fa54
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081859928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.4081859928
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1965447641
Short name T1411
Test name
Test status
Simulation time 512727495 ps
CPU time 1.5 seconds
Started Aug 17 06:05:22 PM PDT 24
Finished Aug 17 06:05:24 PM PDT 24
Peak memory 207500 kb
Host smart-c7c44a80-f8bd-4034-ab30-2f029e634220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19654
47641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1965447641
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1037784104
Short name T1821
Test name
Test status
Simulation time 136111125 ps
CPU time 0.83 seconds
Started Aug 17 06:05:27 PM PDT 24
Finished Aug 17 06:05:28 PM PDT 24
Peak memory 207516 kb
Host smart-9d2280d7-f5af-4bc2-82bb-c16c6b08b831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10377
84104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1037784104
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.1736387823
Short name T2278
Test name
Test status
Simulation time 37490883 ps
CPU time 0.71 seconds
Started Aug 17 06:05:26 PM PDT 24
Finished Aug 17 06:05:27 PM PDT 24
Peak memory 207420 kb
Host smart-f1efe797-a0e6-4d8d-b6e9-b0d5b178f9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17363
87823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1736387823
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.222036398
Short name T2776
Test name
Test status
Simulation time 1041528451 ps
CPU time 2.8 seconds
Started Aug 17 06:05:30 PM PDT 24
Finished Aug 17 06:05:33 PM PDT 24
Peak memory 207692 kb
Host smart-db797f15-8070-49f3-9a00-daf648189d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22203
6398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.222036398
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1658853237
Short name T785
Test name
Test status
Simulation time 248657672 ps
CPU time 1.87 seconds
Started Aug 17 06:05:27 PM PDT 24
Finished Aug 17 06:05:29 PM PDT 24
Peak memory 207592 kb
Host smart-fe2b5374-3824-44b0-8f25-78ac33625fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16588
53237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1658853237
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1202738068
Short name T2169
Test name
Test status
Simulation time 234164523 ps
CPU time 1.1 seconds
Started Aug 17 06:05:30 PM PDT 24
Finished Aug 17 06:05:32 PM PDT 24
Peak memory 215880 kb
Host smart-add8c620-bf0c-479d-ba4b-54dda376c1ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1202738068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1202738068
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1812566945
Short name T1753
Test name
Test status
Simulation time 191032917 ps
CPU time 0.91 seconds
Started Aug 17 06:05:30 PM PDT 24
Finished Aug 17 06:05:31 PM PDT 24
Peak memory 207384 kb
Host smart-9612099b-c9d1-438f-8ef7-e4ed01e1b5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18125
66945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1812566945
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1770579451
Short name T704
Test name
Test status
Simulation time 224550975 ps
CPU time 1.02 seconds
Started Aug 17 06:05:28 PM PDT 24
Finished Aug 17 06:05:30 PM PDT 24
Peak memory 207416 kb
Host smart-e65b9850-6316-456c-b2a9-25c00e184e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17705
79451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1770579451
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3735190074
Short name T2488
Test name
Test status
Simulation time 4013348725 ps
CPU time 124.7 seconds
Started Aug 17 06:05:27 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 217900 kb
Host smart-940f446d-8bd8-4789-8eec-5f4bf9396643
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3735190074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3735190074
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.492282506
Short name T1262
Test name
Test status
Simulation time 5124786052 ps
CPU time 33.36 seconds
Started Aug 17 06:05:27 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207772 kb
Host smart-cbc7e1ce-332c-41a8-a5af-574a3dd3b4d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=492282506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.492282506
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3710205282
Short name T2474
Test name
Test status
Simulation time 259031443 ps
CPU time 1.04 seconds
Started Aug 17 06:05:31 PM PDT 24
Finished Aug 17 06:05:32 PM PDT 24
Peak memory 207476 kb
Host smart-27ffb89f-3d8b-4088-93b8-7750ddc33644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
05282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3710205282
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2147822571
Short name T3060
Test name
Test status
Simulation time 32535102536 ps
CPU time 50.41 seconds
Started Aug 17 06:05:31 PM PDT 24
Finished Aug 17 06:06:21 PM PDT 24
Peak memory 207768 kb
Host smart-c55979a8-a2e4-4252-bca5-982defbbcf68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21478
22571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2147822571
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3828981888
Short name T2088
Test name
Test status
Simulation time 10509462736 ps
CPU time 13.98 seconds
Started Aug 17 06:05:29 PM PDT 24
Finished Aug 17 06:05:43 PM PDT 24
Peak memory 207800 kb
Host smart-e2a9e087-8f1e-405e-b6bf-95dcc5a6d069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38289
81888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3828981888
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2108770806
Short name T1988
Test name
Test status
Simulation time 5067850598 ps
CPU time 42.83 seconds
Started Aug 17 06:05:31 PM PDT 24
Finished Aug 17 06:06:14 PM PDT 24
Peak memory 224156 kb
Host smart-f277fa09-b8b8-45da-abe4-16814d45378f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2108770806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2108770806
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.2225603389
Short name T1865
Test name
Test status
Simulation time 1838290286 ps
CPU time 14.74 seconds
Started Aug 17 06:05:32 PM PDT 24
Finished Aug 17 06:05:46 PM PDT 24
Peak memory 207636 kb
Host smart-f93bf073-344f-4cc3-a5db-b03c6daeb322
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2225603389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.2225603389
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2734565471
Short name T346
Test name
Test status
Simulation time 261038488 ps
CPU time 1 seconds
Started Aug 17 06:05:31 PM PDT 24
Finished Aug 17 06:05:32 PM PDT 24
Peak memory 207488 kb
Host smart-8ec4275a-f753-461c-9c66-1f160fdc3f42
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2734565471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2734565471
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.497564860
Short name T1578
Test name
Test status
Simulation time 244915977 ps
CPU time 0.99 seconds
Started Aug 17 06:05:27 PM PDT 24
Finished Aug 17 06:05:28 PM PDT 24
Peak memory 207424 kb
Host smart-99d26fda-c60a-48d1-8b28-84623b07e7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49756
4860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.497564860
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.2392568181
Short name T1537
Test name
Test status
Simulation time 2532688860 ps
CPU time 73.83 seconds
Started Aug 17 06:05:27 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 217456 kb
Host smart-1a730ed4-47b5-4d66-a17d-79c11f4d0f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23925
68181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.2392568181
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.773346349
Short name T1675
Test name
Test status
Simulation time 2167565207 ps
CPU time 71.9 seconds
Started Aug 17 06:05:27 PM PDT 24
Finished Aug 17 06:06:39 PM PDT 24
Peak memory 217860 kb
Host smart-079544f7-09da-4138-8b8d-5a5cf9b143df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=773346349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.773346349
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.888685693
Short name T631
Test name
Test status
Simulation time 3612776239 ps
CPU time 35.5 seconds
Started Aug 17 06:05:31 PM PDT 24
Finished Aug 17 06:06:07 PM PDT 24
Peak memory 216012 kb
Host smart-33d19891-86db-4dc2-bce0-09e063674f6f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=888685693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.888685693
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.962699639
Short name T3427
Test name
Test status
Simulation time 152072623 ps
CPU time 0.87 seconds
Started Aug 17 06:05:29 PM PDT 24
Finished Aug 17 06:05:30 PM PDT 24
Peak memory 207464 kb
Host smart-b861613e-d0a4-462f-ba3a-3b904ea85714
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=962699639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.962699639
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.449641571
Short name T2013
Test name
Test status
Simulation time 218917788 ps
CPU time 0.95 seconds
Started Aug 17 06:05:31 PM PDT 24
Finished Aug 17 06:05:32 PM PDT 24
Peak memory 207416 kb
Host smart-dcc0e840-8665-4eea-8f30-e15ea1376777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44964
1571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.449641571
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3595417506
Short name T150
Test name
Test status
Simulation time 206143773 ps
CPU time 0.94 seconds
Started Aug 17 06:05:31 PM PDT 24
Finished Aug 17 06:05:32 PM PDT 24
Peak memory 207476 kb
Host smart-8ab1e7c9-1e51-4da9-9609-c0fddbd1b0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35954
17506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3595417506
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.2668057890
Short name T3179
Test name
Test status
Simulation time 159232231 ps
CPU time 0.84 seconds
Started Aug 17 06:05:29 PM PDT 24
Finished Aug 17 06:05:29 PM PDT 24
Peak memory 207452 kb
Host smart-f0f59f95-2a84-4d2f-9817-966310389aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26680
57890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.2668057890
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.137617406
Short name T1921
Test name
Test status
Simulation time 206173360 ps
CPU time 0.93 seconds
Started Aug 17 06:05:30 PM PDT 24
Finished Aug 17 06:05:31 PM PDT 24
Peak memory 207464 kb
Host smart-9efb5170-68e7-47cb-92fe-bad9bf9da322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13761
7406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.137617406
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2449451260
Short name T2565
Test name
Test status
Simulation time 185392805 ps
CPU time 0.91 seconds
Started Aug 17 06:05:27 PM PDT 24
Finished Aug 17 06:05:28 PM PDT 24
Peak memory 207520 kb
Host smart-027fc2fb-0abb-45c7-bf0a-5f3bf2f31ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24494
51260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2449451260
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1428152627
Short name T1067
Test name
Test status
Simulation time 152333024 ps
CPU time 0.89 seconds
Started Aug 17 06:05:28 PM PDT 24
Finished Aug 17 06:05:28 PM PDT 24
Peak memory 207544 kb
Host smart-451668c0-5d39-471f-a754-8558715698b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14281
52627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1428152627
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2073928415
Short name T707
Test name
Test status
Simulation time 208892804 ps
CPU time 1.03 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207552 kb
Host smart-2a71df41-ae35-4c96-89e6-690ddd73b5be
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2073928415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2073928415
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2610819967
Short name T227
Test name
Test status
Simulation time 149079803 ps
CPU time 0.85 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207380 kb
Host smart-0ccf1d78-abde-41e8-b34c-9aa2ca4814d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26108
19967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2610819967
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2397305105
Short name T2749
Test name
Test status
Simulation time 50024542 ps
CPU time 0.71 seconds
Started Aug 17 06:05:37 PM PDT 24
Finished Aug 17 06:05:38 PM PDT 24
Peak memory 207512 kb
Host smart-def83be1-658d-431c-98e2-837deca647f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23973
05105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2397305105
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3032908279
Short name T2621
Test name
Test status
Simulation time 21299031048 ps
CPU time 52.75 seconds
Started Aug 17 06:05:34 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 215956 kb
Host smart-07e0a097-9437-4876-83b3-de436771cd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30329
08279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3032908279
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2380266155
Short name T2126
Test name
Test status
Simulation time 229077621 ps
CPU time 0.99 seconds
Started Aug 17 06:05:35 PM PDT 24
Finished Aug 17 06:05:36 PM PDT 24
Peak memory 207564 kb
Host smart-a934eb25-0ce3-4742-bf48-700277342501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23802
66155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2380266155
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1747964408
Short name T2571
Test name
Test status
Simulation time 294604766 ps
CPU time 1.09 seconds
Started Aug 17 06:05:35 PM PDT 24
Finished Aug 17 06:05:36 PM PDT 24
Peak memory 207468 kb
Host smart-8f582b53-11ab-405c-825d-735401b5cc8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17479
64408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1747964408
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.3690772519
Short name T534
Test name
Test status
Simulation time 233995539 ps
CPU time 1.03 seconds
Started Aug 17 06:05:34 PM PDT 24
Finished Aug 17 06:05:35 PM PDT 24
Peak memory 207416 kb
Host smart-cbbc97c7-c349-47ef-8363-422ec573ae8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36907
72519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.3690772519
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2961276578
Short name T2332
Test name
Test status
Simulation time 193535020 ps
CPU time 0.93 seconds
Started Aug 17 06:05:39 PM PDT 24
Finished Aug 17 06:05:40 PM PDT 24
Peak memory 207432 kb
Host smart-becbd96f-8aa7-4a0f-a5a9-75466e85e929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29612
76578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2961276578
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_resume_link_active.3577942542
Short name T3020
Test name
Test status
Simulation time 20160626704 ps
CPU time 22.82 seconds
Started Aug 17 06:05:35 PM PDT 24
Finished Aug 17 06:05:58 PM PDT 24
Peak memory 207500 kb
Host smart-9291c7ca-e4ce-47fc-a468-ae605d73e7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35779
42542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.3577942542
Directory /workspace/13.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.4209306184
Short name T1771
Test name
Test status
Simulation time 134923300 ps
CPU time 0.85 seconds
Started Aug 17 06:05:38 PM PDT 24
Finished Aug 17 06:05:39 PM PDT 24
Peak memory 207440 kb
Host smart-b2f00791-c7c0-4e76-9aad-8125ff3262da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42093
06184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.4209306184
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_rx_full.2229503335
Short name T329
Test name
Test status
Simulation time 255569611 ps
CPU time 1.17 seconds
Started Aug 17 06:05:37 PM PDT 24
Finished Aug 17 06:05:38 PM PDT 24
Peak memory 207480 kb
Host smart-77dff282-0741-4fa0-ac52-2dcb98e8e4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22295
03335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.2229503335
Directory /workspace/13.usbdev_rx_full/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3945497058
Short name T2991
Test name
Test status
Simulation time 175999260 ps
CPU time 0.88 seconds
Started Aug 17 06:05:38 PM PDT 24
Finished Aug 17 06:05:39 PM PDT 24
Peak memory 207516 kb
Host smart-bda2e609-9a62-472d-9b79-7d04793e22bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
97058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3945497058
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.782916082
Short name T604
Test name
Test status
Simulation time 170243940 ps
CPU time 0.89 seconds
Started Aug 17 06:05:39 PM PDT 24
Finished Aug 17 06:05:40 PM PDT 24
Peak memory 207504 kb
Host smart-6c490aee-bf6c-4cf3-9cae-d67aab8d6c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78291
6082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.782916082
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.706117018
Short name T3482
Test name
Test status
Simulation time 202688368 ps
CPU time 1.02 seconds
Started Aug 17 06:05:38 PM PDT 24
Finished Aug 17 06:05:39 PM PDT 24
Peak memory 207448 kb
Host smart-cbdbec33-b474-42dd-a69f-585847936a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70611
7018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.706117018
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3734464264
Short name T3428
Test name
Test status
Simulation time 2115571208 ps
CPU time 17.15 seconds
Started Aug 17 06:05:35 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 223936 kb
Host smart-bf614b45-8aad-4eb8-b1cc-0e354f698a35
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3734464264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3734464264
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.86924199
Short name T3458
Test name
Test status
Simulation time 159480962 ps
CPU time 0.93 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207452 kb
Host smart-e844b7f9-f194-4bec-8460-df01899037e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86924
199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.86924199
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2545442181
Short name T1499
Test name
Test status
Simulation time 167306275 ps
CPU time 0.95 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207504 kb
Host smart-abafa299-249e-40c9-9ae6-fc0b03bc3c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25454
42181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2545442181
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.207325069
Short name T3350
Test name
Test status
Simulation time 1132289689 ps
CPU time 2.66 seconds
Started Aug 17 06:05:37 PM PDT 24
Finished Aug 17 06:05:40 PM PDT 24
Peak memory 207744 kb
Host smart-74371d25-55d5-4a16-932d-2c793b64f070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20732
5069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.207325069
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3051267242
Short name T1331
Test name
Test status
Simulation time 2075145391 ps
CPU time 17.02 seconds
Started Aug 17 06:05:34 PM PDT 24
Finished Aug 17 06:05:52 PM PDT 24
Peak memory 217480 kb
Host smart-f65c89ad-6de9-4b6d-862a-040330d11b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30512
67242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3051267242
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.1592901053
Short name T563
Test name
Test status
Simulation time 870476634 ps
CPU time 18.79 seconds
Started Aug 17 06:05:20 PM PDT 24
Finished Aug 17 06:05:39 PM PDT 24
Peak memory 207648 kb
Host smart-eab2ffb4-f838-45db-a12e-2ad9d381b02e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592901053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.1592901053
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_tx_rx_disruption.2167341772
Short name T2491
Test name
Test status
Simulation time 456625113 ps
CPU time 1.52 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:38 PM PDT 24
Peak memory 207492 kb
Host smart-49e65f5a-986c-48bb-b19e-21980810c3f6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167341772 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.usbdev_tx_rx_disruption.2167341772
Directory /workspace/13.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/130.usbdev_endpoint_types.3553185632
Short name T1225
Test name
Test status
Simulation time 166666331 ps
CPU time 0.9 seconds
Started Aug 17 06:11:48 PM PDT 24
Finished Aug 17 06:11:49 PM PDT 24
Peak memory 207520 kb
Host smart-0af0a935-bc9a-4714-9fb7-7c4718297d9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3553185632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.3553185632
Directory /workspace/130.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/130.usbdev_tx_rx_disruption.4282551436
Short name T2306
Test name
Test status
Simulation time 491494893 ps
CPU time 1.64 seconds
Started Aug 17 06:11:25 PM PDT 24
Finished Aug 17 06:11:27 PM PDT 24
Peak memory 207536 kb
Host smart-38a8b2b3-783d-4900-af14-d134c0538a7a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282551436 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.usbdev_tx_rx_disruption.4282551436
Directory /workspace/130.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/131.usbdev_endpoint_types.489148990
Short name T446
Test name
Test status
Simulation time 443929903 ps
CPU time 1.39 seconds
Started Aug 17 06:11:35 PM PDT 24
Finished Aug 17 06:11:37 PM PDT 24
Peak memory 207528 kb
Host smart-c5cce01a-df9b-4f24-bc3c-42db95ef860a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=489148990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.489148990
Directory /workspace/131.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/131.usbdev_tx_rx_disruption.3830117052
Short name T2760
Test name
Test status
Simulation time 577736546 ps
CPU time 1.71 seconds
Started Aug 17 06:11:25 PM PDT 24
Finished Aug 17 06:11:27 PM PDT 24
Peak memory 206496 kb
Host smart-c6b8712f-0682-41c6-921b-36a72397cece
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830117052 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.usbdev_tx_rx_disruption.3830117052
Directory /workspace/131.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/132.usbdev_tx_rx_disruption.990774755
Short name T3234
Test name
Test status
Simulation time 592462124 ps
CPU time 1.72 seconds
Started Aug 17 06:11:32 PM PDT 24
Finished Aug 17 06:11:33 PM PDT 24
Peak memory 207592 kb
Host smart-753abab5-f259-444e-a3fe-7094a9681959
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990774755 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 132.usbdev_tx_rx_disruption.990774755
Directory /workspace/132.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/133.usbdev_tx_rx_disruption.855525568
Short name T3129
Test name
Test status
Simulation time 503277649 ps
CPU time 1.67 seconds
Started Aug 17 06:11:33 PM PDT 24
Finished Aug 17 06:11:35 PM PDT 24
Peak memory 207560 kb
Host smart-00f7062c-ca0a-4cd6-8239-5b8da3ab2182
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855525568 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 133.usbdev_tx_rx_disruption.855525568
Directory /workspace/133.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/134.usbdev_endpoint_types.3794355199
Short name T517
Test name
Test status
Simulation time 222205756 ps
CPU time 0.99 seconds
Started Aug 17 06:11:48 PM PDT 24
Finished Aug 17 06:11:49 PM PDT 24
Peak memory 207528 kb
Host smart-5f26f168-5f34-4b2e-a630-29db0160f7d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3794355199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.3794355199
Directory /workspace/134.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/134.usbdev_tx_rx_disruption.2053458502
Short name T3398
Test name
Test status
Simulation time 571668392 ps
CPU time 1.78 seconds
Started Aug 17 06:11:32 PM PDT 24
Finished Aug 17 06:11:34 PM PDT 24
Peak memory 207540 kb
Host smart-f95cccc7-9c30-414c-b7fc-ca570ddf129e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053458502 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.usbdev_tx_rx_disruption.2053458502
Directory /workspace/134.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/135.usbdev_tx_rx_disruption.3592038389
Short name T3562
Test name
Test status
Simulation time 630280023 ps
CPU time 1.8 seconds
Started Aug 17 06:11:46 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207572 kb
Host smart-4b22452f-aba7-46e0-90c3-b4c014663ef3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592038389 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.usbdev_tx_rx_disruption.3592038389
Directory /workspace/135.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/136.usbdev_endpoint_types.3031475608
Short name T480
Test name
Test status
Simulation time 216871382 ps
CPU time 0.99 seconds
Started Aug 17 06:11:41 PM PDT 24
Finished Aug 17 06:11:42 PM PDT 24
Peak memory 207452 kb
Host smart-de3320e1-b4c2-4e21-b815-690ec778234b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3031475608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.3031475608
Directory /workspace/136.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/136.usbdev_tx_rx_disruption.791329832
Short name T181
Test name
Test status
Simulation time 568132733 ps
CPU time 1.68 seconds
Started Aug 17 06:11:49 PM PDT 24
Finished Aug 17 06:11:51 PM PDT 24
Peak memory 207548 kb
Host smart-c301305b-58f1-4151-935e-7f1e28f8a121
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791329832 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 136.usbdev_tx_rx_disruption.791329832
Directory /workspace/136.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/137.usbdev_endpoint_types.434180090
Short name T441
Test name
Test status
Simulation time 233251516 ps
CPU time 1.04 seconds
Started Aug 17 06:11:36 PM PDT 24
Finished Aug 17 06:11:37 PM PDT 24
Peak memory 207532 kb
Host smart-a18a9f50-f631-4428-87a2-081da5ee15cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=434180090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.434180090
Directory /workspace/137.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/137.usbdev_tx_rx_disruption.2479917745
Short name T653
Test name
Test status
Simulation time 583913636 ps
CPU time 1.67 seconds
Started Aug 17 06:11:32 PM PDT 24
Finished Aug 17 06:11:33 PM PDT 24
Peak memory 207544 kb
Host smart-4ca6a14f-365e-42a4-971f-d1fac115dd27
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479917745 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.usbdev_tx_rx_disruption.2479917745
Directory /workspace/137.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/138.usbdev_tx_rx_disruption.4082208393
Short name T3269
Test name
Test status
Simulation time 506687256 ps
CPU time 1.57 seconds
Started Aug 17 06:11:39 PM PDT 24
Finished Aug 17 06:11:41 PM PDT 24
Peak memory 207556 kb
Host smart-cacc526e-f5c4-4620-a551-5fb04cc24e5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082208393 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.usbdev_tx_rx_disruption.4082208393
Directory /workspace/138.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/139.usbdev_endpoint_types.1978748575
Short name T458
Test name
Test status
Simulation time 423218616 ps
CPU time 1.32 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:43 PM PDT 24
Peak memory 207556 kb
Host smart-b34a70b0-b13c-4657-bf31-31fc2d22ccaf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1978748575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.1978748575
Directory /workspace/139.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/139.usbdev_tx_rx_disruption.1619996471
Short name T2535
Test name
Test status
Simulation time 577834730 ps
CPU time 1.84 seconds
Started Aug 17 06:11:45 PM PDT 24
Finished Aug 17 06:11:47 PM PDT 24
Peak memory 207776 kb
Host smart-c1d72416-f2dc-41a9-8541-2474ae855b75
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619996471 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.usbdev_tx_rx_disruption.1619996471
Directory /workspace/139.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.410131604
Short name T844
Test name
Test status
Simulation time 44377149 ps
CPU time 0.69 seconds
Started Aug 17 06:05:44 PM PDT 24
Finished Aug 17 06:05:45 PM PDT 24
Peak memory 207432 kb
Host smart-b754f8e7-122f-4a47-add0-6969a2956e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=410131604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.410131604
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.251996491
Short name T1272
Test name
Test status
Simulation time 8947544704 ps
CPU time 12.33 seconds
Started Aug 17 06:05:34 PM PDT 24
Finished Aug 17 06:05:46 PM PDT 24
Peak memory 207748 kb
Host smart-e7ea7a9d-ba4b-48e4-8fba-ff2455534d6a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251996491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ao
n_wake_disconnect.251996491
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2236871752
Short name T808
Test name
Test status
Simulation time 18943244750 ps
CPU time 21.83 seconds
Started Aug 17 06:05:38 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207792 kb
Host smart-1cc32c5b-e7e5-4e2e-b077-895f59db9546
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236871752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2236871752
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3673726935
Short name T2861
Test name
Test status
Simulation time 23773774612 ps
CPU time 34.23 seconds
Started Aug 17 06:05:35 PM PDT 24
Finished Aug 17 06:06:10 PM PDT 24
Peak memory 215944 kb
Host smart-1f158999-d4f1-4297-9776-7f5bee990370
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673726935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.3673726935
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3299711669
Short name T822
Test name
Test status
Simulation time 184284038 ps
CPU time 0.89 seconds
Started Aug 17 06:05:35 PM PDT 24
Finished Aug 17 06:05:36 PM PDT 24
Peak memory 207460 kb
Host smart-b3c24133-2f47-47e8-9a89-72bb83e6ecab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32997
11669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3299711669
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3231605714
Short name T774
Test name
Test status
Simulation time 154651811 ps
CPU time 0.9 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207544 kb
Host smart-b73fb722-10a6-4e4f-ba94-57b2ba4d5af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32316
05714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3231605714
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.4253197850
Short name T2695
Test name
Test status
Simulation time 423591093 ps
CPU time 1.53 seconds
Started Aug 17 06:05:37 PM PDT 24
Finished Aug 17 06:05:39 PM PDT 24
Peak memory 207544 kb
Host smart-d9272dd0-167f-45e0-aa9b-63215a2dd241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42531
97850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.4253197850
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2031096652
Short name T3093
Test name
Test status
Simulation time 486537788 ps
CPU time 1.63 seconds
Started Aug 17 06:05:34 PM PDT 24
Finished Aug 17 06:05:36 PM PDT 24
Peak memory 207480 kb
Host smart-bff9baf6-8b38-40bb-b805-c7a96d21d5da
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2031096652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2031096652
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.580333763
Short name T354
Test name
Test status
Simulation time 34447497124 ps
CPU time 58.72 seconds
Started Aug 17 06:05:40 PM PDT 24
Finished Aug 17 06:06:39 PM PDT 24
Peak memory 207768 kb
Host smart-94d0dd99-ce1e-4718-8c94-fa539ff1c74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58033
3763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.580333763
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.3047737691
Short name T3483
Test name
Test status
Simulation time 6201997395 ps
CPU time 43.81 seconds
Started Aug 17 06:05:40 PM PDT 24
Finished Aug 17 06:06:24 PM PDT 24
Peak memory 207796 kb
Host smart-9a858d50-c78c-4bc3-a170-ae792ba76d5c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047737691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.3047737691
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.4245696280
Short name T2935
Test name
Test status
Simulation time 604210410 ps
CPU time 1.61 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207500 kb
Host smart-ab7e8c02-697f-4cd7-a0f9-eefe3e13b47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456
96280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.4245696280
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2272824505
Short name T690
Test name
Test status
Simulation time 149091783 ps
CPU time 0.87 seconds
Started Aug 17 06:05:39 PM PDT 24
Finished Aug 17 06:05:40 PM PDT 24
Peak memory 207500 kb
Host smart-5b334f7f-af9b-4f71-8279-32a34dc46843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22728
24505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2272824505
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1623775687
Short name T2108
Test name
Test status
Simulation time 46641877 ps
CPU time 0.72 seconds
Started Aug 17 06:05:37 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207440 kb
Host smart-a4a1e8d4-8ca3-4c70-b04b-061d926eb253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16237
75687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1623775687
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3268415080
Short name T606
Test name
Test status
Simulation time 994354113 ps
CPU time 2.49 seconds
Started Aug 17 06:05:37 PM PDT 24
Finished Aug 17 06:05:40 PM PDT 24
Peak memory 207764 kb
Host smart-4fe694c2-f23b-4982-891f-6f8925b9e1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32684
15080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3268415080
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_types.3562385063
Short name T407
Test name
Test status
Simulation time 388850634 ps
CPU time 1.29 seconds
Started Aug 17 06:05:35 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207432 kb
Host smart-345f9a7f-3ac3-4da0-a84f-f5b8b665206a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3562385063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.3562385063
Directory /workspace/14.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3725333783
Short name T1979
Test name
Test status
Simulation time 190004609 ps
CPU time 1.43 seconds
Started Aug 17 06:05:40 PM PDT 24
Finished Aug 17 06:05:42 PM PDT 24
Peak memory 207620 kb
Host smart-6008a80c-bc54-4d14-bad9-8b8a93765bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37253
33783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3725333783
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.79421159
Short name T2557
Test name
Test status
Simulation time 236983312 ps
CPU time 1.14 seconds
Started Aug 17 06:05:34 PM PDT 24
Finished Aug 17 06:05:36 PM PDT 24
Peak memory 215856 kb
Host smart-a9e3eced-c10a-41f8-89c2-39c5bf52e26b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=79421159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.79421159
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3748591038
Short name T1576
Test name
Test status
Simulation time 183602141 ps
CPU time 0.97 seconds
Started Aug 17 06:05:37 PM PDT 24
Finished Aug 17 06:05:38 PM PDT 24
Peak memory 207452 kb
Host smart-87ede512-2b63-405f-adb4-09b577d279dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37485
91038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3748591038
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1364087261
Short name T748
Test name
Test status
Simulation time 199731364 ps
CPU time 0.96 seconds
Started Aug 17 06:05:40 PM PDT 24
Finished Aug 17 06:05:41 PM PDT 24
Peak memory 207452 kb
Host smart-1b9a547e-005b-459b-b522-14de526858c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13640
87261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1364087261
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.4238224743
Short name T3364
Test name
Test status
Simulation time 4683018019 ps
CPU time 51.89 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 218356 kb
Host smart-e5664c86-8263-4720-b8d9-6819fe5819c4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4238224743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.4238224743
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.3341358147
Short name T2525
Test name
Test status
Simulation time 5394255924 ps
CPU time 62.38 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:06:39 PM PDT 24
Peak memory 207644 kb
Host smart-04e6098f-7c24-402f-aa62-676112bb5b25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3341358147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3341358147
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3360257996
Short name T2639
Test name
Test status
Simulation time 232089927 ps
CPU time 1 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:38 PM PDT 24
Peak memory 207616 kb
Host smart-92d75e00-4489-4db0-9367-7cbbd5fe5ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33602
57996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3360257996
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.260098669
Short name T1309
Test name
Test status
Simulation time 29968825942 ps
CPU time 46.97 seconds
Started Aug 17 06:05:39 PM PDT 24
Finished Aug 17 06:06:26 PM PDT 24
Peak memory 207748 kb
Host smart-52cbbef0-ac76-4f2b-ba2a-10b7bba51254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26009
8669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.260098669
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.592589569
Short name T2024
Test name
Test status
Simulation time 8392562088 ps
CPU time 11.15 seconds
Started Aug 17 06:05:36 PM PDT 24
Finished Aug 17 06:05:47 PM PDT 24
Peak memory 207832 kb
Host smart-b90ca476-5ba3-4a99-bc39-4c5cda9127ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59258
9569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.592589569
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.4063855642
Short name T2212
Test name
Test status
Simulation time 3094868711 ps
CPU time 36.98 seconds
Started Aug 17 06:05:35 PM PDT 24
Finished Aug 17 06:06:12 PM PDT 24
Peak memory 218120 kb
Host smart-66678dbf-0792-403b-983c-fced53772db9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4063855642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.4063855642
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.163201358
Short name T2072
Test name
Test status
Simulation time 2861480495 ps
CPU time 22.64 seconds
Started Aug 17 06:05:38 PM PDT 24
Finished Aug 17 06:06:01 PM PDT 24
Peak memory 224104 kb
Host smart-183b6cfe-2c6a-47a6-909b-463370dda33d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=163201358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.163201358
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2661276347
Short name T2174
Test name
Test status
Simulation time 242843905 ps
CPU time 1.1 seconds
Started Aug 17 06:05:38 PM PDT 24
Finished Aug 17 06:05:39 PM PDT 24
Peak memory 207452 kb
Host smart-c3cf9350-f06b-437d-9153-239fa1b426cc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2661276347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2661276347
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2788434287
Short name T3519
Test name
Test status
Simulation time 195792141 ps
CPU time 1 seconds
Started Aug 17 06:05:37 PM PDT 24
Finished Aug 17 06:05:38 PM PDT 24
Peak memory 207528 kb
Host smart-0c8b1924-3400-4afa-a1cc-128080d8a7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27884
34287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2788434287
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.124229106
Short name T2768
Test name
Test status
Simulation time 2354602896 ps
CPU time 65.69 seconds
Started Aug 17 06:05:39 PM PDT 24
Finished Aug 17 06:06:44 PM PDT 24
Peak memory 217916 kb
Host smart-e4853c0f-17f8-47b7-9d2d-d88cf2ca1013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12422
9106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.124229106
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3816205715
Short name T130
Test name
Test status
Simulation time 2222697750 ps
CPU time 19.24 seconds
Started Aug 17 06:05:40 PM PDT 24
Finished Aug 17 06:05:59 PM PDT 24
Peak memory 218584 kb
Host smart-7f0e99d7-deaf-47e6-b45c-15c55567b054
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3816205715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3816205715
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2086417334
Short name T569
Test name
Test status
Simulation time 1737544469 ps
CPU time 19.39 seconds
Started Aug 17 06:05:35 PM PDT 24
Finished Aug 17 06:05:55 PM PDT 24
Peak memory 217296 kb
Host smart-d7bd0dd5-7b4e-432f-8119-70a22746d8f8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2086417334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2086417334
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1885328159
Short name T2092
Test name
Test status
Simulation time 164443951 ps
CPU time 0.98 seconds
Started Aug 17 06:05:38 PM PDT 24
Finished Aug 17 06:05:39 PM PDT 24
Peak memory 207492 kb
Host smart-fefef8ed-f8c1-421a-b943-18d9de33d25b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1885328159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1885328159
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2902059248
Short name T2223
Test name
Test status
Simulation time 156612277 ps
CPU time 0.87 seconds
Started Aug 17 06:05:38 PM PDT 24
Finished Aug 17 06:05:38 PM PDT 24
Peak memory 207448 kb
Host smart-aaf149d7-3e93-4641-be9d-5ff817fd639e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29020
59248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2902059248
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.4111383979
Short name T162
Test name
Test status
Simulation time 208820629 ps
CPU time 0.97 seconds
Started Aug 17 06:05:45 PM PDT 24
Finished Aug 17 06:05:46 PM PDT 24
Peak memory 207408 kb
Host smart-87104b6d-d531-46d4-8669-4b466b412701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
83979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.4111383979
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1971785809
Short name T2477
Test name
Test status
Simulation time 184976530 ps
CPU time 1.05 seconds
Started Aug 17 06:05:46 PM PDT 24
Finished Aug 17 06:05:47 PM PDT 24
Peak memory 207512 kb
Host smart-b2528ae2-ec2e-4e96-a62e-2c494a43299f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19717
85809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1971785809
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.188738901
Short name T1211
Test name
Test status
Simulation time 172782620 ps
CPU time 0.88 seconds
Started Aug 17 06:05:41 PM PDT 24
Finished Aug 17 06:05:42 PM PDT 24
Peak memory 207456 kb
Host smart-f09b1e2d-c075-4d0d-a512-442582f0ae8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18873
8901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.188738901
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3843966961
Short name T2472
Test name
Test status
Simulation time 165701794 ps
CPU time 0.86 seconds
Started Aug 17 06:05:48 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 207508 kb
Host smart-3eec223e-23a4-499c-bdf3-307f6be56b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38439
66961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3843966961
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.279385302
Short name T170
Test name
Test status
Simulation time 155421347 ps
CPU time 0.86 seconds
Started Aug 17 06:05:43 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 207476 kb
Host smart-70453078-c930-4303-8712-fc85a48ff577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938
5302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.279385302
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2228799845
Short name T1255
Test name
Test status
Simulation time 183046261 ps
CPU time 0.99 seconds
Started Aug 17 06:05:42 PM PDT 24
Finished Aug 17 06:05:43 PM PDT 24
Peak memory 207472 kb
Host smart-e4f0f265-74da-49f2-9bf2-57215317d59a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2228799845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2228799845
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3884106425
Short name T2480
Test name
Test status
Simulation time 158897949 ps
CPU time 0.84 seconds
Started Aug 17 06:05:44 PM PDT 24
Finished Aug 17 06:05:45 PM PDT 24
Peak memory 207424 kb
Host smart-5aa45636-a3f5-4e84-97f2-f28642fd1c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38841
06425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3884106425
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3986596610
Short name T2319
Test name
Test status
Simulation time 29208501 ps
CPU time 0.69 seconds
Started Aug 17 06:05:42 PM PDT 24
Finished Aug 17 06:05:43 PM PDT 24
Peak memory 207524 kb
Host smart-7a4b77b2-ab14-4b34-8c29-209911df51c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39865
96610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3986596610
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3570743593
Short name T2897
Test name
Test status
Simulation time 21864407887 ps
CPU time 52.9 seconds
Started Aug 17 06:05:45 PM PDT 24
Finished Aug 17 06:06:38 PM PDT 24
Peak memory 215884 kb
Host smart-ed4ec423-4a2f-4586-ab1e-288afd6bdcda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35707
43593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3570743593
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3370323232
Short name T3204
Test name
Test status
Simulation time 180966815 ps
CPU time 0.92 seconds
Started Aug 17 06:05:47 PM PDT 24
Finished Aug 17 06:05:48 PM PDT 24
Peak memory 207560 kb
Host smart-c4081165-8fad-4ea0-a718-9e6f2f7ea164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
23232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3370323232
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1949107756
Short name T912
Test name
Test status
Simulation time 196146057 ps
CPU time 0.99 seconds
Started Aug 17 06:05:43 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 207432 kb
Host smart-fae473fb-a761-427d-b7ca-4fd7a2f150bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19491
07756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1949107756
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.1972513528
Short name T2425
Test name
Test status
Simulation time 285577791 ps
CPU time 1.02 seconds
Started Aug 17 06:05:48 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 207436 kb
Host smart-6500c8b4-7c7a-45b9-a711-2238e3b41dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19725
13528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.1972513528
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.4255695815
Short name T1975
Test name
Test status
Simulation time 175004285 ps
CPU time 0.93 seconds
Started Aug 17 06:05:43 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 207420 kb
Host smart-87859eeb-7218-4fb1-8c64-3942890f840c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42556
95815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.4255695815
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_resume_link_active.963165279
Short name T1294
Test name
Test status
Simulation time 20177636493 ps
CPU time 25.81 seconds
Started Aug 17 06:05:46 PM PDT 24
Finished Aug 17 06:06:12 PM PDT 24
Peak memory 207584 kb
Host smart-7a6ed356-e619-4146-bc12-b7dcfbd7ce14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96316
5279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.963165279
Directory /workspace/14.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.733185333
Short name T1105
Test name
Test status
Simulation time 138148248 ps
CPU time 0.83 seconds
Started Aug 17 06:05:44 PM PDT 24
Finished Aug 17 06:05:45 PM PDT 24
Peak memory 207396 kb
Host smart-5e4c3f33-36db-4d41-921c-037a8778429e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73318
5333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.733185333
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_rx_full.3245633451
Short name T46
Test name
Test status
Simulation time 261971744 ps
CPU time 1.11 seconds
Started Aug 17 06:05:44 PM PDT 24
Finished Aug 17 06:05:45 PM PDT 24
Peak memory 207404 kb
Host smart-3730dbcc-4fd0-4fb5-a40a-694291e76119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32456
33451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.3245633451
Directory /workspace/14.usbdev_rx_full/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3192258384
Short name T3021
Test name
Test status
Simulation time 159849687 ps
CPU time 0.83 seconds
Started Aug 17 06:05:43 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 207456 kb
Host smart-2274282e-4f19-43fc-83d2-7f90dba52a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31922
58384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3192258384
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.102056293
Short name T1588
Test name
Test status
Simulation time 190934055 ps
CPU time 0.9 seconds
Started Aug 17 06:05:43 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 207592 kb
Host smart-d8dd890e-a04d-4e7c-b8a2-1e4f22fb08c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10205
6293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.102056293
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.847262521
Short name T1652
Test name
Test status
Simulation time 258537510 ps
CPU time 1.03 seconds
Started Aug 17 06:05:48 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 207432 kb
Host smart-7bc0bd04-a1b0-47a1-b0a8-fe6e604d249c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84726
2521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.847262521
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3475020087
Short name T2927
Test name
Test status
Simulation time 3050203708 ps
CPU time 92.4 seconds
Started Aug 17 06:05:45 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 217464 kb
Host smart-711defa9-2227-43aa-bc6d-130cc10579b8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3475020087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3475020087
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1119339502
Short name T519
Test name
Test status
Simulation time 174429816 ps
CPU time 0.95 seconds
Started Aug 17 06:05:44 PM PDT 24
Finished Aug 17 06:05:45 PM PDT 24
Peak memory 207480 kb
Host smart-b87bcfc2-b123-4f0c-a593-c75602cfb997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11193
39502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1119339502
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.4182442822
Short name T2636
Test name
Test status
Simulation time 166922700 ps
CPU time 0.83 seconds
Started Aug 17 06:05:41 PM PDT 24
Finished Aug 17 06:05:42 PM PDT 24
Peak memory 207576 kb
Host smart-d67075e8-8dbe-444b-88e4-88e4946e4faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41824
42822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.4182442822
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2253361568
Short name T1430
Test name
Test status
Simulation time 1407863784 ps
CPU time 3.17 seconds
Started Aug 17 06:05:46 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 207772 kb
Host smart-f0bb6838-1706-4fe1-8d07-c277b87f40f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22533
61568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2253361568
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2254190406
Short name T1418
Test name
Test status
Simulation time 2722841379 ps
CPU time 80.13 seconds
Started Aug 17 06:05:44 PM PDT 24
Finished Aug 17 06:07:05 PM PDT 24
Peak memory 217324 kb
Host smart-3215072b-4f7b-4655-9914-a2f5b7245edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22541
90406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2254190406
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.3319419587
Short name T3113
Test name
Test status
Simulation time 827011357 ps
CPU time 19.56 seconds
Started Aug 17 06:05:38 PM PDT 24
Finished Aug 17 06:05:58 PM PDT 24
Peak memory 207600 kb
Host smart-84a33d2a-4a61-41b1-a197-e7968bf2064c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319419587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.3319419587
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_tx_rx_disruption.435036759
Short name T3059
Test name
Test status
Simulation time 484518753 ps
CPU time 1.56 seconds
Started Aug 17 06:05:43 PM PDT 24
Finished Aug 17 06:05:45 PM PDT 24
Peak memory 207548 kb
Host smart-dce7b1a0-e851-4921-b27c-4e4d7f97090a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435036759 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.usbdev_tx_rx_disruption.435036759
Directory /workspace/14.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/140.usbdev_tx_rx_disruption.308660268
Short name T3177
Test name
Test status
Simulation time 544331399 ps
CPU time 1.63 seconds
Started Aug 17 06:11:34 PM PDT 24
Finished Aug 17 06:11:36 PM PDT 24
Peak memory 207564 kb
Host smart-6e868f85-7998-4887-8622-b6c1b91db4b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308660268 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 140.usbdev_tx_rx_disruption.308660268
Directory /workspace/140.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/141.usbdev_endpoint_types.1690883747
Short name T516
Test name
Test status
Simulation time 390970034 ps
CPU time 1.28 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207452 kb
Host smart-f6fa55bc-0f6b-4f7d-ba8b-46c7f6712d8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1690883747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.1690883747
Directory /workspace/141.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/141.usbdev_tx_rx_disruption.2418566407
Short name T3573
Test name
Test status
Simulation time 665607691 ps
CPU time 1.71 seconds
Started Aug 17 06:11:29 PM PDT 24
Finished Aug 17 06:11:31 PM PDT 24
Peak memory 207560 kb
Host smart-48036005-b96c-4917-832f-2849044acceb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418566407 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.usbdev_tx_rx_disruption.2418566407
Directory /workspace/141.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/142.usbdev_endpoint_types.3884888281
Short name T3358
Test name
Test status
Simulation time 253401811 ps
CPU time 1.06 seconds
Started Aug 17 06:11:35 PM PDT 24
Finished Aug 17 06:11:36 PM PDT 24
Peak memory 207532 kb
Host smart-308dc648-7627-401f-bc65-d7df799863f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3884888281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.3884888281
Directory /workspace/142.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/142.usbdev_tx_rx_disruption.3795830244
Short name T873
Test name
Test status
Simulation time 389141343 ps
CPU time 1.29 seconds
Started Aug 17 06:11:38 PM PDT 24
Finished Aug 17 06:11:39 PM PDT 24
Peak memory 207544 kb
Host smart-0de90785-fa5b-4266-8a46-6bddef9442a7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795830244 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.usbdev_tx_rx_disruption.3795830244
Directory /workspace/142.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/143.usbdev_endpoint_types.2034919488
Short name T477
Test name
Test status
Simulation time 188685621 ps
CPU time 0.97 seconds
Started Aug 17 06:11:31 PM PDT 24
Finished Aug 17 06:11:32 PM PDT 24
Peak memory 207520 kb
Host smart-75db4593-2d95-4a52-9145-0db909642b63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2034919488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.2034919488
Directory /workspace/143.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_tx_rx_disruption.3124126988
Short name T2845
Test name
Test status
Simulation time 541084693 ps
CPU time 1.68 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:44 PM PDT 24
Peak memory 207544 kb
Host smart-d5559250-98c3-4a24-9fc0-501f7ea70082
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124126988 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.usbdev_tx_rx_disruption.3124126988
Directory /workspace/144.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/145.usbdev_tx_rx_disruption.323295463
Short name T1264
Test name
Test status
Simulation time 576620067 ps
CPU time 1.58 seconds
Started Aug 17 06:11:28 PM PDT 24
Finished Aug 17 06:11:30 PM PDT 24
Peak memory 207552 kb
Host smart-ae861337-2e2b-40ad-8743-0cba897297d2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323295463 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 145.usbdev_tx_rx_disruption.323295463
Directory /workspace/145.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/146.usbdev_endpoint_types.445832938
Short name T469
Test name
Test status
Simulation time 351203254 ps
CPU time 1.21 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207500 kb
Host smart-b49a4f4c-df01-451e-9810-94d5d1ce15b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=445832938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.445832938
Directory /workspace/146.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/146.usbdev_tx_rx_disruption.3123526118
Short name T2561
Test name
Test status
Simulation time 559207041 ps
CPU time 1.56 seconds
Started Aug 17 06:11:33 PM PDT 24
Finished Aug 17 06:11:35 PM PDT 24
Peak memory 207496 kb
Host smart-028f0062-56ab-4088-83b2-00d9d535f74d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123526118 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.usbdev_tx_rx_disruption.3123526118
Directory /workspace/146.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/147.usbdev_tx_rx_disruption.1077125614
Short name T1759
Test name
Test status
Simulation time 522930855 ps
CPU time 1.84 seconds
Started Aug 17 06:11:49 PM PDT 24
Finished Aug 17 06:11:50 PM PDT 24
Peak memory 207572 kb
Host smart-3fff6175-9d84-4fd3-8e3a-a34d53762643
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077125614 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.usbdev_tx_rx_disruption.1077125614
Directory /workspace/147.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/148.usbdev_tx_rx_disruption.1039874748
Short name T3143
Test name
Test status
Simulation time 630308197 ps
CPU time 1.77 seconds
Started Aug 17 06:11:41 PM PDT 24
Finished Aug 17 06:11:43 PM PDT 24
Peak memory 207472 kb
Host smart-eb45e733-ccbd-4bbf-b539-57fb85930bb4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039874748 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.usbdev_tx_rx_disruption.1039874748
Directory /workspace/148.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/149.usbdev_tx_rx_disruption.2009666447
Short name T751
Test name
Test status
Simulation time 508930059 ps
CPU time 1.83 seconds
Started Aug 17 06:11:40 PM PDT 24
Finished Aug 17 06:11:42 PM PDT 24
Peak memory 207500 kb
Host smart-ea558490-4b92-4232-b286-09dc032de966
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009666447 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.usbdev_tx_rx_disruption.2009666447
Directory /workspace/149.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.700181112
Short name T3397
Test name
Test status
Simulation time 120814587 ps
CPU time 0.79 seconds
Started Aug 17 06:05:50 PM PDT 24
Finished Aug 17 06:05:51 PM PDT 24
Peak memory 207428 kb
Host smart-c860f2e9-00a7-4d7b-8251-10ea2b652826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=700181112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.700181112
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2026930196
Short name T716
Test name
Test status
Simulation time 9649260571 ps
CPU time 13.09 seconds
Started Aug 17 06:05:43 PM PDT 24
Finished Aug 17 06:05:56 PM PDT 24
Peak memory 207820 kb
Host smart-c99e3913-2576-4c08-9a49-27f8f5ed64e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026930196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.2026930196
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.332478222
Short name T250
Test name
Test status
Simulation time 14129354550 ps
CPU time 15.3 seconds
Started Aug 17 06:05:43 PM PDT 24
Finished Aug 17 06:05:59 PM PDT 24
Peak memory 215948 kb
Host smart-2ecf0bca-c141-45d5-83c7-ba89a0aa6a2c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=332478222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.332478222
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1334509335
Short name T1954
Test name
Test status
Simulation time 23642256510 ps
CPU time 28.4 seconds
Started Aug 17 06:05:49 PM PDT 24
Finished Aug 17 06:06:17 PM PDT 24
Peak memory 216000 kb
Host smart-0863f9b9-3958-4beb-8a2d-6679c679e663
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334509335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.1334509335
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2897119146
Short name T3421
Test name
Test status
Simulation time 148068153 ps
CPU time 0.85 seconds
Started Aug 17 06:05:44 PM PDT 24
Finished Aug 17 06:05:45 PM PDT 24
Peak memory 207348 kb
Host smart-f47cbc2e-58f4-46f1-bca3-218952e03022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28971
19146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2897119146
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.4034328462
Short name T806
Test name
Test status
Simulation time 184149601 ps
CPU time 0.89 seconds
Started Aug 17 06:05:43 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 207504 kb
Host smart-45cefdb2-3d03-4942-bc93-418b4465f55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40343
28462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.4034328462
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.3262217578
Short name T2374
Test name
Test status
Simulation time 507827419 ps
CPU time 1.86 seconds
Started Aug 17 06:05:44 PM PDT 24
Finished Aug 17 06:05:46 PM PDT 24
Peak memory 207536 kb
Host smart-ab787b68-66ed-41c8-93d4-6932c9379ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32622
17578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.3262217578
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2726045321
Short name T3114
Test name
Test status
Simulation time 728512344 ps
CPU time 2.05 seconds
Started Aug 17 06:05:47 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 207720 kb
Host smart-730b4b5d-d7de-4486-b2d2-049a3d13805e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2726045321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2726045321
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2063745112
Short name T2518
Test name
Test status
Simulation time 21622264737 ps
CPU time 41.27 seconds
Started Aug 17 06:05:42 PM PDT 24
Finished Aug 17 06:06:24 PM PDT 24
Peak memory 207776 kb
Host smart-9df1eb21-8e74-4cbb-bc6e-de573f162016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20637
45112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2063745112
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.571340975
Short name T1782
Test name
Test status
Simulation time 2039991670 ps
CPU time 19.51 seconds
Started Aug 17 06:05:44 PM PDT 24
Finished Aug 17 06:06:03 PM PDT 24
Peak memory 207696 kb
Host smart-f886a51c-c5d1-4a5d-979c-22882ae7daf2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571340975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.571340975
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.16615143
Short name T2198
Test name
Test status
Simulation time 1148051496 ps
CPU time 2.25 seconds
Started Aug 17 06:05:47 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 207528 kb
Host smart-adbedbfd-ccb6-437a-8784-4d62f1fdb1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16615
143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.16615143
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2535376349
Short name T1103
Test name
Test status
Simulation time 138744055 ps
CPU time 0.81 seconds
Started Aug 17 06:05:45 PM PDT 24
Finished Aug 17 06:05:46 PM PDT 24
Peak memory 207560 kb
Host smart-977e7bf5-0077-4b0e-8bad-f7bfef02be6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25353
76349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2535376349
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.872354949
Short name T2729
Test name
Test status
Simulation time 48312398 ps
CPU time 0.74 seconds
Started Aug 17 06:05:45 PM PDT 24
Finished Aug 17 06:05:46 PM PDT 24
Peak memory 207428 kb
Host smart-effe8dc4-f5a2-4132-b4ef-635bd424a8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87235
4949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.872354949
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3375114754
Short name T2116
Test name
Test status
Simulation time 842316123 ps
CPU time 2.4 seconds
Started Aug 17 06:05:50 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207772 kb
Host smart-39d090ae-751a-4b18-8d83-64c41d627098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33751
14754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3375114754
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_types.2886602364
Short name T381
Test name
Test status
Simulation time 182391730 ps
CPU time 0.99 seconds
Started Aug 17 06:05:53 PM PDT 24
Finished Aug 17 06:05:54 PM PDT 24
Peak memory 207464 kb
Host smart-ddfe76fd-520b-4fdb-91c7-4e9148e3a769
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2886602364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.2886602364
Directory /workspace/15.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.183716820
Short name T859
Test name
Test status
Simulation time 228310534 ps
CPU time 1.75 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:54 PM PDT 24
Peak memory 207636 kb
Host smart-ccc44fd2-0108-4f0b-85de-eb47b31c838d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18371
6820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.183716820
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1739036824
Short name T1057
Test name
Test status
Simulation time 177444917 ps
CPU time 0.96 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207344 kb
Host smart-00367b14-e788-46e9-97a7-8d389092597a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1739036824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1739036824
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.109500395
Short name T2457
Test name
Test status
Simulation time 149671282 ps
CPU time 0.9 seconds
Started Aug 17 06:05:50 PM PDT 24
Finished Aug 17 06:05:51 PM PDT 24
Peak memory 207404 kb
Host smart-b96b606e-c7f6-4bff-8b73-b3af78ffd0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10950
0395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.109500395
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.415793772
Short name T2282
Test name
Test status
Simulation time 258080622 ps
CPU time 1.02 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207488 kb
Host smart-3d8b7fbb-0f16-4de9-b4ae-923594d7163a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41579
3772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.415793772
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3898193483
Short name T1501
Test name
Test status
Simulation time 4577529170 ps
CPU time 36.24 seconds
Started Aug 17 06:05:54 PM PDT 24
Finished Aug 17 06:06:30 PM PDT 24
Peak memory 218128 kb
Host smart-e31de39c-94d5-4ba9-8a56-0134c13caf21
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3898193483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3898193483
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.1306847908
Short name T3453
Test name
Test status
Simulation time 5159315503 ps
CPU time 38.04 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:06:30 PM PDT 24
Peak memory 207784 kb
Host smart-4512674e-3dc1-497a-b153-dc0390a1edcb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1306847908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.1306847908
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1625279700
Short name T3190
Test name
Test status
Simulation time 156718308 ps
CPU time 0.96 seconds
Started Aug 17 06:05:50 PM PDT 24
Finished Aug 17 06:05:51 PM PDT 24
Peak memory 207564 kb
Host smart-43f9030e-c928-4460-853f-628585fc40c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
79700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1625279700
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3054584949
Short name T1704
Test name
Test status
Simulation time 27983018148 ps
CPU time 38.49 seconds
Started Aug 17 06:05:49 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 215972 kb
Host smart-5fe882b8-bcc5-4c65-9692-c2cd316cb07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30545
84949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3054584949
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.697158745
Short name T2625
Test name
Test status
Simulation time 5781355746 ps
CPU time 9.21 seconds
Started Aug 17 06:05:51 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 216160 kb
Host smart-a74fb55f-0702-4dce-8bb3-959b88d03ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69715
8745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.697158745
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.3792226868
Short name T3523
Test name
Test status
Simulation time 3310127140 ps
CPU time 98.85 seconds
Started Aug 17 06:05:48 PM PDT 24
Finished Aug 17 06:07:27 PM PDT 24
Peak memory 215944 kb
Host smart-793b3b81-4f53-4527-82bc-68bb83a3e5c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3792226868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.3792226868
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.666079214
Short name T2071
Test name
Test status
Simulation time 3288014866 ps
CPU time 33.04 seconds
Started Aug 17 06:05:49 PM PDT 24
Finished Aug 17 06:06:22 PM PDT 24
Peak memory 217740 kb
Host smart-0d1f0652-ed55-4b72-be61-55dbf775aff6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=666079214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.666079214
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1012148260
Short name T2649
Test name
Test status
Simulation time 243372598 ps
CPU time 1 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207340 kb
Host smart-ca7e5f96-2172-4702-9bb8-8798fbcc3639
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1012148260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1012148260
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3738708498
Short name T842
Test name
Test status
Simulation time 184803030 ps
CPU time 0.96 seconds
Started Aug 17 06:05:51 PM PDT 24
Finished Aug 17 06:05:52 PM PDT 24
Peak memory 207432 kb
Host smart-f2391a95-d822-47b5-be9b-6f3c07779467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37387
08498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3738708498
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.3953728965
Short name T643
Test name
Test status
Simulation time 2438897346 ps
CPU time 21.04 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:20 PM PDT 24
Peak memory 217828 kb
Host smart-c2140ab1-0564-4277-8611-c74d8ee54934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
28965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.3953728965
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3933471235
Short name T2077
Test name
Test status
Simulation time 2744174870 ps
CPU time 86.34 seconds
Started Aug 17 06:05:50 PM PDT 24
Finished Aug 17 06:07:16 PM PDT 24
Peak memory 215904 kb
Host smart-6928db08-4207-4a29-b2c3-858dcc0f6220
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3933471235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3933471235
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1758792390
Short name T3050
Test name
Test status
Simulation time 188536892 ps
CPU time 0.91 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207456 kb
Host smart-7ce50975-e12d-4065-9817-56be8a03bbe8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1758792390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1758792390
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1555839296
Short name T1102
Test name
Test status
Simulation time 145475642 ps
CPU time 0.86 seconds
Started Aug 17 06:05:55 PM PDT 24
Finished Aug 17 06:05:55 PM PDT 24
Peak memory 207468 kb
Host smart-c0c1ec57-445a-481f-8ee3-f92fbfa47e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15558
39296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1555839296
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1742746663
Short name T727
Test name
Test status
Simulation time 216130867 ps
CPU time 0.98 seconds
Started Aug 17 06:05:50 PM PDT 24
Finished Aug 17 06:05:51 PM PDT 24
Peak memory 207468 kb
Host smart-c1065b0c-7a86-4408-bf3e-a1aea377391d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17427
46663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1742746663
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1684781553
Short name T683
Test name
Test status
Simulation time 162351783 ps
CPU time 0.88 seconds
Started Aug 17 06:05:55 PM PDT 24
Finished Aug 17 06:05:56 PM PDT 24
Peak memory 207464 kb
Host smart-3e7504a9-abeb-46de-bc90-2906e968917c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847
81553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1684781553
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.745502791
Short name T1936
Test name
Test status
Simulation time 208614142 ps
CPU time 0.9 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207432 kb
Host smart-f563874c-a1a5-4550-a959-2495a019675c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74550
2791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.745502791
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2188010407
Short name T2386
Test name
Test status
Simulation time 233289713 ps
CPU time 0.95 seconds
Started Aug 17 06:05:54 PM PDT 24
Finished Aug 17 06:05:56 PM PDT 24
Peak memory 207540 kb
Host smart-d162bc8b-d4dd-49aa-9989-3dcd4ab77385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21880
10407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2188010407
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2836731848
Short name T2006
Test name
Test status
Simulation time 152085761 ps
CPU time 0.89 seconds
Started Aug 17 06:05:55 PM PDT 24
Finished Aug 17 06:05:56 PM PDT 24
Peak memory 207548 kb
Host smart-97007e8e-1bc7-436f-b0b2-98718a16bd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28367
31848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2836731848
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1649386779
Short name T2406
Test name
Test status
Simulation time 243623575 ps
CPU time 1.07 seconds
Started Aug 17 06:05:50 PM PDT 24
Finished Aug 17 06:05:51 PM PDT 24
Peak memory 207552 kb
Host smart-30d3825b-209a-4ec7-9c30-e67a46643c0a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1649386779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1649386779
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1983686246
Short name T1890
Test name
Test status
Simulation time 177461760 ps
CPU time 0.87 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207452 kb
Host smart-5adaaa0c-9e65-405e-968d-c5aade20391f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19836
86246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1983686246
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.14560067
Short name T1559
Test name
Test status
Simulation time 40062067 ps
CPU time 0.72 seconds
Started Aug 17 06:05:54 PM PDT 24
Finished Aug 17 06:05:55 PM PDT 24
Peak memory 207512 kb
Host smart-e8cfb756-e283-4e98-9d4d-c00121702ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14560
067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.14560067
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.223177429
Short name T3264
Test name
Test status
Simulation time 20931100526 ps
CPU time 55.54 seconds
Started Aug 17 06:05:55 PM PDT 24
Finished Aug 17 06:06:50 PM PDT 24
Peak memory 215960 kb
Host smart-9d2d57f2-ed3b-4e54-a0b1-1d9d95fd98af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22317
7429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.223177429
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1129798221
Short name T1806
Test name
Test status
Simulation time 150963054 ps
CPU time 0.91 seconds
Started Aug 17 06:05:48 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 207528 kb
Host smart-a2a06721-4bc7-48f6-8a05-9812287fb795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11297
98221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1129798221
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.181777060
Short name T663
Test name
Test status
Simulation time 200487164 ps
CPU time 0.96 seconds
Started Aug 17 06:05:51 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207488 kb
Host smart-438ab024-c1b8-4bd3-9191-4515161a245e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18177
7060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.181777060
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2027312055
Short name T2226
Test name
Test status
Simulation time 184823217 ps
CPU time 0.97 seconds
Started Aug 17 06:05:50 PM PDT 24
Finished Aug 17 06:05:51 PM PDT 24
Peak memory 207472 kb
Host smart-19a08125-d01e-41b0-bc39-55e3339d326f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20273
12055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2027312055
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.423788268
Short name T3391
Test name
Test status
Simulation time 203240932 ps
CPU time 0.91 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207496 kb
Host smart-8fe9d07c-1458-4650-8933-352d77fd1cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378
8268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.423788268
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_resume_link_active.1010341828
Short name T1830
Test name
Test status
Simulation time 20164877941 ps
CPU time 24.28 seconds
Started Aug 17 06:05:51 PM PDT 24
Finished Aug 17 06:06:15 PM PDT 24
Peak memory 207500 kb
Host smart-b6ab825a-6b6e-4187-b979-6c4a71dc604e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10103
41828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.1010341828
Directory /workspace/15.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.4103951245
Short name T3582
Test name
Test status
Simulation time 147740444 ps
CPU time 0.84 seconds
Started Aug 17 06:05:49 PM PDT 24
Finished Aug 17 06:05:50 PM PDT 24
Peak memory 207388 kb
Host smart-b1713bb4-ad08-4ba1-86b4-3ac51f5684f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41039
51245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.4103951245
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_rx_full.3776714074
Short name T1122
Test name
Test status
Simulation time 273488163 ps
CPU time 1.17 seconds
Started Aug 17 06:05:51 PM PDT 24
Finished Aug 17 06:05:52 PM PDT 24
Peak memory 207460 kb
Host smart-77619cc4-b06d-44cf-b63b-d383fd291d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37767
14074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.3776714074
Directory /workspace/15.usbdev_rx_full/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.4024944181
Short name T794
Test name
Test status
Simulation time 165522648 ps
CPU time 0.89 seconds
Started Aug 17 06:05:49 PM PDT 24
Finished Aug 17 06:05:50 PM PDT 24
Peak memory 207512 kb
Host smart-e79eb68f-103e-41f1-87b2-0ee422e55c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40249
44181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.4024944181
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2700318254
Short name T3307
Test name
Test status
Simulation time 145757601 ps
CPU time 0.82 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207428 kb
Host smart-04a97d90-e748-4b19-9de2-4c543d71ed67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27003
18254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2700318254
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1417536483
Short name T907
Test name
Test status
Simulation time 292209481 ps
CPU time 1.11 seconds
Started Aug 17 06:05:48 PM PDT 24
Finished Aug 17 06:05:49 PM PDT 24
Peak memory 207472 kb
Host smart-d6f45c54-76df-4d80-9764-735edf8d2112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14175
36483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1417536483
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2197174239
Short name T2183
Test name
Test status
Simulation time 3064281596 ps
CPU time 88.37 seconds
Started Aug 17 06:05:51 PM PDT 24
Finished Aug 17 06:07:19 PM PDT 24
Peak memory 217876 kb
Host smart-8a5460f6-6665-4e07-87b0-bcf35c9e2139
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2197174239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2197174239
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3314487490
Short name T3373
Test name
Test status
Simulation time 196179911 ps
CPU time 0.91 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207428 kb
Host smart-fd1425eb-4f1b-4335-9994-bc17768eed6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33144
87490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3314487490
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3638294011
Short name T2665
Test name
Test status
Simulation time 143331742 ps
CPU time 0.93 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207476 kb
Host smart-64898ac6-69af-4cd8-ad07-d0e309be9557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36382
94011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3638294011
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.2222538786
Short name T1631
Test name
Test status
Simulation time 549574504 ps
CPU time 1.63 seconds
Started Aug 17 06:05:52 PM PDT 24
Finished Aug 17 06:05:54 PM PDT 24
Peak memory 207504 kb
Host smart-a27a9028-76b2-4c15-bfc8-5c380cbf8989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22225
38786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2222538786
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.4033993757
Short name T2070
Test name
Test status
Simulation time 3786303712 ps
CPU time 37.04 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:36 PM PDT 24
Peak memory 217696 kb
Host smart-3aed24c3-0126-420e-9ddc-9c2a62bbf81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40339
93757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.4033993757
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.4038237656
Short name T924
Test name
Test status
Simulation time 1956590725 ps
CPU time 17.66 seconds
Started Aug 17 06:05:46 PM PDT 24
Finished Aug 17 06:06:04 PM PDT 24
Peak memory 207688 kb
Host smart-df2ad9c5-9c5a-4853-ad3a-c004296f4a1b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038237656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.4038237656
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_tx_rx_disruption.1124973824
Short name T1883
Test name
Test status
Simulation time 551286241 ps
CPU time 1.75 seconds
Started Aug 17 06:05:51 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 207472 kb
Host smart-7d7ab564-3cff-4997-9768-bd45c3d9f44c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124973824 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.usbdev_tx_rx_disruption.1124973824
Directory /workspace/15.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/150.usbdev_tx_rx_disruption.607543183
Short name T721
Test name
Test status
Simulation time 631168865 ps
CPU time 1.87 seconds
Started Aug 17 06:11:33 PM PDT 24
Finished Aug 17 06:11:35 PM PDT 24
Peak memory 207552 kb
Host smart-d3bdff1e-9766-4d23-811d-b54a9cfeeade
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607543183 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 150.usbdev_tx_rx_disruption.607543183
Directory /workspace/150.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/151.usbdev_endpoint_types.2648758052
Short name T1825
Test name
Test status
Simulation time 169202473 ps
CPU time 0.91 seconds
Started Aug 17 06:11:43 PM PDT 24
Finished Aug 17 06:11:44 PM PDT 24
Peak memory 207524 kb
Host smart-1eca70a9-d118-49d9-b7cd-80657eac9e11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2648758052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.2648758052
Directory /workspace/151.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/151.usbdev_tx_rx_disruption.2209656492
Short name T1128
Test name
Test status
Simulation time 614651092 ps
CPU time 1.8 seconds
Started Aug 17 06:11:26 PM PDT 24
Finished Aug 17 06:11:28 PM PDT 24
Peak memory 207544 kb
Host smart-b5f214e5-1ef7-49f5-a55a-df27fcb19acc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209656492 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.usbdev_tx_rx_disruption.2209656492
Directory /workspace/151.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/152.usbdev_endpoint_types.3619816481
Short name T2977
Test name
Test status
Simulation time 479407199 ps
CPU time 1.42 seconds
Started Aug 17 06:11:50 PM PDT 24
Finished Aug 17 06:11:51 PM PDT 24
Peak memory 207452 kb
Host smart-df7cf323-d097-43e9-b43d-3ce30ea6024b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3619816481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.3619816481
Directory /workspace/152.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/152.usbdev_tx_rx_disruption.2608202040
Short name T1946
Test name
Test status
Simulation time 491522316 ps
CPU time 1.56 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207540 kb
Host smart-365521b4-1eb4-4243-9447-f179473df245
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608202040 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.usbdev_tx_rx_disruption.2608202040
Directory /workspace/152.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/153.usbdev_endpoint_types.2606373403
Short name T2012
Test name
Test status
Simulation time 176671671 ps
CPU time 0.84 seconds
Started Aug 17 06:11:34 PM PDT 24
Finished Aug 17 06:11:35 PM PDT 24
Peak memory 207532 kb
Host smart-a472ac0f-51c1-4d20-98d0-6d236878cca5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2606373403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.2606373403
Directory /workspace/153.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/153.usbdev_tx_rx_disruption.1332739856
Short name T3477
Test name
Test status
Simulation time 458264217 ps
CPU time 1.53 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207516 kb
Host smart-843ac5b8-c6fb-438d-a2d0-bd266a74bf32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332739856 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.usbdev_tx_rx_disruption.1332739856
Directory /workspace/153.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/154.usbdev_endpoint_types.579731640
Short name T1080
Test name
Test status
Simulation time 181364222 ps
CPU time 0.93 seconds
Started Aug 17 06:11:35 PM PDT 24
Finished Aug 17 06:11:36 PM PDT 24
Peak memory 207500 kb
Host smart-289edd08-a86c-4840-8a7d-4f1d2c8c19b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=579731640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.579731640
Directory /workspace/154.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/154.usbdev_tx_rx_disruption.4231655644
Short name T3446
Test name
Test status
Simulation time 492681742 ps
CPU time 1.69 seconds
Started Aug 17 06:11:55 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207432 kb
Host smart-17180af6-0475-4912-814f-53013fa748d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231655644 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.usbdev_tx_rx_disruption.4231655644
Directory /workspace/154.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/155.usbdev_endpoint_types.2122771288
Short name T3105
Test name
Test status
Simulation time 151319814 ps
CPU time 0.89 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:44 PM PDT 24
Peak memory 207532 kb
Host smart-8460e0b5-8476-415c-91f8-28513b8a5518
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2122771288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.2122771288
Directory /workspace/155.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/155.usbdev_tx_rx_disruption.3228004638
Short name T3186
Test name
Test status
Simulation time 495818853 ps
CPU time 1.52 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207544 kb
Host smart-c668981e-1320-4d75-964d-a7a04cc864ce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228004638 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.usbdev_tx_rx_disruption.3228004638
Directory /workspace/155.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/156.usbdev_tx_rx_disruption.3861839531
Short name T624
Test name
Test status
Simulation time 639587085 ps
CPU time 1.75 seconds
Started Aug 17 06:11:38 PM PDT 24
Finished Aug 17 06:11:40 PM PDT 24
Peak memory 207536 kb
Host smart-c45f67ba-b050-4b61-81ba-b4dc450ac94c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861839531 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.usbdev_tx_rx_disruption.3861839531
Directory /workspace/156.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/157.usbdev_endpoint_types.3705936445
Short name T415
Test name
Test status
Simulation time 368121008 ps
CPU time 1.17 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207500 kb
Host smart-b4ed9849-8b41-4e8e-b9fc-e709dac563a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3705936445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.3705936445
Directory /workspace/157.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/157.usbdev_tx_rx_disruption.3737364028
Short name T1999
Test name
Test status
Simulation time 562793260 ps
CPU time 1.64 seconds
Started Aug 17 06:11:48 PM PDT 24
Finished Aug 17 06:11:50 PM PDT 24
Peak memory 207520 kb
Host smart-7147db7f-196f-4485-9e8b-4cf8e95af025
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737364028 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.usbdev_tx_rx_disruption.3737364028
Directory /workspace/157.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/158.usbdev_endpoint_types.1225733799
Short name T425
Test name
Test status
Simulation time 521707573 ps
CPU time 1.33 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:00 PM PDT 24
Peak memory 207488 kb
Host smart-2ed82d72-72bc-4179-88cc-7f61afbb57bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1225733799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.1225733799
Directory /workspace/158.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/158.usbdev_tx_rx_disruption.2194709221
Short name T3590
Test name
Test status
Simulation time 629659510 ps
CPU time 1.91 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207520 kb
Host smart-32430cec-b3cc-40fd-a19a-c7fba1f501f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194709221 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.usbdev_tx_rx_disruption.2194709221
Directory /workspace/158.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/159.usbdev_endpoint_types.281903382
Short name T522
Test name
Test status
Simulation time 222736844 ps
CPU time 1.02 seconds
Started Aug 17 06:11:53 PM PDT 24
Finished Aug 17 06:11:54 PM PDT 24
Peak memory 207496 kb
Host smart-8acb3f0e-fba2-40ff-b1e5-be7ab3a689a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=281903382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.281903382
Directory /workspace/159.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/159.usbdev_tx_rx_disruption.1498699812
Short name T2324
Test name
Test status
Simulation time 494420773 ps
CPU time 1.61 seconds
Started Aug 17 06:11:38 PM PDT 24
Finished Aug 17 06:11:40 PM PDT 24
Peak memory 207596 kb
Host smart-bb47fb7e-f35a-4784-9f52-3f2d2e8ca551
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498699812 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.usbdev_tx_rx_disruption.1498699812
Directory /workspace/159.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2568754618
Short name T1337
Test name
Test status
Simulation time 72039072 ps
CPU time 0.7 seconds
Started Aug 17 06:06:05 PM PDT 24
Finished Aug 17 06:06:05 PM PDT 24
Peak memory 207444 kb
Host smart-42376ae3-4562-4aab-a79d-b0fd6875f309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2568754618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2568754618
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1576447347
Short name T3535
Test name
Test status
Simulation time 8475847152 ps
CPU time 11.01 seconds
Started Aug 17 06:05:49 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207812 kb
Host smart-30852753-a568-46c1-8834-1cb1735f7949
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576447347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.1576447347
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3709239879
Short name T560
Test name
Test status
Simulation time 16197476698 ps
CPU time 20.52 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:19 PM PDT 24
Peak memory 215936 kb
Host smart-b25bf00b-e231-4c39-a976-89ce5ffdb69a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709239879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3709239879
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.4007653026
Short name T1083
Test name
Test status
Simulation time 24929825172 ps
CPU time 32.83 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:32 PM PDT 24
Peak memory 215928 kb
Host smart-e2428ccf-d3d3-45af-a391-32be09f9fc09
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007653026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.4007653026
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.4119271429
Short name T2928
Test name
Test status
Simulation time 150275840 ps
CPU time 0.94 seconds
Started Aug 17 06:05:56 PM PDT 24
Finished Aug 17 06:05:57 PM PDT 24
Peak memory 207460 kb
Host smart-88289600-4156-45fc-a0fb-76cc6385d9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41192
71429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.4119271429
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3770730612
Short name T1599
Test name
Test status
Simulation time 172907789 ps
CPU time 0.89 seconds
Started Aug 17 06:06:02 PM PDT 24
Finished Aug 17 06:06:03 PM PDT 24
Peak memory 207552 kb
Host smart-b2305bed-7400-4008-975e-91b65e320006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37707
30612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3770730612
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1750340157
Short name T668
Test name
Test status
Simulation time 160521191 ps
CPU time 0.93 seconds
Started Aug 17 06:05:58 PM PDT 24
Finished Aug 17 06:05:59 PM PDT 24
Peak memory 207532 kb
Host smart-095e3f1e-8834-4404-afbf-dad1fe654e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17503
40157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1750340157
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3182084257
Short name T1690
Test name
Test status
Simulation time 25478318533 ps
CPU time 39.47 seconds
Started Aug 17 06:05:58 PM PDT 24
Finished Aug 17 06:06:38 PM PDT 24
Peak memory 207728 kb
Host smart-bafac055-0de7-4593-bd66-196e1ea6c298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31820
84257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3182084257
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.959666111
Short name T647
Test name
Test status
Simulation time 2896994705 ps
CPU time 18.53 seconds
Started Aug 17 06:05:58 PM PDT 24
Finished Aug 17 06:06:16 PM PDT 24
Peak memory 207784 kb
Host smart-900c910a-63d8-49bd-bfc2-6f1800df815c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959666111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.959666111
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3481107141
Short name T3111
Test name
Test status
Simulation time 477126875 ps
CPU time 1.49 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207532 kb
Host smart-53b67d6f-75e2-4c4d-8fc4-3c07ad0e0f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34811
07141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3481107141
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1389152800
Short name T2204
Test name
Test status
Simulation time 158470446 ps
CPU time 0.9 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207508 kb
Host smart-3ebc3540-7b4a-478e-8b4e-387c19339854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13891
52800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1389152800
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.2044449553
Short name T2873
Test name
Test status
Simulation time 28417456 ps
CPU time 0.71 seconds
Started Aug 17 06:05:58 PM PDT 24
Finished Aug 17 06:05:59 PM PDT 24
Peak memory 207484 kb
Host smart-6c8628c2-4d39-4c5b-989b-438fc3210908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
49553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2044449553
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2579152896
Short name T3557
Test name
Test status
Simulation time 935733452 ps
CPU time 2.79 seconds
Started Aug 17 06:05:57 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207780 kb
Host smart-566dad1d-45e7-4221-9e4e-7bf00858c062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25791
52896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2579152896
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_types.3784048314
Short name T3261
Test name
Test status
Simulation time 302454333 ps
CPU time 1.06 seconds
Started Aug 17 06:05:56 PM PDT 24
Finished Aug 17 06:05:57 PM PDT 24
Peak memory 207456 kb
Host smart-40da0596-018c-4374-977e-8c1a72f9e54d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3784048314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.3784048314
Directory /workspace/16.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2526525878
Short name T2798
Test name
Test status
Simulation time 348633755 ps
CPU time 2.43 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:02 PM PDT 24
Peak memory 207616 kb
Host smart-e53819a8-5bbd-4512-9464-1d19087118db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25265
25878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2526525878
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.128045032
Short name T2906
Test name
Test status
Simulation time 218099996 ps
CPU time 1.14 seconds
Started Aug 17 06:05:58 PM PDT 24
Finished Aug 17 06:05:59 PM PDT 24
Peak memory 215872 kb
Host smart-6b41ff44-82dc-484a-b68e-d95ec692e78f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=128045032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.128045032
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3874076566
Short name T947
Test name
Test status
Simulation time 145892581 ps
CPU time 0.86 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207384 kb
Host smart-5f9a8b7e-7434-4331-a912-8130705064e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38740
76566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3874076566
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4254485116
Short name T852
Test name
Test status
Simulation time 198782736 ps
CPU time 1.05 seconds
Started Aug 17 06:06:02 PM PDT 24
Finished Aug 17 06:06:03 PM PDT 24
Peak memory 207504 kb
Host smart-c0bf9863-15b9-4f51-b410-d9d87888b2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42544
85116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4254485116
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.1633954676
Short name T3416
Test name
Test status
Simulation time 4060348612 ps
CPU time 124.98 seconds
Started Aug 17 06:05:57 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 224152 kb
Host smart-494d4932-e954-460c-b3bb-389f1c94fb95
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1633954676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1633954676
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.4060169593
Short name T1659
Test name
Test status
Simulation time 9545649095 ps
CPU time 74.13 seconds
Started Aug 17 06:06:00 PM PDT 24
Finished Aug 17 06:07:14 PM PDT 24
Peak memory 207780 kb
Host smart-3f5ec902-8b3c-4aba-8351-f65d68570225
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4060169593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.4060169593
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1311985031
Short name T3022
Test name
Test status
Simulation time 206168023 ps
CPU time 0.94 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207560 kb
Host smart-ed2dcfc5-008a-429b-a56a-eb0b50965b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13119
85031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1311985031
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1331627546
Short name T1210
Test name
Test status
Simulation time 11289164261 ps
CPU time 16.3 seconds
Started Aug 17 06:05:58 PM PDT 24
Finished Aug 17 06:06:15 PM PDT 24
Peak memory 207788 kb
Host smart-ef494fdf-12e8-4f86-9478-fa1d12eb93d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13316
27546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1331627546
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1628309915
Short name T3250
Test name
Test status
Simulation time 4223182056 ps
CPU time 5.71 seconds
Started Aug 17 06:05:56 PM PDT 24
Finished Aug 17 06:06:02 PM PDT 24
Peak memory 207756 kb
Host smart-ec9e5764-9973-42f1-bc8e-725c8f45ca3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16283
09915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1628309915
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1114526014
Short name T383
Test name
Test status
Simulation time 4818285356 ps
CPU time 143.69 seconds
Started Aug 17 06:06:02 PM PDT 24
Finished Aug 17 06:08:26 PM PDT 24
Peak memory 224156 kb
Host smart-f2116914-cd4a-4a04-95ba-d75d8c039d3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1114526014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1114526014
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1698215192
Short name T1438
Test name
Test status
Simulation time 2811970691 ps
CPU time 29.11 seconds
Started Aug 17 06:06:00 PM PDT 24
Finished Aug 17 06:06:30 PM PDT 24
Peak memory 215932 kb
Host smart-5a5ecb43-b319-482f-986a-1550615a7a23
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1698215192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1698215192
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.4188198574
Short name T732
Test name
Test status
Simulation time 237626392 ps
CPU time 1.05 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:01 PM PDT 24
Peak memory 207412 kb
Host smart-d78a7e36-c71a-421b-afd3-763acf9a64bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4188198574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.4188198574
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3946502507
Short name T2587
Test name
Test status
Simulation time 183912382 ps
CPU time 0.96 seconds
Started Aug 17 06:06:00 PM PDT 24
Finished Aug 17 06:06:01 PM PDT 24
Peak memory 207484 kb
Host smart-5c39c6da-8f76-4a90-aeae-c79f44b4e4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39465
02507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3946502507
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.1193567466
Short name T3589
Test name
Test status
Simulation time 2135640057 ps
CPU time 18.29 seconds
Started Aug 17 06:05:58 PM PDT 24
Finished Aug 17 06:06:16 PM PDT 24
Peak memory 217592 kb
Host smart-3d8c90c3-9306-4af3-ad1e-fa00a383ee7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11935
67466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.1193567466
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1909352570
Short name T2924
Test name
Test status
Simulation time 1972385480 ps
CPU time 58.72 seconds
Started Aug 17 06:05:57 PM PDT 24
Finished Aug 17 06:06:56 PM PDT 24
Peak memory 224004 kb
Host smart-41fe8c6b-485f-415d-b2dc-016cf28102ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1909352570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1909352570
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1298972471
Short name T1020
Test name
Test status
Simulation time 170020670 ps
CPU time 0.97 seconds
Started Aug 17 06:06:02 PM PDT 24
Finished Aug 17 06:06:03 PM PDT 24
Peak memory 207516 kb
Host smart-573ef525-95a2-431b-8a44-4ed943bce1e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1298972471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1298972471
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3355702173
Short name T2254
Test name
Test status
Simulation time 166989607 ps
CPU time 0.86 seconds
Started Aug 17 06:06:00 PM PDT 24
Finished Aug 17 06:06:01 PM PDT 24
Peak memory 207456 kb
Host smart-e72e2a92-42dd-45e9-8767-68a0c6a4def1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33557
02173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3355702173
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.4266941081
Short name T3217
Test name
Test status
Simulation time 213038688 ps
CPU time 0.98 seconds
Started Aug 17 06:06:00 PM PDT 24
Finished Aug 17 06:06:01 PM PDT 24
Peak memory 207460 kb
Host smart-8c34af0b-65f3-4609-829e-476069ca6b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42669
41081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.4266941081
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2544343341
Short name T1371
Test name
Test status
Simulation time 167603148 ps
CPU time 0.85 seconds
Started Aug 17 06:05:58 PM PDT 24
Finished Aug 17 06:05:59 PM PDT 24
Peak memory 207496 kb
Host smart-6407cc97-505a-42af-be02-4d726a67d501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25443
43341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2544343341
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.25333431
Short name T1636
Test name
Test status
Simulation time 169621766 ps
CPU time 0.92 seconds
Started Aug 17 06:06:02 PM PDT 24
Finished Aug 17 06:06:03 PM PDT 24
Peak memory 207512 kb
Host smart-17bab8e3-49b6-4327-ae40-fa31321ebd8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25333
431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.25333431
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2878661025
Short name T3494
Test name
Test status
Simulation time 214964089 ps
CPU time 0.95 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:00 PM PDT 24
Peak memory 207564 kb
Host smart-6335149b-6e9d-4d21-a256-b80af1942c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28786
61025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2878661025
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3192092996
Short name T183
Test name
Test status
Simulation time 163713222 ps
CPU time 0.9 seconds
Started Aug 17 06:06:07 PM PDT 24
Finished Aug 17 06:06:08 PM PDT 24
Peak memory 207536 kb
Host smart-9c963f66-713c-4a91-b16c-a73026e0ae23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31920
92996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3192092996
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2200411931
Short name T2182
Test name
Test status
Simulation time 202650796 ps
CPU time 0.96 seconds
Started Aug 17 06:06:06 PM PDT 24
Finished Aug 17 06:06:07 PM PDT 24
Peak memory 207556 kb
Host smart-17d3292e-c450-403a-b733-30ad211a8bd6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2200411931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2200411931
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3722079903
Short name T1491
Test name
Test status
Simulation time 141224513 ps
CPU time 0.86 seconds
Started Aug 17 06:06:06 PM PDT 24
Finished Aug 17 06:06:07 PM PDT 24
Peak memory 207484 kb
Host smart-62437930-e76f-4e18-b742-2e17be17f293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37220
79903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3722079903
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.701061081
Short name T930
Test name
Test status
Simulation time 38372139 ps
CPU time 0.68 seconds
Started Aug 17 06:06:05 PM PDT 24
Finished Aug 17 06:06:06 PM PDT 24
Peak memory 207524 kb
Host smart-f237e8ec-0787-4eb3-9ee5-27dcda2cef5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70106
1081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.701061081
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.873108738
Short name T3586
Test name
Test status
Simulation time 15124465391 ps
CPU time 42.21 seconds
Started Aug 17 06:06:08 PM PDT 24
Finished Aug 17 06:06:50 PM PDT 24
Peak memory 220464 kb
Host smart-a66d5b94-cf06-4ae3-8871-f82606528769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87310
8738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.873108738
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3023685319
Short name T1684
Test name
Test status
Simulation time 159699957 ps
CPU time 0.94 seconds
Started Aug 17 06:06:06 PM PDT 24
Finished Aug 17 06:06:07 PM PDT 24
Peak memory 207548 kb
Host smart-eec156d0-756c-49e3-bf6c-7464e349fb56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30236
85319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3023685319
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.4043140783
Short name T3185
Test name
Test status
Simulation time 159753967 ps
CPU time 0.9 seconds
Started Aug 17 06:06:05 PM PDT 24
Finished Aug 17 06:06:06 PM PDT 24
Peak memory 207456 kb
Host smart-984ebd29-a320-4603-8e3a-1a27640b8a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40431
40783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.4043140783
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1988565682
Short name T1076
Test name
Test status
Simulation time 215755335 ps
CPU time 0.98 seconds
Started Aug 17 06:06:05 PM PDT 24
Finished Aug 17 06:06:06 PM PDT 24
Peak memory 207488 kb
Host smart-301120f2-92aa-4721-abb7-ca4b66044b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19885
65682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1988565682
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1667719765
Short name T3559
Test name
Test status
Simulation time 195627509 ps
CPU time 0.96 seconds
Started Aug 17 06:06:06 PM PDT 24
Finished Aug 17 06:06:07 PM PDT 24
Peak memory 207428 kb
Host smart-72c4fb03-0bcf-4bc4-ac4f-0ece73191815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16677
19765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1667719765
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_resume_link_active.2228888694
Short name T1600
Test name
Test status
Simulation time 20186953986 ps
CPU time 28.5 seconds
Started Aug 17 06:06:05 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207560 kb
Host smart-e6a1942f-6c0b-4f14-b71e-136bdbade608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22288
88694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.2228888694
Directory /workspace/16.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/16.usbdev_rx_full.3603725933
Short name T2022
Test name
Test status
Simulation time 245131008 ps
CPU time 1.08 seconds
Started Aug 17 06:06:06 PM PDT 24
Finished Aug 17 06:06:07 PM PDT 24
Peak memory 207460 kb
Host smart-477af8ba-d741-417f-89dd-367d2d0c0520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36037
25933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.3603725933
Directory /workspace/16.usbdev_rx_full/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3479894182
Short name T3279
Test name
Test status
Simulation time 173870587 ps
CPU time 0.89 seconds
Started Aug 17 06:06:05 PM PDT 24
Finished Aug 17 06:06:06 PM PDT 24
Peak memory 207516 kb
Host smart-3db8663b-2580-4f7c-a098-b9f2606c806e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34798
94182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3479894182
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.659598043
Short name T1796
Test name
Test status
Simulation time 185293363 ps
CPU time 0.92 seconds
Started Aug 17 06:06:07 PM PDT 24
Finished Aug 17 06:06:08 PM PDT 24
Peak memory 207560 kb
Host smart-9f5e1726-f7d3-4af7-9a85-69fa5ab4f02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65959
8043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.659598043
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1188217016
Short name T755
Test name
Test status
Simulation time 242322536 ps
CPU time 1.11 seconds
Started Aug 17 06:06:16 PM PDT 24
Finished Aug 17 06:06:17 PM PDT 24
Peak memory 207428 kb
Host smart-32da2773-559c-4f1a-b525-6f03a7f09ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11882
17016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1188217016
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1501672334
Short name T2754
Test name
Test status
Simulation time 2489367677 ps
CPU time 76.79 seconds
Started Aug 17 06:06:06 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 224028 kb
Host smart-f3d3660f-f82d-4dfe-a1b9-7beb32c8f6c6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1501672334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1501672334
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2427591588
Short name T2866
Test name
Test status
Simulation time 147183376 ps
CPU time 0.81 seconds
Started Aug 17 06:06:08 PM PDT 24
Finished Aug 17 06:06:08 PM PDT 24
Peak memory 207500 kb
Host smart-0c0f6b5d-9461-4599-b9b3-cb124ea7265d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24275
91588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2427591588
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3552548559
Short name T2574
Test name
Test status
Simulation time 179255739 ps
CPU time 0.95 seconds
Started Aug 17 06:06:08 PM PDT 24
Finished Aug 17 06:06:09 PM PDT 24
Peak memory 207476 kb
Host smart-d9e717e9-f67b-4379-85ad-0e88a57dbaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35525
48559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3552548559
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.1896325940
Short name T1907
Test name
Test status
Simulation time 1354228687 ps
CPU time 3.17 seconds
Started Aug 17 06:06:02 PM PDT 24
Finished Aug 17 06:06:06 PM PDT 24
Peak memory 207696 kb
Host smart-09416edc-34ab-4b92-a0cf-35ec7438b2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18963
25940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.1896325940
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.4242329552
Short name T3025
Test name
Test status
Simulation time 4356389870 ps
CPU time 46.45 seconds
Started Aug 17 06:06:08 PM PDT 24
Finished Aug 17 06:06:54 PM PDT 24
Peak memory 216008 kb
Host smart-3cfb3e62-aabc-429c-a5b3-0d35bb5dcf24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42423
29552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.4242329552
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.59978127
Short name T3061
Test name
Test status
Simulation time 3463410547 ps
CPU time 28.24 seconds
Started Aug 17 06:05:59 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207680 kb
Host smart-40bfee1f-14e6-450b-8855-3ae1f21fa0eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59978127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_host_
handshake.59978127
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_tx_rx_disruption.1378760310
Short name T3284
Test name
Test status
Simulation time 580311459 ps
CPU time 1.57 seconds
Started Aug 17 06:06:06 PM PDT 24
Finished Aug 17 06:06:07 PM PDT 24
Peak memory 207516 kb
Host smart-27509255-27ef-4e6d-934a-b35a736e5da4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378760310 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.usbdev_tx_rx_disruption.1378760310
Directory /workspace/16.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/160.usbdev_tx_rx_disruption.539727132
Short name T1874
Test name
Test status
Simulation time 501704844 ps
CPU time 1.8 seconds
Started Aug 17 06:11:39 PM PDT 24
Finished Aug 17 06:11:41 PM PDT 24
Peak memory 207576 kb
Host smart-3da1bc2a-c225-4f8a-a851-39fef2a5244e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539727132 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 160.usbdev_tx_rx_disruption.539727132
Directory /workspace/160.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/161.usbdev_endpoint_types.2214171498
Short name T3459
Test name
Test status
Simulation time 240073868 ps
CPU time 1.03 seconds
Started Aug 17 06:11:37 PM PDT 24
Finished Aug 17 06:11:38 PM PDT 24
Peak memory 207516 kb
Host smart-72bf729e-eb0b-4f59-a941-af93177f0281
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2214171498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.2214171498
Directory /workspace/161.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/161.usbdev_tx_rx_disruption.635572121
Short name T2573
Test name
Test status
Simulation time 600755572 ps
CPU time 1.73 seconds
Started Aug 17 06:11:38 PM PDT 24
Finished Aug 17 06:11:40 PM PDT 24
Peak memory 207552 kb
Host smart-1a050768-e58f-4d77-8b8f-87cae7466ac3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635572121 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 161.usbdev_tx_rx_disruption.635572121
Directory /workspace/161.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/162.usbdev_endpoint_types.1650748389
Short name T411
Test name
Test status
Simulation time 670727856 ps
CPU time 1.58 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207500 kb
Host smart-92ea11e3-a3ac-48ef-a2eb-1ec801a995e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1650748389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.1650748389
Directory /workspace/162.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/162.usbdev_tx_rx_disruption.3188697463
Short name T2576
Test name
Test status
Simulation time 556844650 ps
CPU time 1.67 seconds
Started Aug 17 06:11:40 PM PDT 24
Finished Aug 17 06:11:42 PM PDT 24
Peak memory 207520 kb
Host smart-50573601-c158-4252-9082-3d285d35a1ce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188697463 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.usbdev_tx_rx_disruption.3188697463
Directory /workspace/162.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/163.usbdev_endpoint_types.3089211951
Short name T3194
Test name
Test status
Simulation time 443559277 ps
CPU time 1.34 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207468 kb
Host smart-cf1c5018-618d-479c-b8c4-9df01629023b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3089211951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.3089211951
Directory /workspace/163.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/163.usbdev_tx_rx_disruption.2421528798
Short name T3068
Test name
Test status
Simulation time 448621461 ps
CPU time 1.47 seconds
Started Aug 17 06:11:35 PM PDT 24
Finished Aug 17 06:11:36 PM PDT 24
Peak memory 207540 kb
Host smart-613ac967-fe98-4e57-9e45-d9815ef1af0f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421528798 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.usbdev_tx_rx_disruption.2421528798
Directory /workspace/163.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/164.usbdev_endpoint_types.1270343973
Short name T2715
Test name
Test status
Simulation time 182805753 ps
CPU time 0.98 seconds
Started Aug 17 06:11:53 PM PDT 24
Finished Aug 17 06:11:54 PM PDT 24
Peak memory 207580 kb
Host smart-cdf5479d-96f4-4b26-98ae-341472986ff6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1270343973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.1270343973
Directory /workspace/164.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/164.usbdev_tx_rx_disruption.2248455278
Short name T2442
Test name
Test status
Simulation time 491093857 ps
CPU time 1.56 seconds
Started Aug 17 06:11:47 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207568 kb
Host smart-850b960e-dab9-446a-af41-c872083ee117
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248455278 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.usbdev_tx_rx_disruption.2248455278
Directory /workspace/164.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/165.usbdev_endpoint_types.1033313713
Short name T506
Test name
Test status
Simulation time 195953948 ps
CPU time 0.98 seconds
Started Aug 17 06:11:34 PM PDT 24
Finished Aug 17 06:11:35 PM PDT 24
Peak memory 207520 kb
Host smart-5d774542-633f-4876-8c6b-4eef1d4c0eb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1033313713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.1033313713
Directory /workspace/165.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/165.usbdev_tx_rx_disruption.869033893
Short name T3018
Test name
Test status
Simulation time 460712926 ps
CPU time 1.56 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207520 kb
Host smart-e386ee38-5603-4444-b483-0c954d979f48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869033893 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 165.usbdev_tx_rx_disruption.869033893
Directory /workspace/165.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/166.usbdev_endpoint_types.3474971143
Short name T498
Test name
Test status
Simulation time 418014301 ps
CPU time 1.37 seconds
Started Aug 17 06:11:37 PM PDT 24
Finished Aug 17 06:11:38 PM PDT 24
Peak memory 207544 kb
Host smart-9a97bbbd-d264-497f-a479-4a10b68ac005
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3474971143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.3474971143
Directory /workspace/166.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/166.usbdev_tx_rx_disruption.13622021
Short name T1179
Test name
Test status
Simulation time 466600577 ps
CPU time 1.45 seconds
Started Aug 17 06:11:34 PM PDT 24
Finished Aug 17 06:11:35 PM PDT 24
Peak memory 207552 kb
Host smart-58679e68-fb02-465c-ade3-862d230ecc65
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13622021 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 166.usbdev_tx_rx_disruption.13622021
Directory /workspace/166.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/167.usbdev_endpoint_types.3298241376
Short name T3224
Test name
Test status
Simulation time 347239853 ps
CPU time 1.16 seconds
Started Aug 17 06:11:55 PM PDT 24
Finished Aug 17 06:11:56 PM PDT 24
Peak memory 207464 kb
Host smart-ead3c522-5036-44c8-be5a-67dac50f1883
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3298241376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.3298241376
Directory /workspace/167.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/167.usbdev_tx_rx_disruption.3492498409
Short name T1340
Test name
Test status
Simulation time 503378872 ps
CPU time 1.52 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207488 kb
Host smart-01786eb1-fd06-4b98-be53-ec7dd2db07e3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492498409 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.usbdev_tx_rx_disruption.3492498409
Directory /workspace/167.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/168.usbdev_endpoint_types.3944713288
Short name T3497
Test name
Test status
Simulation time 161535622 ps
CPU time 0.88 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207496 kb
Host smart-743b449b-d769-419e-a567-c3c03c280ea3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3944713288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.3944713288
Directory /workspace/168.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/169.usbdev_endpoint_types.2126989613
Short name T492
Test name
Test status
Simulation time 181681775 ps
CPU time 0.99 seconds
Started Aug 17 06:11:36 PM PDT 24
Finished Aug 17 06:11:37 PM PDT 24
Peak memory 207564 kb
Host smart-debf1f97-ffb7-4ee3-81b4-5fa6f838e2a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2126989613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.2126989613
Directory /workspace/169.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/169.usbdev_tx_rx_disruption.403544886
Short name T40
Test name
Test status
Simulation time 546759431 ps
CPU time 1.69 seconds
Started Aug 17 06:11:36 PM PDT 24
Finished Aug 17 06:11:37 PM PDT 24
Peak memory 207556 kb
Host smart-f9848f20-da6e-4c54-8a97-69a0207bae26
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403544886 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 169.usbdev_tx_rx_disruption.403544886
Directory /workspace/169.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.958021810
Short name T1106
Test name
Test status
Simulation time 33711175 ps
CPU time 0.69 seconds
Started Aug 17 06:06:20 PM PDT 24
Finished Aug 17 06:06:21 PM PDT 24
Peak memory 207360 kb
Host smart-b1dd9445-ba91-4018-ab05-00f8494ad1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=958021810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.958021810
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.147152294
Short name T1355
Test name
Test status
Simulation time 4434449093 ps
CPU time 6.51 seconds
Started Aug 17 06:06:03 PM PDT 24
Finished Aug 17 06:06:10 PM PDT 24
Peak memory 215868 kb
Host smart-7e30d0aa-3232-4a48-acf4-0a04412d9436
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147152294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_disconnect.147152294
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3318288156
Short name T917
Test name
Test status
Simulation time 13928865935 ps
CPU time 16.17 seconds
Started Aug 17 06:06:05 PM PDT 24
Finished Aug 17 06:06:22 PM PDT 24
Peak memory 215952 kb
Host smart-d4d4c612-b91e-4e2c-b9f4-21d56a3490b7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318288156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3318288156
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2257868640
Short name T2350
Test name
Test status
Simulation time 29911303245 ps
CPU time 36.11 seconds
Started Aug 17 06:06:05 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 207780 kb
Host smart-b21696d7-23f5-452f-8a22-84132b6f8597
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257868640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.2257868640
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3290903586
Short name T1899
Test name
Test status
Simulation time 161779375 ps
CPU time 0.88 seconds
Started Aug 17 06:06:16 PM PDT 24
Finished Aug 17 06:06:17 PM PDT 24
Peak memory 207424 kb
Host smart-cdef2a0f-f3d9-4d20-bfd1-f39ef45b4108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32909
03586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3290903586
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.888920234
Short name T2218
Test name
Test status
Simulation time 181186276 ps
CPU time 0.88 seconds
Started Aug 17 06:06:08 PM PDT 24
Finished Aug 17 06:06:09 PM PDT 24
Peak memory 207564 kb
Host smart-d5d717fa-b490-47e3-9324-14578f1f2388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88892
0234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.888920234
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1952064100
Short name T1722
Test name
Test status
Simulation time 280233898 ps
CPU time 1.25 seconds
Started Aug 17 06:06:16 PM PDT 24
Finished Aug 17 06:06:18 PM PDT 24
Peak memory 207508 kb
Host smart-77abf4f5-d02f-4d11-860d-65e28b73ddf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19520
64100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1952064100
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2578041124
Short name T2433
Test name
Test status
Simulation time 692609945 ps
CPU time 2.17 seconds
Started Aug 17 06:06:08 PM PDT 24
Finished Aug 17 06:06:11 PM PDT 24
Peak memory 207456 kb
Host smart-c5bda8b9-e2d6-40a1-b3b9-6bdc6dbc8fdb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2578041124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2578041124
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.1138017100
Short name T3137
Test name
Test status
Simulation time 39525132961 ps
CPU time 61.86 seconds
Started Aug 17 06:06:16 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 207736 kb
Host smart-0efb1609-fd34-468d-bbe3-7e9d5c59010f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11380
17100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.1138017100
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.3555206481
Short name T2321
Test name
Test status
Simulation time 1129961306 ps
CPU time 25.58 seconds
Started Aug 17 06:06:07 PM PDT 24
Finished Aug 17 06:06:32 PM PDT 24
Peak memory 207704 kb
Host smart-722d8d8a-dbd4-4dd7-8943-4cbf799b6e08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555206481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.3555206481
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.4197740647
Short name T1279
Test name
Test status
Simulation time 701879216 ps
CPU time 1.74 seconds
Started Aug 17 06:06:03 PM PDT 24
Finished Aug 17 06:06:05 PM PDT 24
Peak memory 207532 kb
Host smart-180a6fab-5ae6-4cc0-82af-fd3290a2e8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41977
40647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.4197740647
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_enable.2661012638
Short name T2247
Test name
Test status
Simulation time 58674886 ps
CPU time 0.76 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:18 PM PDT 24
Peak memory 207364 kb
Host smart-5d841949-34f5-4cf7-97e3-5a77bc3da373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26610
12638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2661012638
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1773676910
Short name T864
Test name
Test status
Simulation time 743397878 ps
CPU time 2.1 seconds
Started Aug 17 06:06:07 PM PDT 24
Finished Aug 17 06:06:09 PM PDT 24
Peak memory 207764 kb
Host smart-910266e8-b956-4804-a9c0-b74e2a265ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17736
76910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1773676910
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_types.102929542
Short name T468
Test name
Test status
Simulation time 242220385 ps
CPU time 1.13 seconds
Started Aug 17 06:06:06 PM PDT 24
Finished Aug 17 06:06:08 PM PDT 24
Peak memory 207528 kb
Host smart-4ec696d7-28ac-4eb3-93a6-633cef7bb164
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=102929542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.102929542
Directory /workspace/17.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3027285162
Short name T3268
Test name
Test status
Simulation time 170518632 ps
CPU time 1.91 seconds
Started Aug 17 06:06:04 PM PDT 24
Finished Aug 17 06:06:06 PM PDT 24
Peak memory 207616 kb
Host smart-2a338431-d1b3-44be-8c26-6de1b9e518f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30272
85162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3027285162
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.4227917957
Short name T1955
Test name
Test status
Simulation time 180470551 ps
CPU time 0.96 seconds
Started Aug 17 06:06:07 PM PDT 24
Finished Aug 17 06:06:08 PM PDT 24
Peak memory 215880 kb
Host smart-82555e2b-e041-42f7-ba0b-54815949b8a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4227917957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.4227917957
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2807179986
Short name T847
Test name
Test status
Simulation time 145965517 ps
CPU time 0.82 seconds
Started Aug 17 06:06:09 PM PDT 24
Finished Aug 17 06:06:10 PM PDT 24
Peak memory 207436 kb
Host smart-d3106357-97a1-4528-a753-32981c0e5735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28071
79986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2807179986
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1787353619
Short name T1364
Test name
Test status
Simulation time 195515044 ps
CPU time 0.95 seconds
Started Aug 17 06:06:16 PM PDT 24
Finished Aug 17 06:06:17 PM PDT 24
Peak memory 207460 kb
Host smart-6d19fe39-4d68-47da-a20f-2666c40b4976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17873
53619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1787353619
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.692778058
Short name T1790
Test name
Test status
Simulation time 3389020656 ps
CPU time 99.75 seconds
Started Aug 17 06:06:09 PM PDT 24
Finished Aug 17 06:07:49 PM PDT 24
Peak memory 218284 kb
Host smart-7f5319af-dcd8-4862-831a-c8acd51c8dd3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=692778058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.692778058
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.949479394
Short name T3540
Test name
Test status
Simulation time 9466607199 ps
CPU time 71.47 seconds
Started Aug 17 06:06:19 PM PDT 24
Finished Aug 17 06:07:30 PM PDT 24
Peak memory 207836 kb
Host smart-af3958e4-8b12-4507-b74e-4f4015c8216a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=949479394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.949479394
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3618237565
Short name T1174
Test name
Test status
Simulation time 227037352 ps
CPU time 1.06 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:18 PM PDT 24
Peak memory 207536 kb
Host smart-b500ce0a-972a-4e84-a932-77780ec2ede2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36182
37565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3618237565
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2233707911
Short name T2031
Test name
Test status
Simulation time 31326342234 ps
CPU time 51.56 seconds
Started Aug 17 06:06:16 PM PDT 24
Finished Aug 17 06:07:08 PM PDT 24
Peak memory 207724 kb
Host smart-6473e2e9-4cca-4ba2-a19d-75191efc70e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22337
07911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2233707911
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.890297832
Short name T3026
Test name
Test status
Simulation time 9876318692 ps
CPU time 13.98 seconds
Started Aug 17 06:06:18 PM PDT 24
Finished Aug 17 06:06:32 PM PDT 24
Peak memory 207764 kb
Host smart-db44a14f-d66f-4823-b9b7-a5cf0bc13865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89029
7832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.890297832
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1728570047
Short name T2162
Test name
Test status
Simulation time 4959381245 ps
CPU time 58.68 seconds
Started Aug 17 06:06:19 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 218864 kb
Host smart-ba8265db-dc5a-4cc8-8adf-fb3ce6fbec66
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1728570047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1728570047
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.858879458
Short name T2851
Test name
Test status
Simulation time 2503514779 ps
CPU time 20.63 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:38 PM PDT 24
Peak memory 217716 kb
Host smart-4a40b428-8798-492e-a3c4-ed5d7b072d8e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=858879458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.858879458
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1640916134
Short name T1248
Test name
Test status
Simulation time 265705621 ps
CPU time 1.09 seconds
Started Aug 17 06:06:22 PM PDT 24
Finished Aug 17 06:06:23 PM PDT 24
Peak memory 207420 kb
Host smart-824f02b4-b55a-47fc-8172-a53b1a9ed9da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1640916134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1640916134
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.830448205
Short name T2737
Test name
Test status
Simulation time 189975057 ps
CPU time 1 seconds
Started Aug 17 06:06:19 PM PDT 24
Finished Aug 17 06:06:20 PM PDT 24
Peak memory 207456 kb
Host smart-94691b44-3cd7-4511-973d-567f6ac3cac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83044
8205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.830448205
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.702594867
Short name T1384
Test name
Test status
Simulation time 3447248946 ps
CPU time 99.32 seconds
Started Aug 17 06:06:16 PM PDT 24
Finished Aug 17 06:07:55 PM PDT 24
Peak memory 224004 kb
Host smart-87ea56a8-82e3-4524-aef5-e437e04fb25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70259
4867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.702594867
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1067116851
Short name T2399
Test name
Test status
Simulation time 1675841484 ps
CPU time 16.47 seconds
Started Aug 17 06:06:18 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 223996 kb
Host smart-6003bd63-596d-4a71-943d-d27f061da585
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1067116851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1067116851
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.648706612
Short name T909
Test name
Test status
Simulation time 152201836 ps
CPU time 0.89 seconds
Started Aug 17 06:06:19 PM PDT 24
Finished Aug 17 06:06:20 PM PDT 24
Peak memory 207488 kb
Host smart-ed890e3a-4025-4671-84a0-0898c3cd3709
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=648706612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.648706612
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2097374343
Short name T3106
Test name
Test status
Simulation time 174854199 ps
CPU time 0.93 seconds
Started Aug 17 06:06:18 PM PDT 24
Finished Aug 17 06:06:19 PM PDT 24
Peak memory 207388 kb
Host smart-344fe1c3-2223-46ba-ab8c-ee90f15606f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20973
74343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2097374343
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3518082733
Short name T134
Test name
Test status
Simulation time 244336732 ps
CPU time 1.04 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:18 PM PDT 24
Peak memory 207484 kb
Host smart-110528e2-0616-4f83-91f6-d5423c034a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35180
82733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3518082733
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.149093372
Short name T918
Test name
Test status
Simulation time 195995073 ps
CPU time 0.95 seconds
Started Aug 17 06:06:20 PM PDT 24
Finished Aug 17 06:06:21 PM PDT 24
Peak memory 207476 kb
Host smart-5e1231d8-a82a-4c4a-9b63-eb6cae6614ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14909
3372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.149093372
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3055830087
Short name T762
Test name
Test status
Simulation time 174140309 ps
CPU time 0.93 seconds
Started Aug 17 06:06:19 PM PDT 24
Finished Aug 17 06:06:20 PM PDT 24
Peak memory 207532 kb
Host smart-b2ef9fd1-cc66-47d5-a112-5d9118522716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30558
30087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3055830087
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1141357725
Short name T880
Test name
Test status
Simulation time 240026136 ps
CPU time 1.07 seconds
Started Aug 17 06:06:15 PM PDT 24
Finished Aug 17 06:06:17 PM PDT 24
Peak memory 207444 kb
Host smart-fe395754-256c-4aa2-a0f0-60d31d8cb385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11413
57725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1141357725
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.602804829
Short name T3251
Test name
Test status
Simulation time 164052939 ps
CPU time 0.85 seconds
Started Aug 17 06:06:19 PM PDT 24
Finished Aug 17 06:06:20 PM PDT 24
Peak memory 207540 kb
Host smart-629f3e39-876f-47af-be94-a75416d503a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60280
4829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.602804829
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3790410702
Short name T740
Test name
Test status
Simulation time 239665026 ps
CPU time 1.06 seconds
Started Aug 17 06:06:20 PM PDT 24
Finished Aug 17 06:06:21 PM PDT 24
Peak memory 207540 kb
Host smart-c8a7593b-f583-47de-b83e-00d3d3c860d2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3790410702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3790410702
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4276067054
Short name T3617
Test name
Test status
Simulation time 181374363 ps
CPU time 0.89 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:18 PM PDT 24
Peak memory 207452 kb
Host smart-c6d7b4ab-5f66-4cad-a8fe-f6d4158e585d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42760
67054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4276067054
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.4199488010
Short name T3450
Test name
Test status
Simulation time 42308998 ps
CPU time 0.72 seconds
Started Aug 17 06:06:16 PM PDT 24
Finished Aug 17 06:06:17 PM PDT 24
Peak memory 207520 kb
Host smart-14d58c91-9601-44d8-84f1-cb8801e125ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41994
88010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.4199488010
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.796677884
Short name T2752
Test name
Test status
Simulation time 18042141552 ps
CPU time 42.41 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:07:00 PM PDT 24
Peak memory 215876 kb
Host smart-7d05022f-c69d-4b3c-9568-9b5f58e664db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79667
7884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.796677884
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.571055115
Short name T1627
Test name
Test status
Simulation time 166042971 ps
CPU time 0.91 seconds
Started Aug 17 06:06:22 PM PDT 24
Finished Aug 17 06:06:24 PM PDT 24
Peak memory 207504 kb
Host smart-6fec76cf-5040-4584-8d54-d22b90344e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57105
5115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.571055115
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3151268657
Short name T2069
Test name
Test status
Simulation time 152376161 ps
CPU time 0.85 seconds
Started Aug 17 06:06:21 PM PDT 24
Finished Aug 17 06:06:22 PM PDT 24
Peak memory 207472 kb
Host smart-7970536c-e44a-47fb-98db-c98f7c84a8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31512
68657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3151268657
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2789116116
Short name T1395
Test name
Test status
Simulation time 197804802 ps
CPU time 0.95 seconds
Started Aug 17 06:06:18 PM PDT 24
Finished Aug 17 06:06:19 PM PDT 24
Peak memory 207440 kb
Host smart-7c3db446-83ab-407b-81fe-f9e42dfb69bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27891
16116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2789116116
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3918058794
Short name T2868
Test name
Test status
Simulation time 164288605 ps
CPU time 0.93 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:18 PM PDT 24
Peak memory 207480 kb
Host smart-8b08af33-9f58-4fb1-9822-db0701267ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39180
58794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3918058794
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_resume_link_active.3531156256
Short name T3528
Test name
Test status
Simulation time 20163301377 ps
CPU time 24.63 seconds
Started Aug 17 06:06:16 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 207536 kb
Host smart-b1aacaad-93f7-483b-acd4-6a59b2fbab76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35311
56256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.3531156256
Directory /workspace/17.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.892102496
Short name T2051
Test name
Test status
Simulation time 169746386 ps
CPU time 0.97 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:18 PM PDT 24
Peak memory 207464 kb
Host smart-ae281bfb-3365-474d-88b3-d6670fe4aba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89210
2496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.892102496
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_rx_full.1243142934
Short name T596
Test name
Test status
Simulation time 344334603 ps
CPU time 1.35 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:19 PM PDT 24
Peak memory 207460 kb
Host smart-c3c655df-8f8b-407c-9226-f32fedbc022b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12431
42934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.1243142934
Directory /workspace/17.usbdev_rx_full/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1184330394
Short name T2358
Test name
Test status
Simulation time 172997801 ps
CPU time 0.95 seconds
Started Aug 17 06:06:21 PM PDT 24
Finished Aug 17 06:06:22 PM PDT 24
Peak memory 207504 kb
Host smart-4aad66af-a4f9-4b67-b363-a530de78c3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11843
30394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1184330394
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.684651704
Short name T3103
Test name
Test status
Simulation time 146570021 ps
CPU time 0.87 seconds
Started Aug 17 06:06:18 PM PDT 24
Finished Aug 17 06:06:19 PM PDT 24
Peak memory 207548 kb
Host smart-1dedb352-3fc7-41c6-a446-11dca54b9294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68465
1704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.684651704
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3061869687
Short name T3601
Test name
Test status
Simulation time 236179600 ps
CPU time 1.07 seconds
Started Aug 17 06:06:18 PM PDT 24
Finished Aug 17 06:06:19 PM PDT 24
Peak memory 207456 kb
Host smart-2e0d1338-8e47-49e6-a8be-2ba754029d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30618
69687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3061869687
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2590903260
Short name T1519
Test name
Test status
Simulation time 2994188881 ps
CPU time 33.12 seconds
Started Aug 17 06:06:18 PM PDT 24
Finished Aug 17 06:06:52 PM PDT 24
Peak memory 217852 kb
Host smart-5bf8670c-c56f-49e6-996d-d25bb772b4c2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2590903260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2590903260
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2739429537
Short name T1773
Test name
Test status
Simulation time 171911493 ps
CPU time 0.93 seconds
Started Aug 17 06:06:15 PM PDT 24
Finished Aug 17 06:06:16 PM PDT 24
Peak memory 207472 kb
Host smart-6b66c5e9-7885-46d8-95cb-d0cc7a8c724a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
29537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2739429537
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.684855390
Short name T2609
Test name
Test status
Simulation time 163782934 ps
CPU time 0.88 seconds
Started Aug 17 06:06:19 PM PDT 24
Finished Aug 17 06:06:20 PM PDT 24
Peak memory 207416 kb
Host smart-b399ada0-dd60-4b9d-b83c-e8f3a8b57122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68485
5390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.684855390
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.3690162410
Short name T1723
Test name
Test status
Simulation time 654428350 ps
CPU time 2 seconds
Started Aug 17 06:06:21 PM PDT 24
Finished Aug 17 06:06:23 PM PDT 24
Peak memory 207508 kb
Host smart-bec6e6e6-7984-465e-b378-ace471c0a7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36901
62410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3690162410
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.4175438167
Short name T3196
Test name
Test status
Simulation time 2949159457 ps
CPU time 92.64 seconds
Started Aug 17 06:06:18 PM PDT 24
Finished Aug 17 06:07:51 PM PDT 24
Peak memory 224136 kb
Host smart-80fb2a35-c5de-4a3e-9bfe-546cb4ec13d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41754
38167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.4175438167
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.436254216
Short name T1037
Test name
Test status
Simulation time 4409218503 ps
CPU time 28.25 seconds
Started Aug 17 06:06:07 PM PDT 24
Finished Aug 17 06:06:36 PM PDT 24
Peak memory 207684 kb
Host smart-d4dac08d-1fdc-4692-a86e-e0111c5f41b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436254216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_host
_handshake.436254216
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_tx_rx_disruption.1813247697
Short name T2629
Test name
Test status
Simulation time 465341000 ps
CPU time 1.52 seconds
Started Aug 17 06:06:22 PM PDT 24
Finished Aug 17 06:06:24 PM PDT 24
Peak memory 207508 kb
Host smart-05bc1a3f-dd9f-4989-85e0-4cdd4bb55a52
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813247697 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.usbdev_tx_rx_disruption.1813247697
Directory /workspace/17.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/170.usbdev_endpoint_types.3949755905
Short name T384
Test name
Test status
Simulation time 301038083 ps
CPU time 1.18 seconds
Started Aug 17 06:11:40 PM PDT 24
Finished Aug 17 06:11:41 PM PDT 24
Peak memory 207512 kb
Host smart-d3d51b5a-6ac1-41fd-bb1b-651b5e809051
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3949755905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.3949755905
Directory /workspace/170.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_endpoint_types.3889244444
Short name T445
Test name
Test status
Simulation time 654302676 ps
CPU time 1.61 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207524 kb
Host smart-d7c7d266-1221-493f-9315-22d653ffb73c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3889244444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.3889244444
Directory /workspace/171.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_tx_rx_disruption.62291531
Short name T2628
Test name
Test status
Simulation time 481496920 ps
CPU time 1.53 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207536 kb
Host smart-0f818cc7-83e3-40b7-a2ff-b930040e7067
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62291531 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 171.usbdev_tx_rx_disruption.62291531
Directory /workspace/171.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/172.usbdev_endpoint_types.1776519036
Short name T15
Test name
Test status
Simulation time 351637126 ps
CPU time 1.24 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207588 kb
Host smart-501207d7-61b2-456f-93ee-573853df0f06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1776519036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.1776519036
Directory /workspace/172.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/172.usbdev_tx_rx_disruption.3588288829
Short name T2387
Test name
Test status
Simulation time 532752992 ps
CPU time 1.62 seconds
Started Aug 17 06:11:54 PM PDT 24
Finished Aug 17 06:11:56 PM PDT 24
Peak memory 207540 kb
Host smart-1e670f44-ff9c-48db-8a87-61c0a2637325
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588288829 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.usbdev_tx_rx_disruption.3588288829
Directory /workspace/172.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/173.usbdev_endpoint_types.705621563
Short name T478
Test name
Test status
Simulation time 526609689 ps
CPU time 1.47 seconds
Started Aug 17 06:12:00 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207436 kb
Host smart-5c059bcf-e5c1-4d35-b966-7c67fa075300
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=705621563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.705621563
Directory /workspace/173.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/173.usbdev_tx_rx_disruption.1839085878
Short name T648
Test name
Test status
Simulation time 518571452 ps
CPU time 1.52 seconds
Started Aug 17 06:11:46 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207564 kb
Host smart-15ec62b4-52ee-451e-b1b7-5e9a1866a6da
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839085878 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.usbdev_tx_rx_disruption.1839085878
Directory /workspace/173.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/174.usbdev_endpoint_types.1918180623
Short name T2697
Test name
Test status
Simulation time 511005877 ps
CPU time 1.44 seconds
Started Aug 17 06:11:47 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207544 kb
Host smart-290dc5dd-3053-49a8-ac31-8991d5aa8a80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1918180623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.1918180623
Directory /workspace/174.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/174.usbdev_tx_rx_disruption.4113116434
Short name T3636
Test name
Test status
Simulation time 487655486 ps
CPU time 1.44 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207560 kb
Host smart-ac8ccd54-c6f6-4e39-8d91-62954f546ae7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113116434 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.usbdev_tx_rx_disruption.4113116434
Directory /workspace/174.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/175.usbdev_endpoint_types.1416827898
Short name T455
Test name
Test status
Simulation time 602733641 ps
CPU time 1.63 seconds
Started Aug 17 06:11:41 PM PDT 24
Finished Aug 17 06:11:43 PM PDT 24
Peak memory 207564 kb
Host smart-37abf537-d5a4-4114-b62d-45c14e892ef0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1416827898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.1416827898
Directory /workspace/175.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/175.usbdev_tx_rx_disruption.1280663248
Short name T1661
Test name
Test status
Simulation time 615038780 ps
CPU time 1.71 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207568 kb
Host smart-ec3dff9d-c300-4459-be93-606741f4c4e9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280663248 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.usbdev_tx_rx_disruption.1280663248
Directory /workspace/175.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/176.usbdev_endpoint_types.146925286
Short name T14
Test name
Test status
Simulation time 175483781 ps
CPU time 0.95 seconds
Started Aug 17 06:11:53 PM PDT 24
Finished Aug 17 06:11:54 PM PDT 24
Peak memory 207448 kb
Host smart-c6101833-c1ff-40b2-b425-69aab8b40820
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=146925286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.146925286
Directory /workspace/176.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/176.usbdev_tx_rx_disruption.29996504
Short name T766
Test name
Test status
Simulation time 573604887 ps
CPU time 1.61 seconds
Started Aug 17 06:11:41 PM PDT 24
Finished Aug 17 06:11:42 PM PDT 24
Peak memory 207584 kb
Host smart-1143dc2f-5587-4b21-a53c-fc774bc2232b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29996504 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 176.usbdev_tx_rx_disruption.29996504
Directory /workspace/176.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/177.usbdev_endpoint_types.3197051438
Short name T393
Test name
Test status
Simulation time 213321159 ps
CPU time 1 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207384 kb
Host smart-844d5e64-e642-4493-a51d-bf6dbae5634e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3197051438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.3197051438
Directory /workspace/177.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/177.usbdev_tx_rx_disruption.3135160275
Short name T125
Test name
Test status
Simulation time 460198574 ps
CPU time 1.45 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207568 kb
Host smart-b85191ac-51e8-4f1b-aa8d-118d0b0301cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135160275 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.usbdev_tx_rx_disruption.3135160275
Directory /workspace/177.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/178.usbdev_endpoint_types.3618160497
Short name T385
Test name
Test status
Simulation time 210959090 ps
CPU time 0.93 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 207480 kb
Host smart-4d0ae769-992f-409f-9a29-3ef35adc10b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3618160497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.3618160497
Directory /workspace/178.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/178.usbdev_tx_rx_disruption.2441199827
Short name T3057
Test name
Test status
Simulation time 557764923 ps
CPU time 1.54 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207540 kb
Host smart-1fe6e77c-ac59-4ab6-9d08-dde551974b6f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441199827 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.usbdev_tx_rx_disruption.2441199827
Directory /workspace/178.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/179.usbdev_endpoint_types.3360615610
Short name T3368
Test name
Test status
Simulation time 345351663 ps
CPU time 1.27 seconds
Started Aug 17 06:11:55 PM PDT 24
Finished Aug 17 06:11:56 PM PDT 24
Peak memory 207524 kb
Host smart-a499d6e7-e9e6-4227-bfbb-4548f2d2081d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3360615610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.3360615610
Directory /workspace/179.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/179.usbdev_tx_rx_disruption.2921702356
Short name T2394
Test name
Test status
Simulation time 565530882 ps
CPU time 1.9 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207572 kb
Host smart-1a318398-6165-49ee-a243-bbc6f741dc34
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921702356 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.usbdev_tx_rx_disruption.2921702356
Directory /workspace/179.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3642187996
Short name T781
Test name
Test status
Simulation time 42260742 ps
CPU time 0.7 seconds
Started Aug 17 06:06:30 PM PDT 24
Finished Aug 17 06:06:31 PM PDT 24
Peak memory 207380 kb
Host smart-7a6d9e3e-4744-4dfb-95b2-af9fcdefa4f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3642187996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3642187996
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3818720841
Short name T8
Test name
Test status
Simulation time 4714904663 ps
CPU time 6.93 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:24 PM PDT 24
Peak memory 215988 kb
Host smart-1417716a-a526-448a-8858-6c1b5a524ec4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818720841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.3818720841
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2374667
Short name T1717
Test name
Test status
Simulation time 20296304028 ps
CPU time 28.93 seconds
Started Aug 17 06:06:19 PM PDT 24
Finished Aug 17 06:06:48 PM PDT 24
Peak memory 207748 kb
Host smart-da8c36a5-eebf-4006-92f2-66bb95ad29d2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2374667
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.4078906720
Short name T2801
Test name
Test status
Simulation time 24942601807 ps
CPU time 31.06 seconds
Started Aug 17 06:06:21 PM PDT 24
Finished Aug 17 06:06:52 PM PDT 24
Peak memory 216012 kb
Host smart-567770b0-4d4b-4a38-8fc1-5ba69f2564cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078906720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.4078906720
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2131763924
Short name T2583
Test name
Test status
Simulation time 176754345 ps
CPU time 0.89 seconds
Started Aug 17 06:06:17 PM PDT 24
Finished Aug 17 06:06:18 PM PDT 24
Peak memory 207452 kb
Host smart-588bd7da-1328-440e-a958-712526f1f1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21317
63924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2131763924
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3412509609
Short name T2725
Test name
Test status
Simulation time 145779716 ps
CPU time 0.87 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207524 kb
Host smart-4cf19771-de3e-4bf1-93cd-c3fcf9f1eb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34125
09609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3412509609
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.4081928191
Short name T589
Test name
Test status
Simulation time 424071463 ps
CPU time 1.5 seconds
Started Aug 17 06:06:26 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207476 kb
Host smart-99c7af9f-ab5b-4929-a9d3-a3000a83ae60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40819
28191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.4081928191
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3512891647
Short name T2498
Test name
Test status
Simulation time 496482374 ps
CPU time 1.49 seconds
Started Aug 17 06:06:24 PM PDT 24
Finished Aug 17 06:06:26 PM PDT 24
Peak memory 207464 kb
Host smart-57c95ccc-4a2f-421e-b2a7-4e7848bdda3e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3512891647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3512891647
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2485165850
Short name T3585
Test name
Test status
Simulation time 24882482238 ps
CPU time 38.46 seconds
Started Aug 17 06:06:24 PM PDT 24
Finished Aug 17 06:07:02 PM PDT 24
Peak memory 207800 kb
Host smart-1e1cac54-2485-4912-a16e-8a0d419fe0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24851
65850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2485165850
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.1082119836
Short name T3362
Test name
Test status
Simulation time 4951391100 ps
CPU time 34.34 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:07:02 PM PDT 24
Peak memory 207804 kb
Host smart-46ce0376-ae85-45a3-a398-e04dec2bdc23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082119836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.1082119836
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.332091726
Short name T1866
Test name
Test status
Simulation time 738080995 ps
CPU time 1.93 seconds
Started Aug 17 06:06:29 PM PDT 24
Finished Aug 17 06:06:31 PM PDT 24
Peak memory 207520 kb
Host smart-387a0911-f455-412a-a710-7a3dd222a59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33209
1726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.332091726
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1202806222
Short name T3621
Test name
Test status
Simulation time 154576560 ps
CPU time 0.84 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207456 kb
Host smart-055bf7a7-383c-46c7-bcb2-f8c8dab4ba1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12028
06222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1202806222
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1350968757
Short name T3005
Test name
Test status
Simulation time 65073443 ps
CPU time 0.81 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:06:26 PM PDT 24
Peak memory 207456 kb
Host smart-3b2c4aaa-4e5c-43f3-beb0-e08d7b7e6a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13509
68757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1350968757
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2901241794
Short name T708
Test name
Test status
Simulation time 1036716107 ps
CPU time 2.83 seconds
Started Aug 17 06:06:26 PM PDT 24
Finished Aug 17 06:06:29 PM PDT 24
Peak memory 207804 kb
Host smart-c7115fb4-89dd-423d-a431-c4bfaaba5e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29012
41794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2901241794
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_types.1221324740
Short name T448
Test name
Test status
Simulation time 636917310 ps
CPU time 1.69 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207524 kb
Host smart-27366f89-62da-4220-8d66-e221ae838243
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1221324740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.1221324740
Directory /workspace/18.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.452321704
Short name T1536
Test name
Test status
Simulation time 230469530 ps
CPU time 1.84 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207648 kb
Host smart-246e1620-59c6-40af-8214-a702be20728c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45232
1704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.452321704
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2652305957
Short name T875
Test name
Test status
Simulation time 183176286 ps
CPU time 0.98 seconds
Started Aug 17 06:06:29 PM PDT 24
Finished Aug 17 06:06:30 PM PDT 24
Peak memory 207460 kb
Host smart-66d7b4db-0f32-4027-a882-33ba439bf0cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2652305957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2652305957
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1568399506
Short name T2019
Test name
Test status
Simulation time 157322305 ps
CPU time 0.95 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207432 kb
Host smart-a5d8e50d-c11c-415d-80c1-f266d713cf30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15683
99506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1568399506
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2297250787
Short name T2745
Test name
Test status
Simulation time 189010884 ps
CPU time 0.98 seconds
Started Aug 17 06:06:30 PM PDT 24
Finished Aug 17 06:06:31 PM PDT 24
Peak memory 207416 kb
Host smart-a8d026f5-940e-4798-8c12-7cd0bcd62643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22972
50787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2297250787
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.3790354114
Short name T3381
Test name
Test status
Simulation time 2915962284 ps
CPU time 88.86 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 215932 kb
Host smart-afd4c155-9d5b-4fdf-8445-30733b4168e0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3790354114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.3790354114
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.1646506594
Short name T2896
Test name
Test status
Simulation time 6793088129 ps
CPU time 44.82 seconds
Started Aug 17 06:06:26 PM PDT 24
Finished Aug 17 06:07:11 PM PDT 24
Peak memory 207784 kb
Host smart-7be981d6-3e0d-4dc4-83a1-a4f0bd428e7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1646506594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.1646506594
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.4100818584
Short name T2764
Test name
Test status
Simulation time 240428909 ps
CPU time 1.01 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207572 kb
Host smart-a0a17eb6-8e9e-4c63-9204-825342d73652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41008
18584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.4100818584
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.3336619498
Short name T983
Test name
Test status
Simulation time 28868106938 ps
CPU time 54.68 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207820 kb
Host smart-18902941-d817-4d05-8ee8-862d6f391e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33366
19498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.3336619498
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2986669617
Short name T1646
Test name
Test status
Simulation time 6048017974 ps
CPU time 8.5 seconds
Started Aug 17 06:06:29 PM PDT 24
Finished Aug 17 06:06:37 PM PDT 24
Peak memory 207816 kb
Host smart-a1e22525-156b-4e05-9f5e-14b32acd4f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29866
69617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2986669617
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.2416076060
Short name T3304
Test name
Test status
Simulation time 4525911429 ps
CPU time 49.47 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:07:14 PM PDT 24
Peak memory 218480 kb
Host smart-7961d6b9-b3d3-4538-92dd-506ba85eb201
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2416076060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.2416076060
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3712207353
Short name T2965
Test name
Test status
Simulation time 4203315690 ps
CPU time 32.64 seconds
Started Aug 17 06:06:29 PM PDT 24
Finished Aug 17 06:07:02 PM PDT 24
Peak memory 215812 kb
Host smart-914e2b3a-a8f3-49f6-bf73-76252d9e86b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3712207353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3712207353
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.354689129
Short name T2481
Test name
Test status
Simulation time 247217868 ps
CPU time 1.08 seconds
Started Aug 17 06:06:26 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207484 kb
Host smart-232bf631-6686-49f6-8f2c-d624648cbdcb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=354689129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.354689129
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3105726437
Short name T3235
Test name
Test status
Simulation time 212844043 ps
CPU time 0.95 seconds
Started Aug 17 06:06:30 PM PDT 24
Finished Aug 17 06:06:31 PM PDT 24
Peak memory 207412 kb
Host smart-449391b3-2b83-44f6-8047-538921058eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057
26437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3105726437
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.3292300252
Short name T871
Test name
Test status
Simulation time 2281497347 ps
CPU time 71.51 seconds
Started Aug 17 06:06:23 PM PDT 24
Finished Aug 17 06:07:34 PM PDT 24
Peak memory 217628 kb
Host smart-c1c20533-e20c-423a-a6ff-a48b58f1a8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32923
00252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.3292300252
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1582128367
Short name T1338
Test name
Test status
Simulation time 3067382376 ps
CPU time 35.58 seconds
Started Aug 17 06:06:24 PM PDT 24
Finished Aug 17 06:07:00 PM PDT 24
Peak memory 217404 kb
Host smart-c02e734a-7e35-4796-836b-a86aa1e0b246
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1582128367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1582128367
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.253351979
Short name T1148
Test name
Test status
Simulation time 188362775 ps
CPU time 0.95 seconds
Started Aug 17 06:06:26 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207500 kb
Host smart-4a95be29-816b-4408-867d-20c770ccb613
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=253351979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.253351979
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1917197155
Short name T2926
Test name
Test status
Simulation time 236560654 ps
CPU time 0.99 seconds
Started Aug 17 06:06:26 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207372 kb
Host smart-973f2bd7-fbb5-48d0-94ab-33780cfe8f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19171
97155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1917197155
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.657723104
Short name T738
Test name
Test status
Simulation time 175429926 ps
CPU time 0.91 seconds
Started Aug 17 06:06:30 PM PDT 24
Finished Aug 17 06:06:31 PM PDT 24
Peak memory 207420 kb
Host smart-a6b3ac32-f42c-436e-ab72-66302ed7be2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65772
3104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.657723104
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3880480932
Short name T3246
Test name
Test status
Simulation time 207770693 ps
CPU time 0.99 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:06:26 PM PDT 24
Peak memory 207456 kb
Host smart-aa55481a-bb94-44d8-956d-309bced37956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38804
80932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3880480932
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1650518954
Short name T2512
Test name
Test status
Simulation time 166557839 ps
CPU time 0.9 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207480 kb
Host smart-9a8689e3-eaff-4644-a735-a8837adef40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16505
18954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1650518954
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3657399845
Short name T190
Test name
Test status
Simulation time 145611534 ps
CPU time 0.9 seconds
Started Aug 17 06:06:26 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207556 kb
Host smart-eb91696d-9a5b-4603-8001-864584af2cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36573
99845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3657399845
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1580701529
Short name T88
Test name
Test status
Simulation time 267858650 ps
CPU time 1.14 seconds
Started Aug 17 06:06:28 PM PDT 24
Finished Aug 17 06:06:29 PM PDT 24
Peak memory 207528 kb
Host smart-85766e5a-1fbf-4516-9000-22ce3ff4e799
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1580701529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1580701529
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2693150118
Short name T845
Test name
Test status
Simulation time 192376213 ps
CPU time 0.89 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207392 kb
Host smart-ef8078fe-e17d-4374-8531-f384777d7a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26931
50118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2693150118
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.803792785
Short name T833
Test name
Test status
Simulation time 33690958 ps
CPU time 0.68 seconds
Started Aug 17 06:06:28 PM PDT 24
Finished Aug 17 06:06:29 PM PDT 24
Peak memory 207512 kb
Host smart-b74fdb07-b798-4367-8384-b7b033a917e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80379
2785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.803792785
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2139575963
Short name T1547
Test name
Test status
Simulation time 213092393 ps
CPU time 0.93 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207464 kb
Host smart-f44d4854-0467-4c73-9327-5d4a69d106fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21395
75963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2139575963
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3706209736
Short name T1467
Test name
Test status
Simulation time 232847196 ps
CPU time 1.02 seconds
Started Aug 17 06:06:29 PM PDT 24
Finished Aug 17 06:06:31 PM PDT 24
Peak memory 207472 kb
Host smart-4558f0fb-275d-4a31-8477-13bec8630df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37062
09736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3706209736
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3709640453
Short name T1774
Test name
Test status
Simulation time 215328450 ps
CPU time 0.95 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207460 kb
Host smart-b42fdf02-5d69-4be1-848d-5311a28ae157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37096
40453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3709640453
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.253411368
Short name T1373
Test name
Test status
Simulation time 178150623 ps
CPU time 0.92 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:06:26 PM PDT 24
Peak memory 207472 kb
Host smart-143e6dbd-63a6-46a7-9eb7-87e501e8df8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25341
1368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.253411368
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_resume_link_active.1424283002
Short name T2417
Test name
Test status
Simulation time 20154403256 ps
CPU time 24.79 seconds
Started Aug 17 06:06:28 PM PDT 24
Finished Aug 17 06:06:53 PM PDT 24
Peak memory 207616 kb
Host smart-5c3eabca-fc23-4323-b856-13d45e692bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14242
83002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.1424283002
Directory /workspace/18.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2644771435
Short name T1391
Test name
Test status
Simulation time 144687717 ps
CPU time 0.84 seconds
Started Aug 17 06:06:24 PM PDT 24
Finished Aug 17 06:06:25 PM PDT 24
Peak memory 207452 kb
Host smart-3eee99c2-2c89-4d88-91fa-e9d9fc14d120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26447
71435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2644771435
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_rx_full.1453387320
Short name T1816
Test name
Test status
Simulation time 350899505 ps
CPU time 1.22 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:29 PM PDT 24
Peak memory 207448 kb
Host smart-ace3d05e-c4a1-4f89-af7d-d2e488e4e776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14533
87320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.1453387320
Directory /workspace/18.usbdev_rx_full/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3467259508
Short name T3270
Test name
Test status
Simulation time 148814211 ps
CPU time 0.85 seconds
Started Aug 17 06:06:28 PM PDT 24
Finished Aug 17 06:06:29 PM PDT 24
Peak memory 207536 kb
Host smart-34daf930-bcce-4357-93c1-7d3fc62bde64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34672
59508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3467259508
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3996839330
Short name T1642
Test name
Test status
Simulation time 161758049 ps
CPU time 0.92 seconds
Started Aug 17 06:06:28 PM PDT 24
Finished Aug 17 06:06:29 PM PDT 24
Peak memory 207488 kb
Host smart-a3353e95-d304-454a-a159-2eb53c8a36ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39968
39330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3996839330
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2936602796
Short name T1503
Test name
Test status
Simulation time 226441253 ps
CPU time 1.1 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:29 PM PDT 24
Peak memory 207424 kb
Host smart-2b827945-4706-4ca7-b8ed-7bea894015ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29366
02796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2936602796
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2664795684
Short name T3386
Test name
Test status
Simulation time 2024389285 ps
CPU time 15.67 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 224056 kb
Host smart-672150c9-aaf3-4cc8-ac5c-daa12db3b88c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2664795684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2664795684
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2713272362
Short name T1545
Test name
Test status
Simulation time 190900682 ps
CPU time 0.95 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207400 kb
Host smart-757959d0-a29a-4c5e-b4f9-4cece144230a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27132
72362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2713272362
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3647859306
Short name T633
Test name
Test status
Simulation time 225267874 ps
CPU time 0.94 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:06:33 PM PDT 24
Peak memory 207536 kb
Host smart-817c94fa-f300-42da-8cf7-a88311f4098b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36478
59306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3647859306
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.2711213006
Short name T1854
Test name
Test status
Simulation time 1238749027 ps
CPU time 3.11 seconds
Started Aug 17 06:06:24 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 207672 kb
Host smart-33a9a2a8-1511-4f4d-94bc-9727105b3297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27112
13006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.2711213006
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2687161292
Short name T1446
Test name
Test status
Simulation time 2702854570 ps
CPU time 26.22 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:06:58 PM PDT 24
Peak memory 217760 kb
Host smart-cbbf2385-7731-4117-9f28-8e2abd40e9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871
61292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2687161292
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.135660798
Short name T2270
Test name
Test status
Simulation time 878903991 ps
CPU time 19.65 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 207632 kb
Host smart-8d461538-3042-4dfc-8438-79cc319a60e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135660798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_host
_handshake.135660798
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_tx_rx_disruption.824573830
Short name T3429
Test name
Test status
Simulation time 489690861 ps
CPU time 1.7 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:35 PM PDT 24
Peak memory 207480 kb
Host smart-f2c25c9a-9ea6-4f67-9cde-a7e467257fda
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824573830 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.usbdev_tx_rx_disruption.824573830
Directory /workspace/18.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/180.usbdev_endpoint_types.1211845341
Short name T2451
Test name
Test status
Simulation time 405589005 ps
CPU time 1.31 seconds
Started Aug 17 06:11:58 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207520 kb
Host smart-e69ac709-91ed-4f62-8c92-885939fc7bd4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1211845341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.1211845341
Directory /workspace/180.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/180.usbdev_tx_rx_disruption.488437164
Short name T1111
Test name
Test status
Simulation time 610537097 ps
CPU time 1.84 seconds
Started Aug 17 06:11:43 PM PDT 24
Finished Aug 17 06:11:44 PM PDT 24
Peak memory 207564 kb
Host smart-6f69d9d1-8b0f-4390-915b-08a6e64763b8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488437164 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 180.usbdev_tx_rx_disruption.488437164
Directory /workspace/180.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/181.usbdev_endpoint_types.1231644218
Short name T3004
Test name
Test status
Simulation time 394673881 ps
CPU time 1.38 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:44 PM PDT 24
Peak memory 207524 kb
Host smart-fb06d7ae-f3da-4751-a92b-43c1d802c3f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1231644218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.1231644218
Directory /workspace/181.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/181.usbdev_tx_rx_disruption.3119466929
Short name T2794
Test name
Test status
Simulation time 542263992 ps
CPU time 1.55 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207540 kb
Host smart-bb9806fb-7af4-4c05-bcc9-dd4168f644f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119466929 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.usbdev_tx_rx_disruption.3119466929
Directory /workspace/181.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/182.usbdev_tx_rx_disruption.850577479
Short name T2001
Test name
Test status
Simulation time 557891387 ps
CPU time 1.67 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:43 PM PDT 24
Peak memory 207576 kb
Host smart-4678ad44-2965-483e-93ca-61088a3f37c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850577479 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 182.usbdev_tx_rx_disruption.850577479
Directory /workspace/182.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/183.usbdev_endpoint_types.1705286673
Short name T1764
Test name
Test status
Simulation time 231597129 ps
CPU time 0.96 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 207528 kb
Host smart-6da6fb9d-abc0-4c33-a147-a8388c3073b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1705286673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.1705286673
Directory /workspace/183.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/183.usbdev_tx_rx_disruption.83646758
Short name T3164
Test name
Test status
Simulation time 643650729 ps
CPU time 1.8 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207560 kb
Host smart-7c3306a3-e7ac-4aeb-8e41-202c421051ee
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83646758 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 183.usbdev_tx_rx_disruption.83646758
Directory /workspace/183.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/184.usbdev_endpoint_types.685014751
Short name T512
Test name
Test status
Simulation time 171924315 ps
CPU time 0.89 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207520 kb
Host smart-16446be1-973e-4cc2-9c71-f2b0ec0c40b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=685014751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.685014751
Directory /workspace/184.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/184.usbdev_tx_rx_disruption.586889947
Short name T1178
Test name
Test status
Simulation time 435885335 ps
CPU time 1.46 seconds
Started Aug 17 06:12:00 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207536 kb
Host smart-b98ede78-ac8e-4d98-9857-b6febbe6c3c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586889947 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 184.usbdev_tx_rx_disruption.586889947
Directory /workspace/184.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/185.usbdev_endpoint_types.2376900728
Short name T1251
Test name
Test status
Simulation time 170543488 ps
CPU time 0.9 seconds
Started Aug 17 06:11:48 PM PDT 24
Finished Aug 17 06:11:49 PM PDT 24
Peak memory 207524 kb
Host smart-c6eae449-8610-4b0a-bbae-c3d5f289e06f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2376900728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.2376900728
Directory /workspace/185.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/185.usbdev_tx_rx_disruption.2186926396
Short name T2963
Test name
Test status
Simulation time 561560239 ps
CPU time 1.66 seconds
Started Aug 17 06:12:00 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207540 kb
Host smart-de0bde69-9425-4c9e-a13a-ec3421927210
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186926396 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.usbdev_tx_rx_disruption.2186926396
Directory /workspace/185.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/186.usbdev_endpoint_types.3481077904
Short name T497
Test name
Test status
Simulation time 252977183 ps
CPU time 1.13 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207516 kb
Host smart-4e475e1c-5ddc-41a8-9802-c76740772d78
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3481077904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.3481077904
Directory /workspace/186.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/186.usbdev_tx_rx_disruption.622722088
Short name T184
Test name
Test status
Simulation time 474793166 ps
CPU time 1.62 seconds
Started Aug 17 06:11:39 PM PDT 24
Finished Aug 17 06:11:41 PM PDT 24
Peak memory 207548 kb
Host smart-67efbf93-e554-4b1d-af46-28c9617b8d6c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622722088 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 186.usbdev_tx_rx_disruption.622722088
Directory /workspace/186.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/187.usbdev_endpoint_types.2599253025
Short name T2937
Test name
Test status
Simulation time 570962699 ps
CPU time 1.49 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207476 kb
Host smart-66664eee-150a-4058-a4cb-bd2a7c94d3c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2599253025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.2599253025
Directory /workspace/187.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/187.usbdev_tx_rx_disruption.2891908295
Short name T2207
Test name
Test status
Simulation time 509140062 ps
CPU time 1.65 seconds
Started Aug 17 06:11:58 PM PDT 24
Finished Aug 17 06:12:00 PM PDT 24
Peak memory 207484 kb
Host smart-f2e44cea-514a-4bd0-8610-a61509c23edd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891908295 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.usbdev_tx_rx_disruption.2891908295
Directory /workspace/187.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/188.usbdev_endpoint_types.2485047322
Short name T403
Test name
Test status
Simulation time 664105103 ps
CPU time 1.79 seconds
Started Aug 17 06:11:43 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 207532 kb
Host smart-40f3ae2c-a103-4e9a-aa31-a71e31ba8871
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2485047322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.2485047322
Directory /workspace/188.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/188.usbdev_tx_rx_disruption.548515747
Short name T1036
Test name
Test status
Simulation time 512857150 ps
CPU time 1.72 seconds
Started Aug 17 06:11:43 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 207560 kb
Host smart-a891ca89-06af-4b44-ae38-baed8a0e7c0d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548515747 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 188.usbdev_tx_rx_disruption.548515747
Directory /workspace/188.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/189.usbdev_endpoint_types.1226634491
Short name T111
Test name
Test status
Simulation time 185163049 ps
CPU time 0.91 seconds
Started Aug 17 06:12:04 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207472 kb
Host smart-fcb52cf3-edf9-47d8-8fda-2102d56ebc63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1226634491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.1226634491
Directory /workspace/189.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/189.usbdev_tx_rx_disruption.357249548
Short name T194
Test name
Test status
Simulation time 414091536 ps
CPU time 1.47 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207492 kb
Host smart-4da89eeb-dd67-4319-9a46-f79a675a14f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357249548 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 189.usbdev_tx_rx_disruption.357249548
Directory /workspace/189.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.910935265
Short name T1161
Test name
Test status
Simulation time 37459381 ps
CPU time 0.67 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207420 kb
Host smart-bcf53e40-e544-447d-b4e5-fa44611798f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=910935265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.910935265
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.885276947
Short name T551
Test name
Test status
Simulation time 5462142750 ps
CPU time 7.79 seconds
Started Aug 17 06:06:28 PM PDT 24
Finished Aug 17 06:06:36 PM PDT 24
Peak memory 215980 kb
Host smart-fdcffb0c-fee6-48a8-a7b7-d2a31f3a3751
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885276947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_disconnect.885276947
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3669232504
Short name T814
Test name
Test status
Simulation time 20207458050 ps
CPU time 26.73 seconds
Started Aug 17 06:06:28 PM PDT 24
Finished Aug 17 06:06:55 PM PDT 24
Peak memory 207736 kb
Host smart-5e95aa57-bd36-4683-b5c0-598dda08fd85
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669232504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3669232504
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.4174292817
Short name T3176
Test name
Test status
Simulation time 25546920967 ps
CPU time 33.13 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:07:05 PM PDT 24
Peak memory 216004 kb
Host smart-14ebcc99-0af7-4878-a25c-e406bc355f64
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174292817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.4174292817
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1363717686
Short name T1980
Test name
Test status
Simulation time 143172939 ps
CPU time 0.82 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:33 PM PDT 24
Peak memory 207412 kb
Host smart-4a08d854-2c32-4b27-bea6-51c936c30e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13637
17686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1363717686
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1992054541
Short name T2172
Test name
Test status
Simulation time 185718801 ps
CPU time 0.85 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207500 kb
Host smart-82b94367-08ec-4de3-9bf0-1bdc7f33c65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19920
54541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1992054541
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3106896287
Short name T3457
Test name
Test status
Simulation time 201859869 ps
CPU time 0.94 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207500 kb
Host smart-f351280d-98af-40e9-b740-d03336137ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31068
96287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3106896287
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2202455521
Short name T1677
Test name
Test status
Simulation time 317411958 ps
CPU time 1.18 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207432 kb
Host smart-d542c085-fd8f-4e40-9de3-1cc2eaa5c895
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2202455521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2202455521
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.3250073227
Short name T372
Test name
Test status
Simulation time 32908995401 ps
CPU time 53.38 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207704 kb
Host smart-e94e42bd-cc1a-42ca-b5d0-8c970cad8a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32500
73227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.3250073227
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.3630985997
Short name T2016
Test name
Test status
Simulation time 1557714727 ps
CPU time 13.49 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:46 PM PDT 24
Peak memory 207636 kb
Host smart-daad25d4-f635-4823-98fb-5d8a9f3e66ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630985997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.3630985997
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.4155719535
Short name T2783
Test name
Test status
Simulation time 818864134 ps
CPU time 2.01 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207560 kb
Host smart-3ba9e4b8-0e51-49e7-ba7b-2ec764ac561b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41557
19535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.4155719535
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.2387322560
Short name T3062
Test name
Test status
Simulation time 139544471 ps
CPU time 0.82 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207488 kb
Host smart-02e09576-044b-4c96-a516-1fc5ec7ed711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23873
22560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.2387322560
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.704695114
Short name T2067
Test name
Test status
Simulation time 52368847 ps
CPU time 0.77 seconds
Started Aug 17 06:06:30 PM PDT 24
Finished Aug 17 06:06:31 PM PDT 24
Peak memory 207416 kb
Host smart-dbffc87f-6dde-4265-bf55-77e96b5cbb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70469
5114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.704695114
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2940155130
Short name T2542
Test name
Test status
Simulation time 930664223 ps
CPU time 2.81 seconds
Started Aug 17 06:06:30 PM PDT 24
Finished Aug 17 06:06:33 PM PDT 24
Peak memory 207736 kb
Host smart-0ba61c2d-988a-4228-8ff7-fee9ce459d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29401
55130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2940155130
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_types.1200209302
Short name T435
Test name
Test status
Simulation time 416523847 ps
CPU time 1.36 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207504 kb
Host smart-3fa98a9e-5dfe-4bbd-8513-f8a2e93248ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1200209302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.1200209302
Directory /workspace/19.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.4204585220
Short name T1477
Test name
Test status
Simulation time 163928791 ps
CPU time 1.45 seconds
Started Aug 17 06:06:27 PM PDT 24
Finished Aug 17 06:06:28 PM PDT 24
Peak memory 207608 kb
Host smart-31c0a010-7c7b-428b-acf9-9f5cf90dcbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42045
85220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.4204585220
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3030080825
Short name T1649
Test name
Test status
Simulation time 257881030 ps
CPU time 1.25 seconds
Started Aug 17 06:06:30 PM PDT 24
Finished Aug 17 06:06:31 PM PDT 24
Peak memory 216876 kb
Host smart-fc6ab1a4-3bfc-4eca-a5b2-fdf7469b2072
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3030080825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3030080825
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.570787314
Short name T2519
Test name
Test status
Simulation time 139286081 ps
CPU time 0.83 seconds
Started Aug 17 06:06:30 PM PDT 24
Finished Aug 17 06:06:31 PM PDT 24
Peak memory 207404 kb
Host smart-badfd42b-9e9c-4bae-98d8-c13483da0408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57078
7314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.570787314
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.722283187
Short name T3402
Test name
Test status
Simulation time 233469748 ps
CPU time 0.96 seconds
Started Aug 17 06:06:29 PM PDT 24
Finished Aug 17 06:06:30 PM PDT 24
Peak memory 207436 kb
Host smart-ee95202a-095f-4079-8c9f-2e4d68717ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72228
3187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.722283187
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.481431643
Short name T1227
Test name
Test status
Simulation time 3894458124 ps
CPU time 32.91 seconds
Started Aug 17 06:06:25 PM PDT 24
Finished Aug 17 06:06:58 PM PDT 24
Peak memory 215944 kb
Host smart-f5a93d40-3bd8-41ca-9614-8428cdad1ec9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=481431643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.481431643
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.4006990792
Short name T3040
Test name
Test status
Simulation time 10419081692 ps
CPU time 66.88 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:07:47 PM PDT 24
Peak memory 207976 kb
Host smart-07619931-49ca-4a5b-b22c-2bf12e06d7c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4006990792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.4006990792
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2040709774
Short name T3598
Test name
Test status
Simulation time 202999045 ps
CPU time 0.98 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:06:33 PM PDT 24
Peak memory 207496 kb
Host smart-db6d4665-c376-49a4-98ba-bb788f84c1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20407
09774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2040709774
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.851856203
Short name T649
Test name
Test status
Simulation time 31051536199 ps
CPU time 57.66 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:07:31 PM PDT 24
Peak memory 207728 kb
Host smart-fd250d5e-625a-46e2-a954-1ac5f41f4bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85185
6203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.851856203
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1287726734
Short name T1260
Test name
Test status
Simulation time 10146962271 ps
CPU time 12 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 207808 kb
Host smart-7ee18d31-1d79-4723-a0e5-0bbf6a49097b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12877
26734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1287726734
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.814632098
Short name T3530
Test name
Test status
Simulation time 3718370326 ps
CPU time 111.84 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:08:26 PM PDT 24
Peak memory 218632 kb
Host smart-be2c3a26-f5c7-48c6-8ef3-c2a4853d1561
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=814632098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.814632098
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.4176634960
Short name T2563
Test name
Test status
Simulation time 3167659231 ps
CPU time 32.2 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:07:05 PM PDT 24
Peak memory 215920 kb
Host smart-e9ceac6f-f532-4de5-8d9c-5bf3eff3ed32
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4176634960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.4176634960
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.4164512029
Short name T1929
Test name
Test status
Simulation time 246018901 ps
CPU time 1.04 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:06:33 PM PDT 24
Peak memory 207480 kb
Host smart-8dfd2692-36eb-4691-bab2-7e9da6e9fbd0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4164512029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.4164512029
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3638955188
Short name T3107
Test name
Test status
Simulation time 196261537 ps
CPU time 0.98 seconds
Started Aug 17 06:06:39 PM PDT 24
Finished Aug 17 06:06:40 PM PDT 24
Peak memory 207484 kb
Host smart-55d4bdd6-050f-4609-9153-de936e57923c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36389
55188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3638955188
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.1482515379
Short name T1720
Test name
Test status
Simulation time 2991912496 ps
CPU time 23.5 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207852 kb
Host smart-c1e46e06-c244-44c1-8f12-0358f4d951e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14825
15379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.1482515379
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.4244874557
Short name T2982
Test name
Test status
Simulation time 2773094973 ps
CPU time 81.69 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 215904 kb
Host smart-2443a0e6-3837-4a30-aa47-804432c61d79
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4244874557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.4244874557
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.2407311791
Short name T640
Test name
Test status
Simulation time 151702999 ps
CPU time 0.88 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207424 kb
Host smart-0d2c3bbc-c5f8-411b-934d-c7e8bd8410cc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2407311791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.2407311791
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3463110888
Short name T2533
Test name
Test status
Simulation time 148431095 ps
CPU time 0.83 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207464 kb
Host smart-28e5cc6d-d1de-469d-9a7e-1e863c319c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34631
10888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3463110888
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.474800953
Short name T152
Test name
Test status
Simulation time 189415001 ps
CPU time 0.93 seconds
Started Aug 17 06:06:36 PM PDT 24
Finished Aug 17 06:06:37 PM PDT 24
Peak memory 207488 kb
Host smart-42bba99a-1d80-4e4c-af0f-2b63760bd064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47480
0953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.474800953
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1719776272
Short name T1005
Test name
Test status
Simulation time 175610983 ps
CPU time 0.87 seconds
Started Aug 17 06:06:36 PM PDT 24
Finished Aug 17 06:06:37 PM PDT 24
Peak memory 207432 kb
Host smart-443fbc16-2ae9-47a2-a8a8-caf6bec9a727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17197
76272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1719776272
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3309824107
Short name T3504
Test name
Test status
Simulation time 172028627 ps
CPU time 0.9 seconds
Started Aug 17 06:06:31 PM PDT 24
Finished Aug 17 06:06:32 PM PDT 24
Peak memory 207372 kb
Host smart-e33a4d69-2bf5-4f9e-8cbd-c6de6d83ffb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33098
24107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3309824107
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.807752731
Short name T2939
Test name
Test status
Simulation time 159720137 ps
CPU time 0.88 seconds
Started Aug 17 06:06:35 PM PDT 24
Finished Aug 17 06:06:36 PM PDT 24
Peak memory 207548 kb
Host smart-7dbf2e46-567b-45ed-adef-38ffa70cb76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80775
2731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.807752731
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.4284497442
Short name T1934
Test name
Test status
Simulation time 161343581 ps
CPU time 0.85 seconds
Started Aug 17 06:06:38 PM PDT 24
Finished Aug 17 06:06:39 PM PDT 24
Peak memory 207476 kb
Host smart-14eb5685-7196-4d25-be24-67a714242faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42844
97442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.4284497442
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.2562540296
Short name T2407
Test name
Test status
Simulation time 247665647 ps
CPU time 1.14 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:06:36 PM PDT 24
Peak memory 207560 kb
Host smart-c581b962-b7c3-4d8c-86d6-9fc5b3783042
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2562540296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.2562540296
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1231918634
Short name T1533
Test name
Test status
Simulation time 141546008 ps
CPU time 0.86 seconds
Started Aug 17 06:06:31 PM PDT 24
Finished Aug 17 06:06:32 PM PDT 24
Peak memory 207436 kb
Host smart-2584ec02-87bc-4bcb-90d0-81feb19e1f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12319
18634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1231918634
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.672004218
Short name T2632
Test name
Test status
Simulation time 57305160 ps
CPU time 0.73 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 207728 kb
Host smart-c0cdbb8c-586e-48a5-9638-89ea560579d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67200
4218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.672004218
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2874254578
Short name T1637
Test name
Test status
Simulation time 16087141354 ps
CPU time 43.44 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 215928 kb
Host smart-d28ac370-9596-47e0-a102-18f91fe416fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28742
54578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2874254578
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1410957830
Short name T2682
Test name
Test status
Simulation time 163991437 ps
CPU time 0.91 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:06:33 PM PDT 24
Peak memory 207512 kb
Host smart-7a671075-564c-4254-8564-6c5b10339b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14109
57830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1410957830
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.4148603502
Short name T1966
Test name
Test status
Simulation time 175092079 ps
CPU time 0.88 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:06:35 PM PDT 24
Peak memory 207400 kb
Host smart-bc6c7ff7-8ee7-44fa-8bfb-4312a0c19147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41486
03502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.4148603502
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3984845356
Short name T613
Test name
Test status
Simulation time 220317421 ps
CPU time 0.98 seconds
Started Aug 17 06:06:39 PM PDT 24
Finished Aug 17 06:06:40 PM PDT 24
Peak memory 207692 kb
Host smart-945e19b4-4f54-431d-bc77-16c25aff556c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39848
45356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3984845356
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.562804010
Short name T3462
Test name
Test status
Simulation time 199755485 ps
CPU time 0.95 seconds
Started Aug 17 06:06:31 PM PDT 24
Finished Aug 17 06:06:32 PM PDT 24
Peak memory 207488 kb
Host smart-e1208242-4c5f-49b6-98f5-44242b59cd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56280
4010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.562804010
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_resume_link_active.2788532000
Short name T3551
Test name
Test status
Simulation time 20183297431 ps
CPU time 24.05 seconds
Started Aug 17 06:06:31 PM PDT 24
Finished Aug 17 06:06:55 PM PDT 24
Peak memory 207572 kb
Host smart-6f13d23f-5631-4b05-96f9-172af88cae1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
32000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.2788532000
Directory /workspace/19.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2238558122
Short name T3487
Test name
Test status
Simulation time 150752323 ps
CPU time 0.83 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 207324 kb
Host smart-e5418ca6-0661-4ff7-a609-065dc0b8988b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22385
58122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2238558122
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_rx_full.831284564
Short name T2328
Test name
Test status
Simulation time 299902763 ps
CPU time 1.12 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207540 kb
Host smart-2b3a6dbc-8a75-4b07-8f63-74f7c576de3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83128
4564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.831284564
Directory /workspace/19.usbdev_rx_full/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.889763636
Short name T711
Test name
Test status
Simulation time 153470905 ps
CPU time 0.83 seconds
Started Aug 17 06:06:37 PM PDT 24
Finished Aug 17 06:06:38 PM PDT 24
Peak memory 207424 kb
Host smart-9a254cd6-6889-421f-a494-5dc27838717f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88976
3636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.889763636
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1430312588
Short name T1898
Test name
Test status
Simulation time 151151783 ps
CPU time 0.92 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:06:36 PM PDT 24
Peak memory 207436 kb
Host smart-4cd310c8-e468-447c-8a27-22dfb296f5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
12588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1430312588
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.116234818
Short name T3380
Test name
Test status
Simulation time 221414815 ps
CPU time 1.06 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:35 PM PDT 24
Peak memory 207488 kb
Host smart-08c6d8b4-1651-4a6b-8633-3ff949a0b8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11623
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.116234818
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2723817513
Short name T2418
Test name
Test status
Simulation time 1681342069 ps
CPU time 16.5 seconds
Started Aug 17 06:06:36 PM PDT 24
Finished Aug 17 06:06:52 PM PDT 24
Peak memory 216876 kb
Host smart-dec31364-4431-4da4-8ea7-9a2449b3332b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2723817513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2723817513
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.859461480
Short name T1129
Test name
Test status
Simulation time 147505948 ps
CPU time 0.82 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:06:35 PM PDT 24
Peak memory 207344 kb
Host smart-56da2533-0e7b-4217-8f50-1796aac9c425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85946
1480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.859461480
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3969371836
Short name T268
Test name
Test status
Simulation time 173522487 ps
CPU time 0.93 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:06:36 PM PDT 24
Peak memory 207568 kb
Host smart-a90a7e6a-ed13-4aa9-ae68-d50fe3388750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39693
71836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3969371836
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.1419657539
Short name T1598
Test name
Test status
Simulation time 1132821903 ps
CPU time 2.7 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:06:35 PM PDT 24
Peak memory 207736 kb
Host smart-ddfe8008-701b-46dd-a96c-ce0535bd4217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14196
57539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.1419657539
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.2175876406
Short name T1942
Test name
Test status
Simulation time 3309568512 ps
CPU time 34.65 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:07:07 PM PDT 24
Peak memory 215924 kb
Host smart-cdea3d19-21a7-4212-b91f-12780150a1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21758
76406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2175876406
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.3043258188
Short name T891
Test name
Test status
Simulation time 6966634472 ps
CPU time 45.84 seconds
Started Aug 17 06:06:26 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207692 kb
Host smart-86e8eea8-1c73-40d1-be0a-d511836aa1a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043258188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.3043258188
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_tx_rx_disruption.3687411973
Short name T2192
Test name
Test status
Simulation time 538677331 ps
CPU time 1.69 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:35 PM PDT 24
Peak memory 207428 kb
Host smart-60329219-2806-4adb-9c9a-d307dea2ce68
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687411973 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.usbdev_tx_rx_disruption.3687411973
Directory /workspace/19.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/190.usbdev_tx_rx_disruption.1212034718
Short name T688
Test name
Test status
Simulation time 610417702 ps
CPU time 1.69 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207576 kb
Host smart-fed73b93-7fc5-4b0a-8dff-8888dfc74427
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212034718 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 190.usbdev_tx_rx_disruption.1212034718
Directory /workspace/190.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/191.usbdev_endpoint_types.2098649163
Short name T687
Test name
Test status
Simulation time 139810656 ps
CPU time 0.87 seconds
Started Aug 17 06:11:45 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207512 kb
Host smart-9a50aa50-3cf5-4d27-880b-21501ef86307
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2098649163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.2098649163
Directory /workspace/191.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/191.usbdev_tx_rx_disruption.337261160
Short name T2568
Test name
Test status
Simulation time 511208500 ps
CPU time 1.51 seconds
Started Aug 17 06:11:58 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207520 kb
Host smart-43f76a5e-ec78-44f5-a60d-21cd01f7ccea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337261160 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 191.usbdev_tx_rx_disruption.337261160
Directory /workspace/191.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/192.usbdev_endpoint_types.1875999645
Short name T487
Test name
Test status
Simulation time 160066301 ps
CPU time 0.9 seconds
Started Aug 17 06:11:45 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207508 kb
Host smart-ecce8bac-9d8c-4777-b88f-c1eb270990ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1875999645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.1875999645
Directory /workspace/192.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/192.usbdev_tx_rx_disruption.3481041724
Short name T2980
Test name
Test status
Simulation time 575189382 ps
CPU time 1.69 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207544 kb
Host smart-6dec0c9e-85bd-455b-880b-5288ace7d189
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481041724 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.usbdev_tx_rx_disruption.3481041724
Directory /workspace/192.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/193.usbdev_endpoint_types.3958782333
Short name T430
Test name
Test status
Simulation time 762862859 ps
CPU time 1.76 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:00 PM PDT 24
Peak memory 207512 kb
Host smart-594272f1-74b2-4f64-9dfa-d8768764263d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3958782333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.3958782333
Directory /workspace/193.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/193.usbdev_tx_rx_disruption.4094148806
Short name T3116
Test name
Test status
Simulation time 514653827 ps
CPU time 1.69 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207492 kb
Host smart-0f51ab60-965f-44a8-b905-471eccd95696
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094148806 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.usbdev_tx_rx_disruption.4094148806
Directory /workspace/193.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/194.usbdev_endpoint_types.717742536
Short name T3493
Test name
Test status
Simulation time 217458530 ps
CPU time 1 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207508 kb
Host smart-c7ef029d-3eb7-4182-b19f-0c5b2be00bc3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=717742536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.717742536
Directory /workspace/194.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/194.usbdev_tx_rx_disruption.1380889260
Short name T1033
Test name
Test status
Simulation time 565342143 ps
CPU time 1.73 seconds
Started Aug 17 06:11:45 PM PDT 24
Finished Aug 17 06:11:47 PM PDT 24
Peak memory 207488 kb
Host smart-cb85ad8b-2c08-433e-9774-cb5e7a80b100
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380889260 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.usbdev_tx_rx_disruption.1380889260
Directory /workspace/194.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/195.usbdev_endpoint_types.806162144
Short name T396
Test name
Test status
Simulation time 474848009 ps
CPU time 1.31 seconds
Started Aug 17 06:11:46 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207492 kb
Host smart-dd4cbd2c-831a-4426-8e06-661f97a6abe5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=806162144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.806162144
Directory /workspace/195.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/195.usbdev_tx_rx_disruption.3113138632
Short name T3612
Test name
Test status
Simulation time 425081548 ps
CPU time 1.36 seconds
Started Aug 17 06:11:51 PM PDT 24
Finished Aug 17 06:11:52 PM PDT 24
Peak memory 207560 kb
Host smart-db767a94-de6e-4ffa-abdf-be49bf04a49c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113138632 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.usbdev_tx_rx_disruption.3113138632
Directory /workspace/195.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/196.usbdev_tx_rx_disruption.4173252484
Short name T2689
Test name
Test status
Simulation time 550209647 ps
CPU time 1.73 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207472 kb
Host smart-f280c924-b02a-424e-a09a-8d183bc9b828
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173252484 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.usbdev_tx_rx_disruption.4173252484
Directory /workspace/196.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/197.usbdev_endpoint_types.736397351
Short name T2658
Test name
Test status
Simulation time 330451786 ps
CPU time 1.26 seconds
Started Aug 17 06:11:43 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 207528 kb
Host smart-32118577-7813-4b93-9cc4-029eb6f05360
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=736397351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.736397351
Directory /workspace/197.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/197.usbdev_tx_rx_disruption.1601004951
Short name T1330
Test name
Test status
Simulation time 425476213 ps
CPU time 1.4 seconds
Started Aug 17 06:11:44 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207492 kb
Host smart-5307ef97-e8d6-47b7-b9e8-3b2b8ee45690
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601004951 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.usbdev_tx_rx_disruption.1601004951
Directory /workspace/197.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/198.usbdev_tx_rx_disruption.3880258082
Short name T195
Test name
Test status
Simulation time 598378459 ps
CPU time 1.75 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207472 kb
Host smart-2f4df680-dda6-495b-975c-90e19f1e5cb0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880258082 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.usbdev_tx_rx_disruption.3880258082
Directory /workspace/198.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/199.usbdev_endpoint_types.1862254322
Short name T467
Test name
Test status
Simulation time 216817018 ps
CPU time 1.01 seconds
Started Aug 17 06:11:45 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207460 kb
Host smart-dc458d68-ebb3-4de8-92d6-daac6fccbf32
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1862254322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.1862254322
Directory /workspace/199.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/199.usbdev_tx_rx_disruption.2154030019
Short name T2215
Test name
Test status
Simulation time 575001439 ps
CPU time 1.6 seconds
Started Aug 17 06:11:42 PM PDT 24
Finished Aug 17 06:11:44 PM PDT 24
Peak memory 207544 kb
Host smart-2b072f31-0e71-4a59-8c6a-32dcd17d8122
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154030019 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.usbdev_tx_rx_disruption.2154030019
Directory /workspace/199.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3950558658
Short name T1476
Test name
Test status
Simulation time 50335993 ps
CPU time 0.72 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:02 PM PDT 24
Peak memory 207404 kb
Host smart-9e4c1984-e9bc-4e4c-9e49-47bfb76d3fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3950558658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3950558658
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2617466993
Short name T1168
Test name
Test status
Simulation time 11621886652 ps
CPU time 14.52 seconds
Started Aug 17 06:02:53 PM PDT 24
Finished Aug 17 06:03:07 PM PDT 24
Peak memory 207788 kb
Host smart-6bf3fb29-b0f0-459b-a073-0dedc482475a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617466993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.2617466993
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1985714234
Short name T1242
Test name
Test status
Simulation time 20786141720 ps
CPU time 23.61 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:03:16 PM PDT 24
Peak memory 207712 kb
Host smart-46d76766-c198-42fc-bc61-64dea2a41654
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985714234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1985714234
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.3612951926
Short name T3338
Test name
Test status
Simulation time 25281934861 ps
CPU time 31.34 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:03:22 PM PDT 24
Peak memory 215972 kb
Host smart-ad47fd5b-6259-4f53-a966-faa6d94cc93f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612951926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.3612951926
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3350384066
Short name T2003
Test name
Test status
Simulation time 193833738 ps
CPU time 0.98 seconds
Started Aug 17 06:02:50 PM PDT 24
Finished Aug 17 06:02:51 PM PDT 24
Peak memory 207472 kb
Host smart-ddd9e57f-9536-4255-abb4-849fae33cc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33503
84066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3350384066
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.221947115
Short name T58
Test name
Test status
Simulation time 135902123 ps
CPU time 0.82 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 207380 kb
Host smart-8815ab05-4ef8-4935-8151-da381830ebb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22194
7115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.221947115
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1650038659
Short name T80
Test name
Test status
Simulation time 150396938 ps
CPU time 0.86 seconds
Started Aug 17 06:02:54 PM PDT 24
Finished Aug 17 06:02:55 PM PDT 24
Peak memory 207564 kb
Host smart-3df8febc-49f0-4a5c-8568-f9e70b3c9982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16500
38659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1650038659
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.4115414615
Short name T554
Test name
Test status
Simulation time 509280962 ps
CPU time 1.75 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 207592 kb
Host smart-468e48f6-03c7-4e4f-9fa4-60fa8db18026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41154
14615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.4115414615
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3067681581
Short name T2443
Test name
Test status
Simulation time 29090415772 ps
CPU time 51.48 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:03:43 PM PDT 24
Peak memory 207768 kb
Host smart-021f5eb2-290b-454d-897f-f4c7a6cbcd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30676
81581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3067681581
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.564200823
Short name T1204
Test name
Test status
Simulation time 2489940605 ps
CPU time 23.38 seconds
Started Aug 17 06:02:55 PM PDT 24
Finished Aug 17 06:03:18 PM PDT 24
Peak memory 207716 kb
Host smart-660d8b53-fcaf-4bb3-93f2-f1c2fc68bca2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564200823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.564200823
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.3453149716
Short name T1532
Test name
Test status
Simulation time 559066183 ps
CPU time 1.53 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 207536 kb
Host smart-092517e3-c54a-4b39-a00e-93fd8a915fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34531
49716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.3453149716
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3264675114
Short name T929
Test name
Test status
Simulation time 139179594 ps
CPU time 0.89 seconds
Started Aug 17 06:02:49 PM PDT 24
Finished Aug 17 06:02:50 PM PDT 24
Peak memory 207528 kb
Host smart-9655c922-5a48-482a-8323-12690813f397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32646
75114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3264675114
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3138928169
Short name T1820
Test name
Test status
Simulation time 46228683 ps
CPU time 0.75 seconds
Started Aug 17 06:02:55 PM PDT 24
Finished Aug 17 06:02:56 PM PDT 24
Peak memory 207376 kb
Host smart-6082af78-41f3-4b5f-899b-ead20a8cb004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31389
28169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3138928169
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.884579844
Short name T2419
Test name
Test status
Simulation time 732643705 ps
CPU time 2.28 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:02:54 PM PDT 24
Peak memory 207704 kb
Host smart-c3f2d656-99da-4d1d-8fdd-60c8cae20384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88457
9844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.884579844
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_types.3979681581
Short name T401
Test name
Test status
Simulation time 395640847 ps
CPU time 1.26 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 207512 kb
Host smart-b8d90005-2e27-45f3-aba4-b9f375da3f61
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3979681581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.3979681581
Directory /workspace/2.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.789192786
Short name T2014
Test name
Test status
Simulation time 284969629 ps
CPU time 1.72 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:02:54 PM PDT 24
Peak memory 207588 kb
Host smart-5f01bd77-be20-4ebb-b1f2-5957a4c064e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78919
2786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.789192786
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1106534413
Short name T2165
Test name
Test status
Simulation time 120233649437 ps
CPU time 176.77 seconds
Started Aug 17 06:02:53 PM PDT 24
Finished Aug 17 06:05:50 PM PDT 24
Peak memory 207612 kb
Host smart-3666ea63-8511-402b-affe-e2fece601da3
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1106534413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1106534413
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.2298673244
Short name T2073
Test name
Test status
Simulation time 92139468903 ps
CPU time 136.15 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:05:07 PM PDT 24
Peak memory 207772 kb
Host smart-537cd577-cca3-405b-b806-92e96456fa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298673244 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.2298673244
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.4081284933
Short name T2427
Test name
Test status
Simulation time 116099816469 ps
CPU time 202.66 seconds
Started Aug 17 06:02:53 PM PDT 24
Finished Aug 17 06:06:16 PM PDT 24
Peak memory 207648 kb
Host smart-36ab455e-50d0-4622-9fd6-e89e7b648cf4
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4081284933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.4081284933
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1102139818
Short name T2887
Test name
Test status
Simulation time 100270895345 ps
CPU time 148.56 seconds
Started Aug 17 06:02:54 PM PDT 24
Finished Aug 17 06:05:23 PM PDT 24
Peak memory 207796 kb
Host smart-a708a4da-872c-40f6-b2bb-27b466aa0dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102139818 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1102139818
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.1620888381
Short name T2824
Test name
Test status
Simulation time 102117761030 ps
CPU time 170.08 seconds
Started Aug 17 06:02:54 PM PDT 24
Finished Aug 17 06:05:44 PM PDT 24
Peak memory 207728 kb
Host smart-a5484d27-75a8-418e-aa6d-7d60893e3486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16208
88381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.1620888381
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2431237330
Short name T1542
Test name
Test status
Simulation time 213339120 ps
CPU time 1.12 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:02:53 PM PDT 24
Peak memory 215864 kb
Host smart-b84e6e69-bd8c-4ed5-986f-c46862730839
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2431237330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2431237330
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1438980406
Short name T3418
Test name
Test status
Simulation time 154190214 ps
CPU time 0.91 seconds
Started Aug 17 06:02:51 PM PDT 24
Finished Aug 17 06:02:52 PM PDT 24
Peak memory 207444 kb
Host smart-72994b8c-b414-4305-b43e-984200b85190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
80406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1438980406
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1424006133
Short name T723
Test name
Test status
Simulation time 195747715 ps
CPU time 0.95 seconds
Started Aug 17 06:02:59 PM PDT 24
Finished Aug 17 06:03:00 PM PDT 24
Peak memory 207464 kb
Host smart-51806c4b-e6aa-4c31-9784-796e402a4704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14240
06133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1424006133
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.1413693788
Short name T1915
Test name
Test status
Simulation time 4578051545 ps
CPU time 133.51 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:05:06 PM PDT 24
Peak memory 224052 kb
Host smart-2593292b-58e0-4542-afc7-45ff457c4a8f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1413693788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.1413693788
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.2229988797
Short name T2155
Test name
Test status
Simulation time 6045455366 ps
CPU time 74.04 seconds
Started Aug 17 06:03:04 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 207788 kb
Host smart-88c99acc-6109-4fbb-9512-563d89011571
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2229988797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.2229988797
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.468254855
Short name T2605
Test name
Test status
Simulation time 232030420 ps
CPU time 1.02 seconds
Started Aug 17 06:02:59 PM PDT 24
Finished Aug 17 06:03:00 PM PDT 24
Peak memory 207416 kb
Host smart-90233010-ec72-45c6-b29e-3fd7639ad3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46825
4855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.468254855
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1657657823
Short name T1327
Test name
Test status
Simulation time 28221733751 ps
CPU time 48.21 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:50 PM PDT 24
Peak memory 207696 kb
Host smart-67298afa-22a2-4f12-9e50-d6cf6d2a6294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16576
57823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1657657823
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2957985572
Short name T266
Test name
Test status
Simulation time 3287253566 ps
CPU time 5.22 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:14 PM PDT 24
Peak memory 216092 kb
Host smart-4160470f-4441-4b3f-9d2d-7b3d6f7f7322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29579
85572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2957985572
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2262427398
Short name T2567
Test name
Test status
Simulation time 5142214625 ps
CPU time 42.09 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:50 PM PDT 24
Peak memory 219572 kb
Host smart-63b4706e-c07d-4c31-92d9-ee25ad67ec79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2262427398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2262427398
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3368256017
Short name T1908
Test name
Test status
Simulation time 1850235697 ps
CPU time 15.08 seconds
Started Aug 17 06:03:02 PM PDT 24
Finished Aug 17 06:03:17 PM PDT 24
Peak memory 224004 kb
Host smart-0beb0efb-3ff1-4acd-9f6d-cb59c11c2c54
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3368256017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3368256017
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3792147185
Short name T1097
Test name
Test status
Simulation time 252159100 ps
CPU time 1.05 seconds
Started Aug 17 06:02:59 PM PDT 24
Finished Aug 17 06:03:00 PM PDT 24
Peak memory 207420 kb
Host smart-7c5dc2b8-af98-4bdf-a093-a50dde32e8f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3792147185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3792147185
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.366193181
Short name T3489
Test name
Test status
Simulation time 194866868 ps
CPU time 0.93 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 207428 kb
Host smart-2c46c9a6-48c2-47b9-8762-ab220a18f4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36619
3181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.366193181
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.4077322785
Short name T669
Test name
Test status
Simulation time 1978646385 ps
CPU time 54.46 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:55 PM PDT 24
Peak memory 215848 kb
Host smart-7cbb3e09-8bff-41f5-934d-a5bdecb62981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40773
22785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.4077322785
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1248077643
Short name T1648
Test name
Test status
Simulation time 3620768058 ps
CPU time 110.48 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 223940 kb
Host smart-5cbc7847-eab2-4b02-90bd-f947904a5a23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1248077643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1248077643
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3863074618
Short name T2948
Test name
Test status
Simulation time 3321176602 ps
CPU time 33.93 seconds
Started Aug 17 06:02:59 PM PDT 24
Finished Aug 17 06:03:33 PM PDT 24
Peak memory 217696 kb
Host smart-cb9b3e14-e250-4c03-ab17-a97002a46884
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3863074618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3863074618
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3790029227
Short name T950
Test name
Test status
Simulation time 167347453 ps
CPU time 0.86 seconds
Started Aug 17 06:02:59 PM PDT 24
Finished Aug 17 06:03:00 PM PDT 24
Peak memory 207484 kb
Host smart-69890898-a35a-4470-b872-c4f1fa071d48
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3790029227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3790029227
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3994230940
Short name T1380
Test name
Test status
Simulation time 167184383 ps
CPU time 0.86 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:02 PM PDT 24
Peak memory 207416 kb
Host smart-4996c1cd-39b3-479b-8837-77147ec0e377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39942
30940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3994230940
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2895248057
Short name T138
Test name
Test status
Simulation time 205036878 ps
CPU time 0.95 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 207436 kb
Host smart-a193c87a-c0e7-44b4-ab02-17ae1016cbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28952
48057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2895248057
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1684221338
Short name T1728
Test name
Test status
Simulation time 189683587 ps
CPU time 0.92 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 207480 kb
Host smart-6f45de74-4319-4a6d-83a7-598073d2e7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
21338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1684221338
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1057956729
Short name T1332
Test name
Test status
Simulation time 194120122 ps
CPU time 0.92 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 207456 kb
Host smart-eb06dcc8-dda2-4cf7-b1be-9bc039afa848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
56729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1057956729
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2112083453
Short name T992
Test name
Test status
Simulation time 186174416 ps
CPU time 0.9 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 207552 kb
Host smart-22cc796e-66fe-4763-84ca-3630b74df26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21120
83453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2112083453
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1952882753
Short name T3435
Test name
Test status
Simulation time 204124372 ps
CPU time 0.93 seconds
Started Aug 17 06:03:02 PM PDT 24
Finished Aug 17 06:03:03 PM PDT 24
Peak memory 207564 kb
Host smart-7e46a950-52bc-45db-8a7a-cfcd84e0b464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19528
82753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1952882753
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2739602748
Short name T3337
Test name
Test status
Simulation time 254778508 ps
CPU time 1.11 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:02 PM PDT 24
Peak memory 207600 kb
Host smart-40b8f886-c154-48d7-a28d-197d055c549e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2739602748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2739602748
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.2363332526
Short name T3159
Test name
Test status
Simulation time 207912580 ps
CPU time 1 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:02 PM PDT 24
Peak memory 207400 kb
Host smart-c35b542a-c326-48c7-993f-f00e479df583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23633
32526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.2363332526
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1623261592
Short name T2999
Test name
Test status
Simulation time 216078913 ps
CPU time 0.94 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 207452 kb
Host smart-55337968-d88e-4f09-a40f-abde6e0f5a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16232
61592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1623261592
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1580625049
Short name T2614
Test name
Test status
Simulation time 44206132 ps
CPU time 0.76 seconds
Started Aug 17 06:03:04 PM PDT 24
Finished Aug 17 06:03:04 PM PDT 24
Peak memory 207532 kb
Host smart-99d5ee46-454d-4d52-a387-dfe834041525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
25049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1580625049
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.4265622723
Short name T85
Test name
Test status
Simulation time 146243055 ps
CPU time 0.92 seconds
Started Aug 17 06:03:04 PM PDT 24
Finished Aug 17 06:03:05 PM PDT 24
Peak memory 207568 kb
Host smart-a6856168-02f6-4f00-ad1b-a00ab3eb4ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42656
22723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.4265622723
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2758570831
Short name T3266
Test name
Test status
Simulation time 214816970 ps
CPU time 1.01 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 207428 kb
Host smart-38f85a19-3356-4478-aa8d-cd64137a98d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27585
70831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2758570831
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3587219351
Short name T2261
Test name
Test status
Simulation time 2413152951 ps
CPU time 18.9 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:20 PM PDT 24
Peak memory 218704 kb
Host smart-ffe95e27-b940-4a2c-94d8-a040132b4cd9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587219351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3587219351
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1079495378
Short name T1263
Test name
Test status
Simulation time 6320165130 ps
CPU time 171.65 seconds
Started Aug 17 06:02:59 PM PDT 24
Finished Aug 17 06:05:51 PM PDT 24
Peak memory 218348 kb
Host smart-a727abf2-2743-4317-a2c5-f6252524d09e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1079495378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1079495378
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3155662494
Short name T2397
Test name
Test status
Simulation time 11124181800 ps
CPU time 76.75 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 218812 kb
Host smart-3b49a588-a701-45d9-b70a-bba6a50a1233
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155662494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3155662494
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.930638002
Short name T547
Test name
Test status
Simulation time 243297327 ps
CPU time 1.01 seconds
Started Aug 17 06:02:58 PM PDT 24
Finished Aug 17 06:02:59 PM PDT 24
Peak memory 207440 kb
Host smart-5c1fcea8-dabe-4363-99db-06955d98a1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93063
8002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.930638002
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1659346414
Short name T3354
Test name
Test status
Simulation time 189899983 ps
CPU time 0.97 seconds
Started Aug 17 06:03:02 PM PDT 24
Finished Aug 17 06:03:03 PM PDT 24
Peak memory 207436 kb
Host smart-57de3465-9cbc-4aa1-bccb-102c6413a027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16593
46414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1659346414
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_resume_link_active.3683678
Short name T1120
Test name
Test status
Simulation time 20178376541 ps
CPU time 24.16 seconds
Started Aug 17 06:03:02 PM PDT 24
Finished Aug 17 06:03:27 PM PDT 24
Peak memory 207584 kb
Host smart-3a66d42f-21b2-4d2b-9e4a-4ec64fc61782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36836
78 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.3683678
Directory /workspace/2.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1354416927
Short name T2504
Test name
Test status
Simulation time 192557318 ps
CPU time 0.95 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:02 PM PDT 24
Peak memory 207432 kb
Host smart-074d1f06-9a10-47e0-8e36-b896a0c340d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13544
16927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1354416927
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_full.3049356600
Short name T330
Test name
Test status
Simulation time 267935888 ps
CPU time 1.12 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:03 PM PDT 24
Peak memory 207464 kb
Host smart-96aec881-f0ac-4efc-bf5d-a9b70d861a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30493
56600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.3049356600
Directory /workspace/2.usbdev_rx_full/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2230185809
Short name T77
Test name
Test status
Simulation time 180694013 ps
CPU time 0.94 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:02 PM PDT 24
Peak memory 207432 kb
Host smart-5cfe2acc-4c82-4d36-9d47-f2462b6ef266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22301
85809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2230185809
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2839713945
Short name T89
Test name
Test status
Simulation time 256924096 ps
CPU time 1.1 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 223324 kb
Host smart-d3bfd69d-a275-45c5-b204-114bb37473d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2839713945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2839713945
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1764956875
Short name T45
Test name
Test status
Simulation time 380465029 ps
CPU time 1.39 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 207512 kb
Host smart-737d3527-2224-45a0-834d-9e9f5fd47d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17649
56875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1764956875
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3081404749
Short name T3298
Test name
Test status
Simulation time 222231709 ps
CPU time 1.01 seconds
Started Aug 17 06:02:57 PM PDT 24
Finished Aug 17 06:02:58 PM PDT 24
Peak memory 207504 kb
Host smart-7d62e544-7147-4b75-b792-44b509d580fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30814
04749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3081404749
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2211990047
Short name T1426
Test name
Test status
Simulation time 152184822 ps
CPU time 0.85 seconds
Started Aug 17 06:02:59 PM PDT 24
Finished Aug 17 06:03:00 PM PDT 24
Peak memory 207428 kb
Host smart-36133c37-7cfb-4e35-9d10-e54cf1d282e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22119
90047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2211990047
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.468802077
Short name T2782
Test name
Test status
Simulation time 182129220 ps
CPU time 0.92 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 207552 kb
Host smart-4be92a5d-7981-4855-b449-cc7430d3bff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46880
2077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.468802077
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1096836255
Short name T3515
Test name
Test status
Simulation time 205484409 ps
CPU time 1.06 seconds
Started Aug 17 06:02:59 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 207484 kb
Host smart-ff8418f5-c056-48a1-8a6b-236e98411518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10968
36255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1096836255
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1161482591
Short name T3367
Test name
Test status
Simulation time 3453547292 ps
CPU time 94.29 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:04:35 PM PDT 24
Peak memory 224096 kb
Host smart-25c96ac7-739a-4c83-a6dd-94ac291cfff6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1161482591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1161482591
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.742053831
Short name T3393
Test name
Test status
Simulation time 213819907 ps
CPU time 0.9 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:02 PM PDT 24
Peak memory 207344 kb
Host smart-0369642c-476c-472f-97cf-7b9baedd83a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74205
3831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.742053831
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.332883295
Short name T3618
Test name
Test status
Simulation time 211394137 ps
CPU time 0.96 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:02 PM PDT 24
Peak memory 207456 kb
Host smart-16a97fc0-8cdd-41ca-895f-90309a641efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33288
3295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.332883295
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1845658000
Short name T2214
Test name
Test status
Simulation time 381746640 ps
CPU time 1.3 seconds
Started Aug 17 06:02:58 PM PDT 24
Finished Aug 17 06:02:59 PM PDT 24
Peak memory 207524 kb
Host smart-e6bda50f-367a-4d6f-9b71-4ae196eec995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18456
58000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1845658000
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2288933291
Short name T3141
Test name
Test status
Simulation time 2363156085 ps
CPU time 73.16 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:04:14 PM PDT 24
Peak memory 217188 kb
Host smart-e2aa4f11-3276-42a0-bf58-d2a214582e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22889
33291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2288933291
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3171018037
Short name T3003
Test name
Test status
Simulation time 12332367583 ps
CPU time 78.25 seconds
Started Aug 17 06:03:00 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 218416 kb
Host smart-9598d24d-f398-4965-93df-8e8e139c6f48
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171018037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.3171018037
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.4258499566
Short name T1267
Test name
Test status
Simulation time 2002640019 ps
CPU time 13.81 seconds
Started Aug 17 06:02:52 PM PDT 24
Finished Aug 17 06:03:06 PM PDT 24
Peak memory 207636 kb
Host smart-e4aee034-0c36-48da-b3b8-065511e71857
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258499566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.4258499566
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_tx_rx_disruption.2278195205
Short name T3360
Test name
Test status
Simulation time 489370839 ps
CPU time 1.56 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:10 PM PDT 24
Peak memory 207552 kb
Host smart-de2c03d8-4b01-48ec-95fd-184ad148adb9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278195205 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.usbdev_tx_rx_disruption.2278195205
Directory /workspace/2.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.1048332772
Short name T1707
Test name
Test status
Simulation time 49345911 ps
CPU time 0.72 seconds
Started Aug 17 06:06:42 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 207436 kb
Host smart-253fca3b-9bb1-4af8-a885-8de136125829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1048332772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.1048332772
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.90798629
Short name T2686
Test name
Test status
Simulation time 11433371739 ps
CPU time 17.99 seconds
Started Aug 17 06:06:37 PM PDT 24
Finished Aug 17 06:06:55 PM PDT 24
Peak memory 207804 kb
Host smart-16d9f977-946e-4dd4-8b32-a13731351cef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90798629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon
_wake_disconnect.90798629
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1289915418
Short name T3031
Test name
Test status
Simulation time 19740012528 ps
CPU time 25.33 seconds
Started Aug 17 06:06:38 PM PDT 24
Finished Aug 17 06:07:03 PM PDT 24
Peak memory 207820 kb
Host smart-51c40eb9-0c9c-4e38-8e0d-1f466f1543d6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289915418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1289915418
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3161111373
Short name T2478
Test name
Test status
Simulation time 29610137023 ps
CPU time 33.14 seconds
Started Aug 17 06:06:38 PM PDT 24
Finished Aug 17 06:07:11 PM PDT 24
Peak memory 207720 kb
Host smart-4721a570-2e66-4330-aa18-c39400560675
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161111373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.3161111373
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1482030963
Short name T1350
Test name
Test status
Simulation time 230634586 ps
CPU time 1 seconds
Started Aug 17 06:06:38 PM PDT 24
Finished Aug 17 06:06:39 PM PDT 24
Peak memory 207480 kb
Host smart-9fb579c8-3fe6-42dd-a185-bdc119619a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14820
30963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1482030963
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3499400601
Short name T1888
Test name
Test status
Simulation time 184202333 ps
CPU time 0.88 seconds
Started Aug 17 06:06:38 PM PDT 24
Finished Aug 17 06:06:39 PM PDT 24
Peak memory 207104 kb
Host smart-4a6f2ef0-3031-4c4f-83f6-5c1a618b5ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34994
00601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3499400601
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.161583232
Short name T86
Test name
Test status
Simulation time 288567873 ps
CPU time 1.09 seconds
Started Aug 17 06:06:38 PM PDT 24
Finished Aug 17 06:06:40 PM PDT 24
Peak memory 207484 kb
Host smart-5eef634e-2501-4ab4-ad41-0d72951e9ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16158
3232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.161583232
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.13518132
Short name T340
Test name
Test status
Simulation time 767249732 ps
CPU time 2.33 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:35 PM PDT 24
Peak memory 207772 kb
Host smart-8fb84407-7fb5-40b0-8bb7-53806b839d0a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=13518132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.13518132
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.163720083
Short name T1320
Test name
Test status
Simulation time 6993093500 ps
CPU time 48.72 seconds
Started Aug 17 06:06:38 PM PDT 24
Finished Aug 17 06:07:27 PM PDT 24
Peak memory 207764 kb
Host smart-2bc11ea2-7a67-4dcb-99d8-23f9f72dc24b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163720083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.163720083
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3955729590
Short name T2285
Test name
Test status
Simulation time 894675913 ps
CPU time 2.16 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:36 PM PDT 24
Peak memory 207500 kb
Host smart-b28ab7ba-988a-442c-887e-4e922e59fafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39557
29590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3955729590
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1877736912
Short name T746
Test name
Test status
Simulation time 142649008 ps
CPU time 0.91 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:06:35 PM PDT 24
Peak memory 207512 kb
Host smart-1e32b272-baf5-4468-924a-d04a60ab4a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18777
36912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1877736912
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1121963633
Short name T1678
Test name
Test status
Simulation time 37620415 ps
CPU time 0.71 seconds
Started Aug 17 06:06:38 PM PDT 24
Finished Aug 17 06:06:39 PM PDT 24
Peak memory 207424 kb
Host smart-b7fa9374-4421-44dc-a1ff-245e75217735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11219
63633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1121963633
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3565453247
Short name T3464
Test name
Test status
Simulation time 941233916 ps
CPU time 2.75 seconds
Started Aug 17 06:06:35 PM PDT 24
Finished Aug 17 06:06:38 PM PDT 24
Peak memory 207736 kb
Host smart-024b6db0-0907-40c5-ae4d-7b6dda3554fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35654
53247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3565453247
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_types.3694821829
Short name T906
Test name
Test status
Simulation time 242334896 ps
CPU time 0.99 seconds
Started Aug 17 06:06:35 PM PDT 24
Finished Aug 17 06:06:36 PM PDT 24
Peak memory 207512 kb
Host smart-b10097b9-73fc-4b35-a529-1c0082b178ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3694821829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.3694821829
Directory /workspace/20.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1342843652
Short name T578
Test name
Test status
Simulation time 324455212 ps
CPU time 2.76 seconds
Started Aug 17 06:06:35 PM PDT 24
Finished Aug 17 06:06:38 PM PDT 24
Peak memory 207624 kb
Host smart-d75786a3-12a4-46e5-9ed6-997db723548c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13428
43652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1342843652
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2746769303
Short name T1719
Test name
Test status
Simulation time 208788341 ps
CPU time 1.04 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:42 PM PDT 24
Peak memory 216096 kb
Host smart-abb1fabe-a01b-4034-9b6b-2e78bf521b1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2746769303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2746769303
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4216827678
Short name T2461
Test name
Test status
Simulation time 170929607 ps
CPU time 0.84 seconds
Started Aug 17 06:06:32 PM PDT 24
Finished Aug 17 06:06:33 PM PDT 24
Peak memory 207444 kb
Host smart-3c234ce5-758d-4e16-9326-2a7dc85a8010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42168
27678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4216827678
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3971516742
Short name T1145
Test name
Test status
Simulation time 228958173 ps
CPU time 0.98 seconds
Started Aug 17 06:06:42 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 207396 kb
Host smart-9770ab93-60c5-43e1-8938-1edc7d85940a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715
16742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3971516742
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.1465255426
Short name T1119
Test name
Test status
Simulation time 5298528782 ps
CPU time 161.55 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:09:16 PM PDT 24
Peak memory 215932 kb
Host smart-9d7c0dcc-1e42-4b4c-a802-7289a10c0291
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1465255426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.1465255426
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.959788401
Short name T1443
Test name
Test status
Simulation time 10556283977 ps
CPU time 133.37 seconds
Started Aug 17 06:06:34 PM PDT 24
Finished Aug 17 06:08:47 PM PDT 24
Peak memory 207788 kb
Host smart-d180e3c3-27a9-4abc-9ace-26ee0a68ae1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=959788401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.959788401
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3774561404
Short name T1969
Test name
Test status
Simulation time 189190852 ps
CPU time 0.92 seconds
Started Aug 17 06:06:33 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207564 kb
Host smart-a9fe036b-2d14-4b5d-bda3-3e58bb4df764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37745
61404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3774561404
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.845527209
Short name T2476
Test name
Test status
Simulation time 26767097264 ps
CPU time 37.46 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 215900 kb
Host smart-30f62d41-607f-4d15-879d-a1a0daa3dfbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84552
7209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.845527209
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2429741411
Short name T2859
Test name
Test status
Simulation time 9565120739 ps
CPU time 13.66 seconds
Started Aug 17 06:06:41 PM PDT 24
Finished Aug 17 06:06:55 PM PDT 24
Peak memory 207796 kb
Host smart-a54f0f6b-d2c0-400d-acda-19aa835bd556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24297
41411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2429741411
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.589611734
Short name T2595
Test name
Test status
Simulation time 3180095965 ps
CPU time 33.74 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 219072 kb
Host smart-be350fd0-76bc-4d69-9fda-0c028ae0900a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=589611734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.589611734
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.1741133088
Short name T693
Test name
Test status
Simulation time 1771872014 ps
CPU time 53.25 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:07:33 PM PDT 24
Peak memory 215820 kb
Host smart-56fbf482-40c2-4d1e-af34-2386d38f0b7e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1741133088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.1741133088
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.4092329026
Short name T3009
Test name
Test status
Simulation time 277278425 ps
CPU time 1 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:42 PM PDT 24
Peak memory 207476 kb
Host smart-c9fcac8b-275b-4d46-8156-0dca64ac6f49
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4092329026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.4092329026
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2955869799
Short name T2877
Test name
Test status
Simulation time 230658303 ps
CPU time 0.98 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 207428 kb
Host smart-ec5b4f0b-4a8a-4da5-8b78-ad793071f551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29558
69799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2955869799
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.2437014258
Short name T3404
Test name
Test status
Simulation time 2982949339 ps
CPU time 23.6 seconds
Started Aug 17 06:06:43 PM PDT 24
Finished Aug 17 06:07:07 PM PDT 24
Peak memory 224096 kb
Host smart-5de09595-42ea-4d32-8841-480c3c6b42f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24370
14258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.2437014258
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.3984793786
Short name T114
Test name
Test status
Simulation time 3122753509 ps
CPU time 26.52 seconds
Started Aug 17 06:06:39 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 215924 kb
Host smart-3bc6cedc-01b8-45b1-8f02-d03c5e858f20
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3984793786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.3984793786
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.2672028908
Short name T1032
Test name
Test status
Simulation time 162699211 ps
CPU time 0.83 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 207476 kb
Host smart-54eb847e-1b8e-45dd-af16-eb5dfdcf12ea
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2672028908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.2672028908
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2698623165
Short name T628
Test name
Test status
Simulation time 149179984 ps
CPU time 0.85 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:06:45 PM PDT 24
Peak memory 207444 kb
Host smart-aadccc22-0a46-422c-9f64-bf75748cd547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26986
23165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2698623165
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.448468298
Short name T1549
Test name
Test status
Simulation time 221856858 ps
CPU time 1.01 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:42 PM PDT 24
Peak memory 207480 kb
Host smart-b10532e0-9c2b-488e-afc2-da3d499af95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44846
8298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.448468298
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.884105188
Short name T1246
Test name
Test status
Simulation time 201188722 ps
CPU time 0.95 seconds
Started Aug 17 06:06:43 PM PDT 24
Finished Aug 17 06:06:44 PM PDT 24
Peak memory 207424 kb
Host smart-318ac981-76b5-4322-b7af-1fd46614272c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88410
5188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.884105188
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2195532845
Short name T1188
Test name
Test status
Simulation time 188331670 ps
CPU time 0.86 seconds
Started Aug 17 06:06:39 PM PDT 24
Finished Aug 17 06:06:40 PM PDT 24
Peak memory 207452 kb
Host smart-cdc4a95e-ce74-4bf5-be24-08ddf96a6129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21955
32845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2195532845
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.635123546
Short name T3346
Test name
Test status
Simulation time 201593370 ps
CPU time 0.9 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 207540 kb
Host smart-d4c75496-807a-40ac-944a-35f52704f40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63512
3546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.635123546
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1502128432
Short name T2570
Test name
Test status
Simulation time 240049557 ps
CPU time 0.95 seconds
Started Aug 17 06:06:40 PM PDT 24
Finished Aug 17 06:06:41 PM PDT 24
Peak memory 207572 kb
Host smart-93240888-fced-47f7-b87d-6342e42fddb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15021
28432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1502128432
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2289708404
Short name T558
Test name
Test status
Simulation time 232144099 ps
CPU time 1.09 seconds
Started Aug 17 06:06:43 PM PDT 24
Finished Aug 17 06:06:44 PM PDT 24
Peak memory 207552 kb
Host smart-86c5044a-a698-42c9-b0fb-a69da7268f9e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2289708404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2289708404
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.388073021
Short name T639
Test name
Test status
Simulation time 154133970 ps
CPU time 0.81 seconds
Started Aug 17 06:06:43 PM PDT 24
Finished Aug 17 06:06:44 PM PDT 24
Peak memory 207448 kb
Host smart-5ac8fe37-a8b8-4647-9550-22541634a0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38807
3021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.388073021
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3579424994
Short name T2219
Test name
Test status
Simulation time 8428082231 ps
CPU time 23.69 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:07:10 PM PDT 24
Peak memory 220688 kb
Host smart-a755c12a-98bb-4e30-87ff-f53f338641a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35794
24994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3579424994
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2940373289
Short name T2661
Test name
Test status
Simulation time 157369670 ps
CPU time 0.9 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:06:45 PM PDT 24
Peak memory 207552 kb
Host smart-3078bc08-fc7d-4cb8-9315-d85ef4693874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
73289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2940373289
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2878935520
Short name T790
Test name
Test status
Simulation time 167681592 ps
CPU time 0.86 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 207648 kb
Host smart-bbddd659-4b51-4ddf-a008-955f2821d802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
35520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2878935520
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.1497354540
Short name T1186
Test name
Test status
Simulation time 170520974 ps
CPU time 0.84 seconds
Started Aug 17 06:06:42 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 207420 kb
Host smart-063150f6-ede6-4f84-ade6-926626ee4e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14973
54540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.1497354540
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.118655410
Short name T3310
Test name
Test status
Simulation time 257578226 ps
CPU time 1.04 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:06:45 PM PDT 24
Peak memory 207476 kb
Host smart-66f23fff-152b-4a57-88c9-924e26ea047e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11865
5410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.118655410
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1251250204
Short name T71
Test name
Test status
Simulation time 143332551 ps
CPU time 0.8 seconds
Started Aug 17 06:06:42 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 207396 kb
Host smart-4c9ed6d0-c724-46a7-9dd4-f9b9e543b546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512
50204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1251250204
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_rx_full.2541862163
Short name T1791
Test name
Test status
Simulation time 283886940 ps
CPU time 1.12 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:06:45 PM PDT 24
Peak memory 207452 kb
Host smart-846d315c-f86f-4995-abf8-69624542aa0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25418
62163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.2541862163
Directory /workspace/20.usbdev_rx_full/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1430516982
Short name T2604
Test name
Test status
Simulation time 155766056 ps
CPU time 0.83 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 207696 kb
Host smart-9efc2162-d68f-499c-b5b2-fc5307fb40a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14305
16982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1430516982
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3536161570
Short name T815
Test name
Test status
Simulation time 150825194 ps
CPU time 0.86 seconds
Started Aug 17 06:06:41 PM PDT 24
Finished Aug 17 06:06:42 PM PDT 24
Peak memory 207468 kb
Host smart-c7a75ccf-98af-4dad-8141-e7a2524b76f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35361
61570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3536161570
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.782115285
Short name T2243
Test name
Test status
Simulation time 180124050 ps
CPU time 0.98 seconds
Started Aug 17 06:06:43 PM PDT 24
Finished Aug 17 06:06:44 PM PDT 24
Peak memory 207480 kb
Host smart-332cdf18-9363-4080-970b-48af5b863509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78211
5285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.782115285
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2417546426
Short name T1201
Test name
Test status
Simulation time 2246704754 ps
CPU time 63.15 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:07:48 PM PDT 24
Peak memory 217332 kb
Host smart-7d741b90-ca35-4c65-87e9-6aaad0c82cad
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2417546426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2417546426
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3964273473
Short name T1754
Test name
Test status
Simulation time 189270772 ps
CPU time 0.94 seconds
Started Aug 17 06:06:42 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 207488 kb
Host smart-1c3f1958-3568-46bd-b844-37202e69d1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39642
73473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3964273473
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1098867326
Short name T3257
Test name
Test status
Simulation time 179357339 ps
CPU time 0.95 seconds
Started Aug 17 06:06:42 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 207560 kb
Host smart-940a5848-9c18-47f5-8231-bec3dbd0b000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10988
67326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1098867326
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2254517226
Short name T783
Test name
Test status
Simulation time 194885433 ps
CPU time 0.94 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:06:45 PM PDT 24
Peak memory 207560 kb
Host smart-0aaad0f8-7844-4159-b5dd-3634c4a1b826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22545
17226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2254517226
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3382093713
Short name T1679
Test name
Test status
Simulation time 3801430465 ps
CPU time 28.31 seconds
Started Aug 17 06:06:43 PM PDT 24
Finished Aug 17 06:07:11 PM PDT 24
Peak memory 217644 kb
Host smart-4e89354b-cf1e-4357-842e-40ba07f66c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33820
93713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3382093713
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.2657681967
Short name T896
Test name
Test status
Simulation time 5258098510 ps
CPU time 46.93 seconds
Started Aug 17 06:06:38 PM PDT 24
Finished Aug 17 06:07:25 PM PDT 24
Peak memory 207308 kb
Host smart-85ea5cde-5c3a-4b0a-b9e7-fc0df543ccf1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657681967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.2657681967
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_tx_rx_disruption.2221849270
Short name T2843
Test name
Test status
Simulation time 525972959 ps
CPU time 1.74 seconds
Started Aug 17 06:06:41 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 207480 kb
Host smart-d5fa22b7-0a3c-40ca-a578-7d3a744e52a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221849270 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.usbdev_tx_rx_disruption.2221849270
Directory /workspace/20.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/200.usbdev_tx_rx_disruption.907811431
Short name T3342
Test name
Test status
Simulation time 637710440 ps
CPU time 1.79 seconds
Started Aug 17 06:11:46 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207584 kb
Host smart-4e12336c-af4b-4ad2-b80a-17192d9cd100
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907811431 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 200.usbdev_tx_rx_disruption.907811431
Directory /workspace/200.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/201.usbdev_tx_rx_disruption.2002702558
Short name T202
Test name
Test status
Simulation time 497919768 ps
CPU time 1.48 seconds
Started Aug 17 06:12:04 PM PDT 24
Finished Aug 17 06:12:06 PM PDT 24
Peak memory 207512 kb
Host smart-e4fe4d0e-dcd1-4d0a-a587-23e425a891a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002702558 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.usbdev_tx_rx_disruption.2002702558
Directory /workspace/201.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/202.usbdev_tx_rx_disruption.351037856
Short name T3348
Test name
Test status
Simulation time 587650553 ps
CPU time 1.65 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207560 kb
Host smart-ea73bf9b-932d-41fe-b960-40052325070e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351037856 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 202.usbdev_tx_rx_disruption.351037856
Directory /workspace/202.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/203.usbdev_tx_rx_disruption.2735019552
Short name T1868
Test name
Test status
Simulation time 644959663 ps
CPU time 1.88 seconds
Started Aug 17 06:11:45 PM PDT 24
Finished Aug 17 06:11:47 PM PDT 24
Peak memory 207528 kb
Host smart-98ace075-5fa1-4501-8032-c2eb6457ac3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735019552 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.usbdev_tx_rx_disruption.2735019552
Directory /workspace/203.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/204.usbdev_tx_rx_disruption.3003912161
Short name T1412
Test name
Test status
Simulation time 458276160 ps
CPU time 1.48 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207512 kb
Host smart-eacd5f01-ef51-43f2-84eb-7216a647636b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003912161 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.usbdev_tx_rx_disruption.3003912161
Directory /workspace/204.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/205.usbdev_tx_rx_disruption.1406225739
Short name T1361
Test name
Test status
Simulation time 549615806 ps
CPU time 1.7 seconds
Started Aug 17 06:11:46 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207508 kb
Host smart-29200860-a21b-4ada-8ce1-2a886d22c331
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406225739 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.usbdev_tx_rx_disruption.1406225739
Directory /workspace/205.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/206.usbdev_tx_rx_disruption.3485256847
Short name T3492
Test name
Test status
Simulation time 554752147 ps
CPU time 1.67 seconds
Started Aug 17 06:11:54 PM PDT 24
Finished Aug 17 06:11:56 PM PDT 24
Peak memory 207504 kb
Host smart-4954e87e-5f6e-4039-b63a-f08c6cc6ea91
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485256847 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.usbdev_tx_rx_disruption.3485256847
Directory /workspace/206.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/207.usbdev_tx_rx_disruption.3508778371
Short name T106
Test name
Test status
Simulation time 495719473 ps
CPU time 1.61 seconds
Started Aug 17 06:11:46 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207508 kb
Host smart-5f5021a3-477b-47d6-bb3b-334790c72239
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508778371 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.usbdev_tx_rx_disruption.3508778371
Directory /workspace/207.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/208.usbdev_tx_rx_disruption.538415114
Short name T2284
Test name
Test status
Simulation time 505552183 ps
CPU time 1.62 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207504 kb
Host smart-1aeaab5c-111e-4b78-9d90-c4780c641053
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538415114 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 208.usbdev_tx_rx_disruption.538415114
Directory /workspace/208.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/209.usbdev_tx_rx_disruption.3137406181
Short name T1193
Test name
Test status
Simulation time 582490893 ps
CPU time 1.64 seconds
Started Aug 17 06:11:47 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 207564 kb
Host smart-ad2a1d54-7dd2-4cc3-8e34-9e8e528100c0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137406181 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.usbdev_tx_rx_disruption.3137406181
Directory /workspace/209.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1526884993
Short name T2244
Test name
Test status
Simulation time 40876288 ps
CPU time 0.72 seconds
Started Aug 17 06:06:57 PM PDT 24
Finished Aug 17 06:06:58 PM PDT 24
Peak memory 207448 kb
Host smart-58df35c6-8052-4fc5-9bd2-bb3a4868e1ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1526884993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1526884993
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3401861647
Short name T3385
Test name
Test status
Simulation time 9778653349 ps
CPU time 12.03 seconds
Started Aug 17 06:06:41 PM PDT 24
Finished Aug 17 06:06:53 PM PDT 24
Peak memory 207824 kb
Host smart-52f928f4-bb5a-46ba-8d11-7581dcb9fb7c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401861647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.3401861647
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2291194912
Short name T3326
Test name
Test status
Simulation time 13648399012 ps
CPU time 16.52 seconds
Started Aug 17 06:06:42 PM PDT 24
Finished Aug 17 06:06:58 PM PDT 24
Peak memory 215984 kb
Host smart-19dcf293-021a-4dfc-af28-9fe8ccb929a1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291194912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2291194912
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.683022255
Short name T2747
Test name
Test status
Simulation time 26285528257 ps
CPU time 32.16 seconds
Started Aug 17 06:06:41 PM PDT 24
Finished Aug 17 06:07:13 PM PDT 24
Peak memory 215888 kb
Host smart-9f77e00d-45f7-4bf8-af12-49441c0921c4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683022255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ao
n_wake_resume.683022255
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.4132557313
Short name T2185
Test name
Test status
Simulation time 152185259 ps
CPU time 0.86 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:06:45 PM PDT 24
Peak memory 207516 kb
Host smart-ef249d2a-45fb-455d-ae59-cb31c74c071b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41325
57313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.4132557313
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.2498384717
Short name T1149
Test name
Test status
Simulation time 143135901 ps
CPU time 0.82 seconds
Started Aug 17 06:06:42 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 207548 kb
Host smart-af74839f-9dfe-425d-a68c-195bd9c8e5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24983
84717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.2498384717
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2316826137
Short name T26
Test name
Test status
Simulation time 502290317 ps
CPU time 1.78 seconds
Started Aug 17 06:06:41 PM PDT 24
Finished Aug 17 06:06:43 PM PDT 24
Peak memory 207536 kb
Host smart-c1c6502c-8026-4a14-8a74-471cc7f35d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23168
26137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2316826137
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2820375034
Short name T375
Test name
Test status
Simulation time 41400528725 ps
CPU time 62.7 seconds
Started Aug 17 06:06:42 PM PDT 24
Finished Aug 17 06:07:44 PM PDT 24
Peak memory 207812 kb
Host smart-bc174a6e-844f-4dbc-9377-28f222baf1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28203
75034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2820375034
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.884877887
Short name T2083
Test name
Test status
Simulation time 923154856 ps
CPU time 19.21 seconds
Started Aug 17 06:06:37 PM PDT 24
Finished Aug 17 06:06:56 PM PDT 24
Peak memory 207708 kb
Host smart-0e201c7a-09bb-4647-8cf0-92f2ac7472bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884877887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.884877887
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.107130032
Short name T1386
Test name
Test status
Simulation time 1418373914 ps
CPU time 2.88 seconds
Started Aug 17 06:06:48 PM PDT 24
Finished Aug 17 06:06:51 PM PDT 24
Peak memory 207520 kb
Host smart-20e47682-cf8c-4a90-86e9-6d135c77567f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10713
0032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.107130032
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3624334395
Short name T1632
Test name
Test status
Simulation time 170834541 ps
CPU time 0.84 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 207528 kb
Host smart-eda0bbfc-5902-4e8a-922f-e66f997b3e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36243
34395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3624334395
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2890156067
Short name T883
Test name
Test status
Simulation time 77115308 ps
CPU time 0.77 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 207444 kb
Host smart-ad4c5c56-b217-4200-ba5f-fcd44faaeb96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
56067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2890156067
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2704819470
Short name T2122
Test name
Test status
Simulation time 879049933 ps
CPU time 2.5 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:06:49 PM PDT 24
Peak memory 207768 kb
Host smart-becd9595-b4b4-4fd4-b251-d11367574577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27048
19470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2704819470
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_types.2374040522
Short name T3572
Test name
Test status
Simulation time 226356715 ps
CPU time 0.94 seconds
Started Aug 17 06:06:55 PM PDT 24
Finished Aug 17 06:06:56 PM PDT 24
Peak memory 207520 kb
Host smart-d319039d-7f37-4861-84a0-4bd256084314
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2374040522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.2374040522
Directory /workspace/21.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.171314441
Short name T3280
Test name
Test status
Simulation time 208033724 ps
CPU time 1.77 seconds
Started Aug 17 06:06:52 PM PDT 24
Finished Aug 17 06:06:54 PM PDT 24
Peak memory 207676 kb
Host smart-6ac14e0c-dfb4-48c8-9a19-1e1568fa57ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.171314441
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3171530288
Short name T3035
Test name
Test status
Simulation time 151729253 ps
CPU time 0.89 seconds
Started Aug 17 06:06:47 PM PDT 24
Finished Aug 17 06:06:48 PM PDT 24
Peak memory 207480 kb
Host smart-70713b20-2ce3-4463-90db-1057fe85c5d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3171530288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3171530288
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3826246723
Short name T2922
Test name
Test status
Simulation time 145568784 ps
CPU time 0.85 seconds
Started Aug 17 06:06:47 PM PDT 24
Finished Aug 17 06:06:48 PM PDT 24
Peak memory 207428 kb
Host smart-ab005c45-5822-4661-800b-f9faf544e72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38262
46723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3826246723
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.429066945
Short name T3544
Test name
Test status
Simulation time 217814575 ps
CPU time 1.03 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:06:48 PM PDT 24
Peak memory 207464 kb
Host smart-729cda19-e807-4b09-9c6b-18aadbda3530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42906
6945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.429066945
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.1902395161
Short name T1226
Test name
Test status
Simulation time 5064762892 ps
CPU time 53.43 seconds
Started Aug 17 06:06:47 PM PDT 24
Finished Aug 17 06:07:41 PM PDT 24
Peak memory 217764 kb
Host smart-09f55768-29e0-42fc-9a0e-c325437b827c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1902395161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1902395161
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.3503200761
Short name T2907
Test name
Test status
Simulation time 4337968444 ps
CPU time 57.72 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:07:44 PM PDT 24
Peak memory 207836 kb
Host smart-f13cc112-c780-4521-90d0-a26408cd6eee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3503200761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.3503200761
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2972565498
Short name T585
Test name
Test status
Simulation time 250469070 ps
CPU time 1.12 seconds
Started Aug 17 06:06:54 PM PDT 24
Finished Aug 17 06:06:55 PM PDT 24
Peak memory 207536 kb
Host smart-ecc1860f-a70a-4a96-b963-38a70701668d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29725
65498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2972565498
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3835456233
Short name T2511
Test name
Test status
Simulation time 3509153855 ps
CPU time 5.18 seconds
Started Aug 17 06:06:44 PM PDT 24
Finished Aug 17 06:06:49 PM PDT 24
Peak memory 207752 kb
Host smart-74e537aa-963d-41dc-9133-bcc7c3480edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38354
56233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3835456233
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.2814514203
Short name T1781
Test name
Test status
Simulation time 4757078206 ps
CPU time 54.3 seconds
Started Aug 17 06:06:48 PM PDT 24
Finished Aug 17 06:07:42 PM PDT 24
Peak memory 218552 kb
Host smart-a20dd40d-76b9-4b69-89ee-4880eeac76ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2814514203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.2814514203
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3860311732
Short name T1523
Test name
Test status
Simulation time 3447178700 ps
CPU time 110.36 seconds
Started Aug 17 06:06:49 PM PDT 24
Finished Aug 17 06:08:40 PM PDT 24
Peak memory 217560 kb
Host smart-7bd62363-7b33-47d6-b500-d3a01f421441
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3860311732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3860311732
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2560207141
Short name T3510
Test name
Test status
Simulation time 244009244 ps
CPU time 1.01 seconds
Started Aug 17 06:06:48 PM PDT 24
Finished Aug 17 06:06:49 PM PDT 24
Peak memory 207404 kb
Host smart-485ccff2-f737-46eb-8086-29f52bb466b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2560207141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2560207141
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.4266806733
Short name T527
Test name
Test status
Simulation time 194713870 ps
CPU time 1.16 seconds
Started Aug 17 06:06:48 PM PDT 24
Finished Aug 17 06:06:49 PM PDT 24
Peak memory 207488 kb
Host smart-c9feb83d-e8a2-4cf4-90c0-f98e91d4c8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42668
06733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.4266806733
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.1315922877
Short name T1319
Test name
Test status
Simulation time 2340627721 ps
CPU time 68.01 seconds
Started Aug 17 06:06:52 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 215924 kb
Host smart-626cdc03-fd15-49cb-80b5-64a05a1ee97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13159
22877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.1315922877
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2601498897
Short name T1605
Test name
Test status
Simulation time 2043598510 ps
CPU time 59.18 seconds
Started Aug 17 06:06:47 PM PDT 24
Finished Aug 17 06:07:46 PM PDT 24
Peak memory 223948 kb
Host smart-20b9bf7a-6812-4297-9b29-6a5d792e67b4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2601498897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2601498897
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.2679620782
Short name T899
Test name
Test status
Simulation time 161518936 ps
CPU time 0.94 seconds
Started Aug 17 06:06:47 PM PDT 24
Finished Aug 17 06:06:48 PM PDT 24
Peak memory 207488 kb
Host smart-c8d34406-9ada-4c60-8b92-30e534e48128
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2679620782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.2679620782
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.792592198
Short name T2106
Test name
Test status
Simulation time 184323099 ps
CPU time 0.91 seconds
Started Aug 17 06:06:48 PM PDT 24
Finished Aug 17 06:06:49 PM PDT 24
Peak memory 207372 kb
Host smart-0fecf7ab-2adc-416c-bbf4-18b78995f59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79259
2198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.792592198
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1731917139
Short name T3318
Test name
Test status
Simulation time 219144872 ps
CPU time 1.04 seconds
Started Aug 17 06:06:55 PM PDT 24
Finished Aug 17 06:06:56 PM PDT 24
Peak memory 207460 kb
Host smart-3b8fdabb-81c2-42ff-9ea9-63dfe45f4998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17319
17139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1731917139
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3962732525
Short name T827
Test name
Test status
Simulation time 161483629 ps
CPU time 0.87 seconds
Started Aug 17 06:06:49 PM PDT 24
Finished Aug 17 06:06:50 PM PDT 24
Peak memory 207480 kb
Host smart-13a37c59-58ab-4615-a01f-993cec61a78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39627
32525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3962732525
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3490755161
Short name T3283
Test name
Test status
Simulation time 164645119 ps
CPU time 0.92 seconds
Started Aug 17 06:06:49 PM PDT 24
Finished Aug 17 06:06:50 PM PDT 24
Peak memory 207460 kb
Host smart-9c25980c-975a-4983-bd42-83ef3eaf3f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34907
55161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3490755161
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3099476881
Short name T1466
Test name
Test status
Simulation time 157088912 ps
CPU time 0.93 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 207524 kb
Host smart-4fff896f-ad66-4811-aa31-f1e436ce1d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30994
76881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3099476881
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.4245076905
Short name T1247
Test name
Test status
Simulation time 176809443 ps
CPU time 0.89 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 207564 kb
Host smart-7f843791-061b-46ac-a93b-7c847cdc045d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42450
76905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.4245076905
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2742548591
Short name T41
Test name
Test status
Simulation time 226492845 ps
CPU time 1.13 seconds
Started Aug 17 06:06:47 PM PDT 24
Finished Aug 17 06:06:48 PM PDT 24
Peak memory 207492 kb
Host smart-ccaefced-305a-4f49-8497-d77add01b087
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2742548591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2742548591
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2026928438
Short name T2847
Test name
Test status
Simulation time 172005097 ps
CPU time 0.91 seconds
Started Aug 17 06:06:49 PM PDT 24
Finished Aug 17 06:06:50 PM PDT 24
Peak memory 207436 kb
Host smart-643c8856-5e42-4929-993b-64db826ad6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20269
28438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2026928438
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1126454992
Short name T1668
Test name
Test status
Simulation time 35757185 ps
CPU time 0.71 seconds
Started Aug 17 06:06:55 PM PDT 24
Finished Aug 17 06:06:55 PM PDT 24
Peak memory 207508 kb
Host smart-6184097c-5586-44b6-8047-39f7112a1586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11264
54992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1126454992
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2789810210
Short name T2201
Test name
Test status
Simulation time 7290609830 ps
CPU time 17.25 seconds
Started Aug 17 06:06:47 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 215976 kb
Host smart-1aa8ad11-74dd-417c-8671-a72d466f5c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27898
10210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2789810210
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1863183174
Short name T679
Test name
Test status
Simulation time 200595908 ps
CPU time 1.02 seconds
Started Aug 17 06:06:55 PM PDT 24
Finished Aug 17 06:06:56 PM PDT 24
Peak memory 207544 kb
Host smart-a4d9f0d2-9d96-4a8b-af91-beb9eb07800a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18631
83174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1863183174
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1211797990
Short name T1273
Test name
Test status
Simulation time 270105117 ps
CPU time 1.08 seconds
Started Aug 17 06:06:46 PM PDT 24
Finished Aug 17 06:06:47 PM PDT 24
Peak memory 207416 kb
Host smart-324fc550-7bea-4a75-8674-dea02b2ecc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12117
97990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1211797990
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2421607822
Short name T1798
Test name
Test status
Simulation time 198949373 ps
CPU time 1.04 seconds
Started Aug 17 06:06:48 PM PDT 24
Finished Aug 17 06:06:49 PM PDT 24
Peak memory 207484 kb
Host smart-3a330069-dd09-4e23-94f4-4f362e96d6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
07822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2421607822
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2033676993
Short name T1870
Test name
Test status
Simulation time 181142728 ps
CPU time 0.92 seconds
Started Aug 17 06:06:53 PM PDT 24
Finished Aug 17 06:06:54 PM PDT 24
Peak memory 207384 kb
Host smart-3c5cf480-2305-44b3-8307-66ad5f7a0366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20336
76993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2033676993
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1600089506
Short name T1151
Test name
Test status
Simulation time 146513495 ps
CPU time 0.87 seconds
Started Aug 17 06:06:53 PM PDT 24
Finished Aug 17 06:06:54 PM PDT 24
Peak memory 207384 kb
Host smart-100aa44c-7b68-4cc3-8f0b-c1aa96d008c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16000
89506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1600089506
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_rx_full.3539761323
Short name T1015
Test name
Test status
Simulation time 370218990 ps
CPU time 1.44 seconds
Started Aug 17 06:06:54 PM PDT 24
Finished Aug 17 06:06:56 PM PDT 24
Peak memory 207496 kb
Host smart-b58ebf2e-3d9b-42fb-8cf4-b5b184ee70e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35397
61323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.3539761323
Directory /workspace/21.usbdev_rx_full/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.275180250
Short name T2312
Test name
Test status
Simulation time 149781870 ps
CPU time 0.89 seconds
Started Aug 17 06:06:54 PM PDT 24
Finished Aug 17 06:06:55 PM PDT 24
Peak memory 207448 kb
Host smart-d20a5406-8551-47e6-ba6a-0fb164669ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27518
0250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.275180250
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3347373441
Short name T493
Test name
Test status
Simulation time 142990740 ps
CPU time 0.89 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 207380 kb
Host smart-bd094c5f-4599-4c07-ac1c-91f2de13112d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
73441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3347373441
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1039526403
Short name T2759
Test name
Test status
Simulation time 238357155 ps
CPU time 1.11 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 207372 kb
Host smart-b81cfbdf-eb7c-4760-9ada-e6fb5121a97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10395
26403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1039526403
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1538913251
Short name T1682
Test name
Test status
Simulation time 2303381575 ps
CPU time 18.76 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:24 PM PDT 24
Peak memory 217332 kb
Host smart-ba64080c-f392-4f67-a099-ca35466a970e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1538913251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1538913251
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2214470482
Short name T1038
Test name
Test status
Simulation time 181333329 ps
CPU time 0.95 seconds
Started Aug 17 06:06:54 PM PDT 24
Finished Aug 17 06:06:55 PM PDT 24
Peak memory 207452 kb
Host smart-b0dec1fd-3313-4d9b-a307-e5ccc1b68e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22144
70482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2214470482
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1201839679
Short name T1187
Test name
Test status
Simulation time 181015710 ps
CPU time 0.91 seconds
Started Aug 17 06:06:56 PM PDT 24
Finished Aug 17 06:06:57 PM PDT 24
Peak memory 207564 kb
Host smart-e3b60056-0339-4776-b971-373d3fda58c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12018
39679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1201839679
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3649170906
Short name T2023
Test name
Test status
Simulation time 852090320 ps
CPU time 2.26 seconds
Started Aug 17 06:06:54 PM PDT 24
Finished Aug 17 06:06:56 PM PDT 24
Peak memory 207696 kb
Host smart-d134fd61-b2bc-4a54-8387-dad4b1e43cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36491
70906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3649170906
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2708138844
Short name T696
Test name
Test status
Simulation time 2285834638 ps
CPU time 70.11 seconds
Started Aug 17 06:06:56 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 216000 kb
Host smart-cbcfb582-f247-4f2f-a12c-530b6d6ae90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27081
38844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2708138844
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.570134618
Short name T209
Test name
Test status
Simulation time 604705990 ps
CPU time 4.7 seconds
Started Aug 17 06:06:55 PM PDT 24
Finished Aug 17 06:06:59 PM PDT 24
Peak memory 207672 kb
Host smart-0214dd3a-9b90-47ad-968e-93e1acda9950
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570134618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_host
_handshake.570134618
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_tx_rx_disruption.967602959
Short name T3112
Test name
Test status
Simulation time 510904408 ps
CPU time 1.67 seconds
Started Aug 17 06:06:57 PM PDT 24
Finished Aug 17 06:06:59 PM PDT 24
Peak memory 207564 kb
Host smart-7ec99e7a-1baf-4e48-b083-ed53917bd542
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967602959 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.usbdev_tx_rx_disruption.967602959
Directory /workspace/21.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/210.usbdev_tx_rx_disruption.3541384882
Short name T3220
Test name
Test status
Simulation time 606186807 ps
CPU time 1.67 seconds
Started Aug 17 06:11:53 PM PDT 24
Finished Aug 17 06:11:55 PM PDT 24
Peak memory 207500 kb
Host smart-e897dcf1-56aa-40f0-82de-e37834ea3918
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541384882 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 210.usbdev_tx_rx_disruption.3541384882
Directory /workspace/210.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/211.usbdev_tx_rx_disruption.3557148510
Short name T2671
Test name
Test status
Simulation time 594144201 ps
CPU time 1.61 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207520 kb
Host smart-988dfffe-56ba-4e39-92ad-9f2a2669db37
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557148510 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.usbdev_tx_rx_disruption.3557148510
Directory /workspace/211.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/212.usbdev_tx_rx_disruption.1596227752
Short name T2225
Test name
Test status
Simulation time 615600198 ps
CPU time 1.67 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207520 kb
Host smart-5c7cfb92-667f-4e11-a9fc-7f66a020f2dd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596227752 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.usbdev_tx_rx_disruption.1596227752
Directory /workspace/212.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/213.usbdev_tx_rx_disruption.1897233747
Short name T3395
Test name
Test status
Simulation time 509752549 ps
CPU time 1.67 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207572 kb
Host smart-96b696d1-2581-4477-a8d6-ab1458eeb879
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897233747 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.usbdev_tx_rx_disruption.1897233747
Directory /workspace/213.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/214.usbdev_tx_rx_disruption.3808378640
Short name T2741
Test name
Test status
Simulation time 581801927 ps
CPU time 1.58 seconds
Started Aug 17 06:12:00 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207568 kb
Host smart-8a414b78-4c74-445a-a002-799b0b30ae24
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808378640 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.usbdev_tx_rx_disruption.3808378640
Directory /workspace/214.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/215.usbdev_tx_rx_disruption.3769921885
Short name T982
Test name
Test status
Simulation time 480587512 ps
CPU time 1.56 seconds
Started Aug 17 06:12:05 PM PDT 24
Finished Aug 17 06:12:07 PM PDT 24
Peak memory 207548 kb
Host smart-079a34de-be71-4d95-b1f1-07dc657403bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769921885 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.usbdev_tx_rx_disruption.3769921885
Directory /workspace/215.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/216.usbdev_tx_rx_disruption.305604258
Short name T70
Test name
Test status
Simulation time 466097912 ps
CPU time 1.51 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207540 kb
Host smart-9900ca1b-43a7-4d51-ac41-c5d743d2afcf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305604258 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 216.usbdev_tx_rx_disruption.305604258
Directory /workspace/216.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/217.usbdev_tx_rx_disruption.844387966
Short name T1944
Test name
Test status
Simulation time 449265446 ps
CPU time 1.43 seconds
Started Aug 17 06:12:07 PM PDT 24
Finished Aug 17 06:12:09 PM PDT 24
Peak memory 207540 kb
Host smart-0a9cc44f-5301-49b3-8728-b4b3587daff3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844387966 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 217.usbdev_tx_rx_disruption.844387966
Directory /workspace/217.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/218.usbdev_tx_rx_disruption.2341078238
Short name T1658
Test name
Test status
Simulation time 627020158 ps
CPU time 1.79 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207612 kb
Host smart-51d8e4b1-a3f1-4f2a-82da-c394e2b954eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341078238 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.usbdev_tx_rx_disruption.2341078238
Directory /workspace/218.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/219.usbdev_tx_rx_disruption.2267419868
Short name T1937
Test name
Test status
Simulation time 463758301 ps
CPU time 1.45 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207532 kb
Host smart-7a3052ba-7867-49a7-a3d7-e3f8f13845a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267419868 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.usbdev_tx_rx_disruption.2267419868
Directory /workspace/219.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1754456917
Short name T3587
Test name
Test status
Simulation time 54220746 ps
CPU time 0.69 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207436 kb
Host smart-e2f6662b-90ac-4b7c-890d-f10517ea9aa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1754456917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1754456917
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.68507702
Short name T6
Test name
Test status
Simulation time 5187885277 ps
CPU time 7.68 seconds
Started Aug 17 06:06:53 PM PDT 24
Finished Aug 17 06:07:01 PM PDT 24
Peak memory 215904 kb
Host smart-9326315d-d551-4e9c-8ef6-bb4d39e7c6ae
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68507702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon
_wake_disconnect.68507702
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3349166726
Short name T1619
Test name
Test status
Simulation time 20533240320 ps
CPU time 24.59 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:29 PM PDT 24
Peak memory 207380 kb
Host smart-7e98e985-fbed-4af5-bac3-6af7a8d61cbd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349166726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3349166726
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.320932845
Short name T10
Test name
Test status
Simulation time 31577888870 ps
CPU time 39.21 seconds
Started Aug 17 06:06:54 PM PDT 24
Finished Aug 17 06:07:34 PM PDT 24
Peak memory 207812 kb
Host smart-652b66b0-4058-4b2f-b79d-bafff9f3df88
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320932845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_resume.320932845
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2593838724
Short name T1963
Test name
Test status
Simulation time 167408186 ps
CPU time 0.96 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 207368 kb
Host smart-fcd7ec2b-b185-4e4e-b392-eb082e451434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25938
38724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2593838724
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3560335157
Short name T2124
Test name
Test status
Simulation time 157102133 ps
CPU time 0.91 seconds
Started Aug 17 06:06:55 PM PDT 24
Finished Aug 17 06:06:56 PM PDT 24
Peak memory 207528 kb
Host smart-5baba8ef-5270-48dd-9521-cad09ae1e982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35603
35157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3560335157
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1799988265
Short name T2053
Test name
Test status
Simulation time 382293483 ps
CPU time 1.44 seconds
Started Aug 17 06:06:52 PM PDT 24
Finished Aug 17 06:06:53 PM PDT 24
Peak memory 207528 kb
Host smart-6d945932-bd3a-4657-be75-710b8cb2d7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17999
88265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1799988265
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2724431313
Short name T1433
Test name
Test status
Simulation time 1075130153 ps
CPU time 2.58 seconds
Started Aug 17 06:06:52 PM PDT 24
Finished Aug 17 06:06:55 PM PDT 24
Peak memory 207688 kb
Host smart-92292373-18a7-4e20-85c4-139df2372f6e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2724431313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2724431313
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.293200023
Short name T611
Test name
Test status
Simulation time 3414986982 ps
CPU time 30.41 seconds
Started Aug 17 06:06:55 PM PDT 24
Finished Aug 17 06:07:25 PM PDT 24
Peak memory 207796 kb
Host smart-b624bb2f-2a31-47f8-9bfe-74a1f3810647
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293200023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.293200023
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2854470182
Short name T3549
Test name
Test status
Simulation time 797116442 ps
CPU time 1.95 seconds
Started Aug 17 06:06:55 PM PDT 24
Finished Aug 17 06:06:57 PM PDT 24
Peak memory 207480 kb
Host smart-8a41619b-2832-4168-a5fd-5890b31d6bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28544
70182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2854470182
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.717323563
Short name T2260
Test name
Test status
Simulation time 137264370 ps
CPU time 0.83 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:07:05 PM PDT 24
Peak memory 207504 kb
Host smart-dc301874-6bf7-45dd-aa85-d74f1cc30e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71732
3563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.717323563
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.60462509
Short name T694
Test name
Test status
Simulation time 32930009 ps
CPU time 0.69 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207428 kb
Host smart-4c1da06c-3b08-4d0b-9bb1-52871cc8e6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60462
509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.60462509
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.300732898
Short name T1447
Test name
Test status
Simulation time 996730130 ps
CPU time 2.51 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 207780 kb
Host smart-59e0fa55-65bb-4696-9a48-62a10b73c84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30073
2898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.300732898
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_types.627370593
Short name T1918
Test name
Test status
Simulation time 204110920 ps
CPU time 0.99 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:07:05 PM PDT 24
Peak memory 207452 kb
Host smart-157f141b-cd3d-4bb6-b23c-28009fa3fc75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=627370593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.627370593
Directory /workspace/22.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.759953867
Short name T1733
Test name
Test status
Simulation time 353991106 ps
CPU time 2.63 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 207688 kb
Host smart-13609929-84b2-4acf-95ec-6e1e381c3444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75995
3867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.759953867
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.716661555
Short name T642
Test name
Test status
Simulation time 183398510 ps
CPU time 1 seconds
Started Aug 17 06:07:01 PM PDT 24
Finished Aug 17 06:07:02 PM PDT 24
Peak memory 207460 kb
Host smart-0ab21a0d-e57c-458a-b71b-70a63ad6d200
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=716661555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.716661555
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1274667013
Short name T2400
Test name
Test status
Simulation time 148470553 ps
CPU time 0.92 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 207380 kb
Host smart-ec5ac753-105d-41c5-ad15-9efedc3bb72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12746
67013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1274667013
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3662048417
Short name T608
Test name
Test status
Simulation time 240722345 ps
CPU time 1.1 seconds
Started Aug 17 06:07:02 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207372 kb
Host smart-0e64a56d-dbb1-4780-aaab-e4bfee26a0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36620
48417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3662048417
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1683905676
Short name T3075
Test name
Test status
Simulation time 2897949607 ps
CPU time 78.68 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:08:22 PM PDT 24
Peak memory 218332 kb
Host smart-8d0c2a6c-44ea-42c2-a441-b4a5966857d1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1683905676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1683905676
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.757787259
Short name T1016
Test name
Test status
Simulation time 4551173124 ps
CPU time 28.82 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:34 PM PDT 24
Peak memory 207756 kb
Host smart-74e95eaa-dfdc-40f1-8fd4-896fb1b556ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=757787259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.757787259
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2592704360
Short name T1896
Test name
Test status
Simulation time 191649864 ps
CPU time 0.96 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207572 kb
Host smart-66eb1033-fdef-4120-ac50-51f859bf23d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25927
04360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2592704360
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.483859610
Short name T3602
Test name
Test status
Simulation time 12421935341 ps
CPU time 17.46 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 207676 kb
Host smart-4541c2bb-a854-443e-bdce-c51869023de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48385
9610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.483859610
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3261155477
Short name T2867
Test name
Test status
Simulation time 5167329634 ps
CPU time 7.93 seconds
Started Aug 17 06:07:06 PM PDT 24
Finished Aug 17 06:07:14 PM PDT 24
Peak memory 207756 kb
Host smart-fc4de79d-5f17-4730-81d3-5831ff90fef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
55477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3261155477
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.531860502
Short name T2010
Test name
Test status
Simulation time 4147099933 ps
CPU time 36.34 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:07:41 PM PDT 24
Peak memory 224196 kb
Host smart-c099c123-dcea-456b-905a-3461dd39c74c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=531860502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.531860502
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.2590007587
Short name T2856
Test name
Test status
Simulation time 3063904939 ps
CPU time 86.3 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:08:30 PM PDT 24
Peak memory 217548 kb
Host smart-64f182f7-ca89-48fe-ae33-83bd3cc6ff2c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2590007587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.2590007587
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.826028964
Short name T599
Test name
Test status
Simulation time 291168915 ps
CPU time 1.11 seconds
Started Aug 17 06:07:02 PM PDT 24
Finished Aug 17 06:07:03 PM PDT 24
Peak memory 207396 kb
Host smart-9e32aeaf-e556-4c2f-bc17-2aaab45dea71
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=826028964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.826028964
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.962783821
Short name T1162
Test name
Test status
Simulation time 203118948 ps
CPU time 0.94 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207464 kb
Host smart-2e18a893-6b83-4250-9eef-c35c49e7e706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96278
3821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.962783821
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.642360895
Short name T1427
Test name
Test status
Simulation time 2429610129 ps
CPU time 69.13 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:08:14 PM PDT 24
Peak memory 217472 kb
Host smart-8fb7c167-99e4-400b-8a70-9d314839cbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64236
0895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.642360895
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1904553016
Short name T2470
Test name
Test status
Simulation time 2778931965 ps
CPU time 20.95 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:24 PM PDT 24
Peak memory 215860 kb
Host smart-0769e669-bc70-40e8-b661-a4990133c2b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1904553016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1904553016
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.3211573371
Short name T3228
Test name
Test status
Simulation time 159960845 ps
CPU time 0.95 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 207464 kb
Host smart-dfd6848f-a945-4ec7-a8ad-f68e4584c757
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3211573371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.3211573371
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3992672844
Short name T874
Test name
Test status
Simulation time 146149443 ps
CPU time 0.84 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207484 kb
Host smart-326cc4b8-2c43-40bc-bc1f-a3eb4a3ed696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39926
72844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3992672844
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3520432452
Short name T158
Test name
Test status
Simulation time 240227803 ps
CPU time 1.01 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:07:05 PM PDT 24
Peak memory 207488 kb
Host smart-b61ae312-c189-46f1-84cd-7c674c5e4efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35204
32452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3520432452
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1107935214
Short name T555
Test name
Test status
Simulation time 179680563 ps
CPU time 0.94 seconds
Started Aug 17 06:07:07 PM PDT 24
Finished Aug 17 06:07:08 PM PDT 24
Peak memory 207472 kb
Host smart-6376bea8-ee01-426e-b5ca-0fd85925543f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11079
35214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1107935214
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2102926482
Short name T691
Test name
Test status
Simulation time 162043498 ps
CPU time 0.94 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207464 kb
Host smart-f202b0c6-935d-498c-b910-6ef5112fa7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21029
26482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2102926482
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.4246098092
Short name T3400
Test name
Test status
Simulation time 154566473 ps
CPU time 0.88 seconds
Started Aug 17 06:07:01 PM PDT 24
Finished Aug 17 06:07:02 PM PDT 24
Peak memory 207560 kb
Host smart-1a2b4a7a-428f-40dc-8419-d07b208a1f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42460
98092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.4246098092
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1403266775
Short name T2160
Test name
Test status
Simulation time 161381722 ps
CPU time 0.92 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:07:05 PM PDT 24
Peak memory 207544 kb
Host smart-b1953378-4317-4688-9a9f-c2ff905ecbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14032
66775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1403266775
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2577348443
Short name T2378
Test name
Test status
Simulation time 200072918 ps
CPU time 0.98 seconds
Started Aug 17 06:07:02 PM PDT 24
Finished Aug 17 06:07:03 PM PDT 24
Peak memory 207552 kb
Host smart-05bfb698-c949-4624-a3d8-78c3c11d4f89
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2577348443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2577348443
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3286868670
Short name T2662
Test name
Test status
Simulation time 148450584 ps
CPU time 0.84 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:07:05 PM PDT 24
Peak memory 207424 kb
Host smart-60c43d68-8b85-449a-ad13-893fcb34f1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32868
68670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3286868670
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.718741638
Short name T1548
Test name
Test status
Simulation time 77345554 ps
CPU time 0.74 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207508 kb
Host smart-b0719f35-2a27-40da-9167-3771a59210e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71874
1638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.718741638
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2833274565
Short name T1369
Test name
Test status
Simulation time 226426039 ps
CPU time 0.97 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 207564 kb
Host smart-eddab320-5305-4b9f-862d-0e6fe62a3547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28332
74565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2833274565
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2956329035
Short name T3437
Test name
Test status
Simulation time 159704389 ps
CPU time 0.87 seconds
Started Aug 17 06:07:02 PM PDT 24
Finished Aug 17 06:07:03 PM PDT 24
Peak memory 207540 kb
Host smart-10baf99a-64e9-47be-b66c-be7f23f55e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29563
29035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2956329035
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2683732092
Short name T1117
Test name
Test status
Simulation time 273180825 ps
CPU time 1.02 seconds
Started Aug 17 06:07:06 PM PDT 24
Finished Aug 17 06:07:07 PM PDT 24
Peak memory 207476 kb
Host smart-6935ee42-b9df-4c72-8d61-284d80593ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26837
32092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2683732092
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3746305305
Short name T2848
Test name
Test status
Simulation time 162594418 ps
CPU time 0.89 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207492 kb
Host smart-17cd31c6-b0ee-466a-83e2-551d61bc1fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37463
05305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3746305305
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.228557079
Short name T680
Test name
Test status
Simulation time 147312311 ps
CPU time 0.82 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207436 kb
Host smart-09df346b-0e4b-4208-b659-05654024c9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22855
7079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.228557079
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_rx_full.2967058353
Short name T2499
Test name
Test status
Simulation time 267946894 ps
CPU time 1.2 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207452 kb
Host smart-a636f8f1-2a6c-4317-80ad-b6b26de8abec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29670
58353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.2967058353
Directory /workspace/22.usbdev_rx_full/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2462861214
Short name T3069
Test name
Test status
Simulation time 179656825 ps
CPU time 0.88 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:06 PM PDT 24
Peak memory 207528 kb
Host smart-30213307-6329-4672-a278-61d2ebaaac14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24628
61214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2462861214
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1323337430
Short name T818
Test name
Test status
Simulation time 176740791 ps
CPU time 0.94 seconds
Started Aug 17 06:07:04 PM PDT 24
Finished Aug 17 06:07:05 PM PDT 24
Peak memory 207400 kb
Host smart-fb04dc4e-f2f1-4cc2-8f56-ac86b3b2b0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13233
37430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1323337430
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2570858460
Short name T901
Test name
Test status
Simulation time 180906457 ps
CPU time 1.02 seconds
Started Aug 17 06:07:03 PM PDT 24
Finished Aug 17 06:07:04 PM PDT 24
Peak memory 207440 kb
Host smart-6326f8da-746b-4ee1-967d-45dae9933a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25708
58460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2570858460
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1267977249
Short name T616
Test name
Test status
Simulation time 2164046027 ps
CPU time 62.37 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:08:14 PM PDT 24
Peak memory 217388 kb
Host smart-7a3a087a-788a-48d1-82f8-b6cbc4a53592
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1267977249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1267977249
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2244067856
Short name T1451
Test name
Test status
Simulation time 166912174 ps
CPU time 0.86 seconds
Started Aug 17 06:07:16 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 207488 kb
Host smart-8dcb9d59-5955-4ff4-aa00-fdba1eacc60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22440
67856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2244067856
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2153426252
Short name T3388
Test name
Test status
Simulation time 228292063 ps
CPU time 0.98 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:16 PM PDT 24
Peak memory 207560 kb
Host smart-af91c212-f107-49f1-bf68-7ec1f901eeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21534
26252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2153426252
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.495039066
Short name T1078
Test name
Test status
Simulation time 398260096 ps
CPU time 1.31 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:15 PM PDT 24
Peak memory 207460 kb
Host smart-d5a4cccf-472d-4ad4-a2de-3573b9f9dbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49503
9066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.495039066
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3175871683
Short name T1408
Test name
Test status
Simulation time 1657889386 ps
CPU time 16.03 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:07:28 PM PDT 24
Peak memory 217332 kb
Host smart-daa5f03f-83a1-4bbd-9815-36338240822c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31758
71683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3175871683
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.2382689483
Short name T1590
Test name
Test status
Simulation time 750867029 ps
CPU time 15.64 seconds
Started Aug 17 06:07:05 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207372 kb
Host smart-d77b8315-6787-44c2-8e2b-a1071f104236
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382689483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.2382689483
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_tx_rx_disruption.2781590735
Short name T936
Test name
Test status
Simulation time 560725372 ps
CPU time 1.85 seconds
Started Aug 17 06:07:16 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 207552 kb
Host smart-68ca3956-342a-46ef-9e4a-f0408e867451
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781590735 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.usbdev_tx_rx_disruption.2781590735
Directory /workspace/22.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/220.usbdev_tx_rx_disruption.3214887254
Short name T2046
Test name
Test status
Simulation time 522918173 ps
CPU time 1.63 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207568 kb
Host smart-4df7b904-906a-4023-b18e-028a6a5033f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214887254 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.usbdev_tx_rx_disruption.3214887254
Directory /workspace/220.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/221.usbdev_tx_rx_disruption.960464429
Short name T2579
Test name
Test status
Simulation time 481412099 ps
CPU time 1.64 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207560 kb
Host smart-a7861590-5f43-422b-96ef-dc29c3f1c711
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960464429 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 221.usbdev_tx_rx_disruption.960464429
Directory /workspace/221.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/222.usbdev_tx_rx_disruption.575572865
Short name T121
Test name
Test status
Simulation time 474704082 ps
CPU time 1.5 seconds
Started Aug 17 06:11:53 PM PDT 24
Finished Aug 17 06:11:55 PM PDT 24
Peak memory 207540 kb
Host smart-8eab02de-c248-4985-a681-bb1c33a0b69d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575572865 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 222.usbdev_tx_rx_disruption.575572865
Directory /workspace/222.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/223.usbdev_tx_rx_disruption.287680450
Short name T2938
Test name
Test status
Simulation time 487839836 ps
CPU time 1.48 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207552 kb
Host smart-9691f4df-6a92-47b2-a24c-124202577749
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287680450 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 223.usbdev_tx_rx_disruption.287680450
Directory /workspace/223.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/225.usbdev_tx_rx_disruption.1397269484
Short name T588
Test name
Test status
Simulation time 396156433 ps
CPU time 1.35 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207568 kb
Host smart-1eff54e0-dc1b-4e1b-8704-6cef913e503c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397269484 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.usbdev_tx_rx_disruption.1397269484
Directory /workspace/225.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/226.usbdev_tx_rx_disruption.4257070185
Short name T752
Test name
Test status
Simulation time 538951038 ps
CPU time 1.59 seconds
Started Aug 17 06:12:21 PM PDT 24
Finished Aug 17 06:12:23 PM PDT 24
Peak memory 207508 kb
Host smart-9d323874-ae6c-4f23-b3fb-84ea53b1b191
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257070185 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.usbdev_tx_rx_disruption.4257070185
Directory /workspace/226.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/227.usbdev_tx_rx_disruption.314312157
Short name T3128
Test name
Test status
Simulation time 525422741 ps
CPU time 1.64 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207536 kb
Host smart-5fb4f3be-4e75-4f8f-8a4a-6a426c082766
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314312157 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 227.usbdev_tx_rx_disruption.314312157
Directory /workspace/227.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/228.usbdev_tx_rx_disruption.2756800282
Short name T1520
Test name
Test status
Simulation time 606894269 ps
CPU time 1.6 seconds
Started Aug 17 06:11:54 PM PDT 24
Finished Aug 17 06:11:56 PM PDT 24
Peak memory 207528 kb
Host smart-f8ae8283-e6ac-44fc-bc01-98262a92d71b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756800282 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.usbdev_tx_rx_disruption.2756800282
Directory /workspace/228.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/229.usbdev_tx_rx_disruption.4028523880
Short name T2342
Test name
Test status
Simulation time 567318214 ps
CPU time 1.49 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207512 kb
Host smart-c5206397-22a0-44a8-a205-8537bb4ba776
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028523880 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.usbdev_tx_rx_disruption.4028523880
Directory /workspace/229.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.492821603
Short name T2273
Test name
Test status
Simulation time 30611960 ps
CPU time 0.67 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:14 PM PDT 24
Peak memory 207460 kb
Host smart-52f75645-2f22-4c10-8220-0612fb6a8147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=492821603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.492821603
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.920224159
Short name T2803
Test name
Test status
Simulation time 4814843848 ps
CPU time 6.32 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 215968 kb
Host smart-e9fa7c38-c663-4c30-97ec-01a05f2aefd0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920224159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_ao
n_wake_disconnect.920224159
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3243590165
Short name T11
Test name
Test status
Simulation time 18835001416 ps
CPU time 22.54 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:07:35 PM PDT 24
Peak memory 207784 kb
Host smart-d51c8e4d-9dd3-4701-9c14-9254a48efc34
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243590165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3243590165
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.2217942040
Short name T2900
Test name
Test status
Simulation time 23608315267 ps
CPU time 28.47 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:39 PM PDT 24
Peak memory 215972 kb
Host smart-585a620a-ccb9-436b-a6e7-66a912e2e1cf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217942040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.2217942040
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.801580101
Short name T2735
Test name
Test status
Simulation time 205920114 ps
CPU time 0.96 seconds
Started Aug 17 06:07:16 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 207452 kb
Host smart-bc13442e-de4c-48bc-947c-2ae230a469c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80158
0101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.801580101
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.573995920
Short name T3027
Test name
Test status
Simulation time 177079166 ps
CPU time 0.86 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207524 kb
Host smart-63177ab6-c59e-4427-819b-10be4722c690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57399
5920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.573995920
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.3803279041
Short name T3071
Test name
Test status
Simulation time 545710855 ps
CPU time 1.88 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 207540 kb
Host smart-cfd9c2b8-9134-455a-bbc0-eb2ce2d5ca95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38032
79041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.3803279041
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2187538750
Short name T1860
Test name
Test status
Simulation time 925830189 ps
CPU time 2.6 seconds
Started Aug 17 06:07:17 PM PDT 24
Finished Aug 17 06:07:19 PM PDT 24
Peak memory 207644 kb
Host smart-1db8353b-0f5b-43bf-9056-111574992f59
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2187538750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2187538750
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2217489301
Short name T3161
Test name
Test status
Simulation time 36217373776 ps
CPU time 66.72 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 207780 kb
Host smart-b5b68a5e-197c-4d4a-84c9-e3fa2136f33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22174
89301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2217489301
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.3636568911
Short name T919
Test name
Test status
Simulation time 1170960375 ps
CPU time 26.6 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:07:37 PM PDT 24
Peak memory 207720 kb
Host smart-925a840b-ca6a-4337-a708-53dffb94432b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636568911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.3636568911
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.1698993861
Short name T2382
Test name
Test status
Simulation time 605346896 ps
CPU time 1.69 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:15 PM PDT 24
Peak memory 207528 kb
Host smart-0daf94a8-6dc5-433a-8e08-244a02ffa97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16989
93861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.1698993861
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.3215266949
Short name T3074
Test name
Test status
Simulation time 132677610 ps
CPU time 0.83 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207508 kb
Host smart-f30718e3-e4c4-40a5-93d7-ab5c269f0298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32152
66949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3215266949
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.599044672
Short name T2187
Test name
Test status
Simulation time 43817039 ps
CPU time 0.7 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207392 kb
Host smart-ff502a93-0e88-447a-bb9b-b03b80018186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59904
4672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.599044672
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.4171082359
Short name T2242
Test name
Test status
Simulation time 713700917 ps
CPU time 2.02 seconds
Started Aug 17 06:07:16 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 207772 kb
Host smart-c5981718-ea7b-44c6-8b2d-65909a6d3762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41710
82359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.4171082359
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_types.386536486
Short name T1880
Test name
Test status
Simulation time 395263325 ps
CPU time 1.43 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:16 PM PDT 24
Peak memory 207524 kb
Host smart-286991cb-930e-4df5-98b1-cbf3069f178e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=386536486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.386536486
Directory /workspace/23.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3814254100
Short name T724
Test name
Test status
Simulation time 198053989 ps
CPU time 2.35 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207596 kb
Host smart-aae4f1d6-63b0-4ab4-b2f8-c948b6ccb1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38142
54100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3814254100
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.956796610
Short name T3522
Test name
Test status
Simulation time 202567064 ps
CPU time 1.04 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:07:11 PM PDT 24
Peak memory 215856 kb
Host smart-7685ebf9-d044-479b-844f-157bd2458fee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=956796610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.956796610
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2237999286
Short name T3349
Test name
Test status
Simulation time 158390481 ps
CPU time 0.86 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207456 kb
Host smart-393e533d-ee0f-487c-a58c-8a9a15658078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22379
99286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2237999286
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1751243635
Short name T1439
Test name
Test status
Simulation time 163400616 ps
CPU time 0.89 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:07:13 PM PDT 24
Peak memory 207540 kb
Host smart-4a11299f-28b4-43a1-ad8d-f3169b313981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17512
43635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1751243635
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.1539621470
Short name T2559
Test name
Test status
Simulation time 3807010607 ps
CPU time 106.82 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 224136 kb
Host smart-438db864-2964-487f-bc5c-1c459f0d2e55
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1539621470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.1539621470
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.848334425
Short name T753
Test name
Test status
Simulation time 12355088075 ps
CPU time 90.01 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:08:43 PM PDT 24
Peak memory 207784 kb
Host smart-d6c0b970-c7b8-40a7-880b-09aa9f044c39
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=848334425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.848334425
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1504140938
Short name T3637
Test name
Test status
Simulation time 231455521 ps
CPU time 0.98 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207476 kb
Host smart-fa35af46-bfb4-40a8-808a-5de350cbe76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15041
40938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1504140938
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.3603495609
Short name T3548
Test name
Test status
Simulation time 9409933138 ps
CPU time 13.11 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:33 PM PDT 24
Peak memory 215980 kb
Host smart-608f012c-07b8-4cb9-b3ce-192cfa35d752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36034
95609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3603495609
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.48597408
Short name T2414
Test name
Test status
Simulation time 9672621000 ps
CPU time 13.5 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:25 PM PDT 24
Peak memory 207648 kb
Host smart-2a980698-e8e4-4ad3-8b97-fb07633b42ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48597
408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.48597408
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1924750014
Short name T997
Test name
Test status
Simulation time 2552461287 ps
CPU time 25.97 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:07:38 PM PDT 24
Peak memory 218568 kb
Host smart-8d741b4f-ed1c-4839-820a-ebbc3b2f7837
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1924750014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1924750014
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2089509329
Short name T1615
Test name
Test status
Simulation time 2270131478 ps
CPU time 23 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:34 PM PDT 24
Peak memory 224088 kb
Host smart-260a0cd3-8506-4650-a6b5-b739140f6ef4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2089509329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2089509329
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.4047190261
Short name T3201
Test name
Test status
Simulation time 255172477 ps
CPU time 1.05 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207412 kb
Host smart-285f523a-528f-4502-a489-6d7fb128ae34
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4047190261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.4047190261
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3881149934
Short name T1799
Test name
Test status
Simulation time 231143118 ps
CPU time 1.03 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:15 PM PDT 24
Peak memory 207452 kb
Host smart-f20abb46-0071-416d-b048-d2d07a9f363b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38811
49934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3881149934
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.1287069100
Short name T1570
Test name
Test status
Simulation time 2125371292 ps
CPU time 22.6 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:35 PM PDT 24
Peak memory 215916 kb
Host smart-17d1ee2e-af00-402c-a68c-7c41093af022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12870
69100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.1287069100
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2937867102
Short name T1134
Test name
Test status
Simulation time 4132535744 ps
CPU time 30.98 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:07:42 PM PDT 24
Peak memory 217576 kb
Host smart-d228a4ee-d42c-41f1-ac26-1f04591d693e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2937867102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2937867102
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1978344204
Short name T3029
Test name
Test status
Simulation time 156531754 ps
CPU time 0.91 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:16 PM PDT 24
Peak memory 207452 kb
Host smart-a9437787-e603-4ba4-92d4-5563eff37799
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1978344204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1978344204
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.4220132238
Short name T2544
Test name
Test status
Simulation time 143585383 ps
CPU time 0.88 seconds
Started Aug 17 06:07:14 PM PDT 24
Finished Aug 17 06:07:15 PM PDT 24
Peak memory 207456 kb
Host smart-1d841b09-0c45-4e13-82ed-24c16e4e3895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42201
32238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.4220132238
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2239012685
Short name T2998
Test name
Test status
Simulation time 192795614 ps
CPU time 0.99 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 206820 kb
Host smart-22361908-dda1-4302-b869-7db105002332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22390
12685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2239012685
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.686322792
Short name T3038
Test name
Test status
Simulation time 185291006 ps
CPU time 0.91 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:16 PM PDT 24
Peak memory 207456 kb
Host smart-5e8e2ff2-1b76-42da-a7ac-cece0beba862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68632
2792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.686322792
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.4158208360
Short name T1911
Test name
Test status
Simulation time 162758797 ps
CPU time 0.89 seconds
Started Aug 17 06:07:18 PM PDT 24
Finished Aug 17 06:07:19 PM PDT 24
Peak memory 207448 kb
Host smart-88fc8bfc-6051-4be9-b4cb-286441068a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41582
08360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.4158208360
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2728371
Short name T1613
Test name
Test status
Simulation time 155767541 ps
CPU time 0.89 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207392 kb
Host smart-3d356b64-dca0-40e0-81d4-bc92560e6fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27283
71 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2728371
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3738527740
Short name T813
Test name
Test status
Simulation time 148713786 ps
CPU time 0.83 seconds
Started Aug 17 06:07:17 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 207488 kb
Host smart-b1b8394b-b76b-43b8-be04-fd34bcfe87b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37385
27740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3738527740
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3799263491
Short name T810
Test name
Test status
Simulation time 236554556 ps
CPU time 1.1 seconds
Started Aug 17 06:07:14 PM PDT 24
Finished Aug 17 06:07:15 PM PDT 24
Peak memory 207564 kb
Host smart-a93ded05-145a-4066-85ff-a2a42173ba9b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3799263491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3799263491
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1260423843
Short name T2216
Test name
Test status
Simulation time 147494098 ps
CPU time 0.84 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:07:11 PM PDT 24
Peak memory 207380 kb
Host smart-09952bfa-d4f4-43c6-a8d2-b42629556f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12604
23843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1260423843
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1338545105
Short name T2601
Test name
Test status
Simulation time 96191764 ps
CPU time 0.75 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:14 PM PDT 24
Peak memory 207496 kb
Host smart-46dbe009-18e5-4c16-96d0-ae44246047ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13385
45105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1338545105
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.209379864
Short name T1091
Test name
Test status
Simulation time 15440357527 ps
CPU time 45.02 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 220300 kb
Host smart-1cff369b-b86e-49d0-84b5-10ccd6472d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
9864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.209379864
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.164096317
Short name T2466
Test name
Test status
Simulation time 186879818 ps
CPU time 0.93 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207548 kb
Host smart-8766ae45-27d2-411c-8d45-fc4546bbd13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16409
6317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.164096317
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1059026826
Short name T2554
Test name
Test status
Simulation time 237632908 ps
CPU time 1.02 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:12 PM PDT 24
Peak memory 207452 kb
Host smart-4478a5b1-2169-4c8a-ae3a-838d46b838ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10590
26826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1059026826
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.4102732505
Short name T1018
Test name
Test status
Simulation time 234817908 ps
CPU time 1.03 seconds
Started Aug 17 06:07:16 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 207460 kb
Host smart-75db4394-8e2f-4b37-aae1-5f5075c59cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41027
32505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.4102732505
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2045138596
Short name T970
Test name
Test status
Simulation time 189114450 ps
CPU time 1.03 seconds
Started Aug 17 06:07:16 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 207464 kb
Host smart-9aac6ee3-c4ca-4d0e-a400-1b75c915d4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20451
38596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2045138596
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1420753804
Short name T1727
Test name
Test status
Simulation time 152875124 ps
CPU time 0.87 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:07:13 PM PDT 24
Peak memory 207420 kb
Host smart-84a137a4-812a-4024-b911-8519fb50c6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14207
53804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1420753804
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_rx_full.3408741456
Short name T3513
Test name
Test status
Simulation time 318148221 ps
CPU time 1.27 seconds
Started Aug 17 06:07:11 PM PDT 24
Finished Aug 17 06:07:13 PM PDT 24
Peak memory 207536 kb
Host smart-c5011b46-b62f-4c97-adc5-5836fecf54c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
41456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.3408741456
Directory /workspace/23.usbdev_rx_full/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2787080923
Short name T2615
Test name
Test status
Simulation time 143484934 ps
CPU time 0.9 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:07:13 PM PDT 24
Peak memory 207536 kb
Host smart-4ac0e947-6e5d-4964-b11c-3961605aff6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27870
80923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2787080923
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1738943308
Short name T1571
Test name
Test status
Simulation time 149785204 ps
CPU time 0.81 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:16 PM PDT 24
Peak memory 207472 kb
Host smart-abe49c09-be0a-4732-8e4d-e1d4c486960a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17389
43308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1738943308
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2727975044
Short name T3536
Test name
Test status
Simulation time 235497375 ps
CPU time 1.07 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:07:13 PM PDT 24
Peak memory 207476 kb
Host smart-84619815-d7a5-4f28-b865-ffc86a1b807f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27279
75044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2727975044
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1458913517
Short name T2669
Test name
Test status
Simulation time 1926125758 ps
CPU time 56.18 seconds
Started Aug 17 06:07:17 PM PDT 24
Finished Aug 17 06:08:13 PM PDT 24
Peak memory 217300 kb
Host smart-a4b1c5ee-47b7-4500-ba37-e6790af57d86
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1458913517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1458913517
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.4065650457
Short name T945
Test name
Test status
Simulation time 194357158 ps
CPU time 0.9 seconds
Started Aug 17 06:07:12 PM PDT 24
Finished Aug 17 06:07:13 PM PDT 24
Peak memory 207496 kb
Host smart-0ce312a8-ccc8-441f-bf6d-f120c519cdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40656
50457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.4065650457
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.4006036852
Short name T1041
Test name
Test status
Simulation time 159430330 ps
CPU time 0.89 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:14 PM PDT 24
Peak memory 207424 kb
Host smart-57fd0445-f262-45f1-b3ae-4732c84af2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40060
36852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.4006036852
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2863572176
Short name T312
Test name
Test status
Simulation time 676328652 ps
CPU time 1.77 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 207516 kb
Host smart-365c592e-5792-443a-81a9-c8ce5e2a0500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28635
72176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2863572176
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2404419644
Short name T543
Test name
Test status
Simulation time 2983588247 ps
CPU time 23.95 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:37 PM PDT 24
Peak memory 215848 kb
Host smart-6f1c8be3-d1c9-4506-9693-bae257bcbac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24044
19644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2404419644
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.762164129
Short name T1062
Test name
Test status
Simulation time 2937757249 ps
CPU time 19.04 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 207668 kb
Host smart-2b91baac-d366-4e27-b1f9-d170e9bdfd37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762164129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_host
_handshake.762164129
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_tx_rx_disruption.239552440
Short name T1683
Test name
Test status
Simulation time 528134106 ps
CPU time 1.59 seconds
Started Aug 17 06:07:16 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 207548 kb
Host smart-bbda5f21-c095-4e35-bfde-77ab90268218
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239552440 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.usbdev_tx_rx_disruption.239552440
Directory /workspace/23.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/230.usbdev_tx_rx_disruption.916291720
Short name T1593
Test name
Test status
Simulation time 539753328 ps
CPU time 1.5 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207484 kb
Host smart-7ff99f96-3ca8-4ad4-ac69-a2b7ac11424e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916291720 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 230.usbdev_tx_rx_disruption.916291720
Directory /workspace/230.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/231.usbdev_tx_rx_disruption.1916395085
Short name T171
Test name
Test status
Simulation time 600492280 ps
CPU time 1.75 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207568 kb
Host smart-d56d5ee7-4ba3-4c90-8957-33dbfd02947d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916395085 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.usbdev_tx_rx_disruption.1916395085
Directory /workspace/231.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/232.usbdev_tx_rx_disruption.2242848349
Short name T971
Test name
Test status
Simulation time 478374203 ps
CPU time 1.43 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207544 kb
Host smart-48ca0bc6-b675-485e-9080-e5c2b6141463
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242848349 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.usbdev_tx_rx_disruption.2242848349
Directory /workspace/232.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/233.usbdev_tx_rx_disruption.2169927772
Short name T1234
Test name
Test status
Simulation time 429659350 ps
CPU time 1.47 seconds
Started Aug 17 06:11:55 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207596 kb
Host smart-575f049c-0840-48a9-870d-0279db0cdecf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169927772 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.usbdev_tx_rx_disruption.2169927772
Directory /workspace/233.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/234.usbdev_tx_rx_disruption.131079053
Short name T1066
Test name
Test status
Simulation time 549839004 ps
CPU time 1.73 seconds
Started Aug 17 06:12:10 PM PDT 24
Finished Aug 17 06:12:12 PM PDT 24
Peak memory 207508 kb
Host smart-350bc447-7588-4a74-b9b4-4c1c9aceb700
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131079053 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 234.usbdev_tx_rx_disruption.131079053
Directory /workspace/234.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/235.usbdev_tx_rx_disruption.979062769
Short name T1310
Test name
Test status
Simulation time 464599978 ps
CPU time 1.42 seconds
Started Aug 17 06:11:55 PM PDT 24
Finished Aug 17 06:11:56 PM PDT 24
Peak memory 207560 kb
Host smart-17270b57-e01b-44de-b82d-d23a42d62b79
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979062769 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 235.usbdev_tx_rx_disruption.979062769
Directory /workspace/235.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/236.usbdev_tx_rx_disruption.2003265221
Short name T188
Test name
Test status
Simulation time 503222704 ps
CPU time 1.59 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207536 kb
Host smart-3f1cabe4-2137-49cd-a861-09f9de45fb3e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003265221 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.usbdev_tx_rx_disruption.2003265221
Directory /workspace/236.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/237.usbdev_tx_rx_disruption.829508542
Short name T2287
Test name
Test status
Simulation time 636782980 ps
CPU time 1.74 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207576 kb
Host smart-cd592de0-a3fe-4f33-ad48-541127c0cf61
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829508542 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 237.usbdev_tx_rx_disruption.829508542
Directory /workspace/237.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/238.usbdev_tx_rx_disruption.3834332323
Short name T1055
Test name
Test status
Simulation time 508599778 ps
CPU time 1.57 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207540 kb
Host smart-e7beba4e-4f97-40a8-880d-a3aea8b8c410
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834332323 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.usbdev_tx_rx_disruption.3834332323
Directory /workspace/238.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/239.usbdev_tx_rx_disruption.586477188
Short name T3347
Test name
Test status
Simulation time 582453933 ps
CPU time 1.65 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207568 kb
Host smart-0cdcce11-18e1-4edf-9652-ec9c4aac5f05
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586477188 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 239.usbdev_tx_rx_disruption.586477188
Directory /workspace/239.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.298967128
Short name T3312
Test name
Test status
Simulation time 57095632 ps
CPU time 0.73 seconds
Started Aug 17 06:07:22 PM PDT 24
Finished Aug 17 06:07:23 PM PDT 24
Peak memory 207404 kb
Host smart-9275013f-1ce0-445f-b27b-fa722e0b6120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=298967128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.298967128
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.223524707
Short name T3155
Test name
Test status
Simulation time 11407793703 ps
CPU time 14.47 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:30 PM PDT 24
Peak memory 207764 kb
Host smart-081e2183-bf02-4f79-b2e3-42620aed6844
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223524707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_disconnect.223524707
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3204356809
Short name T2366
Test name
Test status
Simulation time 14459191292 ps
CPU time 20.48 seconds
Started Aug 17 06:07:10 PM PDT 24
Finished Aug 17 06:07:31 PM PDT 24
Peak memory 215984 kb
Host smart-da0e5766-ea0b-49fc-8852-0d210574e654
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204356809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3204356809
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1016112907
Short name T2337
Test name
Test status
Simulation time 25611598311 ps
CPU time 33.17 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:48 PM PDT 24
Peak memory 215988 kb
Host smart-64555ccb-35d0-42d7-8149-19e602eb8ad2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016112907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.1016112907
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3409905
Short name T629
Test name
Test status
Simulation time 183051353 ps
CPU time 1.02 seconds
Started Aug 17 06:07:14 PM PDT 24
Finished Aug 17 06:07:15 PM PDT 24
Peak memory 207488 kb
Host smart-d8d18232-3b5c-4fc0-a3ce-6bb443c38bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34099
05 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3409905
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1749494489
Short name T3205
Test name
Test status
Simulation time 150567363 ps
CPU time 0.86 seconds
Started Aug 17 06:07:16 PM PDT 24
Finished Aug 17 06:07:17 PM PDT 24
Peak memory 207540 kb
Host smart-4eb3c060-f167-4c9b-be39-1e7878de6251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17494
94489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1749494489
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2411343635
Short name T3506
Test name
Test status
Simulation time 306411203 ps
CPU time 1.36 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:07:16 PM PDT 24
Peak memory 207544 kb
Host smart-b923df7d-facb-40b3-9455-8113aa78bc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24113
43635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2411343635
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2082383771
Short name T336
Test name
Test status
Simulation time 791762181 ps
CPU time 2.11 seconds
Started Aug 17 06:07:17 PM PDT 24
Finished Aug 17 06:07:19 PM PDT 24
Peak memory 207432 kb
Host smart-b3aa60d1-97a7-4864-8a1c-a2af1337cfbd
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2082383771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2082383771
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.882550285
Short name T182
Test name
Test status
Simulation time 41059295389 ps
CPU time 67.67 seconds
Started Aug 17 06:07:15 PM PDT 24
Finished Aug 17 06:08:23 PM PDT 24
Peak memory 207776 kb
Host smart-93743f47-17c4-484a-b68d-1e3d18306053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88255
0285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.882550285
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.270846605
Short name T2036
Test name
Test status
Simulation time 5668531860 ps
CPU time 38.1 seconds
Started Aug 17 06:07:17 PM PDT 24
Finished Aug 17 06:07:55 PM PDT 24
Peak memory 207732 kb
Host smart-59b8f0b5-2f2c-44a1-a214-d3977005dc9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270846605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.270846605
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.4115314241
Short name T1346
Test name
Test status
Simulation time 890199716 ps
CPU time 1.95 seconds
Started Aug 17 06:07:18 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207476 kb
Host smart-95d31cd5-78a2-4f89-abd6-756182389776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41153
14241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.4115314241
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2580097085
Short name T1123
Test name
Test status
Simulation time 136551710 ps
CPU time 0.9 seconds
Started Aug 17 06:07:14 PM PDT 24
Finished Aug 17 06:07:15 PM PDT 24
Peak memory 207536 kb
Host smart-4e41ba48-e1e8-4eca-99f1-cca6280bb962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25800
97085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2580097085
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.529457899
Short name T2830
Test name
Test status
Simulation time 75216601 ps
CPU time 0.73 seconds
Started Aug 17 06:07:17 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 207392 kb
Host smart-0f3a8f4c-52e8-4b44-adbf-14cff51d7789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52945
7899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.529457899
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.485822293
Short name T2428
Test name
Test status
Simulation time 962155483 ps
CPU time 2.6 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 207696 kb
Host smart-f6c6617a-399c-4fea-ace4-ac660982e434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48582
2293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.485822293
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_types.3421363259
Short name T447
Test name
Test status
Simulation time 338322657 ps
CPU time 1.15 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207516 kb
Host smart-10bf6ae4-c467-4916-9ff4-ab3c7d995d12
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3421363259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.3421363259
Directory /workspace/24.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1013366300
Short name T1815
Test name
Test status
Simulation time 273856815 ps
CPU time 2.29 seconds
Started Aug 17 06:07:23 PM PDT 24
Finished Aug 17 06:07:26 PM PDT 24
Peak memory 207560 kb
Host smart-4211e9e5-9e63-41b5-9251-8ca156c37a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10133
66300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1013366300
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.101554539
Short name T1968
Test name
Test status
Simulation time 210745573 ps
CPU time 1.15 seconds
Started Aug 17 06:07:23 PM PDT 24
Finished Aug 17 06:07:24 PM PDT 24
Peak memory 215888 kb
Host smart-c6cb9ae4-b43b-4867-bab7-17bea2d480a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=101554539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.101554539
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2788770736
Short name T2943
Test name
Test status
Simulation time 155384850 ps
CPU time 0.82 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207652 kb
Host smart-e00b0f31-f27f-4fb8-8d3c-0fb09f87d24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27887
70736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2788770736
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2156800026
Short name T2828
Test name
Test status
Simulation time 229413078 ps
CPU time 1.02 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207684 kb
Host smart-b9f579e4-f130-468b-ad69-94b2b6a0ff0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21568
00026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2156800026
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1665821006
Short name T3276
Test name
Test status
Simulation time 4403803397 ps
CPU time 138.97 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 224036 kb
Host smart-e462eb5a-b6f5-482b-ae36-0c9ab3cb1fc3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1665821006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1665821006
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.4122004799
Short name T3184
Test name
Test status
Simulation time 6561360214 ps
CPU time 71.71 seconds
Started Aug 17 06:07:25 PM PDT 24
Finished Aug 17 06:08:37 PM PDT 24
Peak memory 207712 kb
Host smart-cbb47711-7cb5-423c-839d-6e77414e133a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4122004799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.4122004799
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.811175878
Short name T3431
Test name
Test status
Simulation time 160666591 ps
CPU time 0.88 seconds
Started Aug 17 06:07:18 PM PDT 24
Finished Aug 17 06:07:19 PM PDT 24
Peak memory 207476 kb
Host smart-ab266c5e-d33c-4fbc-a0ad-9508998e8005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81117
5878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.811175878
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1847370563
Short name T3245
Test name
Test status
Simulation time 32317729260 ps
CPU time 53.19 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:08:12 PM PDT 24
Peak memory 207772 kb
Host smart-8ebdde17-e5d5-4c39-9566-81a0dc84291a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18473
70563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1847370563
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1205156625
Short name T1835
Test name
Test status
Simulation time 9372782162 ps
CPU time 12.6 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 207852 kb
Host smart-65c726f1-0b0e-42f4-b774-2b2181674e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12051
56625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1205156625
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.188316572
Short name T2546
Test name
Test status
Simulation time 4398826202 ps
CPU time 35.3 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 219224 kb
Host smart-352f1f7f-2f21-4821-b8ec-ddf515c40c59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=188316572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.188316572
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.3205288561
Short name T1871
Test name
Test status
Simulation time 2704105100 ps
CPU time 76.36 seconds
Started Aug 17 06:07:22 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 217320 kb
Host smart-5641ce6e-5c54-4338-8327-f3818380cdbd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3205288561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.3205288561
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.2332993170
Short name T2117
Test name
Test status
Simulation time 236145032 ps
CPU time 1.01 seconds
Started Aug 17 06:07:24 PM PDT 24
Finished Aug 17 06:07:25 PM PDT 24
Peak memory 207448 kb
Host smart-df5bdff5-1d0c-4f8c-b899-401e4f1286ee
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2332993170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.2332993170
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1464618276
Short name T2727
Test name
Test status
Simulation time 197751320 ps
CPU time 1 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207468 kb
Host smart-686d6ba0-494b-49e6-aa61-5ff46313338e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14646
18276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1464618276
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.382734958
Short name T2522
Test name
Test status
Simulation time 2828872726 ps
CPU time 21.75 seconds
Started Aug 17 06:07:26 PM PDT 24
Finished Aug 17 06:07:48 PM PDT 24
Peak memory 217896 kb
Host smart-4e5667e7-30d1-4b50-b93a-140bb1f90350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38273
4958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.382734958
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.119766939
Short name T2822
Test name
Test status
Simulation time 3350599539 ps
CPU time 26.3 seconds
Started Aug 17 06:07:22 PM PDT 24
Finished Aug 17 06:07:48 PM PDT 24
Peak memory 216012 kb
Host smart-9c44e914-68f9-4397-8260-626d74cbd7cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=119766939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.119766939
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.1383897076
Short name T609
Test name
Test status
Simulation time 158955389 ps
CPU time 0.89 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207484 kb
Host smart-8f57922c-d78c-47b3-9032-96b85ca9edc3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1383897076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.1383897076
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3776114703
Short name T1379
Test name
Test status
Simulation time 227267998 ps
CPU time 0.93 seconds
Started Aug 17 06:07:26 PM PDT 24
Finished Aug 17 06:07:27 PM PDT 24
Peak memory 207388 kb
Host smart-b865f887-403f-4a46-92a3-a102e75444f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37761
14703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3776114703
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.280800335
Short name T1155
Test name
Test status
Simulation time 203861774 ps
CPU time 0.93 seconds
Started Aug 17 06:07:26 PM PDT 24
Finished Aug 17 06:07:27 PM PDT 24
Peak memory 207420 kb
Host smart-7d1fd509-e797-4bdd-beb8-d1a17fe08574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28080
0335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.280800335
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2320250856
Short name T1387
Test name
Test status
Simulation time 187135334 ps
CPU time 0.96 seconds
Started Aug 17 06:07:17 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 207476 kb
Host smart-6e8b7c9e-09ac-475b-ae09-610253a5bd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
50856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2320250856
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.541093249
Short name T1058
Test name
Test status
Simulation time 178486203 ps
CPU time 0.91 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207504 kb
Host smart-70155093-7524-440d-98f7-522551cdbde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54109
3249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.541093249
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.514616224
Short name T1671
Test name
Test status
Simulation time 166116897 ps
CPU time 0.88 seconds
Started Aug 17 06:07:21 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 207532 kb
Host smart-ac1df522-9549-4c2b-a8ed-c67406d70677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51461
6224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.514616224
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.192630800
Short name T1747
Test name
Test status
Simulation time 204939500 ps
CPU time 0.97 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207580 kb
Host smart-f44bd1e3-e24f-4666-9ba8-a839d360c25e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=192630800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.192630800
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.459645957
Short name T1718
Test name
Test status
Simulation time 157566104 ps
CPU time 0.87 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207428 kb
Host smart-0a8b2f0b-c59e-40aa-8889-8357ec5c50fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45964
5957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.459645957
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3365746159
Short name T3577
Test name
Test status
Simulation time 50345529 ps
CPU time 0.73 seconds
Started Aug 17 06:07:24 PM PDT 24
Finished Aug 17 06:07:24 PM PDT 24
Peak memory 207452 kb
Host smart-98315d35-386a-46a6-ad3f-75f2d614b46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33657
46159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3365746159
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3283726411
Short name T265
Test name
Test status
Simulation time 17218144567 ps
CPU time 41.11 seconds
Started Aug 17 06:07:18 PM PDT 24
Finished Aug 17 06:08:00 PM PDT 24
Peak memory 215956 kb
Host smart-cc0506e0-ccb5-49f9-bf7a-32222fc128f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32837
26411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3283726411
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3061350734
Short name T1910
Test name
Test status
Simulation time 188144075 ps
CPU time 0.92 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207472 kb
Host smart-a87bfe5f-9f33-4d6f-b306-36ed02d89ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30613
50734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3061350734
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2341653977
Short name T2884
Test name
Test status
Simulation time 246956236 ps
CPU time 1.11 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207684 kb
Host smart-9fdc65d2-a4e9-4fcf-a101-dfa3bb72d9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23416
53977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2341653977
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3335146247
Short name T1531
Test name
Test status
Simulation time 251863029 ps
CPU time 1.23 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 207460 kb
Host smart-75e89ff2-4a94-47aa-848f-01cb0a0471d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33351
46247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3335146247
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3800696719
Short name T1009
Test name
Test status
Simulation time 182449272 ps
CPU time 0.87 seconds
Started Aug 17 06:07:18 PM PDT 24
Finished Aug 17 06:07:19 PM PDT 24
Peak memory 207476 kb
Host smart-59537277-4dd9-4580-ba0b-c2ac95126066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38006
96719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3800696719
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1522954929
Short name T812
Test name
Test status
Simulation time 170626196 ps
CPU time 0.9 seconds
Started Aug 17 06:07:23 PM PDT 24
Finished Aug 17 06:07:24 PM PDT 24
Peak memory 207456 kb
Host smart-d182ad5b-2967-4986-9acf-a064e7b6e124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15229
54929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1522954929
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_rx_full.1368791756
Short name T1962
Test name
Test status
Simulation time 282896264 ps
CPU time 1.14 seconds
Started Aug 17 06:07:21 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 207480 kb
Host smart-1bdab889-9cd1-4754-8d1a-0269b75db137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13687
91756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.1368791756
Directory /workspace/24.usbdev_rx_full/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3696351260
Short name T1766
Test name
Test status
Simulation time 175775162 ps
CPU time 0.87 seconds
Started Aug 17 06:07:18 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 207528 kb
Host smart-26503b9b-c4b1-4693-99ab-28e85b90f147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36963
51260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3696351260
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.172343193
Short name T3570
Test name
Test status
Simulation time 159841116 ps
CPU time 0.85 seconds
Started Aug 17 06:07:21 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 207564 kb
Host smart-b0f47095-a263-439d-9522-6f13efa3a555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17234
3193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.172343193
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.758318340
Short name T2593
Test name
Test status
Simulation time 221249432 ps
CPU time 0.99 seconds
Started Aug 17 06:07:22 PM PDT 24
Finished Aug 17 06:07:23 PM PDT 24
Peak memory 207428 kb
Host smart-d1c24604-b644-415f-a1ce-bf2e585372a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75831
8340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.758318340
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.774951231
Short name T2716
Test name
Test status
Simulation time 2218313773 ps
CPU time 65.27 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:08:25 PM PDT 24
Peak memory 224000 kb
Host smart-6e53b8a3-1639-49c6-a2a9-217f1659cbd4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=774951231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.774951231
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3986837016
Short name T1222
Test name
Test status
Simulation time 173137986 ps
CPU time 0.92 seconds
Started Aug 17 06:07:18 PM PDT 24
Finished Aug 17 06:07:19 PM PDT 24
Peak memory 207492 kb
Host smart-0470a108-3380-4d40-a8a1-3b4c0de20cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39868
37016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3986837016
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3864623809
Short name T1558
Test name
Test status
Simulation time 187968721 ps
CPU time 0.94 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207508 kb
Host smart-3fae133a-4a04-4e9d-b994-1da9501a49de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38646
23809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3864623809
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1195751904
Short name T1974
Test name
Test status
Simulation time 996012123 ps
CPU time 2.57 seconds
Started Aug 17 06:07:23 PM PDT 24
Finished Aug 17 06:07:26 PM PDT 24
Peak memory 207688 kb
Host smart-d48eaeb5-da3f-40c4-b47f-0a0e3b04c7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11957
51904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1195751904
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.4064882933
Short name T2040
Test name
Test status
Simulation time 2901377718 ps
CPU time 29.6 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:49 PM PDT 24
Peak memory 217688 kb
Host smart-a567cc83-9172-4a16-960c-520443374f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40648
82933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.4064882933
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.3083161182
Short name T963
Test name
Test status
Simulation time 1507289298 ps
CPU time 36.6 seconds
Started Aug 17 06:07:13 PM PDT 24
Finished Aug 17 06:07:50 PM PDT 24
Peak memory 207648 kb
Host smart-633b995e-bbe9-4969-a536-3a5edafe85ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083161182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.3083161182
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_tx_rx_disruption.2693660692
Short name T3467
Test name
Test status
Simulation time 492861818 ps
CPU time 1.58 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 207600 kb
Host smart-3e6c24fa-ab7b-494e-b264-627fa89e5b3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693660692 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.usbdev_tx_rx_disruption.2693660692
Directory /workspace/24.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/240.usbdev_tx_rx_disruption.3719209856
Short name T2510
Test name
Test status
Simulation time 452663243 ps
CPU time 1.55 seconds
Started Aug 17 06:11:55 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207580 kb
Host smart-4dd244b6-19d0-4c62-8b50-dfd6b640c380
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719209856 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.usbdev_tx_rx_disruption.3719209856
Directory /workspace/240.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/241.usbdev_tx_rx_disruption.3733090823
Short name T2045
Test name
Test status
Simulation time 544960042 ps
CPU time 1.79 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207540 kb
Host smart-0fa264da-92e0-4227-81a1-c3db7cd4017d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733090823 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.usbdev_tx_rx_disruption.3733090823
Directory /workspace/241.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/242.usbdev_tx_rx_disruption.1271172604
Short name T3213
Test name
Test status
Simulation time 486041644 ps
CPU time 1.51 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207544 kb
Host smart-1b5cebce-8dbf-464f-bf6a-1deaae9eb96b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271172604 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.usbdev_tx_rx_disruption.1271172604
Directory /workspace/242.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/243.usbdev_tx_rx_disruption.3811280410
Short name T1856
Test name
Test status
Simulation time 636349787 ps
CPU time 1.72 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207612 kb
Host smart-256ba019-3354-41c5-8f6e-4b89158c6d21
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811280410 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.usbdev_tx_rx_disruption.3811280410
Directory /workspace/243.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/244.usbdev_tx_rx_disruption.3896609576
Short name T1514
Test name
Test status
Simulation time 471699293 ps
CPU time 1.52 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207784 kb
Host smart-66b4c06d-7e8f-4f2a-9e7b-a555ef23b905
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896609576 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.usbdev_tx_rx_disruption.3896609576
Directory /workspace/244.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/245.usbdev_tx_rx_disruption.3404232997
Short name T2543
Test name
Test status
Simulation time 499312296 ps
CPU time 1.55 seconds
Started Aug 17 06:12:11 PM PDT 24
Finished Aug 17 06:12:12 PM PDT 24
Peak memory 207528 kb
Host smart-a5f81ce9-9dfa-4e10-a662-1cde08243d49
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404232997 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 245.usbdev_tx_rx_disruption.3404232997
Directory /workspace/245.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/246.usbdev_tx_rx_disruption.1868246312
Short name T3274
Test name
Test status
Simulation time 484132038 ps
CPU time 1.46 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207544 kb
Host smart-76dad5df-0313-4d09-9dc5-58f479f3f19e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868246312 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.usbdev_tx_rx_disruption.1868246312
Directory /workspace/246.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/247.usbdev_tx_rx_disruption.3465937001
Short name T2703
Test name
Test status
Simulation time 600239541 ps
CPU time 1.95 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207488 kb
Host smart-9d98559f-33be-4b31-bf69-2556b1c02093
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465937001 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.usbdev_tx_rx_disruption.3465937001
Directory /workspace/247.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/248.usbdev_tx_rx_disruption.3250212350
Short name T3500
Test name
Test status
Simulation time 582319601 ps
CPU time 1.74 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207512 kb
Host smart-5ca6f3d3-7a49-4bbb-9923-df43c5b7740a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250212350 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.usbdev_tx_rx_disruption.3250212350
Directory /workspace/248.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/249.usbdev_tx_rx_disruption.1583237873
Short name T3468
Test name
Test status
Simulation time 554514477 ps
CPU time 1.58 seconds
Started Aug 17 06:11:59 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207496 kb
Host smart-00c3cb39-a9c5-4c75-b977-b1cc7f5b9845
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583237873 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.usbdev_tx_rx_disruption.1583237873
Directory /workspace/249.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2015918857
Short name T3546
Test name
Test status
Simulation time 56036867 ps
CPU time 0.73 seconds
Started Aug 17 06:07:32 PM PDT 24
Finished Aug 17 06:07:33 PM PDT 24
Peak memory 207480 kb
Host smart-4be09417-47da-4849-bdf1-813f0aea0fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2015918857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2015918857
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1219007135
Short name T2728
Test name
Test status
Simulation time 5712431080 ps
CPU time 7.8 seconds
Started Aug 17 06:07:23 PM PDT 24
Finished Aug 17 06:07:31 PM PDT 24
Peak memory 216004 kb
Host smart-94ec6fa0-4a58-49de-88bd-30ab89c34cc5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219007135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.1219007135
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.502045579
Short name T1689
Test name
Test status
Simulation time 19948056694 ps
CPU time 23.12 seconds
Started Aug 17 06:07:22 PM PDT 24
Finished Aug 17 06:07:45 PM PDT 24
Peak memory 207736 kb
Host smart-cc6002f5-69f6-4b0d-b38e-faf949bf52a7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=502045579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.502045579
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1897369334
Short name T615
Test name
Test status
Simulation time 29511095973 ps
CPU time 33.67 seconds
Started Aug 17 06:07:21 PM PDT 24
Finished Aug 17 06:07:55 PM PDT 24
Peak memory 207784 kb
Host smart-c046f54f-984a-4baa-9f95-d8137519e742
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897369334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.1897369334
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2870371427
Short name T3608
Test name
Test status
Simulation time 145067479 ps
CPU time 0.83 seconds
Started Aug 17 06:07:26 PM PDT 24
Finished Aug 17 06:07:27 PM PDT 24
Peak memory 207396 kb
Host smart-6535c217-9e76-4878-935b-47891f15a4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28703
71427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2870371427
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.379295935
Short name T807
Test name
Test status
Simulation time 145688788 ps
CPU time 0.83 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207524 kb
Host smart-38485b12-ed42-4a9e-9c79-8ee9790ad724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37929
5935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.379295935
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.143925333
Short name T3526
Test name
Test status
Simulation time 405567756 ps
CPU time 1.48 seconds
Started Aug 17 06:07:22 PM PDT 24
Finished Aug 17 06:07:24 PM PDT 24
Peak memory 207488 kb
Host smart-be286c6e-a968-4aa8-b4d1-f347f43e3e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14392
5333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.143925333
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2808193490
Short name T1778
Test name
Test status
Simulation time 359586443 ps
CPU time 1.27 seconds
Started Aug 17 06:07:21 PM PDT 24
Finished Aug 17 06:07:22 PM PDT 24
Peak memory 207444 kb
Host smart-35ff22c1-1c76-4896-afec-21113e075a86
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2808193490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2808193490
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3565006921
Short name T1220
Test name
Test status
Simulation time 34328929849 ps
CPU time 56.42 seconds
Started Aug 17 06:07:21 PM PDT 24
Finished Aug 17 06:08:18 PM PDT 24
Peak memory 207744 kb
Host smart-e9c62d76-06ae-46ca-8f67-a24af4fd2320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35650
06921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3565006921
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.1937784763
Short name T2694
Test name
Test status
Simulation time 1365854024 ps
CPU time 9.37 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:29 PM PDT 24
Peak memory 207748 kb
Host smart-c715d7e9-801a-4cb9-9ea7-ef0c3406a1ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937784763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.1937784763
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2613314587
Short name T2309
Test name
Test status
Simulation time 904608125 ps
CPU time 1.91 seconds
Started Aug 17 06:07:21 PM PDT 24
Finished Aug 17 06:07:23 PM PDT 24
Peak memory 207504 kb
Host smart-ef4b8cef-c403-4d10-9b2c-0cb4f9486806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26133
14587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2613314587
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1582205345
Short name T2992
Test name
Test status
Simulation time 136090754 ps
CPU time 0.81 seconds
Started Aug 17 06:07:19 PM PDT 24
Finished Aug 17 06:07:20 PM PDT 24
Peak memory 207504 kb
Host smart-48732456-165b-4343-be1a-f9e80538dbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15822
05345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1582205345
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.513295670
Short name T1301
Test name
Test status
Simulation time 35291148 ps
CPU time 0.7 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207428 kb
Host smart-bdb62022-c58d-4853-9d13-d97273833005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51329
5670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.513295670
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1978049115
Short name T2177
Test name
Test status
Simulation time 1238273817 ps
CPU time 3.06 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:23 PM PDT 24
Peak memory 207792 kb
Host smart-b3e3ab20-a630-4f89-87dd-915272aadefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19780
49115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1978049115
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_types.2217660739
Short name T399
Test name
Test status
Simulation time 557516740 ps
CPU time 1.5 seconds
Started Aug 17 06:07:20 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 207472 kb
Host smart-0266769d-26a1-448b-825c-f88dc5b284b4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2217660739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.2217660739
Directory /workspace/25.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2734726356
Short name T2060
Test name
Test status
Simulation time 185952799 ps
CPU time 1.91 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:30 PM PDT 24
Peak memory 207664 kb
Host smart-263ff268-4f9e-4db6-b8a7-fa9e43ba8c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27347
26356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2734726356
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3004113140
Short name T754
Test name
Test status
Simulation time 161661564 ps
CPU time 0.88 seconds
Started Aug 17 06:07:35 PM PDT 24
Finished Aug 17 06:07:36 PM PDT 24
Peak memory 207460 kb
Host smart-606d399b-a583-4af4-87d9-91d437169e9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3004113140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3004113140
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2246088030
Short name T3537
Test name
Test status
Simulation time 151741983 ps
CPU time 0.9 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 207428 kb
Host smart-71a71579-1dff-40f9-a1ed-99b297ff803f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22460
88030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2246088030
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3496261402
Short name T1601
Test name
Test status
Simulation time 245463392 ps
CPU time 1.09 seconds
Started Aug 17 06:07:29 PM PDT 24
Finished Aug 17 06:07:30 PM PDT 24
Peak memory 207416 kb
Host smart-4115214c-1d1b-4bc7-9080-2587c4d6cb19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34962
61402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3496261402
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.1369665988
Short name T1987
Test name
Test status
Simulation time 3526362268 ps
CPU time 26.37 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 218164 kb
Host smart-b615bade-f6a7-4ab0-8498-8fe8d5c3a0ab
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1369665988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1369665988
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.1698275574
Short name T60
Test name
Test status
Simulation time 5893894910 ps
CPU time 74.25 seconds
Started Aug 17 06:07:26 PM PDT 24
Finished Aug 17 06:08:46 PM PDT 24
Peak memory 207768 kb
Host smart-c95cb0ec-5120-4a40-bf21-e722f2494767
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1698275574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.1698275574
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1967922522
Short name T1507
Test name
Test status
Simulation time 171389305 ps
CPU time 0.99 seconds
Started Aug 17 06:07:29 PM PDT 24
Finished Aug 17 06:07:30 PM PDT 24
Peak memory 207476 kb
Host smart-f26176e3-8641-430e-b263-7c89ebd48c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19679
22522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1967922522
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.2923879565
Short name T1876
Test name
Test status
Simulation time 9871951320 ps
CPU time 12.39 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:41 PM PDT 24
Peak memory 207816 kb
Host smart-5844604a-18b1-46d2-98c6-bfd7c1cbe163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29238
79565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.2923879565
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.971415341
Short name T2853
Test name
Test status
Simulation time 5331355148 ps
CPU time 7.47 seconds
Started Aug 17 06:07:30 PM PDT 24
Finished Aug 17 06:07:38 PM PDT 24
Peak memory 215908 kb
Host smart-5cbb5b76-a321-45b2-8f86-6bbd66771c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97141
5341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.971415341
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2342379050
Short name T2211
Test name
Test status
Simulation time 3290662808 ps
CPU time 34.5 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 217412 kb
Host smart-823b8f09-3bff-4145-ab45-5bf7c136244e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2342379050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2342379050
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.2481088025
Short name T2485
Test name
Test status
Simulation time 4178378011 ps
CPU time 47.21 seconds
Started Aug 17 06:07:29 PM PDT 24
Finished Aug 17 06:08:17 PM PDT 24
Peak memory 215868 kb
Host smart-1f9e6a44-423c-41d6-b81f-d877611b826a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2481088025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.2481088025
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.35260492
Short name T659
Test name
Test status
Simulation time 237005910 ps
CPU time 0.98 seconds
Started Aug 17 06:07:29 PM PDT 24
Finished Aug 17 06:07:30 PM PDT 24
Peak memory 207460 kb
Host smart-93aabb51-9b7a-434c-a7c4-f3fb94863dbd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=35260492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.35260492
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.388182251
Short name T3316
Test name
Test status
Simulation time 186522326 ps
CPU time 0.95 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:07:29 PM PDT 24
Peak memory 207372 kb
Host smart-e58e247d-796d-4f27-9d6e-efe6e65abac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38818
2251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.388182251
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.440187340
Short name T2771
Test name
Test status
Simulation time 3297532120 ps
CPU time 35.28 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 217648 kb
Host smart-2b761ad3-d684-420f-b90f-2008da2bfbe3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=440187340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.440187340
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.1850857473
Short name T1783
Test name
Test status
Simulation time 180086577 ps
CPU time 0.91 seconds
Started Aug 17 06:07:30 PM PDT 24
Finished Aug 17 06:07:31 PM PDT 24
Peak memory 207452 kb
Host smart-04f4e82c-28f8-4236-9854-1ba70be35f3e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1850857473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.1850857473
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2720281785
Short name T2020
Test name
Test status
Simulation time 149375527 ps
CPU time 0.87 seconds
Started Aug 17 06:07:29 PM PDT 24
Finished Aug 17 06:07:30 PM PDT 24
Peak memory 207464 kb
Host smart-3e4b41f3-8dac-4d31-a833-a4c8a54f0ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
81785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2720281785
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.4054392890
Short name T157
Test name
Test status
Simulation time 166434133 ps
CPU time 0.89 seconds
Started Aug 17 06:07:30 PM PDT 24
Finished Aug 17 06:07:31 PM PDT 24
Peak memory 207464 kb
Host smart-a95226aa-6c15-45e0-9297-a635e57156cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40543
92890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.4054392890
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1839171451
Short name T2343
Test name
Test status
Simulation time 180220996 ps
CPU time 0.96 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:07:33 PM PDT 24
Peak memory 207476 kb
Host smart-8733d58b-b689-4baf-8158-c0a76791f845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18391
71451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1839171451
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1575260050
Short name T1630
Test name
Test status
Simulation time 180944352 ps
CPU time 0.86 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 207452 kb
Host smart-2fd0adb8-1fa1-49e9-a09f-0e2193658e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15752
60050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1575260050
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2044772565
Short name T515
Test name
Test status
Simulation time 150149918 ps
CPU time 0.83 seconds
Started Aug 17 06:07:39 PM PDT 24
Finished Aug 17 06:07:40 PM PDT 24
Peak memory 207556 kb
Host smart-e594b1e4-2917-436b-8a56-fc38086a2963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20447
72565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2044772565
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2367590863
Short name T2436
Test name
Test status
Simulation time 157432990 ps
CPU time 0.92 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:29 PM PDT 24
Peak memory 207492 kb
Host smart-4dcb5a81-ec94-4042-9d6e-49b86e06206c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
90863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2367590863
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2318681029
Short name T2723
Test name
Test status
Simulation time 263157229 ps
CPU time 1.11 seconds
Started Aug 17 06:07:29 PM PDT 24
Finished Aug 17 06:07:30 PM PDT 24
Peak memory 207524 kb
Host smart-42ebd916-5fbe-46f4-84f6-84c2023f85c1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2318681029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2318681029
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2382320016
Short name T2460
Test name
Test status
Simulation time 145373423 ps
CPU time 0.85 seconds
Started Aug 17 06:07:30 PM PDT 24
Finished Aug 17 06:07:31 PM PDT 24
Peak memory 207452 kb
Host smart-a66a806f-c25b-4aa0-82ce-f9fe62718731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23823
20016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2382320016
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4180293037
Short name T3553
Test name
Test status
Simulation time 52243671 ps
CPU time 0.71 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:29 PM PDT 24
Peak memory 207520 kb
Host smart-6a4b07f2-92c6-4818-b2dc-750d5c0c2a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41802
93037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4180293037
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3356107764
Short name T275
Test name
Test status
Simulation time 17582863229 ps
CPU time 44.78 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:08:13 PM PDT 24
Peak memory 216172 kb
Host smart-b60e0979-9297-4180-8c15-bae135405c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33561
07764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3356107764
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2211334566
Short name T1452
Test name
Test status
Simulation time 204801985 ps
CPU time 0.91 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:29 PM PDT 24
Peak memory 207544 kb
Host smart-8e04227b-480a-47cb-8fdd-5ce7033bc192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22113
34566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2211334566
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2990251764
Short name T1493
Test name
Test status
Simulation time 228454320 ps
CPU time 1 seconds
Started Aug 17 06:07:26 PM PDT 24
Finished Aug 17 06:07:27 PM PDT 24
Peak memory 207400 kb
Host smart-44d22c9d-a1d7-407b-9bdc-a21256e313d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29902
51764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2990251764
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3521979415
Short name T1685
Test name
Test status
Simulation time 269827416 ps
CPU time 1.02 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 207464 kb
Host smart-4eda5cf1-004a-4c9d-b071-8d50f2dd3fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35219
79415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3521979415
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2272971723
Short name T3171
Test name
Test status
Simulation time 193311673 ps
CPU time 0.95 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:07:28 PM PDT 24
Peak memory 207424 kb
Host smart-39a52486-7645-4029-961b-e53ae07f6feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22729
71723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2272971723
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3750442447
Short name T1506
Test name
Test status
Simulation time 145465742 ps
CPU time 0.82 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:07:28 PM PDT 24
Peak memory 207452 kb
Host smart-d58bee9f-034f-40ec-ae4a-b54104de0c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37504
42447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3750442447
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_rx_full.2267092724
Short name T2726
Test name
Test status
Simulation time 317257193 ps
CPU time 1.24 seconds
Started Aug 17 06:07:30 PM PDT 24
Finished Aug 17 06:07:31 PM PDT 24
Peak memory 207488 kb
Host smart-f09aef01-402f-4c63-9100-6586cbff70a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22670
92724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.2267092724
Directory /workspace/25.usbdev_rx_full/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1843129128
Short name T3507
Test name
Test status
Simulation time 146963665 ps
CPU time 0.88 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:29 PM PDT 24
Peak memory 207532 kb
Host smart-a5e961b5-f3b6-4959-b63f-0c09bce6c8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18431
29128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1843129128
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2690794472
Short name T2383
Test name
Test status
Simulation time 144763242 ps
CPU time 0.83 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:07:28 PM PDT 24
Peak memory 207472 kb
Host smart-60b6ecdb-4f53-4b21-9fac-094ec2be3af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26907
94472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2690794472
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2078719999
Short name T2320
Test name
Test status
Simulation time 204504502 ps
CPU time 1.06 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:07:28 PM PDT 24
Peak memory 207384 kb
Host smart-49bcd953-eff1-4f25-b852-2867bba97652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20787
19999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2078719999
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.762186056
Short name T2042
Test name
Test status
Simulation time 2480328102 ps
CPU time 24.81 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:53 PM PDT 24
Peak memory 224040 kb
Host smart-50912e61-ad76-4cf5-b0ba-e9d126cfb519
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=762186056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.762186056
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1436638838
Short name T3344
Test name
Test status
Simulation time 163861142 ps
CPU time 0.93 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 207500 kb
Host smart-03919333-6385-4226-bc08-4dcda98c3ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14366
38838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1436638838
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2049277478
Short name T673
Test name
Test status
Simulation time 165918255 ps
CPU time 0.91 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 207536 kb
Host smart-3213093b-d8b9-4b8a-a3ce-8ad1623d6e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20492
77478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2049277478
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.2263135415
Short name T2246
Test name
Test status
Simulation time 1192519475 ps
CPU time 2.78 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:07:31 PM PDT 24
Peak memory 207736 kb
Host smart-e84a92e4-f5af-4827-aa29-398412a8bf3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22631
35415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2263135415
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2858945937
Short name T2683
Test name
Test status
Simulation time 3375063420 ps
CPU time 35.28 seconds
Started Aug 17 06:07:27 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 217568 kb
Host smart-6502cdcb-e75b-4da4-acba-8c26b8043fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28589
45937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2858945937
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.622572682
Short name T2164
Test name
Test status
Simulation time 5666398499 ps
CPU time 37.51 seconds
Started Aug 17 06:07:24 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 207688 kb
Host smart-21cc7e69-fedc-41fd-a879-3aed7500a727
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622572682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_host
_handshake.622572682
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_tx_rx_disruption.1766234471
Short name T2063
Test name
Test status
Simulation time 491916535 ps
CPU time 1.67 seconds
Started Aug 17 06:07:30 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 207564 kb
Host smart-8725c930-c732-42b0-bf1a-e5fab14d2722
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766234471 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.usbdev_tx_rx_disruption.1766234471
Directory /workspace/25.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/250.usbdev_tx_rx_disruption.1621609061
Short name T2528
Test name
Test status
Simulation time 472035892 ps
CPU time 1.46 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207560 kb
Host smart-d895cb18-a210-404c-92b1-9cb82c9669c1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621609061 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.usbdev_tx_rx_disruption.1621609061
Directory /workspace/250.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/251.usbdev_tx_rx_disruption.2286271376
Short name T655
Test name
Test status
Simulation time 604031430 ps
CPU time 1.82 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207504 kb
Host smart-1c09f960-9653-4e8c-a052-be9ba9891b20
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286271376 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.usbdev_tx_rx_disruption.2286271376
Directory /workspace/251.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/252.usbdev_tx_rx_disruption.4105185130
Short name T2633
Test name
Test status
Simulation time 492395667 ps
CPU time 1.54 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207580 kb
Host smart-bf443868-509c-4e04-973d-383aa0ccbad5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105185130 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.usbdev_tx_rx_disruption.4105185130
Directory /workspace/252.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/253.usbdev_tx_rx_disruption.3224368074
Short name T2251
Test name
Test status
Simulation time 529710052 ps
CPU time 1.64 seconds
Started Aug 17 06:11:58 PM PDT 24
Finished Aug 17 06:12:00 PM PDT 24
Peak memory 207596 kb
Host smart-fabd85e5-c3a0-4c00-ad38-16f0aa26c33e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224368074 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.usbdev_tx_rx_disruption.3224368074
Directory /workspace/253.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/254.usbdev_tx_rx_disruption.1425049159
Short name T2733
Test name
Test status
Simulation time 518139076 ps
CPU time 1.51 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207564 kb
Host smart-ff4bcf81-b0d7-4b97-807b-8c5b02323e57
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425049159 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.usbdev_tx_rx_disruption.1425049159
Directory /workspace/254.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/255.usbdev_tx_rx_disruption.2300265769
Short name T3412
Test name
Test status
Simulation time 469595305 ps
CPU time 1.67 seconds
Started Aug 17 06:11:54 PM PDT 24
Finished Aug 17 06:11:56 PM PDT 24
Peak memory 207532 kb
Host smart-ce821e53-54e8-4c46-919a-106b3bcea2bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300265769 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.usbdev_tx_rx_disruption.2300265769
Directory /workspace/255.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/256.usbdev_tx_rx_disruption.1395994082
Short name T1383
Test name
Test status
Simulation time 591553556 ps
CPU time 1.6 seconds
Started Aug 17 06:12:15 PM PDT 24
Finished Aug 17 06:12:17 PM PDT 24
Peak memory 207500 kb
Host smart-7e2b1279-6636-4de4-9642-6f5fea9227d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395994082 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.usbdev_tx_rx_disruption.1395994082
Directory /workspace/256.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/257.usbdev_tx_rx_disruption.2000761706
Short name T3146
Test name
Test status
Simulation time 634922604 ps
CPU time 1.87 seconds
Started Aug 17 06:12:00 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207488 kb
Host smart-fe5e3561-d7e8-443d-a91b-932c53dd672b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000761706 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.usbdev_tx_rx_disruption.2000761706
Directory /workspace/257.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/258.usbdev_tx_rx_disruption.3914350116
Short name T2375
Test name
Test status
Simulation time 452645772 ps
CPU time 1.57 seconds
Started Aug 17 06:12:04 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207548 kb
Host smart-c1faff43-3fd1-4058-80eb-d8e0716a0f36
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914350116 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.usbdev_tx_rx_disruption.3914350116
Directory /workspace/258.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/259.usbdev_tx_rx_disruption.2683147272
Short name T34
Test name
Test status
Simulation time 531493987 ps
CPU time 1.63 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207604 kb
Host smart-7d56ff4b-dfa3-4ef8-99d8-5a2e2ab4dc2f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683147272 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.usbdev_tx_rx_disruption.2683147272
Directory /workspace/259.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2656558501
Short name T3104
Test name
Test status
Simulation time 37137799 ps
CPU time 0.69 seconds
Started Aug 17 06:07:41 PM PDT 24
Finished Aug 17 06:07:42 PM PDT 24
Peak memory 207444 kb
Host smart-138d8c3d-d904-4466-818f-b22c04a5639b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2656558501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2656558501
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.550493113
Short name T3466
Test name
Test status
Simulation time 10756214710 ps
CPU time 14.22 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:42 PM PDT 24
Peak memory 207728 kb
Host smart-1ddd539c-47f9-4909-a8a7-0575984e341e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550493113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ao
n_wake_disconnect.550493113
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3723014331
Short name T3163
Test name
Test status
Simulation time 20050644625 ps
CPU time 29.38 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:58 PM PDT 24
Peak memory 207796 kb
Host smart-d0c94c55-efee-49c2-8e32-6d2602d5929d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723014331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3723014331
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3143497573
Short name T2213
Test name
Test status
Simulation time 29437796847 ps
CPU time 36.37 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:08:08 PM PDT 24
Peak memory 207776 kb
Host smart-ef8a6f3a-7fd0-4781-905c-ccd1f4e0fbe3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143497573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.3143497573
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1237761979
Short name T3441
Test name
Test status
Simulation time 164850048 ps
CPU time 0.85 seconds
Started Aug 17 06:07:30 PM PDT 24
Finished Aug 17 06:07:31 PM PDT 24
Peak memory 207516 kb
Host smart-7cdc7a8b-4367-43d5-9209-c7e8dafafd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12377
61979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1237761979
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3123689322
Short name T3255
Test name
Test status
Simulation time 214592249 ps
CPU time 0.88 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 207560 kb
Host smart-d7ced29b-4f0c-4457-80ca-278307208916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31236
89322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3123689322
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3367450204
Short name T1970
Test name
Test status
Simulation time 162830230 ps
CPU time 0.91 seconds
Started Aug 17 06:07:28 PM PDT 24
Finished Aug 17 06:07:29 PM PDT 24
Peak memory 207512 kb
Host smart-0a35b2d4-06fb-47eb-ba35-c152974ed354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33674
50204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3367450204
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3044078505
Short name T2637
Test name
Test status
Simulation time 521170725 ps
CPU time 1.55 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:07:33 PM PDT 24
Peak memory 207476 kb
Host smart-7335e47c-7c97-471d-a89b-973382a8b8aa
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3044078505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3044078505
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1225182641
Short name T2834
Test name
Test status
Simulation time 18969916893 ps
CPU time 32.99 seconds
Started Aug 17 06:07:48 PM PDT 24
Finished Aug 17 06:08:21 PM PDT 24
Peak memory 207756 kb
Host smart-8bf663da-2f34-42df-aadf-66ce4c8a123f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251
82641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1225182641
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.113138039
Short name T2220
Test name
Test status
Simulation time 4300728282 ps
CPU time 38.27 seconds
Started Aug 17 06:07:35 PM PDT 24
Finished Aug 17 06:08:13 PM PDT 24
Peak memory 207772 kb
Host smart-41521313-60fb-413e-9c55-3ed9b0c472e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113138039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.113138039
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.851206291
Short name T482
Test name
Test status
Simulation time 823181800 ps
CPU time 2.04 seconds
Started Aug 17 06:07:34 PM PDT 24
Finished Aug 17 06:07:36 PM PDT 24
Peak memory 207524 kb
Host smart-32280624-89f5-4fe1-8280-f6b187eed0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85120
6291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.851206291
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3838747151
Short name T2532
Test name
Test status
Simulation time 142484549 ps
CPU time 0.82 seconds
Started Aug 17 06:07:35 PM PDT 24
Finished Aug 17 06:07:36 PM PDT 24
Peak memory 207560 kb
Host smart-cc1fee76-6510-4f96-883f-7a6143330e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38387
47151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3838747151
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3744004691
Short name T809
Test name
Test status
Simulation time 42012206 ps
CPU time 0.72 seconds
Started Aug 17 06:07:36 PM PDT 24
Finished Aug 17 06:07:37 PM PDT 24
Peak memory 207428 kb
Host smart-72aebfcf-4a1e-4f8f-abfb-8c159f9b2dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37440
04691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3744004691
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2546587597
Short name T2453
Test name
Test status
Simulation time 926151519 ps
CPU time 2.35 seconds
Started Aug 17 06:07:35 PM PDT 24
Finished Aug 17 06:07:37 PM PDT 24
Peak memory 207764 kb
Host smart-f656eecb-719b-4c70-9623-72733c9af3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25465
87597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2546587597
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_types.793181088
Short name T501
Test name
Test status
Simulation time 201776695 ps
CPU time 0.99 seconds
Started Aug 17 06:07:41 PM PDT 24
Finished Aug 17 06:07:42 PM PDT 24
Peak memory 207560 kb
Host smart-9f59e8c2-87df-4b9d-ac7a-0616f99e00d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=793181088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.793181088
Directory /workspace/26.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3940072140
Short name T2806
Test name
Test status
Simulation time 309215152 ps
CPU time 2.74 seconds
Started Aug 17 06:07:36 PM PDT 24
Finished Aug 17 06:07:38 PM PDT 24
Peak memory 207656 kb
Host smart-db01bded-a744-4939-9820-3db24a26dc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39400
72140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3940072140
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1718139214
Short name T771
Test name
Test status
Simulation time 171677439 ps
CPU time 0.97 seconds
Started Aug 17 06:07:44 PM PDT 24
Finished Aug 17 06:07:45 PM PDT 24
Peak memory 207500 kb
Host smart-f017c949-04aa-43bd-8e72-0737a0f5b734
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1718139214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1718139214
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1164523132
Short name T2970
Test name
Test status
Simulation time 200235054 ps
CPU time 0.92 seconds
Started Aug 17 06:07:34 PM PDT 24
Finished Aug 17 06:07:35 PM PDT 24
Peak memory 207404 kb
Host smart-ca783db7-9c2d-4578-89b4-9ff2f8aca704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645
23132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1164523132
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1329800760
Short name T2209
Test name
Test status
Simulation time 223648806 ps
CPU time 0.98 seconds
Started Aug 17 06:07:45 PM PDT 24
Finished Aug 17 06:07:46 PM PDT 24
Peak memory 207480 kb
Host smart-02cef0a8-4e92-4982-864b-16678b25d6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13298
00760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1329800760
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.3695564310
Short name T931
Test name
Test status
Simulation time 4927923569 ps
CPU time 144.36 seconds
Started Aug 17 06:07:31 PM PDT 24
Finished Aug 17 06:09:56 PM PDT 24
Peak memory 215968 kb
Host smart-e3b73ebe-5ace-480e-a346-9e4e50bb16b0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3695564310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.3695564310
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.1247502263
Short name T819
Test name
Test status
Simulation time 8003553430 ps
CPU time 53.7 seconds
Started Aug 17 06:07:38 PM PDT 24
Finished Aug 17 06:08:31 PM PDT 24
Peak memory 207756 kb
Host smart-e34eceeb-be54-4a90-be43-ab5832e7f055
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1247502263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.1247502263
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1614349647
Short name T1842
Test name
Test status
Simulation time 232486038 ps
CPU time 0.98 seconds
Started Aug 17 06:07:47 PM PDT 24
Finished Aug 17 06:07:48 PM PDT 24
Peak memory 207504 kb
Host smart-c24db892-af47-42aa-bc50-b93135158750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16143
49647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1614349647
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.205748297
Short name T1656
Test name
Test status
Simulation time 8689269513 ps
CPU time 12.38 seconds
Started Aug 17 06:07:38 PM PDT 24
Finished Aug 17 06:07:51 PM PDT 24
Peak memory 215840 kb
Host smart-7169e5c2-2685-4696-a9b8-13f2e2d3a19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20574
8297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.205748297
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2243789777
Short name T105
Test name
Test status
Simulation time 3924082109 ps
CPU time 5.83 seconds
Started Aug 17 06:07:36 PM PDT 24
Finished Aug 17 06:07:42 PM PDT 24
Peak memory 215960 kb
Host smart-2c56aa20-5580-4127-be80-fa889c684760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22437
89777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2243789777
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.1450171229
Short name T460
Test name
Test status
Simulation time 3526122599 ps
CPU time 105.18 seconds
Started Aug 17 06:07:46 PM PDT 24
Finished Aug 17 06:09:32 PM PDT 24
Peak memory 218612 kb
Host smart-11095f32-031f-4914-98af-3a4d509c8173
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1450171229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.1450171229
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.3844037330
Short name T2305
Test name
Test status
Simulation time 2791312902 ps
CPU time 82.82 seconds
Started Aug 17 06:07:38 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 217260 kb
Host smart-806f6a36-8e4b-4d47-a582-588a1c02152c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3844037330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.3844037330
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.2486589262
Short name T536
Test name
Test status
Simulation time 297560093 ps
CPU time 1.09 seconds
Started Aug 17 06:07:39 PM PDT 24
Finished Aug 17 06:07:40 PM PDT 24
Peak memory 207484 kb
Host smart-d55fc483-c045-471f-a5ac-a225649890b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2486589262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.2486589262
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4227945293
Short name T1163
Test name
Test status
Simulation time 193064070 ps
CPU time 0.98 seconds
Started Aug 17 06:07:40 PM PDT 24
Finished Aug 17 06:07:41 PM PDT 24
Peak memory 207468 kb
Host smart-5887bbe6-1e24-46ae-b003-467c57485c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42279
45293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4227945293
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2539247379
Short name T1114
Test name
Test status
Simulation time 2842709773 ps
CPU time 21.52 seconds
Started Aug 17 06:07:36 PM PDT 24
Finished Aug 17 06:07:58 PM PDT 24
Peak memory 217576 kb
Host smart-4d100320-45e6-47ae-949b-b53f2f365de0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2539247379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2539247379
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.1566605565
Short name T1948
Test name
Test status
Simulation time 182136633 ps
CPU time 0.91 seconds
Started Aug 17 06:07:36 PM PDT 24
Finished Aug 17 06:07:37 PM PDT 24
Peak memory 207456 kb
Host smart-3ce748c0-b469-472c-9fa5-92df6d42c4e3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1566605565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.1566605565
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.642711911
Short name T308
Test name
Test status
Simulation time 182367113 ps
CPU time 0.91 seconds
Started Aug 17 06:07:43 PM PDT 24
Finished Aug 17 06:07:44 PM PDT 24
Peak memory 207468 kb
Host smart-215f069a-fe94-452d-a1a4-6deaab6cbb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64271
1911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.642711911
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3064373456
Short name T1535
Test name
Test status
Simulation time 173194921 ps
CPU time 0.96 seconds
Started Aug 17 06:07:47 PM PDT 24
Finished Aug 17 06:07:48 PM PDT 24
Peak memory 207428 kb
Host smart-6ac28497-2949-4a2d-9116-b14440c60cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30643
73456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3064373456
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.354036846
Short name T986
Test name
Test status
Simulation time 188603059 ps
CPU time 0.94 seconds
Started Aug 17 06:07:37 PM PDT 24
Finished Aug 17 06:07:38 PM PDT 24
Peak memory 207484 kb
Host smart-26326729-6a93-4352-93db-5dc4d465e641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35403
6846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.354036846
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1398619582
Short name T378
Test name
Test status
Simulation time 161918619 ps
CPU time 0.94 seconds
Started Aug 17 06:07:39 PM PDT 24
Finished Aug 17 06:07:40 PM PDT 24
Peak memory 207564 kb
Host smart-66721be7-f3dc-43bc-800e-53a63e19f824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13986
19582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1398619582
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3349403286
Short name T3476
Test name
Test status
Simulation time 147026608 ps
CPU time 0.94 seconds
Started Aug 17 06:07:37 PM PDT 24
Finished Aug 17 06:07:38 PM PDT 24
Peak memory 207564 kb
Host smart-ef1bba76-67e1-4a31-83ff-55e172d33d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33494
03286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3349403286
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1615574423
Short name T3265
Test name
Test status
Simulation time 219980985 ps
CPU time 1.01 seconds
Started Aug 17 06:07:45 PM PDT 24
Finished Aug 17 06:07:46 PM PDT 24
Peak memory 207496 kb
Host smart-59e4a5d3-a6e0-4e79-9de8-0e9336a6cea3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1615574423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1615574423
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.3628735587
Short name T2564
Test name
Test status
Simulation time 154818117 ps
CPU time 0.91 seconds
Started Aug 17 06:07:37 PM PDT 24
Finished Aug 17 06:07:38 PM PDT 24
Peak memory 207448 kb
Host smart-a7974480-890e-4b98-9620-608aacc9891c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36287
35587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.3628735587
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3455434248
Short name T1207
Test name
Test status
Simulation time 54143211 ps
CPU time 0.71 seconds
Started Aug 17 06:07:46 PM PDT 24
Finished Aug 17 06:07:47 PM PDT 24
Peak memory 207468 kb
Host smart-e207c67e-0bbb-4230-819d-4f69962ed5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34554
34248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3455434248
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1234237018
Short name T2997
Test name
Test status
Simulation time 10390137184 ps
CPU time 27.67 seconds
Started Aug 17 06:07:41 PM PDT 24
Finished Aug 17 06:08:08 PM PDT 24
Peak memory 215928 kb
Host smart-981e5fb2-0cea-4262-b3fb-9d4798264d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12342
37018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1234237018
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1612012655
Short name T2127
Test name
Test status
Simulation time 161810908 ps
CPU time 0.89 seconds
Started Aug 17 06:07:35 PM PDT 24
Finished Aug 17 06:07:36 PM PDT 24
Peak memory 207528 kb
Host smart-3fc2ca90-4c3b-482d-9e6a-da42d8ee3ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16120
12655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1612012655
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2406990337
Short name T3079
Test name
Test status
Simulation time 193257020 ps
CPU time 0.94 seconds
Started Aug 17 06:07:33 PM PDT 24
Finished Aug 17 06:07:34 PM PDT 24
Peak memory 207484 kb
Host smart-37bcfb99-196f-4c1b-b972-2d959bf58863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24069
90337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2406990337
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1637383159
Short name T3294
Test name
Test status
Simulation time 217213530 ps
CPU time 0.98 seconds
Started Aug 17 06:07:47 PM PDT 24
Finished Aug 17 06:07:48 PM PDT 24
Peak memory 207432 kb
Host smart-24866047-ef2e-4125-9519-e0ca2f65c914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16373
83159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1637383159
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.3654701948
Short name T567
Test name
Test status
Simulation time 199010251 ps
CPU time 0.93 seconds
Started Aug 17 06:07:48 PM PDT 24
Finished Aug 17 06:07:49 PM PDT 24
Peak memory 207432 kb
Host smart-0e29907c-df2e-440a-bf20-9124d4c1c6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36547
01948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.3654701948
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1752254530
Short name T3006
Test name
Test status
Simulation time 146991508 ps
CPU time 0.93 seconds
Started Aug 17 06:07:36 PM PDT 24
Finished Aug 17 06:07:37 PM PDT 24
Peak memory 207456 kb
Host smart-19deba09-8b9c-4980-a886-5639d91909cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17522
54530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1752254530
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_rx_full.2709108193
Short name T1486
Test name
Test status
Simulation time 424190859 ps
CPU time 1.47 seconds
Started Aug 17 06:07:34 PM PDT 24
Finished Aug 17 06:07:35 PM PDT 24
Peak memory 207496 kb
Host smart-9ae02aed-24a2-4aa4-bc88-017418d4c1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27091
08193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.2709108193
Directory /workspace/26.usbdev_rx_full/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.652571697
Short name T1530
Test name
Test status
Simulation time 156633450 ps
CPU time 0.88 seconds
Started Aug 17 06:07:37 PM PDT 24
Finished Aug 17 06:07:38 PM PDT 24
Peak memory 207440 kb
Host smart-b886a395-80ad-4439-8889-68f2b755425f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65257
1697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.652571697
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1886515038
Short name T3053
Test name
Test status
Simulation time 162573241 ps
CPU time 0.87 seconds
Started Aug 17 06:07:40 PM PDT 24
Finished Aug 17 06:07:41 PM PDT 24
Peak memory 207476 kb
Host smart-316927b7-1f2d-46f7-9f37-fdcf5b7b66ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18865
15038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1886515038
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2216379944
Short name T2340
Test name
Test status
Simulation time 202744559 ps
CPU time 0.95 seconds
Started Aug 17 06:07:40 PM PDT 24
Finished Aug 17 06:07:41 PM PDT 24
Peak memory 207468 kb
Host smart-8ff47ce1-a7cd-41fe-ac18-9b6fbdce0004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22163
79944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2216379944
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2139850763
Short name T2744
Test name
Test status
Simulation time 1425783185 ps
CPU time 41.1 seconds
Started Aug 17 06:07:38 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 215812 kb
Host smart-4d8c952b-84d0-4e24-821a-8024571d4164
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2139850763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2139850763
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1778395035
Short name T3033
Test name
Test status
Simulation time 190771009 ps
CPU time 0.89 seconds
Started Aug 17 06:07:45 PM PDT 24
Finished Aug 17 06:07:46 PM PDT 24
Peak memory 207512 kb
Host smart-afe6820a-878e-48c2-b615-dea6ff14393f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17783
95035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1778395035
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2188366785
Short name T2191
Test name
Test status
Simulation time 214364263 ps
CPU time 0.97 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207504 kb
Host smart-32d52a51-bdac-4559-b16a-2528494a87cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21883
66785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2188366785
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.360116058
Short name T1283
Test name
Test status
Simulation time 385110729 ps
CPU time 1.32 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:07:53 PM PDT 24
Peak memory 207504 kb
Host smart-b76f3f01-2ee5-46fc-8587-f0719433f212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36011
6058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.360116058
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.745711662
Short name T2334
Test name
Test status
Simulation time 2669837026 ps
CPU time 26.71 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 217568 kb
Host smart-45c06f93-f5d2-427f-942a-ebee7b10cb1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74571
1662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.745711662
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.1273348359
Short name T3606
Test name
Test status
Simulation time 876926915 ps
CPU time 19.12 seconds
Started Aug 17 06:07:34 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207636 kb
Host smart-6292cde6-7839-493a-8bce-dec6b8850881
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273348359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.1273348359
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_tx_rx_disruption.2765895911
Short name T196
Test name
Test status
Simulation time 585093960 ps
CPU time 1.66 seconds
Started Aug 17 06:07:42 PM PDT 24
Finished Aug 17 06:07:44 PM PDT 24
Peak memory 207536 kb
Host smart-edc212e6-1898-4ba0-912e-eed0d4df7e5d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765895911 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.usbdev_tx_rx_disruption.2765895911
Directory /workspace/26.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/260.usbdev_tx_rx_disruption.389181723
Short name T1995
Test name
Test status
Simulation time 615356072 ps
CPU time 1.7 seconds
Started Aug 17 06:12:13 PM PDT 24
Finished Aug 17 06:12:15 PM PDT 24
Peak memory 207784 kb
Host smart-57cd6845-7360-4d09-b08f-d5e3b74b45de
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389181723 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 260.usbdev_tx_rx_disruption.389181723
Directory /workspace/260.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/261.usbdev_tx_rx_disruption.2810586958
Short name T1628
Test name
Test status
Simulation time 588343782 ps
CPU time 1.48 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207544 kb
Host smart-7a418b11-5ae0-43d7-b999-28debe13056a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810586958 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.usbdev_tx_rx_disruption.2810586958
Directory /workspace/261.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/262.usbdev_tx_rx_disruption.1148920713
Short name T1358
Test name
Test status
Simulation time 616411126 ps
CPU time 1.63 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207520 kb
Host smart-2a751fb3-920a-4c60-88d5-6300dd15f40b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148920713 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.usbdev_tx_rx_disruption.1148920713
Directory /workspace/262.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/263.usbdev_tx_rx_disruption.273335902
Short name T1010
Test name
Test status
Simulation time 619085695 ps
CPU time 1.74 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207576 kb
Host smart-0b73ec71-a29a-461e-9bf5-f2b6529f470b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273335902 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 263.usbdev_tx_rx_disruption.273335902
Directory /workspace/263.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/264.usbdev_tx_rx_disruption.1217823577
Short name T942
Test name
Test status
Simulation time 529380439 ps
CPU time 1.68 seconds
Started Aug 17 06:12:00 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207612 kb
Host smart-7305e685-7e82-4afc-ac3d-fd358a22e989
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217823577 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.usbdev_tx_rx_disruption.1217823577
Directory /workspace/264.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/265.usbdev_tx_rx_disruption.2796469242
Short name T2438
Test name
Test status
Simulation time 472844573 ps
CPU time 1.43 seconds
Started Aug 17 06:12:07 PM PDT 24
Finished Aug 17 06:12:09 PM PDT 24
Peak memory 207496 kb
Host smart-948231db-7808-438b-82b8-fc7b41b05c4a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796469242 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 265.usbdev_tx_rx_disruption.2796469242
Directory /workspace/265.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/266.usbdev_tx_rx_disruption.2378416053
Short name T1424
Test name
Test status
Simulation time 574679613 ps
CPU time 1.67 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207520 kb
Host smart-b706954b-e30e-4833-b47d-d81d732d0b72
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378416053 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.usbdev_tx_rx_disruption.2378416053
Directory /workspace/266.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/267.usbdev_tx_rx_disruption.1198159292
Short name T634
Test name
Test status
Simulation time 558944726 ps
CPU time 1.59 seconds
Started Aug 17 06:11:58 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207576 kb
Host smart-a57a38c2-5d8e-4f56-8f07-8c510fbbd6ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198159292 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.usbdev_tx_rx_disruption.1198159292
Directory /workspace/267.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/268.usbdev_tx_rx_disruption.2137826101
Short name T2616
Test name
Test status
Simulation time 692707295 ps
CPU time 1.88 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207572 kb
Host smart-b6096eaa-72d5-4fbe-8a74-da3ba9f35c71
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137826101 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.usbdev_tx_rx_disruption.2137826101
Directory /workspace/268.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/269.usbdev_tx_rx_disruption.2925611960
Short name T3345
Test name
Test status
Simulation time 492013812 ps
CPU time 1.49 seconds
Started Aug 17 06:12:04 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207548 kb
Host smart-fd2cd461-9ef1-4b87-971c-4e397f85ec87
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925611960 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.usbdev_tx_rx_disruption.2925611960
Directory /workspace/269.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2179385115
Short name T839
Test name
Test status
Simulation time 38499439 ps
CPU time 0.73 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207416 kb
Host smart-e0e2dfe6-83fd-4690-bd50-c6e2d6605f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2179385115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2179385115
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.731363495
Short name T2037
Test name
Test status
Simulation time 4471563766 ps
CPU time 6.04 seconds
Started Aug 17 06:07:46 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 215952 kb
Host smart-1df81dc2-4d80-42a8-bbcb-d514ca19fa5f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731363495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_ao
n_wake_disconnect.731363495
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.453487893
Short name T2
Test name
Test status
Simulation time 15301756586 ps
CPU time 18.07 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:08:10 PM PDT 24
Peak memory 215956 kb
Host smart-4b954e56-8981-494b-8e5a-7f608eeb3877
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=453487893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.453487893
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.4272653946
Short name T559
Test name
Test status
Simulation time 23596105331 ps
CPU time 32.57 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:08:25 PM PDT 24
Peak memory 215872 kb
Host smart-fb7c357e-2c9e-43ce-b036-52c4c362462c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272653946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.4272653946
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3050002050
Short name T3108
Test name
Test status
Simulation time 189561503 ps
CPU time 0.92 seconds
Started Aug 17 06:07:50 PM PDT 24
Finished Aug 17 06:07:51 PM PDT 24
Peak memory 207476 kb
Host smart-66ea2eb1-8299-467b-9773-c708482b25cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
02050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3050002050
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2255517470
Short name T2056
Test name
Test status
Simulation time 187222168 ps
CPU time 0.93 seconds
Started Aug 17 06:07:50 PM PDT 24
Finished Aug 17 06:07:51 PM PDT 24
Peak memory 207456 kb
Host smart-a6eb89a5-4e59-4e4c-a76b-2ead3ca31c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22555
17470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2255517470
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2270733265
Short name T3156
Test name
Test status
Simulation time 260665589 ps
CPU time 1.12 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207536 kb
Host smart-bdef0ce4-3cae-45c9-b120-0f1a58862715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22707
33265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2270733265
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2880262388
Short name T2135
Test name
Test status
Simulation time 573999232 ps
CPU time 1.91 seconds
Started Aug 17 06:07:49 PM PDT 24
Finished Aug 17 06:07:51 PM PDT 24
Peak memory 207448 kb
Host smart-913dd5ec-9bee-4f32-8db8-681edc5a0acb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2880262388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2880262388
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.981271267
Short name T1996
Test name
Test status
Simulation time 18728556370 ps
CPU time 35.06 seconds
Started Aug 17 06:07:48 PM PDT 24
Finished Aug 17 06:08:23 PM PDT 24
Peak memory 207776 kb
Host smart-0a0a6641-5f67-4568-9638-369a1337cf94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98127
1267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.981271267
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.3355826689
Short name T3389
Test name
Test status
Simulation time 1173389983 ps
CPU time 26.31 seconds
Started Aug 17 06:07:47 PM PDT 24
Finished Aug 17 06:08:13 PM PDT 24
Peak memory 207740 kb
Host smart-af6aa458-99cc-44d1-9748-bd054d04b791
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355826689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.3355826689
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1843877807
Short name T1567
Test name
Test status
Simulation time 1170455200 ps
CPU time 2.5 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 207576 kb
Host smart-e8fd5d48-5b3e-4771-b939-0af457ef6471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18438
77807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1843877807
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2896802387
Short name T59
Test name
Test status
Simulation time 134561660 ps
CPU time 0.82 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207524 kb
Host smart-5c8ce422-d9de-47f7-9293-829d57ac5eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28968
02387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2896802387
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2366943496
Short name T1612
Test name
Test status
Simulation time 71354031 ps
CPU time 0.78 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207460 kb
Host smart-0a30d54a-4a0d-445b-afca-bb4de483b0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23669
43496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2366943496
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2859461104
Short name T1254
Test name
Test status
Simulation time 904198863 ps
CPU time 2.4 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 207732 kb
Host smart-1dbd68e0-f0e8-4f66-bad2-abf5ba229b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28594
61104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2859461104
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_types.4059624572
Short name T509
Test name
Test status
Simulation time 458831498 ps
CPU time 1.32 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207520 kb
Host smart-c5a47b3a-6b33-4079-b78a-2976b9ca366e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4059624572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.4059624572
Directory /workspace/27.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.4210316691
Short name T1925
Test name
Test status
Simulation time 330716497 ps
CPU time 2.54 seconds
Started Aug 17 06:07:48 PM PDT 24
Finished Aug 17 06:07:51 PM PDT 24
Peak memory 207624 kb
Host smart-157d2b48-1ada-4df4-bc51-814d86f35473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42103
16691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.4210316691
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3251417967
Short name T2652
Test name
Test status
Simulation time 196237133 ps
CPU time 1.03 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:07:53 PM PDT 24
Peak memory 215876 kb
Host smart-0263d39d-f53d-4fe6-b4a6-f64fd706fbff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3251417967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3251417967
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3653837320
Short name T1460
Test name
Test status
Simulation time 168894271 ps
CPU time 0.87 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207340 kb
Host smart-3c3df2a4-95ef-4443-9050-be5e014972cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36538
37320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3653837320
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.58427348
Short name T2829
Test name
Test status
Simulation time 152695734 ps
CPU time 0.91 seconds
Started Aug 17 06:07:50 PM PDT 24
Finished Aug 17 06:07:51 PM PDT 24
Peak memory 207436 kb
Host smart-d1c94e31-f966-4958-8758-af791d3366f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58427
348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.58427348
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.726390375
Short name T2471
Test name
Test status
Simulation time 3731342315 ps
CPU time 114.23 seconds
Started Aug 17 06:07:50 PM PDT 24
Finished Aug 17 06:09:45 PM PDT 24
Peak memory 217576 kb
Host smart-4d5efb18-a23c-4a6e-b7c1-85a76d92f854
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=726390375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.726390375
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.943656064
Short name T2181
Test name
Test status
Simulation time 11739696012 ps
CPU time 84.7 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:09:16 PM PDT 24
Peak memory 207688 kb
Host smart-ab0e0f28-d490-4274-b5d5-410843c9d0fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=943656064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.943656064
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.835201264
Short name T823
Test name
Test status
Simulation time 251669106 ps
CPU time 1.01 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207460 kb
Host smart-852a0f22-78af-4373-b20e-558ae53355d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83520
1264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.835201264
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3154149503
Short name T1919
Test name
Test status
Simulation time 8524415303 ps
CPU time 13.02 seconds
Started Aug 17 06:07:50 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 216048 kb
Host smart-94f4c417-431d-48f4-8526-50b61c406f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31541
49503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3154149503
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2551488955
Short name T984
Test name
Test status
Simulation time 4383246562 ps
CPU time 6.96 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:08:00 PM PDT 24
Peak memory 216020 kb
Host smart-fc386215-cb6c-4761-b08f-5bfd68f34058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25514
88955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2551488955
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3509433410
Short name T2551
Test name
Test status
Simulation time 4283037092 ps
CPU time 119.98 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 216028 kb
Host smart-df31b82a-13eb-4767-b227-8e92aa418e47
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3509433410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3509433410
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3589863407
Short name T951
Test name
Test status
Simulation time 3743995608 ps
CPU time 27.78 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:08:20 PM PDT 24
Peak memory 215932 kb
Host smart-5f1a8c6d-46ff-4655-8ec0-3a342eeddb55
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3589863407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3589863407
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1696687751
Short name T1510
Test name
Test status
Simulation time 256432732 ps
CPU time 1.04 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207340 kb
Host smart-422bcf34-af33-46b0-a3f9-1cd99ef94d0a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1696687751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1696687751
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3868678180
Short name T1237
Test name
Test status
Simulation time 193027201 ps
CPU time 0.96 seconds
Started Aug 17 06:07:50 PM PDT 24
Finished Aug 17 06:07:51 PM PDT 24
Peak memory 207456 kb
Host smart-dac0465c-2138-4bc3-9706-6196ca681d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38686
78180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3868678180
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.53379434
Short name T1702
Test name
Test status
Simulation time 2041187853 ps
CPU time 22.21 seconds
Started Aug 17 06:07:50 PM PDT 24
Finished Aug 17 06:08:17 PM PDT 24
Peak memory 216440 kb
Host smart-cec85174-5f80-4344-865e-b9783df84d17
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=53379434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.53379434
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3150393442
Short name T1239
Test name
Test status
Simulation time 157842543 ps
CPU time 0.86 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:07:53 PM PDT 24
Peak memory 207392 kb
Host smart-e8e9a006-9603-482e-b5c6-1be682e2c9b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3150393442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3150393442
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1749275512
Short name T651
Test name
Test status
Simulation time 153834528 ps
CPU time 0.83 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207480 kb
Host smart-044f980b-48ed-4fc5-9e2e-f19a031dac56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17492
75512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1749275512
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1762217713
Short name T145
Test name
Test status
Simulation time 253321447 ps
CPU time 1.1 seconds
Started Aug 17 06:07:55 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 207480 kb
Host smart-d56e3265-8977-496a-8996-4ab4cecedae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17622
17713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1762217713
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1501140166
Short name T3303
Test name
Test status
Simulation time 170590600 ps
CPU time 0.9 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207416 kb
Host smart-3feae7de-011f-4278-b756-760810b2dfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15011
40166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1501140166
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3227706163
Short name T838
Test name
Test status
Simulation time 172851646 ps
CPU time 0.9 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207348 kb
Host smart-f485fff5-1563-42c0-a898-0030f0db0058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32277
06163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3227706163
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3253192369
Short name T2918
Test name
Test status
Simulation time 222366472 ps
CPU time 0.98 seconds
Started Aug 17 06:07:48 PM PDT 24
Finished Aug 17 06:07:49 PM PDT 24
Peak memory 207760 kb
Host smart-e54ca2bd-aac0-4a1b-9f97-bae3253b7234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32531
92369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3253192369
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1725753644
Short name T2452
Test name
Test status
Simulation time 206476204 ps
CPU time 0.91 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207508 kb
Host smart-b5a4213e-534f-4055-8e32-fbb8946a05d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17257
53644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1725753644
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3273562196
Short name T654
Test name
Test status
Simulation time 224134307 ps
CPU time 1.05 seconds
Started Aug 17 06:07:55 PM PDT 24
Finished Aug 17 06:07:57 PM PDT 24
Peak memory 207540 kb
Host smart-2e693063-4598-4c1d-8c36-62c947d38804
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3273562196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3273562196
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.294630507
Short name T3043
Test name
Test status
Simulation time 151223722 ps
CPU time 0.87 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207388 kb
Host smart-13c59dd3-ab89-434c-8376-f5328bc560ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29463
0507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.294630507
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.964890057
Short name T2668
Test name
Test status
Simulation time 30055765 ps
CPU time 0.71 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207584 kb
Host smart-93aff116-4f55-43df-a8ba-2db2c7d079f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96489
0057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.964890057
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.573246323
Short name T274
Test name
Test status
Simulation time 20210766143 ps
CPU time 52.1 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:08:46 PM PDT 24
Peak memory 224056 kb
Host smart-21cd0404-4edd-4c34-b91b-807e10cf5be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57324
6323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.573246323
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3351384442
Short name T366
Test name
Test status
Simulation time 194539007 ps
CPU time 0.94 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207564 kb
Host smart-004516fe-964c-4d1f-a74a-5c93f793f229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33513
84442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3351384442
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.212337788
Short name T1473
Test name
Test status
Simulation time 245032678 ps
CPU time 1.01 seconds
Started Aug 17 06:07:57 PM PDT 24
Finished Aug 17 06:07:58 PM PDT 24
Peak memory 207460 kb
Host smart-9e4798c0-0d06-46ef-8c4a-897bdbe8bc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21233
7788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.212337788
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1862653820
Short name T824
Test name
Test status
Simulation time 184218166 ps
CPU time 0.89 seconds
Started Aug 17 06:07:59 PM PDT 24
Finished Aug 17 06:08:00 PM PDT 24
Peak memory 207520 kb
Host smart-7b9e190e-fcc5-4674-9d5c-d2607a42af67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18626
53820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1862653820
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.51095711
Short name T1321
Test name
Test status
Simulation time 153948623 ps
CPU time 0.87 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:07:55 PM PDT 24
Peak memory 207488 kb
Host smart-45983c13-83d5-48e1-a01b-b4e48813cf25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51095
711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.51095711
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1248179058
Short name T72
Test name
Test status
Simulation time 162440638 ps
CPU time 0.91 seconds
Started Aug 17 06:07:55 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 207488 kb
Host smart-29ba7b4f-44a8-45f0-8a5b-d78de4b6a143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12481
79058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1248179058
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_rx_full.1453927645
Short name T3058
Test name
Test status
Simulation time 318546345 ps
CPU time 1.32 seconds
Started Aug 17 06:07:58 PM PDT 24
Finished Aug 17 06:07:59 PM PDT 24
Peak memory 207428 kb
Host smart-b14cc73f-3ea6-4485-acd6-c6c06a4edcee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14539
27645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.1453927645
Directory /workspace/27.usbdev_rx_full/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.619990223
Short name T1875
Test name
Test status
Simulation time 150829671 ps
CPU time 0.84 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:07:55 PM PDT 24
Peak memory 207456 kb
Host smart-b2d23d9d-f52a-4e7b-91d6-cf19eb4b5a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61999
0223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.619990223
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1638426015
Short name T3420
Test name
Test status
Simulation time 166104401 ps
CPU time 0.86 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:52 PM PDT 24
Peak memory 207488 kb
Host smart-0f294a93-19fd-4781-bf2d-01de3ef2cb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16384
26015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1638426015
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.956588182
Short name T779
Test name
Test status
Simulation time 229005753 ps
CPU time 1.02 seconds
Started Aug 17 06:07:55 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 207488 kb
Host smart-fd57a041-12e3-498a-9813-3fa4d0747a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95658
8182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.956588182
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.1771199701
Short name T2706
Test name
Test status
Simulation time 1668431735 ps
CPU time 50.1 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 215840 kb
Host smart-df35c666-1b5c-41b2-bc68-6d0b3e916c1f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1771199701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.1771199701
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.152332710
Short name T2979
Test name
Test status
Simulation time 162883345 ps
CPU time 0.86 seconds
Started Aug 17 06:07:55 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 207468 kb
Host smart-ea5fcff4-614c-4f98-b4d6-142aedbc7854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233
2710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.152332710
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3654261784
Short name T2015
Test name
Test status
Simulation time 170700017 ps
CPU time 0.89 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207532 kb
Host smart-ae30bc19-04a0-4f04-abb7-329a2c52ecf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36542
61784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3654261784
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.2092043719
Short name T3008
Test name
Test status
Simulation time 1225317090 ps
CPU time 3.03 seconds
Started Aug 17 06:07:57 PM PDT 24
Finished Aug 17 06:08:00 PM PDT 24
Peak memory 207708 kb
Host smart-7bf90d9b-7f70-476c-b43b-f1ca69f1772c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20920
43719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2092043719
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.848327171
Short name T1008
Test name
Test status
Simulation time 2507152764 ps
CPU time 18.94 seconds
Started Aug 17 06:07:56 PM PDT 24
Finished Aug 17 06:08:15 PM PDT 24
Peak memory 217876 kb
Host smart-8d170354-35b9-49e5-9a15-69902757c3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84832
7171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.848327171
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.1091787282
Short name T1666
Test name
Test status
Simulation time 1564404058 ps
CPU time 13.37 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207568 kb
Host smart-821a300a-a92c-4fd2-bfca-0ad4ac49ed0a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091787282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.1091787282
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_tx_rx_disruption.4230980283
Short name T1214
Test name
Test status
Simulation time 624603419 ps
CPU time 2 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207472 kb
Host smart-496499ff-0b9e-47bf-a94f-396c2ae399d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230980283 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.usbdev_tx_rx_disruption.4230980283
Directory /workspace/27.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/270.usbdev_tx_rx_disruption.3427791474
Short name T1670
Test name
Test status
Simulation time 399688928 ps
CPU time 1.27 seconds
Started Aug 17 06:12:21 PM PDT 24
Finished Aug 17 06:12:23 PM PDT 24
Peak memory 207508 kb
Host smart-b48a3c87-164d-48f3-99f6-6ddcd2c9501c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427791474 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.usbdev_tx_rx_disruption.3427791474
Directory /workspace/270.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/271.usbdev_tx_rx_disruption.927515903
Short name T2967
Test name
Test status
Simulation time 465596669 ps
CPU time 1.38 seconds
Started Aug 17 06:11:55 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207564 kb
Host smart-97905ba7-1ded-4c57-96c8-b8b150748ab3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927515903 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 271.usbdev_tx_rx_disruption.927515903
Directory /workspace/271.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/272.usbdev_tx_rx_disruption.2519766338
Short name T2520
Test name
Test status
Simulation time 511190130 ps
CPU time 1.5 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:58 PM PDT 24
Peak memory 207520 kb
Host smart-131cd3f6-deb6-4786-b424-ca5854e80d44
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519766338 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.usbdev_tx_rx_disruption.2519766338
Directory /workspace/272.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/273.usbdev_tx_rx_disruption.1182119952
Short name T3309
Test name
Test status
Simulation time 471115974 ps
CPU time 1.57 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207472 kb
Host smart-ec9ac241-d3d5-486a-944d-6820be9fae66
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182119952 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.usbdev_tx_rx_disruption.1182119952
Directory /workspace/273.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/274.usbdev_tx_rx_disruption.3020907045
Short name T1292
Test name
Test status
Simulation time 455192097 ps
CPU time 1.45 seconds
Started Aug 17 06:12:04 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207500 kb
Host smart-1e436804-b9e1-45c0-8a1c-b5eb6bc23713
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020907045 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.usbdev_tx_rx_disruption.3020907045
Directory /workspace/274.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/275.usbdev_tx_rx_disruption.1512385514
Short name T3534
Test name
Test status
Simulation time 462797201 ps
CPU time 1.4 seconds
Started Aug 17 06:12:05 PM PDT 24
Finished Aug 17 06:12:06 PM PDT 24
Peak memory 207568 kb
Host smart-cea59fc1-0a87-4423-9e10-e705d1e33aa9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512385514 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.usbdev_tx_rx_disruption.1512385514
Directory /workspace/275.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/276.usbdev_tx_rx_disruption.1307193059
Short name T211
Test name
Test status
Simulation time 450827620 ps
CPU time 1.48 seconds
Started Aug 17 06:12:06 PM PDT 24
Finished Aug 17 06:12:07 PM PDT 24
Peak memory 207576 kb
Host smart-160e6f0c-519b-4cdd-a4de-c0866efd02a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307193059 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.usbdev_tx_rx_disruption.1307193059
Directory /workspace/276.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/277.usbdev_tx_rx_disruption.2849665769
Short name T2133
Test name
Test status
Simulation time 593963948 ps
CPU time 1.55 seconds
Started Aug 17 06:12:00 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207544 kb
Host smart-07b93ecd-7e93-4065-9ea6-d34e202d7516
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849665769 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.usbdev_tx_rx_disruption.2849665769
Directory /workspace/277.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/278.usbdev_tx_rx_disruption.3733696281
Short name T2360
Test name
Test status
Simulation time 513613634 ps
CPU time 1.66 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207528 kb
Host smart-ec1f364f-9514-4b58-88ee-8589b58c0aad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733696281 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.usbdev_tx_rx_disruption.3733696281
Directory /workspace/278.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/279.usbdev_tx_rx_disruption.1551811889
Short name T2823
Test name
Test status
Simulation time 652622423 ps
CPU time 1.65 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:09 PM PDT 24
Peak memory 207540 kb
Host smart-398ad982-3fae-47b5-9004-e7b865bea601
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551811889 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.usbdev_tx_rx_disruption.1551811889
Directory /workspace/279.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3185170771
Short name T2870
Test name
Test status
Simulation time 45681604 ps
CPU time 0.78 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207420 kb
Host smart-97589a7a-482c-484b-a7f0-30f90b5f7bd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3185170771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3185170771
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.2499715415
Short name T674
Test name
Test status
Simulation time 11197655819 ps
CPU time 15.48 seconds
Started Aug 17 06:07:55 PM PDT 24
Finished Aug 17 06:08:11 PM PDT 24
Peak memory 207800 kb
Host smart-309ed335-dbf3-49a7-95bd-d15cdaf7dea7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499715415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.2499715415
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1460409298
Short name T2344
Test name
Test status
Simulation time 18318968913 ps
CPU time 27.08 seconds
Started Aug 17 06:07:59 PM PDT 24
Finished Aug 17 06:08:26 PM PDT 24
Peak memory 207752 kb
Host smart-514b3781-b7ca-423b-9ab7-a955363b0362
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460409298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1460409298
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2378359391
Short name T3638
Test name
Test status
Simulation time 28588753544 ps
CPU time 36.19 seconds
Started Aug 17 06:07:53 PM PDT 24
Finished Aug 17 06:08:30 PM PDT 24
Peak memory 207700 kb
Host smart-c59395f2-7975-4d47-af70-4fff0969d218
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378359391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.2378359391
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3488586024
Short name T1546
Test name
Test status
Simulation time 184776000 ps
CPU time 0.9 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:07:55 PM PDT 24
Peak memory 207420 kb
Host smart-b793f345-bf74-483c-a8c5-afa6ce3de7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34885
86024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3488586024
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1162953586
Short name T2947
Test name
Test status
Simulation time 141712650 ps
CPU time 0.89 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 207460 kb
Host smart-47ba0cf5-3039-43cd-8de9-46a9bca009fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11629
53586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1162953586
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1727472521
Short name T2808
Test name
Test status
Simulation time 169123284 ps
CPU time 0.9 seconds
Started Aug 17 06:07:52 PM PDT 24
Finished Aug 17 06:07:53 PM PDT 24
Peak memory 207504 kb
Host smart-779ab587-9eda-4f23-a142-2c1485ae69cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17274
72521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1727472521
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.9027088
Short name T2640
Test name
Test status
Simulation time 1065675025 ps
CPU time 3 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:07:57 PM PDT 24
Peak memory 207796 kb
Host smart-96052632-e19e-423d-aad7-80cbf69ac56d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=9027088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.9027088
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1844250613
Short name T2339
Test name
Test status
Simulation time 19725063570 ps
CPU time 33.7 seconds
Started Aug 17 06:07:56 PM PDT 24
Finished Aug 17 06:08:30 PM PDT 24
Peak memory 207780 kb
Host smart-f0b9c997-bebd-4fb2-9169-7b78fc2cafa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18442
50613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1844250613
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.2549009325
Short name T1716
Test name
Test status
Simulation time 647606941 ps
CPU time 11.79 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207648 kb
Host smart-66712c82-d408-4f90-8cc5-9586aad34914
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549009325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.2549009325
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.2443796838
Short name T1767
Test name
Test status
Simulation time 868504247 ps
CPU time 2.04 seconds
Started Aug 17 06:07:59 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 207516 kb
Host smart-1abf6059-f2b7-4754-adee-a4c79f4bf1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24437
96838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.2443796838
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.670056745
Short name T3603
Test name
Test status
Simulation time 162128968 ps
CPU time 0.86 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:07:55 PM PDT 24
Peak memory 207532 kb
Host smart-b34db87c-91f9-4907-ab5c-32f78f49ad3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67005
6745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.670056745
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3021609951
Short name T835
Test name
Test status
Simulation time 59500161 ps
CPU time 0.71 seconds
Started Aug 17 06:07:55 PM PDT 24
Finished Aug 17 06:07:56 PM PDT 24
Peak memory 207416 kb
Host smart-6ea654f8-67aa-4120-b2f5-fcde4a67eac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
09951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3021609951
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1217363119
Short name T2229
Test name
Test status
Simulation time 959178385 ps
CPU time 2.58 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:05 PM PDT 24
Peak memory 207776 kb
Host smart-27df5bdd-a8a8-4f50-91af-8a7b4a121eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12173
63119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1217363119
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3924811186
Short name T722
Test name
Test status
Simulation time 185700277 ps
CPU time 2.3 seconds
Started Aug 17 06:07:51 PM PDT 24
Finished Aug 17 06:07:54 PM PDT 24
Peak memory 207668 kb
Host smart-405b39e1-0261-4969-af42-93fd923ec089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39248
11186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3924811186
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1139809201
Short name T920
Test name
Test status
Simulation time 252539589 ps
CPU time 1.25 seconds
Started Aug 17 06:07:59 PM PDT 24
Finished Aug 17 06:08:00 PM PDT 24
Peak memory 215868 kb
Host smart-dc65abce-696d-4124-bbb3-80eb05c035ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1139809201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1139809201
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2451242981
Short name T2719
Test name
Test status
Simulation time 142919159 ps
CPU time 0.84 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207432 kb
Host smart-29cffe52-3fde-42f5-a017-9b1342f64ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24512
42981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2451242981
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3348111796
Short name T1164
Test name
Test status
Simulation time 177848406 ps
CPU time 1 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207460 kb
Host smart-e9f457e1-84d0-47d5-8e29-5d32ea026c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33481
11796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3348111796
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.20360483
Short name T2784
Test name
Test status
Simulation time 3485215840 ps
CPU time 27.04 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:28 PM PDT 24
Peak memory 224040 kb
Host smart-26ceb34f-138d-4885-a827-7d5ce40b4f5b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=20360483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.20360483
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.1159410320
Short name T2765
Test name
Test status
Simulation time 12548552645 ps
CPU time 78.5 seconds
Started Aug 17 06:07:57 PM PDT 24
Finished Aug 17 06:09:16 PM PDT 24
Peak memory 207800 kb
Host smart-fa25abab-4069-4f34-8866-dc9f2668a188
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1159410320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.1159410320
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1646002419
Short name T2705
Test name
Test status
Simulation time 168065681 ps
CPU time 0.97 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207548 kb
Host smart-71a6b60c-b301-4668-b3d4-2f61b64ae2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16460
02419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1646002419
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.528992893
Short name T2878
Test name
Test status
Simulation time 24220315355 ps
CPU time 37.11 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:40 PM PDT 24
Peak memory 207648 kb
Host smart-af6488d0-94b1-4415-ad81-fa7623d7d957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52899
2893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.528992893
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.4171935438
Short name T35
Test name
Test status
Simulation time 9231810509 ps
CPU time 11.29 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:11 PM PDT 24
Peak memory 207828 kb
Host smart-1015dc11-aea2-4174-95e4-2023092dce6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41719
35438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.4171935438
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2168040822
Short name T1850
Test name
Test status
Simulation time 2412673681 ps
CPU time 23.38 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:26 PM PDT 24
Peak memory 224096 kb
Host smart-f6133e18-e80a-49d1-ae04-8422a415cef5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2168040822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2168040822
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2906744796
Short name T1901
Test name
Test status
Simulation time 3028536564 ps
CPU time 31.9 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:35 PM PDT 24
Peak memory 217696 kb
Host smart-6e03862b-bcc2-4d85-8182-437d2124d1d5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2906744796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2906744796
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1261194949
Short name T2681
Test name
Test status
Simulation time 297261807 ps
CPU time 1.16 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207484 kb
Host smart-f586c9d9-a61a-4653-901d-b35e69ff544b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1261194949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1261194949
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1959593749
Short name T878
Test name
Test status
Simulation time 190097363 ps
CPU time 0.95 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 207456 kb
Host smart-fd973df2-84af-445e-a7cd-130610c1de37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19595
93749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1959593749
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1738981634
Short name T2351
Test name
Test status
Simulation time 2055075656 ps
CPU time 16.22 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:20 PM PDT 24
Peak memory 217484 kb
Host smart-c4306cd4-749d-4674-b524-14d0887876d5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1738981634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1738981634
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2758317032
Short name T713
Test name
Test status
Simulation time 162670692 ps
CPU time 0.9 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 207464 kb
Host smart-541bc4fd-8c58-4826-ad00-30a399cb9ea0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2758317032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2758317032
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2497170116
Short name T958
Test name
Test status
Simulation time 143498831 ps
CPU time 0.84 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207464 kb
Host smart-6ad5a3ee-efe6-40af-a7e1-b9ae9e64b380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24971
70116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2497170116
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3877665031
Short name T3511
Test name
Test status
Simulation time 231536652 ps
CPU time 0.98 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207492 kb
Host smart-2cfc1d27-cb8a-4e79-adf2-caa0c3bdd2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38776
65031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3877665031
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3109718138
Short name T2264
Test name
Test status
Simulation time 200947314 ps
CPU time 1.1 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 207408 kb
Host smart-f699f4aa-61bd-40e6-a1e5-ec0f0bd77ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31097
18138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3109718138
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3081523203
Short name T2052
Test name
Test status
Simulation time 213672014 ps
CPU time 0.97 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:07 PM PDT 24
Peak memory 207484 kb
Host smart-0b451568-2a60-4188-a2b8-db3af28e55e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30815
23203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3081523203
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1907196199
Short name T1941
Test name
Test status
Simulation time 190081616 ps
CPU time 0.95 seconds
Started Aug 17 06:08:04 PM PDT 24
Finished Aug 17 06:08:05 PM PDT 24
Peak memory 207536 kb
Host smart-d795df5e-d560-4595-88b7-8281b0ce0d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19071
96199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1907196199
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2471928498
Short name T2193
Test name
Test status
Simulation time 168873136 ps
CPU time 0.92 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 207476 kb
Host smart-65a17770-ef4e-4b35-a3aa-77857bd46141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24719
28498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2471928498
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.2665455137
Short name T756
Test name
Test status
Simulation time 258984019 ps
CPU time 1.1 seconds
Started Aug 17 06:07:59 PM PDT 24
Finished Aug 17 06:08:00 PM PDT 24
Peak memory 207568 kb
Host smart-e1383141-97e3-45b5-8385-a313c23ebe74
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2665455137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.2665455137
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.577467412
Short name T638
Test name
Test status
Simulation time 151920746 ps
CPU time 0.84 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 207480 kb
Host smart-5ba16b92-68db-4e01-b557-2a5a64006147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57746
7412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.577467412
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2621195543
Short name T2405
Test name
Test status
Simulation time 69673431 ps
CPU time 0.73 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:25 PM PDT 24
Peak memory 207472 kb
Host smart-da8d0c26-2790-4880-88b2-44ca4349e230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26211
95543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2621195543
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1495778664
Short name T1587
Test name
Test status
Simulation time 18872171308 ps
CPU time 45.52 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:47 PM PDT 24
Peak memory 215864 kb
Host smart-7b965b06-d046-4608-832c-23f03ad8faaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14957
78664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1495778664
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2730476867
Short name T2742
Test name
Test status
Simulation time 162776872 ps
CPU time 0.93 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207544 kb
Host smart-d418b9b5-f1e3-4783-b230-fbadf83ebdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
76867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2730476867
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3598496723
Short name T2610
Test name
Test status
Simulation time 191648613 ps
CPU time 0.98 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207408 kb
Host smart-b736f833-25bd-47e1-8e79-290d76e81e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35984
96723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3598496723
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.192398199
Short name T310
Test name
Test status
Simulation time 259563745 ps
CPU time 1.03 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207472 kb
Host smart-75b7d7d2-922d-464f-9e82-18baa1a5a2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19239
8199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.192398199
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1298068345
Short name T2468
Test name
Test status
Simulation time 178268579 ps
CPU time 0.91 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 207468 kb
Host smart-a4c29e41-03d0-4484-a91b-c5ac3cbd291d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12980
68345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1298068345
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3971776803
Short name T772
Test name
Test status
Simulation time 177917863 ps
CPU time 0.87 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 207472 kb
Host smart-b9e7243d-396c-477a-8b5a-8821946ea7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39717
76803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3971776803
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_rx_full.2678081275
Short name T2638
Test name
Test status
Simulation time 359427529 ps
CPU time 1.19 seconds
Started Aug 17 06:08:04 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207416 kb
Host smart-e7c17e08-af56-4261-9a89-5105ccd15ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26780
81275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.2678081275
Directory /workspace/28.usbdev_rx_full/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2606416162
Short name T2911
Test name
Test status
Simulation time 154141055 ps
CPU time 0.87 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207528 kb
Host smart-75aaf272-8a1d-44b3-9670-8a0f482b8c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26064
16162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2606416162
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1899720903
Short name T1322
Test name
Test status
Simulation time 168302319 ps
CPU time 0.94 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 207436 kb
Host smart-a8521fb1-df31-4721-b455-e860316587f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18997
20903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1899720903
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3056746300
Short name T1392
Test name
Test status
Simulation time 222240275 ps
CPU time 1.02 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 206404 kb
Host smart-3d47b1c0-8a63-40df-80cb-9eba3caf24c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30567
46300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3056746300
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.3526142053
Short name T1840
Test name
Test status
Simulation time 1888004249 ps
CPU time 14.01 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:22 PM PDT 24
Peak memory 217396 kb
Host smart-d91150be-8f5f-4c68-8ebb-96a66a2eff9a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3526142053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.3526142053
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2149213604
Short name T2217
Test name
Test status
Simulation time 159839821 ps
CPU time 0.89 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 207432 kb
Host smart-da388c16-6226-45a2-990a-b0b6d34780c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21492
13604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2149213604
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3830847802
Short name T1569
Test name
Test status
Simulation time 223609261 ps
CPU time 0.96 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207544 kb
Host smart-a8361647-0f35-4083-9104-a46fe734ed5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38308
47802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3830847802
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.4184465500
Short name T25
Test name
Test status
Simulation time 724583085 ps
CPU time 1.9 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207460 kb
Host smart-63703bb2-bbef-493c-ba41-6c5c8c1ccc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41844
65500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.4184465500
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3111329172
Short name T1624
Test name
Test status
Simulation time 1773598398 ps
CPU time 48.5 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:54 PM PDT 24
Peak memory 224052 kb
Host smart-80370b85-8091-435c-944f-2d9f17905cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31113
29172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3111329172
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.377817280
Short name T758
Test name
Test status
Simulation time 859907189 ps
CPU time 19.5 seconds
Started Aug 17 06:07:54 PM PDT 24
Finished Aug 17 06:08:13 PM PDT 24
Peak memory 207568 kb
Host smart-f879f8f8-4fa5-4a16-8193-fea568652b8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377817280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_host
_handshake.377817280
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_tx_rx_disruption.2109277614
Short name T2134
Test name
Test status
Simulation time 478597626 ps
CPU time 1.6 seconds
Started Aug 17 06:08:04 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207496 kb
Host smart-ffbce6f3-aaaf-425b-adb5-a2f6b496ac2f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109277614 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.usbdev_tx_rx_disruption.2109277614
Directory /workspace/28.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/280.usbdev_tx_rx_disruption.2393450288
Short name T2096
Test name
Test status
Simulation time 585540131 ps
CPU time 1.58 seconds
Started Aug 17 06:11:57 PM PDT 24
Finished Aug 17 06:11:59 PM PDT 24
Peak memory 207540 kb
Host smart-4e248d4e-fb7c-422f-9745-e3a5dfcaa3d2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393450288 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.usbdev_tx_rx_disruption.2393450288
Directory /workspace/280.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/281.usbdev_tx_rx_disruption.3587494087
Short name T2007
Test name
Test status
Simulation time 503467897 ps
CPU time 1.47 seconds
Started Aug 17 06:11:55 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207584 kb
Host smart-01747a4b-5471-4d0d-9cf8-6d4de951df3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587494087 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.usbdev_tx_rx_disruption.3587494087
Directory /workspace/281.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/282.usbdev_tx_rx_disruption.3216604397
Short name T3192
Test name
Test status
Simulation time 720629642 ps
CPU time 1.91 seconds
Started Aug 17 06:12:22 PM PDT 24
Finished Aug 17 06:12:24 PM PDT 24
Peak memory 207784 kb
Host smart-b33f67a6-2f99-484f-be37-603ec622c310
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216604397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.usbdev_tx_rx_disruption.3216604397
Directory /workspace/282.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/283.usbdev_tx_rx_disruption.831671161
Short name T201
Test name
Test status
Simulation time 581713243 ps
CPU time 1.81 seconds
Started Aug 17 06:12:15 PM PDT 24
Finished Aug 17 06:12:17 PM PDT 24
Peak memory 207528 kb
Host smart-ec5381f2-84da-41e5-9d75-23873922b89e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831671161 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 283.usbdev_tx_rx_disruption.831671161
Directory /workspace/283.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/284.usbdev_tx_rx_disruption.1613404637
Short name T3123
Test name
Test status
Simulation time 617361063 ps
CPU time 1.6 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207544 kb
Host smart-5a3c7cb4-045d-4ffa-979a-1a5ad7c529f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613404637 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.usbdev_tx_rx_disruption.1613404637
Directory /workspace/284.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/285.usbdev_tx_rx_disruption.915346873
Short name T1025
Test name
Test status
Simulation time 668287889 ps
CPU time 1.79 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207572 kb
Host smart-bcc203b6-e889-44eb-8b94-40b9edf16373
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915346873 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 285.usbdev_tx_rx_disruption.915346873
Directory /workspace/285.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/286.usbdev_tx_rx_disruption.212924170
Short name T3271
Test name
Test status
Simulation time 603330958 ps
CPU time 1.62 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207784 kb
Host smart-a488056b-884e-4232-9d92-39976b53484a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212924170 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 286.usbdev_tx_rx_disruption.212924170
Directory /workspace/286.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/287.usbdev_tx_rx_disruption.342080087
Short name T3580
Test name
Test status
Simulation time 600664239 ps
CPU time 1.54 seconds
Started Aug 17 06:12:35 PM PDT 24
Finished Aug 17 06:12:36 PM PDT 24
Peak memory 207516 kb
Host smart-ff4dd4b7-70ae-4c1f-8bb9-126d5f649e8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342080087 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 287.usbdev_tx_rx_disruption.342080087
Directory /workspace/287.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/288.usbdev_tx_rx_disruption.158565847
Short name T1673
Test name
Test status
Simulation time 482462583 ps
CPU time 1.57 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207500 kb
Host smart-a9a6c061-98f8-42b5-a062-c0aab514d632
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158565847 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 288.usbdev_tx_rx_disruption.158565847
Directory /workspace/288.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/289.usbdev_tx_rx_disruption.303691795
Short name T2288
Test name
Test status
Simulation time 570924631 ps
CPU time 1.62 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207548 kb
Host smart-490649a1-2b04-4dc5-9b5a-accbca985129
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303691795 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 289.usbdev_tx_rx_disruption.303691795
Directory /workspace/289.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3281460928
Short name T222
Test name
Test status
Simulation time 31296387 ps
CPU time 0.65 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:05 PM PDT 24
Peak memory 207376 kb
Host smart-c148b033-da16-46d7-abf6-8498741b55be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3281460928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3281460928
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.841271596
Short name T2268
Test name
Test status
Simulation time 9169320793 ps
CPU time 11.93 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:15 PM PDT 24
Peak memory 207788 kb
Host smart-2e541e64-93ab-459f-854c-940e8aef13cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841271596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_disconnect.841271596
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2419214478
Short name T709
Test name
Test status
Simulation time 20093508046 ps
CPU time 25.51 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:31 PM PDT 24
Peak memory 206708 kb
Host smart-7e3d7c68-5372-4e5e-a675-6e655d6ad919
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419214478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2419214478
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.284010340
Short name T12
Test name
Test status
Simulation time 25303736108 ps
CPU time 30.67 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:31 PM PDT 24
Peak memory 215984 kb
Host smart-02ead5b2-3ee0-4d73-81d6-17f30b70b66d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284010340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_resume.284010340
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1714188025
Short name T1250
Test name
Test status
Simulation time 169693389 ps
CPU time 0.99 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207452 kb
Host smart-5dff31cb-2d15-4523-9868-a26464cc5855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17141
88025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1714188025
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3726454605
Short name T2450
Test name
Test status
Simulation time 155635789 ps
CPU time 0.86 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 207560 kb
Host smart-4c0a36ea-f098-4dc3-acfb-4107b25bbdca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37264
54605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3726454605
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.2116457200
Short name T2429
Test name
Test status
Simulation time 421352314 ps
CPU time 1.52 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207476 kb
Host smart-8cc3b835-ed94-48c6-b436-7841e929dc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21164
57200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.2116457200
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.196166241
Short name T2087
Test name
Test status
Simulation time 527726358 ps
CPU time 1.69 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207560 kb
Host smart-5a42884e-a4bf-4f89-b8b8-00c16e3df0c2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=196166241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.196166241
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.2592577700
Short name T1449
Test name
Test status
Simulation time 45268045764 ps
CPU time 86.04 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:09:30 PM PDT 24
Peak memory 207760 kb
Host smart-2459155f-4bc5-4032-af83-81709059341d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25925
77700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.2592577700
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.1191266476
Short name T720
Test name
Test status
Simulation time 226818129 ps
CPU time 1.17 seconds
Started Aug 17 06:08:00 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 207496 kb
Host smart-f949269a-ea26-4e36-adfe-1f472ea088e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191266476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.1191266476
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1229035290
Short name T2755
Test name
Test status
Simulation time 704268015 ps
CPU time 1.88 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:05 PM PDT 24
Peak memory 207500 kb
Host smart-ed079bd0-9aca-4739-a928-ab310f0313f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12290
35290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1229035290
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3637972395
Short name T1653
Test name
Test status
Simulation time 180807919 ps
CPU time 0.89 seconds
Started Aug 17 06:07:58 PM PDT 24
Finished Aug 17 06:07:59 PM PDT 24
Peak memory 207528 kb
Host smart-c4d79fc6-53e2-4688-aaf7-f9627b692d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36379
72395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3637972395
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3050462010
Short name T2333
Test name
Test status
Simulation time 46859719 ps
CPU time 0.74 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207420 kb
Host smart-0bc35cab-0aa4-4429-ac4f-77cd25623651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30504
62010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3050462010
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.324227232
Short name T1287
Test name
Test status
Simulation time 891769785 ps
CPU time 2.6 seconds
Started Aug 17 06:08:16 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 207744 kb
Host smart-c533b46e-f634-4137-b453-ad57edfedd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32422
7232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.324227232
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_types.3028578266
Short name T775
Test name
Test status
Simulation time 158894092 ps
CPU time 0.89 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 207520 kb
Host smart-744158ab-4ad2-499c-af99-e3058a0f29d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3028578266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.3028578266
Directory /workspace/29.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1657893427
Short name T1849
Test name
Test status
Simulation time 298003255 ps
CPU time 2.18 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:05 PM PDT 24
Peak memory 207652 kb
Host smart-4442568b-9564-4dc9-8111-4d42b48ac767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16578
93427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1657893427
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3422102253
Short name T1676
Test name
Test status
Simulation time 270195435 ps
CPU time 1.28 seconds
Started Aug 17 06:08:04 PM PDT 24
Finished Aug 17 06:08:05 PM PDT 24
Peak memory 216812 kb
Host smart-ff678392-dcb6-46dc-9426-484f32552d59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3422102253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3422102253
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1025029906
Short name T579
Test name
Test status
Simulation time 151544829 ps
CPU time 0.88 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207428 kb
Host smart-09c2c9e1-bfb4-4bc7-b7a6-f55b2e5744d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10250
29906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1025029906
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.4129988857
Short name T2398
Test name
Test status
Simulation time 153988182 ps
CPU time 0.88 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207460 kb
Host smart-8fe670df-8151-4d8b-9920-bce8479b44fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41299
88857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.4129988857
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.1674652900
Short name T2530
Test name
Test status
Simulation time 4858773775 ps
CPU time 36.42 seconds
Started Aug 17 06:08:04 PM PDT 24
Finished Aug 17 06:08:41 PM PDT 24
Peak memory 224068 kb
Host smart-efa630cf-94da-49e9-b6ed-a4745626fab1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1674652900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.1674652900
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.1148118189
Short name T2147
Test name
Test status
Simulation time 14785645245 ps
CPU time 104.13 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207688 kb
Host smart-a7ba641a-4cd6-4970-8e48-6b0e10691ce1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1148118189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1148118189
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1427769439
Short name T1074
Test name
Test status
Simulation time 161502289 ps
CPU time 0.92 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:03 PM PDT 24
Peak memory 207488 kb
Host smart-423e9b67-d407-4f89-b9a0-08e8c1ec101f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14277
69439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1427769439
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3502999391
Short name T3199
Test name
Test status
Simulation time 29723648613 ps
CPU time 44.94 seconds
Started Aug 17 06:08:15 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207768 kb
Host smart-3658e00d-e9c3-4121-9ecb-293812aa674b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35029
99391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3502999391
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.4228000530
Short name T1333
Test name
Test status
Simulation time 11096960208 ps
CPU time 13.61 seconds
Started Aug 17 06:07:59 PM PDT 24
Finished Aug 17 06:08:13 PM PDT 24
Peak memory 207808 kb
Host smart-d21b42c1-40eb-43c6-b91b-5ea7766d9a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42280
00530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.4228000530
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2920373500
Short name T2529
Test name
Test status
Simulation time 4575968448 ps
CPU time 45.7 seconds
Started Aug 17 06:08:16 PM PDT 24
Finished Aug 17 06:09:02 PM PDT 24
Peak memory 215560 kb
Host smart-e3b71fa1-1842-4ca2-8af9-73803dfe21c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2920373500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2920373500
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.1088153081
Short name T2318
Test name
Test status
Simulation time 2322355984 ps
CPU time 22.38 seconds
Started Aug 17 06:08:16 PM PDT 24
Finished Aug 17 06:08:39 PM PDT 24
Peak memory 217188 kb
Host smart-e8ac34bd-fbbe-4eb7-80d0-db761b050a31
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1088153081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.1088153081
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.259914563
Short name T1399
Test name
Test status
Simulation time 249757953 ps
CPU time 1.1 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207484 kb
Host smart-ad315e40-3a02-4479-a44c-17e93b3a8cb2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=259914563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.259914563
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2470676547
Short name T1552
Test name
Test status
Simulation time 191943445 ps
CPU time 0.94 seconds
Started Aug 17 06:08:15 PM PDT 24
Finished Aug 17 06:08:17 PM PDT 24
Peak memory 207428 kb
Host smart-b8459a4c-0773-4092-8026-46ed861494e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24706
76547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2470676547
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3249623821
Short name T2138
Test name
Test status
Simulation time 2203601023 ps
CPU time 23.89 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:26 PM PDT 24
Peak memory 215912 kb
Host smart-3622b9e9-966a-453a-88a9-fab8fe270290
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3249623821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3249623821
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1236612813
Short name T2761
Test name
Test status
Simulation time 154395085 ps
CPU time 0.88 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207476 kb
Host smart-2333f7cc-2164-4149-82f5-482f26dc4750
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1236612813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1236612813
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.816843536
Short name T2623
Test name
Test status
Simulation time 160719153 ps
CPU time 0.84 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 207684 kb
Host smart-d1d7dd2c-a7ab-4cf2-bf87-7d9b60d61195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81684
3536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.816843536
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1184594352
Short name T2109
Test name
Test status
Simulation time 219675677 ps
CPU time 0.99 seconds
Started Aug 17 06:08:02 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207368 kb
Host smart-557c22bc-9fd2-469b-80a7-8c0234f3d5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11845
94352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1184594352
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1553011626
Short name T2132
Test name
Test status
Simulation time 165776840 ps
CPU time 0.95 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207448 kb
Host smart-3412512c-22c6-4c3c-8868-936ed2fc7c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15530
11626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1553011626
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1590890272
Short name T1827
Test name
Test status
Simulation time 236084888 ps
CPU time 0.97 seconds
Started Aug 17 06:08:16 PM PDT 24
Finished Aug 17 06:08:17 PM PDT 24
Peak memory 207432 kb
Host smart-901acd92-7e59-4175-bffb-132f327b9f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
90272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1590890272
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3876533141
Short name T778
Test name
Test status
Simulation time 233244746 ps
CPU time 0.93 seconds
Started Aug 17 06:08:06 PM PDT 24
Finished Aug 17 06:08:07 PM PDT 24
Peak memory 207560 kb
Host smart-cdd213b8-3f52-42be-8167-01c7f766f1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38765
33141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3876533141
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1900646041
Short name T1388
Test name
Test status
Simulation time 168808162 ps
CPU time 0.89 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:25 PM PDT 24
Peak memory 207508 kb
Host smart-1aeb4732-e009-412f-abf1-93193c7e0c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19006
46041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1900646041
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2793163577
Short name T665
Test name
Test status
Simulation time 187170501 ps
CPU time 0.98 seconds
Started Aug 17 06:08:11 PM PDT 24
Finished Aug 17 06:08:12 PM PDT 24
Peak memory 207532 kb
Host smart-25e11f68-3c18-4973-ae0b-c22403f6d93c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2793163577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2793163577
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.764631328
Short name T2959
Test name
Test status
Simulation time 150099532 ps
CPU time 0.8 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:25 PM PDT 24
Peak memory 207432 kb
Host smart-3b4925de-4bff-4200-b7f6-af577a0f74db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76463
1328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.764631328
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1415307393
Short name T1372
Test name
Test status
Simulation time 62744915 ps
CPU time 0.73 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207496 kb
Host smart-be2cc6c1-f789-4cc8-9fd3-7c8276a70c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14153
07393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1415307393
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1079677863
Short name T2786
Test name
Test status
Simulation time 21585921638 ps
CPU time 57.17 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:09:03 PM PDT 24
Peak memory 215936 kb
Host smart-d758d7d2-f17f-4200-85cb-745c052a607e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10796
77863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1079677863
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1500683542
Short name T2581
Test name
Test status
Simulation time 156637137 ps
CPU time 0.89 seconds
Started Aug 17 06:08:03 PM PDT 24
Finished Aug 17 06:08:04 PM PDT 24
Peak memory 207544 kb
Host smart-3869d24b-946f-4dd9-ba89-b0c8ccfdf468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15006
83542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1500683542
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2587920045
Short name T686
Test name
Test status
Simulation time 172644222 ps
CPU time 0.9 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207476 kb
Host smart-3698ac51-4261-4c23-8eea-5d365be120a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25879
20045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2587920045
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2432065873
Short name T1498
Test name
Test status
Simulation time 238018920 ps
CPU time 1.02 seconds
Started Aug 17 06:08:04 PM PDT 24
Finished Aug 17 06:08:05 PM PDT 24
Peak memory 207460 kb
Host smart-c7c4c7b4-62ca-4f2d-866d-a9ba33fa2155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24320
65873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2432065873
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.762268231
Short name T2758
Test name
Test status
Simulation time 175563678 ps
CPU time 0.93 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207488 kb
Host smart-d25be489-b057-4963-8ece-9665661753fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76226
8231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.762268231
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.324094044
Short name T2341
Test name
Test status
Simulation time 161292478 ps
CPU time 0.89 seconds
Started Aug 17 06:08:08 PM PDT 24
Finished Aug 17 06:08:09 PM PDT 24
Peak memory 207444 kb
Host smart-f3913252-f396-4482-8103-672b0c98c5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32409
4044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.324094044
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_rx_full.2604925841
Short name T3533
Test name
Test status
Simulation time 320363243 ps
CPU time 1.21 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207456 kb
Host smart-aed55522-73cb-4d24-a44f-1f696a94118b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26049
25841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.2604925841
Directory /workspace/29.usbdev_rx_full/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3252873001
Short name T1597
Test name
Test status
Simulation time 154712423 ps
CPU time 0.88 seconds
Started Aug 17 06:08:01 PM PDT 24
Finished Aug 17 06:08:02 PM PDT 24
Peak memory 207728 kb
Host smart-69d529c6-be88-46ed-ad44-78e4a0a83b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32528
73001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3252873001
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.434999372
Short name T1281
Test name
Test status
Simulation time 209310440 ps
CPU time 0.87 seconds
Started Aug 17 06:08:12 PM PDT 24
Finished Aug 17 06:08:13 PM PDT 24
Peak memory 207564 kb
Host smart-20df7296-9e37-4f7f-a9ab-9ec33571e3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43499
9372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.434999372
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1554902375
Short name T2635
Test name
Test status
Simulation time 194285408 ps
CPU time 0.91 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207456 kb
Host smart-8c126548-3f88-42b7-93bd-26faf6c8d57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15549
02375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1554902375
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3143193095
Short name T610
Test name
Test status
Simulation time 2547195992 ps
CPU time 70.38 seconds
Started Aug 17 06:08:06 PM PDT 24
Finished Aug 17 06:09:16 PM PDT 24
Peak memory 217716 kb
Host smart-bcacdda8-8c58-4754-8f62-f03e59ee921e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3143193095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3143193095
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1962586017
Short name T1455
Test name
Test status
Simulation time 226851770 ps
CPU time 1 seconds
Started Aug 17 06:08:06 PM PDT 24
Finished Aug 17 06:08:07 PM PDT 24
Peak memory 207484 kb
Host smart-d20909ee-cfb9-4da0-b120-0fa37885d2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19625
86017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1962586017
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3114294692
Short name T700
Test name
Test status
Simulation time 157553156 ps
CPU time 0.87 seconds
Started Aug 17 06:08:25 PM PDT 24
Finished Aug 17 06:08:26 PM PDT 24
Peak memory 207540 kb
Host smart-16f36ed7-2d70-4898-b9c7-9f9d27afca81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31142
94692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3114294692
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2166473668
Short name T2566
Test name
Test status
Simulation time 919274107 ps
CPU time 2.18 seconds
Started Aug 17 06:08:11 PM PDT 24
Finished Aug 17 06:08:13 PM PDT 24
Peak memory 207716 kb
Host smart-5df1058b-d30f-4210-a8b4-8e844fb675d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21664
73668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2166473668
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.368535600
Short name T352
Test name
Test status
Simulation time 3798374278 ps
CPU time 40.29 seconds
Started Aug 17 06:08:26 PM PDT 24
Finished Aug 17 06:09:06 PM PDT 24
Peak memory 215960 kb
Host smart-d0b2a406-0485-4f4c-996b-3f3e4e4baccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36853
5600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.368535600
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.4081009364
Short name T3330
Test name
Test status
Simulation time 416536182 ps
CPU time 7.69 seconds
Started Aug 17 06:08:04 PM PDT 24
Finished Aug 17 06:08:12 PM PDT 24
Peak memory 207636 kb
Host smart-e38b2f62-cc4d-4cf3-898f-aa71732578db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081009364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.4081009364
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_tx_rx_disruption.1458826476
Short name T2281
Test name
Test status
Simulation time 572468636 ps
CPU time 1.55 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:26 PM PDT 24
Peak memory 207544 kb
Host smart-7df5e482-a9ab-41d5-9ff9-ac9358d55ebd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458826476 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.usbdev_tx_rx_disruption.1458826476
Directory /workspace/29.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/290.usbdev_tx_rx_disruption.516938640
Short name T1768
Test name
Test status
Simulation time 617191306 ps
CPU time 1.72 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207500 kb
Host smart-c618c53a-fb67-4919-87d4-77b660d16f83
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516938640 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 290.usbdev_tx_rx_disruption.516938640
Directory /workspace/290.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/291.usbdev_tx_rx_disruption.1849163602
Short name T726
Test name
Test status
Simulation time 643295443 ps
CPU time 1.8 seconds
Started Aug 17 06:12:05 PM PDT 24
Finished Aug 17 06:12:07 PM PDT 24
Peak memory 207572 kb
Host smart-3fa836fc-509f-4a24-9589-7535d33e2e27
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849163602 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.usbdev_tx_rx_disruption.1849163602
Directory /workspace/291.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/292.usbdev_tx_rx_disruption.2112998014
Short name T2953
Test name
Test status
Simulation time 498102271 ps
CPU time 1.47 seconds
Started Aug 17 06:11:56 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207584 kb
Host smart-39f6a866-3ee3-4931-8241-38994d476f8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112998014 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.usbdev_tx_rx_disruption.2112998014
Directory /workspace/292.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/293.usbdev_tx_rx_disruption.1246218058
Short name T2696
Test name
Test status
Simulation time 515620504 ps
CPU time 1.59 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207516 kb
Host smart-3df03139-c1c5-4471-a757-fbc4eb626570
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246218058 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.usbdev_tx_rx_disruption.1246218058
Directory /workspace/293.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/294.usbdev_tx_rx_disruption.30523747
Short name T1756
Test name
Test status
Simulation time 684719133 ps
CPU time 1.76 seconds
Started Aug 17 06:12:04 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207500 kb
Host smart-79b13bc4-c233-4749-9238-e4d796dc7815
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30523747 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 294.usbdev_tx_rx_disruption.30523747
Directory /workspace/294.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/295.usbdev_tx_rx_disruption.4086188500
Short name T965
Test name
Test status
Simulation time 478150703 ps
CPU time 1.53 seconds
Started Aug 17 06:12:15 PM PDT 24
Finished Aug 17 06:12:17 PM PDT 24
Peak memory 207784 kb
Host smart-92d0eed7-1ebf-4a23-ab23-9d7deaf4754f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086188500 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.usbdev_tx_rx_disruption.4086188500
Directory /workspace/295.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/296.usbdev_tx_rx_disruption.1837778420
Short name T3109
Test name
Test status
Simulation time 549614590 ps
CPU time 1.89 seconds
Started Aug 17 06:12:11 PM PDT 24
Finished Aug 17 06:12:13 PM PDT 24
Peak memory 207548 kb
Host smart-70f3738d-e0a1-4e4b-a5c4-d4a3532d578c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837778420 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.usbdev_tx_rx_disruption.1837778420
Directory /workspace/296.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/297.usbdev_tx_rx_disruption.909923
Short name T3126
Test name
Test status
Simulation time 509252700 ps
CPU time 1.58 seconds
Started Aug 17 06:12:16 PM PDT 24
Finished Aug 17 06:12:18 PM PDT 24
Peak memory 207508 kb
Host smart-649d1add-7e26-4456-8955-b75a126a8041
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909923 -assert nopostproc +UVM_TESTNA
ME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 297.usbdev_tx_rx_disruption.909923
Directory /workspace/297.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/298.usbdev_tx_rx_disruption.1706851828
Short name T3306
Test name
Test status
Simulation time 580643188 ps
CPU time 1.63 seconds
Started Aug 17 06:12:05 PM PDT 24
Finished Aug 17 06:12:07 PM PDT 24
Peak memory 207548 kb
Host smart-cb6dd543-1c22-4a94-a18c-91ef0dd4b28c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706851828 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.usbdev_tx_rx_disruption.1706851828
Directory /workspace/298.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/299.usbdev_tx_rx_disruption.1234902670
Short name T972
Test name
Test status
Simulation time 592082128 ps
CPU time 1.95 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207548 kb
Host smart-3a4f0967-9db7-4594-8177-c782e9a8f4cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234902670 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.usbdev_tx_rx_disruption.1234902670
Directory /workspace/299.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.3415395498
Short name T3267
Test name
Test status
Simulation time 64475209 ps
CPU time 0.73 seconds
Started Aug 17 06:03:16 PM PDT 24
Finished Aug 17 06:03:17 PM PDT 24
Peak memory 207356 kb
Host smart-920fb7be-b434-4a1c-bcfd-d264ea0cc570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3415395498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3415395498
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1630876152
Short name T614
Test name
Test status
Simulation time 4890930837 ps
CPU time 7.09 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:08 PM PDT 24
Peak memory 215932 kb
Host smart-207b11c6-df4f-4ae9-80ca-c00d4f3b3c58
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630876152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.1630876152
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1406362083
Short name T3133
Test name
Test status
Simulation time 15156146667 ps
CPU time 18.19 seconds
Started Aug 17 06:03:04 PM PDT 24
Finished Aug 17 06:03:22 PM PDT 24
Peak memory 215984 kb
Host smart-d50578d8-aecd-41cf-87f0-418a43de6bb3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406362083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1406362083
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.168407437
Short name T2969
Test name
Test status
Simulation time 24720673035 ps
CPU time 32.34 seconds
Started Aug 17 06:02:59 PM PDT 24
Finished Aug 17 06:03:32 PM PDT 24
Peak memory 215984 kb
Host smart-8f4e5106-aea1-4cf5-a2c4-d51a4f4b030c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168407437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon
_wake_resume.168407437
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.915238416
Short name T1137
Test name
Test status
Simulation time 169811748 ps
CPU time 0.88 seconds
Started Aug 17 06:03:01 PM PDT 24
Finished Aug 17 06:03:02 PM PDT 24
Peak memory 207412 kb
Host smart-1f9fbf81-6b5d-412b-bd61-e2a5ff0eb2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91523
8416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.915238416
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3484248499
Short name T52
Test name
Test status
Simulation time 151542074 ps
CPU time 0.84 seconds
Started Aug 17 06:03:11 PM PDT 24
Finished Aug 17 06:03:12 PM PDT 24
Peak memory 207396 kb
Host smart-aa662733-d318-406a-8913-997338be8974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34842
48499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3484248499
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.225573513
Short name T57
Test name
Test status
Simulation time 142460052 ps
CPU time 0.83 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 207444 kb
Host smart-0c885155-9b2f-452e-8215-08357736a1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22557
3513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.225573513
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3713530606
Short name T825
Test name
Test status
Simulation time 147188567 ps
CPU time 0.89 seconds
Started Aug 17 06:03:07 PM PDT 24
Finished Aug 17 06:03:08 PM PDT 24
Peak memory 207552 kb
Host smart-12c7d981-f0a1-457a-874c-ada481288bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37135
30606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3713530606
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.180784891
Short name T768
Test name
Test status
Simulation time 627198294 ps
CPU time 2.01 seconds
Started Aug 17 06:03:12 PM PDT 24
Finished Aug 17 06:03:14 PM PDT 24
Peak memory 207472 kb
Host smart-6eac2d7c-5631-4f03-82c0-9a591989728d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18078
4891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.180784891
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2791628515
Short name T335
Test name
Test status
Simulation time 543984360 ps
CPU time 1.58 seconds
Started Aug 17 06:03:05 PM PDT 24
Finished Aug 17 06:03:07 PM PDT 24
Peak memory 207528 kb
Host smart-bd847b12-9010-42ef-b67a-32efe4c2d911
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2791628515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2791628515
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3016626327
Short name T2303
Test name
Test status
Simulation time 27019652244 ps
CPU time 45.7 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:54 PM PDT 24
Peak memory 207808 kb
Host smart-ce9fc4f8-0ed4-4a78-a8e0-2d7eb6b03d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30166
26327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3016626327
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.4186749302
Short name T1864
Test name
Test status
Simulation time 717334900 ps
CPU time 15.27 seconds
Started Aug 17 06:03:07 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 207748 kb
Host smart-0f6225b4-a1bb-4989-8845-ab13f81fee8a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186749302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.4186749302
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2184787977
Short name T860
Test name
Test status
Simulation time 758515900 ps
CPU time 1.76 seconds
Started Aug 17 06:03:13 PM PDT 24
Finished Aug 17 06:03:15 PM PDT 24
Peak memory 207520 kb
Host smart-0b832c7f-4f2d-4c1e-98f6-c6d142bde9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21847
87977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2184787977
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2257122488
Short name T980
Test name
Test status
Simulation time 144265018 ps
CPU time 0.87 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 207524 kb
Host smart-ae0fde14-4cf4-4f5b-a611-e9339adf0015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22571
22488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2257122488
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3085889773
Short name T1291
Test name
Test status
Simulation time 39415746 ps
CPU time 0.71 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 207336 kb
Host smart-c604196c-89ab-4f56-8c13-1ca553e0fad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30858
89773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3085889773
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.456122276
Short name T2714
Test name
Test status
Simulation time 846544417 ps
CPU time 2.19 seconds
Started Aug 17 06:03:12 PM PDT 24
Finished Aug 17 06:03:14 PM PDT 24
Peak memory 207672 kb
Host smart-17c33ac0-bb6b-40ab-98ea-fcbe55103298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45612
2276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.456122276
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_types.981456809
Short name T511
Test name
Test status
Simulation time 604116371 ps
CPU time 1.43 seconds
Started Aug 17 06:03:11 PM PDT 24
Finished Aug 17 06:03:13 PM PDT 24
Peak memory 207516 kb
Host smart-a8a2a8b0-e2e2-4c56-ade3-caca302d8060
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=981456809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.981456809
Directory /workspace/3.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1868501202
Short name T1014
Test name
Test status
Simulation time 353017522 ps
CPU time 2.49 seconds
Started Aug 17 06:03:12 PM PDT 24
Finished Aug 17 06:03:15 PM PDT 24
Peak memory 207588 kb
Host smart-49e8c7c8-bbe4-418c-bd60-d130407f0a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18685
01202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1868501202
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3025498092
Short name T1557
Test name
Test status
Simulation time 99154813681 ps
CPU time 152.52 seconds
Started Aug 17 06:03:06 PM PDT 24
Finished Aug 17 06:05:39 PM PDT 24
Peak memory 207804 kb
Host smart-38a67ceb-51d6-41f7-b6ba-bf30d0fe7ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025498092 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3025498092
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.2715673630
Short name T1293
Test name
Test status
Simulation time 101105375998 ps
CPU time 171.83 seconds
Started Aug 17 06:03:09 PM PDT 24
Finished Aug 17 06:06:01 PM PDT 24
Peak memory 207620 kb
Host smart-d94ed155-b604-4f95-82b6-cf8f42292f47
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2715673630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.2715673630
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.1212845383
Short name T1725
Test name
Test status
Simulation time 101997483869 ps
CPU time 167.17 seconds
Started Aug 17 06:03:09 PM PDT 24
Finished Aug 17 06:05:56 PM PDT 24
Peak memory 207768 kb
Host smart-fa80cb1e-8137-40f8-b6c7-db6f7ec2a87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212845383 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1212845383
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.2427235098
Short name T2713
Test name
Test status
Simulation time 92160047241 ps
CPU time 149.75 seconds
Started Aug 17 06:03:07 PM PDT 24
Finished Aug 17 06:05:37 PM PDT 24
Peak memory 207716 kb
Host smart-c0d5d296-b22f-4e63-84dc-a40ec178b9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24272
35098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2427235098
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1822860867
Short name T22
Test name
Test status
Simulation time 232700655 ps
CPU time 1.17 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 215916 kb
Host smart-bae3c67d-b578-4623-864a-f11dca743c18
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1822860867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1822860867
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2172602142
Short name T1044
Test name
Test status
Simulation time 157455940 ps
CPU time 0.84 seconds
Started Aug 17 06:03:09 PM PDT 24
Finished Aug 17 06:03:10 PM PDT 24
Peak memory 207436 kb
Host smart-cf8b9c25-3b3c-4a55-803b-668a929cd687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21726
02142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2172602142
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1364729276
Short name T3239
Test name
Test status
Simulation time 187875042 ps
CPU time 0.92 seconds
Started Aug 17 06:03:13 PM PDT 24
Finished Aug 17 06:03:14 PM PDT 24
Peak memory 207468 kb
Host smart-d94321bd-3314-4db1-b971-a1eaa9b6b068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13647
29276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1364729276
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3873699709
Short name T3208
Test name
Test status
Simulation time 3229256627 ps
CPU time 90.41 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:04:38 PM PDT 24
Peak memory 224144 kb
Host smart-0149378a-f686-465c-bcb1-291af03e9d6d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3873699709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3873699709
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.1234456721
Short name T3258
Test name
Test status
Simulation time 14313822448 ps
CPU time 96.45 seconds
Started Aug 17 06:03:07 PM PDT 24
Finished Aug 17 06:04:43 PM PDT 24
Peak memory 207772 kb
Host smart-86243338-4504-42f7-9641-a77452a8d666
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1234456721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.1234456721
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3689527434
Short name T2300
Test name
Test status
Simulation time 217060870 ps
CPU time 0.95 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 207436 kb
Host smart-b60db7c8-3383-4029-8621-248c32cc9b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36895
27434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3689527434
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.4216101143
Short name T3263
Test name
Test status
Simulation time 7769027799 ps
CPU time 11.63 seconds
Started Aug 17 06:03:09 PM PDT 24
Finished Aug 17 06:03:21 PM PDT 24
Peak memory 207712 kb
Host smart-90a8c021-682c-4060-ae73-aa3f855b7872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42161
01143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.4216101143
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1925100796
Short name T2770
Test name
Test status
Simulation time 10475786392 ps
CPU time 13 seconds
Started Aug 17 06:03:09 PM PDT 24
Finished Aug 17 06:03:22 PM PDT 24
Peak memory 207764 kb
Host smart-9df4c114-0ec1-4af2-8e3b-59337b7e67f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19251
00796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1925100796
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2395501529
Short name T1356
Test name
Test status
Simulation time 4878663776 ps
CPU time 41.16 seconds
Started Aug 17 06:03:13 PM PDT 24
Finished Aug 17 06:03:54 PM PDT 24
Peak memory 218536 kb
Host smart-b9e49333-7209-4355-8753-7b8761754d57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2395501529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2395501529
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3504838804
Short name T1441
Test name
Test status
Simulation time 1891510673 ps
CPU time 16.49 seconds
Started Aug 17 06:03:07 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 215948 kb
Host smart-a5e183b8-2033-4e8c-9d39-b3300e4e8e18
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3504838804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.3504838804
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3946383755
Short name T3007
Test name
Test status
Simulation time 253486480 ps
CPU time 1.05 seconds
Started Aug 17 06:03:08 PM PDT 24
Finished Aug 17 06:03:09 PM PDT 24
Peak memory 207436 kb
Host smart-102a195b-7831-4683-8cb2-06b0d4707091
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3946383755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3946383755
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1300400368
Short name T3456
Test name
Test status
Simulation time 195970855 ps
CPU time 0.98 seconds
Started Aug 17 06:03:07 PM PDT 24
Finished Aug 17 06:03:08 PM PDT 24
Peak memory 207456 kb
Host smart-709313ec-32f3-4469-9a97-a303ce34a3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13004
00368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1300400368
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.937664092
Short name T991
Test name
Test status
Simulation time 2542078885 ps
CPU time 74.64 seconds
Started Aug 17 06:03:13 PM PDT 24
Finished Aug 17 06:04:28 PM PDT 24
Peak memory 215904 kb
Host smart-a2bf12dd-7fd2-4ce7-88d5-3a7c63f9bca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93766
4092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.937664092
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.480546215
Short name T600
Test name
Test status
Simulation time 2800153482 ps
CPU time 21.05 seconds
Started Aug 17 06:03:07 PM PDT 24
Finished Aug 17 06:03:28 PM PDT 24
Peak memory 217684 kb
Host smart-a9d92739-49b6-47e2-afa1-4457bc01f5f3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=480546215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.480546215
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.1931608330
Short name T537
Test name
Test status
Simulation time 156263523 ps
CPU time 0.88 seconds
Started Aug 17 06:03:15 PM PDT 24
Finished Aug 17 06:03:16 PM PDT 24
Peak memory 207480 kb
Host smart-52b902bf-2cd0-4c26-b085-39a7923e4cf8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1931608330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.1931608330
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.155347767
Short name T1131
Test name
Test status
Simulation time 172315274 ps
CPU time 0.94 seconds
Started Aug 17 06:03:17 PM PDT 24
Finished Aug 17 06:03:18 PM PDT 24
Peak memory 207472 kb
Host smart-df947784-d4db-4e71-98de-abf66610bce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15534
7767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.155347767
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3659707324
Short name T160
Test name
Test status
Simulation time 186785468 ps
CPU time 0.93 seconds
Started Aug 17 06:03:12 PM PDT 24
Finished Aug 17 06:03:13 PM PDT 24
Peak memory 207460 kb
Host smart-5d63c50e-5324-4781-b3e6-84e88969f1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36597
07324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3659707324
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2553714470
Short name T2196
Test name
Test status
Simulation time 214341748 ps
CPU time 0.97 seconds
Started Aug 17 06:03:14 PM PDT 24
Finished Aug 17 06:03:16 PM PDT 24
Peak memory 207684 kb
Host smart-6def5ea7-5b24-4753-b96f-9f8ac67659dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25537
14470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2553714470
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2137099894
Short name T1308
Test name
Test status
Simulation time 197050845 ps
CPU time 0.9 seconds
Started Aug 17 06:03:18 PM PDT 24
Finished Aug 17 06:03:19 PM PDT 24
Peak memory 207464 kb
Host smart-bb857918-b252-4dcd-b71f-6161596751cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21370
99894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2137099894
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2527219361
Short name T311
Test name
Test status
Simulation time 186692499 ps
CPU time 0.93 seconds
Started Aug 17 06:03:12 PM PDT 24
Finished Aug 17 06:03:13 PM PDT 24
Peak memory 207544 kb
Host smart-e9f87426-a10e-49f1-94c9-2485a8c8a734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25272
19361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2527219361
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2525042280
Short name T1665
Test name
Test status
Simulation time 173104350 ps
CPU time 0.93 seconds
Started Aug 17 06:03:16 PM PDT 24
Finished Aug 17 06:03:17 PM PDT 24
Peak memory 207564 kb
Host smart-90024d39-244f-4b38-a6b6-d7c173630e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25250
42280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2525042280
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3261021539
Short name T2286
Test name
Test status
Simulation time 235036760 ps
CPU time 1.07 seconds
Started Aug 17 06:03:18 PM PDT 24
Finished Aug 17 06:03:19 PM PDT 24
Peak memory 207528 kb
Host smart-c0f20207-b6bd-4045-bd22-0d8ca3a43ec0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3261021539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3261021539
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.4285372719
Short name T1699
Test name
Test status
Simulation time 198627223 ps
CPU time 0.96 seconds
Started Aug 17 06:03:19 PM PDT 24
Finished Aug 17 06:03:20 PM PDT 24
Peak memory 207480 kb
Host smart-2a26344a-f6d9-47f9-8e3f-f4bb8b1e982d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42853
72719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.4285372719
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3360711180
Short name T656
Test name
Test status
Simulation time 139360470 ps
CPU time 0.83 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:03:22 PM PDT 24
Peak memory 207432 kb
Host smart-683e5244-f9e9-413c-967d-719e08d2be06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33607
11180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3360711180
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.454846024
Short name T19
Test name
Test status
Simulation time 57789602 ps
CPU time 0.74 seconds
Started Aug 17 06:03:18 PM PDT 24
Finished Aug 17 06:03:19 PM PDT 24
Peak memory 207496 kb
Host smart-16bd6b40-8402-40e0-ad17-7cd55ae62162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45484
6024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.454846024
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1832583490
Short name T276
Test name
Test status
Simulation time 18005262408 ps
CPU time 44.89 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 215796 kb
Host smart-33c832cc-8e02-4e30-87af-5afa0744379b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18325
83490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1832583490
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.372940618
Short name T2356
Test name
Test status
Simulation time 196779553 ps
CPU time 0.94 seconds
Started Aug 17 06:03:16 PM PDT 24
Finished Aug 17 06:03:17 PM PDT 24
Peak memory 207492 kb
Host smart-96625c47-a7df-4d83-ad62-746843e0db66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37294
0618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.372940618
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1733119379
Short name T1844
Test name
Test status
Simulation time 225786716 ps
CPU time 0.97 seconds
Started Aug 17 06:03:17 PM PDT 24
Finished Aug 17 06:03:18 PM PDT 24
Peak memory 207492 kb
Host smart-842eaae0-8fb4-4ddd-b20b-263e0d50d2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17331
19379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1733119379
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.4217738685
Short name T2521
Test name
Test status
Simulation time 11178046667 ps
CPU time 220.42 seconds
Started Aug 17 06:03:17 PM PDT 24
Finished Aug 17 06:06:58 PM PDT 24
Peak memory 224128 kb
Host smart-8b42a893-b663-4cba-b3d6-c9e3fcfd4775
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217738685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.4217738685
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1056663522
Short name T540
Test name
Test status
Simulation time 196784603 ps
CPU time 0.98 seconds
Started Aug 17 06:03:17 PM PDT 24
Finished Aug 17 06:03:18 PM PDT 24
Peak memory 207480 kb
Host smart-de43c65e-d4fa-4209-8f11-f0429d898287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10566
63522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1056663522
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3512473755
Short name T2730
Test name
Test status
Simulation time 158096733 ps
CPU time 0.86 seconds
Started Aug 17 06:03:15 PM PDT 24
Finished Aug 17 06:03:16 PM PDT 24
Peak memory 207696 kb
Host smart-5a848489-501d-4485-aace-d1decaf482c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35124
73755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3512473755
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_resume_link_active.3701339766
Short name T2984
Test name
Test status
Simulation time 20196667385 ps
CPU time 26.03 seconds
Started Aug 17 06:03:13 PM PDT 24
Finished Aug 17 06:03:40 PM PDT 24
Peak memory 207596 kb
Host smart-88185834-de91-4a60-9e5f-30eb1362e4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37013
39766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.3701339766
Directory /workspace/3.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1673431480
Short name T2168
Test name
Test status
Simulation time 160303002 ps
CPU time 0.85 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 207484 kb
Host smart-17d122d9-707e-467e-9eec-06e2f11ca5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
31480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1673431480
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_full.3805247841
Short name T2178
Test name
Test status
Simulation time 428492261 ps
CPU time 1.34 seconds
Started Aug 17 06:03:15 PM PDT 24
Finished Aug 17 06:03:16 PM PDT 24
Peak memory 207684 kb
Host smart-5b787a10-d568-4c6d-b5af-11ad444747ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38052
47841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.3805247841
Directory /workspace/3.usbdev_rx_full/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.4268313034
Short name T79
Test name
Test status
Simulation time 225991339 ps
CPU time 1 seconds
Started Aug 17 06:03:15 PM PDT 24
Finished Aug 17 06:03:16 PM PDT 24
Peak memory 207464 kb
Host smart-624276ab-7c96-46d4-910d-eea6a609edbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42683
13034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.4268313034
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.4137461475
Short name T241
Test name
Test status
Simulation time 445368346 ps
CPU time 1.32 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 224256 kb
Host smart-5cdcf506-d338-4b65-86f3-e7e3c5d54fdb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4137461475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.4137461475
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3348685549
Short name T44
Test name
Test status
Simulation time 417501386 ps
CPU time 1.51 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 207560 kb
Host smart-871c6f46-831e-4939-a043-eeccf124236f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33486
85549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3348685549
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1158977771
Short name T2473
Test name
Test status
Simulation time 304736217 ps
CPU time 1.1 seconds
Started Aug 17 06:03:12 PM PDT 24
Finished Aug 17 06:03:13 PM PDT 24
Peak memory 207476 kb
Host smart-477113a6-3592-428b-a3f3-4d97144d04ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11589
77771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1158977771
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3505325628
Short name T3403
Test name
Test status
Simulation time 162232259 ps
CPU time 0.91 seconds
Started Aug 17 06:03:24 PM PDT 24
Finished Aug 17 06:03:25 PM PDT 24
Peak memory 207652 kb
Host smart-3895861c-2911-4f90-b016-0855f668d0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35053
25628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3505325628
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2332720402
Short name T2562
Test name
Test status
Simulation time 142172369 ps
CPU time 0.83 seconds
Started Aug 17 06:03:14 PM PDT 24
Finished Aug 17 06:03:15 PM PDT 24
Peak memory 207560 kb
Host smart-890cb4e7-e851-4b43-9381-4718ae6c3c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23327
20402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2332720402
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1543510100
Short name T792
Test name
Test status
Simulation time 176325442 ps
CPU time 0.97 seconds
Started Aug 17 06:03:18 PM PDT 24
Finished Aug 17 06:03:19 PM PDT 24
Peak memory 207476 kb
Host smart-dc5b9076-c23a-475c-bee8-01d8c71d6279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15435
10100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1543510100
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.591380175
Short name T3609
Test name
Test status
Simulation time 2130807549 ps
CPU time 65.27 seconds
Started Aug 17 06:03:17 PM PDT 24
Finished Aug 17 06:04:23 PM PDT 24
Peak memory 215836 kb
Host smart-f0e92ea0-20ce-4589-ad1f-62534c7e35ff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=591380175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.591380175
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.995840566
Short name T518
Test name
Test status
Simulation time 218207356 ps
CPU time 0.94 seconds
Started Aug 17 06:03:15 PM PDT 24
Finished Aug 17 06:03:16 PM PDT 24
Peak memory 207484 kb
Host smart-d13fb520-7d83-49c4-a21e-7c5b7f3f100e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99584
0566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.995840566
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2922765640
Short name T3144
Test name
Test status
Simulation time 178092657 ps
CPU time 0.98 seconds
Started Aug 17 06:03:12 PM PDT 24
Finished Aug 17 06:03:13 PM PDT 24
Peak memory 207468 kb
Host smart-32c0ebec-8ccb-4c54-a35e-5c89bb2ac378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29227
65640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2922765640
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3257213890
Short name T1257
Test name
Test status
Simulation time 791702301 ps
CPU time 2.13 seconds
Started Aug 17 06:03:14 PM PDT 24
Finished Aug 17 06:03:16 PM PDT 24
Peak memory 207460 kb
Host smart-aa6f47c2-ee7c-4b11-85b3-686220c9c45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32572
13890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3257213890
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.3578297371
Short name T3356
Test name
Test status
Simulation time 2995960322 ps
CPU time 87.3 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:04:49 PM PDT 24
Peak memory 217284 kb
Host smart-ef8753f0-e749-48be-b8e5-eb06ab4f38c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35782
97371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.3578297371
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.728632863
Short name T83
Test name
Test status
Simulation time 12115281793 ps
CPU time 65.33 seconds
Started Aug 17 06:03:15 PM PDT 24
Finished Aug 17 06:04:21 PM PDT 24
Peak memory 218648 kb
Host smart-2ee4e974-93da-4ad4-b8b1-915c11bcde00
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728632863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.728632863
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.1319792953
Short name T2691
Test name
Test status
Simulation time 2499143271 ps
CPU time 20.91 seconds
Started Aug 17 06:03:11 PM PDT 24
Finished Aug 17 06:03:32 PM PDT 24
Peak memory 207720 kb
Host smart-d97389f2-6845-43c3-93d8-1e4b3f7e2c43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319792953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.1319792953
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_tx_rx_disruption.1903238224
Short name T3198
Test name
Test status
Simulation time 414436890 ps
CPU time 1.31 seconds
Started Aug 17 06:03:15 PM PDT 24
Finished Aug 17 06:03:16 PM PDT 24
Peak memory 207548 kb
Host smart-98802cff-61ea-427c-87a7-71a7fe527478
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903238224 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.usbdev_tx_rx_disruption.1903238224
Directory /workspace/3.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3386083291
Short name T221
Test name
Test status
Simulation time 61237271 ps
CPU time 0.67 seconds
Started Aug 17 06:08:18 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 207428 kb
Host smart-1e8d31ce-e179-49ff-b8be-5a0cca40993a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3386083291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3386083291
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3955464288
Short name T2586
Test name
Test status
Simulation time 10116244337 ps
CPU time 13.3 seconds
Started Aug 17 06:08:06 PM PDT 24
Finished Aug 17 06:08:20 PM PDT 24
Peak memory 207780 kb
Host smart-e5efc36a-f5b7-4df6-bc56-569b78b80fea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955464288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.3955464288
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3627166668
Short name T1039
Test name
Test status
Simulation time 18835227659 ps
CPU time 23.6 seconds
Started Aug 17 06:08:08 PM PDT 24
Finished Aug 17 06:08:32 PM PDT 24
Peak memory 207764 kb
Host smart-e7fdefd5-f882-4995-baf0-fc59da83f434
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627166668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3627166668
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2993315126
Short name T3552
Test name
Test status
Simulation time 23428820946 ps
CPU time 29.59 seconds
Started Aug 17 06:08:17 PM PDT 24
Finished Aug 17 06:08:46 PM PDT 24
Peak memory 215988 kb
Host smart-9678a191-9d24-4db5-93f2-2df140ba5752
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993315126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.2993315126
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.205575349
Short name T549
Test name
Test status
Simulation time 204506060 ps
CPU time 0.94 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:11 PM PDT 24
Peak memory 207436 kb
Host smart-ef2fe231-267a-4336-8db5-8ae2b9ee991f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557
5349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.205575349
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2267069141
Short name T3256
Test name
Test status
Simulation time 142831962 ps
CPU time 0.85 seconds
Started Aug 17 06:08:31 PM PDT 24
Finished Aug 17 06:08:32 PM PDT 24
Peak memory 207552 kb
Host smart-44825e98-4a5f-4ee9-9352-ad78339ab46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22670
69141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2267069141
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3364159421
Short name T3211
Test name
Test status
Simulation time 217995155 ps
CPU time 1.01 seconds
Started Aug 17 06:08:09 PM PDT 24
Finished Aug 17 06:08:10 PM PDT 24
Peak memory 207484 kb
Host smart-ceb393e5-9d3d-4578-a9bf-6e2892d5fd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33641
59421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3364159421
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1293124130
Short name T3297
Test name
Test status
Simulation time 604307114 ps
CPU time 1.81 seconds
Started Aug 17 06:08:26 PM PDT 24
Finished Aug 17 06:08:28 PM PDT 24
Peak memory 207456 kb
Host smart-2d215597-388b-4d12-ab6c-a71ba13cd773
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1293124130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1293124130
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3127804183
Short name T3319
Test name
Test status
Simulation time 22411433047 ps
CPU time 35.49 seconds
Started Aug 17 06:08:11 PM PDT 24
Finished Aug 17 06:08:47 PM PDT 24
Peak memory 207756 kb
Host smart-263ebcf0-94f8-4564-843c-aff082ac97ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31278
04183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3127804183
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.2158293935
Short name T1664
Test name
Test status
Simulation time 1420108366 ps
CPU time 34.11 seconds
Started Aug 17 06:08:26 PM PDT 24
Finished Aug 17 06:09:00 PM PDT 24
Peak memory 207712 kb
Host smart-b1e1e63a-7cc8-47ea-8e87-965d7451dafd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158293935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.2158293935
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1702186247
Short name T2361
Test name
Test status
Simulation time 1084999843 ps
CPU time 2.41 seconds
Started Aug 17 06:08:09 PM PDT 24
Finished Aug 17 06:08:11 PM PDT 24
Peak memory 207460 kb
Host smart-7abae986-e570-41b6-81ea-482eddd1456c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17021
86247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1702186247
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.85354859
Short name T3322
Test name
Test status
Simulation time 156627592 ps
CPU time 0.89 seconds
Started Aug 17 06:08:09 PM PDT 24
Finished Aug 17 06:08:10 PM PDT 24
Peak memory 207472 kb
Host smart-8ea5da06-dadf-4a1e-9a71-d6b491cc762c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85354
859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.85354859
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2766636939
Short name T670
Test name
Test status
Simulation time 85066686 ps
CPU time 0.82 seconds
Started Aug 17 06:08:08 PM PDT 24
Finished Aug 17 06:08:09 PM PDT 24
Peak memory 207444 kb
Host smart-3bf7eb49-9f1f-4387-9190-e0b24c0db24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27666
36939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2766636939
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.979517475
Short name T1206
Test name
Test status
Simulation time 787012284 ps
CPU time 2.31 seconds
Started Aug 17 06:08:07 PM PDT 24
Finished Aug 17 06:08:09 PM PDT 24
Peak memory 207672 kb
Host smart-84350613-0428-49c6-9a04-8b687154581d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97951
7475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.979517475
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_types.429899237
Short name T505
Test name
Test status
Simulation time 196852419 ps
CPU time 1.03 seconds
Started Aug 17 06:08:26 PM PDT 24
Finished Aug 17 06:08:27 PM PDT 24
Peak memory 207500 kb
Host smart-010cc675-8409-4a27-9057-57ad94882de6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=429899237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.429899237
Directory /workspace/30.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3416788245
Short name T2871
Test name
Test status
Simulation time 277695745 ps
CPU time 2.35 seconds
Started Aug 17 06:08:12 PM PDT 24
Finished Aug 17 06:08:15 PM PDT 24
Peak memory 207632 kb
Host smart-24a62937-3133-4d87-8251-51f605be441e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34167
88245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3416788245
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.41713658
Short name T1374
Test name
Test status
Simulation time 221528658 ps
CPU time 1.11 seconds
Started Aug 17 06:08:06 PM PDT 24
Finished Aug 17 06:08:07 PM PDT 24
Peak memory 215856 kb
Host smart-aee55ef9-5aa1-408f-aa77-e890324d0fdb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=41713658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.41713658
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3701629962
Short name T2301
Test name
Test status
Simulation time 144514779 ps
CPU time 0.93 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207388 kb
Host smart-05c97deb-a577-465f-ab85-0d42a23e8be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37016
29962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3701629962
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.4180535110
Short name T577
Test name
Test status
Simulation time 193474373 ps
CPU time 1.04 seconds
Started Aug 17 06:08:09 PM PDT 24
Finished Aug 17 06:08:10 PM PDT 24
Peak memory 207484 kb
Host smart-ea4ebb2d-8500-4a08-b129-6b655115abda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41805
35110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.4180535110
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.1884078868
Short name T1351
Test name
Test status
Simulation time 2719296660 ps
CPU time 19.69 seconds
Started Aug 17 06:08:07 PM PDT 24
Finished Aug 17 06:08:27 PM PDT 24
Peak memory 217328 kb
Host smart-f3bd070c-721c-4f47-9392-660226dc2f17
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1884078868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.1884078868
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.742503359
Short name T2994
Test name
Test status
Simulation time 8547230724 ps
CPU time 59.08 seconds
Started Aug 17 06:08:26 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207756 kb
Host smart-fa128f1e-ba6a-4c0d-a700-bec731e15a74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=742503359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.742503359
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2187879697
Short name T1824
Test name
Test status
Simulation time 173634943 ps
CPU time 0.88 seconds
Started Aug 17 06:08:06 PM PDT 24
Finished Aug 17 06:08:07 PM PDT 24
Peak memory 207540 kb
Host smart-b4447bd1-df39-48d5-8cc9-de04b8abb89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21878
79697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2187879697
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.4035937431
Short name T595
Test name
Test status
Simulation time 23270005956 ps
CPU time 40.26 seconds
Started Aug 17 06:08:06 PM PDT 24
Finished Aug 17 06:08:46 PM PDT 24
Peak memory 216420 kb
Host smart-d2461f27-1173-4b70-8dc1-c41a7c4739b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40359
37431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.4035937431
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.199559079
Short name T2707
Test name
Test status
Simulation time 6234282001 ps
CPU time 8.38 seconds
Started Aug 17 06:08:28 PM PDT 24
Finished Aug 17 06:08:37 PM PDT 24
Peak memory 215960 kb
Host smart-aa011b36-f966-4de4-bcca-b7f4a329eacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19955
9079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.199559079
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.3750665121
Short name T3019
Test name
Test status
Simulation time 3456812078 ps
CPU time 27.87 seconds
Started Aug 17 06:08:10 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 218720 kb
Host smart-656cf4ee-8a58-4950-b4e8-5fc0394f996e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3750665121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.3750665121
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3096822431
Short name T1509
Test name
Test status
Simulation time 2303596477 ps
CPU time 20.98 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:27 PM PDT 24
Peak memory 215908 kb
Host smart-7f234233-68de-42f1-bfb7-992730b9c1e6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3096822431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3096822431
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.134691471
Short name T2430
Test name
Test status
Simulation time 240690590 ps
CPU time 0.98 seconds
Started Aug 17 06:08:09 PM PDT 24
Finished Aug 17 06:08:10 PM PDT 24
Peak memory 207408 kb
Host smart-71a6124a-1bc7-4a4c-9627-4f42b3f20378
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=134691471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.134691471
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2105793267
Short name T2104
Test name
Test status
Simulation time 211998636 ps
CPU time 1.04 seconds
Started Aug 17 06:08:04 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207684 kb
Host smart-c46ae1a2-6917-4973-b76c-2db2ce21a838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
93267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2105793267
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.309058256
Short name T3051
Test name
Test status
Simulation time 4304436844 ps
CPU time 45.65 seconds
Started Aug 17 06:08:06 PM PDT 24
Finished Aug 17 06:08:52 PM PDT 24
Peak memory 215972 kb
Host smart-ddc7daa6-0fa2-4f09-9eae-c2660c499f55
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=309058256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.309058256
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2024360809
Short name T913
Test name
Test status
Simulation time 168461007 ps
CPU time 0.87 seconds
Started Aug 17 06:08:08 PM PDT 24
Finished Aug 17 06:08:09 PM PDT 24
Peak memory 207408 kb
Host smart-5e020a8b-3950-436e-83e1-49ecf24be43a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2024360809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2024360809
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1132851485
Short name T978
Test name
Test status
Simulation time 166339091 ps
CPU time 0.85 seconds
Started Aug 17 06:08:11 PM PDT 24
Finished Aug 17 06:08:12 PM PDT 24
Peak memory 207488 kb
Host smart-f658a611-ce80-45cc-b35b-917a1e102e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11328
51485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1132851485
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2702296351
Short name T153
Test name
Test status
Simulation time 151999011 ps
CPU time 0.85 seconds
Started Aug 17 06:08:27 PM PDT 24
Finished Aug 17 06:08:28 PM PDT 24
Peak memory 207476 kb
Host smart-19c76fcd-e94c-421d-a8d0-6867c7e06419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27022
96351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2702296351
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.2457333701
Short name T1219
Test name
Test status
Simulation time 155392856 ps
CPU time 0.89 seconds
Started Aug 17 06:08:05 PM PDT 24
Finished Aug 17 06:08:06 PM PDT 24
Peak memory 207368 kb
Host smart-05111831-35f5-48fd-acd1-5f0c54d46585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24573
33701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.2457333701
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3699210005
Short name T90
Test name
Test status
Simulation time 190822726 ps
CPU time 0.92 seconds
Started Aug 17 06:08:07 PM PDT 24
Finished Aug 17 06:08:08 PM PDT 24
Peak memory 207392 kb
Host smart-90603720-8bb9-4eb7-96c3-025af3435fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36992
10005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3699210005
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3333509630
Short name T17
Test name
Test status
Simulation time 205167077 ps
CPU time 0.94 seconds
Started Aug 17 06:08:31 PM PDT 24
Finished Aug 17 06:08:32 PM PDT 24
Peak memory 207552 kb
Host smart-87079e5b-a22c-408e-aead-d5d90eb942f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33335
09630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3333509630
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1323002582
Short name T800
Test name
Test status
Simulation time 152747651 ps
CPU time 0.85 seconds
Started Aug 17 06:08:06 PM PDT 24
Finished Aug 17 06:08:07 PM PDT 24
Peak memory 207560 kb
Host smart-b94cf3d8-f028-41f6-9e93-e16a1a83b53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13230
02582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1323002582
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1369052092
Short name T2575
Test name
Test status
Simulation time 253039717 ps
CPU time 1.05 seconds
Started Aug 17 06:08:12 PM PDT 24
Finished Aug 17 06:08:13 PM PDT 24
Peak memory 207568 kb
Host smart-64bd5ed9-0ff2-4566-9734-f0ea94273b8d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1369052092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1369052092
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.54438763
Short name T3272
Test name
Test status
Simulation time 142035328 ps
CPU time 0.85 seconds
Started Aug 17 06:08:21 PM PDT 24
Finished Aug 17 06:08:22 PM PDT 24
Peak memory 207424 kb
Host smart-a5ae8737-f098-49ca-9757-5f3bbbd816e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54438
763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.54438763
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.32672837
Short name T3094
Test name
Test status
Simulation time 57197055 ps
CPU time 0.72 seconds
Started Aug 17 06:08:18 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 207476 kb
Host smart-d36a487b-cc2a-440a-a5db-404bc93803ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32672
837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.32672837
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3210488638
Short name T2274
Test name
Test status
Simulation time 20110661562 ps
CPU time 55.82 seconds
Started Aug 17 06:08:15 PM PDT 24
Finished Aug 17 06:09:11 PM PDT 24
Peak memory 215960 kb
Host smart-537c16b2-b029-4b83-a996-b6a90b443613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32104
88638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3210488638
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1517945028
Short name T597
Test name
Test status
Simulation time 154685688 ps
CPU time 0.87 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:25 PM PDT 24
Peak memory 207492 kb
Host smart-f896d86c-05f0-4cf0-8afe-9a2916e711ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15179
45028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1517945028
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.964578779
Short name T3096
Test name
Test status
Simulation time 194381822 ps
CPU time 0.98 seconds
Started Aug 17 06:08:16 PM PDT 24
Finished Aug 17 06:08:17 PM PDT 24
Peak memory 207412 kb
Host smart-247923c5-7f75-454a-8956-f5256e8f1594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96457
8779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.964578779
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3045771656
Short name T2597
Test name
Test status
Simulation time 227219071 ps
CPU time 1.02 seconds
Started Aug 17 06:08:12 PM PDT 24
Finished Aug 17 06:08:14 PM PDT 24
Peak memory 207456 kb
Host smart-d0242aed-874a-424a-9cd4-b300d35950ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30457
71656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3045771656
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2683770214
Short name T2203
Test name
Test status
Simulation time 182316081 ps
CPU time 0.93 seconds
Started Aug 17 06:08:20 PM PDT 24
Finished Aug 17 06:08:21 PM PDT 24
Peak memory 207496 kb
Host smart-ae7f072b-ce5a-44b7-82aa-8b387a2bb132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26837
70214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2683770214
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.4250913795
Short name T627
Test name
Test status
Simulation time 156613775 ps
CPU time 0.92 seconds
Started Aug 17 06:08:21 PM PDT 24
Finished Aug 17 06:08:22 PM PDT 24
Peak memory 207420 kb
Host smart-be8de393-af69-4d37-9732-49e1be282fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42509
13795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.4250913795
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_rx_full.3463070626
Short name T1862
Test name
Test status
Simulation time 262509518 ps
CPU time 1.14 seconds
Started Aug 17 06:08:18 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 207448 kb
Host smart-413ee9da-598f-411f-a2be-6a7d74a4bc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34630
70626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.3463070626
Directory /workspace/30.usbdev_rx_full/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.625305403
Short name T2599
Test name
Test status
Simulation time 157318442 ps
CPU time 0.97 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:25 PM PDT 24
Peak memory 207432 kb
Host smart-12283fba-7d4e-429e-aca1-f27868b42395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62530
5403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.625305403
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.929478307
Short name T741
Test name
Test status
Simulation time 144100112 ps
CPU time 0.84 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:25 PM PDT 24
Peak memory 207532 kb
Host smart-b54cc529-1499-4f9b-af9f-48a1c381bcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92947
8307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.929478307
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1178923584
Short name T3376
Test name
Test status
Simulation time 213016514 ps
CPU time 1 seconds
Started Aug 17 06:08:20 PM PDT 24
Finished Aug 17 06:08:21 PM PDT 24
Peak memory 207464 kb
Host smart-edd8de19-b432-419d-9f91-a71127e14400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11789
23584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1178923584
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.631416923
Short name T2503
Test name
Test status
Simulation time 2007328522 ps
CPU time 20.06 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 215792 kb
Host smart-b4389b41-099e-477d-9939-b058b3f22c7e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=631416923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.631416923
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2261208871
Short name T949
Test name
Test status
Simulation time 211690726 ps
CPU time 0.91 seconds
Started Aug 17 06:08:15 PM PDT 24
Finished Aug 17 06:08:17 PM PDT 24
Peak memory 207460 kb
Host smart-1a2d4298-e2a2-416b-80f1-439bf8839a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22612
08871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2261208871
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3957256940
Short name T2089
Test name
Test status
Simulation time 182044470 ps
CPU time 0.95 seconds
Started Aug 17 06:08:27 PM PDT 24
Finished Aug 17 06:08:28 PM PDT 24
Peak memory 207488 kb
Host smart-ee2e7426-3808-4e01-b690-07c19ff99a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39572
56940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3957256940
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2770649098
Short name T798
Test name
Test status
Simulation time 1020160913 ps
CPU time 2.43 seconds
Started Aug 17 06:08:25 PM PDT 24
Finished Aug 17 06:08:28 PM PDT 24
Peak memory 207648 kb
Host smart-a16ec288-cddb-48b1-a38b-c4710b978a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706
49098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2770649098
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.3132688968
Short name T2230
Test name
Test status
Simulation time 2338365803 ps
CPU time 68.73 seconds
Started Aug 17 06:08:18 PM PDT 24
Finished Aug 17 06:09:27 PM PDT 24
Peak memory 224144 kb
Host smart-859d90d1-7190-49f0-9a30-0002aeb8f620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31326
88968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3132688968
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.3963404660
Short name T3547
Test name
Test status
Simulation time 3421002168 ps
CPU time 30.48 seconds
Started Aug 17 06:08:12 PM PDT 24
Finished Aug 17 06:08:42 PM PDT 24
Peak memory 207748 kb
Host smart-beb88285-adea-453c-a69d-d640aa7dadef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963404660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.3963404660
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_tx_rx_disruption.1572950189
Short name T2445
Test name
Test status
Simulation time 580712548 ps
CPU time 1.83 seconds
Started Aug 17 06:08:17 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 207492 kb
Host smart-0b2e846f-f975-476b-88ef-62cf8a572c24
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572950189 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.usbdev_tx_rx_disruption.1572950189
Directory /workspace/30.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/300.usbdev_tx_rx_disruption.292055823
Short name T3188
Test name
Test status
Simulation time 517096255 ps
CPU time 1.59 seconds
Started Aug 17 06:12:00 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 207516 kb
Host smart-e0720a64-19c7-4a64-9322-ea659f53665b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292055823 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 300.usbdev_tx_rx_disruption.292055823
Directory /workspace/300.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/301.usbdev_tx_rx_disruption.2161882885
Short name T2698
Test name
Test status
Simulation time 582001255 ps
CPU time 1.58 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207532 kb
Host smart-7a6257d1-b008-4dbf-bad5-ca644ae09fe8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161882885 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 301.usbdev_tx_rx_disruption.2161882885
Directory /workspace/301.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/302.usbdev_tx_rx_disruption.3866775592
Short name T1417
Test name
Test status
Simulation time 405705361 ps
CPU time 1.43 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207548 kb
Host smart-d6c9ea1d-13da-4998-81de-9350d03c9f03
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866775592 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 302.usbdev_tx_rx_disruption.3866775592
Directory /workspace/302.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/303.usbdev_tx_rx_disruption.3301557300
Short name T3440
Test name
Test status
Simulation time 529316540 ps
CPU time 1.64 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207516 kb
Host smart-b18f1242-3023-4b1b-bc17-aab46b482efe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301557300 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 303.usbdev_tx_rx_disruption.3301557300
Directory /workspace/303.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/304.usbdev_tx_rx_disruption.1534368003
Short name T2763
Test name
Test status
Simulation time 475326464 ps
CPU time 1.44 seconds
Started Aug 17 06:12:19 PM PDT 24
Finished Aug 17 06:12:21 PM PDT 24
Peak memory 207548 kb
Host smart-8f299c5a-b5fa-4808-a15f-97e3d809eccb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534368003 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 304.usbdev_tx_rx_disruption.1534368003
Directory /workspace/304.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/305.usbdev_tx_rx_disruption.1386307167
Short name T2296
Test name
Test status
Simulation time 576003068 ps
CPU time 1.77 seconds
Started Aug 17 06:12:22 PM PDT 24
Finished Aug 17 06:12:23 PM PDT 24
Peak memory 207432 kb
Host smart-cc2b78e5-5859-4f87-a511-bf8b0b8e8fcd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386307167 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 305.usbdev_tx_rx_disruption.1386307167
Directory /workspace/305.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/306.usbdev_tx_rx_disruption.211303933
Short name T2314
Test name
Test status
Simulation time 558432075 ps
CPU time 1.56 seconds
Started Aug 17 06:12:22 PM PDT 24
Finished Aug 17 06:12:24 PM PDT 24
Peak memory 207568 kb
Host smart-9e6edc98-f963-4b43-ab81-337a9baf743b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211303933 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 306.usbdev_tx_rx_disruption.211303933
Directory /workspace/306.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/308.usbdev_tx_rx_disruption.3139197302
Short name T2785
Test name
Test status
Simulation time 601599288 ps
CPU time 1.72 seconds
Started Aug 17 06:12:13 PM PDT 24
Finished Aug 17 06:12:15 PM PDT 24
Peak memory 207544 kb
Host smart-77456066-9ea3-4d3b-ada0-144b84ef35e9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139197302 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 308.usbdev_tx_rx_disruption.3139197302
Directory /workspace/308.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/309.usbdev_tx_rx_disruption.86935343
Short name T3436
Test name
Test status
Simulation time 599292361 ps
CPU time 1.81 seconds
Started Aug 17 06:12:12 PM PDT 24
Finished Aug 17 06:12:14 PM PDT 24
Peak memory 207544 kb
Host smart-64c06f75-5817-439a-9c03-c5dc69eee829
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86935343 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 309.usbdev_tx_rx_disruption.86935343
Directory /workspace/309.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.3810573597
Short name T1059
Test name
Test status
Simulation time 36683911 ps
CPU time 0.65 seconds
Started Aug 17 06:08:34 PM PDT 24
Finished Aug 17 06:08:35 PM PDT 24
Peak memory 207444 kb
Host smart-01cfbfea-a06b-4e02-8a66-70bf7b360d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3810573597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3810573597
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1379957893
Short name T7
Test name
Test status
Simulation time 6788181578 ps
CPU time 9.38 seconds
Started Aug 17 06:08:25 PM PDT 24
Finished Aug 17 06:08:34 PM PDT 24
Peak memory 215952 kb
Host smart-230733bb-2378-42ab-888c-4396af95eda4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379957893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.1379957893
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3855539128
Short name T744
Test name
Test status
Simulation time 20133559686 ps
CPU time 28.61 seconds
Started Aug 17 06:08:29 PM PDT 24
Finished Aug 17 06:08:58 PM PDT 24
Peak memory 207792 kb
Host smart-6e36c31f-6840-4dfb-8114-16491af961f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855539128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3855539128
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.363286375
Short name T225
Test name
Test status
Simulation time 31358262263 ps
CPU time 38.94 seconds
Started Aug 17 06:08:21 PM PDT 24
Finished Aug 17 06:09:00 PM PDT 24
Peak memory 207808 kb
Host smart-c3550313-8f5e-4df6-8d4d-2d17cd7d90e2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363286375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_ao
n_wake_resume.363286375
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1756947186
Short name T3539
Test name
Test status
Simulation time 168735544 ps
CPU time 0.9 seconds
Started Aug 17 06:08:13 PM PDT 24
Finished Aug 17 06:08:14 PM PDT 24
Peak memory 207476 kb
Host smart-80b897aa-15b4-49bc-be0c-37fa0c61c77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17569
47186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1756947186
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.4282811415
Short name T1797
Test name
Test status
Simulation time 150821257 ps
CPU time 0.9 seconds
Started Aug 17 06:08:21 PM PDT 24
Finished Aug 17 06:08:22 PM PDT 24
Peak memory 207520 kb
Host smart-bc9c0185-9acb-4dd4-b0a3-adc4edb22047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42828
11415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.4282811415
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2971213519
Short name T3295
Test name
Test status
Simulation time 279904087 ps
CPU time 1.11 seconds
Started Aug 17 06:08:28 PM PDT 24
Finished Aug 17 06:08:29 PM PDT 24
Peak memory 207536 kb
Host smart-129ec923-d299-4ca0-8b9c-ec99172b9e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29712
13519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2971213519
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3921111802
Short name T2389
Test name
Test status
Simulation time 548491752 ps
CPU time 1.65 seconds
Started Aug 17 06:08:21 PM PDT 24
Finished Aug 17 06:08:22 PM PDT 24
Peak memory 207440 kb
Host smart-9de5f826-c9e9-4964-97d7-df55f44b2741
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3921111802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3921111802
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3137550600
Short name T3480
Test name
Test status
Simulation time 36613699614 ps
CPU time 60.21 seconds
Started Aug 17 06:08:21 PM PDT 24
Finished Aug 17 06:09:21 PM PDT 24
Peak memory 207756 kb
Host smart-7ab2cd45-bfcc-49ca-a2cf-2154e08d7c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31375
50600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3137550600
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.1573585098
Short name T175
Test name
Test status
Simulation time 1588660475 ps
CPU time 13.33 seconds
Started Aug 17 06:08:27 PM PDT 24
Finished Aug 17 06:08:40 PM PDT 24
Peak memory 207676 kb
Host smart-d591c682-fc9a-4d38-877e-e432246fbcef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573585098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.1573585098
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.1166909028
Short name T3203
Test name
Test status
Simulation time 579365255 ps
CPU time 1.63 seconds
Started Aug 17 06:08:16 PM PDT 24
Finished Aug 17 06:08:18 PM PDT 24
Peak memory 207512 kb
Host smart-19ad18b3-bcba-448d-8477-914c430d0864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11669
09028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.1166909028
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2132841680
Short name T1286
Test name
Test status
Simulation time 163198800 ps
CPU time 0.84 seconds
Started Aug 17 06:08:23 PM PDT 24
Finished Aug 17 06:08:24 PM PDT 24
Peak memory 207580 kb
Host smart-be57af20-006d-4c4a-8e34-60782cae4328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21328
41680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2132841680
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3842710097
Short name T855
Test name
Test status
Simulation time 96907796 ps
CPU time 0.77 seconds
Started Aug 17 06:08:15 PM PDT 24
Finished Aug 17 06:08:15 PM PDT 24
Peak memory 207428 kb
Host smart-7ad0e146-422b-485e-9178-e24c286694f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38427
10097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3842710097
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1838999701
Short name T2240
Test name
Test status
Simulation time 902527440 ps
CPU time 2.76 seconds
Started Aug 17 06:08:16 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 207820 kb
Host smart-982ed7f4-7b48-418b-8472-3ae059bf765c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18389
99701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1838999701
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_types.3813188945
Short name T3135
Test name
Test status
Simulation time 329179674 ps
CPU time 1.17 seconds
Started Aug 17 06:08:16 PM PDT 24
Finished Aug 17 06:08:17 PM PDT 24
Peak memory 207520 kb
Host smart-316d6988-61d6-4263-a19b-27a17ee55884
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3813188945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.3813188945
Directory /workspace/31.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2636808692
Short name T1233
Test name
Test status
Simulation time 311810432 ps
CPU time 2.1 seconds
Started Aug 17 06:08:20 PM PDT 24
Finished Aug 17 06:08:22 PM PDT 24
Peak memory 207644 kb
Host smart-8ac3fc12-e2ea-49f3-8ff7-537a679a39f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26368
08692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2636808692
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4115097698
Short name T2961
Test name
Test status
Simulation time 187811289 ps
CPU time 1.11 seconds
Started Aug 17 06:08:26 PM PDT 24
Finished Aug 17 06:08:27 PM PDT 24
Peak memory 215876 kb
Host smart-5c71a595-958f-45c8-b5b6-e6c077ae0416
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4115097698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4115097698
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1190789417
Short name T1502
Test name
Test status
Simulation time 169055768 ps
CPU time 0.87 seconds
Started Aug 17 06:08:20 PM PDT 24
Finished Aug 17 06:08:21 PM PDT 24
Peak memory 207432 kb
Host smart-760d08e4-f5dd-431b-a93f-c8f5ce9e54e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11907
89417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1190789417
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.732087206
Short name T786
Test name
Test status
Simulation time 203411699 ps
CPU time 1 seconds
Started Aug 17 06:08:26 PM PDT 24
Finished Aug 17 06:08:27 PM PDT 24
Peak memory 207348 kb
Host smart-c94177c0-c31c-40b3-864f-fbd6c12d7fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73208
7206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.732087206
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.3754145187
Short name T2416
Test name
Test status
Simulation time 3360668332 ps
CPU time 100.06 seconds
Started Aug 17 06:08:20 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 218464 kb
Host smart-39ec6ea1-fcf5-4526-8b7f-9e195063a12a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3754145187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.3754145187
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.365660992
Short name T581
Test name
Test status
Simulation time 9547191725 ps
CPU time 68.28 seconds
Started Aug 17 06:08:15 PM PDT 24
Finished Aug 17 06:09:23 PM PDT 24
Peak memory 207784 kb
Host smart-9653f58a-eeeb-4ee7-b009-2972de4a8055
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=365660992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.365660992
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.24683325
Short name T2423
Test name
Test status
Simulation time 228623518 ps
CPU time 1 seconds
Started Aug 17 06:08:23 PM PDT 24
Finished Aug 17 06:08:24 PM PDT 24
Peak memory 207392 kb
Host smart-e6a29833-59bf-4700-ab94-acd7b2e57f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24683
325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.24683325
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3369778508
Short name T1316
Test name
Test status
Simulation time 15399746661 ps
CPU time 23.13 seconds
Started Aug 17 06:08:16 PM PDT 24
Finished Aug 17 06:08:39 PM PDT 24
Peak memory 207808 kb
Host smart-f2fed2d8-461c-44fc-a4d0-f4380a8ff8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33697
78508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3369778508
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.4263658261
Short name T2516
Test name
Test status
Simulation time 10177625057 ps
CPU time 13.94 seconds
Started Aug 17 06:08:26 PM PDT 24
Finished Aug 17 06:08:40 PM PDT 24
Peak memory 207828 kb
Host smart-eedfa41a-1e5f-45c7-9e27-d7ee28b7bcc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42636
58261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.4263658261
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2267761061
Short name T1553
Test name
Test status
Simulation time 3324409743 ps
CPU time 97.2 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:10:02 PM PDT 24
Peak memory 215980 kb
Host smart-bfe798a7-2e7e-47f1-aa7b-3c286082fe9c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2267761061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2267761061
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2017794378
Short name T3073
Test name
Test status
Simulation time 2291087847 ps
CPU time 67.82 seconds
Started Aug 17 06:08:19 PM PDT 24
Finished Aug 17 06:09:26 PM PDT 24
Peak memory 215892 kb
Host smart-6e428a57-37b1-4380-8d10-39e79de18b01
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2017794378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2017794378
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3720159370
Short name T1311
Test name
Test status
Simulation time 244951266 ps
CPU time 1.04 seconds
Started Aug 17 06:08:14 PM PDT 24
Finished Aug 17 06:08:16 PM PDT 24
Peak memory 207480 kb
Host smart-7d0e94e4-6abd-48a0-b0dd-de6ddf98df9f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3720159370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3720159370
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.145976910
Short name T3593
Test name
Test status
Simulation time 194988170 ps
CPU time 0.95 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:25 PM PDT 24
Peak memory 207480 kb
Host smart-f81d2a2f-baaf-4b24-bcb3-962033387217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14597
6910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.145976910
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2622384407
Short name T3242
Test name
Test status
Simulation time 2639902411 ps
CPU time 80.85 seconds
Started Aug 17 06:08:18 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 215860 kb
Host smart-34e4011b-7e17-400a-9dd7-d2254caa048c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2622384407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2622384407
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1686290056
Short name T979
Test name
Test status
Simulation time 153421321 ps
CPU time 0.91 seconds
Started Aug 17 06:08:18 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 207492 kb
Host smart-ce09e1d5-f794-4ace-b46b-e258c35600b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1686290056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1686290056
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1722452799
Short name T3320
Test name
Test status
Simulation time 170582661 ps
CPU time 0.9 seconds
Started Aug 17 06:08:18 PM PDT 24
Finished Aug 17 06:08:19 PM PDT 24
Peak memory 207472 kb
Host smart-53ed606b-c2ca-44d7-b401-f50ba6d18e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
52799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1722452799
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2990169386
Short name T3315
Test name
Test status
Simulation time 187520664 ps
CPU time 0.93 seconds
Started Aug 17 06:08:24 PM PDT 24
Finished Aug 17 06:08:26 PM PDT 24
Peak memory 207452 kb
Host smart-352f21f1-53bb-4007-af93-c57c67433886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29901
69386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2990169386
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.651303568
Short name T1431
Test name
Test status
Simulation time 167544685 ps
CPU time 0.93 seconds
Started Aug 17 06:08:20 PM PDT 24
Finished Aug 17 06:08:21 PM PDT 24
Peak memory 207448 kb
Host smart-f8454730-002e-4a37-a961-16ad0fb454ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65130
3568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.651303568
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3201608985
Short name T544
Test name
Test status
Simulation time 186716825 ps
CPU time 0.92 seconds
Started Aug 17 06:08:28 PM PDT 24
Finished Aug 17 06:08:29 PM PDT 24
Peak memory 207460 kb
Host smart-e7d698c9-358a-4a66-b50a-ac27dcf4b18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32016
08985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3201608985
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.4215746349
Short name T92
Test name
Test status
Simulation time 174795352 ps
CPU time 0.88 seconds
Started Aug 17 06:08:34 PM PDT 24
Finished Aug 17 06:08:35 PM PDT 24
Peak memory 207564 kb
Host smart-10f427e1-9cf0-4dd7-a177-d7e5bb41d557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42157
46349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.4215746349
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.21834272
Short name T2753
Test name
Test status
Simulation time 155824945 ps
CPU time 0.86 seconds
Started Aug 17 06:08:29 PM PDT 24
Finished Aug 17 06:08:29 PM PDT 24
Peak memory 207532 kb
Host smart-84af9bf9-d88e-43d6-81c4-85b154365237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21834
272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.21834272
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.4053092363
Short name T2680
Test name
Test status
Simulation time 262704049 ps
CPU time 1.16 seconds
Started Aug 17 06:08:36 PM PDT 24
Finished Aug 17 06:08:37 PM PDT 24
Peak memory 207480 kb
Host smart-6c65cfe6-839d-462e-bca8-ab42b892ecce
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4053092363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.4053092363
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1619862208
Short name T1917
Test name
Test status
Simulation time 157996963 ps
CPU time 0.86 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 207452 kb
Host smart-e6d4e6b4-677b-476c-ab1d-985d69676969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16198
62208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1619862208
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.698328202
Short name T2248
Test name
Test status
Simulation time 38545930 ps
CPU time 0.68 seconds
Started Aug 17 06:08:29 PM PDT 24
Finished Aug 17 06:08:30 PM PDT 24
Peak memory 207512 kb
Host smart-76776e9e-4181-4d10-9d23-c674a9a50e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69832
8202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.698328202
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1961701309
Short name T314
Test name
Test status
Simulation time 12582651438 ps
CPU time 35.21 seconds
Started Aug 17 06:08:29 PM PDT 24
Finished Aug 17 06:09:04 PM PDT 24
Peak memory 215976 kb
Host smart-57f1b109-7e30-4196-9887-465fc02b9f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19617
01309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1961701309
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2301754378
Short name T601
Test name
Test status
Simulation time 251795646 ps
CPU time 1.01 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 207488 kb
Host smart-c663d1e5-3d38-411f-a540-249b35bd657d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23017
54378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2301754378
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1838583905
Short name T1056
Test name
Test status
Simulation time 244602771 ps
CPU time 1.01 seconds
Started Aug 17 06:08:36 PM PDT 24
Finished Aug 17 06:08:37 PM PDT 24
Peak memory 207412 kb
Host smart-ebb7ba5a-2faa-4c73-b6d6-19137f6c6739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18385
83905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1838583905
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2398124589
Short name T2701
Test name
Test status
Simulation time 199192040 ps
CPU time 0.88 seconds
Started Aug 17 06:08:25 PM PDT 24
Finished Aug 17 06:08:26 PM PDT 24
Peak memory 207468 kb
Host smart-6e811303-1f35-42d9-b69a-abab7dabdcee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23981
24589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2398124589
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.2354745379
Short name T1347
Test name
Test status
Simulation time 164630163 ps
CPU time 0.96 seconds
Started Aug 17 06:08:27 PM PDT 24
Finished Aug 17 06:08:28 PM PDT 24
Peak memory 207492 kb
Host smart-52566248-def1-450c-ae23-e29bd3aecd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23547
45379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.2354745379
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.88184989
Short name T3219
Test name
Test status
Simulation time 196018663 ps
CPU time 0.95 seconds
Started Aug 17 06:08:29 PM PDT 24
Finished Aug 17 06:08:30 PM PDT 24
Peak memory 207472 kb
Host smart-463613ed-76da-42ce-aa6f-4ce4819d99e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88184
989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.88184989
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_rx_full.4105397132
Short name T328
Test name
Test status
Simulation time 258660563 ps
CPU time 1.13 seconds
Started Aug 17 06:08:28 PM PDT 24
Finished Aug 17 06:08:29 PM PDT 24
Peak memory 207428 kb
Host smart-eb64bb1c-3742-4857-bac3-8653e6e0fba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41053
97132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.4105397132
Directory /workspace/31.usbdev_rx_full/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.502765693
Short name T2454
Test name
Test status
Simulation time 189138789 ps
CPU time 0.89 seconds
Started Aug 17 06:08:27 PM PDT 24
Finished Aug 17 06:08:28 PM PDT 24
Peak memory 207452 kb
Host smart-dbe05cd5-0b0c-4750-a66b-99bc3bcd658d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50276
5693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.502765693
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2618139201
Short name T3422
Test name
Test status
Simulation time 160983789 ps
CPU time 0.87 seconds
Started Aug 17 06:08:36 PM PDT 24
Finished Aug 17 06:08:37 PM PDT 24
Peak memory 207416 kb
Host smart-c14dca8a-1e22-4237-8503-726aaf842acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26181
39201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2618139201
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3583239708
Short name T1304
Test name
Test status
Simulation time 202829152 ps
CPU time 0.98 seconds
Started Aug 17 06:08:29 PM PDT 24
Finished Aug 17 06:08:30 PM PDT 24
Peak memory 207476 kb
Host smart-a996262d-9dd2-4ec1-8ad5-015303b99076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35832
39708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3583239708
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.941521814
Short name T3538
Test name
Test status
Simulation time 3096882813 ps
CPU time 30.02 seconds
Started Aug 17 06:08:36 PM PDT 24
Finished Aug 17 06:09:06 PM PDT 24
Peak memory 215840 kb
Host smart-7adab850-3295-4b32-a6ee-159e23e35ae1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=941521814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.941521814
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1985725449
Short name T3012
Test name
Test status
Simulation time 199774701 ps
CPU time 1 seconds
Started Aug 17 06:08:40 PM PDT 24
Finished Aug 17 06:08:42 PM PDT 24
Peak memory 207432 kb
Host smart-472bb359-5353-453a-bd2c-8510d924fcf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19857
25449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1985725449
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3017005823
Short name T1461
Test name
Test status
Simulation time 247994906 ps
CPU time 1.05 seconds
Started Aug 17 06:08:36 PM PDT 24
Finished Aug 17 06:08:37 PM PDT 24
Peak memory 207544 kb
Host smart-c53f2cea-bf24-405c-b70a-251c895229fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30170
05823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3017005823
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.908435176
Short name T2855
Test name
Test status
Simulation time 1327431906 ps
CPU time 3.23 seconds
Started Aug 17 06:08:32 PM PDT 24
Finished Aug 17 06:08:35 PM PDT 24
Peak memory 207672 kb
Host smart-92a32705-753f-4aaf-aee2-57a17c73375d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90843
5176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.908435176
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2244193389
Short name T1625
Test name
Test status
Simulation time 1962819142 ps
CPU time 15.72 seconds
Started Aug 17 06:08:36 PM PDT 24
Finished Aug 17 06:08:52 PM PDT 24
Peak memory 217536 kb
Host smart-4429d2fd-a49a-47b4-9e96-08e356e7f9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22441
93389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2244193389
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.2525972768
Short name T1081
Test name
Test status
Simulation time 741603073 ps
CPU time 15.49 seconds
Started Aug 17 06:08:28 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 207708 kb
Host smart-7f22060b-8469-4079-a6c9-6cbe3a2d95a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525972768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.2525972768
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_tx_rx_disruption.3331749724
Short name T2093
Test name
Test status
Simulation time 482612101 ps
CPU time 1.54 seconds
Started Aug 17 06:08:29 PM PDT 24
Finished Aug 17 06:08:31 PM PDT 24
Peak memory 207568 kb
Host smart-c8e19718-6582-4d9a-9982-d820cc9dc5ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331749724 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.usbdev_tx_rx_disruption.3331749724
Directory /workspace/31.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/310.usbdev_tx_rx_disruption.4157301923
Short name T3088
Test name
Test status
Simulation time 582417695 ps
CPU time 1.72 seconds
Started Aug 17 06:12:19 PM PDT 24
Finished Aug 17 06:12:21 PM PDT 24
Peak memory 207512 kb
Host smart-3050cbe3-abc1-4ce2-a350-38a2c23194a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157301923 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 310.usbdev_tx_rx_disruption.4157301923
Directory /workspace/310.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/311.usbdev_tx_rx_disruption.3206452541
Short name T3296
Test name
Test status
Simulation time 557002304 ps
CPU time 1.78 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207540 kb
Host smart-b9d68f63-bf78-46c4-a156-5adb8a1db149
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206452541 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 311.usbdev_tx_rx_disruption.3206452541
Directory /workspace/311.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/312.usbdev_tx_rx_disruption.1526913603
Short name T682
Test name
Test status
Simulation time 469457948 ps
CPU time 1.46 seconds
Started Aug 17 06:12:15 PM PDT 24
Finished Aug 17 06:12:17 PM PDT 24
Peak memory 207540 kb
Host smart-0ad048a4-a994-4d17-b7d2-d062aec9c3a4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526913603 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 312.usbdev_tx_rx_disruption.1526913603
Directory /workspace/312.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/313.usbdev_tx_rx_disruption.2580607045
Short name T1352
Test name
Test status
Simulation time 544386200 ps
CPU time 1.56 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207540 kb
Host smart-7f6ddfd2-cf75-4007-b839-49989d1e2bdd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580607045 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 313.usbdev_tx_rx_disruption.2580607045
Directory /workspace/313.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/314.usbdev_tx_rx_disruption.2468481459
Short name T2113
Test name
Test status
Simulation time 584819752 ps
CPU time 1.62 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207556 kb
Host smart-f91e23a0-f195-4bae-94d7-8a7076ed2fdb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468481459 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 314.usbdev_tx_rx_disruption.2468481459
Directory /workspace/314.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/315.usbdev_tx_rx_disruption.3674484256
Short name T2047
Test name
Test status
Simulation time 466858282 ps
CPU time 1.47 seconds
Started Aug 17 06:12:04 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207500 kb
Host smart-db3b2d88-6f9e-45c8-8fce-87a5fc3c0bd0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674484256 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 315.usbdev_tx_rx_disruption.3674484256
Directory /workspace/315.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/316.usbdev_tx_rx_disruption.2749322405
Short name T2612
Test name
Test status
Simulation time 537148298 ps
CPU time 1.65 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207548 kb
Host smart-b6e94cf5-3756-436e-b116-65871197fee8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749322405 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 316.usbdev_tx_rx_disruption.2749322405
Directory /workspace/316.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/317.usbdev_tx_rx_disruption.2848688220
Short name T1223
Test name
Test status
Simulation time 546800694 ps
CPU time 1.7 seconds
Started Aug 17 06:12:07 PM PDT 24
Finished Aug 17 06:12:08 PM PDT 24
Peak memory 207572 kb
Host smart-a0f74e32-23c7-4fb2-8352-f351156970fa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848688220 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 317.usbdev_tx_rx_disruption.2848688220
Directory /workspace/317.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/318.usbdev_tx_rx_disruption.3772417965
Short name T69
Test name
Test status
Simulation time 419618479 ps
CPU time 1.39 seconds
Started Aug 17 06:12:12 PM PDT 24
Finished Aug 17 06:12:13 PM PDT 24
Peak memory 207560 kb
Host smart-ce0cea57-1d67-44f2-ba2c-6ff82649c92a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772417965 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 318.usbdev_tx_rx_disruption.3772417965
Directory /workspace/318.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/319.usbdev_tx_rx_disruption.1742961137
Short name T865
Test name
Test status
Simulation time 484917446 ps
CPU time 1.42 seconds
Started Aug 17 06:12:07 PM PDT 24
Finished Aug 17 06:12:08 PM PDT 24
Peak memory 207572 kb
Host smart-f05d7879-15c2-4289-93fd-72950fc3f1a0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742961137 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 319.usbdev_tx_rx_disruption.1742961137
Directory /workspace/319.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.4031202699
Short name T1276
Test name
Test status
Simulation time 90515766 ps
CPU time 0.71 seconds
Started Aug 17 06:08:41 PM PDT 24
Finished Aug 17 06:08:41 PM PDT 24
Peak memory 207448 kb
Host smart-09773756-d86e-43f8-86d5-d764a384a987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4031202699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.4031202699
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3292558578
Short name T1575
Test name
Test status
Simulation time 4320564048 ps
CPU time 6.84 seconds
Started Aug 17 06:08:28 PM PDT 24
Finished Aug 17 06:08:34 PM PDT 24
Peak memory 215968 kb
Host smart-65feaf73-104c-410d-b0d0-f7d8f48e7bf5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292558578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.3292558578
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3799413896
Short name T2690
Test name
Test status
Simulation time 20390340648 ps
CPU time 28.73 seconds
Started Aug 17 06:08:32 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207736 kb
Host smart-7b455cd1-968e-4528-a394-2b33fe318938
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799413896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3799413896
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3729453727
Short name T1893
Test name
Test status
Simulation time 24736525393 ps
CPU time 30.3 seconds
Started Aug 17 06:08:40 PM PDT 24
Finished Aug 17 06:09:11 PM PDT 24
Peak memory 216000 kb
Host smart-fb3d8537-f93f-44ba-80cc-400c39db348c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729453727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.3729453727
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2886468161
Short name T2618
Test name
Test status
Simulation time 158074188 ps
CPU time 0.91 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:39 PM PDT 24
Peak memory 207460 kb
Host smart-dd90d007-d2fc-49bf-b853-b0078eb4e129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28864
68161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2886468161
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.258063537
Short name T1166
Test name
Test status
Simulation time 152604810 ps
CPU time 0.89 seconds
Started Aug 17 06:08:30 PM PDT 24
Finished Aug 17 06:08:31 PM PDT 24
Peak memory 207532 kb
Host smart-b655914a-1273-4f1f-b6b0-0f6b94c854d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25806
3537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.258063537
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2214595185
Short name T1762
Test name
Test status
Simulation time 150215906 ps
CPU time 0.84 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:34 PM PDT 24
Peak memory 207480 kb
Host smart-002e280e-cc2e-4a7c-b323-f529376e900e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22145
95185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2214595185
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3333929554
Short name T2874
Test name
Test status
Simulation time 363171131 ps
CPU time 1.22 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:34 PM PDT 24
Peak memory 207540 kb
Host smart-a919c41a-3a19-46c8-bd99-d471051b6e03
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3333929554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3333929554
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.4261720340
Short name T2444
Test name
Test status
Simulation time 2963663154 ps
CPU time 25.25 seconds
Started Aug 17 06:08:28 PM PDT 24
Finished Aug 17 06:08:54 PM PDT 24
Peak memory 207756 kb
Host smart-67b984c1-7e72-402b-9191-fd543b8eda6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261720340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.4261720340
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3263050994
Short name T2057
Test name
Test status
Simulation time 567027380 ps
CPU time 1.48 seconds
Started Aug 17 06:08:34 PM PDT 24
Finished Aug 17 06:08:35 PM PDT 24
Peak memory 207528 kb
Host smart-8d277bd1-43f5-4916-b6ef-1873d137c90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32630
50994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3263050994
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3479682894
Short name T1031
Test name
Test status
Simulation time 167296688 ps
CPU time 0.85 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:34 PM PDT 24
Peak memory 207532 kb
Host smart-3e065b45-0ac6-4e0e-be30-b1ab1fc75024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34796
82894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3479682894
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.193304525
Short name T3616
Test name
Test status
Simulation time 37857618 ps
CPU time 0.68 seconds
Started Aug 17 06:08:48 PM PDT 24
Finished Aug 17 06:08:49 PM PDT 24
Peak memory 207428 kb
Host smart-456986c8-ec43-4d1a-93dc-d50e389696d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19330
4525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.193304525
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2862242031
Short name T1847
Test name
Test status
Simulation time 720785163 ps
CPU time 2.02 seconds
Started Aug 17 06:08:35 PM PDT 24
Finished Aug 17 06:08:37 PM PDT 24
Peak memory 207744 kb
Host smart-529ce378-1a86-4ccd-b486-546fd9f4db23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28622
42031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2862242031
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_types.2706746686
Short name T437
Test name
Test status
Simulation time 612690357 ps
CPU time 1.56 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:35 PM PDT 24
Peak memory 207508 kb
Host smart-2025150e-a2fe-4bf3-a48b-ed47be30b1d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2706746686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.2706746686
Directory /workspace/32.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3472904459
Short name T2354
Test name
Test status
Simulation time 302786200 ps
CPU time 2.74 seconds
Started Aug 17 06:08:35 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 207620 kb
Host smart-80919cba-44f5-4700-b1fc-ae491018ea0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34729
04459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3472904459
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1635670415
Short name T2228
Test name
Test status
Simulation time 263100099 ps
CPU time 1.21 seconds
Started Aug 17 06:08:42 PM PDT 24
Finished Aug 17 06:08:43 PM PDT 24
Peak memory 215868 kb
Host smart-4cc6b3c8-48ad-459d-984a-f359a0d98455
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1635670415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1635670415
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2431851062
Short name T3230
Test name
Test status
Simulation time 140664390 ps
CPU time 0.82 seconds
Started Aug 17 06:08:39 PM PDT 24
Finished Aug 17 06:08:40 PM PDT 24
Peak memory 207456 kb
Host smart-691b2ae8-c382-4b61-8985-d1eb7ed6f4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24318
51062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2431851062
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2130493709
Short name T1698
Test name
Test status
Simulation time 225989187 ps
CPU time 1.12 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 207412 kb
Host smart-48f4cb13-6b3c-4bec-976c-62bfdf698839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304
93709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2130493709
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1771361717
Short name T2660
Test name
Test status
Simulation time 2974107080 ps
CPU time 88.78 seconds
Started Aug 17 06:08:32 PM PDT 24
Finished Aug 17 06:10:01 PM PDT 24
Peak memory 218560 kb
Host smart-424907e7-2f82-4dc6-90d7-92f3bc015da2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1771361717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1771361717
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.3613853398
Short name T2827
Test name
Test status
Simulation time 13013730350 ps
CPU time 163.64 seconds
Started Aug 17 06:08:34 PM PDT 24
Finished Aug 17 06:11:17 PM PDT 24
Peak memory 207752 kb
Host smart-60ed8eec-77af-4add-b98d-81d958ba2283
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3613853398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.3613853398
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.277314941
Short name T2792
Test name
Test status
Simulation time 166654896 ps
CPU time 0.87 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:51 PM PDT 24
Peak memory 207500 kb
Host smart-965d61bf-6634-4e5d-80f2-3a86740e531e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27731
4941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.277314941
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3206664629
Short name T1295
Test name
Test status
Simulation time 14289439536 ps
CPU time 24.15 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:09:07 PM PDT 24
Peak memory 207836 kb
Host smart-54694f6b-b7ef-4ba2-93ec-56e8dda3c51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
64629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3206664629
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2438937720
Short name T3341
Test name
Test status
Simulation time 10875976721 ps
CPU time 15.62 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:53 PM PDT 24
Peak memory 207736 kb
Host smart-2dbba159-7c1f-4308-93d0-78ca2ee8904d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24389
37720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2438937720
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1037201856
Short name T2308
Test name
Test status
Simulation time 3788516608 ps
CPU time 109.33 seconds
Started Aug 17 06:08:42 PM PDT 24
Finished Aug 17 06:10:32 PM PDT 24
Peak memory 224136 kb
Host smart-a41613e9-82d9-4fe1-8b91-a577bd075faa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1037201856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1037201856
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.185833704
Short name T1253
Test name
Test status
Simulation time 2360170362 ps
CPU time 25.26 seconds
Started Aug 17 06:08:34 PM PDT 24
Finished Aug 17 06:09:00 PM PDT 24
Peak memory 217684 kb
Host smart-1ef0c293-6c18-4194-9e80-e57f291e4eba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=185833704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.185833704
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1776142606
Short name T115
Test name
Test status
Simulation time 234512394 ps
CPU time 0.99 seconds
Started Aug 17 06:08:38 PM PDT 24
Finished Aug 17 06:08:39 PM PDT 24
Peak memory 207452 kb
Host smart-87ef6f4a-1591-4748-aca7-212d0c76796f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1776142606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1776142606
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1476821817
Short name T2983
Test name
Test status
Simulation time 248522795 ps
CPU time 1.07 seconds
Started Aug 17 06:08:39 PM PDT 24
Finished Aug 17 06:08:40 PM PDT 24
Peak memory 207488 kb
Host smart-9838e9ea-0211-49ad-b204-4af3adcc32f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14768
21817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1476821817
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3195252021
Short name T2368
Test name
Test status
Simulation time 1493089638 ps
CPU time 12.01 seconds
Started Aug 17 06:08:31 PM PDT 24
Finished Aug 17 06:08:43 PM PDT 24
Peak memory 207620 kb
Host smart-fc6f6799-ee1c-46a7-beda-d481077b074c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3195252021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3195252021
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2904600324
Short name T2004
Test name
Test status
Simulation time 155392421 ps
CPU time 0.87 seconds
Started Aug 17 06:08:47 PM PDT 24
Finished Aug 17 06:08:48 PM PDT 24
Peak memory 207492 kb
Host smart-708b707b-e7be-4e58-8c4d-aee6a6bdaa12
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2904600324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2904600324
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3380044756
Short name T2302
Test name
Test status
Simulation time 174182926 ps
CPU time 0.89 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:34 PM PDT 24
Peak memory 207496 kb
Host smart-15346d25-4504-4f5e-9b2a-edb08fa27002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33800
44756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3380044756
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2100406555
Short name T2482
Test name
Test status
Simulation time 200715906 ps
CPU time 0.99 seconds
Started Aug 17 06:08:36 PM PDT 24
Finished Aug 17 06:08:37 PM PDT 24
Peak memory 207420 kb
Host smart-e78ee115-ca52-42eb-96a0-6525fa268bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21004
06555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2100406555
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.820282683
Short name T3615
Test name
Test status
Simulation time 175477802 ps
CPU time 0.9 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 207424 kb
Host smart-137fc54e-34fa-42fc-9b4c-d7ea95d15d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82028
2683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.820282683
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2324733022
Short name T1916
Test name
Test status
Simulation time 174338464 ps
CPU time 0.88 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 207460 kb
Host smart-6521e5dc-af66-4d15-ac98-655587f58057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23247
33022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2324733022
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1601162862
Short name T3178
Test name
Test status
Simulation time 162949689 ps
CPU time 0.84 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:34 PM PDT 24
Peak memory 207560 kb
Host smart-741af0ef-9f27-403c-b304-6b8dfd9e33e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16011
62862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1601162862
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.967439931
Short name T2348
Test name
Test status
Simulation time 184673799 ps
CPU time 0.9 seconds
Started Aug 17 06:08:47 PM PDT 24
Finished Aug 17 06:08:48 PM PDT 24
Peak memory 207584 kb
Host smart-91d88fa0-c024-40dc-ab9d-9bdeb95ac91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96743
9931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.967439931
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3560420480
Short name T2919
Test name
Test status
Simulation time 248465222 ps
CPU time 1.11 seconds
Started Aug 17 06:08:36 PM PDT 24
Finished Aug 17 06:08:37 PM PDT 24
Peak memory 207540 kb
Host smart-e1d4cb0d-054f-4c59-a633-b9d56a0ead78
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3560420480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3560420480
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2877530134
Short name T2370
Test name
Test status
Simulation time 231001192 ps
CPU time 0.93 seconds
Started Aug 17 06:08:35 PM PDT 24
Finished Aug 17 06:08:36 PM PDT 24
Peak memory 207496 kb
Host smart-5cffc014-689d-4180-8243-320ec47796e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28775
30134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2877530134
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3528193280
Short name T1160
Test name
Test status
Simulation time 55003679 ps
CPU time 0.71 seconds
Started Aug 17 06:08:32 PM PDT 24
Finished Aug 17 06:08:32 PM PDT 24
Peak memory 207500 kb
Host smart-6330fb40-6c3e-4356-b922-473ee0bb24d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35281
93280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3528193280
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3147833872
Short name T1935
Test name
Test status
Simulation time 14761145611 ps
CPU time 42.2 seconds
Started Aug 17 06:08:34 PM PDT 24
Finished Aug 17 06:09:17 PM PDT 24
Peak memory 215912 kb
Host smart-1ac9ed4d-1b8f-4109-b4c8-bc28cd2be380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31478
33872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3147833872
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2822024134
Short name T630
Test name
Test status
Simulation time 171100615 ps
CPU time 0.83 seconds
Started Aug 17 06:08:48 PM PDT 24
Finished Aug 17 06:08:49 PM PDT 24
Peak memory 207544 kb
Host smart-45fb027c-c8ec-4e54-8207-a5f404e0881e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28220
24134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2822024134
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3687066538
Short name T3514
Test name
Test status
Simulation time 211561449 ps
CPU time 0.98 seconds
Started Aug 17 06:08:34 PM PDT 24
Finished Aug 17 06:08:35 PM PDT 24
Peak memory 207684 kb
Host smart-64647948-4961-4257-8f49-32af426d3391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36870
66538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3687066538
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.4202806939
Short name T2653
Test name
Test status
Simulation time 163229162 ps
CPU time 0.87 seconds
Started Aug 17 06:08:40 PM PDT 24
Finished Aug 17 06:08:42 PM PDT 24
Peak memory 207476 kb
Host smart-1d8c738d-43ca-4c89-bbb5-1f613038e100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42028
06939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.4202806939
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2475434310
Short name T1141
Test name
Test status
Simulation time 253747108 ps
CPU time 0.95 seconds
Started Aug 17 06:08:39 PM PDT 24
Finished Aug 17 06:08:40 PM PDT 24
Peak memory 207488 kb
Host smart-35ff4d9c-6be9-462b-89a1-a6971f0528b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
34310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2475434310
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2931640806
Short name T2844
Test name
Test status
Simulation time 176765913 ps
CPU time 0.87 seconds
Started Aug 17 06:08:35 PM PDT 24
Finished Aug 17 06:08:36 PM PDT 24
Peak memory 207460 kb
Host smart-0caa0466-1448-4233-8520-6d258a88a178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29316
40806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2931640806
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_rx_full.2060860583
Short name T2643
Test name
Test status
Simulation time 296062485 ps
CPU time 1.23 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:34 PM PDT 24
Peak memory 207472 kb
Host smart-dbd6dd2c-e7ae-4c97-91aa-e9e4e4f57105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20608
60583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.2060860583
Directory /workspace/32.usbdev_rx_full/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1455670707
Short name T2336
Test name
Test status
Simulation time 185778805 ps
CPU time 0.9 seconds
Started Aug 17 06:08:32 PM PDT 24
Finished Aug 17 06:08:33 PM PDT 24
Peak memory 207532 kb
Host smart-c8cbcf29-cf28-4439-bf50-99a0908b3425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14556
70707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1455670707
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1761462853
Short name T1345
Test name
Test status
Simulation time 149493121 ps
CPU time 0.85 seconds
Started Aug 17 06:08:35 PM PDT 24
Finished Aug 17 06:08:36 PM PDT 24
Peak memory 207348 kb
Host smart-5f198914-ec23-4ddb-ab15-be3019510f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17614
62853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1761462853
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1644670223
Short name T780
Test name
Test status
Simulation time 249314783 ps
CPU time 1.07 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 207412 kb
Host smart-ffe03e8f-c132-4b00-ac38-82d431e583a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16446
70223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1644670223
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.4040272295
Short name T1170
Test name
Test status
Simulation time 3131052271 ps
CPU time 27.42 seconds
Started Aug 17 06:08:41 PM PDT 24
Finished Aug 17 06:09:09 PM PDT 24
Peak memory 217992 kb
Host smart-ce693257-437d-4dd5-8a8c-f0ba7aa44ed9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4040272295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.4040272295
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2893190349
Short name T1061
Test name
Test status
Simulation time 177974055 ps
CPU time 0.89 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:34 PM PDT 24
Peak memory 207484 kb
Host smart-e6374b1f-0598-4a6f-8af0-a6e3c4bcc433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28931
90349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2893190349
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2991592393
Short name T379
Test name
Test status
Simulation time 223895332 ps
CPU time 0.96 seconds
Started Aug 17 06:08:38 PM PDT 24
Finished Aug 17 06:08:39 PM PDT 24
Peak memory 207560 kb
Host smart-2fbd5d69-af3a-4b49-8329-78d12b24f5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
92393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2991592393
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.231320515
Short name T769
Test name
Test status
Simulation time 1340023494 ps
CPU time 3.54 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:40 PM PDT 24
Peak memory 207796 kb
Host smart-a7e4fc55-c027-4313-8204-91527cd9643c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23132
0515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.231320515
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2776953983
Short name T2355
Test name
Test status
Simulation time 2451824365 ps
CPU time 70.97 seconds
Started Aug 17 06:08:36 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 217748 kb
Host smart-400ed16d-d66c-4b45-b9dc-f8dba2e3aedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27769
53983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2776953983
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.4230599668
Short name T2857
Test name
Test status
Simulation time 1433316277 ps
CPU time 33.86 seconds
Started Aug 17 06:08:34 PM PDT 24
Finished Aug 17 06:09:08 PM PDT 24
Peak memory 207672 kb
Host smart-c222b35a-0d0e-46a9-a7a3-36696c55ea48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230599668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.4230599668
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_tx_rx_disruption.2961241149
Short name T2536
Test name
Test status
Simulation time 536642145 ps
CPU time 1.73 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:35 PM PDT 24
Peak memory 207784 kb
Host smart-156ff664-a28b-4c46-a291-ade445869011
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961241149 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.usbdev_tx_rx_disruption.2961241149
Directory /workspace/32.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/320.usbdev_tx_rx_disruption.400615396
Short name T3154
Test name
Test status
Simulation time 708352201 ps
CPU time 1.96 seconds
Started Aug 17 06:12:16 PM PDT 24
Finished Aug 17 06:12:18 PM PDT 24
Peak memory 207584 kb
Host smart-d74fe7cd-e96f-44e0-bd38-46a5922b48ab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400615396 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 320.usbdev_tx_rx_disruption.400615396
Directory /workspace/320.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/321.usbdev_tx_rx_disruption.2626441742
Short name T1998
Test name
Test status
Simulation time 416786216 ps
CPU time 1.38 seconds
Started Aug 17 06:12:12 PM PDT 24
Finished Aug 17 06:12:13 PM PDT 24
Peak memory 207544 kb
Host smart-f3cc5a69-0150-4cb9-8ff5-b6984c31d0bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626441742 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 321.usbdev_tx_rx_disruption.2626441742
Directory /workspace/321.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/322.usbdev_tx_rx_disruption.3950434192
Short name T2446
Test name
Test status
Simulation time 493830076 ps
CPU time 1.71 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207504 kb
Host smart-c49a2a1c-2ce2-4af5-893f-7b9c3219a219
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950434192 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 322.usbdev_tx_rx_disruption.3950434192
Directory /workspace/322.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/323.usbdev_tx_rx_disruption.3466837100
Short name T2385
Test name
Test status
Simulation time 548417021 ps
CPU time 1.72 seconds
Started Aug 17 06:12:15 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207576 kb
Host smart-29c943df-495e-4c31-a145-77e1cc5b0831
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466837100 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 323.usbdev_tx_rx_disruption.3466837100
Directory /workspace/323.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/324.usbdev_tx_rx_disruption.1490257302
Short name T837
Test name
Test status
Simulation time 607086693 ps
CPU time 1.63 seconds
Started Aug 17 06:12:17 PM PDT 24
Finished Aug 17 06:12:18 PM PDT 24
Peak memory 207560 kb
Host smart-be17b038-186c-44bb-b8e9-651652627d9d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490257302 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 324.usbdev_tx_rx_disruption.1490257302
Directory /workspace/324.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/325.usbdev_tx_rx_disruption.3813787287
Short name T3554
Test name
Test status
Simulation time 476082661 ps
CPU time 1.69 seconds
Started Aug 17 06:12:16 PM PDT 24
Finished Aug 17 06:12:18 PM PDT 24
Peak memory 207548 kb
Host smart-66bbc7e0-b132-4226-b1b9-3122643a70d6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813787287 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 325.usbdev_tx_rx_disruption.3813787287
Directory /workspace/325.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/326.usbdev_tx_rx_disruption.3154585428
Short name T1538
Test name
Test status
Simulation time 658529923 ps
CPU time 1.84 seconds
Started Aug 17 06:12:17 PM PDT 24
Finished Aug 17 06:12:19 PM PDT 24
Peak memory 207560 kb
Host smart-aa3ce7ee-cc10-4ebb-bf9d-866f81036eb2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154585428 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 326.usbdev_tx_rx_disruption.3154585428
Directory /workspace/326.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/327.usbdev_tx_rx_disruption.193925005
Short name T2280
Test name
Test status
Simulation time 537199491 ps
CPU time 1.66 seconds
Started Aug 17 06:12:17 PM PDT 24
Finished Aug 17 06:12:19 PM PDT 24
Peak memory 207552 kb
Host smart-019c063b-9ce8-4ad0-b37e-e89867cef1f6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193925005 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 327.usbdev_tx_rx_disruption.193925005
Directory /workspace/327.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/328.usbdev_tx_rx_disruption.1161738434
Short name T1512
Test name
Test status
Simulation time 481206478 ps
CPU time 1.43 seconds
Started Aug 17 06:12:22 PM PDT 24
Finished Aug 17 06:12:24 PM PDT 24
Peak memory 207500 kb
Host smart-e03d4c66-3bbd-4254-86ae-d58a9c28cbf3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161738434 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 328.usbdev_tx_rx_disruption.1161738434
Directory /workspace/328.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/329.usbdev_tx_rx_disruption.2241930882
Short name T2099
Test name
Test status
Simulation time 571475280 ps
CPU time 1.69 seconds
Started Aug 17 06:12:18 PM PDT 24
Finished Aug 17 06:12:20 PM PDT 24
Peak memory 207532 kb
Host smart-51cdd4de-f3dd-46f5-9844-e09068d798a4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241930882 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 329.usbdev_tx_rx_disruption.2241930882
Directory /workspace/329.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.2455640552
Short name T1147
Test name
Test status
Simulation time 145960551 ps
CPU time 0.78 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:51 PM PDT 24
Peak memory 207428 kb
Host smart-32b7d8fe-cb74-4512-8adf-5c94f2d58afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2455640552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.2455640552
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1029260215
Short name T1297
Test name
Test status
Simulation time 5131531014 ps
CPU time 7.54 seconds
Started Aug 17 06:08:38 PM PDT 24
Finished Aug 17 06:08:46 PM PDT 24
Peak memory 216016 kb
Host smart-87dd2f96-8a85-4f07-a33c-5b5f5614f2e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029260215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.1029260215
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1567696340
Short name T1085
Test name
Test status
Simulation time 29659872592 ps
CPU time 34.43 seconds
Started Aug 17 06:08:40 PM PDT 24
Finished Aug 17 06:09:14 PM PDT 24
Peak memory 207828 kb
Host smart-a856df0b-8972-4d78-85a8-d46d8e71c4d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567696340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.1567696340
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3711092576
Short name T1109
Test name
Test status
Simulation time 172841190 ps
CPU time 0.91 seconds
Started Aug 17 06:08:38 PM PDT 24
Finished Aug 17 06:08:39 PM PDT 24
Peak memory 207516 kb
Host smart-7a879e7e-dfb1-4cc7-9fe4-aa4aae7d21be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37110
92576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3711092576
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.1673686901
Short name T1621
Test name
Test status
Simulation time 147215808 ps
CPU time 0.82 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 207444 kb
Host smart-79147e31-f2a9-4637-85a4-24671c6a9175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16736
86901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.1673686901
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3881382552
Short name T804
Test name
Test status
Simulation time 411996095 ps
CPU time 1.58 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:35 PM PDT 24
Peak memory 207564 kb
Host smart-90cc557f-ffb0-4285-a4fd-5c189b2f7102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38813
82552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3881382552
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.289874878
Short name T1495
Test name
Test status
Simulation time 1319697563 ps
CPU time 3.26 seconds
Started Aug 17 06:08:42 PM PDT 24
Finished Aug 17 06:08:45 PM PDT 24
Peak memory 207740 kb
Host smart-86bd322d-3bbe-4c5c-8ac4-87db3707b472
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=289874878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.289874878
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.2879377870
Short name T3210
Test name
Test status
Simulation time 1037137714 ps
CPU time 23.19 seconds
Started Aug 17 06:08:47 PM PDT 24
Finished Aug 17 06:09:10 PM PDT 24
Peak memory 207744 kb
Host smart-bb73ec52-ca2c-4c2e-aafa-ce77f1becc13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879377870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.2879377870
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3118784078
Short name T1845
Test name
Test status
Simulation time 673548696 ps
CPU time 1.75 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:39 PM PDT 24
Peak memory 207392 kb
Host smart-16fad49d-5fcb-448b-9e3e-9f7bed23c6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31187
84078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3118784078
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.637092159
Short name T39
Test name
Test status
Simulation time 133282904 ps
CPU time 0.82 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 207532 kb
Host smart-ce530303-b16f-42db-925f-5cfb7a4f5261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63709
2159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.637092159
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2930282689
Short name T1892
Test name
Test status
Simulation time 72174713 ps
CPU time 0.74 seconds
Started Aug 17 06:08:39 PM PDT 24
Finished Aug 17 06:08:39 PM PDT 24
Peak memory 207384 kb
Host smart-7ca3876c-a808-4ee9-86ec-1f566e55cf7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29302
82689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2930282689
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.3325987124
Short name T695
Test name
Test status
Simulation time 910153416 ps
CPU time 2.58 seconds
Started Aug 17 06:08:33 PM PDT 24
Finished Aug 17 06:08:36 PM PDT 24
Peak memory 207696 kb
Host smart-5b6ea915-2196-463e-8f3c-aedab3bdccb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33259
87124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.3325987124
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_types.511147767
Short name T2256
Test name
Test status
Simulation time 269055500 ps
CPU time 1.07 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 207520 kb
Host smart-73f1cdb3-8d5f-48aa-b27e-9ef07d207fea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=511147767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.511147767
Directory /workspace/33.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3268953714
Short name T1428
Test name
Test status
Simulation time 190766547 ps
CPU time 1.75 seconds
Started Aug 17 06:08:42 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 207628 kb
Host smart-4b7ba118-58ea-48f8-b882-70ab57d3ef35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32689
53714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3268953714
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.675334799
Short name T1159
Test name
Test status
Simulation time 210773406 ps
CPU time 1.11 seconds
Started Aug 17 06:08:44 PM PDT 24
Finished Aug 17 06:08:45 PM PDT 24
Peak memory 215884 kb
Host smart-e4554fa4-47a7-4137-8e00-5ac893b39993
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=675334799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.675334799
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1800945904
Short name T1173
Test name
Test status
Simulation time 156453713 ps
CPU time 0.84 seconds
Started Aug 17 06:08:48 PM PDT 24
Finished Aug 17 06:08:49 PM PDT 24
Peak memory 207432 kb
Host smart-1c6e6d59-e06c-40f2-abf5-a6c34186f317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18009
45904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1800945904
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.362440337
Short name T3438
Test name
Test status
Simulation time 175789069 ps
CPU time 0.91 seconds
Started Aug 17 06:08:41 PM PDT 24
Finished Aug 17 06:08:42 PM PDT 24
Peak memory 207488 kb
Host smart-aed89785-7a85-4aff-a6b4-de8ab9fe0529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36244
0337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.362440337
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1881514196
Short name T2030
Test name
Test status
Simulation time 2751087620 ps
CPU time 27.73 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:09:05 PM PDT 24
Peak memory 218116 kb
Host smart-d70fab10-5a67-4fee-9956-977097d8b9e0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1881514196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1881514196
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2243362052
Short name T2893
Test name
Test status
Simulation time 12765298462 ps
CPU time 91.2 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:10:08 PM PDT 24
Peak memory 207632 kb
Host smart-069f8f05-b714-4690-8578-898559174bdf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2243362052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2243362052
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3747533296
Short name T1681
Test name
Test status
Simulation time 185419808 ps
CPU time 0.97 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:38 PM PDT 24
Peak memory 207548 kb
Host smart-68945cd0-0c1c-4b22-857d-329874b9b901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37475
33296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3747533296
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1885892935
Short name T1855
Test name
Test status
Simulation time 7681202146 ps
CPU time 12.07 seconds
Started Aug 17 06:08:37 PM PDT 24
Finished Aug 17 06:08:49 PM PDT 24
Peak memory 216016 kb
Host smart-da10ef9c-ef00-4fa4-b0b5-07dac75fb749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18858
92935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1885892935
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3987202472
Short name T856
Test name
Test status
Simulation time 9356414177 ps
CPU time 12.01 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:09:02 PM PDT 24
Peak memory 207820 kb
Host smart-5a14953f-4f1d-4f87-a2aa-c888694af0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39872
02472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3987202472
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.95047824
Short name T926
Test name
Test status
Simulation time 2660904206 ps
CPU time 26.25 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:09:09 PM PDT 24
Peak memory 215992 kb
Host smart-715235f4-2bc2-4262-a68a-da70ea3c716c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=95047824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.95047824
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.114481115
Short name T2810
Test name
Test status
Simulation time 244384158 ps
CPU time 0.95 seconds
Started Aug 17 06:08:32 PM PDT 24
Finished Aug 17 06:08:33 PM PDT 24
Peak memory 207452 kb
Host smart-c40dad6d-79dd-4e33-bcb3-aec101c139fe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=114481115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.114481115
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.121703918
Short name T1175
Test name
Test status
Simulation time 188177751 ps
CPU time 0.98 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 207348 kb
Host smart-cd690dc8-74ac-4b9d-a27a-54f68b9741a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12170
3918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.121703918
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1241923043
Short name T1603
Test name
Test status
Simulation time 1893909441 ps
CPU time 21.74 seconds
Started Aug 17 06:08:52 PM PDT 24
Finished Aug 17 06:09:14 PM PDT 24
Peak memory 217140 kb
Host smart-7978838f-0285-4c9d-913d-6340d0f35aae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1241923043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1241923043
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3413969947
Short name T2619
Test name
Test status
Simulation time 234358738 ps
CPU time 0.89 seconds
Started Aug 17 06:08:40 PM PDT 24
Finished Aug 17 06:08:41 PM PDT 24
Peak memory 207408 kb
Host smart-ff6c3e7f-8ae0-4f16-9b7b-6d576d666356
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3413969947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3413969947
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1373160297
Short name T2590
Test name
Test status
Simulation time 181423428 ps
CPU time 0.9 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 207472 kb
Host smart-0457d043-991c-4ef1-8e42-4a2245426850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13731
60297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1373160297
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3696044916
Short name T149
Test name
Test status
Simulation time 236550600 ps
CPU time 1.03 seconds
Started Aug 17 06:08:47 PM PDT 24
Finished Aug 17 06:08:48 PM PDT 24
Peak memory 207476 kb
Host smart-30572176-4e69-4f06-a306-84bd2c9b520d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36960
44916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3696044916
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.1981556039
Short name T3355
Test name
Test status
Simulation time 152338608 ps
CPU time 0.89 seconds
Started Aug 17 06:08:40 PM PDT 24
Finished Aug 17 06:08:41 PM PDT 24
Peak memory 207424 kb
Host smart-e48b5ece-886d-404a-920f-340a50a2b328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815
56039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.1981556039
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2544469640
Short name T21
Test name
Test status
Simulation time 178447674 ps
CPU time 0.89 seconds
Started Aug 17 06:09:00 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207428 kb
Host smart-14bc95f4-2239-4745-b950-44e3ed10ed87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25444
69640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2544469640
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2188218361
Short name T3581
Test name
Test status
Simulation time 184085914 ps
CPU time 0.98 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 207520 kb
Host smart-abf51f67-6595-4441-854a-93b5e480586a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21882
18361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2188218361
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3861294092
Short name T2988
Test name
Test status
Simulation time 194959915 ps
CPU time 0.91 seconds
Started Aug 17 06:08:42 PM PDT 24
Finished Aug 17 06:08:43 PM PDT 24
Peak memory 207548 kb
Host smart-2a634bcf-6d3c-440b-9ff5-7e5cc6f5dcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38612
94092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3861294092
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2495128442
Short name T788
Test name
Test status
Simulation time 203548549 ps
CPU time 1 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:45 PM PDT 24
Peak memory 207556 kb
Host smart-66b58333-3117-4dd3-bd57-c2d379ae596b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2495128442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2495128442
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.916418216
Short name T2034
Test name
Test status
Simulation time 141453978 ps
CPU time 0.81 seconds
Started Aug 17 06:08:44 PM PDT 24
Finished Aug 17 06:08:45 PM PDT 24
Peak memory 207448 kb
Host smart-38f5d220-8f8d-4e2b-ad43-90889b6f2fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91641
8216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.916418216
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1301935206
Short name T18
Test name
Test status
Simulation time 35741825 ps
CPU time 0.67 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:08:50 PM PDT 24
Peak memory 207508 kb
Host smart-591c3e29-85c9-4bcb-ac48-bb664bbaf583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13019
35206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1301935206
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3081786811
Short name T1362
Test name
Test status
Simulation time 8118515521 ps
CPU time 20.57 seconds
Started Aug 17 06:08:40 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 215884 kb
Host smart-a11f6347-dc95-4f22-8b8b-ab4014d1ab06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30817
86811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3081786811
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1948642348
Short name T3080
Test name
Test status
Simulation time 180249075 ps
CPU time 0.96 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:51 PM PDT 24
Peak memory 207552 kb
Host smart-90208065-ad13-4913-be6a-e9c50a819482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19486
42348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1948642348
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1286731371
Short name T2993
Test name
Test status
Simulation time 215727328 ps
CPU time 0.93 seconds
Started Aug 17 06:08:53 PM PDT 24
Finished Aug 17 06:08:54 PM PDT 24
Peak memory 207384 kb
Host smart-0eda134e-7e2d-4796-a0ea-0d33cc253ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12867
31371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1286731371
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.1450281842
Short name T3086
Test name
Test status
Simulation time 221225190 ps
CPU time 0.97 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:51 PM PDT 24
Peak memory 207520 kb
Host smart-8fb68a4d-407e-405b-9279-80e9430827bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14502
81842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.1450281842
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.1042008070
Short name T870
Test name
Test status
Simulation time 199930814 ps
CPU time 0.98 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 207460 kb
Host smart-8a414049-aa7e-489c-ae39-4af1eb4bd73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10420
08070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1042008070
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1614651221
Short name T2990
Test name
Test status
Simulation time 170566054 ps
CPU time 0.84 seconds
Started Aug 17 06:08:41 PM PDT 24
Finished Aug 17 06:08:42 PM PDT 24
Peak memory 206380 kb
Host smart-f1584734-4540-409f-9dbd-65d8ff47cbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16146
51221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1614651221
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_rx_full.762787886
Short name T331
Test name
Test status
Simulation time 371690877 ps
CPU time 1.4 seconds
Started Aug 17 06:08:51 PM PDT 24
Finished Aug 17 06:08:52 PM PDT 24
Peak memory 207456 kb
Host smart-44a1324f-733a-4aa5-8381-0dd4e46cc2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76278
7886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.762787886
Directory /workspace/33.usbdev_rx_full/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1852405779
Short name T3329
Test name
Test status
Simulation time 149747329 ps
CPU time 0.84 seconds
Started Aug 17 06:08:55 PM PDT 24
Finished Aug 17 06:08:56 PM PDT 24
Peak memory 207472 kb
Host smart-e9c97f7f-d601-47fc-ada7-922e776852b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18524
05779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1852405779
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3876268829
Short name T1325
Test name
Test status
Simulation time 164340524 ps
CPU time 0.85 seconds
Started Aug 17 06:08:48 PM PDT 24
Finished Aug 17 06:08:49 PM PDT 24
Peak memory 207472 kb
Host smart-429dbdd6-e9bd-4ae9-a136-eb87372256ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38762
68829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3876268829
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.4196645483
Short name T1389
Test name
Test status
Simulation time 267426063 ps
CPU time 1.08 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 207480 kb
Host smart-9f8336da-3db2-4e2c-9f44-d5379291bd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41966
45483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.4196645483
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1033693598
Short name T959
Test name
Test status
Simulation time 2918575890 ps
CPU time 88.35 seconds
Started Aug 17 06:08:51 PM PDT 24
Finished Aug 17 06:10:20 PM PDT 24
Peak memory 215888 kb
Host smart-72a37736-3aaf-4384-83f3-81a56cbbec38
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1033693598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1033693598
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1330113081
Short name T2199
Test name
Test status
Simulation time 177375926 ps
CPU time 0.86 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:08:50 PM PDT 24
Peak memory 207472 kb
Host smart-abe3d172-6259-4fb6-b310-9b5e3940618d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13301
13081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1330113081
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.363801299
Short name T1508
Test name
Test status
Simulation time 166036778 ps
CPU time 0.97 seconds
Started Aug 17 06:08:51 PM PDT 24
Finished Aug 17 06:08:53 PM PDT 24
Peak memory 207432 kb
Host smart-0ee16026-2c4c-4fd1-826a-76b72417128e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36380
1299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.363801299
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.344916227
Short name T1079
Test name
Test status
Simulation time 1338117026 ps
CPU time 3.36 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:46 PM PDT 24
Peak memory 207720 kb
Host smart-70004e76-23bf-4481-9f08-ca7307b8b50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491
6227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.344916227
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.2114142740
Short name T1770
Test name
Test status
Simulation time 2145177607 ps
CPU time 60.88 seconds
Started Aug 17 06:08:47 PM PDT 24
Finished Aug 17 06:09:48 PM PDT 24
Peak memory 215808 kb
Host smart-2d81c9d2-098d-464c-b5ac-83028813a489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21141
42740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.2114142740
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.1118546408
Short name T1400
Test name
Test status
Simulation time 1543396491 ps
CPU time 9.8 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:08:58 PM PDT 24
Peak memory 207736 kb
Host smart-a6b080e2-7207-45bc-aa1f-538fd21c36cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118546408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.1118546408
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_tx_rx_disruption.3388962446
Short name T934
Test name
Test status
Simulation time 472233223 ps
CPU time 1.46 seconds
Started Aug 17 06:08:45 PM PDT 24
Finished Aug 17 06:08:46 PM PDT 24
Peak memory 207784 kb
Host smart-9a38da35-b9ff-4f5b-bd9a-b07c6719f96a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388962446 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.usbdev_tx_rx_disruption.3388962446
Directory /workspace/33.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/330.usbdev_tx_rx_disruption.2236330198
Short name T212
Test name
Test status
Simulation time 452201296 ps
CPU time 1.54 seconds
Started Aug 17 06:12:24 PM PDT 24
Finished Aug 17 06:12:26 PM PDT 24
Peak memory 207584 kb
Host smart-4d94115d-0d48-4b5c-a1bc-bdcc5719159c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236330198 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 330.usbdev_tx_rx_disruption.2236330198
Directory /workspace/330.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/331.usbdev_tx_rx_disruption.410308695
Short name T2679
Test name
Test status
Simulation time 595260016 ps
CPU time 1.73 seconds
Started Aug 17 06:12:05 PM PDT 24
Finished Aug 17 06:12:07 PM PDT 24
Peak memory 207508 kb
Host smart-67df0b8c-dd63-4cba-b154-0fe2236b69e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410308695 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 331.usbdev_tx_rx_disruption.410308695
Directory /workspace/331.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/332.usbdev_tx_rx_disruption.2364994038
Short name T1623
Test name
Test status
Simulation time 578000454 ps
CPU time 1.7 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207556 kb
Host smart-106d7fec-1378-4bba-880b-a049410d7928
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364994038 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 332.usbdev_tx_rx_disruption.2364994038
Directory /workspace/332.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/333.usbdev_tx_rx_disruption.298543769
Short name T1786
Test name
Test status
Simulation time 585329917 ps
CPU time 1.54 seconds
Started Aug 17 06:12:08 PM PDT 24
Finished Aug 17 06:12:10 PM PDT 24
Peak memory 207568 kb
Host smart-06f9f50b-478a-4439-9410-9a7930246e02
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298543769 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 333.usbdev_tx_rx_disruption.298543769
Directory /workspace/333.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/334.usbdev_tx_rx_disruption.7124549
Short name T199
Test name
Test status
Simulation time 403034711 ps
CPU time 1.36 seconds
Started Aug 17 06:12:05 PM PDT 24
Finished Aug 17 06:12:06 PM PDT 24
Peak memory 207508 kb
Host smart-eb4e9431-2e78-478d-bee7-59d0ca26337e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7124549 -assert nopostproc +UVM_TESTN
AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 334.usbdev_tx_rx_disruption.7124549
Directory /workspace/334.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/335.usbdev_tx_rx_disruption.2976222290
Short name T2000
Test name
Test status
Simulation time 607649603 ps
CPU time 1.63 seconds
Started Aug 17 06:12:17 PM PDT 24
Finished Aug 17 06:12:19 PM PDT 24
Peak memory 207540 kb
Host smart-4c2136ed-c67e-4bfc-98f1-3db2228a9d72
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976222290 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 335.usbdev_tx_rx_disruption.2976222290
Directory /workspace/335.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/336.usbdev_tx_rx_disruption.783128156
Short name T2188
Test name
Test status
Simulation time 483455738 ps
CPU time 1.5 seconds
Started Aug 17 06:12:05 PM PDT 24
Finished Aug 17 06:12:06 PM PDT 24
Peak memory 207572 kb
Host smart-1874db38-d8ad-464b-a847-b2b4b2f504d4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783128156 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 336.usbdev_tx_rx_disruption.783128156
Directory /workspace/336.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/337.usbdev_tx_rx_disruption.1255726214
Short name T2594
Test name
Test status
Simulation time 509320515 ps
CPU time 1.58 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207576 kb
Host smart-0724dc9f-c732-44d2-8d81-64ab85e35ddb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255726214 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 337.usbdev_tx_rx_disruption.1255726214
Directory /workspace/337.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/338.usbdev_tx_rx_disruption.3769564360
Short name T3200
Test name
Test status
Simulation time 466795134 ps
CPU time 1.58 seconds
Started Aug 17 06:12:33 PM PDT 24
Finished Aug 17 06:12:35 PM PDT 24
Peak memory 207500 kb
Host smart-39c2d21d-46ff-46ae-bb31-a1d730bfb3a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769564360 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 338.usbdev_tx_rx_disruption.3769564360
Directory /workspace/338.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/339.usbdev_tx_rx_disruption.3246741478
Short name T3248
Test name
Test status
Simulation time 441875057 ps
CPU time 1.48 seconds
Started Aug 17 06:12:15 PM PDT 24
Finished Aug 17 06:12:17 PM PDT 24
Peak memory 207548 kb
Host smart-20c5947b-e5c6-43d8-8979-f068ba65a209
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246741478 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 339.usbdev_tx_rx_disruption.3246741478
Directory /workspace/339.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.771072653
Short name T1329
Test name
Test status
Simulation time 39407507 ps
CPU time 0.67 seconds
Started Aug 17 06:09:01 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207408 kb
Host smart-d96c75cb-ee0b-4605-9556-31b891f8a63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=771072653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.771072653
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.816683322
Short name T3165
Test name
Test status
Simulation time 10089557091 ps
CPU time 12.97 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:56 PM PDT 24
Peak memory 207800 kb
Host smart-1909ab48-8fcb-4475-b829-477932e25012
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816683322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_ao
n_wake_disconnect.816683322
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.175838148
Short name T2458
Test name
Test status
Simulation time 13459886247 ps
CPU time 18.72 seconds
Started Aug 17 06:08:48 PM PDT 24
Finished Aug 17 06:09:07 PM PDT 24
Peak memory 215968 kb
Host smart-1f0e98cd-392c-4cc1-9c07-c4c114ddd871
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=175838148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.175838148
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3628438078
Short name T1730
Test name
Test status
Simulation time 29858338500 ps
CPU time 36.87 seconds
Started Aug 17 06:08:45 PM PDT 24
Finished Aug 17 06:09:22 PM PDT 24
Peak memory 207776 kb
Host smart-039998b4-929f-40f6-a1b8-6545576d6344
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628438078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.3628438078
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.61999429
Short name T564
Test name
Test status
Simulation time 245534068 ps
CPU time 1 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 207476 kb
Host smart-a1a3e807-3e8f-4d31-b078-d211d42857a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61999
429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.61999429
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.4010459900
Short name T2238
Test name
Test status
Simulation time 180287452 ps
CPU time 0.89 seconds
Started Aug 17 06:08:46 PM PDT 24
Finished Aug 17 06:08:47 PM PDT 24
Peak memory 207536 kb
Host smart-778ab70a-973a-472b-83b9-2c1363197c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40104
59900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.4010459900
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1972329093
Short name T635
Test name
Test status
Simulation time 419988165 ps
CPU time 1.54 seconds
Started Aug 17 06:08:59 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207552 kb
Host smart-6efb9376-337c-413b-aa1f-833d044f3174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19723
29093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1972329093
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3286294146
Short name T341
Test name
Test status
Simulation time 525713745 ps
CPU time 1.67 seconds
Started Aug 17 06:08:55 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 207468 kb
Host smart-d582f593-eb7b-49c1-88f8-76ab69d7f47c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3286294146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3286294146
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1682797729
Short name T133
Test name
Test status
Simulation time 48198812737 ps
CPU time 77.22 seconds
Started Aug 17 06:08:47 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 207808 kb
Host smart-daf7b6d4-e71f-4354-a6c5-046bd4f191a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16827
97729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1682797729
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.237493988
Short name T3605
Test name
Test status
Simulation time 155396246 ps
CPU time 0.87 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:08:50 PM PDT 24
Peak memory 207508 kb
Host smart-a97d5aba-fa66-41b5-b66a-9b8d6de46804
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237493988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.237493988
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1547715098
Short name T387
Test name
Test status
Simulation time 909685107 ps
CPU time 2.15 seconds
Started Aug 17 06:08:54 PM PDT 24
Finished Aug 17 06:08:56 PM PDT 24
Peak memory 207500 kb
Host smart-0c7c36c6-158c-4eb9-bcea-3f249bfa8370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
15098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1547715098
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.554848675
Short name T2076
Test name
Test status
Simulation time 137394302 ps
CPU time 0.89 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 207404 kb
Host smart-1c243d59-9ad1-49fe-abe5-e2a685f64786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55484
8675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.554848675
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1579861574
Short name T2987
Test name
Test status
Simulation time 66917075 ps
CPU time 0.75 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:44 PM PDT 24
Peak memory 207380 kb
Host smart-98785ed5-895d-4914-8ffc-0a1c752a8143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15798
61574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1579861574
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1603019503
Short name T1859
Test name
Test status
Simulation time 962653868 ps
CPU time 2.87 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:08:46 PM PDT 24
Peak memory 207772 kb
Host smart-06af3b9c-7f7b-4a88-86ef-bd3918658d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16030
19503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1603019503
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.345298464
Short name T1278
Test name
Test status
Simulation time 169810623 ps
CPU time 1.58 seconds
Started Aug 17 06:08:41 PM PDT 24
Finished Aug 17 06:08:43 PM PDT 24
Peak memory 207536 kb
Host smart-9fece5f9-0ddd-47b9-b684-7db40347741b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
8464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.345298464
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.981626378
Short name T3222
Test name
Test status
Simulation time 239411384 ps
CPU time 1.23 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:08:50 PM PDT 24
Peak memory 216096 kb
Host smart-5d14894e-3df4-4631-a7d8-49d05a518dd9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=981626378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.981626378
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1566255822
Short name T1610
Test name
Test status
Simulation time 139995266 ps
CPU time 0.87 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:08:50 PM PDT 24
Peak memory 207420 kb
Host smart-a7c8a632-fd3f-4dae-87f5-289a325e6458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15662
55822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1566255822
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2947150900
Short name T767
Test name
Test status
Simulation time 183006991 ps
CPU time 0.93 seconds
Started Aug 17 06:08:51 PM PDT 24
Finished Aug 17 06:08:52 PM PDT 24
Peak memory 207428 kb
Host smart-7c4bfe6f-7e35-427c-8507-5ba754724ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29471
50900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2947150900
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2006061605
Short name T1415
Test name
Test status
Simulation time 5221136536 ps
CPU time 52.15 seconds
Started Aug 17 06:08:46 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 218308 kb
Host smart-255364d8-76f7-45f6-9b1b-874f40a7bb23
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2006061605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2006061605
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.3371562944
Short name T932
Test name
Test status
Simulation time 11515466900 ps
CPU time 90.57 seconds
Started Aug 17 06:08:44 PM PDT 24
Finished Aug 17 06:10:15 PM PDT 24
Peak memory 207824 kb
Host smart-1db72e19-e1db-42c6-b977-ae3abebdbb22
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3371562944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3371562944
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1682401587
Short name T802
Test name
Test status
Simulation time 181192890 ps
CPU time 0.91 seconds
Started Aug 17 06:08:47 PM PDT 24
Finished Aug 17 06:08:48 PM PDT 24
Peak memory 207544 kb
Host smart-87937cf9-02d5-4406-b047-08d7d194663f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16824
01587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1682401587
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1023852786
Short name T602
Test name
Test status
Simulation time 34023076713 ps
CPU time 53.37 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:09:48 PM PDT 24
Peak memory 207792 kb
Host smart-21966645-f360-423f-93eb-28069353739d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10238
52786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1023852786
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.4092119289
Short name T3072
Test name
Test status
Simulation time 4347507106 ps
CPU time 5.85 seconds
Started Aug 17 06:08:59 PM PDT 24
Finished Aug 17 06:09:05 PM PDT 24
Peak memory 216868 kb
Host smart-41831910-26bf-4091-b1b5-819728bbe436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40921
19289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.4092119289
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2331382311
Short name T2541
Test name
Test status
Simulation time 4688568352 ps
CPU time 47.42 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:49 PM PDT 24
Peak memory 219252 kb
Host smart-13573b2b-6459-4096-9e64-73e5984f31b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2331382311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2331382311
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2898096648
Short name T2323
Test name
Test status
Simulation time 2540724662 ps
CPU time 19.7 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:09:09 PM PDT 24
Peak memory 224036 kb
Host smart-518e3bbc-5931-40c0-8ab9-ea6e41665e72
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2898096648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2898096648
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.2107010293
Short name T1343
Test name
Test status
Simulation time 234757660 ps
CPU time 1.06 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:08:50 PM PDT 24
Peak memory 207500 kb
Host smart-99cc57ee-99ab-4578-87ca-4958e0f1c970
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2107010293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2107010293
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.372136453
Short name T3090
Test name
Test status
Simulation time 195082101 ps
CPU time 0.95 seconds
Started Aug 17 06:08:51 PM PDT 24
Finished Aug 17 06:08:52 PM PDT 24
Peak memory 207512 kb
Host smart-60ded1a3-23a5-411a-9f7a-de5aa10a6c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37213
6453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.372136453
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.1008707646
Short name T3328
Test name
Test status
Simulation time 2911004896 ps
CPU time 24.9 seconds
Started Aug 17 06:08:43 PM PDT 24
Finished Aug 17 06:09:08 PM PDT 24
Peak memory 217712 kb
Host smart-28fc1781-f6a4-4a47-9844-d0995f5d50af
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1008707646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.1008707646
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3484875354
Short name T1680
Test name
Test status
Simulation time 157678123 ps
CPU time 0.93 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:52 PM PDT 24
Peak memory 207516 kb
Host smart-f34a0d89-60c7-4522-b049-65ae0216e7e0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3484875354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3484875354
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2489774562
Short name T3037
Test name
Test status
Simulation time 140333937 ps
CPU time 0.85 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:51 PM PDT 24
Peak memory 207452 kb
Host smart-22e72a0b-33ec-4651-84ae-648a7223803a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897
74562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2489774562
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2589944988
Short name T136
Test name
Test status
Simulation time 224596274 ps
CPU time 1.04 seconds
Started Aug 17 06:08:57 PM PDT 24
Finished Aug 17 06:08:58 PM PDT 24
Peak memory 207428 kb
Host smart-9cfc95ae-c4df-44a4-af16-29e9d2cf5d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25899
44988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2589944988
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1412554159
Short name T712
Test name
Test status
Simulation time 171118978 ps
CPU time 0.9 seconds
Started Aug 17 06:08:51 PM PDT 24
Finished Aug 17 06:08:52 PM PDT 24
Peak memory 207428 kb
Host smart-6cba72ca-41d9-406d-ac4a-4c34a9ecc4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14125
54159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1412554159
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.975004644
Short name T542
Test name
Test status
Simulation time 204379828 ps
CPU time 0.9 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:03 PM PDT 24
Peak memory 207428 kb
Host smart-85a183b6-ec77-4f62-80f5-d77fdb12a8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97500
4644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.975004644
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1884452611
Short name T1515
Test name
Test status
Simulation time 197923201 ps
CPU time 0.89 seconds
Started Aug 17 06:08:46 PM PDT 24
Finished Aug 17 06:08:47 PM PDT 24
Peak memory 206484 kb
Host smart-351b9794-bd92-4da0-8a42-302dbe24865d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18844
52611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1884452611
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1281326314
Short name T3461
Test name
Test status
Simulation time 163769258 ps
CPU time 0.91 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:51 PM PDT 24
Peak memory 207568 kb
Host smart-2b1263f5-2a52-49ab-9d4a-c2aea510b354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12813
26314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1281326314
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1727573613
Short name T2194
Test name
Test status
Simulation time 202262930 ps
CPU time 0.95 seconds
Started Aug 17 06:08:42 PM PDT 24
Finished Aug 17 06:08:43 PM PDT 24
Peak memory 207544 kb
Host smart-65a175c3-e3eb-45ce-bf61-6bb6a8287df2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1727573613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1727573613
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1315204252
Short name T3444
Test name
Test status
Simulation time 150712459 ps
CPU time 0.87 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:51 PM PDT 24
Peak memory 207380 kb
Host smart-adb129b9-4579-493f-a40a-0ea0d91a682a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13152
04252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1315204252
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.4228143778
Short name T1471
Test name
Test status
Simulation time 59617253 ps
CPU time 0.73 seconds
Started Aug 17 06:08:55 PM PDT 24
Finished Aug 17 06:08:55 PM PDT 24
Peak memory 207524 kb
Host smart-78d05d85-484c-4116-bb82-945849986712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42281
43778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.4228143778
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1462520249
Short name T3324
Test name
Test status
Simulation time 16589013842 ps
CPU time 41.88 seconds
Started Aug 17 06:09:00 PM PDT 24
Finished Aug 17 06:09:42 PM PDT 24
Peak memory 215940 kb
Host smart-bed2a419-f6ee-4217-b006-d20c2e106abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14625
20249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1462520249
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3116417156
Short name T1398
Test name
Test status
Simulation time 203348032 ps
CPU time 1.01 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:09:02 PM PDT 24
Peak memory 207512 kb
Host smart-70efe140-c0bd-4a51-80e8-23b5ef856810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31164
17156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3116417156
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.802392043
Short name T1017
Test name
Test status
Simulation time 216077253 ps
CPU time 1.05 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:08:50 PM PDT 24
Peak memory 207668 kb
Host smart-bfab7e60-e916-4597-b48c-e6aa322d6772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80239
2043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.802392043
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1611215565
Short name T3140
Test name
Test status
Simulation time 272770270 ps
CPU time 0.99 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 207472 kb
Host smart-b51716bc-a8e5-4793-aa56-845a261ac8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16112
15565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1611215565
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2208749842
Short name T1813
Test name
Test status
Simulation time 171213176 ps
CPU time 1.01 seconds
Started Aug 17 06:08:53 PM PDT 24
Finished Aug 17 06:08:54 PM PDT 24
Peak memory 207472 kb
Host smart-dd380e7c-bc59-4638-9ef5-e04a24499e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22087
49842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2208749842
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1132079579
Short name T1484
Test name
Test status
Simulation time 175870778 ps
CPU time 0.89 seconds
Started Aug 17 06:08:51 PM PDT 24
Finished Aug 17 06:08:52 PM PDT 24
Peak memory 207492 kb
Host smart-56528b29-b142-47fd-9d59-23abf1e4e350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11320
79579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1132079579
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3719159355
Short name T3498
Test name
Test status
Simulation time 203302799 ps
CPU time 0.91 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:08:50 PM PDT 24
Peak memory 207516 kb
Host smart-cc466e5d-83aa-42e0-9ef5-d4e3b9537477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37191
59355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3719159355
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2384932391
Short name T1752
Test name
Test status
Simulation time 187242631 ps
CPU time 0.93 seconds
Started Aug 17 06:08:54 PM PDT 24
Finished Aug 17 06:08:55 PM PDT 24
Peak memory 207452 kb
Host smart-14ebf2f7-1531-491f-b5c7-96cb83a617eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23849
32391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2384932391
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1371065043
Short name T167
Test name
Test status
Simulation time 249191388 ps
CPU time 1.08 seconds
Started Aug 17 06:08:54 PM PDT 24
Finished Aug 17 06:08:55 PM PDT 24
Peak memory 207428 kb
Host smart-32b15e7b-2e9b-4af1-b804-9cdf1f2c63ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13710
65043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1371065043
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.39204573
Short name T1853
Test name
Test status
Simulation time 2347840435 ps
CPU time 17.22 seconds
Started Aug 17 06:08:59 PM PDT 24
Finished Aug 17 06:09:16 PM PDT 24
Peak memory 224076 kb
Host smart-649dc9ba-0bcf-43d3-8e52-312d80b61c9a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=39204573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.39204573
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3852579491
Short name T736
Test name
Test status
Simulation time 190742656 ps
CPU time 0.88 seconds
Started Aug 17 06:08:53 PM PDT 24
Finished Aug 17 06:08:54 PM PDT 24
Peak memory 207476 kb
Host smart-1b3dcca3-0463-46dc-bfab-94fa546743c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38525
79491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3852579491
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3608698517
Short name T1895
Test name
Test status
Simulation time 175464433 ps
CPU time 0.9 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:51 PM PDT 24
Peak memory 207544 kb
Host smart-90376de5-1c12-4b9b-b232-822fb60362c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36086
98517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3608698517
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.1218096456
Short name T1324
Test name
Test status
Simulation time 944399060 ps
CPU time 2.37 seconds
Started Aug 17 06:08:53 PM PDT 24
Finished Aug 17 06:08:56 PM PDT 24
Peak memory 207736 kb
Host smart-77f12214-5dce-4ff1-953e-ae8fdb2b601c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
96456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1218096456
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.242985683
Short name T3110
Test name
Test status
Simulation time 1782138468 ps
CPU time 52.13 seconds
Started Aug 17 06:08:58 PM PDT 24
Finished Aug 17 06:09:50 PM PDT 24
Peak memory 215932 kb
Host smart-d6ba71f6-a2b4-43ba-b141-fbbfb229589f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24298
5683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.242985683
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.1696869272
Short name T1505
Test name
Test status
Simulation time 1814388081 ps
CPU time 45.39 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:09:35 PM PDT 24
Peak memory 207660 kb
Host smart-52e17546-d962-4d64-8c01-f636ab886007
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696869272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.1696869272
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_tx_rx_disruption.3830405112
Short name T2986
Test name
Test status
Simulation time 501261777 ps
CPU time 1.62 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 207568 kb
Host smart-ea6b50ea-9f77-4d33-82ff-05d0814217a6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830405112 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.usbdev_tx_rx_disruption.3830405112
Directory /workspace/34.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/340.usbdev_tx_rx_disruption.3884369936
Short name T2670
Test name
Test status
Simulation time 497535118 ps
CPU time 1.56 seconds
Started Aug 17 06:12:03 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207472 kb
Host smart-54fe4719-8db7-4a38-a59a-bc7dad0e9a50
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884369936 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 340.usbdev_tx_rx_disruption.3884369936
Directory /workspace/340.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/341.usbdev_tx_rx_disruption.857729845
Short name T2161
Test name
Test status
Simulation time 646845094 ps
CPU time 1.63 seconds
Started Aug 17 06:12:05 PM PDT 24
Finished Aug 17 06:12:07 PM PDT 24
Peak memory 207568 kb
Host smart-740a113c-44d8-4853-81e7-8e239fb99536
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857729845 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 341.usbdev_tx_rx_disruption.857729845
Directory /workspace/341.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/342.usbdev_tx_rx_disruption.2507700135
Short name T1378
Test name
Test status
Simulation time 497690260 ps
CPU time 1.54 seconds
Started Aug 17 06:12:16 PM PDT 24
Finished Aug 17 06:12:17 PM PDT 24
Peak memory 207560 kb
Host smart-0bb93de4-8842-43de-b895-83d9830506ca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507700135 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 342.usbdev_tx_rx_disruption.2507700135
Directory /workspace/342.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/343.usbdev_tx_rx_disruption.3037738979
Short name T1393
Test name
Test status
Simulation time 566541807 ps
CPU time 1.5 seconds
Started Aug 17 06:12:12 PM PDT 24
Finished Aug 17 06:12:13 PM PDT 24
Peak memory 207516 kb
Host smart-0c77c5ab-e772-4e21-94f9-92c812b6040c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037738979 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 343.usbdev_tx_rx_disruption.3037738979
Directory /workspace/343.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/344.usbdev_tx_rx_disruption.471762281
Short name T1096
Test name
Test status
Simulation time 656773393 ps
CPU time 1.87 seconds
Started Aug 17 06:12:13 PM PDT 24
Finished Aug 17 06:12:14 PM PDT 24
Peak memory 207568 kb
Host smart-2ce71201-6a46-4a3b-ace3-78d9b8db971b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471762281 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 344.usbdev_tx_rx_disruption.471762281
Directory /workspace/344.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/345.usbdev_tx_rx_disruption.89226896
Short name T1060
Test name
Test status
Simulation time 549677830 ps
CPU time 1.63 seconds
Started Aug 17 06:12:20 PM PDT 24
Finished Aug 17 06:12:22 PM PDT 24
Peak memory 207576 kb
Host smart-e95547aa-60f8-4bb8-914c-db3ff7b75f57
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89226896 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 345.usbdev_tx_rx_disruption.89226896
Directory /workspace/345.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/346.usbdev_tx_rx_disruption.1236611780
Short name T3321
Test name
Test status
Simulation time 617052095 ps
CPU time 1.64 seconds
Started Aug 17 06:12:13 PM PDT 24
Finished Aug 17 06:12:15 PM PDT 24
Peak memory 207500 kb
Host smart-adbcfa64-aad2-4f0f-8844-c8294151c1bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236611780 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 346.usbdev_tx_rx_disruption.1236611780
Directory /workspace/346.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/347.usbdev_tx_rx_disruption.1528209757
Short name T2684
Test name
Test status
Simulation time 532069284 ps
CPU time 1.66 seconds
Started Aug 17 06:12:09 PM PDT 24
Finished Aug 17 06:12:11 PM PDT 24
Peak memory 207540 kb
Host smart-1ee83bb5-a4b0-4e61-980b-f693acba0ad1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528209757 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 347.usbdev_tx_rx_disruption.1528209757
Directory /workspace/347.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/348.usbdev_tx_rx_disruption.3676165551
Short name T1150
Test name
Test status
Simulation time 521775346 ps
CPU time 1.69 seconds
Started Aug 17 06:12:07 PM PDT 24
Finished Aug 17 06:12:14 PM PDT 24
Peak memory 207520 kb
Host smart-d76a2192-86b4-4a67-9443-fb0790a531b8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676165551 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 348.usbdev_tx_rx_disruption.3676165551
Directory /workspace/348.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/349.usbdev_tx_rx_disruption.1194281035
Short name T3369
Test name
Test status
Simulation time 430766312 ps
CPU time 1.73 seconds
Started Aug 17 06:12:18 PM PDT 24
Finished Aug 17 06:12:20 PM PDT 24
Peak memory 207596 kb
Host smart-a3887d1a-cc1e-4ff5-ae6f-f40a3902bf07
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194281035 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 349.usbdev_tx_rx_disruption.1194281035
Directory /workspace/349.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.24988882
Short name T1216
Test name
Test status
Simulation time 50632264 ps
CPU time 0.71 seconds
Started Aug 17 06:09:11 PM PDT 24
Finished Aug 17 06:09:11 PM PDT 24
Peak memory 207352 kb
Host smart-83298a35-9c63-4073-9834-ba9d5d67122e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=24988882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.24988882
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2572603480
Short name T811
Test name
Test status
Simulation time 6697802418 ps
CPU time 10.18 seconds
Started Aug 17 06:08:49 PM PDT 24
Finished Aug 17 06:09:00 PM PDT 24
Peak memory 215984 kb
Host smart-79f038a9-1ac3-400b-aee6-21c21f148e11
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572603480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.2572603480
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3073385035
Short name T1897
Test name
Test status
Simulation time 14574577771 ps
CPU time 17.46 seconds
Started Aug 17 06:08:57 PM PDT 24
Finished Aug 17 06:09:14 PM PDT 24
Peak memory 215984 kb
Host smart-e2d3db6f-981a-4ee5-8dd3-b146d6f96cc1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073385035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3073385035
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.483523702
Short name T2435
Test name
Test status
Simulation time 30800004712 ps
CPU time 39.18 seconds
Started Aug 17 06:08:51 PM PDT 24
Finished Aug 17 06:09:31 PM PDT 24
Peak memory 207692 kb
Host smart-57dadd9b-2061-474c-af10-855eb727b061
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483523702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ao
n_wake_resume.483523702
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.118972974
Short name T3065
Test name
Test status
Simulation time 163685013 ps
CPU time 0.92 seconds
Started Aug 17 06:09:00 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207428 kb
Host smart-a2efe020-bfc8-45b3-87c2-ec015158d3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11897
2974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.118972974
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1370014945
Short name T81
Test name
Test status
Simulation time 174480355 ps
CPU time 0.89 seconds
Started Aug 17 06:08:52 PM PDT 24
Finished Aug 17 06:08:53 PM PDT 24
Peak memory 207420 kb
Host smart-62430d73-bf02-42e5-881e-079ae4b9a6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13700
14945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1370014945
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.4163979284
Short name T568
Test name
Test status
Simulation time 174010132 ps
CPU time 0.94 seconds
Started Aug 17 06:08:57 PM PDT 24
Finished Aug 17 06:08:58 PM PDT 24
Peak memory 207536 kb
Host smart-f8e3d0a0-8f9f-4fdb-a10e-4d0488defed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41639
79284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.4163979284
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.315311652
Short name T1808
Test name
Test status
Simulation time 874886122 ps
CPU time 2.44 seconds
Started Aug 17 06:09:12 PM PDT 24
Finished Aug 17 06:09:14 PM PDT 24
Peak memory 207676 kb
Host smart-06481063-f046-4076-b2fb-17227f7a37c6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=315311652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.315311652
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3829977374
Short name T2916
Test name
Test status
Simulation time 45058766903 ps
CPU time 79.51 seconds
Started Aug 17 06:08:58 PM PDT 24
Finished Aug 17 06:10:17 PM PDT 24
Peak memory 207784 kb
Host smart-758796a4-ada8-4f1d-93b1-fa2343c72a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38299
77374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3829977374
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.3996719176
Short name T205
Test name
Test status
Simulation time 503004993 ps
CPU time 8.64 seconds
Started Aug 17 06:09:07 PM PDT 24
Finished Aug 17 06:09:16 PM PDT 24
Peak memory 207712 kb
Host smart-0cd57580-a783-4be3-b682-3a09f1862d16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996719176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.3996719176
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.4246043033
Short name T2624
Test name
Test status
Simulation time 551608927 ps
CPU time 1.64 seconds
Started Aug 17 06:08:59 PM PDT 24
Finished Aug 17 06:09:00 PM PDT 24
Peak memory 207512 kb
Host smart-0d451ebf-62f5-46ec-9b83-2366c6e237d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42460
43033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.4246043033
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3817612931
Short name T1200
Test name
Test status
Simulation time 161186999 ps
CPU time 0.88 seconds
Started Aug 17 06:08:50 PM PDT 24
Finished Aug 17 06:08:51 PM PDT 24
Peak memory 207464 kb
Host smart-d2fb72c9-debb-47c4-9279-bc026ca23471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
12931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3817612931
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3233469347
Short name T1296
Test name
Test status
Simulation time 43401479 ps
CPU time 0.72 seconds
Started Aug 17 06:08:55 PM PDT 24
Finished Aug 17 06:08:56 PM PDT 24
Peak memory 207392 kb
Host smart-1e08fe6d-a1ee-45a1-ac6c-6528a8f63776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32334
69347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3233469347
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1272452892
Short name T2084
Test name
Test status
Simulation time 784084732 ps
CPU time 2.27 seconds
Started Aug 17 06:09:01 PM PDT 24
Finished Aug 17 06:09:03 PM PDT 24
Peak memory 207744 kb
Host smart-5b48b2ca-1052-4e14-983e-c152bf03afc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12724
52892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1272452892
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_types.2768728324
Short name T500
Test name
Test status
Simulation time 319745560 ps
CPU time 1.23 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:08:58 PM PDT 24
Peak memory 207432 kb
Host smart-2310c066-7998-4a07-a8c4-0cf2f704f672
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2768728324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.2768728324
Directory /workspace/35.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3855135605
Short name T2266
Test name
Test status
Simulation time 371027600 ps
CPU time 2.83 seconds
Started Aug 17 06:08:58 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207652 kb
Host smart-f7f612bf-5ee0-4fd9-b569-b80ef5ae4540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551
35605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3855135605
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3971743706
Short name T1084
Test name
Test status
Simulation time 206261237 ps
CPU time 1.14 seconds
Started Aug 17 06:09:01 PM PDT 24
Finished Aug 17 06:09:03 PM PDT 24
Peak memory 215860 kb
Host smart-d9c5b5f4-7bd7-4812-b702-a6399ec4c612
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3971743706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3971743706
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1337888595
Short name T2210
Test name
Test status
Simulation time 153734591 ps
CPU time 0.91 seconds
Started Aug 17 06:08:58 PM PDT 24
Finished Aug 17 06:08:59 PM PDT 24
Peak memory 207432 kb
Host smart-616b5279-e80d-48e7-ba9c-595aea752bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13378
88595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1337888595
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2713410352
Short name T2944
Test name
Test status
Simulation time 233742766 ps
CPU time 1.16 seconds
Started Aug 17 06:09:15 PM PDT 24
Finished Aug 17 06:09:17 PM PDT 24
Peak memory 207416 kb
Host smart-b704f7a0-c366-4572-b8fc-f22eed9e0555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27134
10352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2713410352
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.2247792219
Short name T2469
Test name
Test status
Simulation time 3966571672 ps
CPU time 108.41 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:10:45 PM PDT 24
Peak memory 224136 kb
Host smart-0966c236-a4b8-4c02-8c47-2a91ce7fe204
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2247792219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.2247792219
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.4160298267
Short name T2722
Test name
Test status
Simulation time 9319465112 ps
CPU time 68.71 seconds
Started Aug 17 06:08:55 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 207696 kb
Host smart-235cc4d5-d568-4a9b-9695-9517ac83e9e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4160298267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.4160298267
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1138956741
Short name T1368
Test name
Test status
Simulation time 229271784 ps
CPU time 1.01 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 207560 kb
Host smart-017a0cb6-d4b5-4465-93b2-a11e2334dc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11389
56741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1138956741
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1927534524
Short name T63
Test name
Test status
Simulation time 30441990447 ps
CPU time 48.47 seconds
Started Aug 17 06:08:57 PM PDT 24
Finished Aug 17 06:09:45 PM PDT 24
Peak memory 207736 kb
Host smart-5a68417d-06ba-4dc8-8bfd-ae9c5fa81e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275
34524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1927534524
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1119231753
Short name T2100
Test name
Test status
Simulation time 9218019420 ps
CPU time 12.65 seconds
Started Aug 17 06:08:56 PM PDT 24
Finished Aug 17 06:09:09 PM PDT 24
Peak memory 207752 kb
Host smart-b3d614ac-6599-4b29-9c2b-ce7ae1141982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11192
31753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1119231753
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1312925907
Short name T1256
Test name
Test status
Simulation time 3724440300 ps
CPU time 108.99 seconds
Started Aug 17 06:08:53 PM PDT 24
Finished Aug 17 06:10:42 PM PDT 24
Peak memory 218336 kb
Host smart-0686ae7c-a258-485e-94ba-3c36e07fd692
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1312925907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1312925907
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.584227798
Short name T1195
Test name
Test status
Simulation time 1980163639 ps
CPU time 15.91 seconds
Started Aug 17 06:09:04 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 217308 kb
Host smart-8afaf0cb-8e6d-4c62-9d8d-195800cd55a3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=584227798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.584227798
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3725122748
Short name T652
Test name
Test status
Simulation time 272151671 ps
CPU time 1.01 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:04 PM PDT 24
Peak memory 207708 kb
Host smart-d09f9daf-7615-4c9d-9173-89d4845805cb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3725122748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3725122748
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1821853062
Short name T2026
Test name
Test status
Simulation time 187140780 ps
CPU time 0.95 seconds
Started Aug 17 06:09:01 PM PDT 24
Finished Aug 17 06:09:02 PM PDT 24
Peak memory 207388 kb
Host smart-eb5747e5-4fb0-42ce-befd-8cd1430ae4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18218
53062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1821853062
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.3617330840
Short name T1199
Test name
Test status
Simulation time 2843856456 ps
CPU time 22.31 seconds
Started Aug 17 06:09:01 PM PDT 24
Finished Aug 17 06:09:23 PM PDT 24
Peak memory 215984 kb
Host smart-8370c761-9f3b-44f0-8e3d-49e563fe273b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3617330840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.3617330840
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2864234600
Short name T1140
Test name
Test status
Simulation time 196192287 ps
CPU time 1.07 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:03 PM PDT 24
Peak memory 207484 kb
Host smart-24543ffc-4f7b-4fb8-bf6a-065f6f3dc429
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2864234600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2864234600
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2405789491
Short name T3628
Test name
Test status
Simulation time 161828531 ps
CPU time 0.99 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:03 PM PDT 24
Peak memory 207432 kb
Host smart-0753d05c-8e5e-4334-bdc4-8c346e21dad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057
89491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2405789491
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1353766067
Short name T3044
Test name
Test status
Simulation time 180469840 ps
CPU time 0.92 seconds
Started Aug 17 06:09:05 PM PDT 24
Finished Aug 17 06:09:06 PM PDT 24
Peak memory 207436 kb
Host smart-1aac423b-eb46-4141-a4fa-ecb941e27c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537
66067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1353766067
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3212633365
Short name T2123
Test name
Test status
Simulation time 182477702 ps
CPU time 0.93 seconds
Started Aug 17 06:09:03 PM PDT 24
Finished Aug 17 06:09:04 PM PDT 24
Peak memory 207464 kb
Host smart-1037a788-8a3e-49b1-b7d9-b1fd185fcf7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32126
33365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3212633365
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3192990395
Short name T2486
Test name
Test status
Simulation time 213974795 ps
CPU time 0.91 seconds
Started Aug 17 06:09:09 PM PDT 24
Finished Aug 17 06:09:10 PM PDT 24
Peak memory 207512 kb
Host smart-0913982d-a1b3-4ef0-b918-9291e6d6a6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31929
90395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3192990395
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.612224573
Short name T2750
Test name
Test status
Simulation time 175329837 ps
CPU time 0.93 seconds
Started Aug 17 06:09:00 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207476 kb
Host smart-aaba7d3f-46f2-4336-972d-e64cac10426d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61222
4573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.612224573
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1811443061
Short name T2448
Test name
Test status
Simulation time 247241856 ps
CPU time 1.04 seconds
Started Aug 17 06:09:00 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207524 kb
Host smart-06d6fd91-79de-4cc0-98f4-020cc444da84
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1811443061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1811443061
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.748118688
Short name T226
Test name
Test status
Simulation time 143838126 ps
CPU time 0.85 seconds
Started Aug 17 06:09:03 PM PDT 24
Finished Aug 17 06:09:04 PM PDT 24
Peak memory 207452 kb
Host smart-f046764f-7d24-4785-b9f9-5f3b69b7acee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74811
8688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.748118688
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2303133008
Short name T3206
Test name
Test status
Simulation time 33319669 ps
CPU time 0.71 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207472 kb
Host smart-0317415e-318b-4020-91e9-8586917bdde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23031
33008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2303133008
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2374066016
Short name T2408
Test name
Test status
Simulation time 14624473196 ps
CPU time 38.63 seconds
Started Aug 17 06:08:59 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 215912 kb
Host smart-ff6fe654-3b07-495e-bb3c-90644740ac6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23740
66016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2374066016
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3574423496
Short name T1740
Test name
Test status
Simulation time 190361663 ps
CPU time 0.92 seconds
Started Aug 17 06:09:03 PM PDT 24
Finished Aug 17 06:09:04 PM PDT 24
Peak memory 207532 kb
Host smart-0be6759f-d947-4054-9991-111de8533ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35744
23496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3574423496
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1167344170
Short name T995
Test name
Test status
Simulation time 206202493 ps
CPU time 1.01 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:03 PM PDT 24
Peak memory 207428 kb
Host smart-9389d5ae-f2af-47a8-9e5a-2679398a54bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11673
44170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1167344170
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.334365834
Short name T2779
Test name
Test status
Simulation time 218275707 ps
CPU time 0.99 seconds
Started Aug 17 06:08:58 PM PDT 24
Finished Aug 17 06:08:59 PM PDT 24
Peak memory 207484 kb
Host smart-90c77c0d-e59a-47f9-899c-8bd5550085aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33436
5834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.334365834
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.116334006
Short name T3182
Test name
Test status
Simulation time 175275240 ps
CPU time 0.95 seconds
Started Aug 17 06:09:00 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207696 kb
Host smart-04496948-1179-4bf3-b4df-778773d2f6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11633
4006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.116334006
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.1700567457
Short name T3555
Test name
Test status
Simulation time 161081045 ps
CPU time 0.89 seconds
Started Aug 17 06:09:00 PM PDT 24
Finished Aug 17 06:09:01 PM PDT 24
Peak memory 207424 kb
Host smart-22fea7b0-1f22-4fa7-926b-fa97b68338bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17005
67457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.1700567457
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_rx_full.2888272472
Short name T1909
Test name
Test status
Simulation time 253378919 ps
CPU time 1.11 seconds
Started Aug 17 06:09:04 PM PDT 24
Finished Aug 17 06:09:05 PM PDT 24
Peak memory 207464 kb
Host smart-75491461-6cf0-431e-aa3c-7da045c3b8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28882
72472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.2888272472
Directory /workspace/35.usbdev_rx_full/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1958849773
Short name T1967
Test name
Test status
Simulation time 152951320 ps
CPU time 0.87 seconds
Started Aug 17 06:08:58 PM PDT 24
Finished Aug 17 06:08:59 PM PDT 24
Peak memory 207540 kb
Host smart-4fc2fcce-6a40-43a2-9f14-4828b1618c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19588
49773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1958849773
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.4066307277
Short name T2819
Test name
Test status
Simulation time 175513228 ps
CPU time 0.9 seconds
Started Aug 17 06:09:10 PM PDT 24
Finished Aug 17 06:09:11 PM PDT 24
Peak memory 207428 kb
Host smart-4223a14d-530e-461c-bd94-ed6f9b4c2148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40663
07277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.4066307277
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3890198552
Short name T1748
Test name
Test status
Simulation time 195663785 ps
CPU time 1.01 seconds
Started Aug 17 06:09:05 PM PDT 24
Finished Aug 17 06:09:07 PM PDT 24
Peak memory 207484 kb
Host smart-38540737-8ba2-431e-8c1e-07b4fbb4b2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38901
98552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3890198552
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3249268748
Short name T1034
Test name
Test status
Simulation time 1852513587 ps
CPU time 17.93 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 216900 kb
Host smart-7ecaca9c-62be-49a7-b9aa-98eecf2905e9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3249268748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3249268748
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.614035106
Short name T3484
Test name
Test status
Simulation time 194794836 ps
CPU time 0.94 seconds
Started Aug 17 06:09:03 PM PDT 24
Finished Aug 17 06:09:04 PM PDT 24
Peak memory 207488 kb
Host smart-453fdf77-3ba6-459c-9053-f551cd73309e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61403
5106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.614035106
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.50014080
Short name T2925
Test name
Test status
Simulation time 166305101 ps
CPU time 0.88 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207432 kb
Host smart-0096e3de-e83e-4207-8d2b-1292a1f3ffb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50014
080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.50014080
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.4191193119
Short name T545
Test name
Test status
Simulation time 1028612306 ps
CPU time 2.8 seconds
Started Aug 17 06:09:03 PM PDT 24
Finished Aug 17 06:09:06 PM PDT 24
Peak memory 207764 kb
Host smart-a66b848b-a491-4091-bd2f-4d242f390167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41911
93119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.4191193119
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1814378419
Short name T2097
Test name
Test status
Simulation time 3313545540 ps
CPU time 27.31 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:30 PM PDT 24
Peak memory 217676 kb
Host smart-a953c81d-69d6-43bf-b03f-f050a3fc85c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18143
78419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1814378419
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.112052472
Short name T168
Test name
Test status
Simulation time 3894718606 ps
CPU time 35.86 seconds
Started Aug 17 06:08:57 PM PDT 24
Finished Aug 17 06:09:33 PM PDT 24
Peak memory 207720 kb
Host smart-77fe151f-9e96-4302-a32b-b1583ad42719
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112052472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_host
_handshake.112052472
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_tx_rx_disruption.1553405421
Short name T243
Test name
Test status
Simulation time 570001327 ps
CPU time 1.79 seconds
Started Aug 17 06:08:55 PM PDT 24
Finished Aug 17 06:08:57 PM PDT 24
Peak memory 207552 kb
Host smart-86be3646-8b05-4e9c-88f1-9bc31ba6fa8b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553405421 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.usbdev_tx_rx_disruption.1553405421
Directory /workspace/35.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/350.usbdev_tx_rx_disruption.836894103
Short name T1792
Test name
Test status
Simulation time 495307368 ps
CPU time 1.7 seconds
Started Aug 17 06:12:18 PM PDT 24
Finished Aug 17 06:12:20 PM PDT 24
Peak memory 207560 kb
Host smart-41a8a8c0-8d96-45e8-8cc2-96cb93ea1a72
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836894103 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 350.usbdev_tx_rx_disruption.836894103
Directory /workspace/350.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/351.usbdev_tx_rx_disruption.3868163442
Short name T1595
Test name
Test status
Simulation time 485227685 ps
CPU time 1.58 seconds
Started Aug 17 06:12:29 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207544 kb
Host smart-cb14475d-d465-4f55-8aac-f2f1721f2183
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868163442 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 351.usbdev_tx_rx_disruption.3868163442
Directory /workspace/351.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/352.usbdev_tx_rx_disruption.931128711
Short name T1385
Test name
Test status
Simulation time 666383014 ps
CPU time 1.74 seconds
Started Aug 17 06:12:22 PM PDT 24
Finished Aug 17 06:12:24 PM PDT 24
Peak memory 207560 kb
Host smart-371a0bd7-1e00-4dc2-89fc-70536a5eb7c3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931128711 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 352.usbdev_tx_rx_disruption.931128711
Directory /workspace/352.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/353.usbdev_tx_rx_disruption.140210390
Short name T2876
Test name
Test status
Simulation time 496865606 ps
CPU time 1.67 seconds
Started Aug 17 06:12:17 PM PDT 24
Finished Aug 17 06:12:19 PM PDT 24
Peak memory 207568 kb
Host smart-7f1faf23-0ffe-4c00-804c-27ccefeb91aa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140210390 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 353.usbdev_tx_rx_disruption.140210390
Directory /workspace/353.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/354.usbdev_tx_rx_disruption.512320077
Short name T2955
Test name
Test status
Simulation time 552482683 ps
CPU time 1.68 seconds
Started Aug 17 06:12:13 PM PDT 24
Finished Aug 17 06:12:15 PM PDT 24
Peak memory 207564 kb
Host smart-36f8f43b-2055-4eba-bc9e-8ac700c6c266
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512320077 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 354.usbdev_tx_rx_disruption.512320077
Directory /workspace/354.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/355.usbdev_tx_rx_disruption.3423301028
Short name T1961
Test name
Test status
Simulation time 518941353 ps
CPU time 1.47 seconds
Started Aug 17 06:12:22 PM PDT 24
Finished Aug 17 06:12:24 PM PDT 24
Peak memory 207784 kb
Host smart-f6331a7e-c477-4348-9cc1-f9746c4b12fc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423301028 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 355.usbdev_tx_rx_disruption.3423301028
Directory /workspace/355.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/356.usbdev_tx_rx_disruption.1456612804
Short name T3387
Test name
Test status
Simulation time 575120806 ps
CPU time 1.68 seconds
Started Aug 17 06:12:06 PM PDT 24
Finished Aug 17 06:12:13 PM PDT 24
Peak memory 207560 kb
Host smart-b671f25a-d7d3-4a15-945d-862e12b7d280
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456612804 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 356.usbdev_tx_rx_disruption.1456612804
Directory /workspace/356.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/357.usbdev_tx_rx_disruption.2997659801
Short name T75
Test name
Test status
Simulation time 444369149 ps
CPU time 1.39 seconds
Started Aug 17 06:12:04 PM PDT 24
Finished Aug 17 06:12:05 PM PDT 24
Peak memory 207512 kb
Host smart-d2af137e-82b1-4e55-ad02-43e72261b8c6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997659801 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 357.usbdev_tx_rx_disruption.2997659801
Directory /workspace/357.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/358.usbdev_tx_rx_disruption.3031789194
Short name T1861
Test name
Test status
Simulation time 677468422 ps
CPU time 1.89 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 207548 kb
Host smart-56b6d22e-6cba-4bfb-bdc3-834a5aa9b374
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031789194 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 358.usbdev_tx_rx_disruption.3031789194
Directory /workspace/358.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/359.usbdev_tx_rx_disruption.327287765
Short name T2102
Test name
Test status
Simulation time 502462366 ps
CPU time 1.67 seconds
Started Aug 17 06:12:01 PM PDT 24
Finished Aug 17 06:12:03 PM PDT 24
Peak memory 207544 kb
Host smart-8edd72c6-df3d-4d48-80ea-ce794d96ba67
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327287765 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 359.usbdev_tx_rx_disruption.327287765
Directory /workspace/359.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.3909871131
Short name T955
Test name
Test status
Simulation time 37402608 ps
CPU time 0.67 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207424 kb
Host smart-ef33f566-29ac-4793-82a3-2bd264d03bef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3909871131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.3909871131
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.4152739468
Short name T904
Test name
Test status
Simulation time 6038975458 ps
CPU time 8.3 seconds
Started Aug 17 06:08:58 PM PDT 24
Finished Aug 17 06:09:06 PM PDT 24
Peak memory 215980 kb
Host smart-10d18b44-e8c5-48a9-8564-70aff09e48c5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152739468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.4152739468
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3848701
Short name T603
Test name
Test status
Simulation time 15529218714 ps
CPU time 21.57 seconds
Started Aug 17 06:09:05 PM PDT 24
Finished Aug 17 06:09:26 PM PDT 24
Peak memory 215964 kb
Host smart-46ee2b17-0a57-4291-bae6-eaff2216c176
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3848701
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2707999129
Short name T2663
Test name
Test status
Simulation time 26081632799 ps
CPU time 34.57 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:41 PM PDT 24
Peak memory 215988 kb
Host smart-2c4d9a76-dc9c-43ae-beae-cf3b9e1eace4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707999129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.2707999129
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.30829186
Short name T2923
Test name
Test status
Simulation time 168977411 ps
CPU time 0.89 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:03 PM PDT 24
Peak memory 207440 kb
Host smart-a0fe47b8-61ee-4225-8f82-4e9a1b7b980c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30829
186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.30829186
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2547314368
Short name T2055
Test name
Test status
Simulation time 236352075 ps
CPU time 0.99 seconds
Started Aug 17 06:09:08 PM PDT 24
Finished Aug 17 06:09:09 PM PDT 24
Peak memory 207512 kb
Host smart-06d762da-8afb-49ed-906c-418c4a2d2960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25473
14368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2547314368
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3017294764
Short name T784
Test name
Test status
Simulation time 361737130 ps
CPU time 1.36 seconds
Started Aug 17 06:09:13 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207500 kb
Host smart-b554868d-4862-4157-b2a9-b56219f2e349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30172
94764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3017294764
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3778245243
Short name T2011
Test name
Test status
Simulation time 1023235694 ps
CPU time 2.85 seconds
Started Aug 17 06:09:00 PM PDT 24
Finished Aug 17 06:09:03 PM PDT 24
Peak memory 207692 kb
Host smart-4d576d44-08bf-42a8-afdf-0874220a7cba
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3778245243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3778245243
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.752378564
Short name T1731
Test name
Test status
Simulation time 14557471546 ps
CPU time 26.34 seconds
Started Aug 17 06:08:59 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207780 kb
Host smart-c04da164-a192-40bb-8f79-1b72ec4a1e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75237
8564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.752378564
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.3127024818
Short name T3448
Test name
Test status
Simulation time 2944064861 ps
CPU time 19.32 seconds
Started Aug 17 06:09:11 PM PDT 24
Finished Aug 17 06:09:30 PM PDT 24
Peak memory 207780 kb
Host smart-53e29a80-b72f-437b-90f0-a48bba4caa5e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127024818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.3127024818
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2173966513
Short name T3575
Test name
Test status
Simulation time 591714188 ps
CPU time 1.68 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:04 PM PDT 24
Peak memory 207524 kb
Host smart-5705b57d-5b65-4062-86b1-a7f8d8da45c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21739
66513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2173966513
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1095963873
Short name T1943
Test name
Test status
Simulation time 156900047 ps
CPU time 0.86 seconds
Started Aug 17 06:08:59 PM PDT 24
Finished Aug 17 06:09:00 PM PDT 24
Peak memory 207500 kb
Host smart-c00b1867-b5f4-4ab5-829e-427c5d1d79a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10959
63873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1095963873
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3301943263
Short name T911
Test name
Test status
Simulation time 41207627 ps
CPU time 0.73 seconds
Started Aug 17 06:09:04 PM PDT 24
Finished Aug 17 06:09:05 PM PDT 24
Peak memory 207428 kb
Host smart-727eae49-6e2d-4d5b-9351-4f888e213aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33019
43263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3301943263
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3964843008
Short name T1775
Test name
Test status
Simulation time 1039896490 ps
CPU time 2.67 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:05 PM PDT 24
Peak memory 207732 kb
Host smart-3dd03fab-cf80-44b8-8faa-cba651ffe304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39648
43008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3964843008
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_types.4226817020
Short name T2914
Test name
Test status
Simulation time 275956310 ps
CPU time 1.05 seconds
Started Aug 17 06:09:05 PM PDT 24
Finished Aug 17 06:09:06 PM PDT 24
Peak memory 207528 kb
Host smart-f14d9eb7-fe84-41f0-889f-f9c754584f30
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4226817020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.4226817020
Directory /workspace/36.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1256784860
Short name T1709
Test name
Test status
Simulation time 147986327 ps
CPU time 1.37 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:21 PM PDT 24
Peak memory 207652 kb
Host smart-21c6da14-169e-4e54-a226-21ccb909567c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12567
84860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1256784860
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2882813389
Short name T645
Test name
Test status
Simulation time 213601820 ps
CPU time 0.99 seconds
Started Aug 17 06:09:05 PM PDT 24
Finished Aug 17 06:09:06 PM PDT 24
Peak memory 207452 kb
Host smart-f14a95c1-ac42-4ff6-a46a-4f6a1742df66
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2882813389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2882813389
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3248373749
Short name T846
Test name
Test status
Simulation time 142771726 ps
CPU time 0.95 seconds
Started Aug 17 06:09:04 PM PDT 24
Finished Aug 17 06:09:05 PM PDT 24
Peak memory 207448 kb
Host smart-e70e05d1-688e-4378-b5f2-b956d514c322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32483
73749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3248373749
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1009349455
Short name T702
Test name
Test status
Simulation time 238421322 ps
CPU time 1.01 seconds
Started Aug 17 06:09:07 PM PDT 24
Finished Aug 17 06:09:08 PM PDT 24
Peak memory 207400 kb
Host smart-6420b971-6342-48dd-a13a-bbbf9bf6db86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
49455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1009349455
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.452779263
Short name T2838
Test name
Test status
Simulation time 4936425696 ps
CPU time 49.4 seconds
Started Aug 17 06:09:11 PM PDT 24
Finished Aug 17 06:10:01 PM PDT 24
Peak memory 217488 kb
Host smart-9272c596-dbcb-4716-aed7-379b81c7e1b5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=452779263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.452779263
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.871742377
Short name T821
Test name
Test status
Simulation time 8775958621 ps
CPU time 107.02 seconds
Started Aug 17 06:09:04 PM PDT 24
Finished Aug 17 06:10:51 PM PDT 24
Peak memory 207796 kb
Host smart-3f2bab50-885f-4d36-964f-d46a600624be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=871742377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.871742377
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.169077025
Short name T1104
Test name
Test status
Simulation time 230421979 ps
CPU time 1.01 seconds
Started Aug 17 06:09:17 PM PDT 24
Finished Aug 17 06:09:18 PM PDT 24
Peak memory 207464 kb
Host smart-357a389d-713e-4fe6-bbf3-5f0eead1fa7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16907
7025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.169077025
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1162373303
Short name T3173
Test name
Test status
Simulation time 9442848262 ps
CPU time 12.77 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:27 PM PDT 24
Peak memory 207732 kb
Host smart-a92680c8-72ea-4d15-916a-b8de2ecefb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11623
73303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1162373303
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1331356831
Short name T1882
Test name
Test status
Simulation time 8470407411 ps
CPU time 10.8 seconds
Started Aug 17 06:09:15 PM PDT 24
Finished Aug 17 06:09:26 PM PDT 24
Peak memory 207820 kb
Host smart-c23fa7ef-c787-4f25-9eff-c1c06916c229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13313
56831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1331356831
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.934711812
Short name T3382
Test name
Test status
Simulation time 3693533452 ps
CPU time 115.29 seconds
Started Aug 17 06:09:03 PM PDT 24
Finished Aug 17 06:10:59 PM PDT 24
Peak memory 218360 kb
Host smart-beb1e345-b806-43d8-92e8-8b76c5b08036
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=934711812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.934711812
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.2617242207
Short name T1526
Test name
Test status
Simulation time 1726855744 ps
CPU time 16.16 seconds
Started Aug 17 06:09:07 PM PDT 24
Finished Aug 17 06:09:23 PM PDT 24
Peak memory 217588 kb
Host smart-dc14de1c-6b6b-4bd3-aaeb-983e9bb4924f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2617242207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.2617242207
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2669891155
Short name T1180
Test name
Test status
Simulation time 238366359 ps
CPU time 0.99 seconds
Started Aug 17 06:09:07 PM PDT 24
Finished Aug 17 06:09:08 PM PDT 24
Peak memory 207400 kb
Host smart-29b4b141-21d8-45a6-9b57-514f91c85c16
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2669891155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2669891155
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1920549128
Short name T3216
Test name
Test status
Simulation time 252708688 ps
CPU time 1.02 seconds
Started Aug 17 06:09:07 PM PDT 24
Finished Aug 17 06:09:09 PM PDT 24
Peak memory 207420 kb
Host smart-e1fce254-10d9-4f12-9e49-5c99df37e45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19205
49128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1920549128
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3526224530
Short name T701
Test name
Test status
Simulation time 3687675513 ps
CPU time 115.84 seconds
Started Aug 17 06:09:07 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 217316 kb
Host smart-2c70e573-06b2-4f6a-b179-3f4529b6086d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3526224530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3526224530
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.4033416775
Short name T1640
Test name
Test status
Simulation time 174183955 ps
CPU time 0.96 seconds
Started Aug 17 06:09:09 PM PDT 24
Finished Aug 17 06:09:10 PM PDT 24
Peak memory 207484 kb
Host smart-9fd34a9d-be9d-41a3-911d-c5665de02146
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4033416775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.4033416775
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.10853191
Short name T1169
Test name
Test status
Simulation time 141562258 ps
CPU time 0.89 seconds
Started Aug 17 06:09:16 PM PDT 24
Finished Aug 17 06:09:17 PM PDT 24
Peak memory 207396 kb
Host smart-545c24ed-9ecc-4285-b903-5f2e746a61d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10853
191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.10853191
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.122780809
Short name T1300
Test name
Test status
Simulation time 204679758 ps
CPU time 1.01 seconds
Started Aug 17 06:09:09 PM PDT 24
Finished Aug 17 06:09:10 PM PDT 24
Peak memory 207460 kb
Host smart-acbb41cd-f41c-4b90-89f3-3f34ed8d8a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12278
0809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.122780809
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3530243350
Short name T3091
Test name
Test status
Simulation time 180587641 ps
CPU time 1 seconds
Started Aug 17 06:09:03 PM PDT 24
Finished Aug 17 06:09:05 PM PDT 24
Peak memory 207456 kb
Host smart-0da232e0-6156-4441-b0cc-1f02561d9abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35302
43350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3530243350
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.4106753777
Short name T831
Test name
Test status
Simulation time 156806020 ps
CPU time 0.87 seconds
Started Aug 17 06:09:07 PM PDT 24
Finished Aug 17 06:09:08 PM PDT 24
Peak memory 207448 kb
Host smart-e96465ff-eb22-4d8e-adce-a1d8b09d6b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41067
53777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.4106753777
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.4293618064
Short name T2505
Test name
Test status
Simulation time 179333825 ps
CPU time 0.87 seconds
Started Aug 17 06:09:06 PM PDT 24
Finished Aug 17 06:09:06 PM PDT 24
Peak memory 207544 kb
Host smart-fa9ace25-44c0-4fb3-9a7c-f41b421f3bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936
18064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.4293618064
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.4100330937
Short name T214
Test name
Test status
Simulation time 183126462 ps
CPU time 0.94 seconds
Started Aug 17 06:09:06 PM PDT 24
Finished Aug 17 06:09:07 PM PDT 24
Peak memory 207564 kb
Host smart-ad98707f-3b75-4d7d-b280-16ffebdc0dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41003
30937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.4100330937
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2527362012
Short name T1271
Test name
Test status
Simulation time 230047046 ps
CPU time 1.01 seconds
Started Aug 17 06:09:07 PM PDT 24
Finished Aug 17 06:09:08 PM PDT 24
Peak memory 207560 kb
Host smart-497fbab6-ad2a-41fd-8d55-dafb4f6196b7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2527362012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2527362012
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1986843238
Short name T2886
Test name
Test status
Simulation time 162948188 ps
CPU time 0.9 seconds
Started Aug 17 06:09:09 PM PDT 24
Finished Aug 17 06:09:10 PM PDT 24
Peak memory 207428 kb
Host smart-3fa78892-c948-4829-9b83-94af30bc37a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19868
43238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1986843238
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.4002073400
Short name T20
Test name
Test status
Simulation time 36076698 ps
CPU time 0.7 seconds
Started Aug 17 06:09:09 PM PDT 24
Finished Aug 17 06:09:10 PM PDT 24
Peak memory 207452 kb
Host smart-7c82317c-2466-4080-be11-1dd85f837ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40020
73400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.4002073400
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1830029539
Short name T2892
Test name
Test status
Simulation time 12664907342 ps
CPU time 37.67 seconds
Started Aug 17 06:09:06 PM PDT 24
Finished Aug 17 06:09:44 PM PDT 24
Peak memory 215924 kb
Host smart-5d7d828d-e33b-4991-9a0b-52c86cd8ce76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18300
29539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1830029539
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.938805487
Short name T1564
Test name
Test status
Simulation time 154362132 ps
CPU time 0.88 seconds
Started Aug 17 06:09:06 PM PDT 24
Finished Aug 17 06:09:07 PM PDT 24
Peak memory 207508 kb
Host smart-23fe686f-bfbd-4b79-bb61-6b5632a9941e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93880
5487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.938805487
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2111723237
Short name T893
Test name
Test status
Simulation time 212986297 ps
CPU time 1 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207536 kb
Host smart-59236b40-e398-4491-887c-e0b4914ae499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21117
23237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2111723237
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1095488495
Short name T2592
Test name
Test status
Simulation time 249372622 ps
CPU time 1.01 seconds
Started Aug 17 06:09:12 PM PDT 24
Finished Aug 17 06:09:13 PM PDT 24
Peak memory 207412 kb
Host smart-3c10c055-3624-45a3-8bcc-c87722f63d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10954
88495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1095488495
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.955768609
Short name T861
Test name
Test status
Simulation time 193313322 ps
CPU time 0.96 seconds
Started Aug 17 06:09:06 PM PDT 24
Finished Aug 17 06:09:07 PM PDT 24
Peak memory 207496 kb
Host smart-e938945d-29e2-42ec-8f9e-57f35fd26fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95576
8609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.955768609
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.4176829259
Short name T73
Test name
Test status
Simulation time 199446927 ps
CPU time 0.92 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207400 kb
Host smart-0b22a0f7-9d6f-431d-8160-90ad86d564b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41768
29259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.4176829259
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_rx_full.3343371269
Short name T3331
Test name
Test status
Simulation time 296226229 ps
CPU time 1.17 seconds
Started Aug 17 06:09:11 PM PDT 24
Finished Aug 17 06:09:13 PM PDT 24
Peak memory 207404 kb
Host smart-0452578c-7991-4094-80df-3e3c9fdcd2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33433
71269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.3343371269
Directory /workspace/36.usbdev_rx_full/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.919705864
Short name T267
Test name
Test status
Simulation time 168562213 ps
CPU time 0.89 seconds
Started Aug 17 06:09:09 PM PDT 24
Finished Aug 17 06:09:10 PM PDT 24
Peak memory 207456 kb
Host smart-34800ba0-5f77-4c60-8c60-27fc2e21620e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91970
5864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.919705864
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.50835230
Short name T1938
Test name
Test status
Simulation time 150234222 ps
CPU time 0.87 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 207528 kb
Host smart-f8830b96-6bb9-427d-a20a-68c758123edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50835
230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.50835230
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2631886343
Short name T1027
Test name
Test status
Simulation time 190288906 ps
CPU time 0.94 seconds
Started Aug 17 06:09:09 PM PDT 24
Finished Aug 17 06:09:10 PM PDT 24
Peak memory 207468 kb
Host smart-261cc0c4-2405-4954-9679-582bebfedfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26318
86343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2631886343
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2363957209
Short name T2881
Test name
Test status
Simulation time 2206056641 ps
CPU time 17.06 seconds
Started Aug 17 06:09:05 PM PDT 24
Finished Aug 17 06:09:22 PM PDT 24
Peak memory 224032 kb
Host smart-92598a06-aaa1-439c-ab0f-11f3a93717eb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2363957209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2363957209
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3845200781
Short name T3302
Test name
Test status
Simulation time 144324648 ps
CPU time 0.84 seconds
Started Aug 17 06:09:05 PM PDT 24
Finished Aug 17 06:09:06 PM PDT 24
Peak memory 207432 kb
Host smart-d132fd8d-b047-4d5b-b874-1169adbe3560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38452
00781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3845200781
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2057310535
Short name T1116
Test name
Test status
Simulation time 192424698 ps
CPU time 0.92 seconds
Started Aug 17 06:09:12 PM PDT 24
Finished Aug 17 06:09:13 PM PDT 24
Peak memory 207428 kb
Host smart-9adf51db-981a-4686-b605-111f03b01cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20573
10535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2057310535
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.44306007
Short name T2537
Test name
Test status
Simulation time 206013508 ps
CPU time 0.98 seconds
Started Aug 17 06:09:13 PM PDT 24
Finished Aug 17 06:09:14 PM PDT 24
Peak memory 207516 kb
Host smart-24c63a57-4fb5-4f53-8fe5-b39f6e28f64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44306
007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.44306007
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1686282535
Short name T2787
Test name
Test status
Simulation time 2534087955 ps
CPU time 72.46 seconds
Started Aug 17 06:09:05 PM PDT 24
Finished Aug 17 06:10:17 PM PDT 24
Peak memory 215968 kb
Host smart-d8a7a042-b988-4586-a560-cc6d45114984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16862
82535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1686282535
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.3594148983
Short name T55
Test name
Test status
Simulation time 736116952 ps
CPU time 14.89 seconds
Started Aug 17 06:09:02 PM PDT 24
Finished Aug 17 06:09:17 PM PDT 24
Peak memory 207700 kb
Host smart-3cde9265-eff2-40ca-b22c-604dc6df8b6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594148983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.3594148983
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_tx_rx_disruption.2725354842
Short name T956
Test name
Test status
Simulation time 597340122 ps
CPU time 1.61 seconds
Started Aug 17 06:09:12 PM PDT 24
Finished Aug 17 06:09:14 PM PDT 24
Peak memory 207784 kb
Host smart-5d0e689d-9f99-4af5-87b8-0aa8bdf208cd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725354842 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.usbdev_tx_rx_disruption.2725354842
Directory /workspace/36.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/360.usbdev_tx_rx_disruption.3954764551
Short name T3541
Test name
Test status
Simulation time 662569273 ps
CPU time 1.71 seconds
Started Aug 17 06:12:02 PM PDT 24
Finished Aug 17 06:12:04 PM PDT 24
Peak memory 207512 kb
Host smart-e645a6f2-b934-4d83-bf12-a79e7c17e3f0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954764551 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 360.usbdev_tx_rx_disruption.3954764551
Directory /workspace/360.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/361.usbdev_tx_rx_disruption.2917209420
Short name T204
Test name
Test status
Simulation time 663707245 ps
CPU time 1.74 seconds
Started Aug 17 06:12:18 PM PDT 24
Finished Aug 17 06:12:20 PM PDT 24
Peak memory 207540 kb
Host smart-4798696e-1c67-4e8e-9f26-fb9a4eacd139
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917209420 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 361.usbdev_tx_rx_disruption.2917209420
Directory /workspace/361.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/362.usbdev_tx_rx_disruption.2575981567
Short name T1244
Test name
Test status
Simulation time 538437693 ps
CPU time 1.62 seconds
Started Aug 17 06:12:31 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207512 kb
Host smart-3b43a0ea-009e-42a5-a414-f98ba11918ce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575981567 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 362.usbdev_tx_rx_disruption.2575981567
Directory /workspace/362.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/363.usbdev_tx_rx_disruption.1886062470
Short name T2234
Test name
Test status
Simulation time 506226911 ps
CPU time 1.45 seconds
Started Aug 17 06:12:17 PM PDT 24
Finished Aug 17 06:12:19 PM PDT 24
Peak memory 207560 kb
Host smart-eb685c7a-1dd4-4beb-ab88-5c75e477eaf2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886062470 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 363.usbdev_tx_rx_disruption.1886062470
Directory /workspace/363.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/364.usbdev_tx_rx_disruption.2809669955
Short name T1382
Test name
Test status
Simulation time 500646531 ps
CPU time 1.48 seconds
Started Aug 17 06:12:08 PM PDT 24
Finished Aug 17 06:12:10 PM PDT 24
Peak memory 207568 kb
Host smart-f1d690f6-7dae-47a5-82ea-76bca3834b84
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809669955 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 364.usbdev_tx_rx_disruption.2809669955
Directory /workspace/364.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/365.usbdev_tx_rx_disruption.3110334604
Short name T3076
Test name
Test status
Simulation time 494471997 ps
CPU time 1.66 seconds
Started Aug 17 06:12:31 PM PDT 24
Finished Aug 17 06:12:33 PM PDT 24
Peak memory 207500 kb
Host smart-656a2c1b-f7b4-4f4a-ad5f-814317190456
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110334604 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 365.usbdev_tx_rx_disruption.3110334604
Directory /workspace/365.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/366.usbdev_tx_rx_disruption.2573728178
Short name T2152
Test name
Test status
Simulation time 575817203 ps
CPU time 1.5 seconds
Started Aug 17 06:12:15 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 206496 kb
Host smart-7c711641-5422-495e-8ef2-6384b15f28a0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573728178 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 366.usbdev_tx_rx_disruption.2573728178
Directory /workspace/366.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/367.usbdev_tx_rx_disruption.1915322906
Short name T3024
Test name
Test status
Simulation time 413956682 ps
CPU time 1.6 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 207540 kb
Host smart-15e213ef-50c2-43cb-924c-7cfc7d837471
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915322906 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 367.usbdev_tx_rx_disruption.1915322906
Directory /workspace/367.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/368.usbdev_tx_rx_disruption.18029373
Short name T3372
Test name
Test status
Simulation time 573061451 ps
CPU time 1.56 seconds
Started Aug 17 06:12:19 PM PDT 24
Finished Aug 17 06:12:21 PM PDT 24
Peak memory 207552 kb
Host smart-4c1b4b42-c3f7-4e88-aef9-e4100c149d29
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18029373 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 368.usbdev_tx_rx_disruption.18029373
Directory /workspace/368.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/369.usbdev_tx_rx_disruption.3469881559
Short name T1249
Test name
Test status
Simulation time 610920342 ps
CPU time 1.79 seconds
Started Aug 17 06:12:15 PM PDT 24
Finished Aug 17 06:12:17 PM PDT 24
Peak memory 207544 kb
Host smart-0417ec67-b077-45d1-b824-942a299f55e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469881559 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 369.usbdev_tx_rx_disruption.3469881559
Directory /workspace/369.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3815083615
Short name T1832
Test name
Test status
Simulation time 79218603 ps
CPU time 0.72 seconds
Started Aug 17 06:09:24 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207424 kb
Host smart-7804ac32-6fc5-436b-a5f8-14e028db9358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3815083615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3815083615
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2706551416
Short name T251
Test name
Test status
Simulation time 10087085765 ps
CPU time 12.92 seconds
Started Aug 17 06:09:18 PM PDT 24
Finished Aug 17 06:09:31 PM PDT 24
Peak memory 207788 kb
Host smart-062e2759-12a4-4eae-b64b-744783662ec5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706551416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.2706551416
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.686433304
Short name T562
Test name
Test status
Simulation time 14148335123 ps
CPU time 18.23 seconds
Started Aug 17 06:09:22 PM PDT 24
Finished Aug 17 06:09:40 PM PDT 24
Peak memory 215968 kb
Host smart-70625dcb-313b-4132-9386-814f0fb7301e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=686433304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.686433304
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.925040414
Short name T2393
Test name
Test status
Simulation time 29192426604 ps
CPU time 36.06 seconds
Started Aug 17 06:09:18 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207796 kb
Host smart-0814fe56-6f50-492b-8741-35a4a751d492
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925040414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_resume.925040414
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3315061678
Short name T1744
Test name
Test status
Simulation time 253048587 ps
CPU time 1.01 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 207392 kb
Host smart-672f4006-f35f-4ae6-8f63-a9449048abf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33150
61678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3315061678
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.496605947
Short name T2825
Test name
Test status
Simulation time 149110930 ps
CPU time 0.82 seconds
Started Aug 17 06:09:13 PM PDT 24
Finished Aug 17 06:09:14 PM PDT 24
Peak memory 207560 kb
Host smart-00444560-18b6-41fe-af19-f7c76ebb0177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49660
5947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.496605947
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3238134285
Short name T850
Test name
Test status
Simulation time 499653607 ps
CPU time 1.74 seconds
Started Aug 17 06:09:17 PM PDT 24
Finished Aug 17 06:09:18 PM PDT 24
Peak memory 207512 kb
Host smart-5c1119c2-4608-4cef-bef5-303e11991fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32381
34285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3238134285
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.1958935235
Short name T344
Test name
Test status
Simulation time 944358721 ps
CPU time 2.39 seconds
Started Aug 17 06:09:12 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207644 kb
Host smart-e1786518-b31f-41f0-a429-0f262b8b742a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1958935235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1958935235
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3232027559
Short name T3622
Test name
Test status
Simulation time 16585980567 ps
CPU time 31.46 seconds
Started Aug 17 06:09:10 PM PDT 24
Finished Aug 17 06:09:42 PM PDT 24
Peak memory 207788 kb
Host smart-ad045d2f-87e0-4142-82a4-c386eeb40e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320
27559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3232027559
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.2251009892
Short name T2647
Test name
Test status
Simulation time 4789381800 ps
CPU time 42.65 seconds
Started Aug 17 06:09:22 PM PDT 24
Finished Aug 17 06:10:05 PM PDT 24
Peak memory 207748 kb
Host smart-f0900f0a-1181-4937-b37d-68230ebd9803
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251009892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.2251009892
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.1590060954
Short name T2580
Test name
Test status
Simulation time 1132978509 ps
CPU time 2.48 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:17 PM PDT 24
Peak memory 207504 kb
Host smart-4024ece1-7ff2-4e17-993b-9df4aaaeca35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15900
60954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.1590060954
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2940376758
Short name T1741
Test name
Test status
Simulation time 159101902 ps
CPU time 0.86 seconds
Started Aug 17 06:09:17 PM PDT 24
Finished Aug 17 06:09:18 PM PDT 24
Peak memory 207508 kb
Host smart-2fdd8696-4023-4473-981b-afe53d6929e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
76758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2940376758
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.64278537
Short name T2345
Test name
Test status
Simulation time 42012497 ps
CPU time 0.69 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 207428 kb
Host smart-bb85950b-1e2d-43c6-9aa4-8bf7881f9326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64278
537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.64278537
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.4057345649
Short name T2804
Test name
Test status
Simulation time 844228414 ps
CPU time 2.28 seconds
Started Aug 17 06:09:13 PM PDT 24
Finished Aug 17 06:09:16 PM PDT 24
Peak memory 207752 kb
Host smart-f9879441-e330-4315-9abd-df49590d2cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40573
45649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.4057345649
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_types.2925841235
Short name T422
Test name
Test status
Simulation time 230904490 ps
CPU time 0.95 seconds
Started Aug 17 06:09:12 PM PDT 24
Finished Aug 17 06:09:13 PM PDT 24
Peak memory 207748 kb
Host smart-13cc0716-c85c-44b7-801a-8b6b963e0f22
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2925841235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.2925841235
Directory /workspace/37.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3758361991
Short name T3254
Test name
Test status
Simulation time 224509279 ps
CPU time 1.68 seconds
Started Aug 17 06:09:13 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207628 kb
Host smart-e2cfbe85-37c3-4c25-8ce3-778a8f5d887c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37583
61991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3758361991
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3852872372
Short name T1474
Test name
Test status
Simulation time 209109943 ps
CPU time 1.16 seconds
Started Aug 17 06:09:16 PM PDT 24
Finished Aug 17 06:09:18 PM PDT 24
Peak memory 215784 kb
Host smart-2a1d7210-ceed-4ca8-a379-423e8f050849
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3852872372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3852872372
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3917613391
Short name T2298
Test name
Test status
Simulation time 160032894 ps
CPU time 0.83 seconds
Started Aug 17 06:09:15 PM PDT 24
Finished Aug 17 06:09:16 PM PDT 24
Peak memory 207448 kb
Host smart-db7958a2-f73c-457e-8171-1914c7e5a808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39176
13391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3917613391
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.524339876
Short name T2257
Test name
Test status
Simulation time 222466742 ps
CPU time 1.03 seconds
Started Aug 17 06:09:17 PM PDT 24
Finished Aug 17 06:09:18 PM PDT 24
Peak memory 207476 kb
Host smart-38d8bbf5-b718-490b-9907-b9788c32bdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52433
9876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.524339876
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.2644171768
Short name T2221
Test name
Test status
Simulation time 4325291786 ps
CPU time 137.27 seconds
Started Aug 17 06:09:15 PM PDT 24
Finished Aug 17 06:11:33 PM PDT 24
Peak memory 218216 kb
Host smart-8f86037a-92b9-4ff8-84c3-09b8f415c73a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2644171768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2644171768
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.947052322
Short name T2467
Test name
Test status
Simulation time 7676519216 ps
CPU time 91.95 seconds
Started Aug 17 06:09:13 PM PDT 24
Finished Aug 17 06:10:45 PM PDT 24
Peak memory 207780 kb
Host smart-3a0a6279-c40e-4bb2-bf61-0c9aee5d257b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=947052322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.947052322
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.805123783
Short name T565
Test name
Test status
Simulation time 182574095 ps
CPU time 0.91 seconds
Started Aug 17 06:09:18 PM PDT 24
Finished Aug 17 06:09:19 PM PDT 24
Peak memory 207460 kb
Host smart-68d4842f-5b74-46c2-82bc-0ca9f16177bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80512
3783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.805123783
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.3122953432
Short name T3202
Test name
Test status
Simulation time 11360494491 ps
CPU time 16.62 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:31 PM PDT 24
Peak memory 207812 kb
Host smart-063d197e-b0e8-4698-8fdc-be72f5aa2881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31229
53432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.3122953432
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2973167187
Short name T886
Test name
Test status
Simulation time 6158808924 ps
CPU time 7.75 seconds
Started Aug 17 06:09:12 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 215964 kb
Host smart-685c4410-a9e4-4397-af20-689f5e01b013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29731
67187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2973167187
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.3043880363
Short name T2043
Test name
Test status
Simulation time 4472113348 ps
CPU time 36.71 seconds
Started Aug 17 06:09:20 PM PDT 24
Finished Aug 17 06:09:57 PM PDT 24
Peak memory 218864 kb
Host smart-4c976ac9-9469-475a-9a2c-ecf275ea1720
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3043880363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.3043880363
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.807849094
Short name T2507
Test name
Test status
Simulation time 2275683727 ps
CPU time 64.2 seconds
Started Aug 17 06:09:25 PM PDT 24
Finished Aug 17 06:10:29 PM PDT 24
Peak memory 215952 kb
Host smart-d21a04a0-6589-4a3a-99df-8bd0b3331ce1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=807849094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.807849094
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.4254363692
Short name T2232
Test name
Test status
Simulation time 245121335 ps
CPU time 1.01 seconds
Started Aug 17 06:09:12 PM PDT 24
Finished Aug 17 06:09:14 PM PDT 24
Peak memory 207476 kb
Host smart-cad140ce-f238-47eb-8d2b-5847ad33762c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4254363692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.4254363692
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.247167822
Short name T910
Test name
Test status
Simulation time 209119406 ps
CPU time 0.9 seconds
Started Aug 17 06:09:18 PM PDT 24
Finished Aug 17 06:09:19 PM PDT 24
Peak memory 207468 kb
Host smart-a72e0241-25a0-49a4-9bf1-b55871894202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24716
7822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.247167822
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.839857079
Short name T2401
Test name
Test status
Simulation time 2521644373 ps
CPU time 18.05 seconds
Started Aug 17 06:09:18 PM PDT 24
Finished Aug 17 06:09:36 PM PDT 24
Peak memory 207788 kb
Host smart-885821d3-33d1-4cb1-ad97-a2952f147308
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=839857079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.839857079
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3026009042
Short name T2250
Test name
Test status
Simulation time 151850564 ps
CPU time 0.81 seconds
Started Aug 17 06:09:16 PM PDT 24
Finished Aug 17 06:09:17 PM PDT 24
Peak memory 207472 kb
Host smart-b2b24598-9aba-4048-988f-d14db68d8257
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3026009042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3026009042
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2057063300
Short name T1143
Test name
Test status
Simulation time 154179344 ps
CPU time 0.87 seconds
Started Aug 17 06:09:13 PM PDT 24
Finished Aug 17 06:09:14 PM PDT 24
Peak memory 207476 kb
Host smart-6bb6053d-f7f9-4c5f-8d9f-2df05e035ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20570
63300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2057063300
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3911039677
Short name T895
Test name
Test status
Simulation time 192752408 ps
CPU time 0.93 seconds
Started Aug 17 06:09:21 PM PDT 24
Finished Aug 17 06:09:22 PM PDT 24
Peak memory 207460 kb
Host smart-1b8a93ea-4256-4cf5-af32-f8ed62adbad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39110
39677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3911039677
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2578707024
Short name T529
Test name
Test status
Simulation time 159765687 ps
CPU time 0.86 seconds
Started Aug 17 06:09:10 PM PDT 24
Finished Aug 17 06:09:11 PM PDT 24
Peak memory 207444 kb
Host smart-760c7c43-9421-46dc-87d7-93ca3b580fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25787
07024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2578707024
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.4248649829
Short name T2772
Test name
Test status
Simulation time 165763480 ps
CPU time 0.89 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 207336 kb
Host smart-485c87c1-eb33-4876-aff4-dcba84e1512f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42486
49829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.4248649829
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3278017017
Short name T192
Test name
Test status
Simulation time 147961931 ps
CPU time 0.83 seconds
Started Aug 17 06:09:20 PM PDT 24
Finished Aug 17 06:09:21 PM PDT 24
Peak memory 207548 kb
Host smart-2bcb2812-893e-4d08-ae8e-9355bd0d1181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32780
17017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3278017017
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1521473018
Short name T1984
Test name
Test status
Simulation time 194872036 ps
CPU time 1.02 seconds
Started Aug 17 06:09:14 PM PDT 24
Finished Aug 17 06:09:15 PM PDT 24
Peak memory 207564 kb
Host smart-9800bbdc-6840-484e-9b48-29ea2d043302
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1521473018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1521473018
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2298771584
Short name T2526
Test name
Test status
Simulation time 218230360 ps
CPU time 0.87 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 207452 kb
Host smart-fc87780f-1bca-4e0d-8547-62b8f1a1437a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987
71584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2298771584
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.957643533
Short name T985
Test name
Test status
Simulation time 19882090330 ps
CPU time 53.77 seconds
Started Aug 17 06:09:15 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 215940 kb
Host smart-0489aff7-9e1b-4610-8bcd-17e08e3e483c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95764
3533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.957643533
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3278541780
Short name T367
Test name
Test status
Simulation time 171459117 ps
CPU time 0.93 seconds
Started Aug 17 06:09:15 PM PDT 24
Finished Aug 17 06:09:16 PM PDT 24
Peak memory 207536 kb
Host smart-f23eb7b7-7e4f-490d-a497-848c4dfc06f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32785
41780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3278541780
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.401999234
Short name T1647
Test name
Test status
Simulation time 197201512 ps
CPU time 0.9 seconds
Started Aug 17 06:09:17 PM PDT 24
Finished Aug 17 06:09:18 PM PDT 24
Peak memory 207432 kb
Host smart-2fb325f0-de06-4ce0-86b1-19cc358198f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40199
9234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.401999234
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2672143270
Short name T1633
Test name
Test status
Simulation time 229900921 ps
CPU time 0.95 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 207236 kb
Host smart-17ce32e1-6526-4853-a2cb-23830c70a578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26721
43270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2672143270
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3204537722
Short name T1960
Test name
Test status
Simulation time 159061659 ps
CPU time 0.89 seconds
Started Aug 17 06:09:22 PM PDT 24
Finished Aug 17 06:09:23 PM PDT 24
Peak memory 207480 kb
Host smart-fd015b6c-5920-4d4d-8a40-6f80fa4b64fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32045
37722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3204537722
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1748095545
Short name T1596
Test name
Test status
Simulation time 163374486 ps
CPU time 0.87 seconds
Started Aug 17 06:09:21 PM PDT 24
Finished Aug 17 06:09:22 PM PDT 24
Peak memory 207484 kb
Host smart-64e2278f-1008-4be5-ad05-9c67c0703fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17480
95545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1748095545
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_rx_full.3250618471
Short name T3212
Test name
Test status
Simulation time 352735240 ps
CPU time 1.33 seconds
Started Aug 17 06:09:24 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207460 kb
Host smart-e253ee75-cf0f-4994-aef7-9c7a974b2ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32506
18471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.3250618471
Directory /workspace/37.usbdev_rx_full/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2535305324
Short name T2672
Test name
Test status
Simulation time 163672248 ps
CPU time 0.87 seconds
Started Aug 17 06:09:24 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207516 kb
Host smart-06cad7dd-1654-44a7-82a0-7cbedde5b3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25353
05324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2535305324
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2456276220
Short name T966
Test name
Test status
Simulation time 159729955 ps
CPU time 0.84 seconds
Started Aug 17 06:09:21 PM PDT 24
Finished Aug 17 06:09:21 PM PDT 24
Peak memory 207464 kb
Host smart-7cf7b85d-0a51-4d95-863e-9d23cdba13d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
76220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2456276220
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1909951295
Short name T2166
Test name
Test status
Simulation time 203805552 ps
CPU time 1.04 seconds
Started Aug 17 06:09:34 PM PDT 24
Finished Aug 17 06:09:35 PM PDT 24
Peak memory 207452 kb
Host smart-6c69cc88-14bb-4e39-b996-068abfea84b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19099
51295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1909951295
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.286788505
Short name T928
Test name
Test status
Simulation time 2295851135 ps
CPU time 66.2 seconds
Started Aug 17 06:09:35 PM PDT 24
Finished Aug 17 06:10:41 PM PDT 24
Peak memory 217580 kb
Host smart-9bfcc18f-320b-48b2-8b99-0c42809ccf1a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=286788505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.286788505
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2734274628
Short name T2724
Test name
Test status
Simulation time 186993820 ps
CPU time 0.89 seconds
Started Aug 17 06:09:26 PM PDT 24
Finished Aug 17 06:09:27 PM PDT 24
Peak memory 207540 kb
Host smart-4cbc3c49-11e6-44d4-b0bf-970e46eb0f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27342
74628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2734274628
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1523648214
Short name T797
Test name
Test status
Simulation time 148891912 ps
CPU time 0.86 seconds
Started Aug 17 06:09:24 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207564 kb
Host smart-1ffd9d89-1392-49ee-81a3-8486268bc572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15236
48214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1523648214
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.1619214362
Short name T2121
Test name
Test status
Simulation time 479903635 ps
CPU time 1.5 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:21 PM PDT 24
Peak memory 207516 kb
Host smart-8e2fe06f-1a1d-4635-8815-c4354da5d61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16192
14362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.1619214362
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3049043510
Short name T3139
Test name
Test status
Simulation time 1759030317 ps
CPU time 13.68 seconds
Started Aug 17 06:09:33 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 217416 kb
Host smart-ec2d0f92-23c3-4273-9738-f79c070c5d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30490
43510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3049043510
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.3841129360
Short name T2952
Test name
Test status
Simulation time 1112119534 ps
CPU time 28.22 seconds
Started Aug 17 06:09:12 PM PDT 24
Finished Aug 17 06:09:40 PM PDT 24
Peak memory 207604 kb
Host smart-a4cc8311-04a7-42e9-8ba6-f4afaf578954
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841129360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.3841129360
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_tx_rx_disruption.898739499
Short name T2917
Test name
Test status
Simulation time 413735241 ps
CPU time 1.4 seconds
Started Aug 17 06:09:24 PM PDT 24
Finished Aug 17 06:09:26 PM PDT 24
Peak memory 207496 kb
Host smart-e788a052-2b07-49d5-99b8-546991cdd2c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898739499 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.usbdev_tx_rx_disruption.898739499
Directory /workspace/37.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/370.usbdev_tx_rx_disruption.2197195182
Short name T2267
Test name
Test status
Simulation time 610631944 ps
CPU time 1.65 seconds
Started Aug 17 06:12:17 PM PDT 24
Finished Aug 17 06:12:19 PM PDT 24
Peak memory 207532 kb
Host smart-7cc79afc-cb7d-4d48-a5d9-69e59fe8a00d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197195182 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 370.usbdev_tx_rx_disruption.2197195182
Directory /workspace/370.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/371.usbdev_tx_rx_disruption.1453255491
Short name T173
Test name
Test status
Simulation time 483468692 ps
CPU time 1.67 seconds
Started Aug 17 06:12:38 PM PDT 24
Finished Aug 17 06:12:40 PM PDT 24
Peak memory 207544 kb
Host smart-11838f82-bebd-4b3b-9746-db4b453f1c11
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453255491 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 371.usbdev_tx_rx_disruption.1453255491
Directory /workspace/371.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/372.usbdev_tx_rx_disruption.2940637743
Short name T1420
Test name
Test status
Simulation time 472850943 ps
CPU time 1.44 seconds
Started Aug 17 06:12:28 PM PDT 24
Finished Aug 17 06:12:29 PM PDT 24
Peak memory 207564 kb
Host smart-2f07bea0-30a7-4eb9-a5fb-b52a8f05b6f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940637743 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 372.usbdev_tx_rx_disruption.2940637743
Directory /workspace/372.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/373.usbdev_tx_rx_disruption.3074013398
Short name T953
Test name
Test status
Simulation time 503672765 ps
CPU time 1.61 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207484 kb
Host smart-a843ad18-44d9-43bd-accf-f90922f5ea80
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074013398 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 373.usbdev_tx_rx_disruption.3074013398
Directory /workspace/373.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/374.usbdev_tx_rx_disruption.710398647
Short name T1787
Test name
Test status
Simulation time 609461547 ps
CPU time 1.57 seconds
Started Aug 17 06:12:20 PM PDT 24
Finished Aug 17 06:12:21 PM PDT 24
Peak memory 207564 kb
Host smart-f400a57a-326b-4a79-a931-23ff4ae0080b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710398647 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 374.usbdev_tx_rx_disruption.710398647
Directory /workspace/374.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/375.usbdev_tx_rx_disruption.1767686784
Short name T198
Test name
Test status
Simulation time 554527932 ps
CPU time 1.71 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207544 kb
Host smart-c916667a-7333-463e-a49d-754ee1989d00
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767686784 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 375.usbdev_tx_rx_disruption.1767686784
Directory /workspace/375.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/376.usbdev_tx_rx_disruption.1823210866
Short name T1611
Test name
Test status
Simulation time 487084447 ps
CPU time 1.43 seconds
Started Aug 17 06:12:25 PM PDT 24
Finished Aug 17 06:12:27 PM PDT 24
Peak memory 207520 kb
Host smart-c87015e4-5400-4be0-8b75-4e9364a1941c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823210866 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 376.usbdev_tx_rx_disruption.1823210866
Directory /workspace/376.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/377.usbdev_tx_rx_disruption.2302632962
Short name T2402
Test name
Test status
Simulation time 574878122 ps
CPU time 1.76 seconds
Started Aug 17 06:12:28 PM PDT 24
Finished Aug 17 06:12:30 PM PDT 24
Peak memory 207548 kb
Host smart-1f90d88e-2a5f-4c52-937b-0d4990cb05b2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302632962 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 377.usbdev_tx_rx_disruption.2302632962
Directory /workspace/377.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/378.usbdev_tx_rx_disruption.2462413557
Short name T172
Test name
Test status
Simulation time 580064300 ps
CPU time 1.77 seconds
Started Aug 17 06:12:15 PM PDT 24
Finished Aug 17 06:12:17 PM PDT 24
Peak memory 207536 kb
Host smart-7cbcf3fc-e9d2-4a6d-8950-b25da98b444f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462413557 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 378.usbdev_tx_rx_disruption.2462413557
Directory /workspace/378.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/379.usbdev_tx_rx_disruption.2656334596
Short name T2025
Test name
Test status
Simulation time 566945363 ps
CPU time 1.78 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207560 kb
Host smart-c5f232bf-a5af-4ad3-bb01-59c2d7b5f0e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656334596 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 379.usbdev_tx_rx_disruption.2656334596
Directory /workspace/379.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.568829140
Short name T1194
Test name
Test status
Simulation time 92439687 ps
CPU time 0.72 seconds
Started Aug 17 06:09:28 PM PDT 24
Finished Aug 17 06:09:29 PM PDT 24
Peak memory 207408 kb
Host smart-af34e070-a4fa-4bb7-a4f3-849e4577e002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=568829140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.568829140
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.631997388
Short name T3561
Test name
Test status
Simulation time 4453955879 ps
CPU time 7.62 seconds
Started Aug 17 06:09:25 PM PDT 24
Finished Aug 17 06:09:33 PM PDT 24
Peak memory 215928 kb
Host smart-680278ad-0aea-4b26-83cd-fb4e03f92932
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631997388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_disconnect.631997388
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3809247061
Short name T3361
Test name
Test status
Simulation time 19754170934 ps
CPU time 24.93 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:44 PM PDT 24
Peak memory 207816 kb
Host smart-bec83f4e-6977-47d0-ae7a-7ee5f83ee1e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809247061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3809247061
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3939564547
Short name T1841
Test name
Test status
Simulation time 25782111493 ps
CPU time 36.14 seconds
Started Aug 17 06:09:25 PM PDT 24
Finished Aug 17 06:10:01 PM PDT 24
Peak memory 215912 kb
Host smart-4b303184-dae3-47fa-b733-fd92a04748b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939564547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.3939564547
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2273234186
Short name T525
Test name
Test status
Simulation time 217670040 ps
CPU time 0.95 seconds
Started Aug 17 06:09:24 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207488 kb
Host smart-b206da0a-22af-4d92-8183-6f280057553b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22732
34186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2273234186
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.4072044108
Short name T632
Test name
Test status
Simulation time 156921251 ps
CPU time 0.87 seconds
Started Aug 17 06:09:22 PM PDT 24
Finished Aug 17 06:09:23 PM PDT 24
Peak memory 207528 kb
Host smart-ef09d4fe-f37a-465c-946f-fb2a1d29885b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40720
44108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.4072044108
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1900577293
Short name T2769
Test name
Test status
Simulation time 415259704 ps
CPU time 1.54 seconds
Started Aug 17 06:09:33 PM PDT 24
Finished Aug 17 06:09:35 PM PDT 24
Peak memory 207540 kb
Host smart-7e43824a-944c-43e7-8afd-0f242fc905e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19005
77293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1900577293
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1024469535
Short name T3451
Test name
Test status
Simulation time 836840998 ps
CPU time 2.36 seconds
Started Aug 17 06:09:39 PM PDT 24
Finished Aug 17 06:09:41 PM PDT 24
Peak memory 207656 kb
Host smart-a59459b0-af5c-4ad0-ba7f-e17ab0209b1f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1024469535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1024469535
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3439530231
Short name T3563
Test name
Test status
Simulation time 42773205175 ps
CPU time 75.24 seconds
Started Aug 17 06:09:25 PM PDT 24
Finished Aug 17 06:10:41 PM PDT 24
Peak memory 207828 kb
Host smart-0a99dcc3-6fc1-452a-a3f6-043a9768fb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34395
30231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3439530231
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.3355161660
Short name T1298
Test name
Test status
Simulation time 1341175461 ps
CPU time 30.11 seconds
Started Aug 17 06:09:21 PM PDT 24
Finished Aug 17 06:09:51 PM PDT 24
Peak memory 207636 kb
Host smart-f0f86a4e-a90e-4393-88db-4d1f9b4bae9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355161660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.3355161660
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2802001207
Short name T2731
Test name
Test status
Simulation time 919207120 ps
CPU time 1.93 seconds
Started Aug 17 06:09:34 PM PDT 24
Finished Aug 17 06:09:36 PM PDT 24
Peak memory 207508 kb
Host smart-b044c0d8-886f-45b1-bf34-a4c84bea04f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28020
01207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2802001207
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.658678790
Short name T3160
Test name
Test status
Simulation time 135477226 ps
CPU time 0.85 seconds
Started Aug 17 06:09:25 PM PDT 24
Finished Aug 17 06:09:26 PM PDT 24
Peak memory 207468 kb
Host smart-2e767ecf-7e6e-4070-86e3-344214e932fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65867
8790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.658678790
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3400357243
Short name T2420
Test name
Test status
Simulation time 56313873 ps
CPU time 0.71 seconds
Started Aug 17 06:09:25 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207316 kb
Host smart-e81e6eab-6556-446b-bcee-d785ca3f1dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34003
57243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3400357243
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1464617143
Short name T3174
Test name
Test status
Simulation time 826599373 ps
CPU time 2.37 seconds
Started Aug 17 06:09:25 PM PDT 24
Finished Aug 17 06:09:27 PM PDT 24
Peak memory 207740 kb
Host smart-7cfc6314-0e7b-4404-b73e-444bf075bef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14646
17143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1464617143
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_types.1557372015
Short name T2655
Test name
Test status
Simulation time 289241580 ps
CPU time 1.17 seconds
Started Aug 17 06:09:23 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207464 kb
Host smart-a13aa052-0a42-41b5-a755-beaba4707335
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1557372015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.1557372015
Directory /workspace/38.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1423418775
Short name T220
Test name
Test status
Simulation time 170939369 ps
CPU time 1.79 seconds
Started Aug 17 06:09:18 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 207656 kb
Host smart-38100072-2833-4a27-82cf-642d7bc47786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234
18775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1423418775
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.781372962
Short name T684
Test name
Test status
Simulation time 218862657 ps
CPU time 1.13 seconds
Started Aug 17 06:09:37 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 215828 kb
Host smart-70ef290a-df64-4034-baa3-e58b8ad37516
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=781372962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.781372962
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2499471815
Short name T2651
Test name
Test status
Simulation time 140999418 ps
CPU time 0.81 seconds
Started Aug 17 06:09:21 PM PDT 24
Finished Aug 17 06:09:22 PM PDT 24
Peak memory 207456 kb
Host smart-acf7371a-b20b-47c1-acbd-d64437f23027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24994
71815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2499471815
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1823001553
Short name T3233
Test name
Test status
Simulation time 165686034 ps
CPU time 0.91 seconds
Started Aug 17 06:09:29 PM PDT 24
Finished Aug 17 06:09:30 PM PDT 24
Peak memory 207460 kb
Host smart-1f5cf0df-e82d-4054-9aa1-068dd8db450f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18230
01553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1823001553
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.2027183779
Short name T1236
Test name
Test status
Simulation time 4309000845 ps
CPU time 135.89 seconds
Started Aug 17 06:09:22 PM PDT 24
Finished Aug 17 06:11:38 PM PDT 24
Peak memory 218280 kb
Host smart-289cd084-d45b-4cf8-a5bf-5997a0fa2921
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2027183779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.2027183779
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.4061388802
Short name T1312
Test name
Test status
Simulation time 11049774299 ps
CPU time 147.18 seconds
Started Aug 17 06:09:25 PM PDT 24
Finished Aug 17 06:11:52 PM PDT 24
Peak memory 207820 kb
Host smart-c8bc7063-8ba2-40f4-9596-f9766e43f273
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4061388802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.4061388802
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1547633123
Short name T2110
Test name
Test status
Simulation time 176516948 ps
CPU time 0.95 seconds
Started Aug 17 06:09:34 PM PDT 24
Finished Aug 17 06:09:35 PM PDT 24
Peak memory 207556 kb
Host smart-b0889315-c24f-4b52-a42a-55354a9627b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476
33123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1547633123
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1190086645
Short name T1318
Test name
Test status
Simulation time 30802858923 ps
CPU time 50.82 seconds
Started Aug 17 06:09:26 PM PDT 24
Finished Aug 17 06:10:17 PM PDT 24
Peak memory 207876 kb
Host smart-4f8f294c-8013-4045-92b0-c1936fbf3824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11900
86645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1190086645
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.291729213
Short name T1403
Test name
Test status
Simulation time 3317083540 ps
CPU time 5.02 seconds
Started Aug 17 06:09:22 PM PDT 24
Finished Aug 17 06:09:27 PM PDT 24
Peak memory 207708 kb
Host smart-3a0b46f5-c51a-4fdb-bcb9-685af3150b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29172
9213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.291729213
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.268237352
Short name T1167
Test name
Test status
Simulation time 2674174791 ps
CPU time 77.91 seconds
Started Aug 17 06:09:42 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 215964 kb
Host smart-d67e8772-e464-4f15-9a32-4ba897f723d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=268237352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.268237352
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.1773622687
Short name T1429
Test name
Test status
Simulation time 2670988373 ps
CPU time 25.47 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:45 PM PDT 24
Peak memory 215936 kb
Host smart-b016d56b-bfdb-49a0-a8f1-7d6117478182
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1773622687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.1773622687
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3873410151
Short name T2634
Test name
Test status
Simulation time 287308931 ps
CPU time 1.04 seconds
Started Aug 17 06:09:28 PM PDT 24
Finished Aug 17 06:09:29 PM PDT 24
Peak memory 207480 kb
Host smart-c4d6c227-ee6c-4ad8-b809-07ea990847da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3873410151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3873410151
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1458628866
Short name T1232
Test name
Test status
Simulation time 187474792 ps
CPU time 0.97 seconds
Started Aug 17 06:09:41 PM PDT 24
Finished Aug 17 06:09:42 PM PDT 24
Peak memory 207440 kb
Host smart-0e72ff01-6c9a-48c6-a6f5-cc184ae54635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14586
28866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1458628866
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.3356432584
Short name T2325
Test name
Test status
Simulation time 3915952482 ps
CPU time 32.5 seconds
Started Aug 17 06:09:23 PM PDT 24
Finished Aug 17 06:09:55 PM PDT 24
Peak memory 217360 kb
Host smart-16c57cdb-f2b9-4759-bf10-084824660545
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3356432584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.3356432584
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.23240760
Short name T2547
Test name
Test status
Simulation time 153013725 ps
CPU time 0.83 seconds
Started Aug 17 06:09:37 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 207432 kb
Host smart-00d95647-8273-4b28-8e9a-7de04940bcc8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=23240760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.23240760
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3330721936
Short name T2748
Test name
Test status
Simulation time 196435957 ps
CPU time 0.91 seconds
Started Aug 17 06:09:37 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 207460 kb
Host smart-89cf1ce3-96d3-4b04-b069-55c25661c9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
21936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3330721936
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1966192284
Short name T147
Test name
Test status
Simulation time 252328354 ps
CPU time 1.04 seconds
Started Aug 17 06:09:43 PM PDT 24
Finished Aug 17 06:09:45 PM PDT 24
Peak memory 207424 kb
Host smart-29350376-7721-4b65-bba5-2af24f770435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19661
92284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1966192284
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2437051622
Short name T3472
Test name
Test status
Simulation time 181457442 ps
CPU time 0.91 seconds
Started Aug 17 06:09:38 PM PDT 24
Finished Aug 17 06:09:39 PM PDT 24
Peak memory 207424 kb
Host smart-668e4889-804c-4952-9aa8-ad98f6adcf3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24370
51622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2437051622
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2603913624
Short name T869
Test name
Test status
Simulation time 178412985 ps
CPU time 0.86 seconds
Started Aug 17 06:09:23 PM PDT 24
Finished Aug 17 06:09:24 PM PDT 24
Peak memory 207472 kb
Host smart-8a464633-3b28-47d5-b9f5-4f05862c54ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26039
13624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2603913624
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.946744597
Short name T2151
Test name
Test status
Simulation time 176336083 ps
CPU time 0.89 seconds
Started Aug 17 06:09:20 PM PDT 24
Finished Aug 17 06:09:21 PM PDT 24
Peak memory 207452 kb
Host smart-5fee7713-32ff-4f5b-a5dd-902dc587dc02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94674
4597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.946744597
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2096473373
Short name T2384
Test name
Test status
Simulation time 190961488 ps
CPU time 0.97 seconds
Started Aug 17 06:09:31 PM PDT 24
Finished Aug 17 06:09:32 PM PDT 24
Peak memory 207532 kb
Host smart-35a418c6-1d21-41cb-90de-d883fc9a4e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20964
73373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2096473373
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2300924027
Short name T1645
Test name
Test status
Simulation time 196415827 ps
CPU time 0.93 seconds
Started Aug 17 06:09:22 PM PDT 24
Finished Aug 17 06:09:23 PM PDT 24
Peak memory 207480 kb
Host smart-2e388f67-aa2b-4b51-9987-69c47a386d85
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2300924027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2300924027
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.84060729
Short name T1761
Test name
Test status
Simulation time 165242670 ps
CPU time 0.86 seconds
Started Aug 17 06:09:38 PM PDT 24
Finished Aug 17 06:09:39 PM PDT 24
Peak memory 207396 kb
Host smart-8434cd62-73c8-40e8-9a04-ea1488138ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84060
729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.84060729
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.4148625009
Short name T3237
Test name
Test status
Simulation time 37857014 ps
CPU time 0.71 seconds
Started Aug 17 06:09:37 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 207504 kb
Host smart-10cb74de-97ce-4981-bc1e-ec3f68433e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41486
25009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.4148625009
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.810271953
Short name T3016
Test name
Test status
Simulation time 10840945832 ps
CPU time 25.72 seconds
Started Aug 17 06:09:38 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 220288 kb
Host smart-0d722863-34d6-4cf9-a1a5-7fef7704b7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81027
1953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.810271953
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1561974116
Short name T3085
Test name
Test status
Simulation time 165615451 ps
CPU time 0.92 seconds
Started Aug 17 06:09:21 PM PDT 24
Finished Aug 17 06:09:22 PM PDT 24
Peak memory 207496 kb
Host smart-08a8db27-0ae1-429c-8835-66b3dfd62015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15619
74116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1561974116
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2083426553
Short name T2463
Test name
Test status
Simulation time 284489094 ps
CPU time 1.02 seconds
Started Aug 17 06:09:24 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207444 kb
Host smart-884c0e0d-9341-4e7c-8c79-8ced0b675258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20834
26553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2083426553
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.4226082747
Short name T1132
Test name
Test status
Simulation time 166687826 ps
CPU time 0.91 seconds
Started Aug 17 06:09:19 PM PDT 24
Finished Aug 17 06:09:20 PM PDT 24
Peak memory 207492 kb
Host smart-1150830a-b4e3-4b0b-8d15-bbcf525452f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
82747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.4226082747
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.494965199
Short name T538
Test name
Test status
Simulation time 180154081 ps
CPU time 0.91 seconds
Started Aug 17 06:09:28 PM PDT 24
Finished Aug 17 06:09:29 PM PDT 24
Peak memory 207460 kb
Host smart-12244536-1c5c-4716-b98c-6ffec6c9a167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49496
5199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.494965199
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1097674788
Short name T1252
Test name
Test status
Simulation time 176121504 ps
CPU time 0.89 seconds
Started Aug 17 06:09:36 PM PDT 24
Finished Aug 17 06:09:37 PM PDT 24
Peak memory 207456 kb
Host smart-369ecea6-38d3-42e6-8458-62cb2f94a7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10976
74788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1097674788
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_rx_full.3865905663
Short name T1789
Test name
Test status
Simulation time 276962350 ps
CPU time 1.16 seconds
Started Aug 17 06:09:43 PM PDT 24
Finished Aug 17 06:09:44 PM PDT 24
Peak memory 207444 kb
Host smart-c92d972e-d59c-4453-8a94-c16ed52ae385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38659
05663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.3865905663
Directory /workspace/38.usbdev_rx_full/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3465951240
Short name T1458
Test name
Test status
Simulation time 173773958 ps
CPU time 0.9 seconds
Started Aug 17 06:09:34 PM PDT 24
Finished Aug 17 06:09:35 PM PDT 24
Peak memory 207544 kb
Host smart-e3b5cfdb-2849-4986-ad11-e711ba0a18b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34659
51240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3465951240
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3113191188
Short name T2687
Test name
Test status
Simulation time 163145654 ps
CPU time 0.88 seconds
Started Aug 17 06:09:30 PM PDT 24
Finished Aug 17 06:09:31 PM PDT 24
Peak memory 207516 kb
Host smart-06e6bd5a-27fb-4257-8d16-92796769fb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31131
91188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3113191188
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3230577485
Short name T1873
Test name
Test status
Simulation time 228847926 ps
CPU time 1.02 seconds
Started Aug 17 06:09:33 PM PDT 24
Finished Aug 17 06:09:34 PM PDT 24
Peak memory 207408 kb
Host smart-00951aac-8cf0-4def-8fe7-68cdfca8d7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32305
77485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3230577485
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2690369968
Short name T1732
Test name
Test status
Simulation time 1671939933 ps
CPU time 13.12 seconds
Started Aug 17 06:09:30 PM PDT 24
Finished Aug 17 06:09:43 PM PDT 24
Peak memory 223996 kb
Host smart-a1b642eb-7aa2-43a0-99eb-116d8acc49fb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2690369968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2690369968
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3865089051
Short name T520
Test name
Test status
Simulation time 184370873 ps
CPU time 0.91 seconds
Started Aug 17 06:09:27 PM PDT 24
Finished Aug 17 06:09:28 PM PDT 24
Peak memory 207424 kb
Host smart-a429cf2d-f32d-46e1-9f4b-8cbf49922366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38650
89051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3865089051
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.502886790
Short name T1344
Test name
Test status
Simulation time 171443586 ps
CPU time 0.94 seconds
Started Aug 17 06:09:36 PM PDT 24
Finished Aug 17 06:09:37 PM PDT 24
Peak memory 207468 kb
Host smart-f15c1378-302f-499b-9ec2-80e122bf26c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50288
6790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.502886790
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.278894007
Short name T1516
Test name
Test status
Simulation time 1401667015 ps
CPU time 3.04 seconds
Started Aug 17 06:09:28 PM PDT 24
Finished Aug 17 06:09:32 PM PDT 24
Peak memory 207716 kb
Host smart-8a593aa2-2acc-4fac-ace0-4505ecfa09a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27889
4007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.278894007
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.744261773
Short name T1285
Test name
Test status
Simulation time 3739749598 ps
CPU time 37.52 seconds
Started Aug 17 06:09:39 PM PDT 24
Finished Aug 17 06:10:16 PM PDT 24
Peak memory 216020 kb
Host smart-c7e89eca-dae3-40ed-b0f1-166c1efd3033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74426
1773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.744261773
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.3288413594
Short name T1072
Test name
Test status
Simulation time 4790167472 ps
CPU time 40.98 seconds
Started Aug 17 06:09:24 PM PDT 24
Finished Aug 17 06:10:05 PM PDT 24
Peak memory 207736 kb
Host smart-698c1ee3-c607-4819-8e64-dcefd04f405a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288413594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.3288413594
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_tx_rx_disruption.2088066764
Short name T1048
Test name
Test status
Simulation time 574157468 ps
CPU time 1.63 seconds
Started Aug 17 06:09:28 PM PDT 24
Finished Aug 17 06:09:30 PM PDT 24
Peak memory 207516 kb
Host smart-d8dbb709-c5ee-42f2-aab4-dcc8d18393cd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088066764 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.usbdev_tx_rx_disruption.2088066764
Directory /workspace/38.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/380.usbdev_tx_rx_disruption.3930333946
Short name T2048
Test name
Test status
Simulation time 491281163 ps
CPU time 1.63 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207536 kb
Host smart-8d9ff034-11db-4f37-8519-6a334eac87bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930333946 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 380.usbdev_tx_rx_disruption.3930333946
Directory /workspace/380.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/381.usbdev_tx_rx_disruption.3201640650
Short name T2746
Test name
Test status
Simulation time 600344587 ps
CPU time 1.8 seconds
Started Aug 17 06:12:33 PM PDT 24
Finished Aug 17 06:12:35 PM PDT 24
Peak memory 207544 kb
Host smart-42a17515-0092-409e-8e15-c2be9702ce3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201640650 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 381.usbdev_tx_rx_disruption.3201640650
Directory /workspace/381.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/382.usbdev_tx_rx_disruption.3771034535
Short name T1708
Test name
Test status
Simulation time 592194480 ps
CPU time 1.62 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:15 PM PDT 24
Peak memory 207536 kb
Host smart-675fec20-ef5e-455e-8156-e7519a2c6f69
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771034535 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 382.usbdev_tx_rx_disruption.3771034535
Directory /workspace/382.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/383.usbdev_tx_rx_disruption.2509915530
Short name T176
Test name
Test status
Simulation time 430169344 ps
CPU time 1.34 seconds
Started Aug 17 06:12:22 PM PDT 24
Finished Aug 17 06:12:24 PM PDT 24
Peak memory 207556 kb
Host smart-3fb33a15-e051-48dc-83d8-64cafc213200
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509915530 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 383.usbdev_tx_rx_disruption.2509915530
Directory /workspace/383.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/384.usbdev_tx_rx_disruption.4114772622
Short name T2650
Test name
Test status
Simulation time 557905777 ps
CPU time 1.65 seconds
Started Aug 17 06:12:19 PM PDT 24
Finished Aug 17 06:12:21 PM PDT 24
Peak memory 207560 kb
Host smart-6a7a9e8a-5abe-46dc-8407-a068361c4d2e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114772622 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 384.usbdev_tx_rx_disruption.4114772622
Directory /workspace/384.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/385.usbdev_tx_rx_disruption.3803799981
Short name T791
Test name
Test status
Simulation time 514766546 ps
CPU time 1.57 seconds
Started Aug 17 06:12:29 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207600 kb
Host smart-073723a5-3c89-42e1-a7fe-e4afa895cd01
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803799981 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 385.usbdev_tx_rx_disruption.3803799981
Directory /workspace/385.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/386.usbdev_tx_rx_disruption.2228128750
Short name T2410
Test name
Test status
Simulation time 504209450 ps
CPU time 1.57 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207512 kb
Host smart-40b1825a-2cb5-45a6-8255-9d45941b99c1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228128750 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 386.usbdev_tx_rx_disruption.2228128750
Directory /workspace/386.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/387.usbdev_tx_rx_disruption.2024202242
Short name T1126
Test name
Test status
Simulation time 589398128 ps
CPU time 1.56 seconds
Started Aug 17 06:12:26 PM PDT 24
Finished Aug 17 06:12:27 PM PDT 24
Peak memory 207512 kb
Host smart-874b4ff4-0f23-49aa-aa0b-9b4ff1dfc79d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024202242 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 387.usbdev_tx_rx_disruption.2024202242
Directory /workspace/387.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/388.usbdev_tx_rx_disruption.285729885
Short name T626
Test name
Test status
Simulation time 507610925 ps
CPU time 1.53 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:15 PM PDT 24
Peak memory 207576 kb
Host smart-541ba464-6f7c-41c3-bd81-bc3cdeee8906
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285729885 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 388.usbdev_tx_rx_disruption.285729885
Directory /workspace/388.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/389.usbdev_tx_rx_disruption.3626279601
Short name T2347
Test name
Test status
Simulation time 499183703 ps
CPU time 1.49 seconds
Started Aug 17 06:12:19 PM PDT 24
Finished Aug 17 06:12:21 PM PDT 24
Peak memory 207544 kb
Host smart-62cb982f-d9bc-4c2b-88af-b5c94ce2fcfc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626279601 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 389.usbdev_tx_rx_disruption.3626279601
Directory /workspace/389.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.2352670716
Short name T3390
Test name
Test status
Simulation time 41058425 ps
CPU time 0.72 seconds
Started Aug 17 06:09:55 PM PDT 24
Finished Aug 17 06:09:56 PM PDT 24
Peak memory 207380 kb
Host smart-ade0f24f-850f-4755-8edd-217aa575fbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2352670716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.2352670716
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.467572098
Short name T2909
Test name
Test status
Simulation time 4585748707 ps
CPU time 6.79 seconds
Started Aug 17 06:09:40 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 215988 kb
Host smart-f2b56ff7-ee94-40b2-b269-a644f55a6cbe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467572098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ao
n_wake_disconnect.467572098
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1298577586
Short name T3505
Test name
Test status
Simulation time 21274979161 ps
CPU time 25.13 seconds
Started Aug 17 06:09:29 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207768 kb
Host smart-301b7a13-46a4-4c99-b84b-c73b576b3c33
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298577586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1298577586
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3629050301
Short name T2131
Test name
Test status
Simulation time 23984439472 ps
CPU time 33.18 seconds
Started Aug 17 06:09:25 PM PDT 24
Finished Aug 17 06:09:59 PM PDT 24
Peak memory 215948 kb
Host smart-bcf15c6e-dd2b-486b-862b-608c8458eebb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629050301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.3629050301
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1357877244
Short name T2664
Test name
Test status
Simulation time 180190868 ps
CPU time 1.01 seconds
Started Aug 17 06:09:37 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 207448 kb
Host smart-323b622f-dc23-4e52-b9b8-c3ed9be469c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13578
77244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1357877244
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3338838878
Short name T1127
Test name
Test status
Simulation time 140486060 ps
CPU time 0.84 seconds
Started Aug 17 06:09:30 PM PDT 24
Finished Aug 17 06:09:31 PM PDT 24
Peak memory 207440 kb
Host smart-c96837d6-d828-457d-960d-7ec763dcc43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33388
38878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3338838878
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.424809100
Short name T528
Test name
Test status
Simulation time 239266477 ps
CPU time 1.04 seconds
Started Aug 17 06:09:31 PM PDT 24
Finished Aug 17 06:09:32 PM PDT 24
Peak memory 207564 kb
Host smart-d484b262-0505-460c-8315-c03314a09c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42480
9100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.424809100
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.434491108
Short name T1965
Test name
Test status
Simulation time 762519018 ps
CPU time 2.13 seconds
Started Aug 17 06:09:31 PM PDT 24
Finished Aug 17 06:09:33 PM PDT 24
Peak memory 207816 kb
Host smart-9fa102d7-7b61-4192-82b6-94b350ab03df
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=434491108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.434491108
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.996864399
Short name T3138
Test name
Test status
Simulation time 41245906879 ps
CPU time 66.4 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:10:52 PM PDT 24
Peak memory 207764 kb
Host smart-88061783-bc6b-4fc1-8f03-16f50c6c1bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99686
4399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.996864399
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.947480905
Short name T2805
Test name
Test status
Simulation time 725201497 ps
CPU time 14.66 seconds
Started Aug 17 06:09:40 PM PDT 24
Finished Aug 17 06:09:55 PM PDT 24
Peak memory 207760 kb
Host smart-71720c4a-c10d-401f-94c7-03e68e6f4124
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947480905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.947480905
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.4036588481
Short name T2600
Test name
Test status
Simulation time 540834002 ps
CPU time 1.54 seconds
Started Aug 17 06:09:26 PM PDT 24
Finished Aug 17 06:09:28 PM PDT 24
Peak memory 207392 kb
Host smart-ce870736-cf91-4399-8cb3-502083272850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40365
88481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.4036588481
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3273429855
Short name T1654
Test name
Test status
Simulation time 167143089 ps
CPU time 0.87 seconds
Started Aug 17 06:09:30 PM PDT 24
Finished Aug 17 06:09:31 PM PDT 24
Peak memory 207412 kb
Host smart-821951b4-bd01-41eb-8aec-509ff2ba98b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32734
29855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3273429855
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2760195517
Short name T750
Test name
Test status
Simulation time 31767132 ps
CPU time 0.68 seconds
Started Aug 17 06:09:37 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 207412 kb
Host smart-6929424a-a8e1-47a8-a571-70fa5c02d3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27601
95517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2760195517
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3091921493
Short name T3098
Test name
Test status
Simulation time 864440747 ps
CPU time 2.45 seconds
Started Aug 17 06:09:30 PM PDT 24
Finished Aug 17 06:09:33 PM PDT 24
Peak memory 207688 kb
Host smart-36de501c-8aa6-42f0-b0e9-6fccb341fe6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30919
21493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3091921493
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_types.2378822633
Short name T1583
Test name
Test status
Simulation time 233962672 ps
CPU time 0.99 seconds
Started Aug 17 06:09:37 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 207524 kb
Host smart-93abe5eb-ce8b-4dbe-b4c8-f3c3d22a3229
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2378822633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.2378822633
Directory /workspace/39.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2077221645
Short name T2930
Test name
Test status
Simulation time 189198413 ps
CPU time 2.52 seconds
Started Aug 17 06:09:27 PM PDT 24
Finished Aug 17 06:09:30 PM PDT 24
Peak memory 207624 kb
Host smart-ced56053-dc08-4e4e-aacf-2c79b3420ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20772
21645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2077221645
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2425325079
Short name T532
Test name
Test status
Simulation time 193345657 ps
CPU time 1.05 seconds
Started Aug 17 06:09:31 PM PDT 24
Finished Aug 17 06:09:32 PM PDT 24
Peak memory 215808 kb
Host smart-5345110f-c490-44c9-9d85-668c2f3efe39
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2425325079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2425325079
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2872863205
Short name T2903
Test name
Test status
Simulation time 154965116 ps
CPU time 0.83 seconds
Started Aug 17 06:09:28 PM PDT 24
Finished Aug 17 06:09:28 PM PDT 24
Peak memory 207484 kb
Host smart-c6a5a993-77c0-4a1d-b098-54889c1d6d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28728
63205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2872863205
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1702272199
Short name T2673
Test name
Test status
Simulation time 187762853 ps
CPU time 0.88 seconds
Started Aug 17 06:09:24 PM PDT 24
Finished Aug 17 06:09:25 PM PDT 24
Peak memory 207476 kb
Host smart-89f68b4b-2162-4814-b7a0-29d4840d189a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17022
72199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1702272199
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.1278060839
Short name T1094
Test name
Test status
Simulation time 4093617221 ps
CPU time 123.35 seconds
Started Aug 17 06:09:27 PM PDT 24
Finished Aug 17 06:11:31 PM PDT 24
Peak memory 224140 kb
Host smart-247a8700-a3ca-4551-aa62-319680ce87cf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1278060839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.1278060839
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.2602560217
Short name T99
Test name
Test status
Simulation time 3744656660 ps
CPU time 24.5 seconds
Started Aug 17 06:09:26 PM PDT 24
Finished Aug 17 06:09:50 PM PDT 24
Peak memory 207784 kb
Host smart-703654bc-b96b-4d07-9af4-38e80f464d9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2602560217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.2602560217
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2525267029
Short name T957
Test name
Test status
Simulation time 188167505 ps
CPU time 0.96 seconds
Started Aug 17 06:09:38 PM PDT 24
Finished Aug 17 06:09:39 PM PDT 24
Peak memory 207564 kb
Host smart-b28953c2-6475-4103-8272-99b3f763c121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25252
67029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2525267029
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.3929622345
Short name T730
Test name
Test status
Simulation time 21978660317 ps
CPU time 39.23 seconds
Started Aug 17 06:09:27 PM PDT 24
Finished Aug 17 06:10:07 PM PDT 24
Peak memory 216144 kb
Host smart-ba8eac6c-601a-4599-aab2-2426076d4080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39296
22345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.3929622345
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.779896532
Short name T2462
Test name
Test status
Simulation time 5485357435 ps
CPU time 7 seconds
Started Aug 17 06:09:32 PM PDT 24
Finished Aug 17 06:09:39 PM PDT 24
Peak memory 207772 kb
Host smart-8d3967f5-87ea-4f62-837a-77442c29df3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77989
6532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.779896532
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.4265707649
Short name T1926
Test name
Test status
Simulation time 3474977817 ps
CPU time 27.22 seconds
Started Aug 17 06:09:43 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 215972 kb
Host smart-22c269a3-e538-4896-8289-af4dfa90d80b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4265707649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.4265707649
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.105774238
Short name T1497
Test name
Test status
Simulation time 2390250842 ps
CPU time 70.37 seconds
Started Aug 17 06:09:30 PM PDT 24
Finished Aug 17 06:10:40 PM PDT 24
Peak memory 217344 kb
Host smart-01ab79b3-1c7c-485c-bd1a-18ef09c45f59
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=105774238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.105774238
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2081494039
Short name T3100
Test name
Test status
Simulation time 242335817 ps
CPU time 1.08 seconds
Started Aug 17 06:09:38 PM PDT 24
Finished Aug 17 06:09:39 PM PDT 24
Peak memory 207420 kb
Host smart-2ba7fff1-8591-4a16-bf0c-2b968f961c17
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2081494039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2081494039
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2589524988
Short name T1858
Test name
Test status
Simulation time 230096665 ps
CPU time 1.01 seconds
Started Aug 17 06:09:43 PM PDT 24
Finished Aug 17 06:09:45 PM PDT 24
Peak memory 207452 kb
Host smart-c99d0fbb-5ba8-499d-9ae6-8b714e2c91f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25895
24988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2589524988
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.109207940
Short name T2086
Test name
Test status
Simulation time 3808603708 ps
CPU time 42.93 seconds
Started Aug 17 06:09:35 PM PDT 24
Finished Aug 17 06:10:18 PM PDT 24
Peak memory 215948 kb
Host smart-9efb550a-bf09-43c5-9427-f5db0f511375
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=109207940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.109207940
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.667477236
Short name T1121
Test name
Test status
Simulation time 174986888 ps
CPU time 0.87 seconds
Started Aug 17 06:09:42 PM PDT 24
Finished Aug 17 06:09:43 PM PDT 24
Peak memory 207484 kb
Host smart-39a8b6b2-db39-4425-8b3c-37c00d6513b3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=667477236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.667477236
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1126891964
Short name T1794
Test name
Test status
Simulation time 144626194 ps
CPU time 0.82 seconds
Started Aug 17 06:09:48 PM PDT 24
Finished Aug 17 06:09:49 PM PDT 24
Peak memory 207412 kb
Host smart-e1e841f1-8ba5-4a18-b024-e466b0a6acf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11268
91964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1126891964
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1223162130
Short name T142
Test name
Test status
Simulation time 195333641 ps
CPU time 0.94 seconds
Started Aug 17 06:09:35 PM PDT 24
Finished Aug 17 06:09:36 PM PDT 24
Peak memory 207460 kb
Host smart-ad383da0-d5c6-4279-8e6c-351993f078b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12231
62130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1223162130
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2368052496
Short name T903
Test name
Test status
Simulation time 194723501 ps
CPU time 1.01 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207460 kb
Host smart-49399ae2-5dd3-4293-9dfc-63108c707c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23680
52496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2368052496
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1653485810
Short name T664
Test name
Test status
Simulation time 150977963 ps
CPU time 0.8 seconds
Started Aug 17 06:09:47 PM PDT 24
Finished Aug 17 06:09:48 PM PDT 24
Peak memory 207416 kb
Host smart-7fb136ba-8cef-4787-8c75-e8c3ec6f441c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16534
85810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1653485810
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2540252311
Short name T2966
Test name
Test status
Simulation time 208313871 ps
CPU time 0.95 seconds
Started Aug 17 06:09:49 PM PDT 24
Finished Aug 17 06:09:50 PM PDT 24
Peak memory 207540 kb
Host smart-f80cdb38-d46a-40b9-b3c3-1fd926ad78ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25402
52311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2540252311
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3606619838
Short name T728
Test name
Test status
Simulation time 196354341 ps
CPU time 0.89 seconds
Started Aug 17 06:09:35 PM PDT 24
Finished Aug 17 06:09:36 PM PDT 24
Peak memory 207496 kb
Host smart-1e407b35-bbe2-4120-8405-89ebd7ba6be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36066
19838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3606619838
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.4155814172
Short name T3434
Test name
Test status
Simulation time 279003466 ps
CPU time 1.07 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207484 kb
Host smart-f829ae19-ea4d-42a1-a6b0-6d4792b96dd7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4155814172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.4155814172
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3023748944
Short name T228
Test name
Test status
Simulation time 169914628 ps
CPU time 0.84 seconds
Started Aug 17 06:09:58 PM PDT 24
Finished Aug 17 06:09:59 PM PDT 24
Peak memory 207380 kb
Host smart-1ee52823-62f3-43c4-aa24-cbc58651965e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30237
48944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3023748944
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1169367294
Short name T31
Test name
Test status
Simulation time 97907583 ps
CPU time 0.75 seconds
Started Aug 17 06:09:41 PM PDT 24
Finished Aug 17 06:09:42 PM PDT 24
Peak memory 206448 kb
Host smart-af9955fc-bb12-4e06-929b-979f6ec4cc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11693
67294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1169367294
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.627663544
Short name T2082
Test name
Test status
Simulation time 6501677751 ps
CPU time 19.28 seconds
Started Aug 17 06:09:38 PM PDT 24
Finished Aug 17 06:09:58 PM PDT 24
Peak memory 215944 kb
Host smart-985717d6-4fed-47ba-b6cc-93fbc30c1a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62766
3544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.627663544
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1467041163
Short name T914
Test name
Test status
Simulation time 205723039 ps
CPU time 0.97 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207492 kb
Host smart-ce6e8f29-951c-4a90-884e-dfada4cff32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14670
41163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1467041163
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1319808676
Short name T2739
Test name
Test status
Simulation time 227590794 ps
CPU time 1.03 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207416 kb
Host smart-6ee63f9c-dd94-4156-85ac-b780b5d50413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13198
08676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1319808676
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3150122826
Short name T3452
Test name
Test status
Simulation time 227840668 ps
CPU time 1 seconds
Started Aug 17 06:09:33 PM PDT 24
Finished Aug 17 06:09:34 PM PDT 24
Peak memory 207404 kb
Host smart-19b557f3-e33c-4da0-87d3-bb74e3948bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31501
22826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3150122826
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1083914722
Short name T828
Test name
Test status
Simulation time 189038434 ps
CPU time 1 seconds
Started Aug 17 06:09:34 PM PDT 24
Finished Aug 17 06:09:35 PM PDT 24
Peak memory 207492 kb
Host smart-b451d86f-fa1d-4ce5-9b36-c0eb7caf2af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10839
14722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1083914722
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3967559735
Short name T1142
Test name
Test status
Simulation time 161242342 ps
CPU time 0.93 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207392 kb
Host smart-7e230a67-fe1f-434a-8507-63f86c7d5e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39675
59735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3967559735
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_rx_full.2961852031
Short name T47
Test name
Test status
Simulation time 377466017 ps
CPU time 1.32 seconds
Started Aug 17 06:09:39 PM PDT 24
Finished Aug 17 06:09:41 PM PDT 24
Peak memory 207448 kb
Host smart-aef6e73a-e603-43cc-97de-5f78daa7012b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29618
52031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.2961852031
Directory /workspace/39.usbdev_rx_full/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1011193789
Short name T1788
Test name
Test status
Simulation time 153366270 ps
CPU time 0.86 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207528 kb
Host smart-a12f0567-5735-475a-a776-1a31138eb391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10111
93789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1011193789
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2073345235
Short name T2156
Test name
Test status
Simulation time 150611635 ps
CPU time 0.86 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:09:46 PM PDT 24
Peak memory 207684 kb
Host smart-ca014869-dc8f-4d25-999b-cad6b2493e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20733
45235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2073345235
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2597347207
Short name T2357
Test name
Test status
Simulation time 225408393 ps
CPU time 1.12 seconds
Started Aug 17 06:09:37 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 207448 kb
Host smart-2491231a-4429-4805-a8ca-b90307de975e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25973
47207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2597347207
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3486455057
Short name T2279
Test name
Test status
Simulation time 2033406739 ps
CPU time 60.61 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 215808 kb
Host smart-073001ff-8b22-41c0-bab6-04823d1166cf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3486455057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3486455057
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3079398188
Short name T2289
Test name
Test status
Simulation time 149178030 ps
CPU time 0.85 seconds
Started Aug 17 06:09:34 PM PDT 24
Finished Aug 17 06:09:35 PM PDT 24
Peak memory 207416 kb
Host smart-6c755802-b354-4dcf-9655-258cd0366b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30793
98188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3079398188
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.4233691308
Short name T2882
Test name
Test status
Simulation time 177283720 ps
CPU time 0.88 seconds
Started Aug 17 06:09:34 PM PDT 24
Finished Aug 17 06:09:35 PM PDT 24
Peak memory 207536 kb
Host smart-8f5ae47d-2831-4f87-b669-36b9d6acfd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42336
91308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.4233691308
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.2113114283
Short name T1651
Test name
Test status
Simulation time 768490036 ps
CPU time 2.15 seconds
Started Aug 17 06:09:34 PM PDT 24
Finished Aug 17 06:09:36 PM PDT 24
Peak memory 207520 kb
Host smart-a21eb68f-9fad-4ce3-9d3a-a1a9e02aa69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21131
14283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.2113114283
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2766080712
Short name T733
Test name
Test status
Simulation time 2038366127 ps
CPU time 55.88 seconds
Started Aug 17 06:09:41 PM PDT 24
Finished Aug 17 06:10:37 PM PDT 24
Peak memory 215960 kb
Host smart-0b276938-c4e2-46a3-8c61-5f3b1519feb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27660
80712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2766080712
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.2451600378
Short name T1582
Test name
Test status
Simulation time 4332985151 ps
CPU time 38.82 seconds
Started Aug 17 06:09:31 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207724 kb
Host smart-d9ad8105-46c1-4fa5-bc3b-de972c8851d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451600378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.2451600378
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_tx_rx_disruption.395417184
Short name T2981
Test name
Test status
Simulation time 672207002 ps
CPU time 1.79 seconds
Started Aug 17 06:09:41 PM PDT 24
Finished Aug 17 06:09:42 PM PDT 24
Peak memory 207552 kb
Host smart-ce7b95eb-4381-437d-80af-b4df020a16da
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395417184 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.usbdev_tx_rx_disruption.395417184
Directory /workspace/39.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/390.usbdev_tx_rx_disruption.3670695920
Short name T636
Test name
Test status
Simulation time 545038970 ps
CPU time 1.8 seconds
Started Aug 17 06:12:24 PM PDT 24
Finished Aug 17 06:12:26 PM PDT 24
Peak memory 207596 kb
Host smart-60f20ee6-4148-409a-b628-134f38ddd437
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670695920 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 390.usbdev_tx_rx_disruption.3670695920
Directory /workspace/390.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/391.usbdev_tx_rx_disruption.420633758
Short name T1800
Test name
Test status
Simulation time 510177253 ps
CPU time 1.67 seconds
Started Aug 17 06:12:31 PM PDT 24
Finished Aug 17 06:12:33 PM PDT 24
Peak memory 207560 kb
Host smart-41fd6d68-d8c1-446a-b74f-3029eb8bea22
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420633758 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 391.usbdev_tx_rx_disruption.420633758
Directory /workspace/391.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/392.usbdev_tx_rx_disruption.3876562139
Short name T3439
Test name
Test status
Simulation time 495808872 ps
CPU time 1.6 seconds
Started Aug 17 06:12:29 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207576 kb
Host smart-74ccb74c-b844-4c81-a882-11ea80de24e7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876562139 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 392.usbdev_tx_rx_disruption.3876562139
Directory /workspace/392.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/393.usbdev_tx_rx_disruption.3937928071
Short name T1945
Test name
Test status
Simulation time 562966558 ps
CPU time 1.62 seconds
Started Aug 17 06:12:18 PM PDT 24
Finished Aug 17 06:12:19 PM PDT 24
Peak memory 207548 kb
Host smart-ca79b1eb-ba42-4847-99a2-54894ccb04a6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937928071 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 393.usbdev_tx_rx_disruption.3937928071
Directory /workspace/393.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/394.usbdev_tx_rx_disruption.3642649345
Short name T189
Test name
Test status
Simulation time 635294207 ps
CPU time 1.71 seconds
Started Aug 17 06:12:12 PM PDT 24
Finished Aug 17 06:12:13 PM PDT 24
Peak memory 207568 kb
Host smart-f7fa3619-e300-4094-8966-bccbea58fcd3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642649345 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 394.usbdev_tx_rx_disruption.3642649345
Directory /workspace/394.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/395.usbdev_tx_rx_disruption.3606633144
Short name T2946
Test name
Test status
Simulation time 527424690 ps
CPU time 1.62 seconds
Started Aug 17 06:12:16 PM PDT 24
Finished Aug 17 06:12:18 PM PDT 24
Peak memory 207516 kb
Host smart-90da8478-b692-4a1a-a9d8-9bcc55aea201
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606633144 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 395.usbdev_tx_rx_disruption.3606633144
Directory /workspace/395.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/396.usbdev_tx_rx_disruption.3614053320
Short name T1543
Test name
Test status
Simulation time 410316393 ps
CPU time 1.45 seconds
Started Aug 17 06:12:29 PM PDT 24
Finished Aug 17 06:12:30 PM PDT 24
Peak memory 207544 kb
Host smart-510c2045-5bff-4bef-86bb-43c07eae193d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614053320 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 396.usbdev_tx_rx_disruption.3614053320
Directory /workspace/396.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/397.usbdev_tx_rx_disruption.1936973422
Short name T1349
Test name
Test status
Simulation time 589550267 ps
CPU time 1.57 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207560 kb
Host smart-440510f0-e144-445d-8be4-8191fe93f01b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936973422 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 397.usbdev_tx_rx_disruption.1936973422
Directory /workspace/397.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/398.usbdev_tx_rx_disruption.2296657397
Short name T887
Test name
Test status
Simulation time 493692689 ps
CPU time 1.55 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:15 PM PDT 24
Peak memory 207572 kb
Host smart-e96ec9fd-a81a-45cf-b116-db01d695c94c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296657397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 398.usbdev_tx_rx_disruption.2296657397
Directory /workspace/398.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/399.usbdev_tx_rx_disruption.3686652755
Short name T2826
Test name
Test status
Simulation time 592229678 ps
CPU time 1.7 seconds
Started Aug 17 06:12:26 PM PDT 24
Finished Aug 17 06:12:27 PM PDT 24
Peak memory 207540 kb
Host smart-2ed2150e-892d-47f6-87cd-b1cd3f129f77
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686652755 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 399.usbdev_tx_rx_disruption.3686652755
Directory /workspace/399.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1310043223
Short name T829
Test name
Test status
Simulation time 33486779 ps
CPU time 0.66 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:37 PM PDT 24
Peak memory 207396 kb
Host smart-d7ead13d-11b3-4d39-b45d-8d326a25071a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1310043223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1310043223
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2202564944
Short name T2598
Test name
Test status
Simulation time 11890122449 ps
CPU time 16.43 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207736 kb
Host smart-30128e59-4835-4fa1-a2aa-3c5de650cddc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202564944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.2202564944
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.601570515
Short name T2515
Test name
Test status
Simulation time 20672832036 ps
CPU time 24.06 seconds
Started Aug 17 06:03:23 PM PDT 24
Finished Aug 17 06:03:47 PM PDT 24
Peak memory 207800 kb
Host smart-74f945f3-22f8-463e-808e-a5200a0e68eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=601570515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.601570515
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.675788355
Short name T13
Test name
Test status
Simulation time 28758731399 ps
CPU time 40.76 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:04:02 PM PDT 24
Peak memory 207736 kb
Host smart-57e31471-a68c-4177-968a-40197d3d4993
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675788355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon
_wake_resume.675788355
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2414326189
Short name T3332
Test name
Test status
Simulation time 154369628 ps
CPU time 0.9 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:03:22 PM PDT 24
Peak memory 207460 kb
Host smart-1b434528-006a-4507-b3e1-b59479309aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24143
26189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2414326189
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.388520410
Short name T53
Test name
Test status
Simulation time 152738593 ps
CPU time 0.91 seconds
Started Aug 17 06:03:26 PM PDT 24
Finished Aug 17 06:03:27 PM PDT 24
Peak memory 207460 kb
Host smart-b2aa1cda-02a9-45f0-8ba9-e18d6e2eed32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38852
0410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.388520410
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2909613563
Short name T56
Test name
Test status
Simulation time 208310758 ps
CPU time 0.94 seconds
Started Aug 17 06:03:24 PM PDT 24
Finished Aug 17 06:03:25 PM PDT 24
Peak memory 207452 kb
Host smart-bd8426f1-c238-436e-acf7-ed1575d2c329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096
13563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2909613563
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3003332544
Short name T1577
Test name
Test status
Simulation time 154030066 ps
CPU time 0.86 seconds
Started Aug 17 06:03:19 PM PDT 24
Finished Aug 17 06:03:20 PM PDT 24
Peak memory 207548 kb
Host smart-553fc838-28e1-4731-80cd-551669b05bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30033
32544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3003332544
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1228831006
Short name T1947
Test name
Test status
Simulation time 184234632 ps
CPU time 0.98 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 207552 kb
Host smart-33d2a7e2-cfbe-4b34-826f-3612b1592029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12288
31006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1228831006
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.313962171
Short name T342
Test name
Test status
Simulation time 1343681054 ps
CPU time 3.59 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:03:26 PM PDT 24
Peak memory 207692 kb
Host smart-bca5d39b-c17c-4a12-b4e6-efc1a1d53129
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=313962171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.313962171
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2520221786
Short name T1574
Test name
Test status
Simulation time 38366776281 ps
CPU time 57.48 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:04:19 PM PDT 24
Peak memory 207824 kb
Host smart-633f6fb3-1047-48f3-970b-3aaf185547f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25202
21786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2520221786
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.4054953831
Short name T3122
Test name
Test status
Simulation time 584241094 ps
CPU time 11.87 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:03:34 PM PDT 24
Peak memory 207732 kb
Host smart-7f61c988-325c-4b06-bfd3-6a6bcb785fa0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054953831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.4054953831
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.797632800
Short name T2447
Test name
Test status
Simulation time 813781996 ps
CPU time 2.17 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 207532 kb
Host smart-79d5537b-3776-44ca-bc8c-efe2334e92fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79763
2800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.797632800
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1266507426
Short name T1573
Test name
Test status
Simulation time 150925786 ps
CPU time 0.86 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:03:22 PM PDT 24
Peak memory 207580 kb
Host smart-6dd4cdfc-285e-4404-8175-a77800ec73a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12665
07426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1266507426
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2225294080
Short name T1837
Test name
Test status
Simulation time 42780438 ps
CPU time 0.76 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 207424 kb
Host smart-cc2eec00-f008-47b9-9c03-33dae7072ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22252
94080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2225294080
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3474273988
Short name T3383
Test name
Test status
Simulation time 885999388 ps
CPU time 2.37 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:03:24 PM PDT 24
Peak memory 207752 kb
Host smart-254aaee9-cd1e-4db9-bcd8-a5ab307065af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34742
73988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3474273988
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_types.3917822876
Short name T1819
Test name
Test status
Simulation time 199710321 ps
CPU time 1 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 207524 kb
Host smart-00d8eaf9-b3ad-4c81-a91d-a6d70c53ae87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3917822876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.3917822876
Directory /workspace/4.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1070179153
Short name T1885
Test name
Test status
Simulation time 315501133 ps
CPU time 2.59 seconds
Started Aug 17 06:03:27 PM PDT 24
Finished Aug 17 06:03:29 PM PDT 24
Peak memory 207624 kb
Host smart-a77dcdad-dc88-493d-859d-87442c5b4ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701
79153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1070179153
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.3990892787
Short name T348
Test name
Test status
Simulation time 99187334529 ps
CPU time 178.82 seconds
Started Aug 17 06:03:26 PM PDT 24
Finished Aug 17 06:06:25 PM PDT 24
Peak memory 207680 kb
Host smart-0b7cbd2a-bf00-41f9-a2d0-6aec846a91c5
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3990892787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.3990892787
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.719035694
Short name T1070
Test name
Test status
Simulation time 83192528247 ps
CPU time 125.97 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:05:28 PM PDT 24
Peak memory 207788 kb
Host smart-5de9c0b3-d70d-41c0-9215-bd1315a63a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719035694 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.719035694
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.107530500
Short name T3619
Test name
Test status
Simulation time 111124910568 ps
CPU time 189.92 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:06:32 PM PDT 24
Peak memory 207748 kb
Host smart-75427b75-6bd3-4fd7-8210-509406cb4fc3
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=107530500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.107530500
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1529072785
Short name T1713
Test name
Test status
Simulation time 81242151348 ps
CPU time 133.46 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:05:35 PM PDT 24
Peak memory 207784 kb
Host smart-2b9c1f74-6d14-4bd1-9075-627470fedb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529072785 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1529072785
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.2601638835
Short name T799
Test name
Test status
Simulation time 105172400480 ps
CPU time 156.18 seconds
Started Aug 17 06:03:23 PM PDT 24
Finished Aug 17 06:05:59 PM PDT 24
Peak memory 207748 kb
Host smart-b6ab6b95-e24a-442e-adb7-c9a6a14f36f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26016
38835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.2601638835
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1130927832
Short name T1724
Test name
Test status
Simulation time 183522442 ps
CPU time 1.04 seconds
Started Aug 17 06:03:22 PM PDT 24
Finished Aug 17 06:03:23 PM PDT 24
Peak memory 215916 kb
Host smart-6a0f2820-72d7-4fc1-845b-c79fa5830b6e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1130927832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1130927832
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2170932449
Short name T2465
Test name
Test status
Simulation time 167175317 ps
CPU time 0.88 seconds
Started Aug 17 06:03:23 PM PDT 24
Finished Aug 17 06:03:24 PM PDT 24
Peak memory 207396 kb
Host smart-b019b6fe-d255-4712-9de3-43b7fc0a19e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21709
32449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2170932449
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1331458544
Short name T658
Test name
Test status
Simulation time 239868651 ps
CPU time 1.11 seconds
Started Aug 17 06:03:21 PM PDT 24
Finished Aug 17 06:03:22 PM PDT 24
Peak memory 207516 kb
Host smart-4716b0b5-d647-42df-b6ea-63315722c817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13314
58544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1331458544
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.4210740777
Short name T3167
Test name
Test status
Simulation time 3647023679 ps
CPU time 29.48 seconds
Started Aug 17 06:03:23 PM PDT 24
Finished Aug 17 06:03:53 PM PDT 24
Peak memory 217108 kb
Host smart-1a676429-ecce-4616-b9e9-b0555f52ea8f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4210740777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.4210740777
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.3293042777
Short name T3252
Test name
Test status
Simulation time 11117900458 ps
CPU time 77.57 seconds
Started Aug 17 06:03:24 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 207728 kb
Host smart-fe734c2e-3eaf-4fcf-9158-6e352da11f32
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3293042777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.3293042777
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3060916180
Short name T270
Test name
Test status
Simulation time 250222619 ps
CPU time 1.02 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:38 PM PDT 24
Peak memory 207428 kb
Host smart-c1ed8354-f88b-431a-ac20-bc9917556986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
16180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3060916180
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3533519515
Short name T2396
Test name
Test status
Simulation time 23892950823 ps
CPU time 45.66 seconds
Started Aug 17 06:03:36 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207704 kb
Host smart-7f0ac36e-de64-4c34-93d1-aeee7a4646c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35335
19515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3533519515
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.780260659
Short name T1118
Test name
Test status
Simulation time 4765766554 ps
CPU time 7.77 seconds
Started Aug 17 06:03:36 PM PDT 24
Finished Aug 17 06:03:43 PM PDT 24
Peak memory 207756 kb
Host smart-17800d5b-3ce4-477a-b4ec-7f3acb746fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78026
0659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.780260659
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.2621732320
Short name T1977
Test name
Test status
Simulation time 5380900437 ps
CPU time 163.56 seconds
Started Aug 17 06:03:39 PM PDT 24
Finished Aug 17 06:06:22 PM PDT 24
Peak memory 218452 kb
Host smart-5678b180-914d-43b6-aebf-c699495600b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2621732320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.2621732320
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.196445718
Short name T1277
Test name
Test status
Simulation time 4262717108 ps
CPU time 32.08 seconds
Started Aug 17 06:03:32 PM PDT 24
Finished Aug 17 06:04:04 PM PDT 24
Peak memory 217636 kb
Host smart-c16c1901-f2b4-4f05-8fca-56cfc0bb9990
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=196445718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.196445718
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3908869074
Short name T2335
Test name
Test status
Simulation time 234208375 ps
CPU time 1.04 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207476 kb
Host smart-5a2c8b3b-cee9-4a11-96c6-7483c68d303b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3908869074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3908869074
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3644682605
Short name T3327
Test name
Test status
Simulation time 250516982 ps
CPU time 0.99 seconds
Started Aug 17 06:03:34 PM PDT 24
Finished Aug 17 06:03:36 PM PDT 24
Peak memory 207464 kb
Host smart-2a87859d-2558-43a3-9421-5f8d3bef32fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
82605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3644682605
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.646617311
Short name T841
Test name
Test status
Simulation time 2457445779 ps
CPU time 73.51 seconds
Started Aug 17 06:03:33 PM PDT 24
Finished Aug 17 06:04:47 PM PDT 24
Peak memory 223984 kb
Host smart-1bc818c8-1d29-45b7-a404-7ceafb74f8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64661
7311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.646617311
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3033976797
Short name T2065
Test name
Test status
Simulation time 2810980299 ps
CPU time 84.94 seconds
Started Aug 17 06:03:35 PM PDT 24
Finished Aug 17 06:05:00 PM PDT 24
Peak memory 218048 kb
Host smart-5a636af6-cdb2-412f-a0d1-f58a38e0fd00
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3033976797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3033976797
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3509473116
Short name T1040
Test name
Test status
Simulation time 2445301907 ps
CPU time 18.91 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 207708 kb
Host smart-7c329fb8-d09e-463b-82d1-226ea7e3d670
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3509473116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3509473116
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2193514442
Short name T1482
Test name
Test status
Simulation time 183683786 ps
CPU time 0.9 seconds
Started Aug 17 06:03:34 PM PDT 24
Finished Aug 17 06:03:35 PM PDT 24
Peak memory 207444 kb
Host smart-d3929b22-89bc-40c1-a5bc-7dff908f58c7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2193514442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2193514442
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.780745200
Short name T2227
Test name
Test status
Simulation time 139878285 ps
CPU time 0.84 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:38 PM PDT 24
Peak memory 207400 kb
Host smart-5ec7cdb0-c83b-4216-b110-315b568af887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78074
5200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.780745200
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3088987389
Short name T143
Test name
Test status
Simulation time 181550440 ps
CPU time 0.93 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207456 kb
Host smart-403bc357-2961-4412-bc48-32234f9f28af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30889
87389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3088987389
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3560224522
Short name T3384
Test name
Test status
Simulation time 163071940 ps
CPU time 0.9 seconds
Started Aug 17 06:03:34 PM PDT 24
Finished Aug 17 06:03:36 PM PDT 24
Peak memory 207428 kb
Host smart-6f252924-145e-418e-ba79-2a90a0c3e38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35602
24522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3560224522
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2948663305
Short name T3474
Test name
Test status
Simulation time 173797691 ps
CPU time 0.89 seconds
Started Aug 17 06:03:36 PM PDT 24
Finished Aug 17 06:03:37 PM PDT 24
Peak memory 207420 kb
Host smart-78e16e04-19b0-41e7-9871-54e28558d179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29486
63305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2948663305
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3264665357
Short name T805
Test name
Test status
Simulation time 195030182 ps
CPU time 1.03 seconds
Started Aug 17 06:03:33 PM PDT 24
Finished Aug 17 06:03:34 PM PDT 24
Peak memory 207560 kb
Host smart-dba52c6e-7014-43e7-8019-b23d47c98387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32646
65357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3264665357
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2434318747
Short name T1485
Test name
Test status
Simulation time 161534067 ps
CPU time 0.85 seconds
Started Aug 17 06:03:34 PM PDT 24
Finished Aug 17 06:03:35 PM PDT 24
Peak memory 207564 kb
Host smart-33ad1f74-a0ec-4799-8951-b9ef51824463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24343
18747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2434318747
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3059050118
Short name T2539
Test name
Test status
Simulation time 253549846 ps
CPU time 1.08 seconds
Started Aug 17 06:03:36 PM PDT 24
Finished Aug 17 06:03:37 PM PDT 24
Peak memory 207532 kb
Host smart-b74e5583-cc89-459b-a767-c9bdc227d6a2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3059050118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3059050118
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.4135867320
Short name T3630
Test name
Test status
Simulation time 246457060 ps
CPU time 1.02 seconds
Started Aug 17 06:03:36 PM PDT 24
Finished Aug 17 06:03:37 PM PDT 24
Peak memory 207464 kb
Host smart-09e4e0aa-3665-4b95-8e16-ff4c6f505395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41358
67320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.4135867320
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.192318403
Short name T1900
Test name
Test status
Simulation time 171948941 ps
CPU time 0.91 seconds
Started Aug 17 06:03:35 PM PDT 24
Finished Aug 17 06:03:36 PM PDT 24
Peak memory 207424 kb
Host smart-6aaac215-88d1-4ea4-bc19-3e99bd5128c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19231
8403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.192318403
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.612597020
Short name T2111
Test name
Test status
Simulation time 46820203 ps
CPU time 0.73 seconds
Started Aug 17 06:03:35 PM PDT 24
Finished Aug 17 06:03:36 PM PDT 24
Peak memory 207512 kb
Host smart-978688ab-d453-4770-9168-de3aae991ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61259
7020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.612597020
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1927356718
Short name T271
Test name
Test status
Simulation time 10382339036 ps
CPU time 27.72 seconds
Started Aug 17 06:03:35 PM PDT 24
Finished Aug 17 06:04:03 PM PDT 24
Peak memory 215952 kb
Host smart-aa6b7e54-c822-474f-9741-d2b1232ad799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19273
56718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1927356718
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2498594113
Short name T836
Test name
Test status
Simulation time 182133932 ps
CPU time 0.93 seconds
Started Aug 17 06:03:33 PM PDT 24
Finished Aug 17 06:03:34 PM PDT 24
Peak memory 207544 kb
Host smart-be995d94-4f17-408b-b1db-8dcc798e53b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24985
94113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2498594113
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2853492341
Short name T981
Test name
Test status
Simulation time 155892071 ps
CPU time 0.89 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:38 PM PDT 24
Peak memory 207416 kb
Host smart-cf7e19a4-2b4e-44c9-b931-eedc7a17de97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28534
92341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2853492341
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.2395025964
Short name T355
Test name
Test status
Simulation time 7114278201 ps
CPU time 99.27 seconds
Started Aug 17 06:03:35 PM PDT 24
Finished Aug 17 06:05:15 PM PDT 24
Peak memory 219196 kb
Host smart-fae0ff04-93a5-49ce-b4cf-4520c55ac006
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395025964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.2395025964
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3283254905
Short name T2271
Test name
Test status
Simulation time 7400644883 ps
CPU time 49.65 seconds
Started Aug 17 06:03:35 PM PDT 24
Finished Aug 17 06:04:24 PM PDT 24
Peak memory 218508 kb
Host smart-0270162e-66b4-45e2-9366-761888c13b81
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3283254905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3283254905
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2267930177
Short name T2888
Test name
Test status
Simulation time 10619669562 ps
CPU time 218.1 seconds
Started Aug 17 06:03:35 PM PDT 24
Finished Aug 17 06:07:13 PM PDT 24
Peak memory 224120 kb
Host smart-41478fe3-67fc-4d96-8607-7cb26fcdb667
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267930177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2267930177
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.2083605337
Short name T1154
Test name
Test status
Simulation time 209870393 ps
CPU time 1.01 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207468 kb
Host smart-633980f9-4eb4-448b-b7af-ce14a911fce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20836
05337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2083605337
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3245192061
Short name T1706
Test name
Test status
Simulation time 189029023 ps
CPU time 0.93 seconds
Started Aug 17 06:03:36 PM PDT 24
Finished Aug 17 06:03:37 PM PDT 24
Peak memory 207476 kb
Host smart-7126ef3a-0a4b-48ac-8288-c18ec40c9155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32451
92061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3245192061
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_resume_link_active.981014079
Short name T1927
Test name
Test status
Simulation time 20216429064 ps
CPU time 25.18 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:04:02 PM PDT 24
Peak memory 207584 kb
Host smart-84d78523-573c-4c84-b8c3-3d51070df09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98101
4079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.981014079
Directory /workspace/4.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3296746999
Short name T826
Test name
Test status
Simulation time 213483346 ps
CPU time 0.89 seconds
Started Aug 17 06:03:34 PM PDT 24
Finished Aug 17 06:03:35 PM PDT 24
Peak memory 207424 kb
Host smart-8fddad36-c65a-44ce-8d98-95c1c2981926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32967
46999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3296746999
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_full.3530173823
Short name T1217
Test name
Test status
Simulation time 353672023 ps
CPU time 1.19 seconds
Started Aug 17 06:03:32 PM PDT 24
Finished Aug 17 06:03:33 PM PDT 24
Peak memory 207368 kb
Host smart-1cec7e2d-9703-4a6f-afb6-23a696bdc40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35301
73823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.3530173823
Directory /workspace/4.usbdev_rx_full/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1096983326
Short name T78
Test name
Test status
Simulation time 148721501 ps
CPU time 0.85 seconds
Started Aug 17 06:03:34 PM PDT 24
Finished Aug 17 06:03:35 PM PDT 24
Peak memory 207488 kb
Host smart-3e5faa5f-1a12-47b1-bbd7-799f3c4424f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10969
83326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1096983326
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.4290647626
Short name T3545
Test name
Test status
Simulation time 382286107 ps
CPU time 1.48 seconds
Started Aug 17 06:03:36 PM PDT 24
Finished Aug 17 06:03:38 PM PDT 24
Peak memory 207504 kb
Host smart-eb68f85e-d6e4-4ec4-813f-9f63b69f3b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42906
47626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.4290647626
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3003966449
Short name T3181
Test name
Test status
Simulation time 193465901 ps
CPU time 0.95 seconds
Started Aug 17 06:03:34 PM PDT 24
Finished Aug 17 06:03:35 PM PDT 24
Peak memory 207432 kb
Host smart-0ddb1f9c-40d0-4fef-8791-0f291c0478e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30039
66449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3003966449
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1992975337
Short name T2237
Test name
Test status
Simulation time 199379439 ps
CPU time 0.97 seconds
Started Aug 17 06:03:39 PM PDT 24
Finished Aug 17 06:03:40 PM PDT 24
Peak memory 207428 kb
Host smart-2ad8825d-41fb-4748-8d25-82e5ae3af635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
75337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1992975337
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.529449605
Short name T2751
Test name
Test status
Simulation time 232122695 ps
CPU time 0.98 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:38 PM PDT 24
Peak memory 207548 kb
Host smart-e67197d2-f0d5-4682-9af1-866c16ddae54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52944
9605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.529449605
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.4068140079
Short name T1348
Test name
Test status
Simulation time 316882599 ps
CPU time 1.12 seconds
Started Aug 17 06:03:36 PM PDT 24
Finished Aug 17 06:03:38 PM PDT 24
Peak memory 207416 kb
Host smart-30d7222b-c149-4c5a-9cfd-6da0ef39704d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40681
40079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.4068140079
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1489191090
Short name T2224
Test name
Test status
Simulation time 2908616213 ps
CPU time 22.49 seconds
Started Aug 17 06:03:39 PM PDT 24
Finished Aug 17 06:04:02 PM PDT 24
Peak memory 217632 kb
Host smart-dc8727f8-bf97-4d40-af59-bc27c353fed8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1489191090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1489191090
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2490527088
Short name T2484
Test name
Test status
Simulation time 192551588 ps
CPU time 0.89 seconds
Started Aug 17 06:03:35 PM PDT 24
Finished Aug 17 06:03:36 PM PDT 24
Peak memory 207496 kb
Host smart-a57a9cbe-c314-402e-aedf-bdf82c9620d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24905
27088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2490527088
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.790718826
Short name T2494
Test name
Test status
Simulation time 217753730 ps
CPU time 0.97 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207460 kb
Host smart-bf3a111e-34eb-4f8d-a9a7-1301ed9f68f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79071
8826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.790718826
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.1931635210
Short name T1152
Test name
Test status
Simulation time 337610761 ps
CPU time 1.33 seconds
Started Aug 17 06:03:42 PM PDT 24
Finished Aug 17 06:03:43 PM PDT 24
Peak memory 207504 kb
Host smart-d029aa84-181a-4477-87f9-5cc039d334b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19316
35210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.1931635210
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3312261710
Short name T552
Test name
Test status
Simulation time 2617071560 ps
CPU time 20.6 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:03:58 PM PDT 24
Peak memory 217724 kb
Host smart-2e4acb4e-f2d7-434d-867a-60b7a8696b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33122
61710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3312261710
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.2155150358
Short name T2509
Test name
Test status
Simulation time 3589402895 ps
CPU time 25.37 seconds
Started Aug 17 06:03:20 PM PDT 24
Finished Aug 17 06:03:45 PM PDT 24
Peak memory 207680 kb
Host smart-e17d18f5-211d-4428-9172-ecc9e27bc366
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155150358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.2155150358
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_tx_rx_disruption.4038187529
Short name T706
Test name
Test status
Simulation time 504536701 ps
CPU time 1.61 seconds
Started Aug 17 06:03:40 PM PDT 24
Finished Aug 17 06:03:42 PM PDT 24
Peak memory 207580 kb
Host smart-79b7fd20-441f-486c-b2c8-63c41c301451
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038187529 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.usbdev_tx_rx_disruption.4038187529
Directory /workspace/4.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.4159708431
Short name T1710
Test name
Test status
Simulation time 72602103 ps
CPU time 0.69 seconds
Started Aug 17 06:09:49 PM PDT 24
Finished Aug 17 06:09:50 PM PDT 24
Peak memory 207396 kb
Host smart-22ac4c4f-44e2-4874-8e93-45a6eb54420b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4159708431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.4159708431
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1063660974
Short name T232
Test name
Test status
Simulation time 4742716045 ps
CPU time 8.14 seconds
Started Aug 17 06:09:48 PM PDT 24
Finished Aug 17 06:09:56 PM PDT 24
Peak memory 215980 kb
Host smart-6ef4e30a-844f-4233-95ff-b7f2733b753e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063660974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.1063660974
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2061823442
Short name T2390
Test name
Test status
Simulation time 20652207514 ps
CPU time 29.54 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:10:16 PM PDT 24
Peak memory 207828 kb
Host smart-68b2def5-e59f-4011-a0a3-4196de477737
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061823442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2061823442
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3233095450
Short name T2310
Test name
Test status
Simulation time 25158428481 ps
CPU time 29.63 seconds
Started Aug 17 06:09:44 PM PDT 24
Finished Aug 17 06:10:14 PM PDT 24
Peak memory 215980 kb
Host smart-acd72c74-03d8-48b7-904d-941bc8376a45
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233095450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.3233095450
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.103604720
Short name T3148
Test name
Test status
Simulation time 236988286 ps
CPU time 0.99 seconds
Started Aug 17 06:09:41 PM PDT 24
Finished Aug 17 06:09:42 PM PDT 24
Peak memory 206412 kb
Host smart-bf130bdd-20bd-46f5-b0cb-d708b9f9cdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10360
4720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.103604720
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.327072633
Short name T2630
Test name
Test status
Simulation time 171577200 ps
CPU time 0.89 seconds
Started Aug 17 06:09:38 PM PDT 24
Finished Aug 17 06:09:39 PM PDT 24
Peak memory 207552 kb
Host smart-78bd4602-47c6-4856-96c3-80b04f4058dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32707
2633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.327072633
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2436112569
Short name T3047
Test name
Test status
Simulation time 347914139 ps
CPU time 1.35 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:09:51 PM PDT 24
Peak memory 207784 kb
Host smart-53b85e70-114e-4ecb-abd6-432cb85c4cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24361
12569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2436112569
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.4112194613
Short name T3034
Test name
Test status
Simulation time 1006962701 ps
CPU time 2.62 seconds
Started Aug 17 06:09:48 PM PDT 24
Finished Aug 17 06:09:51 PM PDT 24
Peak memory 207756 kb
Host smart-f71b2074-381b-451c-987b-2e23455f367a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4112194613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.4112194613
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.216021349
Short name T376
Test name
Test status
Simulation time 39974454370 ps
CPU time 64.47 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:10:50 PM PDT 24
Peak memory 207992 kb
Host smart-d6b184d5-7b52-4255-9af5-01d9e256bcef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21602
1349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.216021349
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.4128137946
Short name T2718
Test name
Test status
Simulation time 1824170103 ps
CPU time 44.26 seconds
Started Aug 17 06:09:51 PM PDT 24
Finished Aug 17 06:10:35 PM PDT 24
Peak memory 207668 kb
Host smart-da05bc43-0e65-4574-806b-20b49381b04f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128137946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.4128137946
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3034240455
Short name T1959
Test name
Test status
Simulation time 777661535 ps
CPU time 1.94 seconds
Started Aug 17 06:09:44 PM PDT 24
Finished Aug 17 06:09:46 PM PDT 24
Peak memory 207452 kb
Host smart-721f1e74-8fa5-4c2b-ab85-ea3155b3ee46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30342
40455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3034240455
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1258180804
Short name T621
Test name
Test status
Simulation time 204402238 ps
CPU time 0.89 seconds
Started Aug 17 06:09:37 PM PDT 24
Finished Aug 17 06:09:38 PM PDT 24
Peak memory 207536 kb
Host smart-148a3643-150a-4344-899f-ee28ba7e86ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12581
80804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1258180804
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1526781043
Short name T1042
Test name
Test status
Simulation time 36448319 ps
CPU time 0.69 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207424 kb
Host smart-fa231a93-099a-4d13-a912-94cadb35c03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15267
81043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1526781043
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2639364169
Short name T3481
Test name
Test status
Simulation time 923359768 ps
CPU time 2.46 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:09:48 PM PDT 24
Peak memory 207756 kb
Host smart-a80d5153-6fb4-4765-9f90-6c208f600817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26393
64169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2639364169
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_types.1991327168
Short name T1755
Test name
Test status
Simulation time 209755263 ps
CPU time 0.93 seconds
Started Aug 17 06:09:36 PM PDT 24
Finished Aug 17 06:09:37 PM PDT 24
Peak memory 207496 kb
Host smart-9f04fbfa-9f0b-4fbf-9153-88358e67fd11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1991327168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.1991327168
Directory /workspace/40.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.401688816
Short name T1964
Test name
Test status
Simulation time 224940228 ps
CPU time 1.94 seconds
Started Aug 17 06:09:38 PM PDT 24
Finished Aug 17 06:09:40 PM PDT 24
Peak memory 207588 kb
Host smart-2c5ee152-07a7-48b6-a1e6-025d3ef99c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40168
8816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.401688816
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.749739714
Short name T3479
Test name
Test status
Simulation time 197497176 ps
CPU time 1.1 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:09:46 PM PDT 24
Peak memory 215812 kb
Host smart-96481646-2e60-4e5b-952a-05105a5bcd65
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=749739714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.749739714
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.157389444
Short name T681
Test name
Test status
Simulation time 170162773 ps
CPU time 0.88 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:09:46 PM PDT 24
Peak memory 207440 kb
Host smart-f2c24b3b-d3e9-47b2-a21a-d8f54d61b639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15738
9444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.157389444
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3295827569
Short name T3030
Test name
Test status
Simulation time 216503286 ps
CPU time 0.97 seconds
Started Aug 17 06:09:40 PM PDT 24
Finished Aug 17 06:09:41 PM PDT 24
Peak memory 207456 kb
Host smart-cbf5883e-c371-4f43-93d3-e04230c8b711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958
27569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3295827569
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.1892600413
Short name T1804
Test name
Test status
Simulation time 3014660651 ps
CPU time 88.77 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:11:19 PM PDT 24
Peak memory 218476 kb
Host smart-80d3bd7f-01c3-4e4e-ad60-f01071c0ce6b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1892600413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.1892600413
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.1689962363
Short name T2778
Test name
Test status
Simulation time 7540799050 ps
CPU time 87.95 seconds
Started Aug 17 06:09:49 PM PDT 24
Finished Aug 17 06:11:17 PM PDT 24
Peak memory 207712 kb
Host smart-a8cc00d8-d03b-4285-a2ea-2d833e6cde2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1689962363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.1689962363
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.3662454355
Short name T1363
Test name
Test status
Simulation time 208126095 ps
CPU time 0.97 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:09:46 PM PDT 24
Peak memory 207760 kb
Host smart-44b0da9b-430c-4f44-b596-a769422195c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36624
54355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.3662454355
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1660131869
Short name T2972
Test name
Test status
Simulation time 5393986696 ps
CPU time 7.15 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:06 PM PDT 24
Peak memory 215916 kb
Host smart-7a75462d-405e-4164-ab6f-e0d717c17ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16601
31869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1660131869
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.250871938
Short name T2359
Test name
Test status
Simulation time 5599912539 ps
CPU time 8.24 seconds
Started Aug 17 06:09:44 PM PDT 24
Finished Aug 17 06:09:52 PM PDT 24
Peak memory 215924 kb
Host smart-226b4451-9d68-496f-bb9a-1bc28da3527c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25087
1938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.250871938
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1151868317
Short name T2934
Test name
Test status
Simulation time 4383832511 ps
CPU time 35.72 seconds
Started Aug 17 06:09:41 PM PDT 24
Finished Aug 17 06:10:22 PM PDT 24
Peak memory 218464 kb
Host smart-09a13d1b-2e0f-4d5d-bc33-ea2234515979
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1151868317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1151868317
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1624713734
Short name T1712
Test name
Test status
Simulation time 2600608577 ps
CPU time 19.81 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 217528 kb
Host smart-a8c7fd97-f158-4df5-9e64-96ca4f3255de
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1624713734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1624713734
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3152959649
Short name T2578
Test name
Test status
Simulation time 238408182 ps
CPU time 1.01 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:48 PM PDT 24
Peak memory 207480 kb
Host smart-50cc6e56-c06c-4670-b774-b8eebfdbcc1f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3152959649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3152959649
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.4048729250
Short name T2129
Test name
Test status
Simulation time 185720504 ps
CPU time 0.95 seconds
Started Aug 17 06:09:41 PM PDT 24
Finished Aug 17 06:09:42 PM PDT 24
Peak memory 207464 kb
Host smart-ea115c4c-5c23-4919-b121-f95adae75eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40487
29250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.4048729250
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.2385165648
Short name T2936
Test name
Test status
Simulation time 3596173216 ps
CPU time 31.16 seconds
Started Aug 17 06:09:40 PM PDT 24
Finished Aug 17 06:10:11 PM PDT 24
Peak memory 217680 kb
Host smart-c9bb75bd-7dd6-490b-8c85-9c2bad3c45b4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2385165648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.2385165648
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.1219657539
Short name T1238
Test name
Test status
Simulation time 159194772 ps
CPU time 0.9 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207452 kb
Host smart-8146e60c-46ee-4f35-bbaa-3eff3b6d171e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1219657539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.1219657539
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2013433972
Short name T2114
Test name
Test status
Simulation time 147590730 ps
CPU time 0.95 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:09:51 PM PDT 24
Peak memory 207452 kb
Host smart-7a957980-9294-4ae2-9653-f96580315a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20134
33972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2013433972
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3862004531
Short name T165
Test name
Test status
Simulation time 213257850 ps
CPU time 0.99 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:09:51 PM PDT 24
Peak memory 207456 kb
Host smart-263a4caa-b062-4b17-a57c-ae827a76f906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38620
04531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3862004531
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.359126143
Short name T1191
Test name
Test status
Simulation time 186629910 ps
CPU time 0.96 seconds
Started Aug 17 06:09:47 PM PDT 24
Finished Aug 17 06:09:48 PM PDT 24
Peak memory 207472 kb
Host smart-6d857aac-4b6e-4590-8cf6-038fce1934b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912
6143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.359126143
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3942407833
Short name T526
Test name
Test status
Simulation time 193296830 ps
CPU time 0.93 seconds
Started Aug 17 06:09:49 PM PDT 24
Finished Aug 17 06:09:51 PM PDT 24
Peak memory 207368 kb
Host smart-6e4e7456-9db8-42c5-94b0-f3216961d4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39424
07833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3942407833
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2395615554
Short name T877
Test name
Test status
Simulation time 209256827 ps
CPU time 0.92 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:09:51 PM PDT 24
Peak memory 207760 kb
Host smart-a199785c-657c-4895-b75f-6c869c216651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23956
15554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2395615554
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1441038126
Short name T2415
Test name
Test status
Simulation time 158321623 ps
CPU time 0.9 seconds
Started Aug 17 06:09:55 PM PDT 24
Finished Aug 17 06:09:56 PM PDT 24
Peak memory 207544 kb
Host smart-40ea4d6d-5efd-4ab1-89cb-c52c77c22859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14410
38126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1441038126
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.643230104
Short name T87
Test name
Test status
Simulation time 233639437 ps
CPU time 1.04 seconds
Started Aug 17 06:09:55 PM PDT 24
Finished Aug 17 06:09:56 PM PDT 24
Peak memory 207564 kb
Host smart-1275a80c-4e53-4d7b-9e1b-352183394f05
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=643230104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.643230104
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3549801051
Short name T3227
Test name
Test status
Simulation time 149752919 ps
CPU time 0.87 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207420 kb
Host smart-645bd9f9-6259-4bdd-a083-7a3fd2b534cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35498
01051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3549801051
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.960253001
Short name T2171
Test name
Test status
Simulation time 47210127 ps
CPU time 0.71 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207508 kb
Host smart-0c44c39c-56e6-4dc7-8cb2-4f45f34a5f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96025
3001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.960253001
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3036553265
Short name T990
Test name
Test status
Simulation time 6214329321 ps
CPU time 16.32 seconds
Started Aug 17 06:09:48 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 215960 kb
Host smart-78cb35d1-202d-4781-8751-13c2fca92144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30365
53265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3036553265
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.417566762
Short name T3001
Test name
Test status
Simulation time 160229838 ps
CPU time 0.92 seconds
Started Aug 17 06:09:51 PM PDT 24
Finished Aug 17 06:09:53 PM PDT 24
Peak memory 207536 kb
Host smart-d8b4b22e-1eb0-4439-ab28-6c73de9f7685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41756
6762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.417566762
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3451696239
Short name T1003
Test name
Test status
Simulation time 233606534 ps
CPU time 0.98 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207464 kb
Host smart-dd6145f5-9e7c-4216-92a8-4d194cf39751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34516
96239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3451696239
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1184858161
Short name T1450
Test name
Test status
Simulation time 163199453 ps
CPU time 0.89 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:09:46 PM PDT 24
Peak memory 207380 kb
Host smart-0ba874bd-a34e-4a17-9b54-5514a8c0c13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11848
58161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1184858161
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.966775460
Short name T2835
Test name
Test status
Simulation time 150688989 ps
CPU time 0.85 seconds
Started Aug 17 06:09:49 PM PDT 24
Finished Aug 17 06:09:50 PM PDT 24
Peak memory 207460 kb
Host smart-6e8ea452-758c-4147-95f3-fd39e10aa018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96677
5460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.966775460
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3372966075
Short name T743
Test name
Test status
Simulation time 253327423 ps
CPU time 0.94 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207484 kb
Host smart-221f9cff-1022-4495-86f3-517d2fde2882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33729
66075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3372966075
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_rx_full.876694496
Short name T48
Test name
Test status
Simulation time 351830297 ps
CPU time 1.25 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:53 PM PDT 24
Peak memory 207472 kb
Host smart-227f1801-a2aa-4b1c-8fe1-2c335185a6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87669
4496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.876694496
Directory /workspace/40.usbdev_rx_full/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2362990626
Short name T3597
Test name
Test status
Simulation time 177648806 ps
CPU time 0.91 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207508 kb
Host smart-b04673ba-8197-4c48-b6f0-1674384b01d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23629
90626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2362990626
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1211344060
Short name T3600
Test name
Test status
Simulation time 148133239 ps
CPU time 0.88 seconds
Started Aug 17 06:09:54 PM PDT 24
Finished Aug 17 06:09:55 PM PDT 24
Peak memory 207484 kb
Host smart-e1031f36-d4eb-49ae-8c54-626557c743ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12113
44060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1211344060
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1110674965
Short name T773
Test name
Test status
Simulation time 241119320 ps
CPU time 1.13 seconds
Started Aug 17 06:09:48 PM PDT 24
Finished Aug 17 06:09:49 PM PDT 24
Peak memory 207464 kb
Host smart-bf6ea44d-80c8-465b-abca-a91a35e0020c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11106
74965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1110674965
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3992867079
Short name T1425
Test name
Test status
Simulation time 1675191277 ps
CPU time 11.99 seconds
Started Aug 17 06:09:47 PM PDT 24
Finished Aug 17 06:09:59 PM PDT 24
Peak memory 217408 kb
Host smart-3d4d959d-fead-482a-845d-fdd78f652480
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3992867079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3992867079
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1552062217
Short name T1462
Test name
Test status
Simulation time 168750216 ps
CPU time 0.89 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207480 kb
Host smart-bf841731-7f17-43e7-a03b-212487f0f75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15520
62217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1552062217
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.29236757
Short name T1711
Test name
Test status
Simulation time 181722194 ps
CPU time 0.95 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 207400 kb
Host smart-86d74307-8bf3-44e2-b419-a73e0f0b3ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29236
757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.29236757
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.656077966
Short name T1504
Test name
Test status
Simulation time 857345583 ps
CPU time 2.45 seconds
Started Aug 17 06:09:49 PM PDT 24
Finished Aug 17 06:09:52 PM PDT 24
Peak memory 207708 kb
Host smart-d579b483-614f-4bee-abc2-206e170b4ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65607
7966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.656077966
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2831400066
Short name T1073
Test name
Test status
Simulation time 2696382190 ps
CPU time 22.35 seconds
Started Aug 17 06:09:51 PM PDT 24
Finished Aug 17 06:10:19 PM PDT 24
Peak memory 207760 kb
Host smart-6039167f-d915-4d52-bedc-0fe0991549ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28314
00066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2831400066
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.1029953094
Short name T1839
Test name
Test status
Simulation time 779114990 ps
CPU time 16.22 seconds
Started Aug 17 06:09:33 PM PDT 24
Finished Aug 17 06:09:49 PM PDT 24
Peak memory 207672 kb
Host smart-fe75bce2-b0b6-4d9a-ad78-9976d642ef6a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029953094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.1029953094
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_tx_rx_disruption.1718088171
Short name T2901
Test name
Test status
Simulation time 550721871 ps
CPU time 1.6 seconds
Started Aug 17 06:09:41 PM PDT 24
Finished Aug 17 06:09:43 PM PDT 24
Peak memory 207548 kb
Host smart-06fd3550-bd2e-4a9b-898b-9139587549dd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718088171 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.usbdev_tx_rx_disruption.1718088171
Directory /workspace/40.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/400.usbdev_tx_rx_disruption.3176052904
Short name T2556
Test name
Test status
Simulation time 509440827 ps
CPU time 1.62 seconds
Started Aug 17 06:12:16 PM PDT 24
Finished Aug 17 06:12:17 PM PDT 24
Peak memory 206496 kb
Host smart-b62add40-48e2-4968-a742-8a01681ec4fe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176052904 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 400.usbdev_tx_rx_disruption.3176052904
Directory /workspace/400.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/401.usbdev_tx_rx_disruption.1435719095
Short name T1339
Test name
Test status
Simulation time 492307441 ps
CPU time 1.63 seconds
Started Aug 17 06:12:34 PM PDT 24
Finished Aug 17 06:12:36 PM PDT 24
Peak memory 207540 kb
Host smart-e00a1e6b-0ba9-4550-86cb-6ac2407cf08c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435719095 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 401.usbdev_tx_rx_disruption.1435719095
Directory /workspace/401.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/402.usbdev_tx_rx_disruption.2361595211
Short name T3070
Test name
Test status
Simulation time 578599748 ps
CPU time 1.73 seconds
Started Aug 17 06:12:25 PM PDT 24
Finished Aug 17 06:12:27 PM PDT 24
Peak memory 207528 kb
Host smart-75e7056d-f4d1-4c0f-8689-df2ed9e171b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361595211 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 402.usbdev_tx_rx_disruption.2361595211
Directory /workspace/402.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/403.usbdev_tx_rx_disruption.2571217328
Short name T3568
Test name
Test status
Simulation time 590870238 ps
CPU time 1.69 seconds
Started Aug 17 06:12:20 PM PDT 24
Finished Aug 17 06:12:22 PM PDT 24
Peak memory 207536 kb
Host smart-61cdf6a2-6049-479d-ac18-8fb294e55a39
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571217328 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 403.usbdev_tx_rx_disruption.2571217328
Directory /workspace/403.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/404.usbdev_tx_rx_disruption.1892384849
Short name T858
Test name
Test status
Simulation time 557239402 ps
CPU time 1.57 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207544 kb
Host smart-c6ba3a5a-14b2-43dd-9e44-5097963a47c1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892384849 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 404.usbdev_tx_rx_disruption.1892384849
Directory /workspace/404.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/405.usbdev_tx_rx_disruption.3436420026
Short name T1785
Test name
Test status
Simulation time 571573664 ps
CPU time 1.63 seconds
Started Aug 17 06:12:36 PM PDT 24
Finished Aug 17 06:12:38 PM PDT 24
Peak memory 207432 kb
Host smart-89965c78-4865-457f-9337-642612e51864
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436420026 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 405.usbdev_tx_rx_disruption.3436420026
Directory /workspace/405.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/406.usbdev_tx_rx_disruption.2997601080
Short name T1086
Test name
Test status
Simulation time 630176056 ps
CPU time 1.87 seconds
Started Aug 17 06:12:24 PM PDT 24
Finished Aug 17 06:12:26 PM PDT 24
Peak memory 207548 kb
Host smart-bdfded96-017e-4e76-9a8d-6618d594525e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997601080 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 406.usbdev_tx_rx_disruption.2997601080
Directory /workspace/406.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/407.usbdev_tx_rx_disruption.3689741280
Short name T1021
Test name
Test status
Simulation time 567432685 ps
CPU time 1.59 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207556 kb
Host smart-5c1fee47-af40-40bf-a513-4d27a353a454
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689741280 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 407.usbdev_tx_rx_disruption.3689741280
Directory /workspace/407.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/408.usbdev_tx_rx_disruption.1300784841
Short name T2905
Test name
Test status
Simulation time 474846539 ps
CPU time 1.57 seconds
Started Aug 17 06:12:19 PM PDT 24
Finished Aug 17 06:12:21 PM PDT 24
Peak memory 207596 kb
Host smart-143d8517-da62-4b1d-a2ab-af2df7faeba1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300784841 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 408.usbdev_tx_rx_disruption.1300784841
Directory /workspace/408.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/409.usbdev_tx_rx_disruption.1241591592
Short name T2973
Test name
Test status
Simulation time 628995378 ps
CPU time 1.66 seconds
Started Aug 17 06:12:21 PM PDT 24
Finished Aug 17 06:12:23 PM PDT 24
Peak memory 207544 kb
Host smart-4078830d-3b86-4bf8-88be-9a6807dc4b1c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241591592 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 409.usbdev_tx_rx_disruption.1241591592
Directory /workspace/409.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1779359634
Short name T2788
Test name
Test status
Simulation time 39804683 ps
CPU time 0.67 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:53 PM PDT 24
Peak memory 207428 kb
Host smart-8d0255fc-a30d-4f56-9de3-50c7dc15bbd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1779359634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1779359634
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3687939836
Short name T2184
Test name
Test status
Simulation time 6478538561 ps
CPU time 8.68 seconds
Started Aug 17 06:09:51 PM PDT 24
Finished Aug 17 06:09:59 PM PDT 24
Peak memory 215984 kb
Host smart-53e2b798-6bc1-4152-a172-a46a70ef7d61
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687939836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.3687939836
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1647031947
Short name T2497
Test name
Test status
Simulation time 14167962081 ps
CPU time 17.28 seconds
Started Aug 17 06:09:55 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 215964 kb
Host smart-dcca38af-0bc7-431b-814d-197ad39b2845
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647031947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1647031947
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3666913812
Short name T3413
Test name
Test status
Simulation time 30226820103 ps
CPU time 34.85 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:10:25 PM PDT 24
Peak memory 207812 kb
Host smart-8e34c800-e5e9-463f-a448-141bb1acc7d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666913812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.3666913812
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2874753771
Short name T1012
Test name
Test status
Simulation time 177006983 ps
CPU time 0.9 seconds
Started Aug 17 06:09:44 PM PDT 24
Finished Aug 17 06:09:45 PM PDT 24
Peak memory 207368 kb
Host smart-0995cc43-c0d3-4fe3-928f-b69393e3bcab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28747
53771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2874753771
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1016595027
Short name T2572
Test name
Test status
Simulation time 149444570 ps
CPU time 0.9 seconds
Started Aug 17 06:09:46 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 207512 kb
Host smart-69a67cf7-0084-4671-8107-6d832f30f226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10165
95027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1016595027
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3291443964
Short name T1550
Test name
Test status
Simulation time 235857313 ps
CPU time 1.17 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207592 kb
Host smart-811fd913-b516-4242-ba90-b802ed0905d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914
43964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3291443964
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.497803637
Short name T110
Test name
Test status
Simulation time 934084624 ps
CPU time 2.45 seconds
Started Aug 17 06:09:55 PM PDT 24
Finished Aug 17 06:09:57 PM PDT 24
Peak memory 207772 kb
Host smart-f939f8d7-aa58-4e3f-912c-38aa4a2e52a8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=497803637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.497803637
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2765069821
Short name T496
Test name
Test status
Simulation time 17228751504 ps
CPU time 27.93 seconds
Started Aug 17 06:09:51 PM PDT 24
Finished Aug 17 06:10:20 PM PDT 24
Peak memory 207776 kb
Host smart-2c4607cd-b1a9-494f-94f4-4cfa5e556e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27650
69821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2765069821
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.333978571
Short name T3011
Test name
Test status
Simulation time 1019931105 ps
CPU time 21.48 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:10:15 PM PDT 24
Peak memory 207676 kb
Host smart-7a23056b-ac15-48ce-8d8b-8459989e60d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333978571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.333978571
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3432425568
Short name T1831
Test name
Test status
Simulation time 755500395 ps
CPU time 1.74 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207524 kb
Host smart-bf92b23f-e3ea-4b04-91d7-84bcef949538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34324
25568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3432425568
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3462256055
Short name T1413
Test name
Test status
Simulation time 141887200 ps
CPU time 0.86 seconds
Started Aug 17 06:09:48 PM PDT 24
Finished Aug 17 06:09:49 PM PDT 24
Peak memory 207440 kb
Host smart-1c97da0f-19ea-4a24-9d91-3f103b89cb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34622
56055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3462256055
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.1922359972
Short name T530
Test name
Test status
Simulation time 31792399 ps
CPU time 0.69 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:09:46 PM PDT 24
Peak memory 207356 kb
Host smart-0508505c-0c11-4a11-ba82-668983686923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19223
59972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1922359972
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.4187612066
Short name T3343
Test name
Test status
Simulation time 820107462 ps
CPU time 2.38 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:09:53 PM PDT 24
Peak memory 207656 kb
Host smart-ea3310d0-c587-4798-ad98-20a820a62124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41876
12066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.4187612066
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_types.282934835
Short name T464
Test name
Test status
Simulation time 333753901 ps
CPU time 1.16 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:55 PM PDT 24
Peak memory 207464 kb
Host smart-d3015d43-bf00-4ad0-bca3-0d821a5ccde8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=282934835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.282934835
Directory /workspace/41.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3545576690
Short name T888
Test name
Test status
Simulation time 185754634 ps
CPU time 2.54 seconds
Started Aug 17 06:09:42 PM PDT 24
Finished Aug 17 06:09:45 PM PDT 24
Peak memory 207564 kb
Host smart-9bbddb24-6d86-4b43-82a1-09220d94e32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35455
76690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3545576690
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1823229042
Short name T1377
Test name
Test status
Simulation time 172731430 ps
CPU time 0.96 seconds
Started Aug 17 06:09:55 PM PDT 24
Finished Aug 17 06:09:56 PM PDT 24
Peak memory 207488 kb
Host smart-f21a8398-aee9-4806-9436-c2508cb6b1ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1823229042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1823229042
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3091840825
Short name T3124
Test name
Test status
Simulation time 156051574 ps
CPU time 0.83 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207428 kb
Host smart-f9994129-b103-4498-98f1-11c4a38e9a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30918
40825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3091840825
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2875300945
Short name T1693
Test name
Test status
Simulation time 219503550 ps
CPU time 0.98 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:53 PM PDT 24
Peak memory 207432 kb
Host smart-4e3a6f3c-17e8-4291-af03-eb3c6067a4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28753
00945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2875300945
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.2264887435
Short name T2915
Test name
Test status
Simulation time 4103508788 ps
CPU time 40.03 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:10:30 PM PDT 24
Peak memory 224152 kb
Host smart-9bad3e0d-f01a-451c-92c3-f0b16bad2735
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2264887435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2264887435
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.4107731879
Short name T1818
Test name
Test status
Simulation time 7544491348 ps
CPU time 48.61 seconds
Started Aug 17 06:09:56 PM PDT 24
Finished Aug 17 06:10:45 PM PDT 24
Peak memory 207772 kb
Host smart-ef95c56d-5c3c-4ead-8c20-dc0bccc52a65
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4107731879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.4107731879
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3414931566
Short name T1920
Test name
Test status
Simulation time 195769590 ps
CPU time 0.88 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:09:51 PM PDT 24
Peak memory 207468 kb
Host smart-bcf84227-064b-462a-bae5-dfb8d009ecaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34149
31566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3414931566
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.804501415
Short name T1326
Test name
Test status
Simulation time 30472646159 ps
CPU time 51.2 seconds
Started Aug 17 06:09:45 PM PDT 24
Finished Aug 17 06:10:36 PM PDT 24
Peak memory 207660 kb
Host smart-70ad3193-f2b0-4f34-87c1-200fa05535ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80450
1415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.804501415
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1027212173
Short name T1863
Test name
Test status
Simulation time 4263815662 ps
CPU time 127.76 seconds
Started Aug 17 06:10:06 PM PDT 24
Finished Aug 17 06:12:14 PM PDT 24
Peak memory 215912 kb
Host smart-83245ab7-3a6a-4fa0-afc2-bfe13cc51927
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1027212173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1027212173
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3550854798
Short name T3207
Test name
Test status
Simulation time 3127402350 ps
CPU time 26.02 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:10:18 PM PDT 24
Peak memory 216936 kb
Host smart-766e06db-6a41-4a15-9a18-5fdc97bfac75
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3550854798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3550854798
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.821924421
Short name T1641
Test name
Test status
Simulation time 271092450 ps
CPU time 1.01 seconds
Started Aug 17 06:09:54 PM PDT 24
Finished Aug 17 06:09:55 PM PDT 24
Peak memory 207420 kb
Host smart-c15b82a6-91c7-4899-b644-f92c682af152
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=821924421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.821924421
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.444332470
Short name T1144
Test name
Test status
Simulation time 193971694 ps
CPU time 1.09 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:53 PM PDT 24
Peak memory 207460 kb
Host smart-c25a89dc-7207-41ba-9301-fbdca70369dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44433
2470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.444332470
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.3388643975
Short name T2796
Test name
Test status
Simulation time 2253224630 ps
CPU time 62.4 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:10:53 PM PDT 24
Peak memory 217184 kb
Host smart-1f473f9f-ac7a-499c-b253-34303677636b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3388643975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.3388643975
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.863077499
Short name T1913
Test name
Test status
Simulation time 157879323 ps
CPU time 0.91 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207420 kb
Host smart-6cd64c0c-3ac9-4ab9-8b75-e61e3eff4f41
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=863077499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.863077499
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2350266514
Short name T1448
Test name
Test status
Simulation time 142969098 ps
CPU time 0.83 seconds
Started Aug 17 06:10:00 PM PDT 24
Finished Aug 17 06:10:01 PM PDT 24
Peak memory 207464 kb
Host smart-cd8a4d05-2df8-4230-86b7-3cf7989b8784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23502
66514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2350266514
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.4143343081
Short name T3454
Test name
Test status
Simulation time 273821413 ps
CPU time 1.01 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:09:51 PM PDT 24
Peak memory 207460 kb
Host smart-44686148-5147-4f96-aa3a-f3d657290588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41433
43081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.4143343081
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1667770380
Short name T3189
Test name
Test status
Simulation time 177960681 ps
CPU time 0.92 seconds
Started Aug 17 06:09:58 PM PDT 24
Finished Aug 17 06:09:59 PM PDT 24
Peak memory 207488 kb
Host smart-f46b20b2-d5c7-4ec3-8ff3-ed5e551633bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16677
70380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1667770380
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.129369612
Short name T927
Test name
Test status
Simulation time 153425006 ps
CPU time 0.85 seconds
Started Aug 17 06:09:49 PM PDT 24
Finished Aug 17 06:09:50 PM PDT 24
Peak memory 207464 kb
Host smart-752a754e-3210-4deb-959d-3c66498868c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12936
9612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.129369612
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.405570652
Short name T531
Test name
Test status
Simulation time 183642374 ps
CPU time 0.89 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207760 kb
Host smart-edb5ea9d-8b18-4752-ab1c-36b86d018ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40557
0652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.405570652
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3653151879
Short name T1976
Test name
Test status
Simulation time 162227988 ps
CPU time 0.88 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 207564 kb
Host smart-0d14801e-5dde-40d4-a107-230e1cfab4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36531
51879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3653151879
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2422142445
Short name T380
Test name
Test status
Simulation time 228678045 ps
CPU time 1.03 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:53 PM PDT 24
Peak memory 207540 kb
Host smart-0f53da31-f316-44f2-9920-88f4b1c53664
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2422142445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2422142445
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2765840743
Short name T1401
Test name
Test status
Simulation time 154441277 ps
CPU time 0.86 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207456 kb
Host smart-e1a252fd-977a-4ede-a778-bf9cf81614a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658
40743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2765840743
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3734493319
Short name T3565
Test name
Test status
Simulation time 43295006 ps
CPU time 0.72 seconds
Started Aug 17 06:10:00 PM PDT 24
Finished Aug 17 06:10:01 PM PDT 24
Peak memory 207464 kb
Host smart-c1b01e76-d5df-49dc-911a-27ad42785433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37344
93319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3734493319
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2092719190
Short name T2259
Test name
Test status
Simulation time 9118884251 ps
CPU time 24.99 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:10:17 PM PDT 24
Peak memory 224136 kb
Host smart-8e5f235a-9d5d-4469-8552-7c50fb150cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20927
19190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2092719190
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.3129827572
Short name T3288
Test name
Test status
Simulation time 185196457 ps
CPU time 0.99 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:53 PM PDT 24
Peak memory 207488 kb
Host smart-adc2a031-21dd-4e30-b119-38f0e67823df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31298
27572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3129827572
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.46067734
Short name T2367
Test name
Test status
Simulation time 209472430 ps
CPU time 0.96 seconds
Started Aug 17 06:09:51 PM PDT 24
Finished Aug 17 06:09:52 PM PDT 24
Peak memory 207456 kb
Host smart-0f838443-656c-4a16-b8fd-d7b60482ade0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46067
734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.46067734
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3116922094
Short name T3433
Test name
Test status
Simulation time 229205382 ps
CPU time 1 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207468 kb
Host smart-69ebfa98-1862-476b-81d7-144f3f45c25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31169
22094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3116922094
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1349610107
Short name T1407
Test name
Test status
Simulation time 190773175 ps
CPU time 0.95 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:10:13 PM PDT 24
Peak memory 207464 kb
Host smart-4db8da9f-d125-4f40-819a-261eace9e4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13496
10107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1349610107
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.710028179
Short name T2239
Test name
Test status
Simulation time 230652887 ps
CPU time 0.94 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207448 kb
Host smart-07b678d3-951f-4a68-8b6d-bae4831246c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71002
8179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.710028179
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_rx_full.2956066703
Short name T29
Test name
Test status
Simulation time 333611078 ps
CPU time 1.2 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 207484 kb
Host smart-aab0bbfb-9966-437a-b2be-ced8b37c6ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29560
66703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.2956066703
Directory /workspace/41.usbdev_rx_full/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.839123464
Short name T1729
Test name
Test status
Simulation time 177596068 ps
CPU time 0.89 seconds
Started Aug 17 06:09:58 PM PDT 24
Finished Aug 17 06:09:59 PM PDT 24
Peak memory 207464 kb
Host smart-5909093d-4d2f-4058-a92c-155e2af01c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83912
3464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.839123464
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3628998846
Short name T1221
Test name
Test status
Simulation time 183312932 ps
CPU time 0.88 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207428 kb
Host smart-9fd4c30c-765e-47ed-ba70-359e232684c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289
98846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3628998846
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.987743340
Short name T3081
Test name
Test status
Simulation time 270927090 ps
CPU time 1.17 seconds
Started Aug 17 06:09:56 PM PDT 24
Finished Aug 17 06:09:58 PM PDT 24
Peak memory 207468 kb
Host smart-60522ec3-b4fe-47c0-8b1e-2c59ff0004ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98774
3340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.987743340
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2535545028
Short name T561
Test name
Test status
Simulation time 2585868890 ps
CPU time 75.86 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 217676 kb
Host smart-a36aac38-b03c-4e42-aeea-3eb032d6e71e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2535545028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2535545028
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1569552189
Short name T946
Test name
Test status
Simulation time 167283768 ps
CPU time 0.88 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207424 kb
Host smart-b2ad4853-e7ac-4bef-98c3-c7ce68ba8f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15695
52189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1569552189
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1591023199
Short name T1050
Test name
Test status
Simulation time 179640529 ps
CPU time 0.93 seconds
Started Aug 17 06:10:05 PM PDT 24
Finished Aug 17 06:10:06 PM PDT 24
Peak memory 207568 kb
Host smart-e1478041-f201-4d90-9c1d-d0ee7c3692a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15910
23199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1591023199
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.554068555
Short name T3287
Test name
Test status
Simulation time 583361314 ps
CPU time 1.75 seconds
Started Aug 17 06:09:50 PM PDT 24
Finished Aug 17 06:09:52 PM PDT 24
Peak memory 207500 kb
Host smart-7042cc37-28aa-47a9-a62a-e83df4e0593b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55406
8555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.554068555
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.4087946712
Short name T3285
Test name
Test status
Simulation time 2626172766 ps
CPU time 75.03 seconds
Started Aug 17 06:09:58 PM PDT 24
Finished Aug 17 06:11:13 PM PDT 24
Peak memory 215928 kb
Host smart-05b44d5c-0fcb-49ca-bda4-8979cbfba0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40879
46712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.4087946712
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.3196492728
Short name T546
Test name
Test status
Simulation time 981364986 ps
CPU time 22.11 seconds
Started Aug 17 06:09:55 PM PDT 24
Finished Aug 17 06:10:17 PM PDT 24
Peak memory 207636 kb
Host smart-eb1e7f5a-5fd2-4ae8-ad9b-245d9e0041ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196492728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.3196492728
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_tx_rx_disruption.3650394988
Short name T3417
Test name
Test status
Simulation time 556817281 ps
CPU time 1.79 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207548 kb
Host smart-eb1e6a4b-ab1b-4810-822f-eaa70af80c97
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650394988 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.usbdev_tx_rx_disruption.3650394988
Directory /workspace/41.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/410.usbdev_tx_rx_disruption.3862898084
Short name T2904
Test name
Test status
Simulation time 567936017 ps
CPU time 1.69 seconds
Started Aug 17 06:12:27 PM PDT 24
Finished Aug 17 06:12:29 PM PDT 24
Peak memory 207568 kb
Host smart-d7f349eb-b2c0-4621-a39c-7f3c0a000964
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862898084 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 410.usbdev_tx_rx_disruption.3862898084
Directory /workspace/410.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/411.usbdev_tx_rx_disruption.1831182491
Short name T1746
Test name
Test status
Simulation time 521992295 ps
CPU time 1.59 seconds
Started Aug 17 06:12:39 PM PDT 24
Finished Aug 17 06:12:40 PM PDT 24
Peak memory 207580 kb
Host smart-b0ce5c76-7811-4599-ac50-da00b0001ecb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831182491 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 411.usbdev_tx_rx_disruption.1831182491
Directory /workspace/411.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/412.usbdev_tx_rx_disruption.2683887898
Short name T1402
Test name
Test status
Simulation time 495877590 ps
CPU time 1.63 seconds
Started Aug 17 06:12:14 PM PDT 24
Finished Aug 17 06:12:16 PM PDT 24
Peak memory 207492 kb
Host smart-ca45d4e0-7ea1-4dd0-802d-761b4c48cf58
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683887898 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 412.usbdev_tx_rx_disruption.2683887898
Directory /workspace/412.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/413.usbdev_tx_rx_disruption.2938076270
Short name T866
Test name
Test status
Simulation time 596924107 ps
CPU time 1.82 seconds
Started Aug 17 06:12:20 PM PDT 24
Finished Aug 17 06:12:22 PM PDT 24
Peak memory 207560 kb
Host smart-5773d775-ec31-47dc-8234-3792dfb7f2bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938076270 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 413.usbdev_tx_rx_disruption.2938076270
Directory /workspace/413.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/414.usbdev_tx_rx_disruption.951360670
Short name T2236
Test name
Test status
Simulation time 497941933 ps
CPU time 1.44 seconds
Started Aug 17 06:12:40 PM PDT 24
Finished Aug 17 06:12:41 PM PDT 24
Peak memory 206496 kb
Host smart-f5e63866-7fd2-461c-a520-e071b4d6e10a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951360670 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 414.usbdev_tx_rx_disruption.951360670
Directory /workspace/414.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/415.usbdev_tx_rx_disruption.2559184892
Short name T2502
Test name
Test status
Simulation time 429209303 ps
CPU time 1.48 seconds
Started Aug 17 06:12:19 PM PDT 24
Finished Aug 17 06:12:21 PM PDT 24
Peak memory 207556 kb
Host smart-99db0b2b-e24a-40f9-92a6-b6b5451cccb0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559184892 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 415.usbdev_tx_rx_disruption.2559184892
Directory /workspace/415.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/416.usbdev_tx_rx_disruption.3054989631
Short name T2206
Test name
Test status
Simulation time 576005605 ps
CPU time 1.6 seconds
Started Aug 17 06:12:24 PM PDT 24
Finished Aug 17 06:12:26 PM PDT 24
Peak memory 207560 kb
Host smart-3b7a2830-3107-4a29-93eb-c78f49348e8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054989631 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 416.usbdev_tx_rx_disruption.3054989631
Directory /workspace/416.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/417.usbdev_tx_rx_disruption.2001851858
Short name T2495
Test name
Test status
Simulation time 615362470 ps
CPU time 1.74 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207544 kb
Host smart-ca32d0dd-6d41-4fc7-8dee-dbea9b5aca45
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001851858 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 417.usbdev_tx_rx_disruption.2001851858
Directory /workspace/417.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/418.usbdev_tx_rx_disruption.1751829172
Short name T2954
Test name
Test status
Simulation time 561801971 ps
CPU time 1.5 seconds
Started Aug 17 06:12:31 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207520 kb
Host smart-c8b6f8a2-84e0-4c4e-890c-04131df98c51
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751829172 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 418.usbdev_tx_rx_disruption.1751829172
Directory /workspace/418.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/419.usbdev_tx_rx_disruption.3612274582
Short name T2078
Test name
Test status
Simulation time 508413031 ps
CPU time 1.58 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:38 PM PDT 24
Peak memory 207568 kb
Host smart-78a969d1-2f37-4fd7-afa4-737e4c57878b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612274582 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 419.usbdev_tx_rx_disruption.3612274582
Directory /workspace/419.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.823294012
Short name T1422
Test name
Test status
Simulation time 53282988 ps
CPU time 0.67 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 207432 kb
Host smart-e8230f78-202f-45df-b37c-ef21102e90cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=823294012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.823294012
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1103390474
Short name T2112
Test name
Test status
Simulation time 10476528319 ps
CPU time 13.29 seconds
Started Aug 17 06:10:02 PM PDT 24
Finished Aug 17 06:10:15 PM PDT 24
Peak memory 207712 kb
Host smart-3bb126b0-eec8-4b8f-b1e4-8a8994d98710
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103390474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.1103390474
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1959534188
Short name T1139
Test name
Test status
Simulation time 14571406296 ps
CPU time 21.08 seconds
Started Aug 17 06:10:04 PM PDT 24
Finished Aug 17 06:10:25 PM PDT 24
Peak memory 215956 kb
Host smart-cadf6885-bd83-44b6-aa05-9ddd86fca9ba
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959534188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1959534188
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1875148535
Short name T3374
Test name
Test status
Simulation time 29879645224 ps
CPU time 40 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:10:33 PM PDT 24
Peak memory 207780 kb
Host smart-17d95a20-a60d-48d1-aa99-2587cba79aa3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875148535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.1875148535
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1373810223
Short name T2620
Test name
Test status
Simulation time 187529436 ps
CPU time 0.98 seconds
Started Aug 17 06:09:54 PM PDT 24
Finished Aug 17 06:09:55 PM PDT 24
Peak memory 207456 kb
Host smart-cded4217-4af1-4653-b97e-9d0f0adfb099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13738
10223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1373810223
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.1374357987
Short name T2362
Test name
Test status
Simulation time 162792577 ps
CPU time 0.92 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207552 kb
Host smart-ef1f42b2-6bf3-48d0-a402-0b933f6c6169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13743
57987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.1374357987
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.561073490
Short name T2272
Test name
Test status
Simulation time 327892227 ps
CPU time 1.3 seconds
Started Aug 17 06:09:54 PM PDT 24
Finished Aug 17 06:09:56 PM PDT 24
Peak memory 207548 kb
Host smart-c32fb41e-13cf-46d9-8d3c-d1cbe575a73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56107
3490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.561073490
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1491053077
Short name T3169
Test name
Test status
Simulation time 1139552548 ps
CPU time 2.86 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:56 PM PDT 24
Peak memory 207936 kb
Host smart-40f0e37d-22a1-484c-b5c2-db804c79ff32
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1491053077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1491053077
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.994336843
Short name T3465
Test name
Test status
Simulation time 50575822559 ps
CPU time 90.53 seconds
Started Aug 17 06:09:54 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207776 kb
Host smart-ba3c77d2-bc65-4d41-a21e-5ddc62f38381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99433
6843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.994336843
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.786248156
Short name T1299
Test name
Test status
Simulation time 275233924 ps
CPU time 4.45 seconds
Started Aug 17 06:09:53 PM PDT 24
Finished Aug 17 06:09:57 PM PDT 24
Peak memory 207700 kb
Host smart-e8cf8462-7dcf-4fdf-8fb1-8baff27851e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786248156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.786248156
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.2589964521
Short name T1306
Test name
Test status
Simulation time 691556968 ps
CPU time 1.65 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:54 PM PDT 24
Peak memory 207488 kb
Host smart-fe51042e-3296-427f-9c68-d1e3cd904d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25899
64521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.2589964521
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.4180442421
Short name T2842
Test name
Test status
Simulation time 175932619 ps
CPU time 0.99 seconds
Started Aug 17 06:10:10 PM PDT 24
Finished Aug 17 06:10:11 PM PDT 24
Peak memory 207508 kb
Host smart-a0bb72d3-48bf-4989-bb5d-3307b45cb150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41804
42421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.4180442421
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2505108549
Short name T1181
Test name
Test status
Simulation time 62682987 ps
CPU time 0.75 seconds
Started Aug 17 06:09:52 PM PDT 24
Finished Aug 17 06:09:53 PM PDT 24
Peak memory 207428 kb
Host smart-c618a1f3-9d45-41af-bef6-9522efa4fc93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25051
08549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2505108549
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3672333223
Short name T2862
Test name
Test status
Simulation time 905540120 ps
CPU time 2.68 seconds
Started Aug 17 06:10:10 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 207756 kb
Host smart-6fb003f7-b858-4805-b5c0-ad797bca8705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36723
33223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3672333223
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_types.3869442014
Short name T462
Test name
Test status
Simulation time 809120920 ps
CPU time 1.88 seconds
Started Aug 17 06:10:03 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 207520 kb
Host smart-ff47bb30-8dc8-4def-8d90-ecf3e597fd0e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3869442014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.3869442014
Directory /workspace/42.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1789057509
Short name T2558
Test name
Test status
Simulation time 185014745 ps
CPU time 2.39 seconds
Started Aug 17 06:09:57 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 207612 kb
Host smart-4d2c4209-dfb1-473f-93ea-1f84fc636273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17890
57509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1789057509
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3391635572
Short name T1064
Test name
Test status
Simulation time 185884225 ps
CPU time 1.01 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 215868 kb
Host smart-6e1809a9-ecee-47cd-902e-9837cb676974
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3391635572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3391635572
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.4137434540
Short name T3152
Test name
Test status
Simulation time 143945382 ps
CPU time 0.83 seconds
Started Aug 17 06:09:58 PM PDT 24
Finished Aug 17 06:09:59 PM PDT 24
Peak memory 207400 kb
Host smart-6f9b8532-a4fb-484a-bbc9-e9309f261794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41374
34540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.4137434540
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.750156718
Short name T1394
Test name
Test status
Simulation time 222168255 ps
CPU time 1 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207476 kb
Host smart-ab71395d-e016-42df-b795-72ef3388cea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75015
6718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.750156718
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.2575643567
Short name T3527
Test name
Test status
Simulation time 3366147684 ps
CPU time 34.69 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 217068 kb
Host smart-974c6637-a571-4300-b6d0-917cab20651f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2575643567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2575643567
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.2979005895
Short name T98
Test name
Test status
Simulation time 10225315883 ps
CPU time 69.09 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:11:08 PM PDT 24
Peak memory 207776 kb
Host smart-580bf9af-5053-472a-af21-e37af4c41510
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2979005895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.2979005895
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3623570010
Short name T964
Test name
Test status
Simulation time 226991683 ps
CPU time 1.02 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207564 kb
Host smart-8ee029ca-ca18-4b2d-a0e8-23e63449f9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36235
70010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3623570010
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1292981446
Short name T350
Test name
Test status
Simulation time 13597207844 ps
CPU time 18.09 seconds
Started Aug 17 06:10:07 PM PDT 24
Finished Aug 17 06:10:25 PM PDT 24
Peak memory 207828 kb
Host smart-12a20068-ce52-4eb6-956e-d956b92d73dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12929
81446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1292981446
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3826899987
Short name T100
Test name
Test status
Simulation time 9891293386 ps
CPU time 14.01 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:13 PM PDT 24
Peak memory 207800 kb
Host smart-2b43c6f7-f5b3-43b1-9640-18aec4126fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38268
99987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3826899987
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.1130367410
Short name T1107
Test name
Test status
Simulation time 3728476218 ps
CPU time 110.37 seconds
Started Aug 17 06:09:58 PM PDT 24
Finished Aug 17 06:11:48 PM PDT 24
Peak memory 224156 kb
Host smart-06e03022-1941-4846-8806-585b0f59dafd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1130367410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.1130367410
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.368895474
Short name T2137
Test name
Test status
Simulation time 1569379450 ps
CPU time 12.64 seconds
Started Aug 17 06:10:00 PM PDT 24
Finished Aug 17 06:10:13 PM PDT 24
Peak memory 224008 kb
Host smart-3f21fb6f-b56e-414c-be0b-1695e1cfc826
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=368895474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.368895474
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2516455480
Short name T1130
Test name
Test status
Simulation time 246708791 ps
CPU time 1.01 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 207708 kb
Host smart-142642aa-6811-43d2-b69c-6be6a473f837
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2516455480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2516455480
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1977428206
Short name T1801
Test name
Test status
Simulation time 224603983 ps
CPU time 0.98 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:10:11 PM PDT 24
Peak memory 207380 kb
Host smart-0663d103-7f11-44fe-9a78-a9e96e59d8c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19774
28206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1977428206
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1053576319
Short name T2743
Test name
Test status
Simulation time 1678802716 ps
CPU time 47.99 seconds
Started Aug 17 06:10:13 PM PDT 24
Finished Aug 17 06:11:01 PM PDT 24
Peak memory 215820 kb
Host smart-7b6e0946-fcd3-4312-aad4-ca6583f81301
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1053576319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1053576319
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3016233704
Short name T1688
Test name
Test status
Simulation time 157380616 ps
CPU time 0.9 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207468 kb
Host smart-616b9b8c-8d94-4f95-a117-7b711b175a40
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3016233704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3016233704
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.188157662
Short name T1274
Test name
Test status
Simulation time 140213378 ps
CPU time 0.82 seconds
Started Aug 17 06:10:03 PM PDT 24
Finished Aug 17 06:10:03 PM PDT 24
Peak memory 207460 kb
Host smart-76c95c1e-451c-488d-afb9-237a86e5f6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815
7662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.188157662
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1877058888
Short name T3052
Test name
Test status
Simulation time 205318903 ps
CPU time 0.96 seconds
Started Aug 17 06:10:03 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 207540 kb
Host smart-87aa9d63-8aba-4728-8c58-0d54649709ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18770
58888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1877058888
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2168841214
Short name T2395
Test name
Test status
Simulation time 210523486 ps
CPU time 0.96 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 207436 kb
Host smart-bdbb7bcd-8339-4f14-9caf-d8a06e85dc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21688
41214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2168841214
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3443579482
Short name T2898
Test name
Test status
Simulation time 182141326 ps
CPU time 0.92 seconds
Started Aug 17 06:10:03 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 207448 kb
Host smart-8b3e3c33-bb93-452e-8fb0-232f2ef960b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34435
79482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3443579482
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2585845737
Short name T3147
Test name
Test status
Simulation time 249618114 ps
CPU time 0.99 seconds
Started Aug 17 06:10:00 PM PDT 24
Finished Aug 17 06:10:01 PM PDT 24
Peak memory 207596 kb
Host smart-cd744d99-474f-4ab1-8b55-8f7b632a3d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25858
45737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2585845737
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.4209810894
Short name T1572
Test name
Test status
Simulation time 160884388 ps
CPU time 0.86 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:10:13 PM PDT 24
Peak memory 207560 kb
Host smart-467145fc-e796-479d-929c-34f30ea4978b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42098
10894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.4209810894
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.2347408648
Short name T2960
Test name
Test status
Simulation time 227679106 ps
CPU time 1.03 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207468 kb
Host smart-989bfde9-9bc8-4376-8005-a2847c641c61
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2347408648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2347408648
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3024020182
Short name T3243
Test name
Test status
Simulation time 172028869 ps
CPU time 0.92 seconds
Started Aug 17 06:10:00 PM PDT 24
Finished Aug 17 06:10:01 PM PDT 24
Peak memory 207436 kb
Host smart-6997c8d6-26c7-4d0c-9ecf-e25d90a3524e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30240
20182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3024020182
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3891527471
Short name T834
Test name
Test status
Simulation time 35540077 ps
CPU time 0.69 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207400 kb
Host smart-0025e9ef-8078-4030-b726-ec0fe8fc9e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38915
27471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3891527471
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2321466648
Short name T273
Test name
Test status
Simulation time 20111570950 ps
CPU time 54.99 seconds
Started Aug 17 06:10:05 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 224060 kb
Host smart-11e29da8-e489-43b7-b39e-107194364f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23214
66648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2321466648
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.4082687924
Short name T1261
Test name
Test status
Simulation time 164937592 ps
CPU time 0.9 seconds
Started Aug 17 06:10:05 PM PDT 24
Finished Aug 17 06:10:06 PM PDT 24
Peak memory 207532 kb
Host smart-89424c48-0a3a-4468-a6a5-ba674eb57ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40826
87924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.4082687924
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2101827719
Short name T2880
Test name
Test status
Simulation time 205324774 ps
CPU time 0.98 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207436 kb
Host smart-f47e8849-e091-4439-8e3e-d2a6ddee007e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21018
27719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2101827719
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.443390529
Short name T2833
Test name
Test status
Simulation time 171642339 ps
CPU time 0.88 seconds
Started Aug 17 06:10:01 PM PDT 24
Finished Aug 17 06:10:02 PM PDT 24
Peak memory 207472 kb
Host smart-238f24c3-97fe-402f-a4d0-ad6d64969eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44339
0529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.443390529
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3326514404
Short name T993
Test name
Test status
Simulation time 172580031 ps
CPU time 0.86 seconds
Started Aug 17 06:10:04 PM PDT 24
Finished Aug 17 06:10:05 PM PDT 24
Peak memory 207456 kb
Host smart-74149845-faa3-4d71-acf2-03e0da2778ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33265
14404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3326514404
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1636963359
Short name T3550
Test name
Test status
Simulation time 236640570 ps
CPU time 0.95 seconds
Started Aug 17 06:10:11 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 207476 kb
Host smart-670f1ec1-61af-4ab7-a587-557bcf5d9e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16369
63359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1636963359
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_rx_full.1624027576
Short name T1826
Test name
Test status
Simulation time 322527982 ps
CPU time 1.23 seconds
Started Aug 17 06:10:00 PM PDT 24
Finished Aug 17 06:10:06 PM PDT 24
Peak memory 207460 kb
Host smart-3d7253dc-5e08-41e9-ae83-d83623b3367d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16240
27576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.1624027576
Directory /workspace/42.usbdev_rx_full/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2009319079
Short name T3039
Test name
Test status
Simulation time 150247867 ps
CPU time 0.88 seconds
Started Aug 17 06:10:03 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 207504 kb
Host smart-25f1e092-f5b4-4009-86f3-3d156d0bc428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20093
19079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2009319079
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1019395752
Short name T889
Test name
Test status
Simulation time 184448323 ps
CPU time 0.89 seconds
Started Aug 17 06:09:57 PM PDT 24
Finished Aug 17 06:09:58 PM PDT 24
Peak memory 207488 kb
Host smart-1c569308-b9be-49ae-8310-0d19f0cca760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10193
95752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1019395752
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2723316790
Short name T1745
Test name
Test status
Simulation time 239215778 ps
CPU time 1.05 seconds
Started Aug 17 06:10:11 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 207460 kb
Host smart-ac0fca36-4fba-4370-a7e7-dd0f8a4866ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233
16790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2723316790
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1962311723
Short name T3317
Test name
Test status
Simulation time 3686728636 ps
CPU time 107.23 seconds
Started Aug 17 06:10:06 PM PDT 24
Finished Aug 17 06:11:53 PM PDT 24
Peak memory 217776 kb
Host smart-66e23c11-18c0-45eb-b286-a7901d96d116
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1962311723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1962311723
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3521670148
Short name T3594
Test name
Test status
Simulation time 225293316 ps
CPU time 0.98 seconds
Started Aug 17 06:10:00 PM PDT 24
Finished Aug 17 06:10:01 PM PDT 24
Peak memory 207392 kb
Host smart-ce944f61-2b04-467d-ac4b-179aa72d0b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35216
70148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3521670148
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2193806340
Short name T2895
Test name
Test status
Simulation time 155196328 ps
CPU time 0.88 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 207536 kb
Host smart-d68bdeeb-57d7-4adc-a07c-419575b4df7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21938
06340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2193806340
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.3682155626
Short name T2645
Test name
Test status
Simulation time 1213219123 ps
CPU time 2.91 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:02 PM PDT 24
Peak memory 207740 kb
Host smart-ccdc8702-f9c6-497c-a59b-61a61b1aff9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36821
55626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.3682155626
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.512459823
Short name T2889
Test name
Test status
Simulation time 2366605379 ps
CPU time 67.26 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:11:16 PM PDT 24
Peak memory 215936 kb
Host smart-a169a182-c08d-44a3-80ba-041c0c34b648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51245
9823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.512459823
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.3348379274
Short name T757
Test name
Test status
Simulation time 2455681254 ps
CPU time 23.21 seconds
Started Aug 17 06:09:58 PM PDT 24
Finished Aug 17 06:10:21 PM PDT 24
Peak memory 207668 kb
Host smart-5c45426a-fbe3-4b7f-a00d-1d563cd5906b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348379274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.3348379274
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_tx_rx_disruption.2243049150
Short name T1518
Test name
Test status
Simulation time 499386111 ps
CPU time 1.63 seconds
Started Aug 17 06:10:10 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 207472 kb
Host smart-6674d074-5b69-4175-b1e1-42ddbcdb2423
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243049150 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.usbdev_tx_rx_disruption.2243049150
Directory /workspace/42.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/420.usbdev_tx_rx_disruption.3186890629
Short name T1669
Test name
Test status
Simulation time 552293572 ps
CPU time 1.71 seconds
Started Aug 17 06:12:26 PM PDT 24
Finished Aug 17 06:12:28 PM PDT 24
Peak memory 207540 kb
Host smart-9484fe4b-6452-41fe-ba35-b269d1b21923
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186890629 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 420.usbdev_tx_rx_disruption.3186890629
Directory /workspace/420.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/421.usbdev_tx_rx_disruption.3909905861
Short name T2157
Test name
Test status
Simulation time 627082573 ps
CPU time 1.79 seconds
Started Aug 17 06:12:35 PM PDT 24
Finished Aug 17 06:12:37 PM PDT 24
Peak memory 207548 kb
Host smart-1024b7ff-0268-4b58-b0dd-2f3db953ad13
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909905861 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 421.usbdev_tx_rx_disruption.3909905861
Directory /workspace/421.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/422.usbdev_tx_rx_disruption.4078606377
Short name T765
Test name
Test status
Simulation time 491982837 ps
CPU time 1.54 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207532 kb
Host smart-4f7a593e-f921-45ad-84af-ca2d710b9925
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078606377 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 422.usbdev_tx_rx_disruption.4078606377
Directory /workspace/422.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/423.usbdev_tx_rx_disruption.3044765177
Short name T1928
Test name
Test status
Simulation time 474806098 ps
CPU time 1.56 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 207556 kb
Host smart-9d48729e-1b43-4b96-83b9-8a3c27510559
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044765177 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 423.usbdev_tx_rx_disruption.3044765177
Directory /workspace/423.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/424.usbdev_tx_rx_disruption.58410519
Short name T120
Test name
Test status
Simulation time 489154977 ps
CPU time 1.59 seconds
Started Aug 17 06:12:36 PM PDT 24
Finished Aug 17 06:12:37 PM PDT 24
Peak memory 207552 kb
Host smart-8b481bc6-dd9f-44fe-97ce-6bd41e10f448
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58410519 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 424.usbdev_tx_rx_disruption.58410519
Directory /workspace/424.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/425.usbdev_tx_rx_disruption.1950876278
Short name T885
Test name
Test status
Simulation time 468867140 ps
CPU time 1.43 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:49 PM PDT 24
Peak memory 207500 kb
Host smart-9bf0cb64-9fe4-4736-9836-5a84c0e7f5d5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950876278 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 425.usbdev_tx_rx_disruption.1950876278
Directory /workspace/425.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/426.usbdev_tx_rx_disruption.3833995260
Short name T76
Test name
Test status
Simulation time 435339593 ps
CPU time 1.36 seconds
Started Aug 17 06:12:46 PM PDT 24
Finished Aug 17 06:12:47 PM PDT 24
Peak memory 207516 kb
Host smart-f2195498-757c-424b-90f2-7c99057c64c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833995260 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 426.usbdev_tx_rx_disruption.3833995260
Directory /workspace/426.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/427.usbdev_tx_rx_disruption.186146574
Short name T1110
Test name
Test status
Simulation time 549628573 ps
CPU time 1.66 seconds
Started Aug 17 06:12:28 PM PDT 24
Finished Aug 17 06:12:30 PM PDT 24
Peak memory 207556 kb
Host smart-59503c88-90e5-4e7d-b7de-9929bd8fe907
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186146574 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 427.usbdev_tx_rx_disruption.186146574
Directory /workspace/427.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/428.usbdev_tx_rx_disruption.4085580698
Short name T2483
Test name
Test status
Simulation time 545805627 ps
CPU time 1.68 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 207544 kb
Host smart-04479d9a-80f0-4f49-9472-267d974c6ab1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085580698 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 428.usbdev_tx_rx_disruption.4085580698
Directory /workspace/428.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/429.usbdev_tx_rx_disruption.1199048559
Short name T1440
Test name
Test status
Simulation time 697548358 ps
CPU time 1.9 seconds
Started Aug 17 06:12:33 PM PDT 24
Finished Aug 17 06:12:35 PM PDT 24
Peak memory 207544 kb
Host smart-4ea33a0f-55ee-420f-b0fb-ecd2cfbf60be
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199048559 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 429.usbdev_tx_rx_disruption.1199048559
Directory /workspace/429.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.713540534
Short name T2968
Test name
Test status
Simulation time 32841608 ps
CPU time 0.72 seconds
Started Aug 17 06:10:07 PM PDT 24
Finished Aug 17 06:10:08 PM PDT 24
Peak memory 207432 kb
Host smart-77bb132f-01e3-4f50-b5e5-1f5c2484615e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=713540534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.713540534
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1264921047
Short name T3424
Test name
Test status
Simulation time 6804780415 ps
CPU time 9.33 seconds
Started Aug 17 06:10:04 PM PDT 24
Finished Aug 17 06:10:13 PM PDT 24
Peak memory 215968 kb
Host smart-4106c78c-21fd-4b60-bd32-67b9e0f9ae95
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264921047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.1264921047
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.762487741
Short name T2094
Test name
Test status
Simulation time 14032232618 ps
CPU time 16.78 seconds
Started Aug 17 06:10:14 PM PDT 24
Finished Aug 17 06:10:30 PM PDT 24
Peak memory 215952 kb
Host smart-a02a2b27-f39f-4b4a-9fd8-d705ae75a5bb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=762487741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.762487741
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3086061836
Short name T1772
Test name
Test status
Simulation time 25913083930 ps
CPU time 37.85 seconds
Started Aug 17 06:09:57 PM PDT 24
Finished Aug 17 06:10:35 PM PDT 24
Peak memory 215984 kb
Host smart-2fb070f4-d19f-4e0a-b59f-cf2c1d1ab14f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086061836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.3086061836
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2852333613
Short name T2032
Test name
Test status
Simulation time 150531847 ps
CPU time 0.85 seconds
Started Aug 17 06:09:59 PM PDT 24
Finished Aug 17 06:10:00 PM PDT 24
Peak memory 207680 kb
Host smart-0449a9b7-c85d-4e76-ac0b-05e350497fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28523
33613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2852333613
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.4230694841
Short name T1700
Test name
Test status
Simulation time 151556782 ps
CPU time 0.86 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207472 kb
Host smart-e1293ce4-700f-4f55-bec2-b173477f99d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
94841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.4230694841
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.1825496790
Short name T1095
Test name
Test status
Simulation time 521140281 ps
CPU time 1.94 seconds
Started Aug 17 06:10:10 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 207564 kb
Host smart-741f2b0f-f1d9-41b4-b928-bede4cdd6408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18254
96790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.1825496790
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3901210073
Short name T339
Test name
Test status
Simulation time 832891071 ps
CPU time 2.51 seconds
Started Aug 17 06:10:02 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 207648 kb
Host smart-6b9b46d0-77b5-436a-b991-15ce5948e29d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3901210073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3901210073
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.2273962548
Short name T1734
Test name
Test status
Simulation time 29980122366 ps
CPU time 49.72 seconds
Started Aug 17 06:10:04 PM PDT 24
Finished Aug 17 06:10:54 PM PDT 24
Peak memory 207736 kb
Host smart-f6f6cf77-a8a1-4f72-b93c-a3e50dfed8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22739
62548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2273962548
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.2165748178
Short name T764
Test name
Test status
Simulation time 154925812 ps
CPU time 0.9 seconds
Started Aug 17 06:10:02 PM PDT 24
Finished Aug 17 06:10:03 PM PDT 24
Peak memory 207452 kb
Host smart-2a91e323-f301-437c-b746-691a4a9c71ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165748178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.2165748178
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.4088391832
Short name T3042
Test name
Test status
Simulation time 840103734 ps
CPU time 2.06 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207364 kb
Host smart-097b6853-4b6d-4cc2-a454-75fd209506f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40883
91832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.4088391832
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.2280914014
Short name T3130
Test name
Test status
Simulation time 164816852 ps
CPU time 0.87 seconds
Started Aug 17 06:10:07 PM PDT 24
Finished Aug 17 06:10:08 PM PDT 24
Peak memory 207476 kb
Host smart-9762792e-bfdb-4d47-b233-aaf30b4c1deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22809
14014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2280914014
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.75364960
Short name T793
Test name
Test status
Simulation time 56630418 ps
CPU time 0.72 seconds
Started Aug 17 06:10:04 PM PDT 24
Finished Aug 17 06:10:05 PM PDT 24
Peak memory 207436 kb
Host smart-cfa8e9fa-cdfd-4db5-b16f-89fdd7fe478b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75364
960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.75364960
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3952471661
Short name T998
Test name
Test status
Simulation time 933045251 ps
CPU time 2.3 seconds
Started Aug 17 06:10:06 PM PDT 24
Finished Aug 17 06:10:08 PM PDT 24
Peak memory 207740 kb
Host smart-495ecc8f-9ebd-45a0-a518-95f89d690e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39524
71661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3952471661
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_types.3092354715
Short name T412
Test name
Test status
Simulation time 662660881 ps
CPU time 1.65 seconds
Started Aug 17 06:10:02 PM PDT 24
Finished Aug 17 06:10:04 PM PDT 24
Peak memory 207468 kb
Host smart-d0083632-4233-425d-810f-1ee1794da74f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3092354715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.3092354715
Directory /workspace/43.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1308328958
Short name T3503
Test name
Test status
Simulation time 392972696 ps
CPU time 2.62 seconds
Started Aug 17 06:10:07 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207596 kb
Host smart-24e07092-b42d-4a3e-a624-88162427f0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13083
28958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1308328958
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.224189843
Short name T1022
Test name
Test status
Simulation time 168123332 ps
CPU time 0.94 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207420 kb
Host smart-065279e8-2ffa-4cf2-b3ef-9623cb8722cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=224189843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.224189843
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.300782780
Short name T2675
Test name
Test status
Simulation time 160882925 ps
CPU time 0.84 seconds
Started Aug 17 06:10:00 PM PDT 24
Finished Aug 17 06:10:01 PM PDT 24
Peak memory 207348 kb
Host smart-cac607c6-e5b7-4e4b-8f91-e574fc5946bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30078
2780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.300782780
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.2584026007
Short name T1483
Test name
Test status
Simulation time 263285935 ps
CPU time 1.06 seconds
Started Aug 17 06:10:05 PM PDT 24
Finished Aug 17 06:10:06 PM PDT 24
Peak memory 207468 kb
Host smart-8263383a-3c61-4d5d-972c-aa5902ad62a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25840
26007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2584026007
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.3493882136
Short name T1525
Test name
Test status
Simulation time 3758830214 ps
CPU time 27.93 seconds
Started Aug 17 06:10:04 PM PDT 24
Finished Aug 17 06:10:32 PM PDT 24
Peak memory 224200 kb
Host smart-6270afaf-a102-4eac-8b35-8a6a33820eb1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3493882136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.3493882136
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.1276775531
Short name T1307
Test name
Test status
Simulation time 6168596839 ps
CPU time 45.2 seconds
Started Aug 17 06:10:04 PM PDT 24
Finished Aug 17 06:10:50 PM PDT 24
Peak memory 207788 kb
Host smart-f3a53bed-766b-407a-8af6-3502c794ecaf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1276775531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.1276775531
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.376633367
Short name T108
Test name
Test status
Simulation time 168906016 ps
CPU time 0.88 seconds
Started Aug 17 06:10:10 PM PDT 24
Finished Aug 17 06:10:11 PM PDT 24
Peak memory 207488 kb
Host smart-88ce1713-6a09-4481-ab10-ff82f76a564d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37663
3367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.376633367
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.3331348199
Short name T1579
Test name
Test status
Simulation time 29559369044 ps
CPU time 52.39 seconds
Started Aug 17 06:10:11 PM PDT 24
Finished Aug 17 06:11:04 PM PDT 24
Peak memory 207812 kb
Host smart-8700d14b-b955-49e5-aee2-8d6419b8b690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33313
48199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.3331348199
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1682925243
Short name T2085
Test name
Test status
Simulation time 8437039672 ps
CPU time 11.43 seconds
Started Aug 17 06:10:06 PM PDT 24
Finished Aug 17 06:10:17 PM PDT 24
Peak memory 207792 kb
Host smart-7567211f-7c83-482c-a4ca-8b8cc858e57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16829
25243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1682925243
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1432784504
Short name T179
Test name
Test status
Simulation time 4601022722 ps
CPU time 51.83 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:11:01 PM PDT 24
Peak memory 218928 kb
Host smart-40a31b44-d0a2-4dc8-905f-269b2756f821
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1432784504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1432784504
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1645120230
Short name T969
Test name
Test status
Simulation time 2644272611 ps
CPU time 20.71 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:29 PM PDT 24
Peak memory 224068 kb
Host smart-5c2fbb8e-8ed2-4721-a417-2c48a282eabf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1645120230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1645120230
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.889500191
Short name T900
Test name
Test status
Simulation time 239409058 ps
CPU time 0.99 seconds
Started Aug 17 06:10:07 PM PDT 24
Finished Aug 17 06:10:08 PM PDT 24
Peak memory 207488 kb
Host smart-a0433dc5-f4c2-497e-90f0-f78366c13139
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=889500191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.889500191
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3222134332
Short name T657
Test name
Test status
Simulation time 191022629 ps
CPU time 0.95 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207484 kb
Host smart-6742403c-be79-4016-95ff-65bab235ca2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32221
34332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3222134332
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3550124587
Short name T2049
Test name
Test status
Simulation time 1751556662 ps
CPU time 48.59 seconds
Started Aug 17 06:10:11 PM PDT 24
Finished Aug 17 06:10:59 PM PDT 24
Peak memory 215824 kb
Host smart-f41ff3a1-8485-4211-9d7e-c7f5e493c087
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3550124587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3550124587
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1368916348
Short name T2540
Test name
Test status
Simulation time 203983868 ps
CPU time 0.9 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207488 kb
Host smart-5cee2ceb-aaba-4d16-b1cc-3737c710ea0d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1368916348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1368916348
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.814676148
Short name T580
Test name
Test status
Simulation time 149934740 ps
CPU time 0.83 seconds
Started Aug 17 06:10:16 PM PDT 24
Finished Aug 17 06:10:16 PM PDT 24
Peak memory 207464 kb
Host smart-930fd320-cbfb-4381-93cc-20297d8a833e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81467
6148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.814676148
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3143648859
Short name T161
Test name
Test status
Simulation time 164756448 ps
CPU time 0.92 seconds
Started Aug 17 06:10:07 PM PDT 24
Finished Aug 17 06:10:08 PM PDT 24
Peak memory 207456 kb
Host smart-97a8c7d6-6e7d-42fc-9560-94ce132d773a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31436
48859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3143648859
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2761250654
Short name T1817
Test name
Test status
Simulation time 175898431 ps
CPU time 0.94 seconds
Started Aug 17 06:10:06 PM PDT 24
Finished Aug 17 06:10:07 PM PDT 24
Peak memory 207464 kb
Host smart-3b386834-1bf7-4ab8-8b42-a55b3952bae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27612
50654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2761250654
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3971962476
Short name T1376
Test name
Test status
Simulation time 209933377 ps
CPU time 0.92 seconds
Started Aug 17 06:10:13 PM PDT 24
Finished Aug 17 06:10:14 PM PDT 24
Peak memory 207516 kb
Host smart-487a4ef6-007e-4a00-b58b-e1b313584420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39719
62476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3971962476
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2747396378
Short name T1051
Test name
Test status
Simulation time 175144533 ps
CPU time 0.86 seconds
Started Aug 17 06:10:07 PM PDT 24
Finished Aug 17 06:10:08 PM PDT 24
Peak memory 207540 kb
Host smart-689bc641-6c02-4bb0-a0ce-26f9fbc24e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27473
96378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2747396378
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3170747094
Short name T2027
Test name
Test status
Simulation time 146384208 ps
CPU time 0.89 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207540 kb
Host smart-47bd9978-22bb-4e79-9795-72e0c62eba87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31707
47094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3170747094
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3894953801
Short name T1981
Test name
Test status
Simulation time 201506815 ps
CPU time 0.99 seconds
Started Aug 17 06:10:05 PM PDT 24
Finished Aug 17 06:10:06 PM PDT 24
Peak memory 207576 kb
Host smart-ce1ddd8b-6629-4cae-9535-d82535a647e6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3894953801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3894953801
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.22033030
Short name T2231
Test name
Test status
Simulation time 166304312 ps
CPU time 0.86 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207396 kb
Host smart-a5243cdb-6d2e-4074-8138-9174ba492e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22033
030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.22033030
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.628919606
Short name T3134
Test name
Test status
Simulation time 48517413 ps
CPU time 0.7 seconds
Started Aug 17 06:10:13 PM PDT 24
Finished Aug 17 06:10:14 PM PDT 24
Peak memory 207512 kb
Host smart-3c509164-6b95-4f28-bf74-4c76c7dc6329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62891
9606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.628919606
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.514140351
Short name T2667
Test name
Test status
Simulation time 12149531272 ps
CPU time 33.14 seconds
Started Aug 17 06:10:10 PM PDT 24
Finished Aug 17 06:10:43 PM PDT 24
Peak memory 219792 kb
Host smart-a981c95f-50f3-42b7-96f3-399c4cb20679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51414
0351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.514140351
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3995772026
Short name T2617
Test name
Test status
Simulation time 177482750 ps
CPU time 0.92 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207552 kb
Host smart-78668750-60cd-404a-aa6d-229cd154ffe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39957
72026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3995772026
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.1148225335
Short name T2064
Test name
Test status
Simulation time 265577534 ps
CPU time 1.03 seconds
Started Aug 17 06:10:06 PM PDT 24
Finished Aug 17 06:10:07 PM PDT 24
Peak memory 207436 kb
Host smart-6c87df93-24de-4de6-8450-df31762b957c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11482
25335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1148225335
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.4240784358
Short name T1323
Test name
Test status
Simulation time 199820456 ps
CPU time 0.98 seconds
Started Aug 17 06:10:09 PM PDT 24
Finished Aug 17 06:10:10 PM PDT 24
Peak memory 207416 kb
Host smart-a37ee99c-5f62-47b7-8ea2-3318248a857d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42407
84358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.4240784358
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.3552275369
Short name T2440
Test name
Test status
Simulation time 175590020 ps
CPU time 0.9 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:10:13 PM PDT 24
Peak memory 207416 kb
Host smart-163501ce-6229-4ee3-851a-579b164f9ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35522
75369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.3552275369
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2595613045
Short name T3017
Test name
Test status
Simulation time 138305796 ps
CPU time 0.86 seconds
Started Aug 17 06:10:11 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 207456 kb
Host smart-7e3f7de0-eb21-472f-aeda-c03c13dff58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25956
13045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2595613045
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_rx_full.1181618501
Short name T2372
Test name
Test status
Simulation time 250419135 ps
CPU time 1.2 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:10:13 PM PDT 24
Peak memory 207464 kb
Host smart-c0c4acc1-cbf9-49ba-a455-6894783f2392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11816
18501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.1181618501
Directory /workspace/43.usbdev_rx_full/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2089841574
Short name T2283
Test name
Test status
Simulation time 155657917 ps
CPU time 0.88 seconds
Started Aug 17 06:10:13 PM PDT 24
Finished Aug 17 06:10:14 PM PDT 24
Peak memory 207480 kb
Host smart-49eb5117-a350-4154-9c41-2296c70b397a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
41574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2089841574
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.642218899
Short name T2144
Test name
Test status
Simulation time 146457061 ps
CPU time 0.86 seconds
Started Aug 17 06:10:13 PM PDT 24
Finished Aug 17 06:10:14 PM PDT 24
Peak memory 207512 kb
Host smart-c181b8a7-0163-4dfc-9e68-16e4f77a67a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64221
8899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.642218899
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.4161198905
Short name T2353
Test name
Test status
Simulation time 195063176 ps
CPU time 0.94 seconds
Started Aug 17 06:10:06 PM PDT 24
Finished Aug 17 06:10:07 PM PDT 24
Peak memory 207452 kb
Host smart-b0d23447-df43-4eb7-89c7-7780493ebe8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
98905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.4161198905
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1022363515
Short name T2603
Test name
Test status
Simulation time 3059843382 ps
CPU time 34.46 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 217588 kb
Host smart-6d6ef0bd-5d2b-43b2-93df-0b94eecc0a66
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1022363515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1022363515
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3854158622
Short name T3371
Test name
Test status
Simulation time 190689609 ps
CPU time 0.99 seconds
Started Aug 17 06:10:11 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 207420 kb
Host smart-908b3346-e237-4d58-b1eb-6c69d289bf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38541
58622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3854158622
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.722282989
Short name T1202
Test name
Test status
Simulation time 191123833 ps
CPU time 0.93 seconds
Started Aug 17 06:10:16 PM PDT 24
Finished Aug 17 06:10:17 PM PDT 24
Peak memory 207436 kb
Host smart-0a3cdb46-28b4-480a-bb3a-c982974d2e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72228
2989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.722282989
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.543348822
Short name T1877
Test name
Test status
Simulation time 304193654 ps
CPU time 1.2 seconds
Started Aug 17 06:10:07 PM PDT 24
Finished Aug 17 06:10:08 PM PDT 24
Peak memory 207516 kb
Host smart-fd44fd9e-c42b-472a-b9b1-5119c02a36e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54334
8822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.543348822
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3768101274
Short name T1434
Test name
Test status
Simulation time 3736220479 ps
CPU time 108.13 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:12:00 PM PDT 24
Peak memory 217436 kb
Host smart-667b2988-837f-43e2-9ef8-57d06fabe294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37681
01274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3768101274
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.3437976414
Short name T28
Test name
Test status
Simulation time 838265640 ps
CPU time 18.35 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:10:30 PM PDT 24
Peak memory 207680 kb
Host smart-f744a8e1-e6c0-48e8-aa1e-b5389b68b736
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437976414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.3437976414
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_tx_rx_disruption.4200346663
Short name T892
Test name
Test status
Simulation time 564518635 ps
CPU time 1.49 seconds
Started Aug 17 06:10:08 PM PDT 24
Finished Aug 17 06:10:09 PM PDT 24
Peak memory 207568 kb
Host smart-217905f0-735f-4936-85fa-67676dc1741b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200346663 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.usbdev_tx_rx_disruption.4200346663
Directory /workspace/43.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/430.usbdev_tx_rx_disruption.1988113159
Short name T1359
Test name
Test status
Simulation time 692698593 ps
CPU time 1.76 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 207544 kb
Host smart-d395c933-1d8d-4392-b8a5-a2a4a34b6491
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988113159 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 430.usbdev_tx_rx_disruption.1988113159
Directory /workspace/430.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/431.usbdev_tx_rx_disruption.557184427
Short name T2009
Test name
Test status
Simulation time 567694646 ps
CPU time 1.69 seconds
Started Aug 17 06:12:44 PM PDT 24
Finished Aug 17 06:12:46 PM PDT 24
Peak memory 207548 kb
Host smart-3ce52aa5-f03d-4cb8-ab99-d8e2436ec50b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557184427 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 431.usbdev_tx_rx_disruption.557184427
Directory /workspace/431.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/432.usbdev_tx_rx_disruption.2722327246
Short name T1992
Test name
Test status
Simulation time 523609931 ps
CPU time 1.57 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207568 kb
Host smart-5fb05106-57d3-4add-9cea-da5a2ce70153
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722327246 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 432.usbdev_tx_rx_disruption.2722327246
Directory /workspace/432.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/433.usbdev_tx_rx_disruption.3750921949
Short name T1638
Test name
Test status
Simulation time 497250306 ps
CPU time 1.58 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:12:43 PM PDT 24
Peak memory 207500 kb
Host smart-52230113-fa49-45ef-b1f8-d48096ce10d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750921949 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 433.usbdev_tx_rx_disruption.3750921949
Directory /workspace/433.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/434.usbdev_tx_rx_disruption.4217382942
Short name T3183
Test name
Test status
Simulation time 460333109 ps
CPU time 1.38 seconds
Started Aug 17 06:12:42 PM PDT 24
Finished Aug 17 06:12:44 PM PDT 24
Peak memory 207512 kb
Host smart-680b4563-ab31-4a9e-a047-d91aa201bcbb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217382942 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 434.usbdev_tx_rx_disruption.4217382942
Directory /workspace/434.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/435.usbdev_tx_rx_disruption.3484725873
Short name T1751
Test name
Test status
Simulation time 526674622 ps
CPU time 1.55 seconds
Started Aug 17 06:12:34 PM PDT 24
Finished Aug 17 06:12:36 PM PDT 24
Peak memory 207572 kb
Host smart-05f0f99e-60b7-45e1-be0e-d4afb0ccc103
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484725873 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 435.usbdev_tx_rx_disruption.3484725873
Directory /workspace/435.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/436.usbdev_tx_rx_disruption.3873071644
Short name T2365
Test name
Test status
Simulation time 524864047 ps
CPU time 1.73 seconds
Started Aug 17 06:12:36 PM PDT 24
Finished Aug 17 06:12:38 PM PDT 24
Peak memory 207488 kb
Host smart-5044ac60-dacf-45a0-9848-4e5291062ad4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873071644 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 436.usbdev_tx_rx_disruption.3873071644
Directory /workspace/436.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/437.usbdev_tx_rx_disruption.524031856
Short name T782
Test name
Test status
Simulation time 558331252 ps
CPU time 1.61 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207564 kb
Host smart-1893bed6-12ff-4326-95b3-94dace943c0b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524031856 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 437.usbdev_tx_rx_disruption.524031856
Directory /workspace/437.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/438.usbdev_tx_rx_disruption.984273814
Short name T582
Test name
Test status
Simulation time 649772296 ps
CPU time 1.75 seconds
Started Aug 17 06:12:26 PM PDT 24
Finished Aug 17 06:12:27 PM PDT 24
Peak memory 207552 kb
Host smart-e2cd3d17-057a-49a0-878c-971ee57fb536
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984273814 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 438.usbdev_tx_rx_disruption.984273814
Directory /workspace/438.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/439.usbdev_tx_rx_disruption.3220917857
Short name T2275
Test name
Test status
Simulation time 511342849 ps
CPU time 1.51 seconds
Started Aug 17 06:12:28 PM PDT 24
Finished Aug 17 06:12:30 PM PDT 24
Peak memory 207540 kb
Host smart-9e6cf3d2-c9d9-45ac-a10f-ccd69c3c4459
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220917857 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 439.usbdev_tx_rx_disruption.3220917857
Directory /workspace/439.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2885101901
Short name T2363
Test name
Test status
Simulation time 45517257 ps
CPU time 0.71 seconds
Started Aug 17 06:10:37 PM PDT 24
Finished Aug 17 06:10:38 PM PDT 24
Peak memory 207428 kb
Host smart-5fe38946-4100-4c4c-b9d9-e8af5f11268d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2885101901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2885101901
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.4106771443
Short name T3102
Test name
Test status
Simulation time 6800294196 ps
CPU time 8.77 seconds
Started Aug 17 06:10:11 PM PDT 24
Finished Aug 17 06:10:20 PM PDT 24
Peak memory 215932 kb
Host smart-98cdb462-6402-46be-9488-ff07569f6907
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106771443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.4106771443
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1947670955
Short name T2860
Test name
Test status
Simulation time 20314714982 ps
CPU time 24.08 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:10:37 PM PDT 24
Peak memory 207820 kb
Host smart-6c3c6925-3f2a-49a7-a331-69f55e8a9fe4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947670955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1947670955
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.1310243048
Short name T954
Test name
Test status
Simulation time 23808260559 ps
CPU time 37.15 seconds
Started Aug 17 06:10:12 PM PDT 24
Finished Aug 17 06:10:49 PM PDT 24
Peak memory 215972 kb
Host smart-02a60306-fe2f-4e5d-acb8-92632e7f3279
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310243048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.1310243048
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1159674620
Short name T937
Test name
Test status
Simulation time 159505188 ps
CPU time 0.89 seconds
Started Aug 17 06:10:07 PM PDT 24
Finished Aug 17 06:10:08 PM PDT 24
Peak memory 207456 kb
Host smart-78a14f4d-7a50-49f9-8b1b-f6907deed6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11596
74620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1159674620
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1401891541
Short name T2712
Test name
Test status
Simulation time 141196180 ps
CPU time 0.79 seconds
Started Aug 17 06:10:17 PM PDT 24
Finished Aug 17 06:10:18 PM PDT 24
Peak memory 207392 kb
Host smart-b0ca4fca-9db4-4de5-b7b3-2f5dbaeacd28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14018
91541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1401891541
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.3190680697
Short name T123
Test name
Test status
Simulation time 283596624 ps
CPU time 1.22 seconds
Started Aug 17 06:10:11 PM PDT 24
Finished Aug 17 06:10:12 PM PDT 24
Peak memory 207564 kb
Host smart-596d5937-9c89-4a75-812d-dd4f97fc6755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31906
80697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.3190680697
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.3308109871
Short name T1629
Test name
Test status
Simulation time 1104190489 ps
CPU time 2.89 seconds
Started Aug 17 06:10:20 PM PDT 24
Finished Aug 17 06:10:23 PM PDT 24
Peak memory 207776 kb
Host smart-00e1968d-401f-4edb-a96a-ea482f4f7b6e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3308109871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.3308109871
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.338571416
Short name T3000
Test name
Test status
Simulation time 39475937878 ps
CPU time 74.66 seconds
Started Aug 17 06:10:19 PM PDT 24
Finished Aug 17 06:11:34 PM PDT 24
Peak memory 207764 kb
Host smart-adfc9df2-810b-4a52-9894-f988ca86191e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33857
1416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.338571416
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.2983751434
Short name T2153
Test name
Test status
Simulation time 1151431309 ps
CPU time 25.81 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:49 PM PDT 24
Peak memory 207704 kb
Host smart-57e3b849-affa-44f5-9569-a317b8427112
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983751434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.2983751434
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.3168982362
Short name T2817
Test name
Test status
Simulation time 741886302 ps
CPU time 1.93 seconds
Started Aug 17 06:10:28 PM PDT 24
Finished Aug 17 06:10:30 PM PDT 24
Peak memory 207528 kb
Host smart-34761be4-14f1-42f6-a365-cc27dad749b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689
82362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.3168982362
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.1049184433
Short name T1082
Test name
Test status
Simulation time 148780434 ps
CPU time 0.84 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207500 kb
Host smart-2b781c41-5a5b-469c-bc28-76f0a23ebff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10491
84433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1049184433
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1424970419
Short name T1030
Test name
Test status
Simulation time 96266018 ps
CPU time 0.77 seconds
Started Aug 17 06:10:29 PM PDT 24
Finished Aug 17 06:10:30 PM PDT 24
Peak memory 207440 kb
Host smart-d23011cb-2dbb-45ce-acd1-38680cae5bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14249
70419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1424970419
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1067962236
Short name T3323
Test name
Test status
Simulation time 823819945 ps
CPU time 2.23 seconds
Started Aug 17 06:10:33 PM PDT 24
Finished Aug 17 06:10:35 PM PDT 24
Peak memory 207760 kb
Host smart-04fedc7b-7281-424f-8aaa-e9cd53554c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10679
62236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1067962236
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_types.2095169289
Short name T454
Test name
Test status
Simulation time 391525637 ps
CPU time 1.29 seconds
Started Aug 17 06:10:32 PM PDT 24
Finished Aug 17 06:10:33 PM PDT 24
Peak memory 207512 kb
Host smart-0f1c1842-32f7-407d-be57-f4f3b62fde87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2095169289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.2095169289
Directory /workspace/44.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2160959042
Short name T2813
Test name
Test status
Simulation time 220078696 ps
CPU time 1.57 seconds
Started Aug 17 06:10:11 PM PDT 24
Finished Aug 17 06:10:18 PM PDT 24
Peak memory 207636 kb
Host smart-c1d08e29-53c4-4630-972b-56b426289645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609
59042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2160959042
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3402265581
Short name T2608
Test name
Test status
Simulation time 204348764 ps
CPU time 1.05 seconds
Started Aug 17 06:10:22 PM PDT 24
Finished Aug 17 06:10:23 PM PDT 24
Peak memory 216840 kb
Host smart-2297e1ff-99d7-46a4-af5a-dbec853a3b4c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3402265581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3402265581
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1506298855
Short name T1390
Test name
Test status
Simulation time 135266092 ps
CPU time 0.84 seconds
Started Aug 17 06:10:30 PM PDT 24
Finished Aug 17 06:10:31 PM PDT 24
Peak memory 207428 kb
Host smart-a5af675d-c15c-4a64-aa3c-e4132f3c1e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15062
98855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1506298855
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.257808688
Short name T2545
Test name
Test status
Simulation time 223117601 ps
CPU time 1.03 seconds
Started Aug 17 06:10:27 PM PDT 24
Finished Aug 17 06:10:28 PM PDT 24
Peak memory 207488 kb
Host smart-883f3cdd-1ffc-49f5-805b-2a9960c0d43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25780
8688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.257808688
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.285932576
Short name T2711
Test name
Test status
Simulation time 3677518246 ps
CPU time 42.43 seconds
Started Aug 17 06:10:33 PM PDT 24
Finished Aug 17 06:11:16 PM PDT 24
Peak memory 218280 kb
Host smart-b77e6575-384d-481d-8a65-c88590129ca1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=285932576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.285932576
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2197247781
Short name T1522
Test name
Test status
Simulation time 194058871 ps
CPU time 0.93 seconds
Started Aug 17 06:10:27 PM PDT 24
Finished Aug 17 06:10:28 PM PDT 24
Peak memory 207528 kb
Host smart-5990b3d9-7bdb-4060-8a2d-3a5d54b617b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21972
47781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2197247781
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1435176380
Short name T1810
Test name
Test status
Simulation time 11432683043 ps
CPU time 16.11 seconds
Started Aug 17 06:10:22 PM PDT 24
Finished Aug 17 06:10:38 PM PDT 24
Peak memory 207744 kb
Host smart-f05d356a-cbf8-42fc-8cee-8ed1b54dd6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14351
76380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1435176380
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.968205724
Short name T3411
Test name
Test status
Simulation time 8371939027 ps
CPU time 11.06 seconds
Started Aug 17 06:10:21 PM PDT 24
Finished Aug 17 06:10:32 PM PDT 24
Peak memory 207756 kb
Host smart-daec2891-4c5a-4f73-b60c-ef5f964d8d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96820
5724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.968205724
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.3497725666
Short name T1370
Test name
Test status
Simulation time 3253526823 ps
CPU time 94.96 seconds
Started Aug 17 06:10:14 PM PDT 24
Finished Aug 17 06:11:50 PM PDT 24
Peak memory 218436 kb
Host smart-49c65cb4-c21d-4e27-9535-b766bd82557f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3497725666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.3497725666
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3340352756
Short name T3214
Test name
Test status
Simulation time 2490636578 ps
CPU time 25.71 seconds
Started Aug 17 06:10:20 PM PDT 24
Finished Aug 17 06:10:46 PM PDT 24
Peak memory 215836 kb
Host smart-3aed15cf-6c24-4b0e-81cd-29765276fbd4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3340352756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3340352756
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.3884944036
Short name T1115
Test name
Test status
Simulation time 237759076 ps
CPU time 0.99 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:24 PM PDT 24
Peak memory 207428 kb
Host smart-6e4127de-47bd-441c-b7d3-5025a9051fa3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3884944036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.3884944036
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3169388962
Short name T2297
Test name
Test status
Simulation time 206261945 ps
CPU time 0.97 seconds
Started Aug 17 06:10:33 PM PDT 24
Finished Aug 17 06:10:34 PM PDT 24
Peak memory 207472 kb
Host smart-5086d400-8e9e-4b5a-b935-71d2b9a3a357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31693
88962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3169388962
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.3119639717
Short name T882
Test name
Test status
Simulation time 3765838036 ps
CPU time 29.63 seconds
Started Aug 17 06:10:15 PM PDT 24
Finished Aug 17 06:10:45 PM PDT 24
Peak memory 217500 kb
Host smart-cb5e9d21-cc0e-4cd9-8f31-57d520316765
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3119639717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.3119639717
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1256150884
Short name T3583
Test name
Test status
Simulation time 159436578 ps
CPU time 0.87 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207436 kb
Host smart-41277d1e-d958-4223-944d-b90d7652b6a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1256150884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1256150884
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.439495427
Short name T2035
Test name
Test status
Simulation time 214361522 ps
CPU time 0.98 seconds
Started Aug 17 06:10:27 PM PDT 24
Finished Aug 17 06:10:28 PM PDT 24
Peak memory 207452 kb
Host smart-a869de3c-8b07-4f5d-b4e4-717b84160c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43949
5427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.439495427
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2491737615
Short name T135
Test name
Test status
Simulation time 192145559 ps
CPU time 0.91 seconds
Started Aug 17 06:10:20 PM PDT 24
Finished Aug 17 06:10:21 PM PDT 24
Peak memory 207500 kb
Host smart-05779f29-fe0c-4e03-9972-faa4da99649f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24917
37615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2491737615
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3780573667
Short name T2832
Test name
Test status
Simulation time 151674717 ps
CPU time 0.88 seconds
Started Aug 17 06:10:24 PM PDT 24
Finished Aug 17 06:10:25 PM PDT 24
Peak memory 207492 kb
Host smart-c0bee40f-a3be-4145-9f9b-59f1cbb322d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37805
73667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3780573667
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.633216190
Short name T1914
Test name
Test status
Simulation time 171781981 ps
CPU time 1 seconds
Started Aug 17 06:10:15 PM PDT 24
Finished Aug 17 06:10:16 PM PDT 24
Peak memory 207400 kb
Host smart-19815cbb-f140-4527-be8c-8d296e9bafe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63321
6190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.633216190
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.567639800
Short name T2531
Test name
Test status
Simulation time 153219569 ps
CPU time 0.88 seconds
Started Aug 17 06:10:18 PM PDT 24
Finished Aug 17 06:10:19 PM PDT 24
Peak memory 207560 kb
Host smart-bcfbe53e-f2b0-442e-aba3-6f47a77ebe7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56763
9800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.567639800
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1359163995
Short name T3131
Test name
Test status
Simulation time 159046793 ps
CPU time 0.85 seconds
Started Aug 17 06:10:22 PM PDT 24
Finished Aug 17 06:10:23 PM PDT 24
Peak memory 207560 kb
Host smart-d4cdfa37-7d5a-4f1c-ac28-1bfd825bde62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13591
63995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1359163995
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3113739042
Short name T3596
Test name
Test status
Simulation time 208878249 ps
CPU time 1.01 seconds
Started Aug 17 06:10:28 PM PDT 24
Finished Aug 17 06:10:29 PM PDT 24
Peak memory 207560 kb
Host smart-c3caa20d-6f76-411a-b582-d3c2581cf292
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3113739042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3113739042
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3739021087
Short name T2809
Test name
Test status
Simulation time 142203223 ps
CPU time 0.81 seconds
Started Aug 17 06:10:17 PM PDT 24
Finished Aug 17 06:10:18 PM PDT 24
Peak memory 207392 kb
Host smart-3c4f2c06-4441-43a5-ad99-4301841b9e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37390
21087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3739021087
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.981290658
Short name T2811
Test name
Test status
Simulation time 42256133 ps
CPU time 0.78 seconds
Started Aug 17 06:10:32 PM PDT 24
Finished Aug 17 06:10:33 PM PDT 24
Peak memory 207524 kb
Host smart-282f9293-7d79-4db8-be80-5e95ae8f0a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98129
0658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.981290658
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1817133967
Short name T3564
Test name
Test status
Simulation time 20063113414 ps
CPU time 49.81 seconds
Started Aug 17 06:10:24 PM PDT 24
Finished Aug 17 06:11:13 PM PDT 24
Peak memory 215956 kb
Host smart-f3cc0375-4b60-4d84-a394-4a1a79605bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18171
33967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1817133967
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3548709617
Short name T3509
Test name
Test status
Simulation time 156439904 ps
CPU time 0.91 seconds
Started Aug 17 06:10:31 PM PDT 24
Finished Aug 17 06:10:32 PM PDT 24
Peak memory 207560 kb
Host smart-5e91f8a3-9785-44b0-9d9b-75030cee1189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35487
09617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3548709617
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3527354374
Short name T925
Test name
Test status
Simulation time 229047488 ps
CPU time 0.98 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:24 PM PDT 24
Peak memory 207420 kb
Host smart-f3bbc3ad-d554-4aba-9f37-233b1fb6747d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35273
54374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3527354374
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2788123294
Short name T571
Test name
Test status
Simulation time 293183824 ps
CPU time 1.08 seconds
Started Aug 17 06:10:17 PM PDT 24
Finished Aug 17 06:10:18 PM PDT 24
Peak memory 207456 kb
Host smart-a8481bcd-0704-4ac8-a777-24a56000a0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27881
23294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2788123294
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.2346513106
Short name T1879
Test name
Test status
Simulation time 167766896 ps
CPU time 0.92 seconds
Started Aug 17 06:10:21 PM PDT 24
Finished Aug 17 06:10:22 PM PDT 24
Peak memory 207436 kb
Host smart-c4a28548-3cb4-40cc-8a53-57b9840f0dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
13106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.2346513106
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2588344035
Short name T2846
Test name
Test status
Simulation time 162363281 ps
CPU time 0.87 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207500 kb
Host smart-926b4489-1471-4f40-a79c-ed5cfb700be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883
44035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2588344035
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_rx_full.1185468135
Short name T1604
Test name
Test status
Simulation time 351968183 ps
CPU time 1.31 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207460 kb
Host smart-b378cc6a-ec12-4601-893e-c115cb4665d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11854
68135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.1185468135
Directory /workspace/44.usbdev_rx_full/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2354597407
Short name T1157
Test name
Test status
Simulation time 153189018 ps
CPU time 0.85 seconds
Started Aug 17 06:10:34 PM PDT 24
Finished Aug 17 06:10:35 PM PDT 24
Peak memory 207504 kb
Host smart-f457f9c0-be47-42cc-bc2b-c3200659c27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23545
97407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2354597407
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2442442560
Short name T2688
Test name
Test status
Simulation time 156432275 ps
CPU time 0.91 seconds
Started Aug 17 06:10:29 PM PDT 24
Finished Aug 17 06:10:30 PM PDT 24
Peak memory 207476 kb
Host smart-f724ba1f-f7fa-4490-95f6-fe4e5a4f9d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24424
42560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2442442560
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3009264935
Short name T1492
Test name
Test status
Simulation time 270549402 ps
CPU time 1.08 seconds
Started Aug 17 06:10:21 PM PDT 24
Finished Aug 17 06:10:22 PM PDT 24
Peak memory 207344 kb
Host smart-485422f9-b461-4fde-b006-9b71a69c0ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30092
64935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3009264935
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.734925747
Short name T2107
Test name
Test status
Simulation time 1658358314 ps
CPU time 17.8 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:41 PM PDT 24
Peak memory 217356 kb
Host smart-a807d9eb-3000-4b68-bd52-338a2098102b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=734925747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.734925747
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1475694500
Short name T1165
Test name
Test status
Simulation time 172768195 ps
CPU time 0.92 seconds
Started Aug 17 06:10:27 PM PDT 24
Finished Aug 17 06:10:28 PM PDT 24
Peak memory 207480 kb
Host smart-5c5a1c91-2b66-4aa1-826a-dc8606562ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14756
94500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1475694500
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1455238067
Short name T3281
Test name
Test status
Simulation time 210806565 ps
CPU time 0.94 seconds
Started Aug 17 06:10:31 PM PDT 24
Finished Aug 17 06:10:32 PM PDT 24
Peak memory 207556 kb
Host smart-5ef9de05-0e17-40ef-b687-09bf79a16c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14552
38067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1455238067
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2189742348
Short name T698
Test name
Test status
Simulation time 1114707874 ps
CPU time 2.78 seconds
Started Aug 17 06:10:24 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207768 kb
Host smart-f1e11d1c-2d2a-4741-8245-eed19e480627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21897
42348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2189742348
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.227478516
Short name T3359
Test name
Test status
Simulation time 3934730338 ps
CPU time 41.75 seconds
Started Aug 17 06:10:21 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 217688 kb
Host smart-0b5ed1ab-d8d3-48c0-81c5-6a8e2daead49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22747
8516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.227478516
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.1006773814
Short name T3299
Test name
Test status
Simulation time 2966130246 ps
CPU time 21.09 seconds
Started Aug 17 06:10:19 PM PDT 24
Finished Aug 17 06:10:41 PM PDT 24
Peak memory 207692 kb
Host smart-74f72aa4-01cf-4045-9def-aff8ca949bdc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006773814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.1006773814
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_tx_rx_disruption.2996907327
Short name T217
Test name
Test status
Simulation time 489530336 ps
CPU time 1.52 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207564 kb
Host smart-65b3ad3c-dc7e-4bef-9f77-0f98b0a82650
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996907327 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.usbdev_tx_rx_disruption.2996907327
Directory /workspace/44.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/440.usbdev_tx_rx_disruption.2011028249
Short name T1099
Test name
Test status
Simulation time 463386146 ps
CPU time 1.46 seconds
Started Aug 17 06:12:31 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207548 kb
Host smart-2f632a0b-d27b-43a2-9c1b-5def3ac5822d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011028249 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 440.usbdev_tx_rx_disruption.2011028249
Directory /workspace/440.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/441.usbdev_tx_rx_disruption.2793004940
Short name T187
Test name
Test status
Simulation time 586796736 ps
CPU time 1.57 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207560 kb
Host smart-74aea000-5f6d-462f-842d-8dae56a7f828
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793004940 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 441.usbdev_tx_rx_disruption.2793004940
Directory /workspace/441.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/442.usbdev_tx_rx_disruption.2907440925
Short name T550
Test name
Test status
Simulation time 681792895 ps
CPU time 1.81 seconds
Started Aug 17 06:12:46 PM PDT 24
Finished Aug 17 06:12:47 PM PDT 24
Peak memory 207544 kb
Host smart-4b93cd25-c307-43bf-b6f5-8b933ddcf8b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907440925 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 442.usbdev_tx_rx_disruption.2907440925
Directory /workspace/442.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/443.usbdev_tx_rx_disruption.1794401270
Short name T1517
Test name
Test status
Simulation time 490008844 ps
CPU time 1.47 seconds
Started Aug 17 06:12:42 PM PDT 24
Finished Aug 17 06:12:44 PM PDT 24
Peak memory 207600 kb
Host smart-785d8590-3593-48d1-b00b-8379910bdaac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794401270 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 443.usbdev_tx_rx_disruption.1794401270
Directory /workspace/443.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/444.usbdev_tx_rx_disruption.931288121
Short name T2252
Test name
Test status
Simulation time 602294704 ps
CPU time 1.57 seconds
Started Aug 17 06:12:29 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207564 kb
Host smart-d042b285-037b-4ebb-85b0-15d6cdc0af50
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931288121 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 444.usbdev_tx_rx_disruption.931288121
Directory /workspace/444.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/445.usbdev_tx_rx_disruption.1771262486
Short name T2957
Test name
Test status
Simulation time 644223700 ps
CPU time 1.74 seconds
Started Aug 17 06:12:24 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207492 kb
Host smart-85f0ef99-74f3-4471-a643-20a64e70ba12
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771262486 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 445.usbdev_tx_rx_disruption.1771262486
Directory /workspace/445.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/446.usbdev_tx_rx_disruption.2792625745
Short name T2145
Test name
Test status
Simulation time 549294975 ps
CPU time 1.67 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207520 kb
Host smart-39b6a4c0-0007-4cd8-b846-ae03d09f2091
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792625745 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 446.usbdev_tx_rx_disruption.2792625745
Directory /workspace/446.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/447.usbdev_tx_rx_disruption.3430805454
Short name T939
Test name
Test status
Simulation time 518749532 ps
CPU time 1.58 seconds
Started Aug 17 06:12:44 PM PDT 24
Finished Aug 17 06:12:45 PM PDT 24
Peak memory 207572 kb
Host smart-e0baf937-0dbd-47c6-8a37-fa953196658d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430805454 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 447.usbdev_tx_rx_disruption.3430805454
Directory /workspace/447.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/448.usbdev_tx_rx_disruption.2116555336
Short name T210
Test name
Test status
Simulation time 505755104 ps
CPU time 1.47 seconds
Started Aug 17 06:12:38 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 207496 kb
Host smart-8d8053fb-f99e-47af-9fb1-ad58bd3dd662
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116555336 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 448.usbdev_tx_rx_disruption.2116555336
Directory /workspace/448.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/449.usbdev_tx_rx_disruption.4044640691
Short name T1290
Test name
Test status
Simulation time 614337159 ps
CPU time 1.76 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 207516 kb
Host smart-3159b6bb-e3f3-4b59-a14e-260eaf20d4f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044640691 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 449.usbdev_tx_rx_disruption.4044640691
Directory /workspace/449.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.1123292597
Short name T3023
Test name
Test status
Simulation time 38914783 ps
CPU time 0.66 seconds
Started Aug 17 06:10:40 PM PDT 24
Finished Aug 17 06:10:41 PM PDT 24
Peak memory 207444 kb
Host smart-5ba9dc94-c48e-4b3a-a6f5-0edcdb088dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1123292597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.1123292597
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1633666727
Short name T2815
Test name
Test status
Simulation time 9389719689 ps
CPU time 12.61 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:36 PM PDT 24
Peak memory 207808 kb
Host smart-11b7900e-f1a8-4b2a-895f-0777eb5135a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633666727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.1633666727
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2815928144
Short name T3158
Test name
Test status
Simulation time 18834773090 ps
CPU time 24.56 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 207772 kb
Host smart-af0e2dc6-7e74-4ba6-983c-2fe9dd8b02af
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815928144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2815928144
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1168764471
Short name T2852
Test name
Test status
Simulation time 30999856285 ps
CPU time 39.72 seconds
Started Aug 17 06:10:27 PM PDT 24
Finished Aug 17 06:11:07 PM PDT 24
Peak memory 207772 kb
Host smart-b86bed6b-9459-4b8d-894a-e45bfaadb34a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168764471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.1168764471
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.4037834400
Short name T2642
Test name
Test status
Simulation time 177822029 ps
CPU time 0.93 seconds
Started Aug 17 06:10:31 PM PDT 24
Finished Aug 17 06:10:32 PM PDT 24
Peak memory 207460 kb
Host smart-14612e06-2503-423b-97f6-a2d09b74138c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40378
34400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.4037834400
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.456296853
Short name T1609
Test name
Test status
Simulation time 159042394 ps
CPU time 1.05 seconds
Started Aug 17 06:10:37 PM PDT 24
Finished Aug 17 06:10:38 PM PDT 24
Peak memory 207436 kb
Host smart-00c5bada-50d4-44f5-b957-21bb1dccf5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45629
6853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.456296853
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.1126410533
Short name T2971
Test name
Test status
Simulation time 243205659 ps
CPU time 1.14 seconds
Started Aug 17 06:10:27 PM PDT 24
Finished Aug 17 06:10:28 PM PDT 24
Peak memory 207528 kb
Host smart-eaf76470-1477-4312-a5a9-d53840e6817a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11264
10533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.1126410533
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3853077187
Short name T343
Test name
Test status
Simulation time 1288389654 ps
CPU time 3.13 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207636 kb
Host smart-3457cac0-89c9-4593-a82a-090742b078ff
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3853077187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3853077187
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.2428746939
Short name T1932
Test name
Test status
Simulation time 15822798441 ps
CPU time 24.86 seconds
Started Aug 17 06:10:19 PM PDT 24
Finished Aug 17 06:10:44 PM PDT 24
Peak memory 207792 kb
Host smart-9c25bb84-f8c4-4590-8384-6ea1cfda0170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24287
46939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2428746939
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.2069979026
Short name T1075
Test name
Test status
Simulation time 767133292 ps
CPU time 5.54 seconds
Started Aug 17 06:10:25 PM PDT 24
Finished Aug 17 06:10:31 PM PDT 24
Peak memory 207748 kb
Host smart-5bbb05da-275b-4878-a58a-df4c56c7d9a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069979026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.2069979026
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.4106770161
Short name T2380
Test name
Test status
Simulation time 708687413 ps
CPU time 1.98 seconds
Started Aug 17 06:10:27 PM PDT 24
Finished Aug 17 06:10:29 PM PDT 24
Peak memory 207528 kb
Host smart-270e45c7-feb1-4d41-85c9-ad8c2d4e4f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41067
70161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.4106770161
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2859139851
Short name T1674
Test name
Test status
Simulation time 189503195 ps
CPU time 0.86 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207508 kb
Host smart-18d23740-d394-4502-81ed-00db57b07371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28591
39851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2859139851
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1493462141
Short name T1235
Test name
Test status
Simulation time 57019988 ps
CPU time 0.77 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:26 PM PDT 24
Peak memory 207428 kb
Host smart-8ba831c1-5c93-461f-a409-c09e258fc909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14934
62141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1493462141
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.994711787
Short name T1367
Test name
Test status
Simulation time 899710892 ps
CPU time 2.38 seconds
Started Aug 17 06:10:33 PM PDT 24
Finished Aug 17 06:10:35 PM PDT 24
Peak memory 207744 kb
Host smart-983cc591-92b3-4aa4-a94f-61d8e93b8ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99471
1787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.994711787
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_types.3828850119
Short name T470
Test name
Test status
Simulation time 493132639 ps
CPU time 1.35 seconds
Started Aug 17 06:10:20 PM PDT 24
Finished Aug 17 06:10:22 PM PDT 24
Peak memory 207576 kb
Host smart-5e4f3777-729f-4e0f-a426-5520570dd3d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3828850119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.3828850119
Directory /workspace/45.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.865013403
Short name T2692
Test name
Test status
Simulation time 282979524 ps
CPU time 2.47 seconds
Started Aug 17 06:10:28 PM PDT 24
Finished Aug 17 06:10:31 PM PDT 24
Peak memory 207644 kb
Host smart-8670d880-01ac-4352-997a-b0e653eb0210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86501
3403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.865013403
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.962562446
Short name T3292
Test name
Test status
Simulation time 223261360 ps
CPU time 1.12 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:28 PM PDT 24
Peak memory 215856 kb
Host smart-03693266-d6be-4f3c-aeaf-d9bda3da886a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=962562446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.962562446
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2014680472
Short name T3623
Test name
Test status
Simulation time 144730119 ps
CPU time 0.82 seconds
Started Aug 17 06:10:28 PM PDT 24
Finished Aug 17 06:10:29 PM PDT 24
Peak memory 207432 kb
Host smart-a5db0c44-f9ec-4ccd-be38-a698dcc05610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20146
80472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2014680472
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.79094970
Short name T3253
Test name
Test status
Simulation time 167612153 ps
CPU time 0.92 seconds
Started Aug 17 06:10:25 PM PDT 24
Finished Aug 17 06:10:26 PM PDT 24
Peak memory 207488 kb
Host smart-1134b16e-aa06-4229-8a0b-6c544dc5dc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79094
970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.79094970
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2842621555
Short name T1565
Test name
Test status
Simulation time 2459471397 ps
CPU time 18.81 seconds
Started Aug 17 06:10:31 PM PDT 24
Finished Aug 17 06:10:50 PM PDT 24
Peak memory 224132 kb
Host smart-45f025fa-32b3-4998-9d0a-1641b7f13967
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2842621555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2842621555
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.3254196582
Short name T1243
Test name
Test status
Simulation time 12224861174 ps
CPU time 147.9 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:12:54 PM PDT 24
Peak memory 207784 kb
Host smart-21f5c134-dd90-4963-b989-f9be1ae72050
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3254196582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.3254196582
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2030150505
Short name T2780
Test name
Test status
Simulation time 218295187 ps
CPU time 1.03 seconds
Started Aug 17 06:10:22 PM PDT 24
Finished Aug 17 06:10:23 PM PDT 24
Peak memory 207532 kb
Host smart-70ab93df-cabd-490f-897c-2395270866c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20301
50505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2030150505
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.145524088
Short name T1063
Test name
Test status
Simulation time 24338842280 ps
CPU time 40.58 seconds
Started Aug 17 06:10:35 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207576 kb
Host smart-385203db-6994-4ea9-acb9-1732ef4fff2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14552
4088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.145524088
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3631380292
Short name T1240
Test name
Test status
Simulation time 3768221339 ps
CPU time 6.14 seconds
Started Aug 17 06:10:32 PM PDT 24
Finished Aug 17 06:10:38 PM PDT 24
Peak memory 216044 kb
Host smart-70fae8d1-5e5b-4b5b-82da-ef2735597f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36313
80292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3631380292
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.3332918867
Short name T1421
Test name
Test status
Simulation time 3613819609 ps
CPU time 37.08 seconds
Started Aug 17 06:10:29 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 224176 kb
Host smart-b4e41937-072e-4b0b-844a-21a0ac746862
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3332918867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.3332918867
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3701531057
Short name T1551
Test name
Test status
Simulation time 4351317930 ps
CPU time 128.35 seconds
Started Aug 17 06:10:24 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 217300 kb
Host smart-bef253c6-3977-4cb0-9e5f-69e0eb300444
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3701531057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3701531057
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.1669424382
Short name T2702
Test name
Test status
Simulation time 262791814 ps
CPU time 1.1 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:24 PM PDT 24
Peak memory 207408 kb
Host smart-8fc20936-9034-4682-a561-c041e8557bb4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1669424382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.1669424382
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2346760505
Short name T787
Test name
Test status
Simulation time 218045654 ps
CPU time 0.98 seconds
Started Aug 17 06:10:21 PM PDT 24
Finished Aug 17 06:10:22 PM PDT 24
Peak memory 207424 kb
Host smart-d5055a1e-8b76-45f1-8176-abe4f702a17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23467
60505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2346760505
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3455766007
Short name T3236
Test name
Test status
Simulation time 3869906251 ps
CPU time 39.05 seconds
Started Aug 17 06:10:30 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 217452 kb
Host smart-eddd5ffb-ae53-4b85-822d-b9580a1671a8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3455766007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3455766007
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.742628964
Short name T573
Test name
Test status
Simulation time 177921490 ps
CPU time 0.9 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207456 kb
Host smart-6464d334-129b-4ae0-8668-bf3231c296d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=742628964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.742628964
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1865628995
Short name T3631
Test name
Test status
Simulation time 144988365 ps
CPU time 0.87 seconds
Started Aug 17 06:10:29 PM PDT 24
Finished Aug 17 06:10:30 PM PDT 24
Peak memory 207480 kb
Host smart-bf499410-4eb0-487b-a1e0-26be3cccfbb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18656
28995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1865628995
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3504686756
Short name T1828
Test name
Test status
Simulation time 211310374 ps
CPU time 0.97 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:24 PM PDT 24
Peak memory 207484 kb
Host smart-cb680f7c-0359-46a9-9267-a7e6bbe65bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35046
86756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3504686756
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.4220655531
Short name T131
Test name
Test status
Simulation time 229419347 ps
CPU time 1 seconds
Started Aug 17 06:10:33 PM PDT 24
Finished Aug 17 06:10:34 PM PDT 24
Peak memory 207428 kb
Host smart-84a9b6d3-37bd-406e-b581-7d02f42b796f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42206
55531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.4220655531
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.816286484
Short name T1750
Test name
Test status
Simulation time 209157290 ps
CPU time 0.91 seconds
Started Aug 17 06:10:22 PM PDT 24
Finished Aug 17 06:10:23 PM PDT 24
Peak memory 207472 kb
Host smart-fbec3476-80d4-402a-b295-e56324233ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81628
6484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.816286484
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.4237085182
Short name T2929
Test name
Test status
Simulation time 170231039 ps
CPU time 0.83 seconds
Started Aug 17 06:10:23 PM PDT 24
Finished Aug 17 06:10:24 PM PDT 24
Peak memory 207564 kb
Host smart-09a07705-217d-4c04-873c-9405db1f54da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42370
85182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.4237085182
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1380722244
Short name T3273
Test name
Test status
Simulation time 153162435 ps
CPU time 0.86 seconds
Started Aug 17 06:10:26 PM PDT 24
Finished Aug 17 06:10:27 PM PDT 24
Peak memory 207536 kb
Host smart-e51de238-6d9c-4482-9f3a-1d7428539141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13807
22244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1380722244
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3933699771
Short name T853
Test name
Test status
Simulation time 195054345 ps
CPU time 1 seconds
Started Aug 17 06:10:35 PM PDT 24
Finished Aug 17 06:10:37 PM PDT 24
Peak memory 207560 kb
Host smart-7442d261-1ab8-46bf-ace5-8d5c7c48d8e2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3933699771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3933699771
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.635418590
Short name T1738
Test name
Test status
Simulation time 176572957 ps
CPU time 0.86 seconds
Started Aug 17 06:10:33 PM PDT 24
Finished Aug 17 06:10:34 PM PDT 24
Peak memory 207436 kb
Host smart-ad6818f1-af65-4173-a7fd-616ea4286098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63541
8590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.635418590
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.515417128
Short name T2322
Test name
Test status
Simulation time 111648036 ps
CPU time 0.79 seconds
Started Aug 17 06:10:25 PM PDT 24
Finished Aug 17 06:10:25 PM PDT 24
Peak memory 207500 kb
Host smart-19d7e9aa-602a-470a-bd4b-eec6fb272a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51541
7128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.515417128
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1703714635
Short name T2631
Test name
Test status
Simulation time 11700725164 ps
CPU time 28.6 seconds
Started Aug 17 06:10:27 PM PDT 24
Finished Aug 17 06:10:56 PM PDT 24
Peak memory 215928 kb
Host smart-02636ced-5c2f-437e-8e49-7c185394335e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17037
14635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1703714635
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3611146810
Short name T2316
Test name
Test status
Simulation time 205984270 ps
CPU time 1 seconds
Started Aug 17 06:10:35 PM PDT 24
Finished Aug 17 06:10:36 PM PDT 24
Peak memory 207560 kb
Host smart-a04f5514-5d5f-444b-bdc4-08fde80714ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36111
46810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3611146810
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2407332979
Short name T816
Test name
Test status
Simulation time 231296122 ps
CPU time 1.04 seconds
Started Aug 17 06:10:43 PM PDT 24
Finished Aug 17 06:10:44 PM PDT 24
Peak memory 207428 kb
Host smart-fe361772-ee84-466e-81d3-958270749e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
32979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2407332979
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.2402901983
Short name T2317
Test name
Test status
Simulation time 196639197 ps
CPU time 0.94 seconds
Started Aug 17 06:10:36 PM PDT 24
Finished Aug 17 06:10:37 PM PDT 24
Peak memory 207380 kb
Host smart-a6584abe-80a6-4c17-9624-265b20e525ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029
01983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2402901983
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.378421972
Short name T1739
Test name
Test status
Simulation time 187586718 ps
CPU time 0.9 seconds
Started Aug 17 06:10:37 PM PDT 24
Finished Aug 17 06:10:38 PM PDT 24
Peak memory 207444 kb
Host smart-544c20b4-2be8-4918-8d92-29633e03277e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37842
1972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.378421972
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.3092786167
Short name T832
Test name
Test status
Simulation time 158324779 ps
CPU time 0.88 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207456 kb
Host smart-a739d508-f082-434a-8dfd-b72f29e059c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30927
86167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.3092786167
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_rx_full.1787397860
Short name T3238
Test name
Test status
Simulation time 282866632 ps
CPU time 1.13 seconds
Started Aug 17 06:10:32 PM PDT 24
Finished Aug 17 06:10:33 PM PDT 24
Peak memory 207428 kb
Host smart-56ba3fab-69e1-4bec-a0d0-ed27b6497b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17873
97860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.1787397860
Directory /workspace/45.usbdev_rx_full/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3521444951
Short name T763
Test name
Test status
Simulation time 150048089 ps
CPU time 0.82 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207532 kb
Host smart-8ba79414-694e-4834-b08c-5933249971d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35214
44951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3521444951
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.112346526
Short name T2802
Test name
Test status
Simulation time 154261319 ps
CPU time 0.84 seconds
Started Aug 17 06:10:33 PM PDT 24
Finished Aug 17 06:10:34 PM PDT 24
Peak memory 207560 kb
Host smart-062a6aa8-0d4d-4918-ae37-5c0e431e0836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11234
6526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.112346526
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1222793044
Short name T2262
Test name
Test status
Simulation time 227713763 ps
CPU time 1.07 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207456 kb
Host smart-24f25057-4dd2-4dc8-b405-26895080d628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12227
93044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1222793044
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3919323439
Short name T1902
Test name
Test status
Simulation time 2543552454 ps
CPU time 20.9 seconds
Started Aug 17 06:10:28 PM PDT 24
Finished Aug 17 06:10:49 PM PDT 24
Peak memory 216680 kb
Host smart-6b4ae2af-c091-4bcf-8082-cff3a4f6fa68
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3919323439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3919323439
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1667757987
Short name T2821
Test name
Test status
Simulation time 164681102 ps
CPU time 0.87 seconds
Started Aug 17 06:10:32 PM PDT 24
Finished Aug 17 06:10:33 PM PDT 24
Peak memory 207476 kb
Host smart-06ba5586-44ef-48b5-b7e4-9936de4fd278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16677
57987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1667757987
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2908473403
Short name T1626
Test name
Test status
Simulation time 148977315 ps
CPU time 0.87 seconds
Started Aug 17 06:10:39 PM PDT 24
Finished Aug 17 06:10:40 PM PDT 24
Peak memory 207560 kb
Host smart-c7dce1d2-ebbb-43bd-b49f-ba8307d0f60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29084
73403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2908473403
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.3331486024
Short name T1288
Test name
Test status
Simulation time 1332457479 ps
CPU time 3.53 seconds
Started Aug 17 06:10:27 PM PDT 24
Finished Aug 17 06:10:31 PM PDT 24
Peak memory 207704 kb
Host smart-3566d9f2-6cf1-48bf-bcd4-9e2c40bb32ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33314
86024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.3331486024
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1357703204
Short name T1903
Test name
Test status
Simulation time 3175964958 ps
CPU time 98.37 seconds
Started Aug 17 06:10:35 PM PDT 24
Finished Aug 17 06:12:14 PM PDT 24
Peak memory 217404 kb
Host smart-f5c34acd-c9a9-47af-b45a-17a6845089ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13577
03204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1357703204
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.3273608661
Short name T1335
Test name
Test status
Simulation time 3133622960 ps
CPU time 21.2 seconds
Started Aug 17 06:10:31 PM PDT 24
Finished Aug 17 06:10:52 PM PDT 24
Peak memory 207720 kb
Host smart-1ea8ed5d-df3f-4255-b592-3aaaef3cecae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273608661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.3273608661
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_tx_rx_disruption.1543751049
Short name T1511
Test name
Test status
Simulation time 549595076 ps
CPU time 1.57 seconds
Started Aug 17 06:10:37 PM PDT 24
Finished Aug 17 06:10:38 PM PDT 24
Peak memory 207568 kb
Host smart-595f2f00-6cbc-481a-98ff-dbe1b16258eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543751049 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.usbdev_tx_rx_disruption.1543751049
Directory /workspace/45.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/450.usbdev_tx_rx_disruption.2611709074
Short name T3197
Test name
Test status
Simulation time 482767679 ps
CPU time 1.52 seconds
Started Aug 17 06:12:25 PM PDT 24
Finished Aug 17 06:12:27 PM PDT 24
Peak memory 207544 kb
Host smart-da53472f-f93b-4dad-85a9-3ef4837c0402
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611709074 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 450.usbdev_tx_rx_disruption.2611709074
Directory /workspace/450.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/451.usbdev_tx_rx_disruption.1475200632
Short name T1555
Test name
Test status
Simulation time 465132271 ps
CPU time 1.59 seconds
Started Aug 17 06:12:36 PM PDT 24
Finished Aug 17 06:12:38 PM PDT 24
Peak memory 207484 kb
Host smart-5102f466-febb-476a-ada5-c2559d629fe7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475200632 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 451.usbdev_tx_rx_disruption.1475200632
Directory /workspace/451.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/452.usbdev_tx_rx_disruption.1912071599
Short name T2956
Test name
Test status
Simulation time 577928272 ps
CPU time 1.67 seconds
Started Aug 17 06:12:32 PM PDT 24
Finished Aug 17 06:12:33 PM PDT 24
Peak memory 207504 kb
Host smart-cd40939a-dcb2-4e65-96af-1b9008358899
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912071599 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 452.usbdev_tx_rx_disruption.1912071599
Directory /workspace/452.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/453.usbdev_tx_rx_disruption.933168083
Short name T1923
Test name
Test status
Simulation time 480896874 ps
CPU time 1.48 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 207580 kb
Host smart-4dce8ab0-0cda-4750-98b6-204fdb580419
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933168083 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 453.usbdev_tx_rx_disruption.933168083
Directory /workspace/453.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/454.usbdev_tx_rx_disruption.3788113080
Short name T2708
Test name
Test status
Simulation time 548715039 ps
CPU time 1.59 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207512 kb
Host smart-d527af9b-980c-4388-b6ce-5f401a4ae7a7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788113080 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 454.usbdev_tx_rx_disruption.3788113080
Directory /workspace/454.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/455.usbdev_tx_rx_disruption.2540882494
Short name T2125
Test name
Test status
Simulation time 619257662 ps
CPU time 1.66 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 207472 kb
Host smart-a6628734-5ee8-4106-a3e3-01ae0d81c018
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540882494 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 455.usbdev_tx_rx_disruption.2540882494
Directory /workspace/455.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/456.usbdev_tx_rx_disruption.2073802206
Short name T676
Test name
Test status
Simulation time 600934308 ps
CPU time 1.57 seconds
Started Aug 17 06:12:42 PM PDT 24
Finished Aug 17 06:12:43 PM PDT 24
Peak memory 207496 kb
Host smart-902bc455-dab5-4e7d-9197-7d40f5d694fb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073802206 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 456.usbdev_tx_rx_disruption.2073802206
Directory /workspace/456.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/457.usbdev_tx_rx_disruption.1735680979
Short name T737
Test name
Test status
Simulation time 458884849 ps
CPU time 1.47 seconds
Started Aug 17 06:12:43 PM PDT 24
Finished Aug 17 06:12:45 PM PDT 24
Peak memory 207484 kb
Host smart-b100a340-a44b-40da-9fdd-6d646a3811f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735680979 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 457.usbdev_tx_rx_disruption.1735680979
Directory /workspace/457.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/458.usbdev_tx_rx_disruption.1941505016
Short name T1171
Test name
Test status
Simulation time 660594490 ps
CPU time 1.96 seconds
Started Aug 17 06:12:23 PM PDT 24
Finished Aug 17 06:12:25 PM PDT 24
Peak memory 207532 kb
Host smart-06810afd-7340-4ead-9e57-5bca6eb62ea7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941505016 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 458.usbdev_tx_rx_disruption.1941505016
Directory /workspace/458.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/459.usbdev_tx_rx_disruption.204631132
Short name T180
Test name
Test status
Simulation time 432343873 ps
CPU time 1.43 seconds
Started Aug 17 06:12:25 PM PDT 24
Finished Aug 17 06:12:26 PM PDT 24
Peak memory 207556 kb
Host smart-3ab225be-9d05-4da9-9e64-4d5d2866486c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204631132 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 459.usbdev_tx_rx_disruption.204631132
Directory /workspace/459.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.2997577826
Short name T1475
Test name
Test status
Simulation time 43842192 ps
CPU time 0.69 seconds
Started Aug 17 06:10:56 PM PDT 24
Finished Aug 17 06:10:57 PM PDT 24
Peak memory 207360 kb
Host smart-a8a48cfd-5fe6-4305-a865-9876f25a3ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2997577826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2997577826
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1123544794
Short name T803
Test name
Test status
Simulation time 4360367090 ps
CPU time 6.7 seconds
Started Aug 17 06:10:41 PM PDT 24
Finished Aug 17 06:10:48 PM PDT 24
Peak memory 215956 kb
Host smart-85c4c96c-9f2d-406b-9e11-d45540b44ffb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123544794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.1123544794
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.646736619
Short name T3604
Test name
Test status
Simulation time 14834884224 ps
CPU time 17.46 seconds
Started Aug 17 06:10:28 PM PDT 24
Finished Aug 17 06:10:46 PM PDT 24
Peak memory 215976 kb
Host smart-b6ed4255-d3bf-4a84-b774-75b2dca37efd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=646736619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.646736619
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.1475979212
Short name T1793
Test name
Test status
Simulation time 30854498993 ps
CPU time 42.01 seconds
Started Aug 17 06:10:31 PM PDT 24
Finished Aug 17 06:11:13 PM PDT 24
Peak memory 207748 kb
Host smart-55ef6dc0-7c22-4fe2-8ca4-deb8db6d1517
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475979212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.1475979212
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3621153789
Short name T1112
Test name
Test status
Simulation time 170278811 ps
CPU time 0.85 seconds
Started Aug 17 06:10:35 PM PDT 24
Finished Aug 17 06:10:36 PM PDT 24
Peak memory 207472 kb
Host smart-68e44efd-9248-4463-a72a-1eacd7e46617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36211
53789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3621153789
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3890483499
Short name T1749
Test name
Test status
Simulation time 166597139 ps
CPU time 0.87 seconds
Started Aug 17 06:10:36 PM PDT 24
Finished Aug 17 06:10:37 PM PDT 24
Peak memory 207520 kb
Host smart-6205b0a2-b964-4e98-b211-bcef65794667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38904
83499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3890483499
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3910059463
Short name T3145
Test name
Test status
Simulation time 243094106 ps
CPU time 1.06 seconds
Started Aug 17 06:10:28 PM PDT 24
Finished Aug 17 06:10:29 PM PDT 24
Peak memory 207560 kb
Host smart-c4a47cf9-96d3-44bd-92c4-ef4a66f07ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39100
59463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3910059463
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1695649863
Short name T3396
Test name
Test status
Simulation time 394199994 ps
CPU time 1.36 seconds
Started Aug 17 06:10:43 PM PDT 24
Finished Aug 17 06:10:44 PM PDT 24
Peak memory 207460 kb
Host smart-4908696a-c4e9-46b8-83b7-38f97954290d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1695649863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1695649863
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.1120644893
Short name T2475
Test name
Test status
Simulation time 47934536866 ps
CPU time 90.82 seconds
Started Aug 17 06:10:40 PM PDT 24
Finished Aug 17 06:12:11 PM PDT 24
Peak memory 207784 kb
Host smart-c07dfc25-63b9-4bd4-805c-c57932619382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11206
44893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.1120644893
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.4139116844
Short name T1270
Test name
Test status
Simulation time 1049918483 ps
CPU time 22.81 seconds
Started Aug 17 06:10:29 PM PDT 24
Finished Aug 17 06:10:52 PM PDT 24
Peak memory 207684 kb
Host smart-32b567d7-dfbe-4616-a449-98fc9630d9b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139116844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.4139116844
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.23109841
Short name T1655
Test name
Test status
Simulation time 839473765 ps
CPU time 2.03 seconds
Started Aug 17 06:10:39 PM PDT 24
Finished Aug 17 06:10:41 PM PDT 24
Peak memory 207552 kb
Host smart-9bf7a7ad-d877-45d5-8a28-0bc8459954a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23109
841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.23109841
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1604418778
Short name T2849
Test name
Test status
Simulation time 174478992 ps
CPU time 0.85 seconds
Started Aug 17 06:10:32 PM PDT 24
Finished Aug 17 06:10:33 PM PDT 24
Peak memory 207516 kb
Host smart-0827f427-311e-4096-b5fd-110e9e39fc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16044
18778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1604418778
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.913877836
Short name T2028
Test name
Test status
Simulation time 35322332 ps
CPU time 0.71 seconds
Started Aug 17 06:10:35 PM PDT 24
Finished Aug 17 06:10:35 PM PDT 24
Peak memory 207428 kb
Host smart-04aad534-b518-4777-88b8-4d872d6c1c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91387
7836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.913877836
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.650389164
Short name T1464
Test name
Test status
Simulation time 742882452 ps
CPU time 2.28 seconds
Started Aug 17 06:10:29 PM PDT 24
Finished Aug 17 06:10:31 PM PDT 24
Peak memory 207708 kb
Host smart-ecee4f71-2545-44f6-9297-b6bde02d7e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65038
9164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.650389164
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_types.2626255570
Short name T2978
Test name
Test status
Simulation time 459298067 ps
CPU time 1.42 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:40 PM PDT 24
Peak memory 207488 kb
Host smart-22215920-4a08-4272-a621-3adba7894cd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2626255570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.2626255570
Directory /workspace/46.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1407460012
Short name T593
Test name
Test status
Simulation time 221939851 ps
CPU time 1.72 seconds
Started Aug 17 06:10:42 PM PDT 24
Finished Aug 17 06:10:44 PM PDT 24
Peak memory 207652 kb
Host smart-36e68050-0c83-44b2-a03b-0fe46f2caca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14074
60012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1407460012
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3529315105
Short name T976
Test name
Test status
Simulation time 201600748 ps
CPU time 1.03 seconds
Started Aug 17 06:10:39 PM PDT 24
Finished Aug 17 06:10:40 PM PDT 24
Peak memory 215848 kb
Host smart-e7c8faa9-4b79-431c-8d37-cc11b9f752ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3529315105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3529315105
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1541683057
Short name T3168
Test name
Test status
Simulation time 203885803 ps
CPU time 0.96 seconds
Started Aug 17 06:10:37 PM PDT 24
Finished Aug 17 06:10:38 PM PDT 24
Peak memory 207340 kb
Host smart-ee1edb75-3038-483e-8ace-4a846f0ac8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416
83057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1541683057
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2834249769
Short name T2589
Test name
Test status
Simulation time 238664843 ps
CPU time 1 seconds
Started Aug 17 06:10:37 PM PDT 24
Finished Aug 17 06:10:38 PM PDT 24
Peak memory 207452 kb
Host smart-0fe8bff8-51d5-494d-89a5-d953296f0a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28342
49769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2834249769
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3757200370
Short name T2054
Test name
Test status
Simulation time 3370160259 ps
CPU time 26.58 seconds
Started Aug 17 06:10:35 PM PDT 24
Finished Aug 17 06:11:02 PM PDT 24
Peak memory 224160 kb
Host smart-8c4a3d3e-7b32-4fe6-936b-71712e2ca7b9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3757200370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3757200370
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.3455477374
Short name T539
Test name
Test status
Simulation time 3611464273 ps
CPU time 45.35 seconds
Started Aug 17 06:10:31 PM PDT 24
Finished Aug 17 06:11:16 PM PDT 24
Peak memory 207712 kb
Host smart-3c602103-bc22-45e5-9aa8-9fda1bdf72da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3455477374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.3455477374
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.224920835
Short name T777
Test name
Test status
Simulation time 229943352 ps
CPU time 1.02 seconds
Started Aug 17 06:10:36 PM PDT 24
Finished Aug 17 06:10:37 PM PDT 24
Peak memory 207468 kb
Host smart-2de416af-00a8-4586-b31d-e69925f459d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22492
0835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.224920835
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.1318267765
Short name T1457
Test name
Test status
Simulation time 13873170206 ps
CPU time 20.98 seconds
Started Aug 17 06:10:32 PM PDT 24
Finished Aug 17 06:10:54 PM PDT 24
Peak memory 207796 kb
Host smart-cd898cb6-edb0-4cd7-85e0-054c3f02cda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13182
67765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.1318267765
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.289801880
Short name T3121
Test name
Test status
Simulation time 10909852090 ps
CPU time 14.48 seconds
Started Aug 17 06:10:37 PM PDT 24
Finished Aug 17 06:10:51 PM PDT 24
Peak memory 207768 kb
Host smart-f93467a4-cce1-40fe-a1d2-903bf8eaea5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28980
1880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.289801880
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2584415672
Short name T3240
Test name
Test status
Simulation time 4852386727 ps
CPU time 51.25 seconds
Started Aug 17 06:10:29 PM PDT 24
Finished Aug 17 06:11:20 PM PDT 24
Peak memory 218264 kb
Host smart-38f98d97-09fa-4b25-a365-2a0b0b7ee21a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2584415672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2584415672
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3198163951
Short name T974
Test name
Test status
Simulation time 2002145459 ps
CPU time 58.01 seconds
Started Aug 17 06:10:40 PM PDT 24
Finished Aug 17 06:11:38 PM PDT 24
Peak memory 215816 kb
Host smart-59c8b930-48bc-4639-9792-51c2fac5e0e9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3198163951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3198163951
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3164142312
Short name T2434
Test name
Test status
Simulation time 270439280 ps
CPU time 1.03 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:10:56 PM PDT 24
Peak memory 207448 kb
Host smart-a8eec5c6-0fe0-4504-ae01-cd0be9124603
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3164142312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3164142312
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.948381482
Short name T671
Test name
Test status
Simulation time 268367836 ps
CPU time 1.07 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207464 kb
Host smart-eed97a11-3297-46b1-9ee7-7556ee26f128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94838
1482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.948381482
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.796423605
Short name T697
Test name
Test status
Simulation time 1974132889 ps
CPU time 20.15 seconds
Started Aug 17 06:10:39 PM PDT 24
Finished Aug 17 06:10:59 PM PDT 24
Peak memory 215880 kb
Host smart-ff1ac364-3229-43b0-aa4f-29c75aee93aa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=796423605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.796423605
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1337893998
Short name T1983
Test name
Test status
Simulation time 165497793 ps
CPU time 0.91 seconds
Started Aug 17 06:10:31 PM PDT 24
Finished Aug 17 06:10:32 PM PDT 24
Peak memory 207408 kb
Host smart-d82bbe40-436a-40e5-b881-c3979c71b76c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1337893998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1337893998
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.281740375
Short name T3502
Test name
Test status
Simulation time 140628863 ps
CPU time 0.86 seconds
Started Aug 17 06:10:39 PM PDT 24
Finished Aug 17 06:10:40 PM PDT 24
Peak memory 207468 kb
Host smart-4f44f44c-1697-4549-b6cc-347c2df5c618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28174
0375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.281740375
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2611644740
Short name T2431
Test name
Test status
Simulation time 210253733 ps
CPU time 0.97 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207684 kb
Host smart-16a2e401-b194-4a9d-896a-384fd4763593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
44740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2611644740
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2640051334
Short name T1035
Test name
Test status
Simulation time 164181773 ps
CPU time 0.85 seconds
Started Aug 17 06:10:41 PM PDT 24
Finished Aug 17 06:10:42 PM PDT 24
Peak memory 207476 kb
Host smart-5e1a303e-80a9-4d47-802a-9a3e124c2742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26400
51334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2640051334
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1102777503
Short name T2910
Test name
Test status
Simulation time 177405561 ps
CPU time 0.94 seconds
Started Aug 17 06:10:29 PM PDT 24
Finished Aug 17 06:10:30 PM PDT 24
Peak memory 207592 kb
Host smart-72a61a59-f612-44ab-af42-90537eeede1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11027
77503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1102777503
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1367817271
Short name T3195
Test name
Test status
Simulation time 147860882 ps
CPU time 0.86 seconds
Started Aug 17 06:10:39 PM PDT 24
Finished Aug 17 06:10:40 PM PDT 24
Peak memory 207784 kb
Host smart-c2bf6160-7b61-4bab-bb8c-38fb1a34480d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678
17271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1367817271
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.615107263
Short name T699
Test name
Test status
Simulation time 207818302 ps
CPU time 0.98 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207784 kb
Host smart-50018d22-1faf-4060-8c12-9e1e5ccfcbaf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=615107263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.615107263
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3334219943
Short name T1444
Test name
Test status
Simulation time 177193714 ps
CPU time 0.89 seconds
Started Aug 17 06:10:41 PM PDT 24
Finished Aug 17 06:10:42 PM PDT 24
Peak memory 207456 kb
Host smart-e32d55a7-4cea-4e4c-a885-c922ec12b4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33342
19943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3334219943
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.875306105
Short name T1952
Test name
Test status
Simulation time 35900520 ps
CPU time 0.7 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207728 kb
Host smart-79547038-8483-472c-a663-f12288346666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87530
6105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.875306105
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1649778255
Short name T272
Test name
Test status
Simulation time 18461562296 ps
CPU time 47.86 seconds
Started Aug 17 06:10:41 PM PDT 24
Finished Aug 17 06:11:29 PM PDT 24
Peak memory 215888 kb
Host smart-d76fe06a-d449-4c06-a311-f695d15beb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16497
78255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1649778255
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3800169374
Short name T1135
Test name
Test status
Simulation time 156102142 ps
CPU time 0.93 seconds
Started Aug 17 06:10:36 PM PDT 24
Finished Aug 17 06:10:37 PM PDT 24
Peak memory 207452 kb
Host smart-3abb3c25-2a6a-4ab9-bf7f-fe01401b8641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38001
69374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3800169374
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.340806956
Short name T1209
Test name
Test status
Simulation time 187101015 ps
CPU time 0.99 seconds
Started Aug 17 06:10:36 PM PDT 24
Finished Aug 17 06:10:37 PM PDT 24
Peak memory 207424 kb
Host smart-138386f2-8b59-4040-873c-cb4e1b2211b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34080
6956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.340806956
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2701506912
Short name T987
Test name
Test status
Simulation time 234031110 ps
CPU time 1.02 seconds
Started Aug 17 06:10:43 PM PDT 24
Finished Aug 17 06:10:44 PM PDT 24
Peak memory 207488 kb
Host smart-f70a5560-5bb4-4333-a05c-188af1bd1a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27015
06912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2701506912
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.2231094611
Short name T1176
Test name
Test status
Simulation time 150976841 ps
CPU time 0.9 seconds
Started Aug 17 06:10:43 PM PDT 24
Finished Aug 17 06:10:44 PM PDT 24
Peak memory 207460 kb
Host smart-fe77abd0-ed44-44cd-aee4-f1906a310c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22310
94611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.2231094611
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2738965511
Short name T996
Test name
Test status
Simulation time 142590308 ps
CPU time 0.84 seconds
Started Aug 17 06:10:48 PM PDT 24
Finished Aug 17 06:10:49 PM PDT 24
Peak memory 207452 kb
Host smart-ab7bcda4-6a4e-4187-9921-0a5137d79055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27389
65511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2738965511
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_rx_full.4150655729
Short name T3049
Test name
Test status
Simulation time 328617834 ps
CPU time 1.37 seconds
Started Aug 17 06:10:50 PM PDT 24
Finished Aug 17 06:10:51 PM PDT 24
Peak memory 207460 kb
Host smart-42e006db-3105-4e4b-942e-94b7307729b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
55729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.4150655729
Directory /workspace/46.usbdev_rx_full/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2322408358
Short name T1489
Test name
Test status
Simulation time 148621339 ps
CPU time 0.9 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:02 PM PDT 24
Peak memory 207444 kb
Host smart-f202294b-a07f-4cd6-a63c-a00801dba831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23224
08358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2322408358
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1091403439
Short name T116
Test name
Test status
Simulation time 187299874 ps
CPU time 0.94 seconds
Started Aug 17 06:10:43 PM PDT 24
Finished Aug 17 06:10:44 PM PDT 24
Peak memory 207468 kb
Host smart-4acc915c-7018-46eb-a9db-a57ccc94c5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10914
03439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1091403439
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1648618323
Short name T2293
Test name
Test status
Simulation time 227293604 ps
CPU time 1.01 seconds
Started Aug 17 06:10:48 PM PDT 24
Finished Aug 17 06:10:49 PM PDT 24
Peak memory 207392 kb
Host smart-7b33098d-bbdb-487f-95dc-fdc195fe1b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16486
18323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1648618323
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.1681925934
Short name T2080
Test name
Test status
Simulation time 1841692392 ps
CPU time 18.53 seconds
Started Aug 17 06:10:45 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 217576 kb
Host smart-cca8eeb7-b54c-4d7a-9f81-0e3e38b79068
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1681925934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.1681925934
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.844032782
Short name T2150
Test name
Test status
Simulation time 178148760 ps
CPU time 0.91 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:10:45 PM PDT 24
Peak memory 207484 kb
Host smart-c5c62ab1-9e93-4522-8203-9d8e0516b30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84403
2782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.844032782
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1835808185
Short name T3443
Test name
Test status
Simulation time 162289100 ps
CPU time 0.95 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207540 kb
Host smart-161036d7-b42f-4f6a-8585-b4b60f1bc32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18358
08185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1835808185
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.744087721
Short name T2933
Test name
Test status
Simulation time 1266946303 ps
CPU time 2.93 seconds
Started Aug 17 06:10:43 PM PDT 24
Finished Aug 17 06:10:46 PM PDT 24
Peak memory 207692 kb
Host smart-79a498ec-5b2a-4556-8ea3-96b2a14c989c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74408
7721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.744087721
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.339043846
Short name T675
Test name
Test status
Simulation time 3504795431 ps
CPU time 27.29 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:11:11 PM PDT 24
Peak memory 217676 kb
Host smart-6a3bbd16-850c-487e-827c-74d0d55a6e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904
3846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.339043846
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.10757971
Short name T2142
Test name
Test status
Simulation time 2171429871 ps
CPU time 14.05 seconds
Started Aug 17 06:10:39 PM PDT 24
Finished Aug 17 06:10:53 PM PDT 24
Peak memory 207620 kb
Host smart-2ef625d2-5789-4ccb-8d5d-5d18b909fd4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10757971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_host_
handshake.10757971
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_tx_rx_disruption.2578855935
Short name T1758
Test name
Test status
Simulation time 455215139 ps
CPU time 1.61 seconds
Started Aug 17 06:10:41 PM PDT 24
Finished Aug 17 06:10:43 PM PDT 24
Peak memory 207576 kb
Host smart-7f19aef2-3b40-4cfe-b7f5-953867486fe9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578855935 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.usbdev_tx_rx_disruption.2578855935
Directory /workspace/46.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/460.usbdev_tx_rx_disruption.3373881909
Short name T1454
Test name
Test status
Simulation time 542196481 ps
CPU time 1.64 seconds
Started Aug 17 06:12:29 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207492 kb
Host smart-dc1df8c3-1828-491b-9327-18c0b5d1f50d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373881909 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 460.usbdev_tx_rx_disruption.3373881909
Directory /workspace/460.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/461.usbdev_tx_rx_disruption.2567068906
Short name T2506
Test name
Test status
Simulation time 612727570 ps
CPU time 1.77 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:55 PM PDT 24
Peak memory 207572 kb
Host smart-34522fee-7339-4563-92b7-7de29e8bd943
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567068906 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 461.usbdev_tx_rx_disruption.2567068906
Directory /workspace/461.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/462.usbdev_tx_rx_disruption.2740361541
Short name T3471
Test name
Test status
Simulation time 616699692 ps
CPU time 1.67 seconds
Started Aug 17 06:12:49 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 207536 kb
Host smart-7daa380b-55f0-4e15-8b6d-e6909daac7c6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740361541 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 462.usbdev_tx_rx_disruption.2740361541
Directory /workspace/462.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/463.usbdev_tx_rx_disruption.1924941407
Short name T3290
Test name
Test status
Simulation time 563425973 ps
CPU time 1.59 seconds
Started Aug 17 06:12:31 PM PDT 24
Finished Aug 17 06:12:33 PM PDT 24
Peak memory 207548 kb
Host smart-3d2eecfd-0d68-4c24-9500-53477516fdba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924941407 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 463.usbdev_tx_rx_disruption.1924941407
Directory /workspace/463.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/464.usbdev_tx_rx_disruption.3278590630
Short name T1229
Test name
Test status
Simulation time 559314215 ps
CPU time 1.69 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:37 PM PDT 24
Peak memory 207544 kb
Host smart-a2610655-458f-454d-9ac0-c7b3e7fba03e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278590630 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 464.usbdev_tx_rx_disruption.3278590630
Directory /workspace/464.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/465.usbdev_tx_rx_disruption.628595678
Short name T921
Test name
Test status
Simulation time 570885378 ps
CPU time 1.8 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 207504 kb
Host smart-ca957ecd-76cc-4e88-aa9b-68450db897ed
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628595678 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 465.usbdev_tx_rx_disruption.628595678
Directory /workspace/465.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/466.usbdev_tx_rx_disruption.4121454533
Short name T2756
Test name
Test status
Simulation time 496036883 ps
CPU time 1.51 seconds
Started Aug 17 06:12:28 PM PDT 24
Finished Aug 17 06:12:30 PM PDT 24
Peak memory 207540 kb
Host smart-2608fcd1-dd51-45a8-9eff-e85f0f4ff55f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121454533 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 466.usbdev_tx_rx_disruption.4121454533
Directory /workspace/466.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/467.usbdev_tx_rx_disruption.2912764158
Short name T2364
Test name
Test status
Simulation time 652941965 ps
CPU time 2.05 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:12:44 PM PDT 24
Peak memory 207544 kb
Host smart-094d8669-7f24-477a-95e2-54873b2ed269
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912764158 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 467.usbdev_tx_rx_disruption.2912764158
Directory /workspace/467.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/468.usbdev_tx_rx_disruption.904360669
Short name T1463
Test name
Test status
Simulation time 612258332 ps
CPU time 1.64 seconds
Started Aug 17 06:12:47 PM PDT 24
Finished Aug 17 06:12:49 PM PDT 24
Peak memory 207496 kb
Host smart-dc5ede84-d770-441f-8a41-ad7f1758c65d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904360669 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 468.usbdev_tx_rx_disruption.904360669
Directory /workspace/468.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/469.usbdev_tx_rx_disruption.1684703466
Short name T203
Test name
Test status
Simulation time 438279962 ps
CPU time 1.37 seconds
Started Aug 17 06:12:36 PM PDT 24
Finished Aug 17 06:12:38 PM PDT 24
Peak memory 207496 kb
Host smart-e007c732-aa48-49bd-bb8b-33c77c2d94ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684703466 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 469.usbdev_tx_rx_disruption.1684703466
Directory /workspace/469.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3179268642
Short name T3300
Test name
Test status
Simulation time 42163933 ps
CPU time 0.68 seconds
Started Aug 17 06:10:45 PM PDT 24
Finished Aug 17 06:10:46 PM PDT 24
Peak memory 207424 kb
Host smart-8764449a-2e32-45bf-9623-06e3cfb32235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3179268642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3179268642
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3992073353
Short name T2180
Test name
Test status
Simulation time 11742771692 ps
CPU time 14.84 seconds
Started Aug 17 06:10:51 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 207736 kb
Host smart-67b00c99-85f4-41c4-88d5-8ecafc9cd5ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992073353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.3992073353
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3744654341
Short name T9
Test name
Test status
Simulation time 16372433364 ps
CPU time 24.77 seconds
Started Aug 17 06:10:50 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 215968 kb
Host smart-98fe0198-0502-486b-a3f8-dd45786fb4d7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744654341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3744654341
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3060865109
Short name T3010
Test name
Test status
Simulation time 28848145816 ps
CPU time 34.1 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:11:18 PM PDT 24
Peak memory 207832 kb
Host smart-2411ff37-6f55-447d-8a2c-53b4272364c5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060865109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.3060865109
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3791460063
Short name T941
Test name
Test status
Simulation time 153406692 ps
CPU time 0.9 seconds
Started Aug 17 06:10:42 PM PDT 24
Finished Aug 17 06:10:43 PM PDT 24
Peak memory 207428 kb
Host smart-4cc030a5-71e5-45c6-aa5f-71a0a923ca1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37914
60063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3791460063
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.544766351
Short name T3305
Test name
Test status
Simulation time 143768272 ps
CPU time 0.87 seconds
Started Aug 17 06:10:42 PM PDT 24
Finished Aug 17 06:10:43 PM PDT 24
Peak memory 207496 kb
Host smart-a9aeaa97-9490-41b3-812a-ba89f2e2a2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54476
6351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.544766351
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.3313146632
Short name T3406
Test name
Test status
Simulation time 372943841 ps
CPU time 1.43 seconds
Started Aug 17 06:10:46 PM PDT 24
Finished Aug 17 06:10:48 PM PDT 24
Peak memory 207544 kb
Host smart-6474714c-57b2-4559-a7e7-eeb8f16cf69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33131
46632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.3313146632
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.4148496077
Short name T109
Test name
Test status
Simulation time 975131921 ps
CPU time 2.77 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 207648 kb
Host smart-8558fe10-3e9d-47a7-9a20-7ed72d4f6bff
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4148496077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.4148496077
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.4073740853
Short name T2891
Test name
Test status
Simulation time 35060631161 ps
CPU time 61.18 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 207808 kb
Host smart-a1280442-c79a-4d74-a365-8cd10ffc546e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40737
40853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.4073740853
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.1595540997
Short name T2103
Test name
Test status
Simulation time 3589711325 ps
CPU time 24.16 seconds
Started Aug 17 06:10:40 PM PDT 24
Finished Aug 17 06:11:04 PM PDT 24
Peak memory 207800 kb
Host smart-0c170b27-d475-4ea1-8cd3-6f58eb6f9b9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595540997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.1595540997
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.4290642218
Short name T1023
Test name
Test status
Simulation time 925778971 ps
CPU time 2.24 seconds
Started Aug 17 06:10:40 PM PDT 24
Finished Aug 17 06:10:42 PM PDT 24
Peak memory 207476 kb
Host smart-0aba1608-b5b4-42db-8ac6-8a5f351672b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42906
42218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.4290642218
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1169771522
Short name T574
Test name
Test status
Simulation time 143849026 ps
CPU time 0.88 seconds
Started Aug 17 06:10:59 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207480 kb
Host smart-62ad4378-500f-4a3c-82f6-e11d273ba2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11697
71522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1169771522
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2143449707
Short name T2038
Test name
Test status
Simulation time 36992461 ps
CPU time 0.71 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:10:56 PM PDT 24
Peak memory 207432 kb
Host smart-dfd443e9-47f1-4851-ad9b-e22dbfe2e6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
49707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2143449707
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1610113004
Short name T1007
Test name
Test status
Simulation time 918423812 ps
CPU time 2.45 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 207720 kb
Host smart-f7615efe-a59e-41f0-baa5-d3d319b9618c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16101
13004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1610113004
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_types.2475505336
Short name T483
Test name
Test status
Simulation time 366770543 ps
CPU time 1.25 seconds
Started Aug 17 06:10:42 PM PDT 24
Finished Aug 17 06:10:43 PM PDT 24
Peak memory 207460 kb
Host smart-07416939-a01f-4077-be05-b44012e7bd46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2475505336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.2475505336
Directory /workspace/47.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3286385044
Short name T219
Test name
Test status
Simulation time 247681731 ps
CPU time 1.5 seconds
Started Aug 17 06:10:45 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 207672 kb
Host smart-f4f67b46-4933-4578-b39f-31962432b71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
85044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3286385044
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3240771862
Short name T3028
Test name
Test status
Simulation time 243214314 ps
CPU time 1.5 seconds
Started Aug 17 06:10:42 PM PDT 24
Finished Aug 17 06:10:44 PM PDT 24
Peak memory 216884 kb
Host smart-37d7d3fd-618f-440c-a65f-002a25ad945c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3240771862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3240771862
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.4275838441
Short name T2648
Test name
Test status
Simulation time 143855489 ps
CPU time 0.82 seconds
Started Aug 17 06:10:48 PM PDT 24
Finished Aug 17 06:10:49 PM PDT 24
Peak memory 207484 kb
Host smart-e65cbd8d-866e-4391-a5fb-46e8e60b025d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42758
38441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.4275838441
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3895872771
Short name T3375
Test name
Test status
Simulation time 235998850 ps
CPU time 1.06 seconds
Started Aug 17 06:10:48 PM PDT 24
Finished Aug 17 06:10:50 PM PDT 24
Peak memory 207484 kb
Host smart-50233995-df08-4ddf-bcd7-eb903082a78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38958
72771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3895872771
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.2713588914
Short name T126
Test name
Test status
Simulation time 3450476181 ps
CPU time 97.39 seconds
Started Aug 17 06:10:43 PM PDT 24
Finished Aug 17 06:12:20 PM PDT 24
Peak memory 218448 kb
Host smart-5208e2e9-1a6d-42ad-84e3-eb3a8a3af021
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2713588914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.2713588914
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1739655010
Short name T1302
Test name
Test status
Simulation time 10564153416 ps
CPU time 131.01 seconds
Started Aug 17 06:10:41 PM PDT 24
Finished Aug 17 06:12:52 PM PDT 24
Peak memory 208004 kb
Host smart-06a49f92-1397-4831-a516-5fb629f0508f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1739655010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1739655010
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.844082877
Short name T881
Test name
Test status
Simulation time 223630471 ps
CPU time 1.05 seconds
Started Aug 17 06:10:50 PM PDT 24
Finished Aug 17 06:10:51 PM PDT 24
Peak memory 207484 kb
Host smart-099d6220-ac6a-4b1a-a28f-d36d90fcc093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84408
2877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.844082877
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1861030050
Short name T3613
Test name
Test status
Simulation time 34692335204 ps
CPU time 55.46 seconds
Started Aug 17 06:10:49 PM PDT 24
Finished Aug 17 06:11:45 PM PDT 24
Peak memory 207796 kb
Host smart-50d56287-f47f-4204-9404-640d88a34d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18610
30050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1861030050
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.740078349
Short name T2222
Test name
Test status
Simulation time 4866013086 ps
CPU time 6.9 seconds
Started Aug 17 06:10:53 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207736 kb
Host smart-645bbc7c-ebbb-432f-aaa0-26170b45015a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74007
8349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.740078349
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.2748755093
Short name T3569
Test name
Test status
Simulation time 4343325018 ps
CPU time 36.2 seconds
Started Aug 17 06:10:56 PM PDT 24
Finished Aug 17 06:11:33 PM PDT 24
Peak memory 215992 kb
Host smart-c11cc4e0-44af-4f9b-9baa-0367603537af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2748755093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2748755093
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2764402603
Short name T1949
Test name
Test status
Simulation time 3042791975 ps
CPU time 23.9 seconds
Started Aug 17 06:10:40 PM PDT 24
Finished Aug 17 06:11:04 PM PDT 24
Peak memory 215892 kb
Host smart-2cbf6d8b-29c4-491a-97fb-977c06d7f816
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2764402603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2764402603
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.4195570591
Short name T2950
Test name
Test status
Simulation time 245530981 ps
CPU time 1.12 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207476 kb
Host smart-57b5af0b-16d8-4072-9ff2-940019d2862d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4195570591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.4195570591
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1921291401
Short name T1735
Test name
Test status
Simulation time 189255971 ps
CPU time 0.95 seconds
Started Aug 17 06:10:41 PM PDT 24
Finished Aug 17 06:10:42 PM PDT 24
Peak memory 207448 kb
Host smart-e15cb410-b8d9-4991-9cad-974f3f968605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19212
91401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1921291401
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.1529150055
Short name T1607
Test name
Test status
Simulation time 2679885718 ps
CPU time 22.28 seconds
Started Aug 17 06:10:49 PM PDT 24
Finished Aug 17 06:11:11 PM PDT 24
Peak memory 217792 kb
Host smart-bf682936-7deb-4171-b865-0d8e22478ee8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1529150055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.1529150055
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.4120205053
Short name T666
Test name
Test status
Simulation time 151191643 ps
CPU time 0.83 seconds
Started Aug 17 06:10:54 PM PDT 24
Finished Aug 17 06:10:55 PM PDT 24
Peak memory 207408 kb
Host smart-612db537-abf7-47c7-9a8b-3689ae9f5a30
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4120205053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.4120205053
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.174296864
Short name T3002
Test name
Test status
Simulation time 155362196 ps
CPU time 0.88 seconds
Started Aug 17 06:10:43 PM PDT 24
Finished Aug 17 06:10:44 PM PDT 24
Peak memory 207488 kb
Host smart-d5faa54b-a10f-4f6e-b2f0-2d9a31cc9d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17429
6864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.174296864
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3402711806
Short name T1488
Test name
Test status
Simulation time 175553353 ps
CPU time 0.91 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:10:45 PM PDT 24
Peak memory 207464 kb
Host smart-2e6e9692-35d7-41f0-a40e-d3cedeed41e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34027
11806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3402711806
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.666063223
Short name T760
Test name
Test status
Simulation time 174062756 ps
CPU time 0.87 seconds
Started Aug 17 06:10:39 PM PDT 24
Finished Aug 17 06:10:40 PM PDT 24
Peak memory 207460 kb
Host smart-27f29100-6975-4ed8-baf8-165b56897db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66606
3223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.666063223
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3099419893
Short name T3325
Test name
Test status
Simulation time 183379274 ps
CPU time 0.86 seconds
Started Aug 17 06:10:48 PM PDT 24
Finished Aug 17 06:10:49 PM PDT 24
Peak memory 207460 kb
Host smart-9840da51-a794-4c6c-a211-3ec33d9d2500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30994
19893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3099419893
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.406649034
Short name T2549
Test name
Test status
Simulation time 181751070 ps
CPU time 0.86 seconds
Started Aug 17 06:10:47 PM PDT 24
Finished Aug 17 06:10:48 PM PDT 24
Peak memory 207760 kb
Host smart-a107eff6-e7a9-4dbb-9125-4f05347d27e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664
9034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.406649034
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.4023218621
Short name T208
Test name
Test status
Simulation time 188737147 ps
CPU time 0.93 seconds
Started Aug 17 06:10:42 PM PDT 24
Finished Aug 17 06:10:43 PM PDT 24
Peak memory 207544 kb
Host smart-8cc52241-00b8-44ce-b777-785010b52603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40232
18621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.4023218621
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3544731720
Short name T1622
Test name
Test status
Simulation time 239523667 ps
CPU time 1.02 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:10:45 PM PDT 24
Peak memory 207528 kb
Host smart-8c77ae05-c47f-457f-83fe-752192b37c75
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3544731720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3544731720
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.56262483
Short name T3351
Test name
Test status
Simulation time 153524584 ps
CPU time 0.85 seconds
Started Aug 17 06:10:47 PM PDT 24
Finished Aug 17 06:10:48 PM PDT 24
Peak memory 207440 kb
Host smart-1e659b6d-e8dd-452e-ad7c-6da9c7827c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56262
483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.56262483
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2622886098
Short name T3566
Test name
Test status
Simulation time 39621955 ps
CPU time 0.72 seconds
Started Aug 17 06:10:39 PM PDT 24
Finished Aug 17 06:10:39 PM PDT 24
Peak memory 207508 kb
Host smart-f4ead781-9dc3-48ab-b91e-7d4053f3cf71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26228
86098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2622886098
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3076741940
Short name T3119
Test name
Test status
Simulation time 16660284307 ps
CPU time 43.75 seconds
Started Aug 17 06:10:42 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 216136 kb
Host smart-30655211-6451-4aed-ad8c-c1d62c98ca03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30767
41940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3076741940
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.884889371
Short name T3485
Test name
Test status
Simulation time 164981174 ps
CPU time 0.95 seconds
Started Aug 17 06:10:54 PM PDT 24
Finished Aug 17 06:10:55 PM PDT 24
Peak memory 207560 kb
Host smart-af3784c7-8570-4675-a241-c4d0d53903a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88488
9371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.884889371
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.75552282
Short name T3394
Test name
Test status
Simulation time 247703831 ps
CPU time 1.03 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:10:45 PM PDT 24
Peak memory 207444 kb
Host smart-71499499-6741-469d-8e7c-dbbbf643d3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75552
282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.75552282
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.386170575
Short name T3150
Test name
Test status
Simulation time 195268901 ps
CPU time 0.94 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:02 PM PDT 24
Peak memory 207420 kb
Host smart-df325554-e7a1-4b27-bd18-e79cb50f99b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38617
0575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.386170575
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1720689755
Short name T3193
Test name
Test status
Simulation time 218957282 ps
CPU time 0.96 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 207492 kb
Host smart-d80f71de-6e3f-4668-b436-d2cc111dc734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17206
89755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1720689755
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1221421980
Short name T2720
Test name
Test status
Simulation time 182982835 ps
CPU time 0.89 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:10:45 PM PDT 24
Peak memory 207472 kb
Host smart-22d1c1ae-61d3-4b25-b914-060f68ecea84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12214
21980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1221421980
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_rx_full.3218222248
Short name T1269
Test name
Test status
Simulation time 265171537 ps
CPU time 1.14 seconds
Started Aug 17 06:10:47 PM PDT 24
Finished Aug 17 06:10:49 PM PDT 24
Peak memory 207460 kb
Host smart-c5d1c9c1-c2a0-452a-9d85-77db59608bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32182
22248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.3218222248
Directory /workspace/47.usbdev_rx_full/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1873433938
Short name T2762
Test name
Test status
Simulation time 141732539 ps
CPU time 0.9 seconds
Started Aug 17 06:10:47 PM PDT 24
Finished Aug 17 06:10:48 PM PDT 24
Peak memory 207444 kb
Host smart-206e373b-aad0-49ac-8f79-ffc419390d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18734
33938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1873433938
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3644430068
Short name T2304
Test name
Test status
Simulation time 150283440 ps
CPU time 0.84 seconds
Started Aug 17 06:11:00 PM PDT 24
Finished Aug 17 06:11:01 PM PDT 24
Peak memory 207452 kb
Host smart-fb5a4f55-71d0-4062-bb8c-a2fb5c6a688d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36444
30068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3644430068
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1499047159
Short name T1494
Test name
Test status
Simulation time 220492295 ps
CPU time 1.02 seconds
Started Aug 17 06:10:46 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 207460 kb
Host smart-731b75bf-fbba-4e3d-93e9-b25d1dea384b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14990
47159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1499047159
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.4013632096
Short name T3
Test name
Test status
Simulation time 1922074348 ps
CPU time 20.02 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 216712 kb
Host smart-a3979bbf-5fec-4c69-a2e2-9f0ee5c2f7c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4013632096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.4013632096
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3567505959
Short name T1098
Test name
Test status
Simulation time 178329821 ps
CPU time 0.93 seconds
Started Aug 17 06:10:54 PM PDT 24
Finished Aug 17 06:10:55 PM PDT 24
Peak memory 207404 kb
Host smart-3e824907-4587-4e3a-8671-35844064605b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35675
05959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3567505959
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2538467640
Short name T868
Test name
Test status
Simulation time 180715397 ps
CPU time 0.94 seconds
Started Aug 17 06:10:56 PM PDT 24
Finished Aug 17 06:10:57 PM PDT 24
Peak memory 207616 kb
Host smart-9d84e3c8-3068-474d-966a-11cc4459f763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25384
67640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2538467640
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.3839863867
Short name T2179
Test name
Test status
Simulation time 886278359 ps
CPU time 2.29 seconds
Started Aug 17 06:10:56 PM PDT 24
Finished Aug 17 06:10:58 PM PDT 24
Peak memory 207656 kb
Host smart-12d7602b-f91e-4752-9c33-d604a0b5d353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398
63867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.3839863867
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2151602949
Short name T908
Test name
Test status
Simulation time 2222528839 ps
CPU time 65.15 seconds
Started Aug 17 06:10:44 PM PDT 24
Finished Aug 17 06:11:50 PM PDT 24
Peak memory 216004 kb
Host smart-83d13354-b636-4ddb-9f5e-204dfc01fff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21516
02949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2151602949
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.2339578943
Short name T2098
Test name
Test status
Simulation time 2905667446 ps
CPU time 25.88 seconds
Started Aug 17 06:10:38 PM PDT 24
Finished Aug 17 06:11:04 PM PDT 24
Peak memory 207700 kb
Host smart-f952d760-6671-4947-a0b8-12857d9fe4ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339578943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.2339578943
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_tx_rx_disruption.4270449417
Short name T2766
Test name
Test status
Simulation time 629545042 ps
CPU time 1.74 seconds
Started Aug 17 06:10:45 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 207552 kb
Host smart-1afc625a-1564-4a74-a1c8-26df0b61691f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270449417 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.usbdev_tx_rx_disruption.4270449417
Directory /workspace/47.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/470.usbdev_tx_rx_disruption.4031733883
Short name T607
Test name
Test status
Simulation time 431424385 ps
CPU time 1.42 seconds
Started Aug 17 06:12:29 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207528 kb
Host smart-9dffe29b-7bad-44b5-866d-116f11b0c048
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031733883 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 470.usbdev_tx_rx_disruption.4031733883
Directory /workspace/470.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/471.usbdev_tx_rx_disruption.1622938827
Short name T2352
Test name
Test status
Simulation time 475743563 ps
CPU time 1.52 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:12:42 PM PDT 24
Peak memory 207548 kb
Host smart-46dc12bf-4350-48b3-aa3f-d403ab598552
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622938827 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 471.usbdev_tx_rx_disruption.1622938827
Directory /workspace/471.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/472.usbdev_tx_rx_disruption.3319886932
Short name T2388
Test name
Test status
Simulation time 550701474 ps
CPU time 1.68 seconds
Started Aug 17 06:12:32 PM PDT 24
Finished Aug 17 06:12:34 PM PDT 24
Peak memory 207576 kb
Host smart-682c9f2e-f79c-456d-ad50-1fee979583b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319886932 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 472.usbdev_tx_rx_disruption.3319886932
Directory /workspace/472.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/473.usbdev_tx_rx_disruption.657645772
Short name T1912
Test name
Test status
Simulation time 433716135 ps
CPU time 1.37 seconds
Started Aug 17 06:12:49 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 207540 kb
Host smart-07ba5463-3c8b-4ab4-afb4-f109dd5bef3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657645772 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 473.usbdev_tx_rx_disruption.657645772
Directory /workspace/473.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/474.usbdev_tx_rx_disruption.1598057650
Short name T938
Test name
Test status
Simulation time 448477181 ps
CPU time 1.46 seconds
Started Aug 17 06:12:46 PM PDT 24
Finished Aug 17 06:12:48 PM PDT 24
Peak memory 207572 kb
Host smart-69783528-4239-42c7-9d1e-c355ccd45dc1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598057650 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 474.usbdev_tx_rx_disruption.1598057650
Directory /workspace/474.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/475.usbdev_tx_rx_disruption.3394438445
Short name T2710
Test name
Test status
Simulation time 504301736 ps
CPU time 1.64 seconds
Started Aug 17 06:12:42 PM PDT 24
Finished Aug 17 06:12:44 PM PDT 24
Peak memory 207600 kb
Host smart-53d23a05-7ed3-4f45-8adb-4db286297a0c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394438445 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 475.usbdev_tx_rx_disruption.3394438445
Directory /workspace/475.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/476.usbdev_tx_rx_disruption.4075209700
Short name T1581
Test name
Test status
Simulation time 626534702 ps
CPU time 1.67 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207520 kb
Host smart-0f7535af-33e7-4f3a-9cf9-3c9505c14ac8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075209700 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 476.usbdev_tx_rx_disruption.4075209700
Directory /workspace/476.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/477.usbdev_tx_rx_disruption.2128116782
Short name T2101
Test name
Test status
Simulation time 614526755 ps
CPU time 1.83 seconds
Started Aug 17 06:12:33 PM PDT 24
Finished Aug 17 06:12:34 PM PDT 24
Peak memory 207528 kb
Host smart-713d44d7-58b6-4942-9aec-5441e4adcea6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128116782 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 477.usbdev_tx_rx_disruption.2128116782
Directory /workspace/477.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/478.usbdev_tx_rx_disruption.2047733666
Short name T2858
Test name
Test status
Simulation time 414999460 ps
CPU time 1.29 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:54 PM PDT 24
Peak memory 207548 kb
Host smart-3a421c17-c26c-4edb-8cde-de36f4f75146
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047733666 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 478.usbdev_tx_rx_disruption.2047733666
Directory /workspace/478.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/479.usbdev_tx_rx_disruption.103041945
Short name T1092
Test name
Test status
Simulation time 516942573 ps
CPU time 1.54 seconds
Started Aug 17 06:12:26 PM PDT 24
Finished Aug 17 06:12:27 PM PDT 24
Peak memory 207556 kb
Host smart-e7bd33d8-c0e5-4463-9039-299ab03ac5bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103041945 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 479.usbdev_tx_rx_disruption.103041945
Directory /workspace/479.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3916211612
Short name T93
Test name
Test status
Simulation time 36768979 ps
CPU time 0.74 seconds
Started Aug 17 06:11:03 PM PDT 24
Finished Aug 17 06:11:04 PM PDT 24
Peak memory 207424 kb
Host smart-5adb8f8b-3c9e-439c-92c1-34936619c447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3916211612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3916211612
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.33898298
Short name T692
Test name
Test status
Simulation time 4557943886 ps
CPU time 6.36 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:11:01 PM PDT 24
Peak memory 215916 kb
Host smart-7714f2fd-816f-4ce8-865b-f041bb6979b4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33898298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon
_wake_disconnect.33898298
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.514464198
Short name T1049
Test name
Test status
Simulation time 15179061442 ps
CPU time 18.69 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:21 PM PDT 24
Peak memory 215988 kb
Host smart-0cdc8595-40d5-4f06-9e49-93303ffa50e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=514464198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.514464198
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.1317098157
Short name T2449
Test name
Test status
Simulation time 28900193676 ps
CPU time 36.36 seconds
Started Aug 17 06:10:45 PM PDT 24
Finished Aug 17 06:11:22 PM PDT 24
Peak memory 207752 kb
Host smart-f1e1493c-e883-4538-984f-faa4ceb69926
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317098157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.1317098157
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1524709395
Short name T3064
Test name
Test status
Simulation time 244411690 ps
CPU time 1.03 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207476 kb
Host smart-583c24b2-41cf-4ee6-a664-5ae06d84db8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15247
09395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1524709395
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2902828126
Short name T1635
Test name
Test status
Simulation time 183143032 ps
CPU time 0.86 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 207504 kb
Host smart-c88c1d99-dc14-4bdb-a20c-e9baca038206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29028
28126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2902828126
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2814374145
Short name T548
Test name
Test status
Simulation time 275329678 ps
CPU time 1.21 seconds
Started Aug 17 06:10:54 PM PDT 24
Finished Aug 17 06:10:55 PM PDT 24
Peak memory 207476 kb
Host smart-0b28ac05-dab4-4dcf-b6be-30ec656f8051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28143
74145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2814374145
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.4090715055
Short name T922
Test name
Test status
Simulation time 451484071 ps
CPU time 1.48 seconds
Started Aug 17 06:10:58 PM PDT 24
Finished Aug 17 06:10:59 PM PDT 24
Peak memory 207476 kb
Host smart-202ce972-1beb-454f-b8f5-3d89194c39a1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4090715055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.4090715055
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1157016231
Short name T2585
Test name
Test status
Simulation time 30809593287 ps
CPU time 49.21 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:57 PM PDT 24
Peak memory 207792 kb
Host smart-69069a07-2a1c-406e-95d9-a6cfe5d5b124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11570
16231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1157016231
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.2506909124
Short name T1616
Test name
Test status
Simulation time 606061637 ps
CPU time 5.24 seconds
Started Aug 17 06:10:47 PM PDT 24
Finished Aug 17 06:10:52 PM PDT 24
Peak memory 207688 kb
Host smart-9375e765-bf42-47f4-a81d-1b61a3087c40
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506909124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.2506909124
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2165542094
Short name T2167
Test name
Test status
Simulation time 513402471 ps
CPU time 1.66 seconds
Started Aug 17 06:10:47 PM PDT 24
Finished Aug 17 06:10:48 PM PDT 24
Peak memory 207564 kb
Host smart-706f2b0f-2eac-442b-bece-4498f2aa295c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
42094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2165542094
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1456943332
Short name T2869
Test name
Test status
Simulation time 141782092 ps
CPU time 0.84 seconds
Started Aug 17 06:10:49 PM PDT 24
Finished Aug 17 06:10:50 PM PDT 24
Peak memory 207420 kb
Host smart-d33b3e68-ecbe-4c64-9f10-d637c887cb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14569
43332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1456943332
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1904717799
Short name T1268
Test name
Test status
Simulation time 44252864 ps
CPU time 0.78 seconds
Started Aug 17 06:10:52 PM PDT 24
Finished Aug 17 06:10:53 PM PDT 24
Peak memory 207444 kb
Host smart-f617f6ca-7d38-4a4c-94b7-ee6f3d135852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19047
17799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1904717799
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1403128953
Short name T662
Test name
Test status
Simulation time 704863566 ps
CPU time 2.19 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:04 PM PDT 24
Peak memory 207784 kb
Host smart-871e39af-d914-41c9-8319-d1e2887e5193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14031
28953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1403128953
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1484651019
Short name T677
Test name
Test status
Simulation time 196978896 ps
CPU time 2.33 seconds
Started Aug 17 06:10:52 PM PDT 24
Finished Aug 17 06:10:55 PM PDT 24
Peak memory 207684 kb
Host smart-d017e4bd-5487-4fd6-bfd2-0b185a043f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14846
51019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1484651019
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2221141343
Short name T1529
Test name
Test status
Simulation time 179627597 ps
CPU time 0.98 seconds
Started Aug 17 06:10:45 PM PDT 24
Finished Aug 17 06:10:46 PM PDT 24
Peak memory 215876 kb
Host smart-f6ab3798-d8e0-4d23-b017-1e8b04f1dec7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2221141343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2221141343
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1754688520
Short name T2241
Test name
Test status
Simulation time 154445977 ps
CPU time 0.84 seconds
Started Aug 17 06:11:04 PM PDT 24
Finished Aug 17 06:11:05 PM PDT 24
Peak memory 207384 kb
Host smart-d6b09ff8-ea7c-4588-9c9a-5f34df9c37d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546
88520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1754688520
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.282398592
Short name T2459
Test name
Test status
Simulation time 162582418 ps
CPU time 0.88 seconds
Started Aug 17 06:11:03 PM PDT 24
Finished Aug 17 06:11:04 PM PDT 24
Peak memory 207416 kb
Host smart-6e509b8d-8708-447b-b9b1-47a04bc1948b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28239
8592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.282398592
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.435276740
Short name T2820
Test name
Test status
Simulation time 4027261817 ps
CPU time 121.42 seconds
Started Aug 17 06:11:03 PM PDT 24
Finished Aug 17 06:13:04 PM PDT 24
Peak memory 217688 kb
Host smart-726d965e-9864-4d20-be1e-7e7a590e51a2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=435276740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.435276740
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.3188124467
Short name T1906
Test name
Test status
Simulation time 11524191227 ps
CPU time 134.53 seconds
Started Aug 17 06:10:45 PM PDT 24
Finished Aug 17 06:12:59 PM PDT 24
Peak memory 207756 kb
Host smart-0b9d779d-f84a-41be-8772-6e5782fa55fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3188124467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.3188124467
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1897633743
Short name T2588
Test name
Test status
Simulation time 249340601 ps
CPU time 1.06 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:02 PM PDT 24
Peak memory 207512 kb
Host smart-e4dfc4cc-d9a4-412c-ba29-6fed9f32ac2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18976
33743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1897633743
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3835221616
Short name T2154
Test name
Test status
Simulation time 9962069475 ps
CPU time 14.69 seconds
Started Aug 17 06:10:53 PM PDT 24
Finished Aug 17 06:11:07 PM PDT 24
Peak memory 207824 kb
Host smart-b908005f-f938-4825-b27d-d7c350ac5c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38352
21616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3835221616
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2258326898
Short name T1192
Test name
Test status
Simulation time 3545148174 ps
CPU time 26.14 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:27 PM PDT 24
Peak memory 216008 kb
Host smart-4bec3efe-ea1e-4181-ab95-1ce4cf601128
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2258326898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2258326898
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2380671075
Short name T3414
Test name
Test status
Simulation time 2488230547 ps
CPU time 24.36 seconds
Started Aug 17 06:10:54 PM PDT 24
Finished Aug 17 06:11:19 PM PDT 24
Peak memory 215880 kb
Host smart-e914f4d7-72ad-4d01-86a8-e41639d01f18
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2380671075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2380671075
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3685242558
Short name T3187
Test name
Test status
Simulation time 238817845 ps
CPU time 0.95 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 207468 kb
Host smart-f36cab82-5073-4083-a7ac-7f3909933f62
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3685242558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3685242558
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3422627990
Short name T2894
Test name
Test status
Simulation time 243676707 ps
CPU time 0.99 seconds
Started Aug 17 06:10:50 PM PDT 24
Finished Aug 17 06:10:51 PM PDT 24
Peak memory 207412 kb
Host smart-03c35b10-ff6d-4263-9f61-ea5662e3bc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34226
27990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3422627990
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.801424536
Short name T1563
Test name
Test status
Simulation time 2127899400 ps
CPU time 59.59 seconds
Started Aug 17 06:11:06 PM PDT 24
Finished Aug 17 06:12:06 PM PDT 24
Peak memory 215916 kb
Host smart-50a81a0b-b6d0-4688-892a-d8de36d2a02b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=801424536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.801424536
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.413393990
Short name T2931
Test name
Test status
Simulation time 164781680 ps
CPU time 0.93 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207468 kb
Host smart-69f1ca23-ea83-44c2-be8a-07065a79a458
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=413393990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.413393990
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2578142997
Short name T2136
Test name
Test status
Simulation time 161703278 ps
CPU time 0.96 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207488 kb
Host smart-ed4cd61f-f3e5-47c0-a83e-821589c3f9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25781
42997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2578142997
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2923406911
Short name T139
Test name
Test status
Simulation time 217446821 ps
CPU time 0.98 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:10:56 PM PDT 24
Peak memory 207460 kb
Host smart-fee6965b-18b6-4470-969e-43d10b482fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29234
06911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2923406911
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3751847432
Short name T2951
Test name
Test status
Simulation time 176760504 ps
CPU time 1.02 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207476 kb
Host smart-fab2d625-c599-47f8-8c65-03c318fc93c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37518
47432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3751847432
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1836275756
Short name T3560
Test name
Test status
Simulation time 151730856 ps
CPU time 0.86 seconds
Started Aug 17 06:10:45 PM PDT 24
Finished Aug 17 06:10:46 PM PDT 24
Peak memory 207460 kb
Host smart-afae2229-4605-4ea0-8733-6ff89dc2a939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18362
75756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1836275756
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1679981215
Short name T940
Test name
Test status
Simulation time 195006780 ps
CPU time 0.9 seconds
Started Aug 17 06:10:54 PM PDT 24
Finished Aug 17 06:10:55 PM PDT 24
Peak memory 207436 kb
Host smart-b2e14082-3a97-44fb-a185-70e151cd1dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16799
81215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1679981215
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2964483814
Short name T2130
Test name
Test status
Simulation time 166926056 ps
CPU time 0.86 seconds
Started Aug 17 06:10:54 PM PDT 24
Finished Aug 17 06:10:55 PM PDT 24
Peak memory 207480 kb
Host smart-047b31c3-9bc3-463c-b812-66d6698d4a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29644
83814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2964483814
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.2987490537
Short name T1989
Test name
Test status
Simulation time 237124721 ps
CPU time 1 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 207544 kb
Host smart-b2d6b4d4-9170-4df6-a9b2-81027981a96a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2987490537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.2987490537
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.4090559479
Short name T2068
Test name
Test status
Simulation time 141322018 ps
CPU time 0.86 seconds
Started Aug 17 06:10:47 PM PDT 24
Finished Aug 17 06:10:48 PM PDT 24
Peak memory 207380 kb
Host smart-bf5bf350-c9e9-46c2-b17f-4aef03fa5b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40905
59479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.4090559479
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1126262236
Short name T30
Test name
Test status
Simulation time 38103017 ps
CPU time 0.7 seconds
Started Aug 17 06:10:52 PM PDT 24
Finished Aug 17 06:10:53 PM PDT 24
Peak memory 207528 kb
Host smart-d5270ca4-05ea-4c86-bd14-97f515184769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11262
62236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1126262236
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.590350115
Short name T3301
Test name
Test status
Simulation time 12478113810 ps
CPU time 31.03 seconds
Started Aug 17 06:10:58 PM PDT 24
Finished Aug 17 06:11:29 PM PDT 24
Peak memory 215916 kb
Host smart-9c625b9d-fec0-49e4-b371-ccec67aaa0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59035
0115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.590350115
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.4279502184
Short name T1667
Test name
Test status
Simulation time 205588952 ps
CPU time 0.97 seconds
Started Aug 17 06:10:59 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207612 kb
Host smart-b3ce2f99-c54a-4788-86bf-85b043c60b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42795
02184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.4279502184
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.23750963
Short name T650
Test name
Test status
Simulation time 207411486 ps
CPU time 1.03 seconds
Started Aug 17 06:10:56 PM PDT 24
Finished Aug 17 06:10:57 PM PDT 24
Peak memory 207400 kb
Host smart-a972ab0e-8c2d-41e4-8aae-d8bef7998010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23750
963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.23750963
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2337560951
Short name T2676
Test name
Test status
Simulation time 239150468 ps
CPU time 0.99 seconds
Started Aug 17 06:10:57 PM PDT 24
Finished Aug 17 06:10:58 PM PDT 24
Peak memory 207492 kb
Host smart-b00d0378-95d0-4232-881c-ce178d17de89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23375
60951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2337560951
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3705999064
Short name T725
Test name
Test status
Simulation time 155727666 ps
CPU time 0.91 seconds
Started Aug 17 06:10:52 PM PDT 24
Finished Aug 17 06:10:53 PM PDT 24
Peak memory 207492 kb
Host smart-38b8fa64-1d61-4b41-ae98-09f97361e961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37059
99064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3705999064
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.357580817
Short name T1760
Test name
Test status
Simulation time 168547743 ps
CPU time 0.84 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:08 PM PDT 24
Peak memory 207416 kb
Host smart-874d8560-db22-4d72-a9a7-f2ccebbeaa19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35758
0817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.357580817
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_rx_full.2694321213
Short name T3445
Test name
Test status
Simulation time 248678890 ps
CPU time 1.06 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207476 kb
Host smart-1b15eb3b-7e01-4aa7-8d1d-c67af0a1266d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26943
21213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.2694321213
Directory /workspace/48.usbdev_rx_full/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1013293640
Short name T2626
Test name
Test status
Simulation time 190978310 ps
CPU time 0.89 seconds
Started Aug 17 06:10:52 PM PDT 24
Finished Aug 17 06:10:53 PM PDT 24
Peak memory 207548 kb
Host smart-a36f9bfd-b593-4c20-bda5-913c473239e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10132
93640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1013293640
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3831514195
Short name T583
Test name
Test status
Simulation time 151568182 ps
CPU time 0.85 seconds
Started Aug 17 06:10:52 PM PDT 24
Finished Aug 17 06:10:52 PM PDT 24
Peak memory 207472 kb
Host smart-9c6e36e8-aba8-4191-b56c-d5fd76fdfcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38315
14195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3831514195
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3378628992
Short name T1692
Test name
Test status
Simulation time 241270288 ps
CPU time 1.04 seconds
Started Aug 17 06:10:58 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207460 kb
Host smart-dabb4583-b3c3-472e-8f56-29451ed8db6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33786
28992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3378628992
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2703505146
Short name T1884
Test name
Test status
Simulation time 2804925883 ps
CPU time 24.94 seconds
Started Aug 17 06:10:52 PM PDT 24
Finished Aug 17 06:11:17 PM PDT 24
Peak memory 215884 kb
Host smart-911386d2-862c-4d3e-8428-611d45dcb870
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2703505146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2703505146
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3977201604
Short name T1822
Test name
Test status
Simulation time 157993742 ps
CPU time 0.9 seconds
Started Aug 17 06:10:58 PM PDT 24
Finished Aug 17 06:10:59 PM PDT 24
Peak memory 207480 kb
Host smart-7c0b8490-564c-486a-a30a-656e90acce01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39772
01604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3977201604
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.749176330
Short name T1972
Test name
Test status
Simulation time 194340733 ps
CPU time 0.92 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207484 kb
Host smart-baf8c388-a47a-40ef-9016-1c219d092dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74917
6330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.749176330
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.2371667179
Short name T3335
Test name
Test status
Simulation time 1201246778 ps
CPU time 2.96 seconds
Started Aug 17 06:11:06 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207708 kb
Host smart-d1ab0591-c650-4407-a03b-bc57e2d5e5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23716
67179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2371667179
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1381707365
Short name T2403
Test name
Test status
Simulation time 1855439110 ps
CPU time 14.53 seconds
Started Aug 17 06:10:54 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207772 kb
Host smart-4e77bb8b-8c6a-4997-84c5-ccafabef8cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13817
07365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1381707365
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.967239603
Short name T2426
Test name
Test status
Simulation time 2889922150 ps
CPU time 25.82 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:31 PM PDT 24
Peak memory 207648 kb
Host smart-fd227798-1d21-4799-921a-452ba4835f93
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967239603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_host
_handshake.967239603
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_tx_rx_disruption.930179131
Short name T3578
Test name
Test status
Simulation time 500718172 ps
CPU time 1.62 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:08 PM PDT 24
Peak memory 207544 kb
Host smart-9ca3a19b-95d4-4c8c-8718-fd1971290873
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930179131 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.usbdev_tx_rx_disruption.930179131
Directory /workspace/48.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/480.usbdev_tx_rx_disruption.3277121049
Short name T2066
Test name
Test status
Simulation time 488892396 ps
CPU time 1.49 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207544 kb
Host smart-b6a87a9f-8c2d-4339-a710-056f424a4c17
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277121049 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 480.usbdev_tx_rx_disruption.3277121049
Directory /workspace/480.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/481.usbdev_tx_rx_disruption.3360280191
Short name T2622
Test name
Test status
Simulation time 591159890 ps
CPU time 1.65 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207484 kb
Host smart-ba823827-8bcb-48d2-b48f-55817e728578
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360280191 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 481.usbdev_tx_rx_disruption.3360280191
Directory /workspace/481.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/482.usbdev_tx_rx_disruption.384279266
Short name T3592
Test name
Test status
Simulation time 538484436 ps
CPU time 1.52 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207500 kb
Host smart-5b41049e-0019-43c0-8ebd-8c22c2b3c058
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384279266 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 482.usbdev_tx_rx_disruption.384279266
Directory /workspace/482.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/483.usbdev_tx_rx_disruption.705092274
Short name T2128
Test name
Test status
Simulation time 549136883 ps
CPU time 1.67 seconds
Started Aug 17 06:12:28 PM PDT 24
Finished Aug 17 06:12:30 PM PDT 24
Peak memory 207552 kb
Host smart-7d8f0f28-ed3b-4ffd-83c4-61095ae95101
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705092274 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 483.usbdev_tx_rx_disruption.705092274
Directory /workspace/483.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/484.usbdev_tx_rx_disruption.1945614542
Short name T952
Test name
Test status
Simulation time 616082386 ps
CPU time 1.88 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:52 PM PDT 24
Peak memory 207504 kb
Host smart-78625ea7-9197-4a9f-8047-a92a270530a2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945614542 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 484.usbdev_tx_rx_disruption.1945614542
Directory /workspace/484.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/485.usbdev_tx_rx_disruption.2240981244
Short name T3191
Test name
Test status
Simulation time 464964046 ps
CPU time 1.44 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 207572 kb
Host smart-90743383-e48d-4c7a-83d3-32edf2c654fd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240981244 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 485.usbdev_tx_rx_disruption.2240981244
Directory /workspace/485.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/486.usbdev_tx_rx_disruption.1609224658
Short name T1423
Test name
Test status
Simulation time 461335862 ps
CPU time 1.48 seconds
Started Aug 17 06:12:32 PM PDT 24
Finished Aug 17 06:12:34 PM PDT 24
Peak memory 207544 kb
Host smart-235f886f-cad7-440b-b50a-0fe02ef06a78
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609224658 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 486.usbdev_tx_rx_disruption.1609224658
Directory /workspace/486.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/487.usbdev_tx_rx_disruption.1537008377
Short name T622
Test name
Test status
Simulation time 494824969 ps
CPU time 1.65 seconds
Started Aug 17 06:12:32 PM PDT 24
Finished Aug 17 06:12:34 PM PDT 24
Peak memory 207548 kb
Host smart-63a56945-3295-4926-90a0-e04220c85355
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537008377 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 487.usbdev_tx_rx_disruption.1537008377
Directory /workspace/487.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/488.usbdev_tx_rx_disruption.816182311
Short name T840
Test name
Test status
Simulation time 537696253 ps
CPU time 1.68 seconds
Started Aug 17 06:12:39 PM PDT 24
Finished Aug 17 06:12:41 PM PDT 24
Peak memory 207500 kb
Host smart-ba5cd5d0-eae2-46b9-ad2e-b961ef5fdaf3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816182311 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 488.usbdev_tx_rx_disruption.816182311
Directory /workspace/488.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/489.usbdev_tx_rx_disruption.715424703
Short name T3501
Test name
Test status
Simulation time 582774810 ps
CPU time 1.61 seconds
Started Aug 17 06:12:35 PM PDT 24
Finished Aug 17 06:12:37 PM PDT 24
Peak memory 207600 kb
Host smart-cc198a32-e815-40d3-919a-4d3a79a82efa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715424703 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 489.usbdev_tx_rx_disruption.715424703
Directory /workspace/489.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.725406629
Short name T2377
Test name
Test status
Simulation time 42576726 ps
CPU time 0.67 seconds
Started Aug 17 06:10:58 PM PDT 24
Finished Aug 17 06:10:59 PM PDT 24
Peak memory 207440 kb
Host smart-77c9b5a5-6eae-4783-9c53-0d1e62cabe34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=725406629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.725406629
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1737646712
Short name T943
Test name
Test status
Simulation time 6428528110 ps
CPU time 10.44 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:18 PM PDT 24
Peak memory 215972 kb
Host smart-b23a0618-c106-4cfb-971e-c8516e94df2e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737646712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.1737646712
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3966019275
Short name T1052
Test name
Test status
Simulation time 15194934439 ps
CPU time 18 seconds
Started Aug 17 06:10:59 PM PDT 24
Finished Aug 17 06:11:17 PM PDT 24
Peak memory 216012 kb
Host smart-071a729c-e0b0-4878-ab88-c4eee72d2127
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966019275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3966019275
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.4261800907
Short name T3409
Test name
Test status
Simulation time 24628808480 ps
CPU time 32.88 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:11:28 PM PDT 24
Peak memory 215984 kb
Host smart-29777e4b-4164-4f97-b641-273090736773
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261800907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.4261800907
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3331612695
Short name T575
Test name
Test status
Simulation time 169253867 ps
CPU time 0.96 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:02 PM PDT 24
Peak memory 207488 kb
Host smart-e8f4fb9d-c4d7-4a59-b8f8-eb8fc6e42b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33316
12695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3331612695
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.4015667432
Short name T749
Test name
Test status
Simulation time 253298176 ps
CPU time 1.12 seconds
Started Aug 17 06:10:57 PM PDT 24
Finished Aug 17 06:10:58 PM PDT 24
Peak memory 207500 kb
Host smart-d0ce5409-6531-40d8-a735-21c85af2f684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40156
67432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.4015667432
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.617924719
Short name T2548
Test name
Test status
Simulation time 1329291557 ps
CPU time 3.48 seconds
Started Aug 17 06:10:50 PM PDT 24
Finished Aug 17 06:10:53 PM PDT 24
Peak memory 207760 kb
Host smart-f70cac6e-4c7f-4d9c-b5eb-22b56b522e4c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=617924719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.617924719
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3423544407
Short name T112
Test name
Test status
Simulation time 15461576957 ps
CPU time 28.49 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:11:23 PM PDT 24
Peak memory 207768 kb
Host smart-50f3954b-7005-410a-91a5-8dea8bb64d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
44407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3423544407
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.1009739136
Short name T1701
Test name
Test status
Simulation time 612813049 ps
CPU time 4.97 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207740 kb
Host smart-d521e9de-74f7-4b90-9817-77c2de4e4412
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009739136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.1009739136
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.660465392
Short name T2790
Test name
Test status
Simulation time 979700701 ps
CPU time 2.24 seconds
Started Aug 17 06:10:53 PM PDT 24
Finished Aug 17 06:10:55 PM PDT 24
Peak memory 207508 kb
Host smart-a25333bd-d5f5-4a63-bc7a-93fde1fecc00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66046
5392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.660465392
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3388474127
Short name T37
Test name
Test status
Simulation time 146206125 ps
CPU time 0.82 seconds
Started Aug 17 06:11:06 PM PDT 24
Finished Aug 17 06:11:07 PM PDT 24
Peak memory 207504 kb
Host smart-6f994d05-2ae4-40b8-a9e5-f319ba2c68c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33884
74127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3388474127
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2182755485
Short name T1805
Test name
Test status
Simulation time 48792786 ps
CPU time 0.74 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207440 kb
Host smart-433ab2af-cd45-47ff-8c7b-d6bb081c42fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21827
55485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2182755485
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1697410163
Short name T620
Test name
Test status
Simulation time 804329323 ps
CPU time 2.2 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:11 PM PDT 24
Peak memory 207720 kb
Host smart-3331fd0b-e5da-4519-9db5-06cc971cad51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16974
10163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1697410163
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_types.1296496674
Short name T419
Test name
Test status
Simulation time 318384831 ps
CPU time 1.19 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207448 kb
Host smart-aaf6c0a1-1d0d-41a2-a576-b44b719810cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1296496674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.1296496674
Directory /workspace/49.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2163378748
Short name T989
Test name
Test status
Simulation time 214510010 ps
CPU time 2.22 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:10:58 PM PDT 24
Peak memory 207632 kb
Host smart-3288fba2-8123-4547-b599-ba1f9446b79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21633
78748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2163378748
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2986789076
Short name T2294
Test name
Test status
Simulation time 227871389 ps
CPU time 1.26 seconds
Started Aug 17 06:11:03 PM PDT 24
Finished Aug 17 06:11:05 PM PDT 24
Peak memory 215780 kb
Host smart-1c3f0806-fef6-4449-a975-6ddc3d3bfadf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2986789076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2986789076
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3129557116
Short name T1614
Test name
Test status
Simulation time 151023324 ps
CPU time 0.93 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:02 PM PDT 24
Peak memory 207440 kb
Host smart-c5a5b4d0-bfe8-4f58-9a80-99dc88955a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31295
57116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3129557116
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2080957003
Short name T2409
Test name
Test status
Simulation time 172726636 ps
CPU time 0.85 seconds
Started Aug 17 06:10:57 PM PDT 24
Finished Aug 17 06:10:58 PM PDT 24
Peak memory 207436 kb
Host smart-c2ef3c79-9356-41b1-b63e-7e82c840862a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20809
57003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2080957003
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3688098879
Short name T1994
Test name
Test status
Simulation time 3971774286 ps
CPU time 31.4 seconds
Started Aug 17 06:11:03 PM PDT 24
Finished Aug 17 06:11:34 PM PDT 24
Peak memory 218184 kb
Host smart-ad3986af-4c8a-4b89-9f68-7020ad6dd576
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3688098879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3688098879
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.4162909522
Short name T1100
Test name
Test status
Simulation time 4660535082 ps
CPU time 60.28 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:12:02 PM PDT 24
Peak memory 207784 kb
Host smart-55036edc-7341-4103-a55d-e76aa7e5cdcb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4162909522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.4162909522
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3399202840
Short name T2455
Test name
Test status
Simulation time 232626098 ps
CPU time 1.03 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 207512 kb
Host smart-381b898c-a5b9-4c15-89f3-611505bbbde4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33992
02840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3399202840
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1241996224
Short name T1006
Test name
Test status
Simulation time 8763759253 ps
CPU time 15.75 seconds
Started Aug 17 06:11:03 PM PDT 24
Finished Aug 17 06:11:18 PM PDT 24
Peak memory 207728 kb
Host smart-f78d0066-9b8a-465c-8583-7be826cfb260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12419
96224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1241996224
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.803919007
Short name T2807
Test name
Test status
Simulation time 6030758554 ps
CPU time 8.44 seconds
Started Aug 17 06:11:04 PM PDT 24
Finished Aug 17 06:11:12 PM PDT 24
Peak memory 207760 kb
Host smart-7e4a4ee5-b3dc-4914-b9c6-ee40dcf9d19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80391
9007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.803919007
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1654783696
Short name T1662
Test name
Test status
Simulation time 3967844199 ps
CPU time 41.79 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:50 PM PDT 24
Peak memory 219320 kb
Host smart-d11acbc6-bbdb-48db-969e-d282a981ce87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1654783696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1654783696
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.621061932
Short name T3635
Test name
Test status
Simulation time 3271200748 ps
CPU time 25.73 seconds
Started Aug 17 06:11:02 PM PDT 24
Finished Aug 17 06:11:28 PM PDT 24
Peak memory 217592 kb
Host smart-9f291df6-d829-44f9-b2fc-533ca143406b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=621061932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.621061932
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2798338400
Short name T2538
Test name
Test status
Simulation time 298405435 ps
CPU time 1.14 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207404 kb
Host smart-d95489f1-e16b-466a-ad76-d07ed405c527
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2798338400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2798338400
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2133848639
Short name T2717
Test name
Test status
Simulation time 192890189 ps
CPU time 1.03 seconds
Started Aug 17 06:10:52 PM PDT 24
Finished Aug 17 06:10:53 PM PDT 24
Peak memory 207456 kb
Host smart-ca1f5076-f225-4e2f-a721-6ecb5628f892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21338
48639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2133848639
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.4264167597
Short name T3455
Test name
Test status
Simulation time 2211101819 ps
CPU time 17.91 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:11:14 PM PDT 24
Peak memory 217392 kb
Host smart-03139a90-255c-4d2b-a6ec-dae85c8d44de
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4264167597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.4264167597
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.85220415
Short name T1065
Test name
Test status
Simulation time 165130174 ps
CPU time 0.84 seconds
Started Aug 17 06:10:53 PM PDT 24
Finished Aug 17 06:10:54 PM PDT 24
Peak memory 207464 kb
Host smart-288ba5eb-9ba7-4029-ac71-cdf3ee4d8335
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=85220415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.85220415
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2273291294
Short name T1617
Test name
Test status
Simulation time 153081602 ps
CPU time 0.84 seconds
Started Aug 17 06:11:04 PM PDT 24
Finished Aug 17 06:11:04 PM PDT 24
Peak memory 207432 kb
Host smart-67614932-2205-4bce-a83c-8fefd78901aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22732
91294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2273291294
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3262434601
Short name T164
Test name
Test status
Simulation time 199432092 ps
CPU time 0.99 seconds
Started Aug 17 06:10:56 PM PDT 24
Finished Aug 17 06:10:57 PM PDT 24
Peak memory 207464 kb
Host smart-03916240-a588-4151-99a1-196a7c4d8556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32624
34601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3262434601
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.3698421141
Short name T2523
Test name
Test status
Simulation time 166848411 ps
CPU time 0.86 seconds
Started Aug 17 06:10:50 PM PDT 24
Finished Aug 17 06:10:51 PM PDT 24
Peak memory 207684 kb
Host smart-fbf776a7-0924-4020-809d-44ffdc1103ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36984
21141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3698421141
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2843467647
Short name T3607
Test name
Test status
Simulation time 213379995 ps
CPU time 0.97 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:02 PM PDT 24
Peak memory 207480 kb
Host smart-dfaa8932-d00e-40bb-b80b-18836ee1ce61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28434
67647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2843467647
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.300889776
Short name T3512
Test name
Test status
Simulation time 163131553 ps
CPU time 0.84 seconds
Started Aug 17 06:10:51 PM PDT 24
Finished Aug 17 06:10:52 PM PDT 24
Peak memory 207452 kb
Host smart-0ada22b1-834f-4e1a-a8e2-c926dd794ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30088
9776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.300889776
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.714733312
Short name T1894
Test name
Test status
Simulation time 141673815 ps
CPU time 0.84 seconds
Started Aug 17 06:10:54 PM PDT 24
Finished Aug 17 06:10:55 PM PDT 24
Peak memory 207584 kb
Host smart-02830656-6001-4a9d-90fd-5557a918a86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71473
3312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.714733312
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1368980564
Short name T1784
Test name
Test status
Simulation time 201214444 ps
CPU time 1.06 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 207532 kb
Host smart-9ab54eb8-0b88-40d9-91d7-0ad77ef0ff04
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1368980564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1368980564
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3563387100
Short name T770
Test name
Test status
Simulation time 141402770 ps
CPU time 0.82 seconds
Started Aug 17 06:10:59 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207396 kb
Host smart-f07da450-91bf-4ae3-bf61-ad1c18c3ea91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
87100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3563387100
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1617813947
Short name T1275
Test name
Test status
Simulation time 42340029 ps
CPU time 0.74 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207504 kb
Host smart-f833acf5-975e-4ece-9060-67074f416905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16178
13947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1617813947
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3037135097
Short name T2295
Test name
Test status
Simulation time 11892120466 ps
CPU time 33.48 seconds
Started Aug 17 06:11:11 PM PDT 24
Finished Aug 17 06:11:44 PM PDT 24
Peak memory 215888 kb
Host smart-146dd6fc-dbae-46af-8a13-84b51c0b44bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30371
35097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3037135097
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1226112176
Short name T1406
Test name
Test status
Simulation time 228769908 ps
CPU time 0.95 seconds
Started Aug 17 06:10:55 PM PDT 24
Finished Aug 17 06:10:56 PM PDT 24
Peak memory 207520 kb
Host smart-7aaf41a2-d8c4-4068-8447-703d8cd9201a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12261
12176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1226112176
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2185518222
Short name T923
Test name
Test status
Simulation time 178957842 ps
CPU time 0.95 seconds
Started Aug 17 06:11:13 PM PDT 24
Finished Aug 17 06:11:14 PM PDT 24
Peak memory 207460 kb
Host smart-6ac766e7-79f1-47c8-892c-4adc0447a800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21855
18222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2185518222
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3332542547
Short name T961
Test name
Test status
Simulation time 176885050 ps
CPU time 0.91 seconds
Started Aug 17 06:11:12 PM PDT 24
Finished Aug 17 06:11:13 PM PDT 24
Peak memory 207404 kb
Host smart-f6014910-6abe-4ea5-a02a-617c667d4707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33325
42547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3332542547
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2133562333
Short name T2964
Test name
Test status
Simulation time 158232568 ps
CPU time 0.86 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:08 PM PDT 24
Peak memory 207440 kb
Host smart-8486fe71-c812-4c19-bee0-a58a3680c045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21335
62333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2133562333
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.535358495
Short name T2496
Test name
Test status
Simulation time 200445198 ps
CPU time 0.95 seconds
Started Aug 17 06:11:09 PM PDT 24
Finished Aug 17 06:11:10 PM PDT 24
Peak memory 207460 kb
Host smart-25a63e8c-6b4c-4a8f-866e-ea4e8371b756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53535
8495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.535358495
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_rx_full.2512688327
Short name T1305
Test name
Test status
Simulation time 374419809 ps
CPU time 1.25 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 207480 kb
Host smart-95a9dd68-1dea-4fbb-932b-00e764fb3b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25126
88327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.2512688327
Directory /workspace/49.usbdev_rx_full/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1922803163
Short name T1639
Test name
Test status
Simulation time 158202412 ps
CPU time 0.83 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207528 kb
Host smart-e8584781-b854-42e2-9373-5c1b6d8ad38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19228
03163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1922803163
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1271118352
Short name T2514
Test name
Test status
Simulation time 155762698 ps
CPU time 0.82 seconds
Started Aug 17 06:10:59 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207488 kb
Host smart-de4f0ac2-8cad-45b9-809d-0994588ecbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12711
18352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1271118352
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2033101412
Short name T2553
Test name
Test status
Simulation time 275789838 ps
CPU time 1.07 seconds
Started Aug 17 06:10:59 PM PDT 24
Finished Aug 17 06:11:01 PM PDT 24
Peak memory 207476 kb
Host smart-4949620d-46aa-48b2-91a4-2079f4faf383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20331
01412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2033101412
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3663371437
Short name T3379
Test name
Test status
Simulation time 2493324607 ps
CPU time 25.06 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:30 PM PDT 24
Peak memory 223004 kb
Host smart-3d6b5deb-c8e5-4672-9b2c-510a0602e8a7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3663371437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3663371437
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.609186412
Short name T3015
Test name
Test status
Simulation time 169187142 ps
CPU time 0.95 seconds
Started Aug 17 06:10:59 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207496 kb
Host smart-ebcf9aac-cfc5-436c-ac06-e1bb745b28a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60918
6412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.609186412
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3993046623
Short name T3516
Test name
Test status
Simulation time 160219348 ps
CPU time 0.88 seconds
Started Aug 17 06:10:56 PM PDT 24
Finished Aug 17 06:10:57 PM PDT 24
Peak memory 207544 kb
Host smart-58fdde23-0430-42eb-ad2e-119e83e4ccfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39930
46623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3993046623
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.3336439298
Short name T1602
Test name
Test status
Simulation time 270293518 ps
CPU time 1.1 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207508 kb
Host smart-e46eac0b-50d9-4f44-81dd-59e0fdb48e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33364
39298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.3336439298
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1806714759
Short name T3558
Test name
Test status
Simulation time 2060154728 ps
CPU time 15.79 seconds
Started Aug 17 06:11:10 PM PDT 24
Finished Aug 17 06:11:26 PM PDT 24
Peak memory 223992 kb
Host smart-a77355c3-6418-4a66-ba46-f179ed1acec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18067
14759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1806714759
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.2681510715
Short name T1172
Test name
Test status
Simulation time 1132996136 ps
CPU time 9.37 seconds
Started Aug 17 06:10:53 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207636 kb
Host smart-e89a2fb4-c562-4200-a4e3-645ddbac2e89
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681510715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.2681510715
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_tx_rx_disruption.3558716380
Short name T3624
Test name
Test status
Simulation time 632924919 ps
CPU time 1.79 seconds
Started Aug 17 06:10:59 PM PDT 24
Finished Aug 17 06:11:01 PM PDT 24
Peak memory 207552 kb
Host smart-99c2f255-24ed-4d5b-bd17-591f4ed4ac92
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558716380 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.usbdev_tx_rx_disruption.3558716380
Directory /workspace/49.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/490.usbdev_tx_rx_disruption.3876947515
Short name T2176
Test name
Test status
Simulation time 519503947 ps
CPU time 1.46 seconds
Started Aug 17 06:12:44 PM PDT 24
Finished Aug 17 06:12:45 PM PDT 24
Peak memory 207568 kb
Host smart-a818c3f9-08eb-482e-9038-74fce36bfd33
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876947515 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 490.usbdev_tx_rx_disruption.3876947515
Directory /workspace/490.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/491.usbdev_tx_rx_disruption.2971698849
Short name T967
Test name
Test status
Simulation time 479466955 ps
CPU time 1.63 seconds
Started Aug 17 06:12:28 PM PDT 24
Finished Aug 17 06:12:29 PM PDT 24
Peak memory 207528 kb
Host smart-44629009-5745-4c58-bdfa-a71ae6396fb2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971698849 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 491.usbdev_tx_rx_disruption.2971698849
Directory /workspace/491.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/492.usbdev_tx_rx_disruption.2497837098
Short name T1068
Test name
Test status
Simulation time 569025875 ps
CPU time 1.65 seconds
Started Aug 17 06:12:44 PM PDT 24
Finished Aug 17 06:12:45 PM PDT 24
Peak memory 207568 kb
Host smart-1ef5f9a5-a6bc-49a7-83a2-a8475728f7f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497837098 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 492.usbdev_tx_rx_disruption.2497837098
Directory /workspace/492.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/493.usbdev_tx_rx_disruption.1587856851
Short name T1410
Test name
Test status
Simulation time 576490876 ps
CPU time 1.61 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 207500 kb
Host smart-037d2145-aad4-45a8-9611-081afc92be7a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587856851 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 493.usbdev_tx_rx_disruption.1587856851
Directory /workspace/493.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/494.usbdev_tx_rx_disruption.2116095369
Short name T1736
Test name
Test status
Simulation time 519771437 ps
CPU time 1.63 seconds
Started Aug 17 06:12:45 PM PDT 24
Finished Aug 17 06:12:47 PM PDT 24
Peak memory 207520 kb
Host smart-249aa3de-148d-4fba-a5c3-1e8a340bcc59
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116095369 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 494.usbdev_tx_rx_disruption.2116095369
Directory /workspace/494.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/495.usbdev_tx_rx_disruption.1014297664
Short name T3282
Test name
Test status
Simulation time 558401466 ps
CPU time 1.7 seconds
Started Aug 17 06:12:47 PM PDT 24
Finished Aug 17 06:12:49 PM PDT 24
Peak memory 207500 kb
Host smart-7f40bcc4-31f5-4fef-b66c-3a7bcda99c8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014297664 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 495.usbdev_tx_rx_disruption.1014297664
Directory /workspace/495.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/496.usbdev_tx_rx_disruption.2022322955
Short name T1953
Test name
Test status
Simulation time 619580406 ps
CPU time 1.65 seconds
Started Aug 17 06:12:31 PM PDT 24
Finished Aug 17 06:12:33 PM PDT 24
Peak memory 207548 kb
Host smart-b4ea6fe6-1661-4fb7-aa58-6453f728f874
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022322955 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 496.usbdev_tx_rx_disruption.2022322955
Directory /workspace/496.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/497.usbdev_tx_rx_disruption.1158531962
Short name T218
Test name
Test status
Simulation time 650403675 ps
CPU time 1.73 seconds
Started Aug 17 06:12:45 PM PDT 24
Finished Aug 17 06:12:47 PM PDT 24
Peak memory 207568 kb
Host smart-1e415fa5-c2e7-48f5-86ca-6fada3b96903
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158531962 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 497.usbdev_tx_rx_disruption.1158531962
Directory /workspace/497.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/498.usbdev_tx_rx_disruption.3918605288
Short name T3620
Test name
Test status
Simulation time 531290855 ps
CPU time 1.7 seconds
Started Aug 17 06:12:29 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 207532 kb
Host smart-26af065d-409a-4f8f-9fed-c79deea51063
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918605288 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 498.usbdev_tx_rx_disruption.3918605288
Directory /workspace/498.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/499.usbdev_tx_rx_disruption.3928851153
Short name T2233
Test name
Test status
Simulation time 502429779 ps
CPU time 1.64 seconds
Started Aug 17 06:12:31 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207492 kb
Host smart-2a28f597-f917-4f20-b644-d0a69f9d1913
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928851153 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 499.usbdev_tx_rx_disruption.3928851153
Directory /workspace/499.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2959771049
Short name T1028
Test name
Test status
Simulation time 70604825 ps
CPU time 0.72 seconds
Started Aug 17 06:03:52 PM PDT 24
Finished Aug 17 06:03:53 PM PDT 24
Peak memory 207420 kb
Host smart-43a0fc4e-28d8-43df-bff9-26af8f7feb7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2959771049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2959771049
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.4274432067
Short name T3377
Test name
Test status
Simulation time 4845039780 ps
CPU time 6.49 seconds
Started Aug 17 06:03:39 PM PDT 24
Finished Aug 17 06:03:46 PM PDT 24
Peak memory 215988 kb
Host smart-bb2acb9a-1eab-45d5-b862-ea928f0efd25
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274432067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.4274432067
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.1824366285
Short name T1715
Test name
Test status
Simulation time 13648711688 ps
CPU time 16.13 seconds
Started Aug 17 06:03:40 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 215980 kb
Host smart-580f6846-531c-48e7-a88f-af4328cb79ad
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824366285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.1824366285
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2152207830
Short name T1360
Test name
Test status
Simulation time 25517318744 ps
CPU time 31.47 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:04:09 PM PDT 24
Peak memory 215928 kb
Host smart-25c9166a-eca5-4536-97dc-48b8bad84f33
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152207830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.2152207830
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1177453547
Short name T1258
Test name
Test status
Simulation time 152625819 ps
CPU time 0.88 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207480 kb
Host smart-7a820531-be37-4531-8492-508d8a427bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11774
53547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1177453547
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.750693166
Short name T1470
Test name
Test status
Simulation time 157612378 ps
CPU time 0.91 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207400 kb
Host smart-3040fedd-9380-46a6-a279-53486993c7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75069
3166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.750693166
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3174882027
Short name T1957
Test name
Test status
Simulation time 219903909 ps
CPU time 1.08 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207476 kb
Host smart-f4feacc7-0893-441a-82da-3b88ae0367a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31748
82027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3174882027
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1877715226
Short name T2975
Test name
Test status
Simulation time 584603887 ps
CPU time 1.65 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:03:40 PM PDT 24
Peak memory 207544 kb
Host smart-f19a45b9-7e5c-4f08-bd51-56da167488c9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1877715226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1877715226
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3805705304
Short name T2422
Test name
Test status
Simulation time 23158349574 ps
CPU time 41.75 seconds
Started Aug 17 06:03:42 PM PDT 24
Finished Aug 17 06:04:24 PM PDT 24
Peak memory 207776 kb
Host smart-13ecaab1-e4c4-4386-a22e-03b963ddc9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38057
05304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3805705304
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.3139103956
Short name T1697
Test name
Test status
Simulation time 7786006980 ps
CPU time 51.77 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:04:29 PM PDT 24
Peak memory 207792 kb
Host smart-62fef09c-eaa7-4762-a687-acdc3352c0af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139103956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3139103956
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.874303142
Short name T2908
Test name
Test status
Simulation time 482294164 ps
CPU time 1.58 seconds
Started Aug 17 06:03:41 PM PDT 24
Finished Aug 17 06:03:42 PM PDT 24
Peak memory 207536 kb
Host smart-136e39ad-5038-4cea-b7fc-d74e3b03bdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87430
3142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.874303142
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3682387138
Short name T1124
Test name
Test status
Simulation time 151649236 ps
CPU time 0.82 seconds
Started Aug 17 06:03:43 PM PDT 24
Finished Aug 17 06:03:44 PM PDT 24
Peak memory 207504 kb
Host smart-05c81851-b872-4cee-aeac-5567ca580e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36823
87138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3682387138
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.3020357766
Short name T1956
Test name
Test status
Simulation time 89813783 ps
CPU time 0.81 seconds
Started Aug 17 06:03:41 PM PDT 24
Finished Aug 17 06:03:42 PM PDT 24
Peak memory 207420 kb
Host smart-fcda5fcf-2a4e-42b4-9a75-95e6777bd6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30203
57766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3020357766
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3853235446
Short name T3054
Test name
Test status
Simulation time 855356937 ps
CPU time 2.51 seconds
Started Aug 17 06:03:39 PM PDT 24
Finished Aug 17 06:03:42 PM PDT 24
Peak memory 207740 kb
Host smart-962a4a5e-fa5a-4014-b215-618364016281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38532
35446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3853235446
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.52180036
Short name T3584
Test name
Test status
Simulation time 178397599 ps
CPU time 2.17 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:40 PM PDT 24
Peak memory 207612 kb
Host smart-ca3d63de-9a69-4b19-b376-f8abb5ce38a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52180
036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.52180036
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.654629612
Short name T1606
Test name
Test status
Simulation time 196469503 ps
CPU time 1.09 seconds
Started Aug 17 06:03:39 PM PDT 24
Finished Aug 17 06:03:41 PM PDT 24
Peak memory 215864 kb
Host smart-b0c536b6-43b1-42cb-84b8-eff1afc34677
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=654629612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.654629612
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.753720103
Short name T1019
Test name
Test status
Simulation time 138973816 ps
CPU time 0.83 seconds
Started Aug 17 06:03:42 PM PDT 24
Finished Aug 17 06:03:43 PM PDT 24
Peak memory 207420 kb
Host smart-a74edeaf-868d-46dc-a7c4-0e4b3eccc5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75372
0103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.753720103
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1305182272
Short name T625
Test name
Test status
Simulation time 179863193 ps
CPU time 0.92 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207460 kb
Host smart-e6e90783-51ff-43ce-b1e9-ea9aabab4ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13051
82272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1305182272
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.4064611283
Short name T2527
Test name
Test status
Simulation time 4155582257 ps
CPU time 43.07 seconds
Started Aug 17 06:03:39 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 217240 kb
Host smart-c2977ae0-a5f6-47fa-bbb2-3af0dd028e85
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4064611283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.4064611283
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1016042741
Short name T1093
Test name
Test status
Simulation time 9532216045 ps
CPU time 122.6 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:05:40 PM PDT 24
Peak memory 207736 kb
Host smart-e2a687bc-6eff-4733-8212-bfc51f9049dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1016042741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1016042741
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.225045277
Short name T2421
Test name
Test status
Simulation time 234515219 ps
CPU time 1 seconds
Started Aug 17 06:03:38 PM PDT 24
Finished Aug 17 06:03:39 PM PDT 24
Peak memory 207464 kb
Host smart-fb50e189-ffc7-4821-bf51-784e421a6bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504
5277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.225045277
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1105829846
Short name T2349
Test name
Test status
Simulation time 24015460699 ps
CPU time 49.11 seconds
Started Aug 17 06:03:37 PM PDT 24
Finished Aug 17 06:04:27 PM PDT 24
Peak memory 216084 kb
Host smart-f2c5b0b7-a1f2-4dd1-b1a5-e127054b9516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11058
29846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1105829846
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.258930443
Short name T2391
Test name
Test status
Simulation time 5317893700 ps
CPU time 7.38 seconds
Started Aug 17 06:03:41 PM PDT 24
Finished Aug 17 06:03:48 PM PDT 24
Peak memory 215980 kb
Host smart-38a59bf1-7a91-437e-b565-8d3e97177197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25893
0443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.258930443
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.2412968794
Short name T1777
Test name
Test status
Simulation time 6212869486 ps
CPU time 185.05 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:06:52 PM PDT 24
Peak memory 215916 kb
Host smart-bd91a3b5-b441-4a6d-acbb-62662f315647
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2412968794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.2412968794
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.4038890397
Short name T3149
Test name
Test status
Simulation time 2866712566 ps
CPU time 28 seconds
Started Aug 17 06:03:48 PM PDT 24
Finished Aug 17 06:04:16 PM PDT 24
Peak memory 215860 kb
Host smart-657860c7-9b31-4f97-ba46-3b4029e3d3e6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4038890397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.4038890397
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.382005675
Short name T2061
Test name
Test status
Simulation time 235620570 ps
CPU time 0.96 seconds
Started Aug 17 06:03:45 PM PDT 24
Finished Aug 17 06:03:46 PM PDT 24
Peak memory 207704 kb
Host smart-7fef63f5-6188-4125-a3fe-df28d952f703
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=382005675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.382005675
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2033800088
Short name T3087
Test name
Test status
Simulation time 193406478 ps
CPU time 0.94 seconds
Started Aug 17 06:03:43 PM PDT 24
Finished Aug 17 06:03:44 PM PDT 24
Peak memory 207468 kb
Host smart-0aed5c48-9165-4c56-8ba7-1e89b53a80c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20338
00088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2033800088
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.1854794645
Short name T2437
Test name
Test status
Simulation time 3150304236 ps
CPU time 34.43 seconds
Started Aug 17 06:03:44 PM PDT 24
Finished Aug 17 06:04:19 PM PDT 24
Peak memory 217688 kb
Host smart-59a37d04-8fb8-47e9-8a88-daddc5be448f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
94645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.1854794645
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.2575006944
Short name T1053
Test name
Test status
Simulation time 3428723740 ps
CPU time 39.02 seconds
Started Aug 17 06:03:47 PM PDT 24
Finished Aug 17 06:04:26 PM PDT 24
Peak memory 224104 kb
Host smart-3792d485-58ce-459d-b2a2-ea84bae20e37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2575006944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.2575006944
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1369152002
Short name T2885
Test name
Test status
Simulation time 2363447232 ps
CPU time 25.65 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:04:12 PM PDT 24
Peak memory 217532 kb
Host smart-867f1a24-ac39-4495-b726-3866ebd6b908
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1369152002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1369152002
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3676497054
Short name T1245
Test name
Test status
Simulation time 164827511 ps
CPU time 0.86 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:03:47 PM PDT 24
Peak memory 207488 kb
Host smart-e9f1e97a-5f69-4fd2-be44-3170f580d247
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3676497054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3676497054
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1326704717
Short name T3170
Test name
Test status
Simulation time 144605939 ps
CPU time 0.84 seconds
Started Aug 17 06:03:45 PM PDT 24
Finished Aug 17 06:03:46 PM PDT 24
Peak memory 207456 kb
Host smart-e626faaa-fdcd-4f02-868d-461574156618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13267
04717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1326704717
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1933599567
Short name T146
Test name
Test status
Simulation time 231809141 ps
CPU time 1 seconds
Started Aug 17 06:03:45 PM PDT 24
Finished Aug 17 06:03:47 PM PDT 24
Peak memory 207472 kb
Host smart-a943f099-5a34-4d53-a6d5-9b6c51dac559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19335
99567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1933599567
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.423812434
Short name T3078
Test name
Test status
Simulation time 182543730 ps
CPU time 0.9 seconds
Started Aug 17 06:03:45 PM PDT 24
Finished Aug 17 06:03:46 PM PDT 24
Peak memory 207684 kb
Host smart-c63ac289-7615-44de-91fd-bdcf6693898d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42381
2434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.423812434
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1598237543
Short name T2912
Test name
Test status
Simulation time 226387722 ps
CPU time 0.96 seconds
Started Aug 17 06:03:47 PM PDT 24
Finished Aug 17 06:03:48 PM PDT 24
Peak memory 207488 kb
Host smart-8ab12efe-7596-41ad-b83a-44b82e5bddf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15982
37543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1598237543
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.26868183
Short name T2958
Test name
Test status
Simulation time 175760924 ps
CPU time 0.97 seconds
Started Aug 17 06:03:45 PM PDT 24
Finished Aug 17 06:03:46 PM PDT 24
Peak memory 207432 kb
Host smart-92c27f77-992a-424c-b201-5e668ab871c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26868
183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.26868183
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2526946734
Short name T2740
Test name
Test status
Simulation time 160316095 ps
CPU time 0.99 seconds
Started Aug 17 06:03:47 PM PDT 24
Finished Aug 17 06:03:48 PM PDT 24
Peak memory 207564 kb
Host smart-b3aab634-72bd-497e-8d58-29a57824a577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25269
46734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2526946734
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1594303235
Short name T2018
Test name
Test status
Simulation time 247571736 ps
CPU time 1.05 seconds
Started Aug 17 06:03:44 PM PDT 24
Finished Aug 17 06:03:45 PM PDT 24
Peak memory 207468 kb
Host smart-beb6fdae-1ff7-479a-8b4f-56ca308a2c98
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1594303235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1594303235
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1008542453
Short name T1125
Test name
Test status
Simulation time 206046507 ps
CPU time 0.84 seconds
Started Aug 17 06:03:44 PM PDT 24
Finished Aug 17 06:03:45 PM PDT 24
Peak memory 207448 kb
Host smart-ca6b19d1-bbd1-4116-a3ef-7451405d6ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10085
42453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1008542453
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.824347759
Short name T1554
Test name
Test status
Simulation time 36060847 ps
CPU time 0.7 seconds
Started Aug 17 06:03:49 PM PDT 24
Finished Aug 17 06:03:50 PM PDT 24
Peak memory 207532 kb
Host smart-21374130-8e48-4df8-8bac-d0f1ae1cc81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82434
7759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.824347759
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3517768004
Short name T279
Test name
Test status
Simulation time 19230091884 ps
CPU time 48.05 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:04:34 PM PDT 24
Peak memory 215908 kb
Host smart-29834340-2d01-4833-a9e5-289f9cb596d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35177
68004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3517768004
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2553391008
Short name T1284
Test name
Test status
Simulation time 204199489 ps
CPU time 0.97 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:03:47 PM PDT 24
Peak memory 207564 kb
Host smart-eba825f9-82f8-4659-a1e9-4e8157407906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25533
91008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2553391008
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3071273683
Short name T2331
Test name
Test status
Simulation time 247865586 ps
CPU time 1.02 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:03:48 PM PDT 24
Peak memory 207440 kb
Host smart-b0062113-936f-4653-aeb1-39a914896c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30712
73683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3071273683
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1215183090
Short name T1539
Test name
Test status
Simulation time 7480040664 ps
CPU time 73.35 seconds
Started Aug 17 06:03:47 PM PDT 24
Finished Aug 17 06:05:01 PM PDT 24
Peak memory 218744 kb
Host smart-dcb81a54-f11a-4a70-9ce1-fe2f52412fbb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215183090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1215183090
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2195532902
Short name T191
Test name
Test status
Simulation time 5774293857 ps
CPU time 27.21 seconds
Started Aug 17 06:03:44 PM PDT 24
Finished Aug 17 06:04:11 PM PDT 24
Peak memory 219632 kb
Host smart-9cac0513-198d-49ac-b6d8-6dd5cf7ddc14
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2195532902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2195532902
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2577247910
Short name T2163
Test name
Test status
Simulation time 6290844657 ps
CPU time 26.96 seconds
Started Aug 17 06:03:47 PM PDT 24
Finished Aug 17 06:04:14 PM PDT 24
Peak memory 219108 kb
Host smart-e406962b-3816-4ae7-81b6-d213935995bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577247910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2577247910
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3552741121
Short name T2602
Test name
Test status
Simulation time 207519590 ps
CPU time 0.93 seconds
Started Aug 17 06:03:47 PM PDT 24
Finished Aug 17 06:03:48 PM PDT 24
Peak memory 207496 kb
Host smart-0f16813c-f535-48b6-aaed-3780c38c583c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35527
41121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3552741121
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3333707822
Short name T3430
Test name
Test status
Simulation time 167364958 ps
CPU time 0.86 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:03:47 PM PDT 24
Peak memory 207440 kb
Host smart-6e71a237-c4de-416d-a9d8-670836367db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33337
07822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3333707822
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_resume_link_active.14720227
Short name T2290
Test name
Test status
Simulation time 20165448455 ps
CPU time 26.88 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:04:13 PM PDT 24
Peak memory 207580 kb
Host smart-da56c6d9-8ee3-4706-9d07-8a794fafa954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14720
227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.14720227
Directory /workspace/5.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1432123028
Short name T2863
Test name
Test status
Simulation time 165870965 ps
CPU time 0.88 seconds
Started Aug 17 06:03:47 PM PDT 24
Finished Aug 17 06:03:48 PM PDT 24
Peak memory 207460 kb
Host smart-fa0618e6-b3db-4174-8668-110796aa6b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14321
23028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1432123028
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_rx_full.3888660319
Short name T3529
Test name
Test status
Simulation time 360613258 ps
CPU time 1.28 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:03:48 PM PDT 24
Peak memory 207448 kb
Host smart-47a66228-e995-401c-b4b9-de9cbadb9d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38886
60319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.3888660319
Directory /workspace/5.usbdev_rx_full/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1699227003
Short name T1562
Test name
Test status
Simulation time 150447365 ps
CPU time 0.83 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:03:47 PM PDT 24
Peak memory 207472 kb
Host smart-f902a8ac-e8e7-4b7c-9a0f-cd20040c8a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16992
27003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1699227003
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3945589721
Short name T3260
Test name
Test status
Simulation time 167488673 ps
CPU time 0.88 seconds
Started Aug 17 06:03:46 PM PDT 24
Finished Aug 17 06:03:47 PM PDT 24
Peak memory 207552 kb
Host smart-071f646b-0423-452e-a063-df8f2e432534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39455
89721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3945589721
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.973749142
Short name T3056
Test name
Test status
Simulation time 227233256 ps
CPU time 1.08 seconds
Started Aug 17 06:03:47 PM PDT 24
Finished Aug 17 06:03:48 PM PDT 24
Peak memory 207464 kb
Host smart-9aa7c7bd-567d-46e5-a14e-dcf5bb3bcdf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97374
9142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.973749142
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1164216511
Short name T1228
Test name
Test status
Simulation time 2865609428 ps
CPU time 22.77 seconds
Started Aug 17 06:03:56 PM PDT 24
Finished Aug 17 06:04:19 PM PDT 24
Peak memory 217764 kb
Host smart-8c7d8612-51c8-4ff3-ab73-bef59023f8ca
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1164216511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1164216511
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.249968826
Short name T2253
Test name
Test status
Simulation time 193838176 ps
CPU time 0.98 seconds
Started Aug 17 06:03:57 PM PDT 24
Finished Aug 17 06:03:59 PM PDT 24
Peak memory 207484 kb
Host smart-5db218d7-4fcf-4a55-98ad-d6c2a4648615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24996
8826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.249968826
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2756850069
Short name T2890
Test name
Test status
Simulation time 161586270 ps
CPU time 0.84 seconds
Started Aug 17 06:03:53 PM PDT 24
Finished Aug 17 06:03:54 PM PDT 24
Peak memory 207436 kb
Host smart-19b6fe19-03f5-4037-b390-a9dbbf224838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27568
50069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2756850069
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2688605362
Short name T3117
Test name
Test status
Simulation time 649568374 ps
CPU time 1.94 seconds
Started Aug 17 06:03:55 PM PDT 24
Finished Aug 17 06:03:57 PM PDT 24
Peak memory 207456 kb
Host smart-936a2995-99a7-4d77-9895-7a612068e1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26886
05362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2688605362
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2147687135
Short name T3336
Test name
Test status
Simulation time 3116939334 ps
CPU time 24.78 seconds
Started Aug 17 06:04:02 PM PDT 24
Finished Aug 17 06:04:27 PM PDT 24
Peak memory 215944 kb
Host smart-1ed60975-d520-4f25-84aa-a666350aeb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
87135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2147687135
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.3006097609
Short name T944
Test name
Test status
Simulation time 1251852859 ps
CPU time 28.97 seconds
Started Aug 17 06:03:42 PM PDT 24
Finished Aug 17 06:04:11 PM PDT 24
Peak memory 207680 kb
Host smart-20bb7eba-686d-4d75-8482-e41af3a13e16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006097609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.3006097609
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_tx_rx_disruption.1551783667
Short name T2105
Test name
Test status
Simulation time 465109243 ps
CPU time 1.47 seconds
Started Aug 17 06:03:55 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 207560 kb
Host smart-b58da619-6b48-4b72-90cb-0bd64af93df1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551783667 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.usbdev_tx_rx_disruption.1551783667
Directory /workspace/5.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/50.usbdev_endpoint_types.1876613851
Short name T521
Test name
Test status
Simulation time 456818699 ps
CPU time 1.31 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:10 PM PDT 24
Peak memory 207516 kb
Host smart-78337ef6-667f-4388-a620-14ff9ba2ce38
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1876613851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.1876613851
Directory /workspace/50.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/50.usbdev_tx_rx_disruption.3267821217
Short name T3633
Test name
Test status
Simulation time 544074644 ps
CPU time 1.69 seconds
Started Aug 17 06:11:05 PM PDT 24
Finished Aug 17 06:11:07 PM PDT 24
Peak memory 207560 kb
Host smart-4c87a277-71c8-467c-8280-6bdab1630bb9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267821217 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.usbdev_tx_rx_disruption.3267821217
Directory /workspace/50.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/51.usbdev_endpoint_types.1948340434
Short name T442
Test name
Test status
Simulation time 500169017 ps
CPU time 1.49 seconds
Started Aug 17 06:10:58 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207516 kb
Host smart-f0f1130e-ae8f-41ef-a4e8-3b090b174c35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1948340434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.1948340434
Directory /workspace/51.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/51.usbdev_tx_rx_disruption.205577017
Short name T1133
Test name
Test status
Simulation time 595468180 ps
CPU time 1.81 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207616 kb
Host smart-5623eeed-95bc-4b26-bd45-767d90d6af22
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205577017 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 51.usbdev_tx_rx_disruption.205577017
Directory /workspace/51.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/52.usbdev_endpoint_types.142124390
Short name T409
Test name
Test status
Simulation time 299840586 ps
CPU time 1.09 seconds
Started Aug 17 06:11:01 PM PDT 24
Finished Aug 17 06:11:03 PM PDT 24
Peak memory 207504 kb
Host smart-24740ff5-9a74-424f-a943-c4296fdb70b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=142124390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.142124390
Directory /workspace/52.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/52.usbdev_tx_rx_disruption.4040733470
Short name T3278
Test name
Test status
Simulation time 606983154 ps
CPU time 1.59 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207516 kb
Host smart-3c22b755-1bea-4249-b9b1-148db91fae1b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040733470 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.usbdev_tx_rx_disruption.4040733470
Directory /workspace/52.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/53.usbdev_endpoint_types.1095444006
Short name T491
Test name
Test status
Simulation time 308264794 ps
CPU time 1.16 seconds
Started Aug 17 06:11:00 PM PDT 24
Finished Aug 17 06:11:01 PM PDT 24
Peak memory 207516 kb
Host smart-f6b4cfa1-2d80-4e6b-84db-6d001bded4d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1095444006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.1095444006
Directory /workspace/53.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/53.usbdev_tx_rx_disruption.1317797484
Short name T3524
Test name
Test status
Simulation time 569397155 ps
CPU time 1.73 seconds
Started Aug 17 06:11:04 PM PDT 24
Finished Aug 17 06:11:06 PM PDT 24
Peak memory 207508 kb
Host smart-f62262c6-4b14-4c28-a409-49668181cc91
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317797484 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.usbdev_tx_rx_disruption.1317797484
Directory /workspace/53.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/54.usbdev_endpoint_types.3402670446
Short name T3488
Test name
Test status
Simulation time 495030777 ps
CPU time 1.41 seconds
Started Aug 17 06:11:04 PM PDT 24
Finished Aug 17 06:11:05 PM PDT 24
Peak memory 207484 kb
Host smart-572bb37a-ddc2-46fb-8045-8628e5cf4a48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3402670446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.3402670446
Directory /workspace/54.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/54.usbdev_tx_rx_disruption.3962772829
Short name T2685
Test name
Test status
Simulation time 493933014 ps
CPU time 1.67 seconds
Started Aug 17 06:11:10 PM PDT 24
Finished Aug 17 06:11:12 PM PDT 24
Peak memory 207472 kb
Host smart-002e8eb9-224d-41e4-beec-6cfc1cc3e1b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962772829 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.usbdev_tx_rx_disruption.3962772829
Directory /workspace/54.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/55.usbdev_endpoint_types.3373283982
Short name T414
Test name
Test status
Simulation time 718006831 ps
CPU time 1.61 seconds
Started Aug 17 06:10:59 PM PDT 24
Finished Aug 17 06:11:01 PM PDT 24
Peak memory 207520 kb
Host smart-b8b8b63b-3ec0-46a0-9b90-3265f537c4c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3373283982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.3373283982
Directory /workspace/55.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/55.usbdev_tx_rx_disruption.25563000
Short name T1366
Test name
Test status
Simulation time 577596540 ps
CPU time 1.58 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207516 kb
Host smart-5bf5a5d0-98d7-423a-b196-5e557cd84a35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25563000 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 55.usbdev_tx_rx_disruption.25563000
Directory /workspace/55.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/56.usbdev_endpoint_types.81592205
Short name T1013
Test name
Test status
Simulation time 233492162 ps
CPU time 0.99 seconds
Started Aug 17 06:11:04 PM PDT 24
Finished Aug 17 06:11:05 PM PDT 24
Peak memory 207388 kb
Host smart-3f93ba50-07bf-46cc-9161-8a29e1c6a6a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=81592205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.81592205
Directory /workspace/56.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/56.usbdev_tx_rx_disruption.45165288
Short name T3247
Test name
Test status
Simulation time 626932520 ps
CPU time 1.76 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:10 PM PDT 24
Peak memory 207568 kb
Host smart-00a6da60-3347-4e31-9a1e-f26e739f5a03
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45165288 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 56.usbdev_tx_rx_disruption.45165288
Directory /workspace/56.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/57.usbdev_endpoint_types.4218118107
Short name T489
Test name
Test status
Simulation time 184042645 ps
CPU time 0.96 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207496 kb
Host smart-039562f8-11da-4ce3-b2c4-f9b4b229580c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4218118107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.4218118107
Directory /workspace/57.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/57.usbdev_tx_rx_disruption.3511466308
Short name T1705
Test name
Test status
Simulation time 539226144 ps
CPU time 1.66 seconds
Started Aug 17 06:10:58 PM PDT 24
Finished Aug 17 06:11:00 PM PDT 24
Peak memory 207568 kb
Host smart-3228e71e-1372-47e4-836b-ad7eb1fdf1b2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511466308 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.usbdev_tx_rx_disruption.3511466308
Directory /workspace/57.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/58.usbdev_endpoint_types.208581475
Short name T429
Test name
Test status
Simulation time 572983898 ps
CPU time 1.56 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207456 kb
Host smart-15bcf574-f955-4936-87be-03faec129691
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=208581475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.208581475
Directory /workspace/58.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/58.usbdev_tx_rx_disruption.2888801788
Short name T178
Test name
Test status
Simulation time 495460484 ps
CPU time 1.54 seconds
Started Aug 17 06:11:12 PM PDT 24
Finished Aug 17 06:11:13 PM PDT 24
Peak memory 207492 kb
Host smart-c5835826-cf9a-491e-9670-5fa778345dde
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888801788 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.usbdev_tx_rx_disruption.2888801788
Directory /workspace/58.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/59.usbdev_tx_rx_disruption.789708093
Short name T1259
Test name
Test status
Simulation time 628154029 ps
CPU time 1.59 seconds
Started Aug 17 06:11:09 PM PDT 24
Finished Aug 17 06:11:10 PM PDT 24
Peak memory 207604 kb
Host smart-26cf2061-e8eb-44b5-b9de-5f1419ce52db
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789708093 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 59.usbdev_tx_rx_disruption.789708093
Directory /workspace/59.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.3427072110
Short name T2095
Test name
Test status
Simulation time 38945734 ps
CPU time 0.7 seconds
Started Aug 17 06:04:06 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 207436 kb
Host smart-1c082dba-8d7e-4826-b2ba-ec60deb67867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3427072110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.3427072110
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3129154084
Short name T1829
Test name
Test status
Simulation time 10255277149 ps
CPU time 13.4 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:04:07 PM PDT 24
Peak memory 207720 kb
Host smart-0412dc7f-c1e4-4dc8-be65-5649c66138a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129154084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.3129154084
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.253219756
Short name T1047
Test name
Test status
Simulation time 18567869393 ps
CPU time 22.7 seconds
Started Aug 17 06:03:56 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 207780 kb
Host smart-f3ac359f-6eae-4ff4-be51-c463c75deda1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=253219756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.253219756
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2853693920
Short name T1353
Test name
Test status
Simulation time 29816894899 ps
CPU time 35.15 seconds
Started Aug 17 06:03:57 PM PDT 24
Finished Aug 17 06:04:32 PM PDT 24
Peak memory 207732 kb
Host smart-2f6cbdd7-ab69-4347-b9e8-f5e2263b635b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853693920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.2853693920
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2717943072
Short name T3442
Test name
Test status
Simulation time 160441162 ps
CPU time 0.92 seconds
Started Aug 17 06:04:01 PM PDT 24
Finished Aug 17 06:04:02 PM PDT 24
Peak memory 207392 kb
Host smart-6bba9bde-7a22-4ec0-94a3-a3b2068b9eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179
43072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2717943072
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1283836262
Short name T2413
Test name
Test status
Simulation time 209392375 ps
CPU time 0.97 seconds
Started Aug 17 06:03:55 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 207540 kb
Host smart-fe4c7ac2-7ee3-40f6-97e1-876a5bc9a428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12838
36262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1283836262
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.1393364481
Short name T1459
Test name
Test status
Simulation time 409158493 ps
CPU time 1.49 seconds
Started Aug 17 06:03:59 PM PDT 24
Finished Aug 17 06:04:01 PM PDT 24
Peak memory 207064 kb
Host smart-05cd0be5-72b7-4478-8caa-71cf24ac04c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13933
64481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.1393364481
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.856738444
Short name T1982
Test name
Test status
Simulation time 536543285 ps
CPU time 1.93 seconds
Started Aug 17 06:03:57 PM PDT 24
Finished Aug 17 06:03:59 PM PDT 24
Peak memory 207564 kb
Host smart-81051c35-33c7-4f0c-85f5-b0118a3b3ec8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=856738444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.856738444
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3595010397
Short name T2831
Test name
Test status
Simulation time 50644444362 ps
CPU time 92.4 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:05:27 PM PDT 24
Peak memory 207792 kb
Host smart-dda95393-6827-4f92-a3de-a24ddb668ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
10397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3595010397
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.914262418
Short name T2816
Test name
Test status
Simulation time 748119388 ps
CPU time 16.14 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:04:10 PM PDT 24
Peak memory 207732 kb
Host smart-de0fa156-59ed-4541-8432-8cd0b2b2c531
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914262418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.914262418
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.1004375571
Short name T3157
Test name
Test status
Simulation time 646519839 ps
CPU time 1.62 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 207496 kb
Host smart-6b2a31ca-d25a-4b2b-94bb-fa500a0f91f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10043
75571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.1004375571
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2235359386
Short name T1521
Test name
Test status
Simulation time 143625643 ps
CPU time 0.84 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:03:55 PM PDT 24
Peak memory 207504 kb
Host smart-67b36c63-adb2-48b2-8e85-75dbb81bcc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22353
59386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2235359386
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2925412658
Short name T2552
Test name
Test status
Simulation time 45973173 ps
CPU time 0.72 seconds
Started Aug 17 06:04:01 PM PDT 24
Finished Aug 17 06:04:02 PM PDT 24
Peak memory 207364 kb
Host smart-d4e25d44-abc1-4972-9d19-93d1610005f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29254
12658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2925412658
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.4131256642
Short name T1737
Test name
Test status
Simulation time 864060794 ps
CPU time 2.19 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 207744 kb
Host smart-2a00bdaf-6e99-45c7-ac11-14960d6d68cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41312
56642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.4131256642
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_types.3375338051
Short name T400
Test name
Test status
Simulation time 420929829 ps
CPU time 1.23 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:03:55 PM PDT 24
Peak memory 207508 kb
Host smart-910c4641-5343-4169-92dc-15723c85dbdf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3375338051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.3375338051
Directory /workspace/6.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2864645682
Short name T1886
Test name
Test status
Simulation time 194483145 ps
CPU time 2.29 seconds
Started Aug 17 06:03:53 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 207616 kb
Host smart-1a82048e-a58d-4a82-a177-029c0167e66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
45682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2864645682
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.133820251
Short name T1205
Test name
Test status
Simulation time 178904452 ps
CPU time 1.02 seconds
Started Aug 17 06:03:57 PM PDT 24
Finished Aug 17 06:03:59 PM PDT 24
Peak memory 215832 kb
Host smart-071c8a35-ae54-445c-8776-f04565b86733
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=133820251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.133820251
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.315858602
Short name T795
Test name
Test status
Simulation time 134465911 ps
CPU time 0.88 seconds
Started Aug 17 06:03:55 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 207388 kb
Host smart-40d3f9a3-a8ba-466b-b70a-e22f89554954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31585
8602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.315858602
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2811161239
Short name T1618
Test name
Test status
Simulation time 158311593 ps
CPU time 0.86 seconds
Started Aug 17 06:03:55 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 207464 kb
Host smart-59aefefc-1cff-4353-91be-439068089421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28111
61239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2811161239
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.2704105139
Short name T2921
Test name
Test status
Simulation time 4850259118 ps
CPU time 36.84 seconds
Started Aug 17 06:03:59 PM PDT 24
Finished Aug 17 06:04:36 PM PDT 24
Peak memory 215720 kb
Host smart-b9043750-6fac-42dc-a4c8-1f8b46b75368
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2704105139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.2704105139
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.2834983331
Short name T1560
Test name
Test status
Simulation time 5165432945 ps
CPU time 40.28 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:04:34 PM PDT 24
Peak memory 207712 kb
Host smart-ae2b4c86-59b6-49df-922f-22d3e93fb56c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2834983331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.2834983331
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.998951841
Short name T717
Test name
Test status
Simulation time 203075066 ps
CPU time 0.92 seconds
Started Aug 17 06:03:56 PM PDT 24
Finished Aug 17 06:03:57 PM PDT 24
Peak memory 207480 kb
Host smart-dbb87bb2-19e0-4847-88a4-1919109a0901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99895
1841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.998951841
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2153308896
Short name T224
Test name
Test status
Simulation time 13694593559 ps
CPU time 20.03 seconds
Started Aug 17 06:03:56 PM PDT 24
Finished Aug 17 06:04:16 PM PDT 24
Peak memory 207764 kb
Host smart-a04b7af0-b7bc-4c9a-8ed9-464005e60c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21533
08896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2153308896
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.884876941
Short name T1077
Test name
Test status
Simulation time 11362344118 ps
CPU time 13.93 seconds
Started Aug 17 06:03:56 PM PDT 24
Finished Aug 17 06:04:10 PM PDT 24
Peak memory 207716 kb
Host smart-101f0770-a759-44e5-a59e-daf5a53484d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88487
6941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.884876941
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.630578596
Short name T2940
Test name
Test status
Simulation time 3854823109 ps
CPU time 40.8 seconds
Started Aug 17 06:04:01 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 224092 kb
Host smart-d3cdaa1e-832b-4d50-8ba4-c4ca14cbb84a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=630578596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.630578596
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3474472029
Short name T1189
Test name
Test status
Simulation time 2099533603 ps
CPU time 62.33 seconds
Started Aug 17 06:04:18 PM PDT 24
Finished Aug 17 06:05:20 PM PDT 24
Peak memory 215852 kb
Host smart-b8d04759-d062-4a53-86eb-5dcc12658f25
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3474472029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3474472029
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.1017886018
Short name T1354
Test name
Test status
Simulation time 258279504 ps
CPU time 1.04 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:03:56 PM PDT 24
Peak memory 207488 kb
Host smart-f313af1a-d375-492f-9978-0d62bcf8408c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1017886018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.1017886018
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.379198391
Short name T313
Test name
Test status
Simulation time 201183716 ps
CPU time 1.05 seconds
Started Aug 17 06:03:55 PM PDT 24
Finished Aug 17 06:03:57 PM PDT 24
Peak memory 207448 kb
Host smart-e46ac51e-a2b7-435e-ba8c-37ac1cdee5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37919
8391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.379198391
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.387951953
Short name T3125
Test name
Test status
Simulation time 1808105153 ps
CPU time 17.83 seconds
Started Aug 17 06:03:53 PM PDT 24
Finished Aug 17 06:04:11 PM PDT 24
Peak memory 222952 kb
Host smart-fa4114c2-b914-46ca-8da1-79e32439815e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38795
1953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.387951953
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.114663616
Short name T3101
Test name
Test status
Simulation time 2900578894 ps
CPU time 85.59 seconds
Started Aug 17 06:03:56 PM PDT 24
Finished Aug 17 06:05:22 PM PDT 24
Peak memory 218620 kb
Host smart-10dd64dd-c2e3-4bb8-8a27-b6b33a2a29ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=114663616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.114663616
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.169946922
Short name T1419
Test name
Test status
Simulation time 2181345141 ps
CPU time 21.88 seconds
Started Aug 17 06:03:55 PM PDT 24
Finished Aug 17 06:04:17 PM PDT 24
Peak memory 216508 kb
Host smart-5a61db9b-a4cc-42d4-a76a-d1d176ab7aed
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=169946922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.169946922
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.371904797
Short name T867
Test name
Test status
Simulation time 193110734 ps
CPU time 0.94 seconds
Started Aug 17 06:03:54 PM PDT 24
Finished Aug 17 06:03:55 PM PDT 24
Peak memory 207456 kb
Host smart-643ce297-aaf6-468b-abfa-ff7ceddee413
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=371904797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.371904797
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.795194441
Short name T2493
Test name
Test status
Simulation time 162144475 ps
CPU time 0.85 seconds
Started Aug 17 06:03:58 PM PDT 24
Finished Aug 17 06:03:59 PM PDT 24
Peak memory 207432 kb
Host smart-a7264fd8-888f-433e-a022-fcb246ecf0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79519
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.795194441
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1776321537
Short name T3499
Test name
Test status
Simulation time 237828548 ps
CPU time 0.99 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:05 PM PDT 24
Peak memory 207532 kb
Host smart-26ba684c-bc46-4743-b6dd-d67e61500075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17763
21537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1776321537
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2139919585
Short name T1397
Test name
Test status
Simulation time 190298578 ps
CPU time 1.02 seconds
Started Aug 17 06:04:03 PM PDT 24
Finished Aug 17 06:04:04 PM PDT 24
Peak memory 207368 kb
Host smart-b788d67b-fc14-45eb-89a6-2115038a331c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21399
19585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2139919585
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2517339820
Short name T689
Test name
Test status
Simulation time 176841124 ps
CPU time 0.88 seconds
Started Aug 17 06:04:06 PM PDT 24
Finished Aug 17 06:04:07 PM PDT 24
Peak memory 207472 kb
Host smart-eeaaa2fa-2b8a-4f3f-bab2-89cd9c868ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25173
39820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2517339820
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2265679641
Short name T2269
Test name
Test status
Simulation time 166434386 ps
CPU time 0.86 seconds
Started Aug 17 06:04:10 PM PDT 24
Finished Aug 17 06:04:11 PM PDT 24
Peak memory 207488 kb
Host smart-5d083136-0020-4a89-9834-b8b5b16c61ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22656
79641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2265679641
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1413241120
Short name T2677
Test name
Test status
Simulation time 202119105 ps
CPU time 0.95 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:05 PM PDT 24
Peak memory 207500 kb
Host smart-ec39ec34-cb84-409b-9e90-64ed733af4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14132
41120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1413241120
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.895806933
Short name T3172
Test name
Test status
Simulation time 201817764 ps
CPU time 1.05 seconds
Started Aug 17 06:04:06 PM PDT 24
Finished Aug 17 06:04:07 PM PDT 24
Peak memory 207488 kb
Host smart-712b8226-67cd-48a2-8515-f77be835d725
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=895806933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.895806933
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.1957208595
Short name T3357
Test name
Test status
Simulation time 146267453 ps
CPU time 0.9 seconds
Started Aug 17 06:04:03 PM PDT 24
Finished Aug 17 06:04:04 PM PDT 24
Peak memory 207436 kb
Host smart-cb038c5d-525a-45b2-8487-45c336ce3a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19572
08595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1957208595
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.503683459
Short name T2989
Test name
Test status
Simulation time 34173173 ps
CPU time 0.7 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 207472 kb
Host smart-c0c1b27b-fadf-4c87-aff8-e854cee95f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50368
3459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.503683459
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.156921304
Short name T315
Test name
Test status
Simulation time 21233630874 ps
CPU time 56.9 seconds
Started Aug 17 06:04:03 PM PDT 24
Finished Aug 17 06:05:00 PM PDT 24
Peak memory 215916 kb
Host smart-727aeb66-befe-42bc-8354-17986618c744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15692
1304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.156921304
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.504937138
Short name T1997
Test name
Test status
Simulation time 235372303 ps
CPU time 0.94 seconds
Started Aug 17 06:04:13 PM PDT 24
Finished Aug 17 06:04:14 PM PDT 24
Peak memory 207012 kb
Host smart-bb74449f-c825-4e94-98b0-c1f93d3c4150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50493
7138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.504937138
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1294064585
Short name T1481
Test name
Test status
Simulation time 181097718 ps
CPU time 0.93 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 207428 kb
Host smart-47aac8af-7420-4d2a-ab15-2691454cfae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12940
64585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1294064585
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3319549004
Short name T1317
Test name
Test status
Simulation time 6292151216 ps
CPU time 28.92 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:34 PM PDT 24
Peak memory 224220 kb
Host smart-79a3d85d-9ed8-498e-b5d4-28bb8eeca8d1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3319549004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3319549004
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2935593559
Short name T1541
Test name
Test status
Simulation time 7169045949 ps
CPU time 35.72 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:40 PM PDT 24
Peak memory 224164 kb
Host smart-4afe7eb3-f3f3-4c26-834e-0427e72c2b13
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935593559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2935593559
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1970632245
Short name T1303
Test name
Test status
Simulation time 226763933 ps
CPU time 1.02 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 207464 kb
Host smart-0a0aa9b6-6465-4042-b3e4-5bf66c9627dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19706
32245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1970632245
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3008714603
Short name T2148
Test name
Test status
Simulation time 162962049 ps
CPU time 0.89 seconds
Started Aug 17 06:04:01 PM PDT 24
Finished Aug 17 06:04:02 PM PDT 24
Peak memory 207460 kb
Host smart-b5fbb9a7-bdf3-4119-b93d-ecc1161a4fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30087
14603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3008714603
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_resume_link_active.2652099044
Short name T3366
Test name
Test status
Simulation time 20160865884 ps
CPU time 27.06 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:32 PM PDT 24
Peak memory 207564 kb
Host smart-6d0e2a55-2eba-4937-9bf7-5057bf883d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26520
99044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.2652099044
Directory /workspace/6.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.867363130
Short name T2560
Test name
Test status
Simulation time 180603362 ps
CPU time 0.94 seconds
Started Aug 17 06:04:06 PM PDT 24
Finished Aug 17 06:04:07 PM PDT 24
Peak memory 207472 kb
Host smart-5a9f7c7a-dd29-4370-96a5-5c799dcb581f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86736
3130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.867363130
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_rx_full.3468235591
Short name T705
Test name
Test status
Simulation time 394860165 ps
CPU time 1.42 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:05 PM PDT 24
Peak memory 207460 kb
Host smart-4275cf3c-0edf-4243-94f1-7abb1d3c4731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34682
35591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.3468235591
Directory /workspace/6.usbdev_rx_full/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4086705062
Short name T3576
Test name
Test status
Simulation time 159464186 ps
CPU time 0.89 seconds
Started Aug 17 06:04:03 PM PDT 24
Finished Aug 17 06:04:04 PM PDT 24
Peak memory 207444 kb
Host smart-4b82307c-5338-4675-a526-e84114a38f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40867
05062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4086705062
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2019818970
Short name T269
Test name
Test status
Simulation time 219884603 ps
CPU time 0.99 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:05 PM PDT 24
Peak memory 207552 kb
Host smart-d9984933-ba6f-481f-babb-3401dba83d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20198
18970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2019818970
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3131235011
Short name T3517
Test name
Test status
Simulation time 225764821 ps
CPU time 1.05 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:05 PM PDT 24
Peak memory 207460 kb
Host smart-a668f802-33b8-43a5-9520-7be544c73a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31312
35011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3131235011
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2559085038
Short name T1409
Test name
Test status
Simulation time 1983918515 ps
CPU time 57.66 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:05:03 PM PDT 24
Peak memory 223940 kb
Host smart-f136f7ce-1efb-403d-afef-e173a3b461a5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2559085038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2559085038
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1832296118
Short name T3556
Test name
Test status
Simulation time 223233124 ps
CPU time 0.98 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:05 PM PDT 24
Peak memory 207492 kb
Host smart-0a44b1e2-1839-4833-a6fb-284ca5a21a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18322
96118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1832296118
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1554886434
Short name T1933
Test name
Test status
Simulation time 168687740 ps
CPU time 0.93 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 207472 kb
Host smart-a4da1c5e-4380-41f5-85f2-9175f4227be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15548
86434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1554886434
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.3774343307
Short name T1643
Test name
Test status
Simulation time 1040604044 ps
CPU time 2.56 seconds
Started Aug 17 06:04:03 PM PDT 24
Finished Aug 17 06:04:05 PM PDT 24
Peak memory 207684 kb
Host smart-3e5eb4cf-444a-4868-a866-260ab6c3c2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37743
43307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.3774343307
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3650724975
Short name T1146
Test name
Test status
Simulation time 2394003594 ps
CPU time 20.27 seconds
Started Aug 17 06:04:03 PM PDT 24
Finished Aug 17 06:04:23 PM PDT 24
Peak memory 217696 kb
Host smart-0edbf8ba-3c08-42a6-b84a-00a9857434e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36507
24975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3650724975
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.584337730
Short name T1958
Test name
Test status
Simulation time 2948617124 ps
CPU time 20.57 seconds
Started Aug 17 06:04:01 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207640 kb
Host smart-aed8800e-81fd-473c-82bb-eb9493a500d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584337730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host_
handshake.584337730
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_tx_rx_disruption.126643852
Short name T207
Test name
Test status
Simulation time 494778019 ps
CPU time 1.54 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 207540 kb
Host smart-aa41a21b-ac7e-4e1b-a3aa-22b60f499806
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126643852 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.usbdev_tx_rx_disruption.126643852
Directory /workspace/6.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/60.usbdev_endpoint_types.3442776687
Short name T495
Test name
Test status
Simulation time 345169499 ps
CPU time 1.23 seconds
Started Aug 17 06:11:08 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207524 kb
Host smart-482fda87-775c-4e5b-8f87-a3549eca171c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3442776687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.3442776687
Directory /workspace/60.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/60.usbdev_tx_rx_disruption.536782783
Short name T2837
Test name
Test status
Simulation time 582660884 ps
CPU time 1.72 seconds
Started Aug 17 06:11:11 PM PDT 24
Finished Aug 17 06:11:13 PM PDT 24
Peak memory 207580 kb
Host smart-ad692133-95cd-4507-835a-5b66412c3880
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536782783 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 60.usbdev_tx_rx_disruption.536782783
Directory /workspace/60.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/61.usbdev_endpoint_types.749291478
Short name T1663
Test name
Test status
Simulation time 208915490 ps
CPU time 1.02 seconds
Started Aug 17 06:11:23 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207520 kb
Host smart-77a4010a-eacf-48ad-800b-b887ef3f8db8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=749291478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.749291478
Directory /workspace/61.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/61.usbdev_tx_rx_disruption.4113775336
Short name T3408
Test name
Test status
Simulation time 512231360 ps
CPU time 1.47 seconds
Started Aug 17 06:11:25 PM PDT 24
Finished Aug 17 06:11:26 PM PDT 24
Peak memory 207564 kb
Host smart-afd6e7c6-84e8-4953-8006-1c69224b20e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113775336 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.usbdev_tx_rx_disruption.4113775336
Directory /workspace/61.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/62.usbdev_endpoint_types.3752608095
Short name T3046
Test name
Test status
Simulation time 163078550 ps
CPU time 0.84 seconds
Started Aug 17 06:11:23 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207524 kb
Host smart-147551d3-6fa5-485f-87a2-941602d5c9aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3752608095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.3752608095
Directory /workspace/62.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/62.usbdev_tx_rx_disruption.788948598
Short name T905
Test name
Test status
Simulation time 505692921 ps
CPU time 1.54 seconds
Started Aug 17 06:11:14 PM PDT 24
Finished Aug 17 06:11:16 PM PDT 24
Peak memory 207500 kb
Host smart-38ffc1cf-503b-444e-a742-5305be2f48de
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788948598 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 62.usbdev_tx_rx_disruption.788948598
Directory /workspace/62.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/63.usbdev_endpoint_types.646136860
Short name T459
Test name
Test status
Simulation time 383986022 ps
CPU time 1.19 seconds
Started Aug 17 06:11:23 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 207524 kb
Host smart-ee6a8a7d-4245-47a0-b017-213e0ed76237
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=646136860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.646136860
Directory /workspace/63.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/63.usbdev_tx_rx_disruption.2724597006
Short name T594
Test name
Test status
Simulation time 474699074 ps
CPU time 1.53 seconds
Started Aug 17 06:11:13 PM PDT 24
Finished Aug 17 06:11:14 PM PDT 24
Peak memory 207540 kb
Host smart-1e3f3315-9e92-42bb-8c11-71727df83a27
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724597006 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.usbdev_tx_rx_disruption.2724597006
Directory /workspace/63.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/64.usbdev_endpoint_types.242943621
Short name T508
Test name
Test status
Simulation time 424862471 ps
CPU time 1.33 seconds
Started Aug 17 06:11:06 PM PDT 24
Finished Aug 17 06:11:08 PM PDT 24
Peak memory 207460 kb
Host smart-67cf5d7d-5d3f-46d8-870f-00b0d8cd142c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=242943621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.242943621
Directory /workspace/64.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/64.usbdev_tx_rx_disruption.1966396601
Short name T2002
Test name
Test status
Simulation time 549379018 ps
CPU time 1.77 seconds
Started Aug 17 06:11:21 PM PDT 24
Finished Aug 17 06:11:23 PM PDT 24
Peak memory 207560 kb
Host smart-c3ceb025-a485-480f-92dd-5ed6ee4e9f09
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966396601 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.usbdev_tx_rx_disruption.1966396601
Directory /workspace/64.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/65.usbdev_endpoint_types.3796674510
Short name T481
Test name
Test status
Simulation time 284239789 ps
CPU time 1.11 seconds
Started Aug 17 06:11:17 PM PDT 24
Finished Aug 17 06:11:18 PM PDT 24
Peak memory 207488 kb
Host smart-f406d6e6-f213-4913-b400-6ba88edcee1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3796674510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.3796674510
Directory /workspace/65.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/65.usbdev_tx_rx_disruption.1377178259
Short name T3066
Test name
Test status
Simulation time 504504553 ps
CPU time 1.58 seconds
Started Aug 17 06:11:13 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207552 kb
Host smart-dba9b558-04e6-404b-acb3-28b4ccff56e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377178259 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.usbdev_tx_rx_disruption.1377178259
Directory /workspace/65.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/66.usbdev_endpoint_types.2695465763
Short name T2500
Test name
Test status
Simulation time 167636919 ps
CPU time 0.92 seconds
Started Aug 17 06:11:25 PM PDT 24
Finished Aug 17 06:11:26 PM PDT 24
Peak memory 207564 kb
Host smart-ef86f8ab-3679-4391-bee9-5ef87b099613
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2695465763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.2695465763
Directory /workspace/66.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/66.usbdev_tx_rx_disruption.2062751236
Short name T3092
Test name
Test status
Simulation time 578026324 ps
CPU time 1.6 seconds
Started Aug 17 06:11:24 PM PDT 24
Finished Aug 17 06:11:26 PM PDT 24
Peak memory 207568 kb
Host smart-1e784eae-9695-49d5-add6-eb221b96cda1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062751236 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.usbdev_tx_rx_disruption.2062751236
Directory /workspace/66.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/67.usbdev_endpoint_types.2273240466
Short name T453
Test name
Test status
Simulation time 788362750 ps
CPU time 1.88 seconds
Started Aug 17 06:11:15 PM PDT 24
Finished Aug 17 06:11:17 PM PDT 24
Peak memory 207504 kb
Host smart-c466ec8a-a43b-4a85-b737-6a42efb50d71
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2273240466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.2273240466
Directory /workspace/67.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/67.usbdev_tx_rx_disruption.1631139564
Short name T848
Test name
Test status
Simulation time 648019354 ps
CPU time 1.85 seconds
Started Aug 17 06:11:20 PM PDT 24
Finished Aug 17 06:11:22 PM PDT 24
Peak memory 207568 kb
Host smart-d100f7d2-5cd3-4d15-99fa-686549391749
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631139564 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.usbdev_tx_rx_disruption.1631139564
Directory /workspace/67.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/68.usbdev_endpoint_types.160124143
Short name T474
Test name
Test status
Simulation time 516429414 ps
CPU time 1.45 seconds
Started Aug 17 06:11:35 PM PDT 24
Finished Aug 17 06:11:36 PM PDT 24
Peak memory 207500 kb
Host smart-2f8e92bf-40e4-4178-a33c-84c11a4d4fa9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=160124143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.160124143
Directory /workspace/68.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/68.usbdev_tx_rx_disruption.2131091727
Short name T3334
Test name
Test status
Simulation time 656203791 ps
CPU time 1.86 seconds
Started Aug 17 06:11:19 PM PDT 24
Finished Aug 17 06:11:21 PM PDT 24
Peak memory 207568 kb
Host smart-bfb8659f-b875-4f35-8a92-c1d079dfa531
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131091727 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.usbdev_tx_rx_disruption.2131091727
Directory /workspace/68.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/69.usbdev_endpoint_types.1254074707
Short name T423
Test name
Test status
Simulation time 495347153 ps
CPU time 1.42 seconds
Started Aug 17 06:11:13 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207508 kb
Host smart-5961908c-777d-4ddc-831f-d8d1846a3577
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1254074707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.1254074707
Directory /workspace/69.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/69.usbdev_tx_rx_disruption.3824303318
Short name T245
Test name
Test status
Simulation time 637048486 ps
CPU time 1.98 seconds
Started Aug 17 06:11:17 PM PDT 24
Finished Aug 17 06:11:20 PM PDT 24
Peak memory 207572 kb
Host smart-021b6021-cf2d-46cb-aecc-89510a955ad9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824303318 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.usbdev_tx_rx_disruption.3824303318
Directory /workspace/69.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.186369579
Short name T734
Test name
Test status
Simulation time 53150053 ps
CPU time 0.7 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:21 PM PDT 24
Peak memory 207372 kb
Host smart-6913b826-8efd-496d-8ed1-385d348d15fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=186369579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.186369579
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3618725691
Short name T1183
Test name
Test status
Simulation time 4628664977 ps
CPU time 6.53 seconds
Started Aug 17 06:04:03 PM PDT 24
Finished Aug 17 06:04:10 PM PDT 24
Peak memory 215984 kb
Host smart-71693dd1-23bf-4181-b7ff-d06504e3b663
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618725691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.3618725691
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1250263671
Short name T3308
Test name
Test status
Simulation time 19868296926 ps
CPU time 25.35 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:29 PM PDT 24
Peak memory 207764 kb
Host smart-728cf37b-093e-4606-b9ae-ea166f53b989
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250263671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1250263671
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3542030785
Short name T249
Test name
Test status
Simulation time 30872265326 ps
CPU time 34.76 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:40 PM PDT 24
Peak memory 207752 kb
Host smart-c5c74e75-0140-4d29-aaf3-59fd0213528c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542030785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.3542030785
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.146673750
Short name T1869
Test name
Test status
Simulation time 152051603 ps
CPU time 0.85 seconds
Started Aug 17 06:04:06 PM PDT 24
Finished Aug 17 06:04:07 PM PDT 24
Peak memory 207476 kb
Host smart-676575ab-9da5-43aa-b285-47572a0c3143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14667
3750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.146673750
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1391982916
Short name T884
Test name
Test status
Simulation time 167121346 ps
CPU time 0.92 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 207444 kb
Host smart-d7b12363-32b1-453a-8483-6ca411fb1e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919
82916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1391982916
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.611543363
Short name T1836
Test name
Test status
Simulation time 518859736 ps
CPU time 1.6 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:05 PM PDT 24
Peak memory 207556 kb
Host smart-74df9018-5537-4a8b-8b01-05f6287f8bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61154
3363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.611543363
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.4213477565
Short name T1930
Test name
Test status
Simulation time 397057370 ps
CPU time 1.32 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:05 PM PDT 24
Peak memory 207616 kb
Host smart-79546b8a-8de9-4f3c-b43b-372a44605fdd
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4213477565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.4213477565
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.3193151557
Short name T2173
Test name
Test status
Simulation time 18219940122 ps
CPU time 29.7 seconds
Started Aug 17 06:04:07 PM PDT 24
Finished Aug 17 06:04:37 PM PDT 24
Peak memory 207796 kb
Host smart-4ed871aa-7ca9-45cd-af8c-adce87a3d6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31931
51557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.3193151557
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.437030310
Short name T1468
Test name
Test status
Simulation time 1393238122 ps
CPU time 32.92 seconds
Started Aug 17 06:04:04 PM PDT 24
Finished Aug 17 06:04:37 PM PDT 24
Peak memory 207760 kb
Host smart-12eecdff-ba0c-4a54-9228-63cadec02bbe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437030310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.437030310
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.4051373376
Short name T128
Test name
Test status
Simulation time 765408017 ps
CPU time 2.1 seconds
Started Aug 17 06:04:13 PM PDT 24
Finished Aug 17 06:04:15 PM PDT 24
Peak memory 207520 kb
Host smart-f8f74526-4609-4995-9d1f-449766f04fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40513
73376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.4051373376
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3725692057
Short name T1985
Test name
Test status
Simulation time 140729993 ps
CPU time 0.87 seconds
Started Aug 17 06:04:05 PM PDT 24
Finished Aug 17 06:04:06 PM PDT 24
Peak memory 207472 kb
Host smart-b938fd5f-2141-4e6b-948f-8509d0f60a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37256
92057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3725692057
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3856781438
Short name T1404
Test name
Test status
Simulation time 43870748 ps
CPU time 0.75 seconds
Started Aug 17 06:04:11 PM PDT 24
Finished Aug 17 06:04:12 PM PDT 24
Peak memory 207428 kb
Host smart-39e30e07-1dff-4647-9b0d-d6105b572ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567
81438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3856781438
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3940980849
Short name T2839
Test name
Test status
Simulation time 935559463 ps
CPU time 2.44 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:04:19 PM PDT 24
Peak memory 207784 kb
Host smart-5fef1c62-a4cb-4608-aebd-60a01da79163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39409
80849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3940980849
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2451396367
Short name T1465
Test name
Test status
Simulation time 313373252 ps
CPU time 2.74 seconds
Started Aug 17 06:04:12 PM PDT 24
Finished Aug 17 06:04:15 PM PDT 24
Peak memory 207652 kb
Host smart-ef4a1423-870a-497a-bab3-f83efab7b07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513
96367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2451396367
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3103483250
Short name T641
Test name
Test status
Simulation time 180401931 ps
CPU time 0.93 seconds
Started Aug 17 06:04:11 PM PDT 24
Finished Aug 17 06:04:12 PM PDT 24
Peak memory 207468 kb
Host smart-a0da29f4-86c0-4c98-b8d3-4bad7915fd29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3103483250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3103483250
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2513313652
Short name T968
Test name
Test status
Simulation time 139598518 ps
CPU time 0.86 seconds
Started Aug 17 06:04:14 PM PDT 24
Finished Aug 17 06:04:15 PM PDT 24
Peak memory 207324 kb
Host smart-4d448367-8230-4885-aab8-672bff1077d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25133
13652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2513313652
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2286831148
Short name T1490
Test name
Test status
Simulation time 240674042 ps
CPU time 1.03 seconds
Started Aug 17 06:04:11 PM PDT 24
Finished Aug 17 06:04:12 PM PDT 24
Peak memory 207484 kb
Host smart-a74377c7-a36f-43b8-9edc-d6b5ae1f5072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22868
31148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2286831148
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1019259044
Short name T2411
Test name
Test status
Simulation time 3399918014 ps
CPU time 27.29 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:04:44 PM PDT 24
Peak memory 224156 kb
Host smart-1acab242-f745-4182-acb9-3e9b131a09e3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1019259044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1019259044
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.1612964038
Short name T2899
Test name
Test status
Simulation time 10767965755 ps
CPU time 136.37 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:06:34 PM PDT 24
Peak memory 207744 kb
Host smart-6883cbdc-2301-4fc1-8719-c081415bb9ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1612964038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.1612964038
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3255891185
Short name T2962
Test name
Test status
Simulation time 175221522 ps
CPU time 0.92 seconds
Started Aug 17 06:04:11 PM PDT 24
Finished Aug 17 06:04:12 PM PDT 24
Peak memory 207484 kb
Host smart-13214a69-fae1-4fd0-8831-da573e87dedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32558
91185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3255891185
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.484698350
Short name T2311
Test name
Test status
Simulation time 6539201104 ps
CPU time 11.01 seconds
Started Aug 17 06:04:11 PM PDT 24
Finished Aug 17 06:04:23 PM PDT 24
Peak memory 216048 kb
Host smart-ceed79a0-8749-4719-88ee-7f6e4816c8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48469
8350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.484698350
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1700487624
Short name T2607
Test name
Test status
Simulation time 5065515205 ps
CPU time 6.58 seconds
Started Aug 17 06:04:12 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 216036 kb
Host smart-aafb1c20-6906-45d8-9897-880ded529fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17004
87624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1700487624
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1163204610
Short name T3180
Test name
Test status
Simulation time 4036210125 ps
CPU time 119.63 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:06:16 PM PDT 24
Peak memory 218624 kb
Host smart-d2fe4a4e-3452-4f9d-91f7-4cd444a5f6d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1163204610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1163204610
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.699806241
Short name T1282
Test name
Test status
Simulation time 2087456004 ps
CPU time 62.04 seconds
Started Aug 17 06:04:11 PM PDT 24
Finished Aug 17 06:05:13 PM PDT 24
Peak memory 216900 kb
Host smart-4d23463b-a495-4e63-bd27-a0083ba0f2d6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=699806241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.699806241
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.3047257342
Short name T2379
Test name
Test status
Simulation time 242453284 ps
CPU time 0.98 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 207476 kb
Host smart-6014a48e-1163-45d7-8122-60dc06d4f812
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3047257342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.3047257342
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3107951722
Short name T1809
Test name
Test status
Simulation time 191132956 ps
CPU time 0.97 seconds
Started Aug 17 06:04:08 PM PDT 24
Finished Aug 17 06:04:09 PM PDT 24
Peak memory 207480 kb
Host smart-86f3566d-1bd7-490e-9be1-2c15abd1b1e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31079
51722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3107951722
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.3566531786
Short name T2404
Test name
Test status
Simulation time 2026167302 ps
CPU time 54.37 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:05:11 PM PDT 24
Peak memory 217416 kb
Host smart-d3702e52-93e3-469d-9ef3-2ae1cbf6a005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35665
31786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.3566531786
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2729181818
Short name T2263
Test name
Test status
Simulation time 2429742856 ps
CPU time 72.74 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:05:30 PM PDT 24
Peak memory 223944 kb
Host smart-ea2ca6a0-0d31-4980-92f8-cc2439d3dc17
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2729181818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2729181818
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2417265122
Short name T186
Test name
Test status
Simulation time 3180152475 ps
CPU time 92.95 seconds
Started Aug 17 06:04:12 PM PDT 24
Finished Aug 17 06:05:45 PM PDT 24
Peak memory 217608 kb
Host smart-5d963dda-6bb8-490c-9688-7470706ac72e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2417265122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2417265122
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2050014509
Short name T2299
Test name
Test status
Simulation time 168542231 ps
CPU time 0.89 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 207492 kb
Host smart-acc032e8-165d-4cb8-97d9-18f31909a3fc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2050014509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2050014509
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.613508181
Short name T3425
Test name
Test status
Simulation time 139787728 ps
CPU time 0.84 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 207476 kb
Host smart-a0f003f8-50c9-42ea-b69f-387cc88420df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61350
8181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.613508181
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3368232852
Short name T2424
Test name
Test status
Simulation time 210219115 ps
CPU time 0.92 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 207484 kb
Host smart-b9194a06-bb24-4f6c-8261-b26f8ffe1fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33682
32852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3368232852
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1133545591
Short name T2850
Test name
Test status
Simulation time 188180814 ps
CPU time 0.98 seconds
Started Aug 17 06:04:16 PM PDT 24
Finished Aug 17 06:04:17 PM PDT 24
Peak memory 207480 kb
Host smart-f4b9778b-ca99-4c1d-9a32-e88c6067c684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11335
45591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1133545591
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2916019672
Short name T2170
Test name
Test status
Simulation time 187237573 ps
CPU time 0.95 seconds
Started Aug 17 06:04:10 PM PDT 24
Finished Aug 17 06:04:11 PM PDT 24
Peak memory 207376 kb
Host smart-afbd485a-7b71-4935-9bc4-d1192a5a1c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29160
19672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2916019672
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3514851334
Short name T3225
Test name
Test status
Simulation time 179407772 ps
CPU time 0.97 seconds
Started Aug 17 06:04:12 PM PDT 24
Finished Aug 17 06:04:13 PM PDT 24
Peak memory 207536 kb
Host smart-dc9e1fb3-dd80-4657-b007-d8ccf7fdaac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35148
51334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3514851334
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.624162860
Short name T213
Test name
Test status
Simulation time 146866368 ps
CPU time 0.83 seconds
Started Aug 17 06:04:10 PM PDT 24
Finished Aug 17 06:04:11 PM PDT 24
Peak memory 207548 kb
Host smart-7af7f0c0-f42e-40c5-9b30-c259c946cbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62416
2860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.624162860
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.807477659
Short name T2005
Test name
Test status
Simulation time 261930161 ps
CPU time 1.12 seconds
Started Aug 17 06:04:16 PM PDT 24
Finished Aug 17 06:04:17 PM PDT 24
Peak memory 207548 kb
Host smart-3f145c26-5f2a-407e-a666-9e589b6d3278
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=807477659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.807477659
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.4227376440
Short name T789
Test name
Test status
Simulation time 139091984 ps
CPU time 0.86 seconds
Started Aug 17 06:04:17 PM PDT 24
Finished Aug 17 06:04:18 PM PDT 24
Peak memory 207452 kb
Host smart-203dc773-4bac-4ab1-8e8d-8e59e5a86863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42273
76440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.4227376440
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2637782897
Short name T2577
Test name
Test status
Simulation time 50495386 ps
CPU time 0.71 seconds
Started Aug 17 06:04:11 PM PDT 24
Finished Aug 17 06:04:11 PM PDT 24
Peak memory 207524 kb
Host smart-9db668f2-9547-425f-a22f-f6dcea36aea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26377
82897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2637782897
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.483463066
Short name T278
Test name
Test status
Simulation time 15735853801 ps
CPU time 41.77 seconds
Started Aug 17 06:04:12 PM PDT 24
Finished Aug 17 06:04:54 PM PDT 24
Peak memory 220300 kb
Host smart-13dd13e7-0053-4431-93e1-44ecbfaa15bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48346
3066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.483463066
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1321086781
Short name T3166
Test name
Test status
Simulation time 216749609 ps
CPU time 0.92 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207476 kb
Host smart-ac34aa41-6af0-439c-9141-1b66cd1b4fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13210
86781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1321086781
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1051493120
Short name T1215
Test name
Test status
Simulation time 221240434 ps
CPU time 0.96 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:21 PM PDT 24
Peak memory 207444 kb
Host smart-22629d91-7284-47a1-a4dd-dca6a055d27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10514
93120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1051493120
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1519556508
Short name T1591
Test name
Test status
Simulation time 5322307542 ps
CPU time 23.43 seconds
Started Aug 17 06:04:19 PM PDT 24
Finished Aug 17 06:04:43 PM PDT 24
Peak memory 219784 kb
Host smart-dca77895-48f0-4a43-8e03-bd24efc31293
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519556508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1519556508
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.648348352
Short name T2050
Test name
Test status
Simulation time 7233519872 ps
CPU time 66.72 seconds
Started Aug 17 06:04:18 PM PDT 24
Finished Aug 17 06:05:25 PM PDT 24
Peak memory 224176 kb
Host smart-0b736cb0-987e-4d2b-aff3-a2b56892c05a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=648348352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.648348352
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.4221345392
Short name T1742
Test name
Test status
Simulation time 9591665783 ps
CPU time 193.71 seconds
Started Aug 17 06:04:19 PM PDT 24
Finished Aug 17 06:07:33 PM PDT 24
Peak memory 215988 kb
Host smart-ad5c747f-6768-41be-8748-723167c9a360
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221345392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.4221345392
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.1695609001
Short name T309
Test name
Test status
Simulation time 180341141 ps
CPU time 0.9 seconds
Started Aug 17 06:04:18 PM PDT 24
Finished Aug 17 06:04:19 PM PDT 24
Peak memory 207460 kb
Host smart-a1fb8b65-e1b1-48c3-88dd-ecd8ee828cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16956
09001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1695609001
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2080009346
Short name T3634
Test name
Test status
Simulation time 184354267 ps
CPU time 0.91 seconds
Started Aug 17 06:04:19 PM PDT 24
Finished Aug 17 06:04:20 PM PDT 24
Peak memory 207480 kb
Host smart-ef98ccd3-6e15-4241-be66-258f613a9ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
09346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2080009346
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_resume_link_active.2088161003
Short name T2945
Test name
Test status
Simulation time 20155395777 ps
CPU time 24.03 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:45 PM PDT 24
Peak memory 207516 kb
Host smart-32a65333-5b25-432c-ab1d-823497e3d865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20881
61003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.2088161003
Directory /workspace/7.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.497769852
Short name T353
Test name
Test status
Simulation time 152842121 ps
CPU time 0.83 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207400 kb
Host smart-c48336a0-9dd8-46e4-948b-bf230921e2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49776
9852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.497769852
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_rx_full.3351868359
Short name T2330
Test name
Test status
Simulation time 269900330 ps
CPU time 1.15 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207456 kb
Host smart-04c985aa-3be7-4dd9-b85c-f86bb0706d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33518
68359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.3351868359
Directory /workspace/7.usbdev_rx_full/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1563538573
Short name T1315
Test name
Test status
Simulation time 147378433 ps
CPU time 0.91 seconds
Started Aug 17 06:04:19 PM PDT 24
Finished Aug 17 06:04:20 PM PDT 24
Peak memory 207452 kb
Host smart-11cbb85d-b342-4e3e-90f4-47cbc4837922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15635
38573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1563538573
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2377184407
Short name T2371
Test name
Test status
Simulation time 210009371 ps
CPU time 0.91 seconds
Started Aug 17 06:04:25 PM PDT 24
Finished Aug 17 06:04:26 PM PDT 24
Peak memory 207528 kb
Host smart-4d7e65f1-7d25-4626-a14c-02b0264fd18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23771
84407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2377184407
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1327965036
Short name T2840
Test name
Test status
Simulation time 224392092 ps
CPU time 1.08 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207456 kb
Host smart-11efe996-50a0-478d-a144-ad29572bb0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13279
65036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1327965036
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2752574341
Short name T1011
Test name
Test status
Simulation time 1546089568 ps
CPU time 13.22 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:33 PM PDT 24
Peak memory 215868 kb
Host smart-fc32abe4-8f20-4ac1-a755-0b15f75d373a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2752574341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2752574341
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2269376788
Short name T3063
Test name
Test status
Simulation time 173237427 ps
CPU time 0.87 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:21 PM PDT 24
Peak memory 207424 kb
Host smart-c9f66c7b-cda8-4798-89ad-4bd1fd8cc2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22693
76788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2269376788
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.672123203
Short name T576
Test name
Test status
Simulation time 177634802 ps
CPU time 0.85 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:21 PM PDT 24
Peak memory 207428 kb
Host smart-fd6ad553-cd31-432b-9564-2dc9f290de11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67212
3203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.672123203
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.821690075
Short name T1993
Test name
Test status
Simulation time 264749185 ps
CPU time 1.2 seconds
Started Aug 17 06:04:18 PM PDT 24
Finished Aug 17 06:04:19 PM PDT 24
Peak memory 207540 kb
Host smart-1aa72008-3ff6-4a61-acc4-0f6254af10f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82169
0075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.821690075
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3781545151
Short name T3291
Test name
Test status
Simulation time 2443501335 ps
CPU time 19.33 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:40 PM PDT 24
Peak memory 216036 kb
Host smart-2bf74583-c917-492c-8b50-8575bdb9bea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37815
45151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3781545151
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.3734092350
Short name T3095
Test name
Test status
Simulation time 1007343119 ps
CPU time 23.14 seconds
Started Aug 17 06:04:03 PM PDT 24
Finished Aug 17 06:04:26 PM PDT 24
Peak memory 207672 kb
Host smart-34fcbc92-4822-4185-88d9-3ea730e1d71e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734092350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.3734092350
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_tx_rx_disruption.2778687862
Short name T3378
Test name
Test status
Simulation time 576347699 ps
CPU time 1.76 seconds
Started Aug 17 06:04:18 PM PDT 24
Finished Aug 17 06:04:20 PM PDT 24
Peak memory 207564 kb
Host smart-e647c33d-3440-471b-9a0c-45f299ff6473
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778687862 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.usbdev_tx_rx_disruption.2778687862
Directory /workspace/7.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/70.usbdev_endpoint_types.2049015092
Short name T451
Test name
Test status
Simulation time 560660579 ps
CPU time 1.54 seconds
Started Aug 17 06:11:20 PM PDT 24
Finished Aug 17 06:11:22 PM PDT 24
Peak memory 207524 kb
Host smart-2fbed122-61d2-4dfa-8f05-3aed8fde1eb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2049015092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.2049015092
Directory /workspace/70.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/70.usbdev_tx_rx_disruption.3297689241
Short name T1435
Test name
Test status
Simulation time 586515822 ps
CPU time 1.66 seconds
Started Aug 17 06:11:14 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207568 kb
Host smart-65e41fa6-f1ca-46a4-a7fd-12c90833a91c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297689241 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.usbdev_tx_rx_disruption.3297689241
Directory /workspace/70.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/71.usbdev_endpoint_types.680766977
Short name T488
Test name
Test status
Simulation time 411051328 ps
CPU time 1.24 seconds
Started Aug 17 06:11:11 PM PDT 24
Finished Aug 17 06:11:12 PM PDT 24
Peak memory 207464 kb
Host smart-04e7ed72-734e-49fc-b160-99664fd57b69
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=680766977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.680766977
Directory /workspace/71.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/71.usbdev_tx_rx_disruption.882858042
Short name T2058
Test name
Test status
Simulation time 566463595 ps
CPU time 1.55 seconds
Started Aug 17 06:11:12 PM PDT 24
Finished Aug 17 06:11:14 PM PDT 24
Peak memory 207616 kb
Host smart-b3fd225a-0e14-406d-a9de-30f6927c98e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882858042 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 71.usbdev_tx_rx_disruption.882858042
Directory /workspace/71.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/72.usbdev_endpoint_types.798697410
Short name T3495
Test name
Test status
Simulation time 231538505 ps
CPU time 1 seconds
Started Aug 17 06:11:22 PM PDT 24
Finished Aug 17 06:11:23 PM PDT 24
Peak memory 207520 kb
Host smart-44f4ae9d-672a-4b02-a26b-768d27f59624
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=798697410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.798697410
Directory /workspace/72.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/72.usbdev_tx_rx_disruption.1292162521
Short name T1691
Test name
Test status
Simulation time 616168091 ps
CPU time 1.61 seconds
Started Aug 17 06:11:24 PM PDT 24
Finished Aug 17 06:11:26 PM PDT 24
Peak memory 207568 kb
Host smart-90b9399b-05f5-4330-8b7c-8b01e9eb4246
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292162521 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.usbdev_tx_rx_disruption.1292162521
Directory /workspace/72.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/73.usbdev_endpoint_types.1226899320
Short name T443
Test name
Test status
Simulation time 549126166 ps
CPU time 1.47 seconds
Started Aug 17 06:11:22 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207540 kb
Host smart-916229f2-c012-4da8-b5b3-fd3cb278abcc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1226899320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.1226899320
Directory /workspace/73.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/73.usbdev_tx_rx_disruption.207063505
Short name T678
Test name
Test status
Simulation time 491323877 ps
CPU time 1.61 seconds
Started Aug 17 06:11:18 PM PDT 24
Finished Aug 17 06:11:20 PM PDT 24
Peak memory 207576 kb
Host smart-43ea2626-3c74-412f-a427-6625f7d55228
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207063505 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 73.usbdev_tx_rx_disruption.207063505
Directory /workspace/73.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/74.usbdev_tx_rx_disruption.175807364
Short name T862
Test name
Test status
Simulation time 569922760 ps
CPU time 1.55 seconds
Started Aug 17 06:11:13 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207520 kb
Host smart-7c5b699b-ff47-4e4d-befb-60029b9761d7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175807364 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 74.usbdev_tx_rx_disruption.175807364
Directory /workspace/74.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/75.usbdev_endpoint_types.2927704014
Short name T405
Test name
Test status
Simulation time 482456127 ps
CPU time 1.48 seconds
Started Aug 17 06:11:14 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207524 kb
Host smart-2dfd1ead-4762-41aa-b349-38f5d461ea9c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2927704014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.2927704014
Directory /workspace/75.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/75.usbdev_tx_rx_disruption.965077571
Short name T3599
Test name
Test status
Simulation time 535063679 ps
CPU time 1.61 seconds
Started Aug 17 06:11:12 PM PDT 24
Finished Aug 17 06:11:14 PM PDT 24
Peak memory 207544 kb
Host smart-78eaf924-3c43-4185-b396-1eb246c1c672
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965077571 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 75.usbdev_tx_rx_disruption.965077571
Directory /workspace/75.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/76.usbdev_endpoint_types.3820366655
Short name T513
Test name
Test status
Simulation time 244050065 ps
CPU time 1.12 seconds
Started Aug 17 06:11:16 PM PDT 24
Finished Aug 17 06:11:17 PM PDT 24
Peak memory 207532 kb
Host smart-4b09e77b-d7b7-4ec5-bc9d-a9197740d85f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3820366655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.3820366655
Directory /workspace/76.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/76.usbdev_tx_rx_disruption.4093261492
Short name T3626
Test name
Test status
Simulation time 405437568 ps
CPU time 1.47 seconds
Started Aug 17 06:11:21 PM PDT 24
Finished Aug 17 06:11:23 PM PDT 24
Peak memory 207604 kb
Host smart-1cbaa4d1-7125-4e6f-b79a-dc43bc18d9c4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093261492 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.usbdev_tx_rx_disruption.4093261492
Directory /workspace/76.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/77.usbdev_endpoint_types.1454388788
Short name T3629
Test name
Test status
Simulation time 206014829 ps
CPU time 0.98 seconds
Started Aug 17 06:11:23 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 207540 kb
Host smart-92b70815-6583-4035-b56b-8f3ce3693d6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1454388788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.1454388788
Directory /workspace/77.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/77.usbdev_tx_rx_disruption.4237165269
Short name T1714
Test name
Test status
Simulation time 546227353 ps
CPU time 1.78 seconds
Started Aug 17 06:11:14 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207564 kb
Host smart-6d325f13-9684-4e11-9266-65d3d06828bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237165269 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.usbdev_tx_rx_disruption.4237165269
Directory /workspace/77.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/78.usbdev_endpoint_types.3386527609
Short name T428
Test name
Test status
Simulation time 376457031 ps
CPU time 1.17 seconds
Started Aug 17 06:11:07 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 207488 kb
Host smart-de8a0178-8c11-4e7c-a3e4-3b4e94c1091a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3386527609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.3386527609
Directory /workspace/78.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/78.usbdev_tx_rx_disruption.1278529571
Short name T820
Test name
Test status
Simulation time 479975677 ps
CPU time 1.5 seconds
Started Aug 17 06:11:17 PM PDT 24
Finished Aug 17 06:11:19 PM PDT 24
Peak memory 207572 kb
Host smart-a19b0321-fee1-47f2-ad4c-e03f97700da1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278529571 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.usbdev_tx_rx_disruption.1278529571
Directory /workspace/78.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/79.usbdev_endpoint_types.934004594
Short name T421
Test name
Test status
Simulation time 630761034 ps
CPU time 1.64 seconds
Started Aug 17 06:11:25 PM PDT 24
Finished Aug 17 06:11:26 PM PDT 24
Peak memory 207468 kb
Host smart-8cd17379-4cf4-40b6-879b-d04e29c302cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=934004594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.934004594
Directory /workspace/79.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/79.usbdev_tx_rx_disruption.555893804
Short name T3543
Test name
Test status
Simulation time 571230780 ps
CPU time 1.65 seconds
Started Aug 17 06:11:15 PM PDT 24
Finished Aug 17 06:11:17 PM PDT 24
Peak memory 207544 kb
Host smart-b17f29be-2480-451d-bd05-a3fb8d6daac7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555893804 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 79.usbdev_tx_rx_disruption.555893804
Directory /workspace/79.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.3211241184
Short name T1445
Test name
Test status
Simulation time 54622881 ps
CPU time 0.69 seconds
Started Aug 17 06:04:43 PM PDT 24
Finished Aug 17 06:04:43 PM PDT 24
Peak memory 207308 kb
Host smart-beea932c-7ba7-40d3-ae01-b8f918ae7f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3211241184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3211241184
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.355036609
Short name T1000
Test name
Test status
Simulation time 10280038263 ps
CPU time 14.7 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:36 PM PDT 24
Peak memory 207744 kb
Host smart-aadf5602-fb8a-44ca-b3a8-e8b8f615e604
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355036609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon
_wake_disconnect.355036609
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3867780747
Short name T566
Test name
Test status
Simulation time 20064787159 ps
CPU time 24.54 seconds
Started Aug 17 06:04:19 PM PDT 24
Finished Aug 17 06:04:44 PM PDT 24
Peak memory 207720 kb
Host smart-ec4a5619-4a04-454d-abe6-aadbd63e21b6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867780747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3867780747
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3999713921
Short name T1951
Test name
Test status
Simulation time 23471250317 ps
CPU time 33.16 seconds
Started Aug 17 06:04:23 PM PDT 24
Finished Aug 17 06:04:56 PM PDT 24
Peak memory 216004 kb
Host smart-26fbd337-a32c-400f-aad4-b99f6aba9074
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999713921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.3999713921
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3783542666
Short name T3415
Test name
Test status
Simulation time 180022049 ps
CPU time 0.91 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207464 kb
Host smart-585a5c29-da25-44ea-a52c-765591cf4bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37835
42666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3783542666
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1841227075
Short name T3032
Test name
Test status
Simulation time 181204000 ps
CPU time 0.87 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:21 PM PDT 24
Peak memory 207472 kb
Host smart-295407b6-7319-4e5f-8229-f656a8369155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18412
27075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1841227075
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2344207019
Short name T1852
Test name
Test status
Simulation time 387511375 ps
CPU time 1.4 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:21 PM PDT 24
Peak memory 207532 kb
Host smart-929619d7-9d62-40d5-9720-1f2dbc864b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23442
07019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2344207019
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2141258053
Short name T337
Test name
Test status
Simulation time 1155618181 ps
CPU time 3.35 seconds
Started Aug 17 06:04:22 PM PDT 24
Finished Aug 17 06:04:25 PM PDT 24
Peak memory 207700 kb
Host smart-598c0290-4ac9-4ea8-b0a6-5572ccf822de
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2141258053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2141258053
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2081678000
Short name T377
Test name
Test status
Simulation time 19800043665 ps
CPU time 32.93 seconds
Started Aug 17 06:04:18 PM PDT 24
Finished Aug 17 06:04:51 PM PDT 24
Peak memory 207776 kb
Host smart-e32019a5-e7d0-4d86-97fc-1bdb88f74f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20816
78000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2081678000
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.3191970078
Short name T857
Test name
Test status
Simulation time 1092123935 ps
CPU time 24.22 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:45 PM PDT 24
Peak memory 207664 kb
Host smart-0332dede-8a20-48c5-9106-f1cd7e1c7506
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191970078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.3191970078
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.3044807513
Short name T2606
Test name
Test status
Simulation time 899803541 ps
CPU time 2.01 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:23 PM PDT 24
Peak memory 207532 kb
Host smart-4a22a8ab-1c25-415d-abd6-0a75cb604d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30448
07513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.3044807513
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2832210730
Short name T731
Test name
Test status
Simulation time 146987314 ps
CPU time 0.84 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207524 kb
Host smart-b96cfd0b-f862-41b1-8b96-375a11b35305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28322
10730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2832210730
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3821315234
Short name T2800
Test name
Test status
Simulation time 32621115 ps
CPU time 0.71 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:20 PM PDT 24
Peak memory 207420 kb
Host smart-387f5091-b0ce-4af9-bec3-5bc5ddfcc0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38213
15234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3821315234
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.240230079
Short name T2329
Test name
Test status
Simulation time 1001308206 ps
CPU time 2.63 seconds
Started Aug 17 06:04:19 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207728 kb
Host smart-8d4fbb44-c15d-4e94-a897-931691f22e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24023
0079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.240230079
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1747259506
Short name T3313
Test name
Test status
Simulation time 273210738 ps
CPU time 2.45 seconds
Started Aug 17 06:04:19 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207596 kb
Host smart-6fe9e95a-9370-48df-ae10-6a02f9f3e0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17472
59506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1747259506
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2554203790
Short name T3419
Test name
Test status
Simulation time 204399537 ps
CPU time 0.95 seconds
Started Aug 17 06:04:22 PM PDT 24
Finished Aug 17 06:04:23 PM PDT 24
Peak memory 207420 kb
Host smart-d7964afa-e594-475a-b4ae-ae54252d7692
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2554203790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2554203790
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3271709886
Short name T1101
Test name
Test status
Simulation time 140592226 ps
CPU time 0.83 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:22 PM PDT 24
Peak memory 207428 kb
Host smart-2605e8b9-4275-4bfc-a504-9e3619f2eed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32717
09886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3271709886
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.4158080002
Short name T535
Test name
Test status
Simulation time 223952169 ps
CPU time 1.11 seconds
Started Aug 17 06:04:22 PM PDT 24
Finished Aug 17 06:04:23 PM PDT 24
Peak memory 207400 kb
Host smart-304e3268-3260-494d-a411-abf649ea3829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41580
80002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.4158080002
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.1724443057
Short name T2327
Test name
Test status
Simulation time 3461014145 ps
CPU time 27.83 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:49 PM PDT 24
Peak memory 224080 kb
Host smart-2008fe38-2c10-447d-9ea0-ea1d0b5a9c8d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1724443057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.1724443057
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.3237617134
Short name T1004
Test name
Test status
Simulation time 11483884489 ps
CPU time 141.55 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:06:42 PM PDT 24
Peak memory 207784 kb
Host smart-b66aea9f-85cb-4b87-9ac0-aeef132db3e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3237617134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.3237617134
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.325668109
Short name T703
Test name
Test status
Simulation time 229824223 ps
CPU time 1.01 seconds
Started Aug 17 06:04:21 PM PDT 24
Finished Aug 17 06:04:23 PM PDT 24
Peak memory 207436 kb
Host smart-c529d3e3-bc1e-4322-871b-f2b5576f058e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32566
8109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.325668109
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.767659064
Short name T64
Test name
Test status
Simulation time 31620212445 ps
CPU time 51.02 seconds
Started Aug 17 06:04:30 PM PDT 24
Finished Aug 17 06:05:21 PM PDT 24
Peak memory 207728 kb
Host smart-d1102895-8cac-4044-ba91-7b766f47ad19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76765
9064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.767659064
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.43386678
Short name T894
Test name
Test status
Simulation time 10037175002 ps
CPU time 12.56 seconds
Started Aug 17 06:04:27 PM PDT 24
Finished Aug 17 06:04:40 PM PDT 24
Peak memory 207744 kb
Host smart-73bf4748-dfda-4183-b35b-6cc9bdbacab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43386
678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.43386678
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3174122776
Short name T2276
Test name
Test status
Simulation time 4740392546 ps
CPU time 37.29 seconds
Started Aug 17 06:04:27 PM PDT 24
Finished Aug 17 06:05:04 PM PDT 24
Peak memory 216052 kb
Host smart-1067badf-c4bf-4d03-9762-52e119c2c73f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3174122776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3174122776
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.4008964191
Short name T2197
Test name
Test status
Simulation time 3066954668 ps
CPU time 33.83 seconds
Started Aug 17 06:04:31 PM PDT 24
Finished Aug 17 06:05:05 PM PDT 24
Peak memory 217652 kb
Host smart-5e2ca885-8fb5-4713-9d11-967e263347ac
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4008964191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.4008964191
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.194713297
Short name T1650
Test name
Test status
Simulation time 259741338 ps
CPU time 1.13 seconds
Started Aug 17 06:04:27 PM PDT 24
Finished Aug 17 06:04:28 PM PDT 24
Peak memory 207480 kb
Host smart-c4624775-f96f-4464-9eb8-7afcc89a9ef6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=194713297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.194713297
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2943944884
Short name T1185
Test name
Test status
Simulation time 193030706 ps
CPU time 0.92 seconds
Started Aug 17 06:04:25 PM PDT 24
Finished Aug 17 06:04:26 PM PDT 24
Peak memory 207464 kb
Host smart-05ade722-2764-4965-ae93-b710b0f60a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29439
44884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2943944884
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.2595600117
Short name T3132
Test name
Test status
Simulation time 3003532087 ps
CPU time 85.81 seconds
Started Aug 17 06:04:27 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 217988 kb
Host smart-16f03cae-dd6c-475c-834f-46637df6bc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25956
00117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.2595600117
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1040836590
Short name T854
Test name
Test status
Simulation time 2672100361 ps
CPU time 82.7 seconds
Started Aug 17 06:04:30 PM PDT 24
Finished Aug 17 06:05:53 PM PDT 24
Peak memory 215984 kb
Host smart-54d4409a-221d-44e6-997e-3ef5762065ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1040836590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1040836590
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3362436990
Short name T2189
Test name
Test status
Simulation time 1322753789 ps
CPU time 35.49 seconds
Started Aug 17 06:04:27 PM PDT 24
Finished Aug 17 06:05:03 PM PDT 24
Peak memory 215904 kb
Host smart-0a703405-e82c-4ca4-af0e-825184f6b445
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3362436990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3362436990
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2994976471
Short name T2797
Test name
Test status
Simulation time 161011925 ps
CPU time 0.87 seconds
Started Aug 17 06:04:28 PM PDT 24
Finished Aug 17 06:04:29 PM PDT 24
Peak memory 207508 kb
Host smart-8c546473-7c5b-456b-8988-470002eb29b5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2994976471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2994976471
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2849958191
Short name T1196
Test name
Test status
Simulation time 181595751 ps
CPU time 0.9 seconds
Started Aug 17 06:04:30 PM PDT 24
Finished Aug 17 06:04:31 PM PDT 24
Peak memory 207488 kb
Host smart-39f2e13b-3d17-4f8d-abb3-75db6fe419e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28499
58191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2849958191
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2914891323
Short name T156
Test name
Test status
Simulation time 224448285 ps
CPU time 0.98 seconds
Started Aug 17 06:04:31 PM PDT 24
Finished Aug 17 06:04:32 PM PDT 24
Peak memory 207472 kb
Host smart-2ef3c2de-c7e6-4007-a3b6-37d2c887c8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29148
91323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2914891323
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.455204643
Short name T898
Test name
Test status
Simulation time 160607159 ps
CPU time 0.92 seconds
Started Aug 17 06:04:29 PM PDT 24
Finished Aug 17 06:04:30 PM PDT 24
Peak memory 207436 kb
Host smart-a34922f8-343b-4b36-8831-757ee7a5bdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45520
4643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.455204643
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.4031312256
Short name T2902
Test name
Test status
Simulation time 159235414 ps
CPU time 0.96 seconds
Started Aug 17 06:04:25 PM PDT 24
Finished Aug 17 06:04:26 PM PDT 24
Peak memory 207456 kb
Host smart-bae56377-a0e5-4a13-a5d5-caf40652796d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40313
12256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.4031312256
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2174159543
Short name T2812
Test name
Test status
Simulation time 163442557 ps
CPU time 0.84 seconds
Started Aug 17 06:04:30 PM PDT 24
Finished Aug 17 06:04:31 PM PDT 24
Peak memory 207564 kb
Host smart-ba8e75fa-2841-4e89-a1e8-a92e4d7cf49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21741
59543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2174159543
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3338887190
Short name T2791
Test name
Test status
Simulation time 165740405 ps
CPU time 0.89 seconds
Started Aug 17 06:04:27 PM PDT 24
Finished Aug 17 06:04:28 PM PDT 24
Peak memory 207560 kb
Host smart-1880ed9d-dae9-4b6d-898e-93745c99b754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33388
87190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3338887190
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2274139152
Short name T174
Test name
Test status
Simulation time 231961520 ps
CPU time 1.07 seconds
Started Aug 17 06:04:28 PM PDT 24
Finished Aug 17 06:04:29 PM PDT 24
Peak memory 207532 kb
Host smart-2bb4717f-6376-42e0-bb8a-1fbc29569ab9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2274139152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2274139152
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.904125548
Short name T2657
Test name
Test status
Simulation time 150130446 ps
CPU time 0.82 seconds
Started Aug 17 06:04:31 PM PDT 24
Finished Aug 17 06:04:32 PM PDT 24
Peak memory 207432 kb
Host smart-73cb5810-6b50-4975-9556-e95b49eaa243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90412
5548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.904125548
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.745101952
Short name T2044
Test name
Test status
Simulation time 30340437 ps
CPU time 0.7 seconds
Started Aug 17 06:04:26 PM PDT 24
Finished Aug 17 06:04:27 PM PDT 24
Peak memory 207416 kb
Host smart-f4a6bb34-c04f-4a62-ac2b-0e00c9afb7df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74510
1952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.745101952
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2855064099
Short name T2721
Test name
Test status
Simulation time 8341949680 ps
CPU time 20.64 seconds
Started Aug 17 06:04:31 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 215928 kb
Host smart-791c951a-12e3-49b2-ba29-7aa72491c560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28550
64099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2855064099
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.120585536
Short name T2277
Test name
Test status
Simulation time 158987367 ps
CPU time 0.83 seconds
Started Aug 17 06:04:31 PM PDT 24
Finished Aug 17 06:04:32 PM PDT 24
Peak memory 207492 kb
Host smart-5b94e636-058e-4fa4-aac0-7f4e6d9b4d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12058
5536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.120585536
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.4140255398
Short name T3118
Test name
Test status
Simulation time 222106408 ps
CPU time 0.94 seconds
Started Aug 17 06:04:28 PM PDT 24
Finished Aug 17 06:04:29 PM PDT 24
Peak memory 207476 kb
Host smart-5c21acb0-a96e-4e3d-9599-bf664a227b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41402
55398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.4140255398
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.267401732
Short name T1931
Test name
Test status
Simulation time 10935681075 ps
CPU time 226.45 seconds
Started Aug 17 06:04:30 PM PDT 24
Finished Aug 17 06:08:16 PM PDT 24
Peak memory 224104 kb
Host smart-0c788f66-1a07-459a-83b4-6f78985c549c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=267401732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.267401732
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.4196518672
Short name T1634
Test name
Test status
Simulation time 7520380913 ps
CPU time 41.04 seconds
Started Aug 17 06:04:27 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 216008 kb
Host smart-acf1cd0b-c510-4b80-b1de-6166facc0cdc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4196518672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.4196518672
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1510054217
Short name T2501
Test name
Test status
Simulation time 5780802379 ps
CPU time 29.41 seconds
Started Aug 17 06:04:32 PM PDT 24
Finished Aug 17 06:05:01 PM PDT 24
Peak memory 224104 kb
Host smart-8fa12ffa-68dd-48b3-860f-b53724fff823
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510054217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1510054217
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.13180750
Short name T1644
Test name
Test status
Simulation time 187641645 ps
CPU time 0.96 seconds
Started Aug 17 06:04:27 PM PDT 24
Finished Aug 17 06:04:28 PM PDT 24
Peak memory 207452 kb
Host smart-60c3fbdb-864e-4b41-bbc9-44a5ecc402b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13180
750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.13180750
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.4034535046
Short name T1496
Test name
Test status
Simulation time 214287642 ps
CPU time 0.95 seconds
Started Aug 17 06:04:31 PM PDT 24
Finished Aug 17 06:04:32 PM PDT 24
Peak memory 207436 kb
Host smart-32dd0f0a-2589-418a-b8e9-cec5b49eed6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40345
35046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.4034535046
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_resume_link_active.958712088
Short name T2709
Test name
Test status
Simulation time 20150207419 ps
CPU time 28.5 seconds
Started Aug 17 06:04:28 PM PDT 24
Finished Aug 17 06:04:57 PM PDT 24
Peak memory 207556 kb
Host smart-fbac195f-ab91-4ab7-8204-d6c71b7012d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95871
2088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.958712088
Directory /workspace/8.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1965633236
Short name T2693
Test name
Test status
Simulation time 136467909 ps
CPU time 0.85 seconds
Started Aug 17 06:04:29 PM PDT 24
Finished Aug 17 06:04:30 PM PDT 24
Peak memory 207068 kb
Host smart-623afdd5-90cd-4132-91b4-d14ac66bdeb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19656
33236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1965633236
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_rx_full.3101385903
Short name T332
Test name
Test status
Simulation time 328626664 ps
CPU time 1.19 seconds
Started Aug 17 06:04:30 PM PDT 24
Finished Aug 17 06:04:32 PM PDT 24
Peak memory 207464 kb
Host smart-b3079c15-8d6e-4375-8ac6-8e8468da1568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31013
85903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.3101385903
Directory /workspace/8.usbdev_rx_full/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1352133456
Short name T3142
Test name
Test status
Simulation time 188218390 ps
CPU time 0.91 seconds
Started Aug 17 06:04:29 PM PDT 24
Finished Aug 17 06:04:30 PM PDT 24
Peak memory 206948 kb
Host smart-da40dbd9-bb53-4bb1-a5a6-80ad10972d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13521
33456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1352133456
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2261236759
Short name T933
Test name
Test status
Simulation time 162675841 ps
CPU time 0.9 seconds
Started Aug 17 06:04:30 PM PDT 24
Finished Aug 17 06:04:31 PM PDT 24
Peak memory 207564 kb
Host smart-53887e11-6eea-4de8-bd64-9a53df052344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22612
36759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2261236759
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1366555812
Short name T672
Test name
Test status
Simulation time 216858237 ps
CPU time 1.08 seconds
Started Aug 17 06:04:30 PM PDT 24
Finished Aug 17 06:04:31 PM PDT 24
Peak memory 207464 kb
Host smart-7ab4b02b-7fec-4b5f-b39b-d5c9b3540385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13665
55812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1366555812
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.2349580469
Short name T2412
Test name
Test status
Simulation time 2556413006 ps
CPU time 25.57 seconds
Started Aug 17 06:04:29 PM PDT 24
Finished Aug 17 06:04:55 PM PDT 24
Peak memory 224064 kb
Host smart-168cdc74-197b-417e-837b-ce4b901e7aa4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2349580469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.2349580469
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.629848777
Short name T3491
Test name
Test status
Simulation time 174179050 ps
CPU time 0.92 seconds
Started Aug 17 06:04:26 PM PDT 24
Finished Aug 17 06:04:27 PM PDT 24
Peak memory 207452 kb
Host smart-70bd4f46-f097-48bf-87de-cca285ecf89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62984
8777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.629848777
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3330780119
Short name T2119
Test name
Test status
Simulation time 162410120 ps
CPU time 0.87 seconds
Started Aug 17 06:04:28 PM PDT 24
Finished Aug 17 06:04:29 PM PDT 24
Peak memory 207488 kb
Host smart-58351fd0-20a9-44fd-b9c6-352e0784cad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
80119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3330780119
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.4059442862
Short name T3508
Test name
Test status
Simulation time 1148573979 ps
CPU time 2.87 seconds
Started Aug 17 06:04:26 PM PDT 24
Finished Aug 17 06:04:29 PM PDT 24
Peak memory 207728 kb
Host smart-d2c1ce82-8eb5-4e0e-b8cb-594db1d4564b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40594
42862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.4059442862
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.1214424011
Short name T169
Test name
Test status
Simulation time 2741715389 ps
CPU time 28.44 seconds
Started Aug 17 06:04:26 PM PDT 24
Finished Aug 17 06:04:55 PM PDT 24
Peak memory 224124 kb
Host smart-cb364768-e925-4ba7-8362-5544658d2c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
24011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1214424011
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.1373495190
Short name T2654
Test name
Test status
Simulation time 5009591641 ps
CPU time 34.99 seconds
Started Aug 17 06:04:20 PM PDT 24
Finished Aug 17 06:04:55 PM PDT 24
Peak memory 207684 kb
Host smart-db44024f-42fc-4f00-9fa1-74e450a7a160
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373495190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.1373495190
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_tx_rx_disruption.416531112
Short name T2767
Test name
Test status
Simulation time 459330916 ps
CPU time 1.52 seconds
Started Aug 17 06:04:28 PM PDT 24
Finished Aug 17 06:04:29 PM PDT 24
Peak memory 207476 kb
Host smart-1e3afb97-15e4-4294-a252-cca8bdf67d13
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416531112 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.usbdev_tx_rx_disruption.416531112
Directory /workspace/8.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/80.usbdev_tx_rx_disruption.1980652869
Short name T1833
Test name
Test status
Simulation time 562111700 ps
CPU time 1.66 seconds
Started Aug 17 06:11:29 PM PDT 24
Finished Aug 17 06:11:30 PM PDT 24
Peak memory 207592 kb
Host smart-a73f2af4-414e-4607-ba15-9b05ced77564
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980652869 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.usbdev_tx_rx_disruption.1980652869
Directory /workspace/80.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/81.usbdev_endpoint_types.1844829813
Short name T386
Test name
Test status
Simulation time 326744055 ps
CPU time 1.11 seconds
Started Aug 17 06:11:17 PM PDT 24
Finished Aug 17 06:11:18 PM PDT 24
Peak memory 207472 kb
Host smart-ecd6d511-4680-4438-a6c4-ac5a7531a3cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1844829813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.1844829813
Directory /workspace/81.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/81.usbdev_tx_rx_disruption.1935607127
Short name T1811
Test name
Test status
Simulation time 442083702 ps
CPU time 1.41 seconds
Started Aug 17 06:11:21 PM PDT 24
Finished Aug 17 06:11:23 PM PDT 24
Peak memory 207560 kb
Host smart-d4353382-faf3-418a-9605-208175e2c1ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935607127 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.usbdev_tx_rx_disruption.1935607127
Directory /workspace/81.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/82.usbdev_endpoint_types.3975490854
Short name T471
Test name
Test status
Simulation time 594622493 ps
CPU time 1.42 seconds
Started Aug 17 06:11:23 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 207524 kb
Host smart-590678ae-d6c5-43a9-9e2e-8651ce54c620
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3975490854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.3975490854
Directory /workspace/82.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/82.usbdev_tx_rx_disruption.3668759593
Short name T3627
Test name
Test status
Simulation time 486614359 ps
CPU time 1.53 seconds
Started Aug 17 06:11:22 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207488 kb
Host smart-c393bf4f-bff6-4a2b-ae95-fec55e5c578e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668759593 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.usbdev_tx_rx_disruption.3668759593
Directory /workspace/82.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/83.usbdev_endpoint_types.454442228
Short name T514
Test name
Test status
Simulation time 182620422 ps
CPU time 0.92 seconds
Started Aug 17 06:11:24 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 207500 kb
Host smart-532f831f-1809-4315-8c8e-d925a3cb6e04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=454442228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.454442228
Directory /workspace/83.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/83.usbdev_tx_rx_disruption.1504137178
Short name T916
Test name
Test status
Simulation time 573863024 ps
CPU time 1.63 seconds
Started Aug 17 06:11:24 PM PDT 24
Finished Aug 17 06:11:26 PM PDT 24
Peak memory 207568 kb
Host smart-bddf2ba3-abb0-4cfd-bb05-b6314d5ba8c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504137178 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.usbdev_tx_rx_disruption.1504137178
Directory /workspace/83.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/84.usbdev_endpoint_types.3333824695
Short name T398
Test name
Test status
Simulation time 696240544 ps
CPU time 1.66 seconds
Started Aug 17 06:11:29 PM PDT 24
Finished Aug 17 06:11:31 PM PDT 24
Peak memory 207524 kb
Host smart-653252a4-b0ea-4745-a882-6655ebc7b602
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3333824695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.3333824695
Directory /workspace/84.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/84.usbdev_tx_rx_disruption.856256187
Short name T2315
Test name
Test status
Simulation time 518498468 ps
CPU time 1.58 seconds
Started Aug 17 06:11:19 PM PDT 24
Finished Aug 17 06:11:21 PM PDT 24
Peak memory 207556 kb
Host smart-ff750b32-e7d3-4960-b4e7-aba38a96c478
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856256187 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 84.usbdev_tx_rx_disruption.856256187
Directory /workspace/84.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/85.usbdev_endpoint_types.3662969093
Short name T502
Test name
Test status
Simulation time 502466988 ps
CPU time 1.44 seconds
Started Aug 17 06:11:23 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207536 kb
Host smart-3295d72b-7913-4721-9a22-1539560023b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3662969093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.3662969093
Directory /workspace/85.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/85.usbdev_tx_rx_disruption.3262261402
Short name T1156
Test name
Test status
Simulation time 544310501 ps
CPU time 1.59 seconds
Started Aug 17 06:11:13 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207500 kb
Host smart-5790fc69-82e6-4bb7-8e2f-cd2b7ca2e88e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262261402 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.usbdev_tx_rx_disruption.3262261402
Directory /workspace/85.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/86.usbdev_endpoint_types.531359485
Short name T2865
Test name
Test status
Simulation time 139085796 ps
CPU time 0.85 seconds
Started Aug 17 06:11:20 PM PDT 24
Finished Aug 17 06:11:21 PM PDT 24
Peak memory 207508 kb
Host smart-924d0a0b-9f18-4027-ade5-feb5c51c4cec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=531359485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.531359485
Directory /workspace/86.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/87.usbdev_tx_rx_disruption.3972928656
Short name T333
Test name
Test status
Simulation time 588757548 ps
CPU time 1.56 seconds
Started Aug 17 06:11:24 PM PDT 24
Finished Aug 17 06:11:26 PM PDT 24
Peak memory 207568 kb
Host smart-e6d1432c-1e17-4384-af14-f21601896dda
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972928656 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.usbdev_tx_rx_disruption.3972928656
Directory /workspace/87.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/88.usbdev_endpoint_types.2462760092
Short name T507
Test name
Test status
Simulation time 207148139 ps
CPU time 1 seconds
Started Aug 17 06:11:12 PM PDT 24
Finished Aug 17 06:11:13 PM PDT 24
Peak memory 207436 kb
Host smart-beddf2f6-77be-48c9-a6f7-861a5bd9292a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2462760092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.2462760092
Directory /workspace/88.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/88.usbdev_tx_rx_disruption.1853575749
Short name T1594
Test name
Test status
Simulation time 496438581 ps
CPU time 1.59 seconds
Started Aug 17 06:11:20 PM PDT 24
Finished Aug 17 06:11:22 PM PDT 24
Peak memory 207580 kb
Host smart-de27faf9-915c-4098-9293-1cdefa153120
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853575749 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.usbdev_tx_rx_disruption.1853575749
Directory /workspace/88.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/89.usbdev_endpoint_types.3795871966
Short name T465
Test name
Test status
Simulation time 415302425 ps
CPU time 1.27 seconds
Started Aug 17 06:11:20 PM PDT 24
Finished Aug 17 06:11:21 PM PDT 24
Peak memory 207516 kb
Host smart-065a8ea7-4019-488d-8d81-c32bd7c8a487
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3795871966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.3795871966
Directory /workspace/89.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/89.usbdev_tx_rx_disruption.3739059832
Short name T863
Test name
Test status
Simulation time 447692914 ps
CPU time 1.44 seconds
Started Aug 17 06:11:12 PM PDT 24
Finished Aug 17 06:11:14 PM PDT 24
Peak memory 207564 kb
Host smart-ce9caa1c-6e68-41ca-81fa-fb8ef8b02802
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739059832 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.usbdev_tx_rx_disruption.3739059832
Directory /workspace/89.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.161537501
Short name T1814
Test name
Test status
Simulation time 75253583 ps
CPU time 0.75 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 207404 kb
Host smart-127c892d-2c87-4e89-9d9b-5148fd2b86c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=161537501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.161537501
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1058127616
Short name T2186
Test name
Test status
Simulation time 5049765992 ps
CPU time 7.39 seconds
Started Aug 17 06:04:34 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 215952 kb
Host smart-dba71992-5ab5-4f0d-abdd-a98c8bdb861c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058127616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.1058127616
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3907519415
Short name T1867
Test name
Test status
Simulation time 14367614597 ps
CPU time 18.07 seconds
Started Aug 17 06:04:35 PM PDT 24
Finished Aug 17 06:04:54 PM PDT 24
Peak memory 215892 kb
Host smart-af8bd06b-e937-4277-9252-dafcb03047e2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907519415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3907519415
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1693584282
Short name T3401
Test name
Test status
Simulation time 31077825462 ps
CPU time 43.91 seconds
Started Aug 17 06:04:32 PM PDT 24
Finished Aug 17 06:05:16 PM PDT 24
Peak memory 207804 kb
Host smart-43cd5858-e23a-4605-9a01-9bef90d1898b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693584282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.1693584282
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3508915775
Short name T1045
Test name
Test status
Simulation time 145926606 ps
CPU time 0.85 seconds
Started Aug 17 06:04:35 PM PDT 24
Finished Aug 17 06:04:36 PM PDT 24
Peak memory 207480 kb
Host smart-b4282a62-172f-430b-8675-38177eb61fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35089
15775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3508915775
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1569709167
Short name T2942
Test name
Test status
Simulation time 165285825 ps
CPU time 0.9 seconds
Started Aug 17 06:04:38 PM PDT 24
Finished Aug 17 06:04:39 PM PDT 24
Peak memory 207456 kb
Host smart-46be3c0b-8946-4144-8c4a-0964a682c506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697
09167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1569709167
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.1718429163
Short name T2732
Test name
Test status
Simulation time 252132238 ps
CPU time 1.05 seconds
Started Aug 17 06:04:35 PM PDT 24
Finished Aug 17 06:04:36 PM PDT 24
Peak memory 207496 kb
Host smart-35d06036-71cd-4804-bf00-dfff4c7c4524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17184
29163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.1718429163
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2396473379
Short name T3275
Test name
Test status
Simulation time 521800112 ps
CPU time 1.69 seconds
Started Aug 17 06:04:37 PM PDT 24
Finished Aug 17 06:04:39 PM PDT 24
Peak memory 207480 kb
Host smart-96e5652e-2ddc-4ba0-8d7b-b0ece162aa97
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2396473379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2396473379
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.2055812249
Short name T374
Test name
Test status
Simulation time 14187376707 ps
CPU time 25.08 seconds
Started Aug 17 06:04:38 PM PDT 24
Finished Aug 17 06:05:03 PM PDT 24
Peak memory 207748 kb
Host smart-db246f6c-8d2b-41c0-8a5f-d8e6f3a4b838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20558
12249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2055812249
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.4146701890
Short name T2235
Test name
Test status
Simulation time 594590574 ps
CPU time 12.42 seconds
Started Aug 17 06:04:36 PM PDT 24
Finished Aug 17 06:04:48 PM PDT 24
Peak memory 207696 kb
Host smart-7ce3f87d-e1df-4ed4-bdc4-6f41c7b7ee80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146701890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.4146701890
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.83799698
Short name T1721
Test name
Test status
Simulation time 1076814499 ps
CPU time 2.43 seconds
Started Aug 17 06:04:36 PM PDT 24
Finished Aug 17 06:04:38 PM PDT 24
Peak memory 207500 kb
Host smart-95d6d566-a0e5-45e0-bcdd-aea170ccad89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83799
698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.83799698
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.3000952
Short name T3625
Test name
Test status
Simulation time 170101418 ps
CPU time 0.9 seconds
Started Aug 17 06:04:35 PM PDT 24
Finished Aug 17 06:04:36 PM PDT 24
Peak memory 207428 kb
Host smart-623a106c-060f-4ec9-9846-ed536f383efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30009
52 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.3000952
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1895550840
Short name T3259
Test name
Test status
Simulation time 32285909 ps
CPU time 0.7 seconds
Started Aug 17 06:04:33 PM PDT 24
Finished Aug 17 06:04:34 PM PDT 24
Peak memory 207448 kb
Host smart-a9adf061-482c-4eca-b1d2-ac5b01aaddb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18955
50840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1895550840
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3254702186
Short name T2613
Test name
Test status
Simulation time 835792466 ps
CPU time 2.26 seconds
Started Aug 17 06:04:34 PM PDT 24
Finished Aug 17 06:04:36 PM PDT 24
Peak memory 207748 kb
Host smart-d4bf071d-b53e-4316-9cef-60a901b5b724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32547
02186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3254702186
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_types.3442157976
Short name T504
Test name
Test status
Simulation time 546287144 ps
CPU time 1.54 seconds
Started Aug 17 06:04:43 PM PDT 24
Finished Aug 17 06:04:44 PM PDT 24
Peak memory 207436 kb
Host smart-0852f51b-ce48-4de0-bfc5-a974db9d08d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3442157976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.3442157976
Directory /workspace/9.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2456000120
Short name T1289
Test name
Test status
Simulation time 158560119 ps
CPU time 1.57 seconds
Started Aug 17 06:04:35 PM PDT 24
Finished Aug 17 06:04:37 PM PDT 24
Peak memory 207660 kb
Host smart-0c521508-91aa-45a9-8844-0a2ab8fb3beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24560
00120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2456000120
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2202235941
Short name T1990
Test name
Test status
Simulation time 235969688 ps
CPU time 1.11 seconds
Started Aug 17 06:04:35 PM PDT 24
Finished Aug 17 06:04:36 PM PDT 24
Peak memory 215916 kb
Host smart-9e74a846-dca4-46c0-b82b-b5525f43a2ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2202235941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2202235941
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1130534093
Short name T2611
Test name
Test status
Simulation time 148495971 ps
CPU time 0.84 seconds
Started Aug 17 06:04:34 PM PDT 24
Finished Aug 17 06:04:35 PM PDT 24
Peak memory 207456 kb
Host smart-9e91265c-b481-4fb2-9e27-b6b251e34285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11305
34093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1130534093
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3216149981
Short name T3215
Test name
Test status
Simulation time 221272411 ps
CPU time 0.95 seconds
Started Aug 17 06:04:44 PM PDT 24
Finished Aug 17 06:04:45 PM PDT 24
Peak memory 207428 kb
Host smart-7542898b-f9ca-4294-9701-73db5433d6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32161
49981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3216149981
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.3433383683
Short name T1478
Test name
Test status
Simulation time 4029385607 ps
CPU time 113.58 seconds
Started Aug 17 06:04:33 PM PDT 24
Finished Aug 17 06:06:27 PM PDT 24
Peak memory 217752 kb
Host smart-331a89e0-1fc8-40d6-a681-12838cf3513e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3433383683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3433383683
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.3796162200
Short name T1991
Test name
Test status
Simulation time 13129089472 ps
CPU time 182.62 seconds
Started Aug 17 06:04:35 PM PDT 24
Finished Aug 17 06:07:38 PM PDT 24
Peak memory 207764 kb
Host smart-496bf8b7-0be9-43b5-a0f8-634bef811116
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3796162200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.3796162200
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.303727402
Short name T1138
Test name
Test status
Simulation time 152545658 ps
CPU time 0.9 seconds
Started Aug 17 06:04:43 PM PDT 24
Finished Aug 17 06:04:44 PM PDT 24
Peak memory 207428 kb
Host smart-421c9184-f16a-4431-9e1b-94f1b37b4594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30372
7402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.303727402
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1435778151
Short name T1843
Test name
Test status
Simulation time 33828398845 ps
CPU time 52.3 seconds
Started Aug 17 06:04:44 PM PDT 24
Finished Aug 17 06:05:36 PM PDT 24
Peak memory 207684 kb
Host smart-5197cb8d-03e6-4e74-8988-713980ed2544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14357
78151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1435778151
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.4043209329
Short name T2175
Test name
Test status
Simulation time 4064209955 ps
CPU time 5.77 seconds
Started Aug 17 06:04:36 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 207784 kb
Host smart-26413e78-5d69-4b95-8ac8-90476c6d325b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40432
09329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.4043209329
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.888218128
Short name T2479
Test name
Test status
Simulation time 6113760035 ps
CPU time 53.23 seconds
Started Aug 17 06:04:48 PM PDT 24
Finished Aug 17 06:05:41 PM PDT 24
Peak memory 224060 kb
Host smart-73c83475-2b7e-49c7-a627-20b361730684
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=888218128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.888218128
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.1892575936
Short name T2439
Test name
Test status
Simulation time 3945392684 ps
CPU time 40.7 seconds
Started Aug 17 06:04:48 PM PDT 24
Finished Aug 17 06:05:29 PM PDT 24
Peak memory 215896 kb
Host smart-c5f95e63-6b4b-487e-abca-7e99157edf8e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1892575936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.1892575936
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2127775582
Short name T1802
Test name
Test status
Simulation time 303210239 ps
CPU time 1.13 seconds
Started Aug 17 06:04:35 PM PDT 24
Finished Aug 17 06:04:36 PM PDT 24
Peak memory 207480 kb
Host smart-89798bc9-5c4f-4b98-ac19-ebfdf27a19aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2127775582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2127775582
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3657559902
Short name T3531
Test name
Test status
Simulation time 196265168 ps
CPU time 0.95 seconds
Started Aug 17 06:04:33 PM PDT 24
Finished Aug 17 06:04:34 PM PDT 24
Peak memory 207436 kb
Host smart-36ae55c7-5469-45ec-92c9-2d6a7edd72f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575
59902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3657559902
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.1643987798
Short name T735
Test name
Test status
Simulation time 2001964285 ps
CPU time 21.1 seconds
Started Aug 17 06:04:36 PM PDT 24
Finished Aug 17 06:04:57 PM PDT 24
Peak memory 216584 kb
Host smart-dfba2b1f-82d9-473d-8572-9345569f2190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16439
87798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.1643987798
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2107029140
Short name T3014
Test name
Test status
Simulation time 3182284883 ps
CPU time 99.28 seconds
Started Aug 17 06:04:42 PM PDT 24
Finished Aug 17 06:06:21 PM PDT 24
Peak memory 218684 kb
Host smart-384cab7b-1ca4-49d9-9fcf-14011d2a621c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2107029140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2107029140
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3051458089
Short name T2255
Test name
Test status
Simulation time 2043363441 ps
CPU time 59.81 seconds
Started Aug 17 06:04:41 PM PDT 24
Finished Aug 17 06:05:41 PM PDT 24
Peak memory 215856 kb
Host smart-ee62939e-db5e-4628-89c1-559dda7463a7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3051458089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3051458089
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.1284890978
Short name T3286
Test name
Test status
Simulation time 151008370 ps
CPU time 0.85 seconds
Started Aug 17 06:04:40 PM PDT 24
Finished Aug 17 06:04:41 PM PDT 24
Peak memory 207468 kb
Host smart-2ec48376-555c-4ccb-9796-1d59d07ed841
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1284890978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.1284890978
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.459205675
Short name T2313
Test name
Test status
Simulation time 166779491 ps
CPU time 0.88 seconds
Started Aug 17 06:04:42 PM PDT 24
Finished Aug 17 06:04:43 PM PDT 24
Peak memory 207412 kb
Host smart-312fa64b-d5be-432f-a00a-eff8d113076c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45920
5675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.459205675
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3150495388
Short name T154
Test name
Test status
Simulation time 186762036 ps
CPU time 0.94 seconds
Started Aug 17 06:04:42 PM PDT 24
Finished Aug 17 06:04:43 PM PDT 24
Peak memory 207460 kb
Host smart-85f40276-e32d-4a21-96af-19313f3e7e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31504
95388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3150495388
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.4128558690
Short name T2524
Test name
Test status
Simulation time 166465999 ps
CPU time 0.9 seconds
Started Aug 17 06:04:42 PM PDT 24
Finished Aug 17 06:04:43 PM PDT 24
Peak memory 207400 kb
Host smart-f9495609-cd9c-4c18-ae3c-3b331e6c2d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41285
58690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.4128558690
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3174872958
Short name T572
Test name
Test status
Simulation time 162486270 ps
CPU time 0.89 seconds
Started Aug 17 06:04:53 PM PDT 24
Finished Aug 17 06:04:54 PM PDT 24
Peak memory 207464 kb
Host smart-b7bbe3ff-88f4-4510-9b03-fe796672fc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31748
72958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3174872958
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.4227618348
Short name T2075
Test name
Test status
Simulation time 198458777 ps
CPU time 0.95 seconds
Started Aug 17 06:04:41 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 207500 kb
Host smart-0f20f425-682c-4c54-82d5-a45d531a2935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42276
18348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.4227618348
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1975359535
Short name T2659
Test name
Test status
Simulation time 153982592 ps
CPU time 0.88 seconds
Started Aug 17 06:04:49 PM PDT 24
Finished Aug 17 06:04:50 PM PDT 24
Peak memory 207508 kb
Host smart-099662fe-69da-4c27-83f5-b3ae20106b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19753
59535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1975359535
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2582067429
Short name T2781
Test name
Test status
Simulation time 215922487 ps
CPU time 1 seconds
Started Aug 17 06:04:41 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 207560 kb
Host smart-3db2492b-a0f6-4e24-b045-d5ef2be195dd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2582067429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2582067429
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.632943438
Short name T2854
Test name
Test status
Simulation time 141054248 ps
CPU time 0.87 seconds
Started Aug 17 06:04:41 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 207364 kb
Host smart-2af5663f-8095-4d38-9da5-41bae7759c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63294
3438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.632943438
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1375784121
Short name T1396
Test name
Test status
Simulation time 54319779 ps
CPU time 0.76 seconds
Started Aug 17 06:04:41 PM PDT 24
Finished Aug 17 06:04:41 PM PDT 24
Peak memory 207512 kb
Host smart-92746f90-c510-4369-93d2-8761e7fea60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757
84121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1375784121
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.567449607
Short name T3340
Test name
Test status
Simulation time 18278560558 ps
CPU time 47.77 seconds
Started Aug 17 06:04:53 PM PDT 24
Finished Aug 17 06:05:41 PM PDT 24
Peak memory 215952 kb
Host smart-0581730a-7b6b-4d9a-8ea5-47f191760bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56744
9607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.567449607
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.4242310731
Short name T3591
Test name
Test status
Simulation time 164821940 ps
CPU time 0.89 seconds
Started Aug 17 06:04:51 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 207540 kb
Host smart-1c253a6b-4525-4758-acda-2915958fced6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42423
10731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.4242310731
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3316843646
Short name T1566
Test name
Test status
Simulation time 168627439 ps
CPU time 0.93 seconds
Started Aug 17 06:04:37 PM PDT 24
Finished Aug 17 06:04:38 PM PDT 24
Peak memory 207420 kb
Host smart-6b2b6a7f-e3e3-475b-9ba1-515a3c5be63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33168
43646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3316843646
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.3671230449
Short name T739
Test name
Test status
Simulation time 4137776830 ps
CPU time 30.15 seconds
Started Aug 17 06:04:41 PM PDT 24
Finished Aug 17 06:05:11 PM PDT 24
Peak memory 218596 kb
Host smart-4df8c8ef-5373-4984-97f5-3a27452bc499
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671230449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.3671230449
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2988106499
Short name T2149
Test name
Test status
Simulation time 6227912950 ps
CPU time 72.86 seconds
Started Aug 17 06:04:42 PM PDT 24
Finished Aug 17 06:05:55 PM PDT 24
Peak memory 219120 kb
Host smart-ae8c91b8-4941-4917-b1dd-7c0477463d34
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2988106499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2988106499
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1034542597
Short name T2059
Test name
Test status
Simulation time 10654776165 ps
CPU time 57.28 seconds
Started Aug 17 06:04:42 PM PDT 24
Finished Aug 17 06:05:40 PM PDT 24
Peak memory 224116 kb
Host smart-19b722c0-5fd8-4e49-9638-61c22cf49f68
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034542597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1034542597
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1395999443
Short name T2920
Test name
Test status
Simulation time 202602931 ps
CPU time 0.94 seconds
Started Aug 17 06:04:41 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 207464 kb
Host smart-73e88ef7-b6cb-4c12-b11e-083ffca450ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13959
99443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1395999443
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.743410944
Short name T3077
Test name
Test status
Simulation time 185074842 ps
CPU time 0.91 seconds
Started Aug 17 06:04:42 PM PDT 24
Finished Aug 17 06:04:43 PM PDT 24
Peak memory 207468 kb
Host smart-3088743e-0b4d-4302-8ae2-0f978a95dd3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74341
0944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.743410944
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_resume_link_active.3465331677
Short name T103
Test name
Test status
Simulation time 20154228626 ps
CPU time 27.29 seconds
Started Aug 17 06:04:40 PM PDT 24
Finished Aug 17 06:05:08 PM PDT 24
Peak memory 207496 kb
Host smart-750713d2-0b7e-4c20-a384-45b13816062a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34653
31677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.3465331677
Directory /workspace/9.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3845909563
Short name T646
Test name
Test status
Simulation time 158037974 ps
CPU time 0.86 seconds
Started Aug 17 06:04:49 PM PDT 24
Finished Aug 17 06:04:50 PM PDT 24
Peak memory 207432 kb
Host smart-442003aa-f41f-4380-8090-f8401105135f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38459
09563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3845909563
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_rx_full.3608549260
Short name T51
Test name
Test status
Simulation time 294289953 ps
CPU time 1.11 seconds
Started Aug 17 06:04:53 PM PDT 24
Finished Aug 17 06:04:55 PM PDT 24
Peak memory 207468 kb
Host smart-cc41c335-368f-4804-98a6-98e2c0c5312b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36085
49260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.3608549260
Directory /workspace/9.usbdev_rx_full/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.4048205485
Short name T2704
Test name
Test status
Simulation time 155939454 ps
CPU time 0.84 seconds
Started Aug 17 06:04:41 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 207440 kb
Host smart-714e3da3-1ebf-4ebf-88fe-c23d72c57d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40482
05485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.4048205485
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3141182505
Short name T1763
Test name
Test status
Simulation time 151502103 ps
CPU time 0.91 seconds
Started Aug 17 06:04:53 PM PDT 24
Finished Aug 17 06:04:54 PM PDT 24
Peak memory 207540 kb
Host smart-b37414ce-9c76-4616-be31-3de9483e74e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31411
82505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3141182505
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3181349898
Short name T587
Test name
Test status
Simulation time 194984199 ps
CPU time 1 seconds
Started Aug 17 06:04:43 PM PDT 24
Finished Aug 17 06:04:44 PM PDT 24
Peak memory 207480 kb
Host smart-ef75ad09-bdd9-43d5-92ce-11263ad8d0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31813
49898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3181349898
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1374675088
Short name T3574
Test name
Test status
Simulation time 2754833682 ps
CPU time 80.83 seconds
Started Aug 17 06:04:42 PM PDT 24
Finished Aug 17 06:06:03 PM PDT 24
Peak memory 215964 kb
Host smart-f900f507-adca-4bde-bb67-3f885683da84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1374675088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1374675088
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2822465020
Short name T3339
Test name
Test status
Simulation time 168308954 ps
CPU time 0.88 seconds
Started Aug 17 06:04:42 PM PDT 24
Finished Aug 17 06:04:43 PM PDT 24
Peak memory 207536 kb
Host smart-66c7080a-aab1-4ac7-a5c4-c1c6680850e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28224
65020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2822465020
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3837831057
Short name T1585
Test name
Test status
Simulation time 149398555 ps
CPU time 0.92 seconds
Started Aug 17 06:04:41 PM PDT 24
Finished Aug 17 06:04:42 PM PDT 24
Peak memory 207500 kb
Host smart-383b9159-ac9c-42c3-8bb0-224d93aee18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38378
31057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3837831057
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.1787191573
Short name T1905
Test name
Test status
Simulation time 677896519 ps
CPU time 1.92 seconds
Started Aug 17 06:04:53 PM PDT 24
Finished Aug 17 06:04:55 PM PDT 24
Peak memory 207508 kb
Host smart-06f163ff-ac6e-4b9c-b0b6-1e819bfb378c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17871
91573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.1787191573
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1629865420
Short name T1230
Test name
Test status
Simulation time 2029920757 ps
CPU time 21.21 seconds
Started Aug 17 06:04:47 PM PDT 24
Finished Aug 17 06:05:09 PM PDT 24
Peak memory 216768 kb
Host smart-426032d6-88cf-4afe-b296-ce0043c659bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16298
65420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1629865420
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.560140842
Short name T2774
Test name
Test status
Simulation time 2543960446 ps
CPU time 17.7 seconds
Started Aug 17 06:04:35 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 207704 kb
Host smart-4f7dc55e-e08c-4ae5-94dc-2a5e711e589b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560140842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host_
handshake.560140842
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_tx_rx_disruption.2182117179
Short name T718
Test name
Test status
Simulation time 580302939 ps
CPU time 1.59 seconds
Started Aug 17 06:04:50 PM PDT 24
Finished Aug 17 06:04:52 PM PDT 24
Peak memory 207560 kb
Host smart-eb682deb-e387-44f4-b40f-07b7cb491814
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182117179 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.usbdev_tx_rx_disruption.2182117179
Directory /workspace/9.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/90.usbdev_endpoint_types.363742053
Short name T2883
Test name
Test status
Simulation time 142382503 ps
CPU time 0.87 seconds
Started Aug 17 06:11:24 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 207492 kb
Host smart-f1cda7db-b0e7-4451-9426-733448307c90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=363742053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.363742053
Directory /workspace/90.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/90.usbdev_tx_rx_disruption.2331791049
Short name T3162
Test name
Test status
Simulation time 611581750 ps
CPU time 1.54 seconds
Started Aug 17 06:11:21 PM PDT 24
Finished Aug 17 06:11:22 PM PDT 24
Peak memory 207580 kb
Host smart-b5b08d96-ce47-46f2-8ba7-bfb0eb7f6131
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331791049 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.usbdev_tx_rx_disruption.2331791049
Directory /workspace/90.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/91.usbdev_endpoint_types.260848788
Short name T438
Test name
Test status
Simulation time 627967172 ps
CPU time 1.57 seconds
Started Aug 17 06:11:15 PM PDT 24
Finished Aug 17 06:11:17 PM PDT 24
Peak memory 207508 kb
Host smart-4e9847dc-1253-4e1e-ab9c-4be5b781ad79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=260848788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.260848788
Directory /workspace/91.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/91.usbdev_tx_rx_disruption.3718523585
Short name T197
Test name
Test status
Simulation time 511528148 ps
CPU time 1.57 seconds
Started Aug 17 06:11:15 PM PDT 24
Finished Aug 17 06:11:16 PM PDT 24
Peak memory 207548 kb
Host smart-6fc6b78f-b263-4e60-8428-f3aad156cb0c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718523585 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.usbdev_tx_rx_disruption.3718523585
Directory /workspace/91.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/92.usbdev_endpoint_types.672667677
Short name T418
Test name
Test status
Simulation time 522851222 ps
CPU time 1.65 seconds
Started Aug 17 06:11:25 PM PDT 24
Finished Aug 17 06:11:27 PM PDT 24
Peak memory 207516 kb
Host smart-99a0c931-24b3-467f-83b4-ec85068852f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=672667677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.672667677
Directory /workspace/92.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/92.usbdev_tx_rx_disruption.4171667838
Short name T590
Test name
Test status
Simulation time 627351030 ps
CPU time 1.78 seconds
Started Aug 17 06:11:20 PM PDT 24
Finished Aug 17 06:11:22 PM PDT 24
Peak memory 207580 kb
Host smart-c5fe17ff-9b1c-45ff-8722-100f520dddc3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171667838 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.usbdev_tx_rx_disruption.4171667838
Directory /workspace/92.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/93.usbdev_endpoint_types.657786318
Short name T3048
Test name
Test status
Simulation time 301112831 ps
CPU time 1.09 seconds
Started Aug 17 06:11:22 PM PDT 24
Finished Aug 17 06:11:23 PM PDT 24
Peak memory 207512 kb
Host smart-7e3e9c28-11dd-432f-99b6-a240d018fb52
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=657786318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.657786318
Directory /workspace/93.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/93.usbdev_tx_rx_disruption.1630103215
Short name T3518
Test name
Test status
Simulation time 481170066 ps
CPU time 1.39 seconds
Started Aug 17 06:11:26 PM PDT 24
Finished Aug 17 06:11:27 PM PDT 24
Peak memory 207568 kb
Host smart-882ca330-1772-48f0-bf77-056254bc7102
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630103215 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.usbdev_tx_rx_disruption.1630103215
Directory /workspace/93.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/94.usbdev_endpoint_types.2535307239
Short name T431
Test name
Test status
Simulation time 468151479 ps
CPU time 1.34 seconds
Started Aug 17 06:11:21 PM PDT 24
Finished Aug 17 06:11:22 PM PDT 24
Peak memory 207520 kb
Host smart-36d77d4c-3c9b-420c-a1ca-3dc16b954260
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2535307239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.2535307239
Directory /workspace/94.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/94.usbdev_tx_rx_disruption.2140993299
Short name T1878
Test name
Test status
Simulation time 494243250 ps
CPU time 1.61 seconds
Started Aug 17 06:11:26 PM PDT 24
Finished Aug 17 06:11:28 PM PDT 24
Peak memory 207560 kb
Host smart-5f83e738-151b-4dc1-b38c-f6e0ebb80ea6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140993299 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.usbdev_tx_rx_disruption.2140993299
Directory /workspace/94.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/95.usbdev_endpoint_types.2396875324
Short name T484
Test name
Test status
Simulation time 233404448 ps
CPU time 1.1 seconds
Started Aug 17 06:11:13 PM PDT 24
Finished Aug 17 06:11:15 PM PDT 24
Peak memory 207460 kb
Host smart-f86ecb35-eed3-4de9-a26e-c982941783fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2396875324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.2396875324
Directory /workspace/95.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/95.usbdev_tx_rx_disruption.2159262790
Short name T2641
Test name
Test status
Simulation time 507896640 ps
CPU time 1.51 seconds
Started Aug 17 06:11:14 PM PDT 24
Finished Aug 17 06:11:16 PM PDT 24
Peak memory 207496 kb
Host smart-a9ff3342-2782-4a41-aeba-55e2d0feae9e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159262790 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.usbdev_tx_rx_disruption.2159262790
Directory /workspace/95.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/96.usbdev_endpoint_types.1026938746
Short name T485
Test name
Test status
Simulation time 336996236 ps
CPU time 1.22 seconds
Started Aug 17 06:11:22 PM PDT 24
Finished Aug 17 06:11:24 PM PDT 24
Peak memory 207520 kb
Host smart-f5f5cc49-c323-4aee-85aa-677a555d1b43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1026938746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.1026938746
Directory /workspace/96.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/96.usbdev_tx_rx_disruption.256571318
Short name T591
Test name
Test status
Simulation time 495302149 ps
CPU time 1.57 seconds
Started Aug 17 06:11:13 PM PDT 24
Finished Aug 17 06:11:14 PM PDT 24
Peak memory 207592 kb
Host smart-e447e283-e5a6-4c2b-87cc-28b601838118
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256571318 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 96.usbdev_tx_rx_disruption.256571318
Directory /workspace/96.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/97.usbdev_endpoint_types.634522734
Short name T523
Test name
Test status
Simulation time 221689646 ps
CPU time 0.94 seconds
Started Aug 17 06:11:20 PM PDT 24
Finished Aug 17 06:11:21 PM PDT 24
Peak memory 207540 kb
Host smart-cd1057db-eaee-42c7-bcdc-656c35a9dbe8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=634522734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.634522734
Directory /workspace/97.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/97.usbdev_tx_rx_disruption.3696478512
Short name T2814
Test name
Test status
Simulation time 566234505 ps
CPU time 1.84 seconds
Started Aug 17 06:11:18 PM PDT 24
Finished Aug 17 06:11:19 PM PDT 24
Peak memory 207540 kb
Host smart-b514a077-7e8e-4115-9cab-847c8bd07c13
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696478512 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.usbdev_tx_rx_disruption.3696478512
Directory /workspace/97.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/98.usbdev_endpoint_types.447729775
Short name T2381
Test name
Test status
Simulation time 466432561 ps
CPU time 1.39 seconds
Started Aug 17 06:11:22 PM PDT 24
Finished Aug 17 06:11:23 PM PDT 24
Peak memory 207516 kb
Host smart-4cc1b33c-e6e0-4a94-b598-307d16bd71a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=447729775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.447729775
Directory /workspace/98.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/98.usbdev_tx_rx_disruption.1434598112
Short name T1437
Test name
Test status
Simulation time 584837677 ps
CPU time 1.53 seconds
Started Aug 17 06:11:36 PM PDT 24
Finished Aug 17 06:11:37 PM PDT 24
Peak memory 207568 kb
Host smart-03766b79-6ff2-4c9e-bbb2-001b13d2d929
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434598112 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.usbdev_tx_rx_disruption.1434598112
Directory /workspace/98.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/99.usbdev_endpoint_types.3859921386
Short name T449
Test name
Test status
Simulation time 405603329 ps
CPU time 1.19 seconds
Started Aug 17 06:11:18 PM PDT 24
Finished Aug 17 06:11:25 PM PDT 24
Peak memory 207496 kb
Host smart-07bd684a-58e2-469e-bd71-80e26414308e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3859921386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.3859921386
Directory /workspace/99.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/99.usbdev_tx_rx_disruption.1055252124
Short name T3595
Test name
Test status
Simulation time 519843946 ps
CPU time 1.75 seconds
Started Aug 17 06:11:48 PM PDT 24
Finished Aug 17 06:11:50 PM PDT 24
Peak memory 207552 kb
Host smart-57d18940-4bc8-499c-9a68-1f5970db87e2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055252124 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.usbdev_tx_rx_disruption.1055252124
Directory /workspace/99.usbdev_tx_rx_disruption/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%