Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	172192	1			T1	4		T2	2		T3	5
all_values[1]	172192	1			T1	4		T2	2		T3	5
all_values[2]	172192	1			T1	4		T2	2		T3	5
all_values[3]	172192	1			T1	4		T2	2		T3	5
all_values[4]	172192	1			T1	4		T2	2		T3	5
all_values[5]	172192	1			T1	4		T2	2		T3	5
all_values[6]	172192	1			T1	4		T2	2		T3	5
all_values[7]	172192	1			T1	4		T2	2		T3	5
all_values[8]	172192	1			T1	4		T2	2		T3	5
all_values[9]	172192	1			T1	4		T2	2		T3	5
all_values[10]	172192	1			T1	4		T2	2		T3	5
all_values[11]	172192	1			T1	4		T2	2		T3	5
all_values[12]	172192	1			T1	4		T2	2		T3	5
all_values[13]	172192	1			T1	4		T2	2		T3	5
all_values[14]	172192	1			T1	4		T2	2		T3	5
all_values[15]	172192	1			T1	4		T2	2		T3	5
all_values[16]	172192	1			T1	4		T2	2		T3	5
all_values[17]	172192	1			T1	4		T2	2		T3	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5500334

1

T1

126

T2

64

T3

155

auto[1]

9810

1

T1

2

T3

5

T17

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4721165

1

T1

110

T2

53

T3

135

auto[1]

788979

1

T1

18

T2

11

T3

25

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	143316	1			T1	4		T2	2		T20	11
all_values[0]	auto[0]	auto[1]	25538	1			T18	3		T20	9		T81	1
all_values[0]	auto[1]	auto[0]	3237	1			T3	5		T17	5		T19	5
all_values[0]	auto[1]	auto[1]	101	1			T360	1		T361	1		T362	1
all_values[1]	auto[0]	auto[0]	167738	1			T1	2		T3	2		T17	2
all_values[1]	auto[0]	auto[1]	3058	1			T2	2		T3	3		T17	3
all_values[1]	auto[1]	auto[0]	518	1			T1	1		T36	2		T37	2
all_values[1]	auto[1]	auto[1]	878	1			T1	1		T36	12		T37	1
all_values[2]	auto[0]	auto[0]	4233	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	167677	1			T1	3		T2	1		T3	4
all_values[2]	auto[1]	auto[0]	152	1			T33	1		T55	1		T56	1
all_values[2]	auto[1]	auto[1]	130	1			T33	1		T55	1		T56	1
all_values[3]	auto[0]	auto[0]	170260	1			T1	4		T2	1		T3	5
all_values[3]	auto[0]	auto[1]	283	1			T2	1		T50	1		T57	1
all_values[3]	auto[1]	auto[0]	1590	1			T58	1484		T248	1		T249	2
all_values[3]	auto[1]	auto[1]	59	1			T58	1		T248	3		T336	1
all_values[4]	auto[0]	auto[0]	4222	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	167797	1			T1	3		T2	1		T3	4
all_values[4]	auto[1]	auto[0]	114	1			T59	1		T248	4		T250	4
all_values[4]	auto[1]	auto[1]	59	1			T59	1		T249	1		T250	2
all_values[5]	auto[0]	auto[0]	171683	1			T1	3		T2	2		T3	5
all_values[5]	auto[0]	auto[1]	340	1			T1	1		T50	1		T7	1
all_values[5]	auto[1]	auto[0]	106	1			T248	3		T250	3		T336	5
all_values[5]	auto[1]	auto[1]	63	1			T248	1		T249	2		T250	3
all_values[6]	auto[0]	auto[0]	171757	1			T1	3		T2	2		T3	5
all_values[6]	auto[0]	auto[1]	216	1			T1	1		T50	1		T8	1
all_values[6]	auto[1]	auto[0]	79	1			T249	3		T250	2		T336	4
all_values[6]	auto[1]	auto[1]	140	1			T34	1		T35	1		T60	1
all_values[7]	auto[0]	auto[0]	114995	1			T1	2		T20	2		T23	2
all_values[7]	auto[0]	auto[1]	57040	1			T1	2		T2	2		T3	5
all_values[7]	auto[1]	auto[0]	99	1			T38	1		T248	2		T249	1
all_values[7]	auto[1]	auto[1]	58	1			T38	1		T250	1		T251	2
all_values[8]	auto[0]	auto[0]	171442	1			T1	4		T2	2		T3	5
all_values[8]	auto[0]	auto[1]	61	1			T248	2		T336	1		T251	3
all_values[8]	auto[1]	auto[0]	602	1			T40	10		T42	10		T43	10
all_values[8]	auto[1]	auto[1]	87	1			T40	1		T41	1		T46	1
all_values[9]	auto[0]	auto[0]	171920	1			T1	4		T2	2		T3	5
all_values[9]	auto[0]	auto[1]	55	1			T248	2		T250	2		T336	2
all_values[9]	auto[1]	auto[0]	127	1			T52	3		T53	3		T54	3
all_values[9]	auto[1]	auto[1]	90	1			T52	2		T53	2		T54	2
all_values[10]	auto[0]	auto[0]	171650	1			T1	4		T2	2		T3	5
all_values[10]	auto[0]	auto[1]	408	1			T19	3		T22	1		T51	1
all_values[10]	auto[1]	auto[0]	79	1			T248	2		T250	4		T251	4
all_values[10]	auto[1]	auto[1]	55	1			T248	6		T250	2		T251	3
all_values[11]	auto[0]	auto[0]	171197	1			T1	4		T2	2		T3	5
all_values[11]	auto[0]	auto[1]	716	1			T21	3		T61	3		T62	3
all_values[11]	auto[1]	auto[0]	157	1			T66	1		T67	1		T68	1
all_values[11]	auto[1]	auto[1]	122	1			T66	1		T67	1		T68	1
all_values[12]	auto[0]	auto[0]	171809	1			T1	4		T2	2		T3	5
all_values[12]	auto[0]	auto[1]	195	1			T69	3		T70	3		T71	3
all_values[12]	auto[1]	auto[0]	122	1			T72	2		T73	2		T74	2
all_values[12]	auto[1]	auto[1]	66	1			T72	1		T73	1		T74	1
all_values[13]	auto[0]	auto[0]	171857	1			T1	4		T2	2		T3	5
all_values[13]	auto[0]	auto[1]	68	1			T78	1		T79	1		T80	1
all_values[13]	auto[1]	auto[0]	157	1			T75	1		T76	1		T77	1
all_values[13]	auto[1]	auto[1]	110	1			T75	1		T76	1		T77	1
all_values[14]	auto[0]	auto[0]	35387	1			T1	2		T2	1		T3	5
all_values[14]	auto[0]	auto[1]	136644	1			T1	2		T2	1		T23	1
all_values[14]	auto[1]	auto[0]	89	1			T248	3		T249	1		T250	3
all_values[14]	auto[1]	auto[1]	72	1			T248	2		T249	3		T251	3
all_values[15]	auto[0]	auto[0]	4300	1			T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	167746	1			T1	3		T2	1		T3	4
all_values[15]	auto[1]	auto[0]	88	1			T248	1		T249	1		T336	1
all_values[15]	auto[1]	auto[1]	58	1			T248	1		T249	2		T250	2
all_values[16]	auto[0]	auto[0]	171301	1			T1	4		T2	2		T3	5
all_values[16]	auto[0]	auto[1]	726	1			T21	3		T61	3		T62	3
all_values[16]	auto[1]	auto[0]	85	1			T63	4		T64	4		T65	4
all_values[16]	auto[1]	auto[1]	80	1			T63	4		T64	4		T65	4
all_values[17]	auto[0]	auto[0]	113902	1			T1	2		T4	2		T5	2
all_values[17]	auto[0]	auto[1]	58109	1			T1	2		T2	2		T3	5
all_values[17]	auto[1]	auto[0]	107	1			T47	1		T48	1		T49	1
all_values[17]	auto[1]	auto[1]	74	1			T47	1		T48	1		T49	1