Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg
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Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_crc5 3 0 3 100.00 100 1 1 0
cp_dir 2 0 2 100.00 100 1 1 2


Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_crc5_X_dir 6 0 6 100.00 100 1 1 0


Summary for Variable cp_crc5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_crc5

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_ones 4800 1 T4 9 T5 13 T36 2
leading_zero 6524 1 T2 69 T281 2 T136 1
trailing_zero 5769 1 T50 15 T91 840 T536 2



Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 111429 1 T1 1 T2 403 T3 6
auto[1] 68812 1 T1 1 T2 425 T3 4



Summary for Cross cr_crc5_X_dir

Samples crossed: cp_crc5 cp_dir
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for cr_crc5_X_dir

Bins
cp_crc5cp_dirCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_ones auto[0] 2746 1 T4 4 T5 6 T36 1
all_ones auto[1] 2054 1 T4 5 T5 7 T36 1
leading_zero auto[0] 3941 1 T2 33 T281 1 T136 1
leading_zero auto[1] 2583 1 T2 36 T281 1 T92 30
trailing_zero auto[0] 3657 1 T50 7 T91 840 T536 1
trailing_zero auto[1] 2112 1 T50 8 T536 1 T189 7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%