Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111272

1

T1

1

T2

403

T3

6

auto[1]

46780

1

T1

1

T2

425

T3

3

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	30229	1			T2	2		T17	1		T18	2
max_len_m1	858	1			T2	11		T4	2		T6	4
max_len_m2	849	1			T2	2		T36	2		T50	4
max_len_m3	858	1			T2	11		T189	2		T92	9
five	1211	1			T2	22		T36	2		T50	2
four	1219	1			T2	11		T61	2		T5	2
three	804	1			T2	16		T21	2		T92	5
one	992	1			T2	12		T104	1		T132	1
zero	12188	1			T2	249		T22	3		T127	2

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24481	1			T2	2		T18	1		T20	9
max_len	auto[1]	5748	1			T17	1		T18	1		T4	1
max_len_m1	auto[0]	595	1			T2	11		T4	1		T6	2
max_len_m1	auto[1]	263	1			T4	1		T6	2		T178	1
max_len_m2	auto[0]	584	1			T2	2		T36	1		T50	2
max_len_m2	auto[1]	265	1			T36	1		T50	2		T276	1
max_len_m3	auto[0]	587	1			T2	10		T189	1		T92	8
max_len_m3	auto[1]	271	1			T2	1		T189	1		T92	1
five	auto[0]	612	1			T2	8		T36	1		T50	1
five	auto[1]	599	1			T2	14		T36	1		T50	1
four	auto[0]	646	1			T2	4		T61	1		T5	1
four	auto[1]	573	1			T2	7		T61	1		T5	1
three	auto[0]	389	1			T2	4		T21	1		T92	1
three	auto[1]	415	1			T2	12		T21	1		T92	4
one	auto[0]	416	1			T2	4		T104	1		T132	1
one	auto[1]	576	1			T2	8		T92	12		T69	1
zero	auto[0]	547	1			T2	9		T536	1		T132	1
zero	auto[1]	11641	1			T2	240		T22	3		T127	2